x488 PIXEL SOCS083A - OCTOBER 2002 D High-Resolution, Solid State Image Sensor D D D D D D D D D D D D for B/W Video and Computer Applications 11-mm Image-Area Diagonal Compatible with 2/3" Vidicon Optics 754(H)x484(V) Active Elements in Image-Sensing Area Lateral Overflow Drain Antiblooming Electronic Exposure Control Interlace or Progressive Scan Readout Line Summing and Pixel Summing Modes Low Dark Current Dynamic Range Larger than 64 dB High Sensitivity High Blue Response Including DUV Single Phase Clocking Solid State Reliability With No Image Burn-In, Residual Imaging, Image Distortion, Image Lag, or Microphonics DUAL-IN-LINE PACKAGE (TOP VIEW) GND 1 22 GND ODB 2 21 IDB IAG 20 IAG 3 GND 4 19 GND SAG 5 18 GND SAG 6 17 GND GND 7 16 NC VOUT 8 15 SRG VDD 9 14 TRG CDB 10 13 RSG NC 11 12 NC description The Texas Instruments TC341 sensor is a high-performance frame-transfer charge-coupled device (CCD) image sensor. It is designed for use in B/W video and computer camera applications. The device is intended to replace the 2/3-inch vidicon tube in applications requiring small size, high reliability, and lower cost. The image-sensing area of the TC341 sensor is configured into 488 lines with 780 elements in each line. Twenty-six elements are provided in each line for a dark reference. The blooming protection of the sensor is based on an advanced lateral overflow drain (ALOD). The antiblooming function is activated when a suitable dc bias is applied to the antiblooming drain pin. With this type of blooming protection it is also possible to clear the image area of all charge. This is accomplished by supplying a single 10 V pulse for a minimum of 1 s to the overflow drain pin. The sensor is designed to operate in interlace as well in progressive scan modes. The interlace mode of operation can be achieved in two ways: by skipping odd or even lines in corresponding image fields or by a suitable line summing. The line summing provides higher sensitivity, because all collected charge is used. The line skipping provides somewhat higher vertical resolution, but with a penalty of lower sensitivity. The progressive scan mode sacrifices neither sensitivity nor resolution. A standard gated floating-diffusion charge detection node structure converts charge into a signal voltage. For higher accuracy and stability, this structure is reset to an on-chip automatic potential-tracking voltage reference. The reset gate has a separate external pin, which allows implementing pixel summing by skipping the detection node reset pulses. A low-noise, two-stage, source-follower amplifier buffers the output and provides high output-driving capability. The TC341 sensor is built using TI-proprietary virtual-phase technology, which provides devices with high blue response, low dark current, high photoresponse uniformity, and a single-phase clocking. The TC241 sensor is characterized for operation from -10C to 45C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2002, Texas Instruments Incorporated ! " #$ %!& % "! "! '! ! !( ! %% )*& % "!+ %! !!$* $ %! !+ $$ "!!& POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 x488 PIXEL SOCS083A - OCTOBER 2002 functional block diagram GND GND Dark Reference Pixels Input Diode ODB IDB Image Sensing Area with Blooming Protection IAG IAG GND GND SAG GND SAG GND Image Storage Area Vout NC Output Amplifier GND SRG IIIIIIIIIIIIIII IIIIIIIIIIIIIII Serial Readout Register VDD CDB NC 2 TRG RSG Charge Clearing Drain POST OFFICE BOX 655303 Transfer Gate * DALLAS, TEXAS 75265 NC x488 PIXEL SOCS083A - OCTOBER 2002 sensor topology diagram 26 Dark Reference Pixels 754 Active Pixels 484 Active Lines Dark Reference Pixels 488 Lines Four Dark Isolation Lines Image Sensing Area with Blooming Protection Image Storage Area Optical Black Pixels (OPB) 9 26 754 Active Pixels Dummy Pixels One Dummy Pixel 790 Pixels POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 x488 PIXEL SOCS083A - OCTOBER 2002 Terminal Functions TERMINAL NAME NO. CDB 10 GND 1, 4, 7, 17, 18, 19, 22 IAG 3, 20 I/O I DESCRIPTION Charge clearing drain bias Chip substrate (SUB) I Image area gate IDB 21 I Input diode bias NC 11, 12, 16 - No connection 2 I Charge overflow drain bias RSG 13 I Detection node reset gate SAG 5, 6 I Storage area gate SRG 15 I Serial register gate TRG 14 I Transfer gate VDD 9 I Amplifier drain bias VOUT 8 O Sensor output ODB detailed description The TC341 sensor consists of four basic functional blocks: the image-sensing area, the image storage area, the serial register, and the charge detection amplifier. The location of each of these blocks is identified in the functional block diagram. image sensing and storage areas Figure 1 shows a cross-section with potential-well diagrams and Figure 2 shows a top view of pixels in the image-sensing and storage areas. As light enters silicon in the image-sensing area, electrons are generated and collected in potential wells of the pixels. Applying a suitable dc bias to the antiblooming drain provides blooming protection. The amount of charge that exceeds a specified level, determined by the ODB bias, is drained away from the pixels. If it is necessary to remove all previously accumulated charge from the wells, a short positive pulse must be applied to the drain. This marks the beginning of the new integration period. After the integration cycle is completed, charge is quickly transferred into the memory where it waits for readout. The lines can be read out from the memory in a sequential order to implement progressive scan, or two lines can be summed together in the serial register to implement a pseudo-interlace scan. The true interlace scan is implemented by skipping odd or even lines, depending on the readout field, and dumping the unwanted charge into the clearing drain that is located next to the serial register. Twenty-six columns at the left edge of the image-sensing area are shielded from incident light. These pixels provide the dark reference that is used in subsequent video-processing circuits to restore the video black level. An additional four dark lines, located between the image-sensing area and the image storage area, were added for isolation. 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 x488 PIXEL SOCS083A - OCTOBER 2002 IAG Polysilicon Gate p+ Virtual Phase Gate +++++++++++++++ n--Buried Channel IIIIIIIIII IIIIIIIIII +++++++++++++++++++++++ ++++++++++++++ +++ p--Substrate Pixel Cross Section X Channel Potential for Low Clock Bias Virtual Well O Charge Transfer Charge Transfer Clocked Well Channel Potential for High Clock Bias Figure 1. Image Area and Storage Area Pixel Cross Section with Potential Diagram POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 x488 PIXEL SOCS083A - OCTOBER 2002 13.5 m IAG Antiblooming Drain Channel Stops Storage Area Pixel SAG 11.5 m Figure 2. Image Area and Storage Area Pixel Topologies 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 Image Area Pixel 11.5 m x488 PIXEL SOCS083A - OCTOBER 2002 advanced lateral overflow drain The advanced overflow drain structure is shared by two neighboring pixels in each line. Varying the dc bias of the antiblooming drain controls the blooming protection level and trades it for well capacity. Applying a pulse (approximately 10 V above the nominal level for a minimum of 1 s) to the drain removes all charge from the pixels. This feature permits a precise control of the integration time on a frame-by-frame basis. The single-pulse clearing capability also reduces smear by eliminating accumulated charge in the pixels before the start of the integration period (single-sided smear). The application of a negative 1-V pulse to the antiblooming drain during the parallel transfer is recommended. This pulse prevents creation of undesirable artifacts caused by the on-chip crosstalk between the image area gate clock lines and the antiblooming drain bias lines. serial register The serial register is used to transport charge stored in the pixels of the memory to the output amplifier. The register well capacity is designed to hold two complete lines of data. This allows implementation of pixel summing in the vertical direction (line summing) and thus also implementation of pseudo-interlace. This is accomplished by summing together lines 1+2, 3+4, ... in one field and lines 2+3, 4+5, ... in the other. The true interlace is obtained by skipping appropriate lines in each field and dumping unwanted charge into a clearing drain. The clearing drain is located next to the serial register and charge is directed to it via a special charge transfer gate (TRG). charge detection node The last element of the charge readout chain is the charge detection node. The charge detection used in this device is based on a floating diffusion (FD) concept. The n+ FD node serves as a capacitor that is first reset to a suitable reference voltage. Charge from the serial register pixel is then transferred on the node. This causes a change in the potential of FD, and a gate of the first stage source follower transistor connected to it senses this change. The output signal from the first stage is further buffered by another source follower stage to provide necessary driving capability for the off-chip circuits. The reset gate of the detection node reset transistor is connected to its own pin. This allows more flexibility in operating the sensor. By skipping the reset pulses, charge from several pixels can be summed together. This feature also allows an easy implementation of correlated double sampling (CDS) that is used to minimize the undesirable effect of reset (kTC) noise. The detection node is reset to a voltage reference that is generated internally on-chip and tracks the process induced potential variations. This improves the accuracy and stability of the device operation. special feature The sensor is provided with a charge input structure located at the upper right-hand corner of the image-sensing array. Charge input may be useful for a variety of applications, but its main purpose here is electrical testing of the sensor during manufacturing. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 x488 PIXEL SOCS083A - OCTOBER 2002 absolute maximum ratings over operating free-air temperature (unless otherwise noted) Supply voltage range, VSS: ADB, CDB, IDB (see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . SUB to SUB + 15 V Supply voltage range, VSS: ODB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SUB to SUB + 20 V Input voltage range, VI: IAG, SAG, SRG, RSG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SUB - 15 V to SUB + 15 V Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10C to 45C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -30C to 85C Operating case temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10C to 55C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to SUB (GND). recommended operating conditions MIN NOM ADB 11.5 12 12.5 CDB 11.5 12 12.5 Substrate bias (GND), Vss MAX UNIT 0 For blooming control Supply Su ly voltages, VDD ODB 5 8 V For clearing For transfer IAG SAG IAG, SRG Inp t voltages, Input oltages VI RSG High 1.5 2 2.5 Low -10.5 -10 -9.5 High 1.5 2 2.5 Low -10.5 -10 -9.5 High 1.5 2 2.5 1.5 2 2.5 Low High TRG Low IAG 8 SAG Clock frequency, fck 8 SRG 14.7 RSG 14.7 TRG Load capacitance -10 Fine tuning of ODB voltage is required to achieve an optimum antiblooming performance. Fine tuning of gate clock input voltages is required to obtain the best charge transfer performance. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MHz 8 Cout Operating free-air temperature, TA 8 V 3 pF 45 C x488 PIXEL SOCS083A - OCTOBER 2002 electrical characteristics over recommended operating ranges of supply voltage at operating free-air temperature (unless otherwise noted) MIN TYP Charge conversion factor 6 Signal-response delay time (Note 2) 6 Output resistance Output dc level 3.6 MAX UNIT V/e 10 ns 500 5.5 V Saturation voltage for progressive scan 240 mV Saturation voltage for interlace scan by line summing Amplifier noise-equivalent signal without CDS (Note 3) 480 mV 50 e Amplifier noise-equivalent signal with CDS (Note 3) Output signal dynamic range without CDS 35 e 64 dB Output signal dynamic range with CDS 67 dB Response linearity (Note 4) 1 Charge-transfer efficiency parallel register 0.9999 1 Charge-transfer efficiency serial register 0.9999 1 Supply current mA IAG SAG SRG CI Inp t capacitances Input RSG pF TRG ODB ADB SRG high SRG low P lse amplitude Pulse amplit de rejection ratio RSG high (Note 5) dB RSG low (Note 5) ODB high (Note 6) All typical values are at TA = 25C. CDS is a signal processing technique that improves performance by minimizing undesirable effects of reset noise. NOTES: 2. The signal delay time is measured from the falling edge of the reset pulse (SRG) to 90% of valid signal. 3. The noise measurement is performed at 14.0 MHz. The value shown in the table is RMS value. 4. The response linearity is measured as a deviation from the straight line of the signal transfer curve (voltage output versus light input) at the output saturation point. 5. This level affects only the reset feed through. 6. The charge clearing pulse applied to ODB during the charge readout may cause a slight feed through in the output. To avoid this problem it is recommended to apply the charge clearing pulse only during the horizontal blanking times. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 x488 PIXEL SOCS083A - OCTOBER 2002 optical characteristics, TA = 40C (unless otherwise noted) MIN Sensitivity (Note 7) No IR filter MAX 413 With IR filter VOFF TYP UNIT mV/Lx 51 Zero input offset (Note 8) 0 Blooming overload ratio (Note 9) 100 200 mV 500:1 Image area well capacity with antiblooming off 70k 80k Image area well capacity with antiblooming on 35k 40k Smear (Note 10) 00k 45k -75 Dark current (Note 11) TA = 21C TA = 21C Dark signal (Note 12) Dark-signal uniformity (Note 13) Dark-signal shading (Note 14) Spurious nonuniformity Dark (Note 15) Illuminated lens F#8 Column uniformity (Note 16) 0.1 dB nA/cm2 0.06 mV TA = 21C TA = 21C 0.03 mV 0.03 mV TA = 21C TA = 21C 3.5 mV 15 TA = 21C 0.3 Electronic-shutter capability 1/1000 % mV 1/30 sec NOTES: 7. Light source temperature is 2856K. The IR filter used is CM500 1mm thick. Integration time is 1/30 sec. 8. This is a signal pedestal measured from the output level after reset to the output level after the SRG negative transition without any light input into the sensor. 9. Blooming is the condition in which charge induced by light in one element spills over to the neighboring elements. 10. Smear is the measure of error signal introduced into the pixels by transferring them through the illuminated region into the memory. The illuminated region is 1/10 of the image area height. The value in the table is obtained for the integration time of 33.33 ms and 8 MHz vertical clock transfer frequency. 11. Dark current depends on temperature and approximately doubles every 8C. 12. Dark signal is actual device output measured in dark. 13. Dark signal uniformity is the sigma of difference of two neighboring pixels taken from all the image area pixels. 14. Dark signal shading is the difference between maximum and minimum of 5 pixel median taken anywhere in the array. 15. Spurious non-uniformity is the signal of no more than three neighboring pixels that exceeds or is less than average. 16. Column uniformity is obtain by summing all the lines in the array, finding the maximum of the difference of two neighboring columns anywhere in the array, and dividing the result by number of lines. pixel defect specifications, integration time = 1/60 sec, temperature = 40C DEVICE PART NUMBER DEVICE IN DARK DEFECT COUNT NUMBER DEVICE ILLUMINATED WS BS WS/BS AREA AREA AREA A B A B A B DEFECT COUNT NUMBER SIGNAL OUTPUT LEVEL WS AREA A B TC341-20 > 3.5 mV 0 0 0 0 0 0 > 5% 0 0 TC341-30 2.5~3.5 mV 2 5 2 5 2 2 5~7.5% 2 5 > 3.5 mV 0 0 0 0 0 0 > 7.5% 0 0 3.5~7 mV 3 7 3 7 3 7 7.5~15% 3 7 > 7 mV 0 0 0 0 0 0 > 15% 0 0 TC341-40 17. See Figure 3 for definitions of area A and area B. 10 POST OFFICE BOX 655303 TOTAL DEFECT COUNT * DALLAS, TEXAS 75265 50 mV +/- 10 mV 0 12 15 x488 PIXEL 14 Lines SOCS083A - OCTOBER 2002 B A 22 Lines 233 Lines 360 Pixels 20 Pixels 15 Pixels Figure 3. Image Sensing Area Map POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 x488 PIXEL SOCS083A - OCTOBER 2002 timing requirements Clear Integrate Transfer to Memory Readout Pulse Position Determines Exposure ODB IAG 244 Cycles SAG > 2 s 790 Pulses Line 244 790 Pulses Line 1 SRG RSG TRG Expanded Section of Parallel Transfer: 487 Pulses Even Field, 488 Pulses Odd Field Expanded Section of Serial Transfer IAG SAG SRG 35 ns 70 ns SRG TRG 140 ns RSG > 10 ns > 10 ns All pulse rise times and fall times must be longer than 10 ns. Figure 4. Interlace Timing for Line Skipping Mode 12 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 > 15 ns x488 PIXEL SOCS083A - OCTOBER 2002 timing requirements (continued) Clear Integrate Transfer to Memory Readout Pulse Position Determines Exposure ODB IAG 244 Cycles SAG > 2 s 790 Pulses Line 244 790 Pulses Line 1 SRG RSG TRG Expanded Section of Parallel Transfer: 487 Pulses Even Field, 488 Pulses Odd Field Expanded Section of Serial Transfer IAG SAG SRG 35 ns 70 ns SRG TRG 140 ns RSG > 10 ns > 10 ns > 15 ns All pulse rise times and fall times must be longer than 10 ns. Figure 5. Interlace Timing for Line Summing Mode POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 13 x488 PIXEL SOCS083A - OCTOBER 2002 timing requirements (continued) Clear Integrate Transfer to Memory Readout Pulse Position Determines Exposure ODB IAG 488 Cycles SAG > 1 s 790 Pulses Line 244 790 Pulses Line 1 SRG RSG TRG Expanded Section of Parallel Transfer: 488 Pulses Expanded Section of Serial Transfer IAG SAG SRG 35 ns 70 ns SRG TRG 140 ns RSG > 10 ns All pulse rise times and fall times must be longer than 10 ns. Figure 6. Timing for Progressive Scan Mode 14 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 > 10 ns > 15 ns x488 PIXEL SOCS083A - OCTOBER 2002 timing requirements (continued) RSG SRG Vout Reset Level Output Signal { S/H Clamp { Output signal can not be zero for zero charge. Offset level up to 100 mV can be present. Figure 7. Detail Serial Register Clock Timing for CDS Implementation POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 15 x488 PIXEL SOCS083A - OCTOBER 2002 MECHANICAL DATA The package for the TC341 consists of a ceramic base, a glass window, and a 22-lead frame. The glass window is sealed to the package by an epoxy adhesive. The package leads are configured in a dual-in-line arrangement and fit into mounting holes with 1,xx mm center-to-center spacing. 4204265 Notes 16 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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