SMSC USB3250 Revision 1.7 (02-11-13)
PRODUCT PREVIEW
Data Brief
PRODUCT FEATURES
USB3250
Hi-Speed USB Device Transceiver
with UTMI Interface
USB-IF "Hi-Speed" certified to USB 2.0 electrical
specification
Interface compliant with the UTMI specification
(60MHz 8-bit unidirectional interface or 30MHz 16-bit
bidirectional interface)
Supports 480Mbps High Speed (HS) and 12Mbps
Full Speed (FS) serial data transmission rates
Integrated 45Ω and 1.5kΩ termination resistors
reduce external component count
Internal short circuit protection of DP and DM lines
On-chip oscillator operates with low cost 12MHz
crystal
Robust and low power digital clock and data recovery
circuit
SYNC and EOP generation on transmit packets and
detection on receive packets
NRZI encoding and decoding
Bit stuffing and unstuffing with error detection
Supports the USB suspend state, HS detection, HS
Chirp, Reset and Resume
Support for all test modes defined in the USB 2.0
specification
Draws 72mA (185mW) maximum current
consumption in HS mode - ideal for bus powered
functions
On-die decoupling capacitance and isolation for
immunity to digital switching noise
Available in a 56-pin QFN package
Full industrial operating temperature range from
-40oC to +85oC (ambient)
Applications
The Universal Serial Bus (USB) is the preferred
interface to connect Hi-Speed PC peripherals.
Digital Still and Video Cameras
MP3 Players
External Hard Drives
Scanners
Entertainment Devices
Printers
Test and Measurement Systems
POS Terminals
Set Top Boxes
Ordering Information:
USB3250-ABZJ for 56 pin, QFN lead-free RoHS compliant package, 8 x 8 x 0.85mm
This product meets the halogen maximum concentration values per IEC61249-2-21
For RoHS compliance and environmental information, please visit www.smsc.com/rohs
Hi-Speed USB Device Transceiver with UTMI Interface
Revision 1.7 (02-11-13) 2 SMSC USB3250
PRODUCT PREVIEW
Copyright © 2013 SMSC or its subsidiaries. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for
construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC
reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications
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Hi-Speed USB Device Transceiver with UTMI Interface
SMSC USB3250 3 Revision 1.7 (02-11-13)
PRODUCT PREVIEW
General Description
The USB3250 provides the Physical Layer (PHY) interface to a USB 2.0 Device Controller. The IC is
available in a 56 pin QFN.
The USB3250 is a USB 2.0 physical layer transceiver (PHY) integrated circuit. SMSC's proprietary
technology results in low power dissipation, which is ideal for building a bus powered USB 2.0
peripheral. The PHY can be configured for either an 8-bit unidirectional or a 16-bit bidirectional parallel
interface, which complies with the USB Transceiver Macrocell Interface (UTMI) specification. It
supports 480Mbps transfer rate, while remaining backward compatible with USB 1.1 legacy protocol
at 12Mbps.
All required termination for the USB 2.0 Transceiver is internal. Internal 5.25V short circuit protection
of DP and DM lines is provided for USB compliance.
While transmitting data, the PHY serializes data and generates SYNC and EOP fields. It also performs
needed bit stuffing and NRZI encoding. Likewise, while receiving data, the PHY de-serializes incoming
data, stripping SYNC and EOP fields and performs bit un-stuffing and NRZI decoding.
Hi-Speed USB Device Transceiver with UTMI Interface
Revision 1.7 (02-11-13) 4 SMSC USB3250
PRODUCT PREVIEW
Block Diagram
Figure 1 USB3250 Functional Block Diagram
VALIDH
PWR
CONTROL
FS
SE+
RX
UTMI Interface
TX State
Machine
Parallel to
Serial
Conversion
Bit Stuff
NRZ
Encode
TX
LOGIC
Clock
Recovery Unit
Clock
and
Data
Recovery
Elasticity
Buffer
VP
VM
BIASING
Bandgap Voltage Reference
Current Reference
RBIAS
VDD3.3
VDD1.8
PLL and
XTAL OSC
System
Clocking
FS
RX
FS
SE-
HS
RX
HS
SQ
RX State
Machine
Serial to
Parallel
Conversion
Bit Unstuff
NRZI
Decode
RX
LOGIC
DM
TX
1.5kΩ
FS
TX
HS
TX
HS_DATA
HS_CS_ENABLE
HS_DRIVE_ENABLE
OEB
VMO
VPO
RPU_EN
MUX
DP
RXVALID
RXACTIVE
RXERROR
TXREADY
RESET
SUSPENDN
XCVRSELECT
TERMSELECT
OPMODE[1:0]
LINESTATE[1:0]
CLKOUT
TXVALID
DATABUS16_8
DATA[15:0] *
XI
XO
Hi-Speed USB Device Transceiver with UTMI Interface
SMSC USB3250 5 Revision 1.7 (02-11-13)
PRODUCT PREVIEW
Pin Configuration
Figure 2 56-Pin USB3250 Pin Configuration (Top View)
TERMSELECT
LINESTATE[1]
LINESTATE[0]
VSS
DATA[6]
DATA[7]
DATA[8]
DATA[9]
DATA[10]
DATA[11]
DATA[12]
VSSA
DM
DP
VDDA3.3
VSSA
RBIAS
VDDA3.3
VSSA
XI
XO
VDDA1.8
SUSPENDN
VSS
VDD3.3
XCVRSELECT
OPMODE[1]
OPMODE[0]
VDD1.8
VDD1.8
RESET
DATA[15]
DATA[14]
DATA[13]
VDD3.3
DATA[5]
DATA[2]
DATA[3]
DATA[4]
DATA[1]
USB 2.0
USB3250
PHY IC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
42
41
29
30
31
32
34
35
36
37
38
39
40
33
15
16
17
18
19
20
21
22
23
24
25
26
27
28
48
47
46
45
44
43
56
55
54
53
52
51
50
49
VDD1.8
VSSA
VSS
VSS
DATABUS16_8
VDD1.8
RXERROR
TXREADY
RXACTIVE
CLKOUT
VSS
VALIDH
RXVALID
TXVALID
DATA[0]
VDD3.3
Hi-Speed USB Device Transceiver with UTMI Interface
Revision 1.7 (02-11-13) 6 SMSC USB3250
PRODUCT PREVIEW
Pin Description Tables
Table 1 System Interface Pins
NAME DIRECTION
ACTIVE
LEVEL DESCRIPTION
RESET Input High Reset. Reset all state machines. After coming out of reset, must
wait 5 rising edges of clock before asserting TXValid for transmit.
Assertion of Reset: May be asynchronous to CLKOUT.
De-assertion of Reset: Must be synchronous to CLKOUT unless
RESET is asserted longer than two periods of CLKOUT.
XCVRSELECT Input N/A Transceiver Select. This signal selects between the FS and HS
transceivers:
0: HS transceiver enabled
1: FS transceiver enabled.
TERMSELECT Input N/A Termination Select. This signal selects between the FS and HS
terminations:
0: HS termination enabled
1: FS termination enabled
SUSPENDN Input Low Suspend. Places the transceiver in a mode that draws minimal
power from supplies. Shuts down all blocks not necessary for
Suspend/Resume operation. While suspended, TERMSELECT
must always be in FS mode to ensure that the 1.5k Ω pull-up on
DP remains powered.
0: Transceiver circuitry drawing suspend current
1: Transceiver circuitry drawing normal current
CLKOUT Output Rising Edge System Clock. This output is used for clocking receive and
transmit parallel data at 60MHz (8-bit mode) or 30MHz (16-bit
mode). When in 8-bit mode, this specification refers to CLKOUT
as CLK60. When in 16-bit mode, CLKOUT is referred to as
CLK30.
OPMODE[1:0] Input N/A Operational Mode. These signals select between the various
operational modes:
[1] [0] Description
0 0 0: Normal Operation
0 1 1: Non-driving (all terminations removed)
1 0 2: Disable bit stuffing and NRZI encoding
1 1 3: Reserved
LINESTATE[1:0] Output N/A Line State. These signals reflect the current state of the USB
data bus in FS mode, with [0] reflecting the state of DP and [1]
reflecting the state of DM. When the device is suspended or
resuming from a suspended state, the signals are combinatorial.
Otherwise, the signals are synchronized to CLKOUT.
[1] [0] Description
0 0 0: SE0
0 1 1: J State
1 0 2: K State
1 1 3: SE1
DATABUS16_8 Input N/A Databus Select. Selects between 8-bit and 16-bit data transfers.
0: 8-bit data path enabled. VALIDH is undefined. CLKOUT =
60MHz.
1: 16-bit data path enabled. CLKOUT = 30MHz.
Hi-Speed USB Device Transceiver with UTMI Interface
SMSC USB3250 7 Revision 1.7 (02-11-13)
PRODUCT PREVIEW
Table 2 Data Interface Pins
NAME DIRECTION
ACTIVE
LEVEL DESCRIPTION
DATA[15:0] Bidir N/A DATA BUS. 16-BIT BIDIRECTIONAL MODE.
TXVALID RXVALID VALIDH DATA[15:0]
0 0 X Not used
0 1 0 DATA[7:0] output is valid
for receive
VALIDH is an output
0 1 1 DATA[15:0] output is
valid for receive
VALIDH is an output
1 X 0 DATA[7:0] input is valid
for transmit
VALIDH is an input
1 X 1 DATA[15:0] input is valid
for transmit
VALIDH is an input
DATA BUS. 8-BIT UNIDIRECTIONAL MODE.
TXVALID RXVALID DATA[15:0]
00Not used
0 1 DATA[15:8] output is valid for receive
1 X DATA[7:0] input is valid for transmit
TXVALID Input High Transmit Valid. Indicates that the TXDATA bus is valid for
transmit. The assertion of TXVALID initiates the transmission of
SYNC on the USB bus. The negation of TXVALID initiates EOP
on the USB.
Control inputs (OPMODE[1:0], TERMSELECT,XCVRSELECT)
must not be changed on the de-assertion or assertion of TXVALID.
The PHY must be in a quiescent state when these inputs are
changed.
TXREADY Output High Transmit Data Ready. If TXVALID is asserted, the SIE must
always have data available for clocking into the TX Holding
Register on the rising edge of CLKOUT. TXREADY is an
acknowledgement to the SIE that the transceiver has clocked the
data from the bus and is ready for the next transfer on the bus. If
TXVALID is negated, TXREADY can be ignored by the SIE.
VALIDH Bidir N/A Transmit/Receive High Data Bit Valid (used in 16-bit mode
only). When TXVALID = 1, the 16-bit data bus direction is
changed to inputs, and VALIDH is an input. If VALIDH is asserted,
DATA[15:0] is valid for transmission. If deasserted, only DATA[7:0]
is valid for transmission. The DATA bus is driven by the SIE.
When TXVALID = 0 and RXVALID = 1, the 16-bit data bus
direction is changed to outputs, and VALIDH is an output. If
VALIDH is asserted, the DATA[15:0] outputs are valid for receive.
If deasserted, only DATA[7:0] is valid for receive. The DATA bus
is read by the SIE.
RXVALID Output High Receive Data Valid. Indicates that the RXDATA bus has received
valid data. The Receive Data Holding Register is full and ready to
be unloaded. The SIE is expected to latch the RXDATA bus on the
rising edge of CLKOUT.
Hi-Speed USB Device Transceiver with UTMI Interface
Revision 1.7 (02-11-13) 8 SMSC USB3250
PRODUCT PREVIEW
Note 2.1 A Ferrite Bead (with DC resistance <.5 Ohms) is recommended for filtering between both
the VDD3.3 and VDDA3.3 supplies and the VDD1.8 and VDDA1.8 Supplies.
Note 2.2 All VSS and VSSA are bonded to the exposed pad under the IC in the package. The
exposed pad must be connected to solid GND plane on printed circuit board.
RXACTIVE Output High Receive Active. Indicates that the receive state machine has
detected Start of Packet and is active.
RXERROR Output High Receive Error. 0: Indicates no error. 1: Indicates a receive error
has been detected. This output is clocked with the same timing as
the RXDATA lines and can occur at anytime during a transfer.
Table 3 USB I/O Pins
NAME DIRECTION
ACTIVE
LEVEL DESCRIPTION
DP I/O N/A USB Positive Data Pin.
DM I/O N/A USB Negative Data Pin.
Table 4 Biasing and Clock Oscillator Pins
NAME DIRECTION
ACTIVE
LEVEL DESCRIPTION
RBIAS Input N/A External 1% bias resistor. Requires a 12KΩ resistor to ground.
Used for setting HS transmit current level and on-chip termination
impedance.
XI/XO Input N/A External crystal. 12MHz crystal connected from XI to XO.
Table 5 Power and Ground Pins
NAME DIRECTION
ACTIVE
LEVEL DESCRIPTION
VDD3.3 N/A N/A 3.3V Digital Supply. Powers digital pads. See Note 2.1
VDD1.8 N/A N/A 1.8V Digital Supply. Powers digital core.
VSS N/A N/A Digital Ground. See Note 2.2
VDDA3.3 N/A N/A 3.3V Analog Supply. Powers analog I/O and 3.3V analog
circuitry.
VDDA1.8 N/A N/A 1.8V Analog Supply. Powers 1.8V analog circuitry. See Note 2.1
VSSA N/A N/A Analog Ground. See Note 2.2
Table 2 Data Interface Pins (continued)
NAME DIRECTION
ACTIVE
LEVEL DESCRIPTION
Hi-Speed USB Device Transceiver with UTMI Interface
SMSC USB3250 9 Revision 1.7 (02-11-13)
PRODUCT PREVIEW
Application Diagram
Figure 3 Application Diagram for 56-pin QFN Package
UTMI
USB
POWER
TXVALID
TXREADY
RXACTIVE
RXVALID
RXERROR
VALIDH
DATABUS16_8
XCVRSELECT
TERMSELECT
SUSPENDN
RESET
OPMODE 0
OPMODE 1
LINESTATE 0
LINESTATE 1
CLKOUT
DATA 0
DATA 1
DATA 2
DATA 3
DATA 4
DATA 5
DATA 6
DATA 7
DATA 8
DATA 9
DATA 10
DATA 11
DATA 12
DATA 13
DATA 14
DATA 15
XI
XO
DP
DM
VDDA1.8
VDD1.8
VDD1.8
VDD1.8
VDD1.8
VDDA3.3
VDDA3.3
VDD3.3
VDD3.3
VDD3.3
VSS
VSS
VSS
VSS
VSS
VSSA
VSSA
VSSA
VSSA
USB-B
GND
VDD3.3
1ΜΩ
12MHz
Crystal
C LOAD
C LOAD
44
42
41
40
39
37
36
35
34
32
31
30
29
27
26
25
10
11
12
16
23
38
53
4
7
15
28
43
45
51
50
46
52
47
54
17
18
13
24
20
19
22
21
49
3
2
14
33
48
55
56
1
5
8
9
RBIAS 6
12KΩ
VDD1.8
Voltage
Regulator
VDD3.3
10uF
1uF 1uF
10uF
VDD1.8
Ferrite Bead
Ferrite Bead
10uF
SMSC USB3250 10 Revision 1.7 (02-11-13)
PRODUCT PREVIEW
Hi-Speed USB Device Transceiver with UTMI Interface
Package Outline
A INITIAL RELEASE 2/07/04 S.K.ILIEV
DECIMAL
X.X
X.XX
X.XXX
MATERIAL
FINISH
STD COMPLIANCE
THIRD ANGLE PROJECTION
PR INT W ITH "SC ALE TO FIT"
DO NOT SCALE DRAWING
APPROVED
ANGULAR
UNLES S OTHER W ISE SPECIFIED
DIMENSIONS ARE IN MILLIMETERS
AN D TO LERAN CES ARE:
DIM AN D T O L P E R A SM E Y14.5M - 1994
DRAW N
CHECKED
NAME
SCALE
80 ARKAY DRIVE
H A U P P A U G E, N Y 11788
USA
DWG NUMBER
TITLE
DATE
SHEET
REV
REVISION HISTORY
DESCRIPTIONREVISION RELEASED BYDATE
S.K.ILIEV
S.K.ILIEV
S.K.ILIEV
±1°
-
-
±0.025
±0.05
±0.1
2/07 /04 1:1
2/06/04
2/07/04 C
JEDEC: MO -220 1 O F 1
56 TERMINAL QFN, 8x8mm BODY, 0.5mm PITCH
PACKAGE OUTLINE
MO-56-QFN-8x8
SIDE VIEW
3-D VIEWS
TOP VIEW
3
2
BOTTOM VIEW
NOTES:
1. ALL DIM ENSIONS ARE IN MIL LIM ETER.
2. POSITION TOLERANCE OF EACH TERMINAL AND EXPOSED PAD IS ± 0.05mm AT MAXIMUM MATERIAL
CONDITION. DIMENSIONS "b" APPLIES TO PLATED TERMINALS AND IT IS MEASURED BETWEEN 0.15 AND
0.30 m m FRO M TH E TERM INA L TIP.
3. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED WITHIN THE AREA INDICATED.
E2EE1
D
D1
TERMINAL #1
IDENTIFIER AREA
(D1/2 X E1/2)
56X b
56X L
TERMINAL #1
IDENTIFIER AREA
(D/2 X E/2)
D2
e
EXPOSED PAD
3
A1
A2
A
4X 45°X0.6 MAX (OPTIONAL)
2
D2 / E2 VARIATIONS
CATALOG PART
B REM O VE "PRE LIMINARY" NOTE 10/7/04 S.K .ILIEV
CL(M A X) FR OM 0.55 TO 0.50. ADDE D D2/E2 VARIATIONS TABLE 7/2/05 S.K.ILIEV
