LNK408LG - Power Integrations

LNK403-410/413-420

LinkSwitch-PH LED Driver IC Family

www.power.com June 2015

Single-Stage PFC, Primary-Side Constant Current Control

and TRIAC Dimming/Non-Dimming Options

This Product is Covered by Patents and/or Pending Patent Applications.

This product is not recommended for new designs.

Output Power Table1,2

Product5

RV = 2 MWRV = 4 MW

85-132 VAC 85-308 VAC

Minimum

Output

Power3

Maximum

Output

Power4

Minimum

Output

Power3

Maximum

Output

Power4

LNK403/413E/L 2.5 W 4.5 W 6.5 W 12 W

LNK404/414E/L 2.5 W 5.5 W 6.5 W 15 W

LNK405/415E/L 3.8 W 7.0 W 8.5 W 18 W

LNK406/416E/L 4.5 W 8.0 W 10 W 22 W

LNK407/417E/L 5.5 W 10 W 12 W 25 W

LNK408/418E/L 6.8 W 13.5 W 16 W 35 W

LNK409/419E/L 8.0 W 20 W 18 W 50 W

LNK410/420E/L 18 W 31 W 40 W 78 W

Table 1. Output Power Table.

Notes:

1. Continuous power in an open frame with adequate heat sinking at device local

ambient of 70 °C.

2. Power level calculated on typical LED string voltage with efﬁciency >80%.

3. Minimum output power with CBP = 10 mF.

4. Maximum output power with CBP = 100 mF. LNK4x3EG CBP = 10 mF.

5. Package: eSIP-7C, eSIP-7F.

Product Highlights

Dramatically Simpliﬁes Off-line LED Drivers

• Single-stage combination of power factor correction and

accurate constant-current (CC) output

• Enables very long lifetime designs (no electrolytic capacitors)

• Eliminates optocoupler and all secondary current control

circuitry

• Eliminates control loop compensation circuitry

• Simple primary-side PWM dimming interface

• Universal input voltage range

• LNK403-410 optimized for ﬂicker-free TRIAC dimming

EcoSmart™ – Energy Efﬁcient

• Single-stage PFC combined with output CC control

• Greatly increases efﬁciency, >90% achievable

• Reduces component count

• No current sense resistors

• Low standby power remote ON/OFF feature

(<50 mW at 230 VAC)

Accurate and Consistent Performance

• Compensates for transformer inductance variations

• Compensates for line input voltage variation

• Frequency jittering greatly reduces EMI ﬁlter size and cost

Advanced Protection and Safety Features

• Auto-restart for short-circuit protection

• Open circuit fault detection mode

• Automatic thermal shutdown restart with hysteresis

• Meets high voltage creepage requirement between DRAIN and

all other signal pins both on PCB and at package

Green Package

• Halogen free and ROHS compliant package

Applications

• Off-line LED driver

Description

The LinkSwitch™-PH dramatically simpliﬁes implementation of

LED drivers requiring long lifetime, high efﬁciency, PF >0.9, and

TRIAC dimming capability (LNK403-410). The single-stage

combined power factor and constant-current controller eliminates

a switching stage and the electrolytic bulk capacitor. The

advanced primary-side control used by the LinkSwitch-PH device

provides accurate constant current control while eliminating the

need for an optocoupler and current sensing circuits.

LinkSwitch-PH incorporates a 725 V power FET, a continuous-

mode PWM controller, a high-voltage switched current source for

self biasing, frequency jittering, protection circuitry including

cycle-by-cycle current limit and hysteretic thermal shutdown.

Figure 2. Package Options.

eSIP-7F (L Package)

eSIP-7C (E Package)

Figure 1. Typical Application Schematic.

PI-6543-082211

LinkSwitch-PH

FBR

CONTROL

Rev. G 06/15

LNK403-410/413-420

www.power.com

Figure 4. Pin Conﬁguration.

Pin Functional Description

DRAIN (D) Pin:

This pin is the power FET drain connection. It also provides

internal operating current for both start-up and steady-state

operation.

SOURCE (S) Pin:

This pin is the power FET source connection. It is also the

ground reference for the BYPASS, FEEDBACK, REFERENCE and

VOLTAGE MONITOR pins.

BYPASS (BP) Pin:

This is the connection point for an external bypass capacitor for

the internally generated 5.9 V supply. This pin also provides

output power selection through choice of the BYPASS pin

capacitor value.

FEEDBACK (FB) Pin:

The FEEDBACK pin is used for output voltage feedback. The

current into the FEEDBACK pin is directly proportional to the

output voltage. The FEEDBACK pin also includes circuitry to

protect against open load and overload output conditions.

REFERENCE (R) Pin:

This pin is connected to an external precision resistor and is

used to conﬁgure for dimming (LNK403-410) and non-TRIAC

dimming (LNK413-420) modes of operation.

VOLTAGE MONITOR (V) Pin:

This pin interfaces with an external input line peak detector,

consisting of a rectiﬁer, ﬁlter capacitor and resistors. The

applied current is used to control stop logic for line under-

voltage (UV), overvoltage (OV), provide feed-forward to control

the output current and the remote ON/OFF function.

PI-5431-102610

ILIM

DRAIN (D)

SOURCE (S)

BYPASS (BP)

VOLTAGE

MONITOR (V)

FEEDBACK (FB)

REFERENCE (R)

ILIM

VSENSE

5.9 V

5.0 V

BYPASS PIN

UNDERVOLTAGE

FAULT

PRESENT

Gate

Driver

SenseFet

OCP

CURRENT LIMIT

COMPARATOR

1 V

6.4 V

FBOFF

IFB

DCMAX

Comparator

5.9 V

REGULATOR

SOFT-START

TIMER

JITTER

CLOCK

OSCILLATOR

AUTO-RESTART

COUNTER

BYPASS

CAPACITOR

SELECT

FEEDBACK

SENSE

PFC/CC

CONTROL

LINE

SENSE

HYSTERETIC

THERMAL

SHUTDOWN

3-VT

VBG

UV/OV

REFERENCE

BLOCK

LEB

VBG

STOP

LOGIC

PI-5432-082411

Exposed Pad

(backside) Internally

Connected to

SOURCE Pin (see

eSIP-7C Package

Drawing)

1 R

2 V

3 FB

4 BP

5 S

7 D

E Package (eSIP-7C)

(Top View)

Lead Bend Outward

from Drawing

(Refer to eSIP-7F Package

Outline Drawing)

Exposed Pad

(Backside) Internally

Connected to

SOURCE Pin

L Package (eSIP-7F)

Figure 3. Functional Block Diagram.

Rev. G 06/15

LNK403-410/413-420

www.power.com

Functional Description

A LinkSwitch-PH device monolithically integrates a controller and

high-voltage power FET into one package. The controller

implements both high power factor and a constant current

output in a single stage. The LinkSwitch-PH controller consists

of an oscillator, feedback (sense and logic) circuit, 5.9 V regulator,

hysteretic over-temperature protection, frequency jittering,

cycle-by-cycle current limit, auto-restart, inductance correction,

power factor and constant current control.

FEEDBACK Pin Current Control Characteristics

The ﬁgure shown below illustrates the operating boundaries of

the FEEDBACK pin current. Above IFB(SKIP) switching is disabled

and below IFB(AR) the device enters into auto-restart.

Figure 5. FEEDBACK Pin Current Characteristic.

The FEEDBACK pin current is also used to clamp the maximum

duty cycle to limit the available output power for overload and

open-loop conditions. This duty cycle reduction characteristic

also promotes a monotonic output current start-up characteristic

to prevent over-shoot.

REFERENCE Pin

The REFERENCE pin is tied to ground (SOURCE) via an external

resistor. The value selected sets the internal references,

determining the operating mode for dimming (LNK403-410) and

non-dimming (LNK413-420) operation and the line undervoltage

and overvoltage thresholds of the VOLTAGE MONITOR pin. For

non-dimming or PWM dimming applications with LNK413-420,

the external resistor should be a 24.9 kW ±1%, for high-line and

universal input voltage designs, and 49.9 kW ±1% for low-line

input voltage designs. For phase angle AC dimming with

LNK403-410, the external resistor should be a 49.9 kW ±1%.

One percent resistors are recommended as the resistor

tolerance directly affects the output tolerance. Other resistor

values should not be used.

BYPASS Pin Capacitor Power Gain Selection

LinkSwitch-PH devices have the capability to tailor the internal

gain to either full or a reduced output power setting. This allows

selection of a larger device to minimize dissipation for both

thermal and efﬁciency reasons. The power gain is selected with

the value of the BYPASS pin capacitor. The full power setting is

selected with a 100 mF capacitor and the reduced power setting

(for higher efﬁciency) is selected with a 10 mF capacitor. The

BYPASS pin capacitor sets both the internal power gain as well

as the over-current protection (OCP) threshold. Unlike the

larger devices, the LNK4x3 power gain is not programmable.

Use a 10 mF capacitor for the LNK4x3.

Switching Frequency

The switching frequency is 66 kHz. To further reduce the EMI

level, the switching frequency is jittered (frequency modulated)

by approximately ±1 kHz.

Soft-Start

The controller includes a soft-start timing feature which inhibits

the auto-restart protection feature for the soft-start period (tSOFT)

to distinguish start-up into a fault (short-circuit) from a large

output capacitor. At start-up the LinkSwitch-PH clamps the

maximum duty cycle to reduce the output power. The total

soft-start period is tSOFT.

Remote ON/OFF and EcoSmart

The VOLTAGE MONITOR pin has a 1 V threshold comparator

connected at its input. This voltage threshold is used for

remote ON/OFF control. When a signal is received at the

VOLTAGE MONITOR pin to disable the output (VOLTAGE

MONITOR pin tied to ground through an optocoupler photo-

transistor) the LinkSwitch-PH will complete its current switching

cycle before the internal power FET is forced off.

The remote ON/OFF feature can also be used as an eco-mode

or power switch to turn off the LinkSwitch-PH and keep it in a

very low power consumption state for indeﬁnite long periods.

When the LinkSwitch-PH is remotely turned on after entering

this mode, it will initiate a normal start-up sequence with

soft-start the next time the BYPASS pin reaches 5.9 V. In the

worst case, the delay from remote on to start-up can be equal

to the full discharge/charge cycle time of the BYPASS pin. This

reduced consumption remote off mode can eliminate expensive

and unreliable in-line mechanical switches.

IFB(AR)

IFB(DCMAXR)

DC10 DCMAX

IFB(SKIP)

IFB

PI-5433-060410

Skip-Cycle

CC Control

Region

Soft-Start and

CC Fold-Back

Region

Auto-Restart

Maximum Duty Cycle

Rev. G 06/15

LNK403-410/413-420

www.power.com

Figure 6. Remote ON/OFF VOLTAGE MONITOR pin Control

5.9 V Regulator/Shunt Voltage Clamp

The internal 5.9 V regulator charges the bypass capacitor

connected to the BYPASS pin to 5.9 V by drawing a current

from the voltage on the DRAIN pin whenever the power FET is

off. The BYPASS pin is the internal supply voltage node. When

the power FET is on, the device operates from the energy

stored in the bypass capacitor. Extremely low power

consumption of the internal circuitry allows LinkSwitch-PH

to operate continuously from current it takes from the DRAIN

pin. A bypass capacitor value of 10 or 100 mF is sufﬁcient for

both high frequency decoupling and energy storage. In

addition, there is a 6.4 V shunt regulator clamping the BYPASS

pin at 6.4 V when current is provided to the BYPASS pin

through an external resistor. This facilitates powering of

LinkSwitch-PH externally through a bias winding to increase

operating efﬁciency. It is recommended that the BYPASS pin is

supplied current from the bias winding for normal operation.

Auto-Restart

In the event of an open-loop fault (open FEEDBACK pin resistor

or broken path to feedback winding), output short-circuits or an

overload condition the controller enters into the auto-restart

mode. The controller annunciates both short-circuit and

open-loop conditions once the FEEDBACK pin current falls

below the IFB(AR) threshold after the soft-start period. To

minimize the power dissipation under this fault condition the

shutdown/auto-restart circuit turns the power supply on (same

as the soft-start period) and off at an auto-restart duty cycle of

typically DCAR for as long as the fault condition persists. If the

fault is removed during the auto-restart off-time, the power

supply will remain in auto-restart until the full off-time count is

completed. Special consideration must be made to appropriately

size the output capacitor to ensure that after the soft-start

period (tSOFT) the FEEDBACK pin current is above the IFB(AR)

threshold to ensure successful power-supply start-up.

After the soft-start time period, auto-restart is activated only

when the FEEDBACK pin current falls below IFB(AR).

Over-Current Protection

The current limit circuit senses the current in the power FET.

When this current exceeds the internal threshold (ILIMIT), the power

FET is turned off for the remainder of that cycle. A leading edge

blanking circuit inhibits the current limit comparator for a short

time (tLEB) after the power FET is turned on. This leading edge

blanking time has been set so that current spikes caused by

capacitance and rectiﬁer reverse recovery will not cause

premature termination of the power FET conduction.

Line Under/Overvoltage Protection

This device includes both line under- and overvoltage detection

to limit the minimum start-up and maximum operating voltage

detected through the VOLTAGE MONITOR pin. An external peak

detector consisting of a diode and capacitor are required to

provide input line peak voltage to the VOLTAGE MONITOR pin

through a resistor. At power up, IUV+ keeps the LinkSwitch-PH

off until the input line voltage reaches the undervoltage threshold.

At power down, IUV- prevents restart attempts after the output

goes out of regulation.

The same resistor used for UV also sets line overvoltage (OV)

shutdown threshold which, once exceeded, forces the

LinkSwitch-PH to stop switching (after completion of the current

switching cycle). Once the line voltage returns to normal, the

device resumes normal operation. A small amount of hysteresis

is provided on the OV threshold to prevent noise triggering.

When the power FET is off, the rectiﬁed DC high voltage surge

capability is increased to the voltage rating of the power FET

(725 V), due to the absence of the reﬂected voltage and leakage

spikes on the drain.

Hysteretic Thermal Shutdown

The thermal shutdown circuitry senses the controller die

temperature. The threshold is set at 142 °C typical with a 75 °C

hysteresis. When the die temperature rises above this threshold

(142 °C) the power FET is disabled and remains disabled until

the die temperature falls by 75 °C, at which point the power FET

is re-enabled.

Safe Operating Area (SOA) Protection

The device also features a safe operating area (SOA) protection

mode which disables FET switching for 40 cycles in the event

the peak switch current reaches the ILIMIT threshold and the

switch on-time is less than tON(SOA). This protection mode protects

the device under short-circuited LED conditions and at start-up

during the soft-start period when auto-restart protection is inhibited.

The SOA protection mode remains active in normal operation.

PI-5435-052510

R FB

CONTROL

Rev. G 06/15

LNK403-410/413-420

www.power.com

Application Example

14 W TRIAC Dimmable High Power Factor LED Driver

Design Example

The circuit schematic in Figure 7 shows a TRIAC dimmable high

power-factor LED driver based on LNK406EG from the

LinkSwitch-PH family of devices. It was optimized to drive an

LED string at a voltage of 28 V with a constant current of 0.5 A

(±5%) ideal for PAR lamp retro-ﬁt applications. The design

operates over a universal input voltage range of 90 VAC to

265 VAC but provides the speciﬁed output current tolerance

over a line voltage range of 90 VAC to 132 VAC (this is conﬁgurable

for high-line only applications by simple component value changes).

The key goals of this design were compatibility with standard

leading edge TRIAC AC dimmers, very wide dimming range

(1000:1, 500 mA:0.5 mA), high efﬁciency (>85%) and high power

factor (>0.9). The design is fully protected from faults such as

no-load, overload and output short-circuit conditions and over

temperature.

Circuit Description

The LinkSwitch-PH device (U1) integrates the power FET,

controller and start-up functions into a single package reducing

the component count versus typical implementations. Conﬁgured

as part of an isolated continuous conduction mode ﬂyback

converter, U1 provides high power factor via its internal control

algorithm together with the small input capacitance of the

design. Continuous conduction mode operation results in

reduced primary peak and RMS current. This both reduces

EMI noise, allowing simpler, smaller EMI ﬁltering components and

improves efﬁciency. Output current regulation is maintained

without the need for secondary-side sensing which eliminates

current sense resistors and improves efﬁciency.

Input Stage

Fuse F1 provides protection from component failures while RV1

provides a clamp during differential line surges, keeping the

peak drain voltage of U1 below the 725 V rating of the internal

power FET. Bridge rectiﬁer BR1 rectiﬁes the AC line voltage.

EMI ﬁltering is provided by L1-L3, C1, R16 and R17 together with

the safety rated Y class capacitor (C7) that bridges the safety

isolation barrier between primary and secondary. Resistor R16

and R17 act to damp any resonances formed between L1, L2,

C1 and the AC line impedance. A small bulk capacitor (C2) is

required to provide a low impedance source for the primary

switching current. The maximum value of C1 and C2 is limited in

order to maintain a power factor of greater than 0.9.

LinkSwitch-PH Primary

To provide peak line voltage information to U1 the incoming

rectiﬁed AC peak charges C3 via D2. This is then fed into the

VOLTAGE MONITOR pin of U1 as a current via R2 and R3. This

sensed current is also used by the device to set the line input

overvoltage and undervoltage protection thresholds. Resistor

R1 provides a discharge path for C3 with a time constant much

longer than that of the rectiﬁed AC to prevent generation of line

frequency ripple.

The VOLTAGE MONITOR pin current and the FEEDBACK pin

current are used internally to control the average output LED

current. For TRIAC phase-dimming applications a 49.9 kW

resistor (R4) is used on the REFERENCE pin and 4 MW (R2+R3)

on the VOLTAGE MONITOR pin to provide a linear relationship

between input voltage and the output current and maximizing

the dimming range. Resistor R4 also sets the internal line input

undervoltage and overvoltage protection thresholds.

R11

2.4 MΩ

750 kΩ

R10

750 kΩ

PI-5997-061510

R FB

CONTROL

FL1

RM8

1 FL2

2 MΩ

240 kΩ

1/2 W

R16

1 kΩ

1000 µH

R17

1 kΩ

2 MΩ

49.9 kΩ

162 kΩ

R15

20 kΩ28 V, 500 mA

90 - 265

VAC

RTN

10 kΩ

150 Ω

3 kΩ

R19

1 kΩ

DL4007

UF4007

1N4148

VR3

ZMM5259B-7

39 V

MMBT3904

BAV21WS-7-F

DL4936

MBRS4201T3G

UF4002

VR1

P6KE200A

R20

10 kΩ

BR1

2KBP06M

600 V

3.15 A

RV1

275 VAC

330 µF

50 V

2.2 nF

250 VAC

C10

330 µF

50 V

10 µF

16 V

C12

1 µF

50 V

C13

100 nF

50 V

22 µF

50 V

LinkSwitch-PH

LNK406EG

1 µF

400 V

47 nF

275 VAC

100 nF

630 V

R18

510 Ω

1 W

C11

220 nF

630 V

R12

15 Ω

R13

130 Ω

1/2 W

DL4002

IRFR310

VR2

ZMM5245B-7

15 V

FMMT558

15 nF

50 V

Figure 7. Schematic of an Isolated, TRIAC Dimmable, High Power Factor, Universal Input, 14 W LED Driver.

Rev. G 06/15

LNK403-410/413-420

www.power.com

Diode D3 and VR1 clamp the drain voltage to a safe level due to

the effects of leakage inductance. Diode D4 is necessary to

prevent reverse current from ﬂowing through U1 for the period

of the rectiﬁed AC input voltage that the voltage across C2 falls

to below the reﬂected output voltage (VOR).

Diode D6, C5, R7 and R8 create the primary bias supply from

an auxiliary winding on the transformer. Capacitor C4 provides

local decoupling for the BYPASS pin of U1 which is the supply

pin for the internal controller. During start-up C4 is charged to

~6 V from an internal high-voltage current source tied to the

device DRAIN pin. This allows the part to start switching at

which point the operating supply current is provided from the

bias supply via R5. Capacitor C4 also selects the output power

mode (10 mF for reduced power was selected to reduce

dissipation in U1 and increase efﬁciency).

Feedback

The bias winding voltage is proportional to the output voltage

(set by the turns ratio between the bias and secondary

windings). This allows the output voltage to be monitored

without secondary-side feedback components. Resistor R6

converts the bias voltage into a current which is fed into the

FEEDBACK pin of U1. The internal engine within U1 combines

the FEEDBACK pin current, VOLTAGE MONITOR pin current

and drain current information to provide a constant output

current over a 1.5:1 output voltage variation (LED string voltage

variation of ±25%) at a ﬁxed line input voltage.

To limit the output voltage at no-load an output overvoltage

protection circuit is set by D7, C12, R20, VR3, C13, Q3 and R19.

Should the output load be disconnected then the bias voltage

will increase until VR3 conducts, turning on Q3 and reducing

the current into the FEEDBACK pin. When this current drops

below 20 mA the part enters auto-restart and switching is

disabled for 1500 ms allowing time for the output and bias

voltages to fall.

Output Rectiﬁcation

The transformer secondary winding is rectiﬁed by D8 and

ﬁltered by C8 and C10. A Schottky barrier diode was selected

for efﬁciency and the combined value of C8 and C10 were

selected to give peak-to-peak and LED ripple current equal to

40% of the mean value. For designs where lower ripple is

desirable the output capacitance value can be increased.

A small pre-load is provided by R15 which limits the output

voltage under no-load conditions.

TRIAC Phase Dimming Control Compatibility

The requirement to provide output dimming with low cost,

TRIAC-based, leading edge phase dimmers introduces a

number of trade-offs in the design.

Due to the much lower power consumed by LED based lighting

the current drawn by the overall lamp is below the holding

current of the TRIAC within the dimmer. This can cause

undesirable behaviors such as limited dimming range and/or

ﬂickering as the TRIAC ﬁres inconsistently. The relatively large

impedance the LED lamp presents to the line allows signiﬁcant

ringing to occur due to the inrush current charging the input

capacitance when the TRIAC turns on. This too can cause

similar undesirable behavior as the ringing may cause the

TRIAC current to fall to zero and turn off.

To overcome these issues two circuits, the Active Damper and

Passive Bleeder, are incorporated. The drawback of these

circuits is increased dissipation and therefore reduced efﬁciency

of the supply. For non-dimming applications these components

can simply be omitted.

The Active Damper consists of components R9, R10, R11, R12,

D1, Q1, C6, VR2, Q2 in conjunction with R13. This circuit limits

the inrush current that ﬂows to charge C2 when the TRIAC

turns on by placing R13 in series for the ﬁrst 1 ms of the TRIAC

conduction. After approximately 1 ms, Q2 turns on and shorts

R13. This keeps the power dissipation on R13 low and allows a

larger value during current limiting. Resistor R9, R10, R11 and

C6 provide the 1 ms delay after the TRIAC conducts. Transistor

Q1 discharges C6 when the TRIAC is not conducting and VR2

clamps the gate voltage of Q2 to 15 V.

The Passive Bleeder circuit is comprised of C11 and R18. This

helps to keep the input current above the TRIAC holding current

while the input current corresponding to the effective driver

resistance increases during each AC half-cycle.

Rev. G 06/15

LNK403-410/413-420

www.power.com

7 W High Power Factor Non-Dimmable LED Driver

Design Example with Enhanced Line Regulation

The circuit schematic in Figure 8 shows a high power-factor

LED driver based on a LNK413EG from the LinkSwitch-PH

family of devices. It was optimized to drive an LED string at a

voltage of 21 V with a constant current of 0.33 A, ideal for

PAR20/PAR30 lamp retro-ﬁt applications. The design operates

over the universal input voltage range of 90 VAC to 265 VAC

and is a non-dimming application. A non-dimming application

has tighter output current variation with changes in the line

voltage than a dimming application. It’s key to note that, although

not speciﬁed for dimming, no circuit damage will result if the

end user does operate the design with a phase controlled

dimmer.

Circuit Description

Input Stage

Fuse F1 provides protection from component failures while RV1

provides a clamp during differential line surges, keeping the

peak drain voltage of U1 below the 725 V rating of the internal

power FET. Bridge rectiﬁer BR1 rectiﬁes the AC line voltage.

EMI ﬁltering is provided by L1-L3, C2 together with the safety

rated Y class capacitor (C7) that bridges the safety isolation

barrier between primary and secondary. Resistor R2 and R3

act to damp any resonances formed between L1, L2, C2 and

the AC line impedance. A small bulk capacitor (C3) is required

to provide a low impedance source for the primary switching

current. The maximum value of C2 and C3 is limited in order to

maintain a power factor of greater than 0.9.

LinkSwitch-PH Primary

To provide peak line voltage information to U1 the incoming

rectiﬁed AC peak charges C8 via D6. This is then fed into the

VOLTAGE MONITOR pin of U1 as a current via R4, R7 and R8.

The VOLTAGE MONITOR pin current and the FEEDBACK pin

current are used internally to control the average output LED

current. The combined value of R4, R7 and R8 (3.909 MW)

and R11, R12 (1.402 MW) connected to the VOLTAGE MONITOR

pin provides excellent line regulation over the entire 90 VAC to

265 VAC input range.

The VOLTAGE MONITOR pin current is also used by the device

to set the line input overvoltage and undervoltage protection

thresholds.

Diode D1 and VR1 clamp the drain voltage to a safe level due to

the effects of leakage inductance. A Zener clamp was selected

for lowest component count and highest efﬁciency. Diode D5 is

necessary to prevent reverse current from ﬂowing through U1

during the period when the AC input voltage is lower than the

reﬂected output voltage (VOR). A space efﬁcient RM6 core was

selected for this design. The RM core geometry helps minimizes

audible noise but requires the use of ﬂying leads to meet safety

spacing requirements.

Diode D3, C6, R5, R9 and R18 create the primary bias supply

from an auxiliary winding on the transformer. Resistor R5

provides ﬁltering of leakage inductance generated voltage

spikes to improve tracking of the bias and output voltages. It

also forms a pole with C6 at ~100 Hz. Resistors R9 and R18

act as a small load to ensure that the bias voltage collapses

during output short-circuit when U1 enters auto-restart

operation to protect the supply.

Output overvoltage and load disconnection protection is

provided by D8, C14, R24, VR3, C15, R23 and Q2. Should the

output LED load become disconnected the output voltage will

rise causing an associated rise in the bias winding voltage

across C14. Once this exceeds the voltage rating of VR3, Q2

turns on pulling down the FEEDBACK pin of U1 and initiating

auto-restart operation. Once in auto-restart the low duty cycle

of operation (~3%) together with the small pre-load on the

output prevents the output voltage rising to a high level. Once

the output load is reconnected normal operation resumes.

Figure 8. Schematic of an Isolated, Non-Dimmable, High Power Factor, Universal Input, 7 W LED Driver.

PI-5991-101210

R FB

CONTROL

FL2

RM6

FL1

1 FL3

2 MΩ

1 kΩ

1000 µH

1 kΩ

1 MΩ

909 kΩ

R11

1.0 MΩ

R12

402 kΩ

R19

24.9 kΩ

R15

150 kΩ

20 kΩ21 V, 330 mA

90 - 265

VAC

RTN

10 kΩ

R18

10 kΩ

75 Ω

R10

3 kΩ

R23

1 kΩ

DL4007

UF4007

1N4148

VR3

ZMM5259B-7

39 V

MMBT3904

BAV21WS-7-F

DL4936

MBRS4201T3G

ES1D

VR1

P6KE200A

R24

10 kΩ

BR1

DF06S-E3/45

600 V

3.15 A

RV1

275 VAC

150 µF

35 V

2.2 nF

250 VAC

150 µF

35 V

C12

10 µF

10 V

C14

1 µF

50 V

C15

100 nF

50 V

22 µF

50 V

LinkSwitch-PH

LNK413EG

1 µF

400 V

22 nF

275 VAC

100 nF

400 V

Rev. G 06/15

LNK403-410/413-420

www.power.com

Capacitor C12 provides local decoupling for the BYPASS pin of

U1 which is the supply pin for the internal controller. During

start-up C4 is charged to ~6 V from an internal high-voltage

current source tied to the device DRAIN pin. Once the bias

voltage has risen into regulation the operating supply current is

provided via R10. Diode D4 prevents U1 from charging C6

during start-up which would increase the start-up delay time.

Feedback

The bias winding voltage is proportional to the output voltage

(set by the turns ratio between the bias and secondary

windings). This allows the output voltage to be monitored

without secondary-side feedback components. Resistor R15

converts the bias voltage into a current which is fed into the

FEEDBACK pin of U1. The internal engine within U1 combines

the FEEDBACK pin current, VOLTAGE MONITOR pin current

and drain current information to provide a constant output

current over a 2:1 output voltage range.

Output Rectiﬁcation

The transformer secondary winding is rectiﬁed by D2 and

ﬁltered by C4 and C5. A Schottky barrier diode was selected

for efﬁciency and the combined value of C4 and C5 were

selected to give an acceptable LED ripple current. For designs

where lower ripple is desirable the output capacitance value

can be increased. A small pre-load is provided by R6 which

limits the output voltage under no-load conditions.

Key Application Considerations

Power Table

The data sheet power table (Table 1) represents the minimum

and maximum practical continuous output power based on the

following conditions:

1. Efﬁciency of 80%

2. Device local ambient of 70 °C

3. Sufﬁcient heat sinking to keep the device temperature

below 100 °C

4. For minimum output power column

• Reﬂected output voltage (VOR) of 120 V

• FEEDBACK pin current of 135 mA

• BYPASS pin capacitor value of 10 mF

5. For maximum output power column

• Reﬂected output voltage (VOR) of 65 V

• FEEDBACK pin current of 165 mA

• BYPASS pin capacitor value of 100 mF

(LNK4x3EG = 10 mF)

Note that input line voltages above 85 VAC do not change the

power delivery capability of LinkSwitch-PH devices.

Device Selection

Select the device size by comparing the required output power

to the values in Table 1. For thermally challenging designs,

e.g., incandescent lamp replacement, where either the ambient

temperature local to the LinkSwitch-PH device is high and/or

there is minimal space for heat sinking use the minimum output

power column. This is selected by using a 10 mF BYPASS pin

capacitor and results in a lower device current limit and

therefore lower conduction losses. For open frame design or

designs where space is available for heat sinking then refer to

the maximum output power column. This is selected by using

a 100 mF BYPASS pin capacitor for all but the LNK4x3 which

has only one power setting. In all cases in order to obtain the

best output current tolerance maintain the device temperature

below 100 °C

Maximum Input Capacitance

To achieve high power factor, the capacitance used in both the

EMI ﬁlter and for decoupling the rectiﬁed AC (bulk capacitor)

must be limited in value. The maximum value is a function of

the output power of the design and reduces as the output

power reduces. For the majority of designs limit the total

capacitance to less than 200 nF with a bulk capacitor value of

100 nF. Film capacitors are recommended compared to

ceramic types as they minimize audible noise with operating

with leading edge phase dimmers. Start with a value of 10 nF

for the capacitance in the EMI ﬁlter and increase in value until

there is sufﬁcient EMI margin.

REFERENCE Pin Resistance Value Selection

The LinkSwitch-PH family contains phase dimming devices,

LNK403-410, and non-dimming devices, LNK413-420. The

non-dimmable devices use a 24.9 kW ±1% REFERENCE pin

resistor in high-line and universal input voltage designs and

49.9 kW ±1% in low-line input voltage designs, for best output

current tolerance (over AC input voltage changes). The dimmable

devices use 49.9 kW ±1% to achieve the widest dimming range.

VOLTAGE MONITOR Pin Resistance Network Selection

For widest AC phase angle dimming range with LNK403-410,

use a 4 MW resistor connected to the line voltage peak detector

circuit. Make sure that the resistor’s voltage rating is sufﬁcient

for the peak line voltage. If necessary use multiple series

connected resistors.

For best line regulation, use a series combination of resistors

that equals 3.909 MW connected to the line voltage peak

detector. In addition, connect a 1 MW in series with a 402 kW

resistor (1.402 MW total) from the VOLTAGE MONITOR pin to

SOURCE pin. Use 1% tolerance resistors for good accuracy.

Line regulation can be further improved by using the PIXls

spreadsheet’s ﬁne tuning section. See the LinkSwitch-PH

Application Note for more information.

Primary Clamp and Output Reﬂected Voltage VOR

A primary clamp is necessary to limit the peak drain to source

voltage. A Zener clamp requires the fewest components and

board space and gives the highest efﬁciency. RCD clamps are

also acceptable however the peak drain voltage should be

carefully veriﬁed during start-up and output short-circuit as the

clamping voltage varies with signiﬁcantly with the peak drain

current.

For the highest efﬁciency, the clamping voltage should be

selected to be at least 1.5 times the output reﬂected voltage,

VOR, as this keeps the leakage spike conduction time short.

When using a Zener clamp in a universal input or high-line only

application, a VOR of less than 135 V is recommended to allow

Rev. G 06/15

LNK403-410/413-420

www.power.com

for the absolute tolerances and temperature variations of the

Zener. This will ensure efﬁcient operation of the clamp circuit

and will also keep the maximum drain voltage below the rated

breakdown voltage of the FET. An RCD (or RCDZ) clamp

provides tighter clamp voltage tolerance than a Zener clamp.

The RCD clamp is more cost effective than the Zener clamp but

requires more careful design to ensure that the maximum drain

voltage does not exceed the power FET breakdown voltage.

These VOR limits are based on the BVDSS rating of the internal

FET, a VOR of 60 V to 100 V is typical for most designs, giving

the best PFC and regulation performance.

Series Drain Diode

An ultra-fast or Schottky diode in series with the drain is

necessary to prevent reverse current ﬂowing through the

device. The voltage rating must exceed the output reﬂected

voltage, VOR. The current rating should exceed two times the

average primary current and have a peak rating equal to the

maximum drain current of the selected LinkSwitch-PH device.

Line Voltage Peak Detector Circuit

LinkSwitch-PH devices use the peak line voltage to regulate the

power delivery to the output. A capacitor value of 1 mF to 4.7 mF

is recommended to minimize line ripple and give the highest

power factor (>0.9), smaller values are acceptable but result in

lower PF and higher line current distortion.

Operation with Phase Controlled Dimmers

Dimmer switches control incandescent lamp brightness by not

conducting (blanking) for a portion of the AC voltage sine wave.

This reduces the RMS voltage applied to the lamp thus reducing

the brightness. This is called natural dimming and the

LinkSwitch-PH LNK403-410 devices when conﬁgured for

dimming utilize natural dimming by reducing the LED current as

the RMS line voltage decreases. By this nature, line regulation

performance is purposely decreased to increase the dimming

range and more closely mimic the operation of an incandescent

lamp. Using a 49.9 kW REFERENCE pin resistance selects

natural dimming mode operation.

Leading Edge Phase Controlled Dimmers

The requirement to provide ﬂicker-free output dimming with low

cost, TRIAC-based, leading edge phase dimmers introduces a

number of trade-offs in the design.

Due to the much lower power consumed by LED based lighting

the current drawn by the overall lamp is below the holding

current of the TRIAC within the dimmer. This causes undesirable

behaviors such as limited dimming range and/or ﬂickering. The

relatively large impedance the LED lamp presents to the line

allows signiﬁcant ringing to occur due to the inrush current

charging the input capacitance when the TRIAC turns on. This

too can cause similar undesirable behavior as the ringing may

cause the TRIAC current to fall to zero and turn off.

To overcome these issues two circuits, the Active Damper and

Passive Bleeder, are incorporated. The drawback of these

circuits is increased dissipation and therefore reduced efﬁciency

of the supply so for non-dimming applications these

components can simply be omitted.

Figure 9(a) shows the line voltage and current at the input of a

leading edge TRIAC dimmer with Figure 9(b) showing the

resultant rectiﬁed bus voltage. In this example, the TRIAC

conducts at 90 degrees.

Figure 10 shows undesired rectiﬁed bus voltage and current

with the TRIAC turning off prematurely and restarting.

If the TRIAC is turning off before the end of the half-cycle

erratically or alternate half AC cycles have different conduction

angles then ﬂicker will be observed in the LED light due to

variations in the output current. This can be solved by including

a bleeder and damper circuit.

Dimmers will behave differently based on manufacturer and

power rating, for example a 300 W dimmer requires less

dampening and requires less power loss in the bleeder than a

600 W or 1000 W dimmer due to different drive circuits and

TRIAC holding current speciﬁcations. Line voltage also has a

signiﬁcant impact as at high-line for a given output power the

input current and therefore TRIAC current is lower but the peak

inrush current when the input capacitance charges is higher

creating more ringing. Finally multiple lamps in parallel driven

from the same dimmer can introduce more ringing due to the

50 100 150 200 250 300 350 400

Conduction Angle (°)

Line Voltage (at Dimmer Input) (V)

Line Current (Through Dimmer) (A)

350

250

150

-50

-150

-250

-350

0.35

0.25

0.15

0.05

-0.05

-0.15

-0.25

-0.35

PI-5983-060810

Voltage

Current

0.5

050 100 150 200 250 400350300

Conduction Angle (°)

Rectified Input Voltage (V)

Rectified Input Current (A)

350

300

250

200

150

100

0.35

0.3

0.25

0.2

0.15

0.1

0.05

PI-5984-060810

Voltage

Current

Figure 9. (a) Ideal Input Voltage and Current Waveforms for a Leading Edge

TRIAC Dimmer at 90° Conduction Angle. (b) Resultant Waveforms

Following Rectiﬁcation of TRIAC Dimmer Output.

Rev. G 06/15

LNK403-410/413-420

www.power.com

increased capacitance of parallel units. Therefore when testing

dimmer operation verify on a number of models, different line

voltages and with both a single driver and multiple drivers in parallel.

Start by adding a bleeder circuit. Add a 0.44 mF capacitor and

510 W 1 W resistor (components in series) across the rectiﬁed

bus (C11 and R18 in Figure 7). If this results in satisfactory

operation reduce the capacitor value to the smallest that results

in acceptable performance to reduce losses and increase efﬁciency.

If the bleeder circuit does not maintain conduction in the TRIAC,

then add an active damper as shown in Figure 7. This consists

of components R9, R10, R11, R12, D1, Q1, C6, VR2, Q2 in

conjunction with R13. This circuit limits the inrush current that

ﬂows to charge C2 when the TRIAC turns on by placing R13 in

series for the ﬁrst 1 ms of the TRIAC conduction. After

approximately 1 ms, Q2 turns on and shorts R13. This keeps

the power dissipation on R13 low and allows a larger value to

be used during current limiting. Increasing the delay before Q2

turns on by increasing the values of resistors R9 and R10 will

improve dimmer compatibility but cause more power to be

dissipated across R13. Monitor the AC line current and voltage

at the input of the power supply as you make the adjustments.

Increase the delay until the TRIAC operates properly but keep

the delay as short as possible for efﬁciency.

As a general rule the greater the power dissipated in the

bleeder and damper circuits, the more dimmer types will work

with the driver.

Trailing Edge Phase Controlled Dimmers

Figure 11 shows the line voltage and current at the input of the

power supply with a trailing edge dimmer. In this example, the

dimmer conducts at 90 degrees. Many of these dimmers use

back-to-back connected power FETs rather than a TRIAC to

control the load. This eliminates the holding current issue of

TRIACs and since the conduction begins at the zero crossing, high

current surges and line ringing are minimized. Typically these

types of dimmers do not require damping and bleeder circuits.

Audible Noise Considerations for Use with

Leading Edge Dimmers

Noise created when dimming is typically created by the input

capacitors, EMI ﬁlter inductors and the transformer. The input

capacitors and inductors experience high di/dt and dv/dt every

AC half-cycle as the TRIAC ﬁres and an inrush current ﬂows to

charge the input capacitance. Noise can be minimized by

selecting ﬁlm vs ceramic capacitors, minimizing the capacitor

value and selecting inductors that are physically short and wide.

The transformer may also create noise which can be minimized

by avoiding cores with long narrow legs (high mechanical

resonant frequency). For example, RM cores produce less

audible noise than EE cores for the same ﬂux density. Reducing

the core ﬂux density will also reduce the noise. Reducing the

maximum ﬂux density (BM) to 1500 Gauss usually eliminates

any audible noise but must be balanced with the increased core

size needed for a given output power.

Thermal and Lifetime Considerations

Lighting applications present thermal challenges to the driver.

In many cases the LED load dissipation determines the working

ambient temperature experienced by the drive so thermal

evaluation should be performed with the driver inside the ﬁnal

enclosure. Temperature has a direct impact on driver and LED

lifetime. For every 10 °C rise in temperature, component life is

reduced by a factor of 2. Therefore it is important to properly

heat sink and verify the operating temperatures of all devices.

050 100 150 200 250 400350300

Conduction Angle (°)

Rectified Input Voltage (V)

Rectified Input Current (A)

350

300

250

200

150

100

0.35

0.3

0.25

0.2

0.15

0.1

0.05

PI-5985-102810

Voltage

Current

Figure 10. Example of Phase Angle Dimmer Showing Erratic Firing.

50 100 150 200 250 300 350

Conduction Angle (°)

Dimmer Output Voltage (V)

Dimmer Output Current (A)

350

250

150

-50

-150

-250

-350

0.35

0.25

0.15

0.05

-0.05

-0.15

-0.25

-0.35

PI-5986-060810

Voltage

Current

Figure 11. Ideal Dimmer Output Voltage and Current Waveforms for a Trailing Edge

Dimmer at 90° Conduction Angle.

Rev. G 06/15

LNK403-410/413-420

www.power.com

Layout Considerations

Primary-Side Connections

Use a single point (Kelvin) connection at the negative terminal of

the input ﬁlter capacitor for the SOURCE pin and bias returns.

This improves surge capabilities by returning surge currents

from the bias winding directly to the input ﬁlter capacitor. The

BYPASS pin capacitor should be located as close to the

BYPASS pin and connected as close to the SOURCE pin as

possible. The SOURCE pin trace should not be shared with the

main power FET switching currents. All FEEDBACK pin

components that connect to the SOURCE pin should follow the

Figure 12. RD-193 7 W Layout Example, Top Layer.

same rules as the BYPASS pin capacitor. It is critical that the

main power FET switching currents return to the bulk capacitor

with the shortest path as possible. Long high current paths

create excessive conducted and radiated noise.

Secondary-Side Connections

The output rectiﬁer and output ﬁlter capacitor should be as

close as possible. The transformer’s output return pin should

have a short trace to the return side of the output ﬁlter capacitor.

PI-5987-060110

RV1

L1 C2

R16

R14

VR1

FL1

Transformer

C12

R10

VR3

R24

C14

C15

R15

FL2

FL3

R23

Output

Filter

Capacitors

BYPASS Pin

Capacitor

Copper Area for

Heat Sinking

Input EMI Filter

Bulk Capacitor LNK403EG

Clamp

Rev. G 06/15

LNK403-410/413-420

www.power.com

Figure 13. RD-193 7 W Layout Example, Bottom Layer.

PI-5988-060110

VR2

R4 R7

R20 C13

BR1

R17

R13 D6

R12 D1

R19

R18

Output

Rectifier

Bridge Rectifier

Active Damper

MOSFET

Quick Design Checklist

Maximum Drain Voltage

Verify that the peak VDS does not exceed 725 V under all

operating conditions including start up and fault conditions.

Maximum Drain Current

Measure the peak drain current under all operation conditions

including start up and fault conditions. Look for signs of

transformer saturation (usually occurs at highest operating

ambient temperatures). Verify that the peak current is less that

stated for the Absolute Maximum Rating in the data sheet.

Thermal Check

At maximum output power, both minimum and maximum line

voltage and ambient temperature; verify that temperature

speciﬁcations are not exceeded for the LinkSwitch-PH,

transformer, output diodes, output capacitors and drain clamp

components.

Rev. G 06/15

LNK403-410/413-420

www.power.com

Parameter Symbol

Conditions

SOURCE = 0 V; TJ = -20 °C to 125 °C

(Unless Otherwise Speciﬁed)

Min Typ Max Units

Control Functions

Switching Frequency fOSC TJ = 25 °C Average 62 66 70 kHz

Peak-Peak Jitter 9

Frequency Jitter

Modulation Rate fM

TJ = 25 °C

See Note B 1 kHz

BYPASS Pin

Charge Current

ICH1

VBP = 0 V,

TJ = 25 °C

LNK403, LNK413 -5.0 -4.2 -3.4

LNK404, LNK414 -9.6 -8.0 -6.4

LNK405-410,

LNK415-420 -17 -12 -8.8

ICH2

VBP = 5 V,

TJ = 25 °C

LNK403, LNK413 -1.6 -1.2 -0.6

LNK404, LNK414 -4.2 -3.5 -2.8

LNK405-410,

LNK415-420 -9 -6.8 -4.6

Charging Current

Temperature Drift See Note A 0.5 %/°C

BYPASS Pin Voltage VBP 0 °C < TJ < 100 °C 5.7 5.9 6.1 V

BYPASS Pin Voltage

Hysteresis VBP(H) 0 °C < TJ < 100 °C 0.85 V

BYPASS Pin

Shunt Voltage VBP(SHUNT)

IBP = 2 mA

0 °C < TJ < 100 °C 6.0 6.4 6.7 V

Soft-Start Time tSOFT

TJ = 25 °C

VBP = 5.9 V 40 ms

Absolute Maximum Ratings(1,4)

DRAIN Pin Peak Current(5): LNK403, LNK413 ...................1.37 A

LNK404, LNK414 ...................2.08 A

LNK405, LNK415 ...................2.72 A

LNK406, LNK416 .................. 4.08 A

LNK407, LNK417 .................. 5.44 A

LNK408, LNK418 .................. 6.88 A

LNK409, LNK419 ................... 7.73 A

LNK410, LNK420 .................. 9.00 A

DR AIN Pin Voltage ……………………… ................ -0.3 to 725 V

BYPASS Pin Voltage ............................................... -0.3 to 9 V

BYPASS Pin Current .................................................... 100 mA

VOLTAGE MONITOR Pin Voltage ............................-0.3 to 9 V(6)

FEEDBACK Pin Voltage …….. .................................. -0.3 to 9 V

REFERENCE Pin Voltage .......................................... -0.3 to 9 V

Lead Temperature(3) ....................................................... .........260 °C

Storage Temperature .......................................... -65 to 150 °C

Operating Junction Temperature(2) .........................-40 to 150 °C

Notes:

1. All voltages referenced to SOURCE, TA = 25 °C.

2. Normally limited by internal circuitry.

3. 1/16 in. from case for 5 seconds.

4. Absolute Maximum Ratings speciﬁed may be applied, one

at a time without causing permanent damage to the

product. Exposure to Absolute Maximum Ratings for

extended periods of time may affect product reliability.

5. Peak DRAIN current is allowed while the DRAIN voltage is

simultaneously less than 400 V. See also Figure 17.

6. During start-up (the period before the BYPASS pin begins

powering the IC) the VOLTAGE MONITOR pin voltage can

safely rise to 15 V without damage.

Thermal Resistance

Thermal Resistance: eSIP Package:

(qJA) ....................................................105 °C/W(1)

(qJC) .................................................... 2 °C/W(2)

Notes:

1. Free Standing with no heat sink.

2. Measured at back surface tab.

Rev. G 06/15

LNK403-410/413-420

www.power.com

Parameter Symbol

Conditions

SOURCE = 0 V; TJ = -20 °C to 125 °C

(Unless Otherwise Speciﬁed)

Min Typ Max Units

Control Functions (cont.)

Drain Supply Current

ICD2

0 °C < TJ < 100 °C

FET Not Switching 0.5 0.85 1.2

ICD1

0 °C < TJ < 100 °C

FET Switching at fOSC

0.9 1.5 2.25

VOLTAGE MONITOR Pin

Line Brown-In

Threshold Current IUV+ TJ = 25 °C RR = 24.9 kW21.0 22.5 24.0 mA

RR = 49.9 kW22.8 24.5 26.2

Line Brown-Out

Threshold Current IUV- TJ = 25 °C RR = 24.9 kW18.5 mA

RR = 49.9 kW15.0

Line Brown-In/Out

Hysteresis IUV(H) TJ = 25 °C RR = 24.9 kW1 4 mA

RR = 49.9 kW5 9.4

Line Overvoltage

Threshold IOV

TJ = 25 °C

RR = 24.9 kW

RR = 49.9 kW

Threshold 107 112 117

Hysteresis 4

VOLTAGE MONITOR Pin

Voltage VV

0 °C < TJ < 100 °C

IUV- < IV < IOV

2.75 3.0 3.25 V

VOLTAGE MONITOR Pin

Short-Circuit Current IV(SC)

VV = 5 V

TJ = 25 °C 170 190 210 mA

Remote ON/OFF

Threshold VV(REM) TJ = 25 °C 0.5 V

FEEDBACK Pin

FEEDBACK Pin Current

at Onset of Maximum

Duty Cycle

IFB(DCMAXR) 0 °C < TJ < 100 °C 85 mA

FEEDBACK Pin Current

Skip Cycle Threshold IFB(SKIP) 0 °C < TJ < 100 °C 220 mA

Maximum Duty Cycle DCMAX

IFB(DCMAXR) < IFB < IFB(SKIP)

0 °C < TJ < 100 °C 90 99.9 %

FEEDBACK Pin Voltage VFB

IFB = 150 mA

0 °C < TJ < 100 °C 2.08 2.40 2.62 V

FEEDBACK Pin

Short-Circuit Current IFB(SC)

VFB = 5 V

TJ = 25 °C 320 400 480 mA

Duty Cycle Reduction

DC10 IFB = IFB(AR), TJ = 25 °C, See Note B 10

%DC40 IFB = 40 mA, TJ = 25 °C 20

DC60 IFB = 60 mA, TJ = 25 °C 36

Auto-Restart

Auto-Restart ON-Time tAR

TJ = 25 °C

VBP = 5.9 V 40 ms

Auto-Restart

Duty Cycle DCAR TJ = 25 °C 3 %

Rev. G 06/15

LNK403-410/413-420

www.power.com

Parameter Symbol

Conditions

SOURCE = 0 V; TJ = -20 °C to 125 °C

(Unless Otherwise Speciﬁed)

Min Typ Max Units

Auto-Restart (cont.)

SOA Minimum Switch

ON-Time tON(SOA)

TJ = 25 °C

See Note B 1.75 ms

FEEDBACK Pin

Current During

Auto-Restart

IFB(AR) 0 °C < TJ < 100 °C 17.5 mA

REFERENCE Pin

Voltage VRRR = 24.9 kW

0 °C < TJ < 100 °C

1.215 1.245 1.275 V

REFERENCE Pin

Current IR48.45 49.70 50.95 mA

Current Limit/Circuit Protection

Full Power

Current Limit

(CBP = 100 mF)

ILIMIT(F)

TJ = 25 °C

di/dt = 174 mA/ms LNK404, LNK414 1.02 1.18

di/dt = 174 mA/ms LNK405, LNK415 1.24 1.44

di/dt = 225 mA/ms LNK406, LNK416 1.50 1.74

di/dt = 320 mA/ms LNK407, LNK417 1.77 2.06

di/dt = 350 mA/ms LNK408, LNK418 2.39 2.77

di/dt = 426 mA/ms LNK409, LNK419 3.26 3.79

di/dt = 1060 mA/ms LNK410, LNK420 4.90 5.70

Reduced Power

Current Limit

(CBP = 10 mF)

ILIMIT(R)

TJ = 25 °C

di/dt = 133 mA/ms LNK403, LNK413 0.75 0.85

di/dt = 195 mA/ms LNK404, LNK414 0.81 0.94

di/dt = 192 mA/ms LNK405, LNK415 1.00 1.16

di/dt = 240 mA/ms LNK406, LNK416 1.19 1.38

di/dt = 335 mA/ms LNK407, LNK417 1.42 1.66

di/dt = 380 mA/ms LNK408, LNK418 1.73 2.01

di/dt = 466 mA/msLNK409, LNK419 2.35 2.73

di/dt = 1060 mA/ms LNK410, LNK420 4.90 5.70

Minimum ON-Time

Pulse tLEB + tIL(D) TJ = 25 °C 300 500 700 ns

Leading Edge

Blanking Time tLEB

TJ = 25 °C

See Note B 150 500 ns

Current Limit Delay tIL(D)

TJ = 25 °C

See Note B 150 ns

Thermal Shutdown

Temperature 135 142 150 °C

Thermal Shutdown

Hysteresis 75 °C

BYPASS Pin Power-Up

Reset Threshold

Voltage

VBP(RESET) 0 °C < TJ < 100 °C 2.25 3.5 4.25 V

Rev. G 06/15

LNK403-410/413-420

www.power.com

Parameter Symbol

Conditions

SOURCE = 0 V; TJ = -20 °C to 125 °C

(Unless Otherwise Speciﬁed)

Min Typ Max Units

Output

ON-State Resistance RDS(ON)

LNK403, LNK413

ID = 100 mA

TJ = 25 °C 9.00 10.35

TJ = 100 °C 13.50 15.5

LNK404, LNK414

ID = 100 mA

TJ = 25 °C 5.40 6.25

TJ = 100 °C 8.35 9.7

LNK405, LNK415

ID = 150 mA

TJ = 25 °C 4.10 4.7

TJ = 100 °C 6.30 7.3

LNK406, LNK416

ID = 150 mA

TJ = 25 °C 2.80 3.2

TJ = 100 °C 4.10 4.75

LNK407, LNK417

ID = 200 mA

TJ = 25 °C 2.00 2.3

TJ = 100 °C 3.10 3.6

LNK408, LNK418

ID = 250 mA

TJ = 25 °C 1.60 1.85

TJ = 100 °C 2.40 2.8

LNK409, LNK419

ID = 350 mA

TJ = 25 °C 1.40 1.6

TJ = 100 °C 2.10 2.45

LNK410, LNK420

ID = 550 mA

TJ = 25 °C 1.05 1.2

TJ = 100 °C 1.6 1.85

OFF-State Drain

Leakage Current IDSS

VBP = 6.4 V

VDS = 560 V

TJ = 100 °C

50 mA

Breakdown Voltage BVDSS

VBP = 6.4 V

TJ = 25 °C 725 V

Minimum Drain

Supply Voltage TJ < 100 °C 36 V

Rise Time tRMeasured in a Typical Flyback

100 ns

Fall Time tF50 ns

NOTES:

A. For speciﬁcations with negative values, a negative temperature coefﬁcient corresponds to an increase in magnitude with increas-

ing temperature and a positive temperature coefﬁcient corresponds to a decrease in magnitude with increasing temperature.

B. Guaranteed by characterization. Not tested in production.

Rev. G 06/15

LNK403-410/413-420

www.power.com

Typical Performance Characteristics

Figure 14. Drain Capacitance vs. Drain Pin Voltage. Figure 15. Power vs. Drain Voltage.

Figure 16. Drain Current vs. Drain Voltage. Figure 17. Maximum Allowable Drain Current vs. Drain Voltage.

0 100 200 300 400 500 600

100

1000

10000

PI-5992-032912

DRAIN Pin Voltage (V)

DRAIN Capacitance (pF)

LNK403, LNK413 0.18

LNK404, LNK414 0.28

LNK405, LNK415 0.38

LNK406, LNK416 0.56

LNK407, LNK417 0.75

LNK408, LNK418 1.00

LNK409, LNK419 1.16

LNK410, LNK420 1.55

Scaling Factors:

300

100

200

0 200100 400 500 600300 700

DRAIN Voltage (V)

Power (mW)

PI-5993-032912

LNK403, LNK413 0.18

LNK404, LNK414 0.28

LNK405, LNK415 0.38

LNK406, LNK416 0.56

LNK407, LNK417 0.75

LNK408, LNK418 1.00

LNK409, LNK419 1.16

LNK410, LNK420 1.55

Scaling Factors:

02 4 6 8 10 12 14 16 18 20

DRAIN Voltage (V)

DRAIN Current (A)

PI-5994-032912

LNK408 TCASE = 25 °C

LNK408 TCASE = 100 °C

LNK403, LNK413 0.18

LNK404, LNK414 0.28

LNK405, LNK415 0.38

LNK406, LNK416 0.56

LNK407, LNK417 0.75

LNK408, LNK418 1.00

LNK409, LNK419 1.16

LNK410, LNK420 1.55

Scaling Factors:

0100 200 300 400 600500 700 800

DRAIN Voltage (V)

DRAIN Current

(Normalized to Absolute Maximum Rating)

PI-6010-060410

0.6

0.8

0.4

0.2

1.2

Rev. G 06/15

LNK403-410/413-420

www.power.com

PI-4917-061510

MOUNTING HOLE PATTERN

(not to scale)

PIN 7

PIN 1

0.100 (2.54) 0.100 (2.54)

0.059 (1.50)

0.050 (1.27)

0.100 (2.54)

0.155 (3.93)

0.020 (0.50)

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M-1994.

2. Dimensions noted are determined at the outermost

extremes of the plastic body exclusive of mold flash,

tie bar burrs, gate burrs, and interlead flash, but including

any mismatch between the top and bottom of the plastic

body. Maximum mold protrusion is 0.007 [0.18] per side.

3. Dimensions noted are inclusive of plating thickness.

4. Does not include inter-lead flash or protrusions.

5. Controlling dimensions in inches (mm).

0.403 (10.24)

0.397 (10.08)

0.325 (8.25)

0.320 (8.13)

0.050 (1.27)

FRONT VIEW

0.070 (1.78) Ref.

Pin #1

I.D.

0.016 (0.41)

Ref.

0.290 (7.37)

Ref.

0.047 (1.19)

0.100 (2.54)

0.519 (13.18)

Ref.

0.198 (5.04) Ref.

0.264 (6.70)

Ref.

0.118 (3.00)

6×

0.140 (3.56)

0.120 (3.05)

0.021 (0.53)

0.019 (0.48)

0.378 (9.60)

Ref. 0.019 (0.48) Ref.

0.060 (1.52)

Ref.

0.048 (1.22)

0.046 (1.17)

0.081 (2.06)

0.077 (1.96)

0.207 (5.26)

0.187 (4.75)

0.033 (0.84)

0.028 (0.71)

0.016 (0.41)

0.011 (0.28)

eSIP-7C (E Package)

10° Ref.

All Around

0.020 M 0.51 M C

0.010 M 0.25 M C A B

SIDE VIEW

END VIEW

BACK VIEW

0.023 (0.58)

0.027 (0.70)

DETAIL A

Detail A

Rev. G 06/15

LNK403-410/413-420

www.power.com

Part Ordering Information

• LinkSwitch Product Family

• PH Series Number

• Package Identiﬁer

E eSIP-7C

L eSIP-7F

• Package Material

G GREEN: Halogen Free and RoHS Compliant

LNK 409 E G

1 7

END VIEW

0.021 (0.53)

0.019 (0.48)

0.060 (1.52) Ref.

0.019 (0.48) Ref. 0.378 (9.60)

Ref.

0.048 (1.22)

0.046 (1.17)

SIDE VIEW

6×

0.129 (3.28)

0.122 (3.08)

0.081 (2.06)

0.077 (1.96)

Detail A

0.084 (2.14)

0.047 (1.19) Ref.

0.290 (7.37)

Ref.

0.016 (0.41)

0.011 (0.28)

0.020 M 0.51 M C

PI-5204-061510

Notes:

1. Dimensioning and tolerancing per ASME

Y14.5M-1994.

2. Dimensions noted are determined at the

outermost extremes of the plastic body

exclusive of mold flash, tie bar burrs, gate

burrs, and interlead flash, but including

any mismatch between the top and bottom

of the plastic body. Maximum mold

protrusion is 0.007 [0.18] per side.

3. Dimensions noted are inclusive of plating

thickness.

4. Does not include inter-lead flash or

protrusions.

5. Controlling dimensions in inches (mm).

eSIP-7F (L Package)

1 7

BOTTOM VIEW

Pin 1 I.D.

0.403 (10.24)

0.397 (10.08)

0.325 (8.25)

0.320 (8.13)

0.050 (1.27)

0.070 (1.78) Ref.

Exposed pad hidden Exposed pad up

TOP VIEW

0.089 (2.26)

0.079 (2.01)

0.173 (4.40)

0.163 (4.15)

0.198 (5.04) Ref.

0.264 (6.70) Ref.

0.100 (2.54)

0.490 (12.45) Ref.

6×

0.033 (0.84)

0.028 (0.71)

0.010 M 0.25 M C A B

0.020 (0.50)

0.023 (0.58)

0.027 (0.70)

DETAIL A (Not drawn to scale)

Revision Notes Date

A Initial Release. 06/09/10

B Updated Power Table. 08/06/10

C Added Non-Dimming parts and related text. 11/10

D Added L Package. 08/11

E Added new LNK410 and LNK420 parts. 12/11

E Updated Output Power Table values for LNK410/420. Updated Parameter Table values for LNK410/420. 05/12

F Added Note 6 to Absolute Maximum Ratings section. 06/21/13

G Updated with new Brand Style Logo. 06/15

For the latest updates, visit our website: www.power.com

Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power

Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES

NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED

WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.

Patent Information

The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered

by one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations.

A complete list of Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under

certain patent rights as set forth at http://www.power.com/ip.htm.

Life Support Policy

POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR

SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:

1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii)

whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in signiﬁcant

injury or death to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause

the failure of the life support device or system, or to affect its safety or effectiveness.

The PI logo, TOPSwitch, TinySwitch, LinkSwitch, LYTSwitch, InnoSwitch, DPA-Switch, PeakSwitch, CAPZero, SENZero, LinkZero,

HiperPFS, HiperTFS, HiperLCS, Qspeed, EcoSmart, Clampless, E-Shield, Filterfuse, FluxLink, StakFET, PI Expert and PI FACTS are

Power Integrations Worldwide Sales Support Locations

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LNK415LG LNK408LG LNK413LG LNK407LG LNK403LG LNK405LG LNK406LG LNK409LG LNK417LG

LNK414LG LNK410LG LNK410EG LNK419LG LNK404LG LNK416LG