NET+50
Hardware Reference
net50_20_1.book Page 1 Friday, September 19, 2003 10:41 AM
net50_20_1.book Page 2 Friday, September 19, 2003 10:41 AM
Part number/version: 90000553_A
Releas e dat e: Sept ember 2003
www.netsilicon.com
NET+Works Hardware
Reference
net50_20_1.book Page i Friday, September 19, 2003 10:41 AM
©2001-2003 NetSilicon, Inc.
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Contents
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Using This Guide ................................................................................................... xxix
Chapter 1: About the NET+50 chip and NET+20M chip ............1
Introduction....................................................................................................................2
ARM7TDMI....................................................................................................................2
NET+50 chip...................................................................................................................2
Hardware design.................................................................................................3
Device modules ...................................................................................................3
NET+20M chip.... ...... ..... ....................... ....................... ..... ....................... ......................4
Hardware design.................................................................................................4
Device modules ...................................................................................................4
Differences between the NET+50 and NET+20M chips ..........................................5
Cache support......................................................................................................5
Multi Interface Controller support ...................................................................5
GPIO PORTA/B/C pin availability and assignments...................................5
Pin support...........................................................................................................6
Pinout and features.............................................................................................6
Pinout and packaging ................................................................................6
Features........................................................................................................6
Chapter 2: NET+50/20M Chip Features...................................................7
NET+50 chip key features............................................................................................8
NET+20M chip key features ......................................................................................11
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Chapter 3: NET+50 Chip Package .............................................................. 15
NET+50 chip pinouts.................................................................................................. 16
Table Information and Tables ......................................................................... 18
System bus interface......................................................................................... 19
Chip select controller.......... ....................... ...................... ...... ...................... ..... 22
Ethernet interface................ ...... ...................... ....................... ...................... ..... 22
MIC interface ..................................................................................................... 23
UARTS-SPI-GPIO.............................................................................................. 25
Clock generation/system reset....................................................................... 26
JTAG port for ARM core.................................................................................. 27
Power supply..................................................................................................... 27
Signal description summary...................................................................................... 28
System bus interface......................................................................................... 29
Chip select controller.......... ....................... ...................... ...... ...................... ..... 30
Ethernet MII.............. ...................... ....................... ...................... ...... ................ 30
MIC interface ..................................................................................................... 31
MIC interface configured for GPIO mode............................................ 34
GPIO (PORTA/B/C)........................................................................................ 35
Clock generation and reset.............................................................................. 36
Test support....................................................................................................... 37
ARM debugger.................................................................................................. 38
Power.................................................................................................................. 39
Packaging ..................................................................................................................... 40
NET+50 PQFP package.................................................................................... 40
BGA package ..................................................................................................... 42
Chapter 4: Working with the CPU............................................................. 45
Thumb concept............................................................................................................ 46
Working with ARM exceptions ................................................................................ 46
Exceptions .......................................................................................................... 47
Exception priorities........................................................................................... 48
Exception vector table ...................................................................................... 48
Entering and exiting an exception (software action) ................................... 50
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Entering an exception...............................................................................50
Exiting an Exception.................................................................................50
Exception entry / exit summary.....................................................................51
Notes:..........................................................................................................51
Hardware interrupts.........................................................................................52
The FIRQ and IRQ Lines..........................................................................52
Read-only registers...................................................................................53
Interrupt sources................ ...... ..... ....................... ...... ...................... .........53
Chapter 5: BBus Module.....................................................................................55
BBus functionality .......................................................................................................56
Cycles and BBus arbitration...................... ..... ...... ....................... ..... ....................... ...56
Order of arbitration...........................................................................................56
Address decoding........................................................................................................57
Chapter 6: The GEN Module...........................................................................59
Module configuration.................................................................................................60
A note about interrupts............................................................................60
GEN module hardware initialization.......................................................................61
NET+50 chip bootstrap initialization .............................................................61
System registers...........................................................................................................63
System Control register....................................................................................63
System Status register.......................................................................................67
PLL.................................................................................................................................69
Timing Registers............ ...... ....................... ..... ....................... ...................... ...............69
Software Service register..................................................................................70
Timer Control registers.....................................................................................71
Timer Status register.........................................................................................72
General Purpose I/O (GPIO) Registers....................................................................73
PORTA Register.................................................................................................74
General purpose I/O................................................................................75
Special function mode.................. ...... ...... ...................... ....................... ...75
PORTA register and bit definitions........................................................78
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PORTB Register................................................................................................. 79
General purpose I/O ............................................................................... 81
Special function mode ................ ...... ...................... ....................... .......... 81
PORTB register and bit definitions........................................................ 84
PORTC register.................................................................................................. 86
General purpose I/O ............................................................................... 87
Special function mode ................ ...... ...................... ....................... .......... 87
PORTC register and bit definitions........................................................ 92
Interrupt generation and control.............................................................................. 93
Interrupt Control register and bit definition............. ..... ...... ................ 94
NET+50 internal clock generation............................................................................ 96
System clock generation................................................................................... 97
System clock frequency definitions....................................................... 98
Internal XTAL clock reference............ ...... ..... ....................... ..... ...................... 99
Internal XTAL clock frequency definitions .......................... ................ 99
Crystals and crystal oscillators............................................................. 100
Reset circuit................................................................................................................ 101
Powerup reset.................................................................................................. 101
External reset ................................................................................................... 102
Watch-Dog reset.............................................................................................. 102
ENI reset........................................................................................................... 102
Software reset .................................................................................................. 102
Reset conditions .............................................................................................. 103
PLLTest Mode............................................................................................................ 103
Chapter 7: Cache.................................................................................................... 107
CBUS and BBus system buses................................................................................. 108
BIU and cache controller................................................................................ 108
Cache...........................................................................................................................109
Cache control registers................................................................................... 110
Cache operation............................................................................................... 110
Cache line fill ................................................................................................... 110
Cache line replacement .................................................................................. 111
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Cache line locking ...........................................................................................111
32-bit pre-fetch.................................................................................................111
Cache initialization..........................................................................................111
Cache Control registers ............................................................................................112
Register and bit definitions............................................................................112
Cache RAM.................................................................................................................114
Cache TAG format.....................................................................................................115
Cache TAG format and definitions...............................................................116
Chapter 8: Memory Controller Module................................................119
MEM module features..............................................................................................120
Memory control signals..................................................................................120
Configuration registers.............................................................................................121
Registers............................................................................................................121
Memory Module Control register (MMCR)................................................122
Memory Module Control register and bit definitions.......................123
Chip Select Base Address register and bit definitions.......................126
Chip Select Option register and bit definitions..................................130
Chip Select Option Register B and bit definitions .............................134
Memory control signals............................................................................................134
Data bus (D31:0) ..............................................................................................135
Peripheral devices...................................................................................135
Address bus (A27:0)........................................................................................1 35
Chip selects/RAS (CSx*/RAS).................. ...... ...................... ....................... .136
Setting the Chip Select address range ..........................................................136
Memory space.........................................................................................138
CS0* boot configuration......................................... ...... ...................... .............139
Column address strobes (CAS) .....................................................................140
Read/Write (R/W*)........................................................................................1 41
Output enable (OE*)........................................................................................141
Write enable (WE*)..........................................................................................141
Byte enable (BEx*)...........................................................................................1 41
Transfer Acknowledge (TA*).........................................................................142
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Transfer Error Acknowledge (TEA*) ........................................................... 143
Basic configurations.................................................................................................. 143
Static RAM ....................................................................................................... 144
Configuring a chip select for SRAM.................................................... 144
Fast page and EDO DRAM............................................................................ 145
Configuring a chip select for FP or EDO DRAM............................... 147
External multiplex RAS/CAS addressing.......................................... 148
DRAM Mode-0 addressing........................................................... ........ 149
DRAM Mode-1 multiplexing...................... ...... ..... ....................... ........ 152
SDRAM............................................................................................................. 155
Load-Mode procedure: Setting up the Load-Mode command........ 155
Mode-1 SDRAM multiplexing.............................................................. 160
SDRAM command codes ...................................................................... 161
SDRAM command descriptions........................................................... 161
A10/AP Signal........................................................................................ 163
NET+50 chip SDRAM interconnect........................................................................ 164
SDRAM x16 bursting considerations........................................................... 164
x32 SDRAM configuration............................................................................. 164
x16 SDRAM configuration............................................................................. 166
WAIT configuration.................................................................................................. 167
Burst terminate solution........................................................................................... 168
Option1 .................................................................................................... 168
Option 2 ................................................................................................... 169
Chapter 9: DMA Controller Module....................................................... 173
DMA transfers........................................................................................................... 174
Fly-by operation.............................................................................................. 174
Memory-to-memory operat ion...................................... ....................... ........ 174
DMA module............................................................................................................. 175
DMA controller assignments................................................................................... 176
DMA Channel.................................................................................................. 178
DMA buffer descriptor............................................................................................. 179
Source buffer pointer...................................................................................... 182
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Buffer length.....................................................................................................182
Peripheral-to-memory............................................................................182
Memory-to-peripheral ...........................................................................182
Memory-to-memory...............................................................................182
Destination address pointer...........................................................................183
DMA channel configuration....................................................................................183
DMA registers............................................................................................................185
DMA buffer descriptor pointer.....................................................................186
DMA Control register and bit definition .....................................................186
DMA Status/Interrupt Enable register and bit definition ........................191
Ethernet receiver considerations................... ...... ....................... ..... ....................... .193
External peripheral DMA support..........................................................................194
Signal description............................................................................................194
External DMA configuration.........................................................................196
Fly-by mode .....................................................................................................197
Fly-by write..............................................................................................197
Fly-by read...............................................................................................198
Memory-to-memory mode .................. ...... ...... ...................... ....................... .198
DMA controller reset ................................................................................................199
Chapter 10: Ethernet Controller Module...........................................201
Ethernet (EFE) front-end module.................. ...... ....................... ...................... .......202
Media access controller (MAC) module.................................................................203
Ethernet controller configuration............. ...................... ...... ...................... .............204
Ethernet Registers................ ....................... ...................... ....................... ..................206
Ethernet General Control register and bit definitions ...............................2 07
Media control (ENDEC mode only).....................................................211
Ethernet General Status register and bit definitions..................................212
Media status bits (ENDEC mode only) ...............................................215
Ethernet FIFO Data register.............................................. ..... ....................... .216
Writing to the Ethernet FIFO Data register.........................................2 16
Reading from the Ethernet FIFO Data register ..................................217
Ethernet Transmit Status register and bit definitions................................217
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Ethernet Receive Status register and bit definitions.................................. 220
MAC registers............................................................................................................ 223
MAC Configuration register and bit definitions........................................ 223
MAC Test register and bit definitions .......................................................... 225
PCS registers.............................................................................................................. 226
PCS Configuration register and bit definitions .......................................... 226
PCS Test register ............................................................................................. 228
STL registers............................................................................................................... 228
STL Configuration register and bit definitions........................................... 229
STL Test register and bit definitions ............................................................ 230
Transmit Control registers....................................................................................... 231
Inter-Packet Gap (IPG) registers................................................................... 231
Back-to-Back IPG Gap Timer register.................................................. 231
Non Back-to-Back IPG Gap Timer register......................................... 233
Collision Window/Collision Retry register................................................ 238
“Simulation” registers.................................................................................... 239
Transmit Packet Nibble Counter (PCNT)........................................... 239
Transmit Byte Counter register (TBCT).............................................. 239
Retransmit Byte Counter register (RETX)........................................... 240
Transmit Random Number Generator (RNG)................................... 240
Transmit Masked Random Number (MRNG)................................... 240
Transmit Counter Decodes (ECTDC).................................................. 241
Test Operate Transmit Counters (TECTCL)....................................... 241
Receive Control registers ......................................................................................... 242
Receive Byte Counter (RBCT) ....................................................................... 242
Receive Counter Decodes (ECRDC)............................................................. 242
Test Operate Receive Counters (RECTCL).................................................. 243
PCS Control registers................................................................................................ 244
Link Fail Counter (LFCT)............................................................................... 244
10 MB Jabber Counter (JBCT)........................................................................ 244
10 MB Loss of Carrier Counter (DTLB) ....................................................... 245
Ethernet MII interface signals ................................................................................. 246
MII Control registers................................................................................................. 248
MII Command register and bit definitions ................................................. 248
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MII Address register and bit definitions......................................................249
MII Write Data register and bit definition...................................................249
MII Read Data register and bit definition....................................................250
MII Indicators register and bit definitions...................................................2 50
Statistics monitoring .................................................................................................2 51
Error Statistics registers..................................................................................252
Station Address registers/multicast hash table................. ...... ..... ....................... .254
Station Address Filter register and bit definitions .....................................255
Station Address register and bit definitions................................................256
Multicast hash table entries and bit definitions..........................................257
Calculating hash table entries...............................................................259
Chapter 11: Serial Controller Module..................................................263
Bit-rate generator.......................................................................................................266
Serial protocols...........................................................................................................266
UART mode .....................................................................................................266
HDLC mode................................ ...... ...................... ....................... ..................267
Bit-stuffing...............................................................................................268
Layer 2 frame...........................................................................................268
Layer 3 frame...........................................................................................269
Error detection.........................................................................................269
SPI Mode...........................................................................................................2 69
FIFO management ..................................................................................270
Transmit FIFO interface.........................................................................271
Receive FIFO interface ...........................................................................272
SPI master mode.....................................................................................273
SPI slave mode........................................................................................2 77
General purpose I/O configurations......................................................................280
Serial port performance............................................................................................283
Configuration.............................................................................................................284
Serial controller register diagrams..........................................................................285
Legend......................................................................................................285
Serial Channel registers............................................................................................290
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Serial Channel Control Register A................................................................ 291
Serial Channel Control Register B................................................................ 295
Serial Channel Status Register A .................. ...... ...................... .................... 300
Serial Channel Bit-Rate registers................................................................... 308
Serial Channel Bit-Rate register............................................................ 309
Serial Channel FIFO registers....... ....................... ...................... ...... .............. 314
Receive Gap Timer registers.................................................................................... 314
Receive Buffer Timer register and bit definitions ...................................... 316
HDLC mode................................. ....................... ...................... .............. 316
Receive Character Timer register and bit definitions................................ 317
Receive Match registers............................................................................................ 318
Receive Match register and bit definitions.................................................. 318
Receive Match MASK register and bit definitions..................................... 319
Control Register C (HDLC) ................................ ...................... ....................... ..... ... 320
Status Register B (HDLC)......................................................................................... 321
Status Register B and bit definitions ............................................................ 322
Status Register C (HDLC)........................................................................................ 325
Status Register C and bit definitions............................................................ 325
FIFO Data Register LAST (HDLC) ......................................................................... 326
Chapter 12: MIC Controller Module...................................................... 329
MIC controller modes of operation........................................................................ 330
MIC modes of operation ................................................................................ 331
MIC controller configuration ........................................................................ 332
MIC module interrupts .................................................................................. 333
MIC module hardware initialization ........................................................... 333
GPIO mode................................................................................................................. 334
GPIO function configurations....................................................................... 335
Functions ................................................................................................. 337
Examples using PORTF .................................................................................. 337
PORTD register ............................................................................................... 339
General purpose I/O ............................................................................. 339
Interrupt Mode ...................... ...... ....................... ...................... .............. 340
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PORTD registers and bit definitions....................................................340
PORTF register.................................. ...................... ....................... ..................342
General purpose I/O mode...................................................................3 42
Interrupt mode................... ...... ..... ....................... ...................... ...... .......342
PORTF register and bit definitions ......................................................343
PORTG register................................................................................................345
General purpose I/O..............................................................................345
Interrupt mode................... ...... ..... ....................... ...................... ...... .......345
PORTG register and bit definitio ns......................................................346
PORTH register................................. ...................... ....................... ..................347
General purpose I/O mode...................................................................3 47
Interrupt mode................... ...... ..... ....................... ...................... ...... .......348
PORTH register and bit definitions .....................................................349
IEEE 1284 host interface (4-port) module ..............................................................3 50
IEEE 1284 Signals..................... ...................... ....................... ..................352
IEEE 1284 signal cross reference ...................................................................353
IEEE 1284 port multiplexing..........................................................................354
IEEE 1284 mode configuration............................. ....................... ..................354
IEEE negotiation................... ...... ....................... ...................... ...... ..................355
IEEE 1284 forward compatibility mode.......................................................355
Compatibility SLOW mode...................................................................356
Compatibility FAST mode.....................................................................357
IEEE 1284 nibble mode...................................................................................357
IEEE 1284 byte mode ......................................................................................358
IEEE 1284 forward ECP mode.......................................................................359
ECP SLOW mode....................................................................................360
ECP FAST mode......................................................................................360
IEEE 1284 reverse ECP mode.......... ..... ...... ....................... ...................... .......360
IEEE 1284 EPP mode.......................................................................................3 63
EPP data write cycle...............................................................................364
EPP data read cycle ................................................................................364
EPP address write cycle.........................................................................365
EPP address read cycle ..........................................................................3 66
IEEE 1284 Configuration registers................................................................366
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IEEE 1284 Port Control registers and bit definitions ................................. 367
IEEE 1284 Channel Data registers ................................................................ 372
IEEE 1284 strobe pulse width.................................................... .................... 373
IEEE 1284 external loopback mode .............................................................. 374
ENI mode overview.................................................................................................. 374
ENI host interface............................................................................................ 375
Signal descriptions.......................................................................................... 377
ENI shared RAM mode............................................................................................ 382
Memory map ................................................................................................... 383
Shared RAM..................................................................................................... 383
Shared register................................................................................................. 384
ENI Shared register and bit definitions............................................... 386
Clear interrupts .................................... ....................... ...................... .............. 388
Address interrupts.......................................................................................... 389
ENI bus error interrupts........................................................................ 391
ENI FIFO mode module........................................................................................... 391
FIFO Data register........................................................................................... 393
FIFO Mask/Status register and bit definition............................................. 395
FIFO receiver interrupts........................................................................ 398
FIFO transmitter interrupts ................................................................... 399
ENI mode registers ................................................................................................... 400
General Control register and bit definitions............................................... 401
General Status register and bit definitions.................................................. 405
ENI mode FIFO Data register.................................... ..... ....................... ........ 407
ENI Control register and bit definitions...................................................... 408
ENI Pulsed Interrupt register and bit definition........................................ 415
ENI Shared RAM Address register and bit definitions............................. 415
Chapter 13: Timing .............................................................................................. 419
Thermal considerations...................... ...................... ...... ...................... .................... 420
Absolute maximum ratings..................................................................................... 421
DC characteristics...................................................................................................... 421
AC characteristics......... ....................... ...................... ....................... ...................... ... 423
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Output pad timing ..........................................................................................4 23
Clock relationships..........................................................................................425
RESET* timing..................................................................................................425
SRAM timing..............................................................................................................4 26
SRAM Sync Read (WAIT = 2)........................................................................427
SRAM Sync Write (WAIT = 2).......................................................................428
SRAM Sync Burst Read (2-111) (WAIT = 0, BCYC = 00)...........................429
SRAM Sync Burst Read (4-222) (WAIT = 2, BCYC = 01)...........................430
SRAM Sync Burst Write (4-222) (WAIT = 2, BCYC = 01)..........................431
SRAM Async Read (WAIT = 2).....................................................................432
SRAM Async Write (WAIT = 2)....................................................................4 33
SRAM Async Burst Read (WAIT = 2, BCYC = 01) .....................................434
SRAM Async Burst Write (WAIT = 2, BCYC = 01) ....................................435
Fast Page and EDO DRAM Timing ........................................................................4 36
Fast Page and EDO DRAM Read..................................................................437
Fast Page and EDO DRAM Write.................................................................438
Fast Page and EDO DRAM Burst Read........................................................439
Fast Page and EDO DRAM Burst Write.......................................................441
Fast Page and EDO DRAM Refresh (RCYC = 0) ........................................443
Fast Page and EDO DRAM Refresh (RCYC = 1) ........................................443
Fast Page and EDO DRAM Refresh (RCYC = 2) ........................................444
Fast Page and EDO DRAM Refresh (RCYC = 3) ........................................444
SDRAM timing...........................................................................................................445
SDRAM Read (CAS Latency = 1)..................................................................446
SDRAM Read (CAS Latency = 2)..................................................................447
SDRAM Write (CAS Latency = 2).................................................................448
SDRAM Burst Read (CAS Latency = 1)........................................................4 49
SDRAM Burst Read (CAS Latency = 2)........................................................4 50
SDRAM Burst Write (CAS Latency = 2) .......................................................451
SDRAM Refresh Command...........................................................................452
SDRAM Load-Mode Command....................................................................453
External DMA timing ...............................................................................................4 54
External Fly-by DMA......................................................................................455
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External Memory-to-Memory DMA............................................................ 457
SPI timing................................................................................................................... 459
SPI Master mode 0 and 1 (two-byte transfer) ............................................. 459
SPI Slave mode 0 and 1 .................................................................................. 460
MIC timing................................................................................................................. 461
ENI Shared RAM and Register Cycle timing.............................................. 464
ENI Single Direction DMA timing ............................................................... 465
ENI Dual Direction DMA timing.................................................................. 466
Ethernet timing............. ....................... ...................... ....................... ...................... ... 467
Ethernet timing diagram.......... ..... ...... ....................... ...................... .............. 468
Ethernet Receive Clock Idle........................................................................... 468
External Ethernet CAM Filtering.................................................................. 469
JTAG timing............................................................................................................... 469
1284 Port Multiplexing timing ................................................................................ 470
1284 Compatibility mode timing............................................................................ 471
Forward ECP mode timing...................................................................................... 473
Crystal oscillator specifications............................................................................... 474
Appendix A: ARM Exceptions...................................................................... 475
About ARM exceptions................ ...... ..... ....................... ....................................... ... 476
Reset exception................................................................................................ 476
Undefined exception....................................................................................... 476
SWI exception.................................................................................................. 477
Abort exception............................................................................................... 477
IRQ exception .................................................................................................. 478
FIRQ exception................................................................................................ 478
Appendix B: NET+20M Chip Package ................................................... 481
NET+20M chip pinout............ ...... ...... ...................... ....................... ...................... ... 482
Table Information and Tables ....................................................................... 482
System bus interface....................................................................................... 483
Chip select controller.......... ....................... ...................... ...... ...................... ... 486
Ethernet interface................ ....................... ...................... ....................... ........ 486
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UARTS-SPI-GPIO............................................................................................487
Clock generation/system reset......................................................................4 88
JTAG port for ARM core ................................................................................489
Power supply...................................................................................................489
Additional information about NET+20M pins ...........................................490
Signal description summary....................................................................................491
System Bus Interface.......................................................................................491
Chip select controller ................. ...... ..... ....................... ...................... ...... .......492
Ethernet interface ....................... ...... ..... ....................... ...................... .............493
GPIO (PORTA/B/C) ......................................................................................494
Clock generation and reset.............................................................................496
Test support......................................................................................................496
ARM debugger ................................................................................................497
Power ................................................................................................................498
Packaging....................................................................................................................500
Index
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Tables
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Table 1: NET+50 PQFP/BGA Chip Pinout - System bus interface..................... 19
Table 2: NET+50 PQFP/BGA Chip Pinout - Chip select controller.................... 22
Table 3: NET+50 PQFP/BGA Chip Pinout - Ethernet interface.......................... 22
Table 4: NET+50 PQFP/BGA Chip Pinout - MIC interface................................. 23
Table 5: NET+50 PQFP/BGA Chip Pinout - UARTS-SPI-GPIO.......................... 25
Table 6: NET+50 PQFP/BGA Chip Pinout - Clock generation/system reset... 26
Table 7: NET+50 PQFP/BGA Chip Pi nout - JTAG port for ARM core.............. 27
Table 8: NET+50 PQFP/BGA Chip Pinout - Power supply................................. 27
Table 9: System bus interface signal description ................................................... 29
Table 10: Chip select controller signal description................................................ 30
Table 11: Ethernet MII signal description............................................................... 30
Table 12: MIC IEEE 1284 mode signal description................................................ 32
Table 13: ENI host mode signal description................. ...... ...... ..... ....................... .. 33
Table 14: MIC GPIO mode signal description........................................................ 34
Table 15: GPIO PORTA/B/C signal description................................................... 35
Table 16: Clock generation and reset signal description ........ ..... ...... ..... .............. 37
Table 17: Test support signal description ............................................................... 37
Table 18: Power signal description ................................ ...... ...................... .............. 39
Table 19: PQFP dimensions....................................................................................... 41
Table 20: BGA dimensions........................................................................................ 42
Table 21: Exception vector table............................................................................... 49
Table 22: Exception entry/exit ...................... ...... ...... ...................... ...... ................... 51
Table 23: BBus address decoding............................................................................. 57
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Table 24: GEN module address map....................................................................... 60
Table 25: ADDR bits/function control.................................................................... 61
Table 26: GEN module ADDR bit function control .............................................. 62
Table 27: System Control register bit description.................................................. 63
Table 28: System Status register bit description .................................................... 68
Table 29: NET+ARM chip devices and revision IDs............................................. 68
Table 30: Timer Control register bit definition ...................................................... 71
Table 31: Minimum and maximum timer values.................................................. 72
Table 32: Timer Status register bit definition......................................................... 73
Table 33: PORTA configuration............................................................................... 74
Table 34: PORTA register bit definition.................................................................. 79
Table 35: PORTB configuration................................................................................ 80
Table 36: PORTB register bit definition .................................................................. 85
Table 37: PORTC configuration ............................................................................... 86
Table 38: PORTC register bit definition.................................................................. 92
Table 39: Interrupt Control register bit definition................................................. 94
Table 40: Clock generation signal description ..................................................... 100
Table 41: Reset conditions....................................................................................... 103
Table 42: PLL Test Mode Connections.................................... ...... ...................... .. 104
Table 43: POR25 test mode connections ............................................................... 105
Table 44: CCR0/CCR1 register bit definition ...................................................... 112
Table 45: Cache RAM memory addressin g....................................... ................... 115
Table 46: Cache tag bit definitions......................................................................... 116
Table 47: Memory control signal overview.......................................................... 120
Table 48: MEM module configuration registers.................................................. 121
Table 49: Mask settings and related address space............................................. 138
Table 50: CS0* bootstrap settings........................................................................... 139
Table 51: CAS* lane configurations ....................................................................... 140
Table 52: BE* lane configurations .......................................................................... 142
Table 53: Peripheral cycle termination.................................................................. 143
Table 54: DRAM Mode-0 addressing.................................................................... 151
Table 55: DRAM Mode-1 addressing.................................................................... 154
Table 56: SDRAM (Mode-1) addressing ............................................................... 160
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Table 57: X32 SDRAM configuration..................................................................... 164
Table 58: X16 SDRAM configuration..................................................................... 166
Table 59: DMA IEEE 1284 mode channel assignments....................................... 176
Table 60: DMA MIC mode channel assignments ................................................ 177
Table 61: DMA Buffer Bit Descriptions................................................................. 181
Table 62: DMA channel configuration ............... ....................... ...................... ...... 183
Table 63: DMA Control register bit definition ..................................................... 187
Table 64: DMA Status/Interrupt Enable register bit definition ........................ 191
Table 65: External peripheral DMA support signal descriptions...................... 195
Table 66: DMA channel signals...................................... ....................... ................. 196
Table 67: Ethernet controller configuration.......................................................... 204
Table 68: Ethernet General Control register bit definition ................................. 208
Table 69: ENDEC mode media control bits.......................................................... 211
Table 70: Ethernet General Status register bit definition.................................... 213
Table 71: ENDEC mode media status bits............................................................ 215
Table 72: Ethernet Transmit Status register bit definition.................................. 217
Table 73: Ethernet Receive Status register bit definition .................................... 220
Table 74: MAC Configuration register bit definition.......................................... 223
Table 75: PCS Configuration register bit definition ............................................ 226
Table 76: STL Configuration register bit definition............................................. 229
Table 77: Collision Window/Collision Retry register bit definition ................. 238
Table 78: MII interface signals ................................................................................ 246
Table 79: MII Command register bit definition.................................................... 248
Table 80: MII Address register bit definition ....................................................... 249
Table 81: MII Indicators register bit definition..................................................... 251
Table 82: Station Address FIlter register bit definition....................................... 255
Table 83: Station Address register bit definition.................................................. 257
Table 84: Multicast hash table bit definition......................................................... 258
Table 85: SPI master mode channel A/B configuration ..................................... 274
Table 86: SPI slave mode channel A/B configuration ........................................ 278
Table 87: PORTA/B/C assignments for NMSI mode......................................... 281
Table 88: PORTA/B/C assignments for SPI slave mode ................................... 282
Table 89: PORTA/B/C assignments for SPI master mode ................................ 282
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xxii n n n n n n n
Table 90: Serial channel configuration registers.................................................. 284
Table 91: Serial Channel Control Register A bit definition................................ 291
Table 92: Interrupt enable bit definition - receiver.............................................. 293
Table 93: Interrupt enable bit definition - transmitter........................................ 294
Table 94: Serial Channel Control Register B bit definition................................. 295
Table 95: Serial Channel Status Register A bit definition................................... 301
Table 96: Serial Channel Bit-Rate register bit definition..................................... 309
Table 97: Bit-rate examples..................................................................................... 313
Table 98: Receive Buffer Timer register bit definition ........................................ 316
Table 99: Receive Character Timer register bit definition.................................. 317
Table 100: Receive Match register bit definition.................................................. 319
Table 101: Receive Match MASK register bit definition..................................... 319
Table 102: Control Register C (HDLC) bit definition.......................................... 320
Table 103: Status Register B (HDLC) bit definition............................................. 322
Table 104: Status Register C (HDLC) bit definition ............................................ 326
Table 105: MIC mode settings ................................................................................ 331
Table 106: MIC configurations............................................................................... 332
Table 107: MIC controller configuration registers............................................... 332
Table 108: MIC interrupt sources........................................................................... 333
Table 109: Address bit functionality...................................................................... 334
Table 110: PORTD/F/G/H PQFP/BGA pin assignments ................................ 335
Table 111: PORTD configuration........................................................................... 336
Table 112: PORTF/G/H configuration................................................................. 336
Table 113: GPIO PORTD register bit definition................................................... 341
Table 114: PORTF pin/mode/dir configuration................................................. 343
Table 115: GPIO PORTF register bit definition.................................................... 344
Table 116: PORTG pin/mode/dir configuration ................................................ 346
Table 117: GPIO PORTG register bit definition................................................... 347
Table 118: PORTH pin/mode/dir configuration................................................ 348
Table 119: GPIO PORTH register bit definition................................................... 349
Table 120: IEEE 1284 data bus assignments......................................................... 351
Table 121: 1284 signal cross reference................................................................... 354
Table 122: IEEE 1284 mode configuration............................................................ 355
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n n n n n n n xxiii
Table 123: IEEE 1284 registers ................................................................................ 366
Table 124: IEEE 1284 Port Control register bit definition................................... 367
Table 125: IEEE 1284 Channel Data register bit definition................................. 373
Table 126: Sample IEEE 1284 strobe widths ......................................................... 374
Table 127: ENI interface address map................................................................... 383
Table 128: Shared register layout (ENI interface perspective only).................. 385
Table 129: ENI Shared register bit definition ....................................................... 386
Table 130: ENI interface address map................................................................... 389
Table 131: FIFO Mask/Status register bit definition........................................... 396
Table 132: ENI controller configuration registers................................................ 400
Table 133: General Control register bit definition ............................................... 401
Table 134: General Status register bit definition.................................................. 406
Table 135: ENI Control register and bit definition .............................................. 409
Table 136: ENI Shared RAM Address register bit definition............................. 416
Table 137: Thermal considerations......................................................................... 420
Table 138: Maximum voltage ratings .................................................................... 421
Tabl e 139: D C charac t eristics — Inputs................................................................. 421
Tabl e 140: D C charac t eristics — Outputs.............................................................. 422
Table 141: Output load-dependent delay factors................................................. 424
Table 142: Operating frequencies........................................................................... 425
Table 143: RESET timing values............................................................................. 425
Table 144: SRAM timing characteristics................................................................ 426
Table 145: Fast Page/EDO tim ing characteristics................................................ 436
Table 146: SDRAM timing values .......................................................................... 445
Table 147: External DMA timing values ............................................................... 454
Table 148: SPI Master mode 0 and 1 timing values............................................. 459
Table 149: SPI Slave mode timing values.............................................................. 460
Table 150: MIC timing values................................................................................. 461
Table 151: Ethernet timing values.......................................................................... 467
Table 152: JTAG timing values............................................................................... 469
Table 153: 1284 Port Multiplexin g timing values................................................. 470
Table 154: 1284 Compatibility SLOW mode timing (FAST = 0)........................ 471
Table 155: 1284 Compatibility FAST mode timing (FAST = 1).......................... 472
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Table 156: 1284 SLOW Forward ECP mode timing (FAST = 0) ........................ 473
Table 157: 1284 FAST Forward ECP mode timing (FAST = 1).......................... 473
Table 158: Crystal specification.............................................................................. 474
Table 159: NET+20M BGA Chip Pinout - System bus interface........................ 483
Table 160: NET+20M BGA Chip Pinout - Chip select controller ...................... 486
Table 161: NET+20M BGA Chip Pinout - Ethernet interface............................. 486
Table 162: NET+20M BGA Pinout - UARTS-SPI-GPIO...................................... 487
Table 163: NET+20M BGA Chip Pinout - Clock generation/system reset...... 488
Table 164: NET+20M BGA Chip Pinout - JTAG port for ARM core ................ 489
Table 165: NET+20M BGA Chip Pinout - Power supply ................................... 489
Table 166: System bus interface signal description............................................. 491
Table 167: Chip select controller signal description............................................ 492
Table 168: Ethernet MII signal description........................................................... 493
Table 169: Clock generation and reset signal description.................................. 496
Table 170: Test support signal description........................................ ...... ............. 496
Table 171: Power signal description...................................................................... 498
Table 172: BGA dimensions.................................................................................... 500
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Figures
n n n n n n n xxv
Figure 1: NET+50 device modules............................................................................. 3
Figure 2: NET+20M device modules......................................................................... 4
Figure 3: NET+50 PQFP pinout................................................................................ 17
Figure 4: NET+50 BGA pinout ................................................................................. 18
Figure 5: NET+50/20M reset and ARM debugger circuit.................................... 38
Figure 6: Short plastic quad flat pack (PQFP) ........................................................ 40
Figure 7: BGA package .............................................................................................. 42
Figure 8: NET+50 chip clock generation................................................................. 97
Figure 9: NET+50 CPU core block diagram ......................................................... 108
Figure 10: 4-way associated cache.......................................................................... 109
Figure 11: A27_F functionality ............................................................................... 125
Figure 12: A26F functionality ................................................................................. 125
Figure 13: SRAM chip select configuration .......................................................... 144
Figure 14: External DRAM multiplexer chip select configuration.................... 146
Figure 15: DRAM Mode-0 addressing................................................................... 150
Figure 16: DRAM Mode-1 addressing................................................................... 153
Figure 17: SDRAM (Mode-1) addressing.............................................................. 159
Figure 18: Option 1................................................................................................... 169
Figure 19: Option 2................................................................................................... 170
Figure 20: DMA fly-by transfers............................................................................. 174
Figure 21: DMA memory-to-memory transfer..................................................... 175
Figure 22: DMA channel block diagram............................................................... 175
Figure 23: DMA channel structure......................................................................... 179
Figure 24: DMA buffer descriptor — Fly-by-mode...................... ....................... 180
Figure 25: DMA buffer descriptor — Memory-to-memory mode .................... 180
Figure 26: DMA Buffer descriptor structure ........................................................ 183
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Figure 27: External DMA timing............................................................................ 194
Figure 28: Hardware needed for external fly-by DMA transfers...................... 197
Figure 29: Hardware needed for external memory-to-memory DMA
transfers..................................................................................................................... 199
Figure 30: Ethernet controller module block diagram........................................ 202
Figure 31: Serial port block diagram..................................................................... 265
Figure 32: SPI mode/GPIO signal relationships ................................................. 283
Figure 33: Serial Controller registers — 1............................... ....................... ....... 286
Figure 34: Serial controller registers — 2...................................... ...................... .. 287
Figure 35: Serial controller registers — 3...................................... ...................... .. 288
Figure 36: Serial controller registers — 4...................................... ...................... .. 289
Figure 37: Data coding example............................................................................. 300
Figure 38: Serial channel X1 timing....................................................................... 308
Figure 39: MIC controller high-level block diagram........................................... 330
Figure 40: IEEE 1284 external transceivers........................................ ................... 351
Figure 41: IEEE 1284 host controller block diagram ........................................... 353
Figure 42: Nibble mode cycle................................................................................. 357
Figure 43: Byte mode cycle ..................................................................................... 358
Figure 44: ECP reverse mode timing..................................................................... 362
Figure 45: EPP data write cycle.............................................................................. 364
Figure 46: EPP data read cycle............................................................................... 364
Figure 47: EPP address write cycle........................................................................ 365
Figure 48: EPP address read cycle......................................................................... 366
Figure 49: ENI basic functionality ................................ ...... ...................... ...... ....... 375
Figure 50: NET+50 ENI host signals...................................................................... 376
Figure 51: ENI shared RAM block diagram................................. ...................... .. 382
Figure 52: Writing to the ENI shared register...................................................... 385
Figure 53: PINT1*/PINT2* interrupt pins............................................................ 390
Figure 54: ENI bus error interrupt process........................................................... 391
Figure 55: ENI FIFO mode block diagram ........................................................... 392
Figure 56: Sample application............................................. ...................... ............. 393
Figure 57: ENI FIFO — Transporting data through DMA channels................ 394
Figure 58: ENI receive FIFO interrupt process .................................................... 399
Figure 59: ENI transmit FIFO interrupt process.................................................. 400
Figure 60: RESET* timing........................................................................................ 425
Figure 61: SRAM Synchronous Read (WAIT = 2) ............................................... 427
Figure 62: SRAM Synchronous Write (WAIT = 2) .............................................. 428
Figur e 63: SR AM Synchronous Burs t Read ( 2-111) (WAI T = 0, BCYC = 00)... 429
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Figure 64: SRAM Synchronous Burst Read (4-222) (WAIT = 2, BCYC = 01)... 430
Figure 65: SRAM Synchronous Burst Write (4-222) (WAIT = 2, BCYC = 01).. 431
Figure 66: SRAM Asynchronous Read (WAIT = 2)............................................. 432
Figure 67: SRAM Asynchronous Write (WAIT = 2)............................................ 433
Figure 68: SRAM Asynchronous Burst Read (WAIT = 2, BCYC = 01) ............. 434
Figure 69: SRAM Asynchronous Burst Write (WAIT = 2, BCYC = 01) ............ 435
Figure 70: Fast Page and EDO DRAM Read......................................................... 437
Figure 71: Fast Page and EDO DRAM Write........................................................ 438
Figure 72: Fast Page and EDO DRAM Burst Read.............................................. 439
Figure 73: Fast Page and EDO DRAM Burst Write............................................. 441
Figure 74: Fast Page and EDO DRAM Refresh (RCYC = 0)............................... 443
Figure 75: Fast Page and EDO DRAM Refresh (RCYC = 1)............................... 443
Figure 76: Fast Page and EDO DRAM Refresh (RCYC = 2)............................... 444
Figure 77: Fast Page and EDO DRAM Refresh (RCYC = 3)............................... 444
Figure 78: SDRAM Read (CAS Latency = 1)......................................................... 446
Figure 79: SDRAM Read (CAS Latency = 2)......................................................... 447
Figure 80: SDRAM Write (CAS Latency = 2)........................................................ 448
Figure 81: SDRAM Burst Read (CAS Latency = 1).............................................. 449
Figure 82: SDRAM Burst Read (CAS Latency = 2).............................................. 450
Figure 83: SDRAM Burst Write (CAS Latency = 2)............................................. 451
Figure 84: SDRAM Refresh..................................................................................... 452
Figure 85: SDRAM Load Mode Command .......................................................... 453
Figure 86: External Fly-by DMA ............................................................................ 455
Figure 87: External Memory-to-Memory DMA................................................... 457
Figure 88: SPI Master mode 0 and 1 (two-byte transfer).................................... 460
Figure 89: SPI Slave mode 0 and 1 (two-byte transfer)....................................... 461
Figure 90: ENI Shared RAM and Register Cycle timing..................................... 464
Figure 91: ENI Single Direction DMA timing...................................................... 465
Figure 92: ENI Dual Direction DMA timing ................ ....................... ................. 466
Figure 93: Ethernet timing....................................................................................... 468
Figure 94: Ethernet Receive Clock Idle.................................................................. 468
Figure 95: External Ethernet CAM Filtering......................................................... 469
Figure 96: JTAG timing....... ....................... ...................... ...... ...................... ............ 470
Figure 97: 1284 Port Multiplexing timing............................................................. 471
Figure 98: 1284 Compatibility mode timing......................................................... 472
Figure 99: 1284 Forward ECP mode timing.......................................................... 473
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Figure 100: NET+20M BGA pinout (bottom view)............................................. 482
Figure 101: NET+50/20M reset and ARM debugger circuit ............................. 498
Figure 102: BGA package........................................................................................ 500
net50_20_1.book Page xxviii Friday, September 19, 2003 10:41 AM
Using This Guide
n n n n n n n xxix
Review this section for basic information about the guide you are using, as well as
general support and contact information.
About this guide
This guide provides inf or mation about the NetSilicon NET+50 and NET+20M 32-bit
networked microprocessors. The NET+50 and NET+20M are part of the NetSilicon
NET+ARM line of SoC (System-on-Chip) products, and support any type of high-
bandwidth applications in Intelligent Networked Devices.
The NET+ARM chip is part of the NET+Works integrated product family, which includes
the NET+OS network software suite.
Who should read this guide
This guide is for hardw are developers, system soft ware developers, and applications
programm ers who want to use the NET+50 or NET+20M for development.
To complete the tasks described in this guide, you must:
Understan d the basics o f hardware an d soft ware design, operati ng systems, and
microprocessor design.
Understand the NET+50/20M architecture.
Using This Guide
net50_20_1.book Page xxix Friday, September 19, 2003 10:41 AM
What’s in this guide
xxx n n n n n n n
NET+50/20M Hardware Reference
What’s in this guide
This table shows where you can find specific information in this guide:
Conventions used in this guide
This table describes the typographic conventions used in this guide:
To read about See
Similarities and differences between the NET+50 chi p and
the 20M chip Chapter 1, "About the NET+50 chip and
NET+20M chip"
NET+50 chip and NET+20M chip key features Chapter 2, "NET+50/20M Chip Features"
NET+50 PQFP/BGA pin/ball grid array assignments and
packaging Chapter 3, "NET+50 Chip Package"
NET+50/20M CPU and the ARM Thumb concept Chapter 4, "Working with the CPU"
BBus functionality Chapter 5, "BBus Module"
General (GEN) module functionality Chapter 6, "The GEN Module"
ARM7TDMI stand-alone core and instruct ion/data cache,
write protection, and pre-fetch control
Note: This information applies to the NET+50 chip only.
Chapter 7, "Cache"
How the NET+50/20M can be configured to interface with
different types of memory devices Chapter 8, "Memory Controller Module"
DMA controller, supported DMA channels, and internal
and externalDMA transfers Chapter 9, "DMA Controller Module"
Ethernet controller module Chapter 10, "Ethernet Controller Module"
Serial channel A and serial channel B Chapter 11, "Serial Controller Module"
Multi interface controller (MIC)
Note: This information applies to the NET+50 chip only Chapter 12, "MIC Controller Module"
NET+50/20M timing information and diagrams Chapter 13, "Timing"
ARM exceptions Appendix A, "ARM Exceptions"
NET+20M BGA (ball grid array) assignments and
packaging Appendix B, "NET+20M Chip Package"
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n n n n n n n xxxi
Using This Guide
Related documentation
NET+50/20M Jumpers and Components provides a hardwa re description of
the NET+Works Development Board, and includes information about
jumpers, connectors, switches, and interface configuration as well as
development board diagrams.
Review the documentation CD-ROM that came with your development kit for
info r mation on thi rd-par ty pro ducts and ot her components.
Refer to the NET+OS software d ocumentation for information appropriate to
the chip you are using.
Customer support
To get help with a question or technical problem with this product, or to make comments
and recommendations about our products or documentation, use the contact information
listed in the following tables:
NetSilicon support
This convention Is used for
italic type Empha sis, new terms, variables, and document titles.
PRQRVSDFHGW\SH Filenames, pathnames, and code examples.
For Contact information
Technical support Telephone: 1 800 243-2333/ 1 781 647-1234
Fax: 1 781 893-1388
Email: tech_support@netsilicon.com
Documentation techpubs@netsilicon.com
NetSilicon home page www.netsilicon.com
Online problem reporting www.netsilicon.com/problemreporting.jsp
net50_20_1.book Page xxxi Friday, September 19, 2003 10:41 AM
Customer support
xxxii n n n n n n n
NET+50/20M Hardware Reference
Digi support
For Contact information
Technical support Telephone: 1 877 912-3444 / 1 952 912-3456
Fax: 1 952 912-4960
Documentation techpubs@digi.com
Digi home page www.digi.com/support/eservice/eservicelogin.jsp
Online problem reporting www.digi.com/problemreporting.jsp
net50_20_1.book Page xxxii Friday, September 19, 2003 10:41 AM
n n n n n n n 1
About the NET+50 chip and
NET+20M chip
CHAPTER 1
NetSilicon offers two versions of its system-on-a-chip ASIC that is designed for
use in intelligent network devices and Internet appliance s:
NET+50 chip. Consists of a 208 plastic-quad-flat-pack (PQFP) package
and a 208 ball-grid-array (BGA) package. The NET+50 is a high-
performance, highly-integrated 32-bit chip.
NET+20M chip. Consists of a 208 BGA packag e only. The NET+20M is a
cost-effective, highly-integrated 32-bit chip.
net50_20_1.book Page 1 Friday, September 19, 2003 10:41 AM
Introduction
2 n n n n n n n
NET+50/20M Hardware Reference
Introduction
The NET+50 and NET+20M chips support almost any networking scenario, with a
10/100 BaseT Ethernet MAC with MII interface and two independent serial ports,
each of which can run in UAR T, HDLC, or SPI modes. The CPU is an ARM7TDMI
32-bit RISC processor core with a rich complement of support peripherals,
including memory controllers for various types of memory (including flash,
SDRAM , and EEPROM), prog rammable timers, and a 10-c hannel DMA controller.
The NET+50 and NET+20M provide all tools required for any embedded
networking application.
ARM7TDMI
The heart of the NET+50/NET+20M hardware is provided by the ARM7TDMI.
The ARM7TDMI is a member of the ARM Ltd. family of general purpose 32-bit
microprocessors, which offer high-performance while maintaining very low
power-consumption and size.
The ARM architecture is based on Reduced Instruction Set Computer (RISC)
princ i pl es. Compared wit h Comp l ex In st ru ction Set Co mp u ter s (C I SC)
architecture, the RISC instruction set, and related decoding and exe cution
mechanisms , is simpler and more streamlined. This simplicity results in a high
instruction throughput and impressive real-time interrupt r esponse, as well as a
small, cost-effective circuit. The RISC architecture is conducive to pipelining,
which allows the instruction fetch, decode, and execution units to operate
simultaneously.
NET+50 chip
The NET+50 chip can be used in any embedded environment requiring
networking services in an Ethernet LAN. The NET+50 contains an ARM RISC
processor, 10/100 Ethernet MAC, serial ports, IEEE 1284 parallel ports , memory
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n n n n n n n 3
About the NET+50 chip and NET+20M chip
controllers, and parallel I/O. The NET+50 chip can interface with another
processor using a RAM or shared RAM interface.
Hardware design
The NET+50 chip can attach to another processor using the 1284, ENI shared
RAM, or ENI FIFO interfaces. Application-specific hardware can be attached to the
NET+50 system bus for custom applications that use the NET+50 internal RISC
processor.
Device modules
Figure 1 is an overview of the modules that make up the NET+50 device.
Figure 1: NET+50 device modul es
Interrupt
controller
Clo ck PLL
test
Serial
module Memory
controller BBus
controller
IEEE 1284,
64K s hared
RAM
or
GPI O
MIC
DMA
DMA
DMA
DMA
Ethernet
controller
EFE
ARM7
co re with
8K cach e
or
16K
SRAM
CPU Timer
module General
pu rpose I/O
BBus
arbit er
24 pins
40 pins
18 pins GEN
12 pins 11 pins 70 pins
SYS
SER MEM BUS
BBus
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NET+20M chip
4 n n n n n n n
NET+50/20M Hardware Reference
NET+20M chip
The NET+20M chip can be used in any embedded environment requiring
networking services in an Ethernet LAN. The NET+20M chip contains an
integrated ARM RISC processor, 10/100 Ethernet MAC, serial ports, memory
controllers, and parallel I/O. The NET+20M chip can interface with another
processor using a register or shared RAM interface.
Hardware design
Application- spe cif ic hardware can be attach ed to the NET+ 50 sy stem bus fo r
custom applications that use the NET+50 internal RISC processor.
Device modules
Figure 2 provides an overview of the modules that make up the NET+20 device.
Figure 2: N ET+20M device modules
Interrupt
controller
Clo ck PL L
test
Serial
module Memory
controller BBus
controller
DMA
Ethernet
controller
EFE
ARM7
core
CPU Timer
module General
pu rpo s e I/ O
BBus
arbiter
16 pins
18 pins GEN
12 pins 11 pins 70 pins
SYS
SER MEM BUS
BBus
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n n n n n n n 5
About the NET+50 chip and NET+20M chip
Differences between the NET+50 and NET+20M chips
Although the NET+50 and NET+20M chips are similar in many aspects, there are
several significant differences:
Cache support
Multi interface controller support
GPIO PORTA/B/C pin availability and assignments
Pin support
Pinout and features
Cache support
The NET+20M does not support cache.
If you ar e using the NET+20M chip, you can ignore Chapter 7, "Cache."
Multi Interface Controller support
The NET+20 M does not support the multi interface controller (MIC) module. This
module contains IEEE 1284 and ENI interface information.
If you are using the NET+20M chip, you can ignore Chapter 12, "MIC Controller
Module."
GPIO PORTA/B/C pin availability and assignments
The GP I O PORTA/B/C registe rs contai n ei g h t pi ns each, eac h of which c an be
configured in general purpose inpu t mode , general purpose output mode, special
function input mode, and special function output mode. The NET+50 chip allows
use of all 24 pins. The NET+20M chip, however, allows use of only 16 pins. This
differenc e is no t ed in "Gen er a l Pu r p ose I/O (GP I O) Regist er s," begi n ni ng on page
73, in Chapter 6, "The GEN Module."
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Differences between the NET+50 and NET+20M chips
6 n n n n n n n
NET+50/20M Hardware Reference
Pin support
The NET+50 chip supports up to 40 general-purpose I/O pins and 16 general-
purpose input pins.
The NET+20M chip supports 16 general purpose input pins.
Pinout and features
Pinout and packaging
The pin/ball grid assignments and packaging for the NET+50 chip differs fr om the
NET+20M chip. To make it easier to find chip-specific information for these items,
separate chapters have been created for each chip:
Chapter 3, "NET+50 Chip Package," beginning on page 15, contains
pin/ball grid array assignments and package information for the
NET+50 chip.
Appendix B, "NET+20M Chip Package," beginning on page 481,
contains ball grid array assignments and package information for the
NET+20M chip.
Features
The chip featur es are listed in Chapter 2, "NET+50/20M Chip Features," beginning
on page 7. To make it easier to review chip- specific information, the features have
been presented in two li s t s:
"NET+50 chip key features," beginning on page 8.
"NET+20M chip key features," beginning on page 11.
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n n n n n n n 7
NET+50/20M Chip
Features
CHAPTER 2
The NET+50 and NET+20M chips are based on the standard architecture in the
NET+ARM family of devices. NET+ARM is the hardware foundation for the
NET+Works family of integrated hardwar e and software solutions for device
networking.
This chapter lists the features supported and provided by the NET+50 and
NET+20M chips.
net50_20_1.book Page 7 Friday, September 19, 2003 10:41 AM
NET+50 chip key features
8 n n n n n n n
NET+50/20M Hardware Reference
NET+50 chip key features
The NET+50 chip key features include these components:
CPU core
Full 32-bit ARM7TDMI RISC processor
32-bit internal bus
16-bit Thumb mode
8 Kbyte cache, configurable as 16 Kbyte RAM
15 ge neral-p urpos e 32-bit registers
32-bit program counter and status register
5 supervisor modes, 1 user mode
2 programmable timers
2 async serial ports
Bus interface
Five independen t programmable c hip sele cts with 256 M byte
addressing per chip select
0–15 wait states per chip select
8-bit, 16-bit, and 32-bit peripheral support
Normal and burst cycle support
Glue less interface with all chip selec ts to SRAM, FP/EDO DRAM,
SDRAM, and devices such as flash and EEPROM with SRAM interfaces
External address decoding and cy cle termi na tion support
Dynamic bus sizing support
ASYNC and SYNC peripheral timing support
Internal DRAM address multiplexing
Internal refresh controller (CAS before RAS)
Bootstrap support
Internal bus arbiter support
Configurab le End ia n support
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NET+50/20M Chip Features
Integrated 10/100 Ethernet MAC
10/100 MII-based interface to PHY
10 Mbit ENDEC interface
TP-PMD and fib er-PMD device support
Full-duplex and half-duplex modes
Optional 4B/5B coding
Full statistic s gathering (SNMP and RMON)
Stat ion, broadcast, and multicast a ddress detection a nd filtering
128 byte transmit FIFO, 2 Kbyte receive FIFO
Intelligent receive-side buffer selection
P1284/MIC interface
IEEE 1284 host interface with four parallel ports
DMA support
GPIO mode interface
64K shared RAM ENI interface (8- or 16-bit)
Full-duplex FIFO m ode interface (8- or 16- bit), including 32 byte
transmit/receive mode FIFOs
10-channel DMA controller
Two channels dedicated to Ethernet transmit and receive
Four channels dedicated to serial transmit and receive
Four channels dedicated to P1284/MIC interface
Flex ible buffe r mana gement
Fly-by and memory-to-memory support
Serial ports
Two fu lly-in dependent serial ports (UART, HDLC, SPI)
Digital phase lock loop (DPLL) for receive clock extractions
32 byte transmit/receive FIFOs
Internal programmable bit-rate generators
Bit rates from 75 to 230400 in 16X mode
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NET+50 chip key features
10 n n n n n n n
NET+50/20M Hardware Reference
Bit rates from 1200 to 4 Mbps in 1X mode
(Note: Higher rates may be possible, depending on your design; consult
factory for mo re inform ation.)
Odd, even, or no parity
5, 6, 7, or 8 bits; 1 or 2 stop bits
Internal and external clock support
Receive side character and buffer gap timers
Four receive side data match detectors
Pr ogr ammable Timers
Two independent programmable timers (2µs to 20.7 Hours)
Watch-dog timer (interrupt or reset on expiration)
Bus timer
General-purpose I/O
40 programmable I/O interface pins and 16 input-only interface pins
36 pins with programmable interrupt
Clock genera tor
Only a simple external crystal required
Programmable phase lock loop (PLL), which generates a 44MHz
operating frequency from an 18.432 MHz crystal. Allows a range of
frequ encies from 25–44 MHz, only by using external cryst als.
Direct external clock input support
Power and operating voltage
552 mW maximum (typically 368 mW), outputs switching, VDD max
and VCC max
3.3 volts – I/O
2.5 volts – Core
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NET+50/20M Chip Features
NET+20M chip key features
The NET+2 0M chip key features include the following:
CPU core
Full 32-bit ARM7TDMI RISC processor
32-bit internal bus
16-bit Thumb mode
15 ge neral-p urpos e 32-bit registers
32-bit program counter and status register
5 supervisor modes and 1 user mode
Bus interface
5 independent programmable chip selects with 256 Mbyte addressing
per c hip
0-15 wait states per c hip select
8-bit, 16-bit, and 32-bit peripherals
Normal and burst cycle support
Glue less interface with all chip selec ts to SRAM, FP/EDO DRAM,
SDRAM, and devices such as flash and EEPROM with SRAM interfaces
External address decoding and cy cle termi na tion support
Dynamic bus sizing support
ASYNC and SYNC peripheral timing support
Internal DRAM address multiplexing
Interna l refre sh controller (CAS before RA S)
Bootstrap support
Internal bus arbiter support
Configurable Endia n support
Integrated 10/100 Ethernet MAC
10/100 MII-based interface to PHY
10Mbit ENDEC interface
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NET+20M chip key features
12 n n n n n n n
NET+50/20M Hardware Reference
TP-PMD and fiber-PMD device support
Full-duplex and half-duplex modes
Optional 4B/5B coding
Full statistic s gathering (SNMP and RMON)
Stat ion, broadcast, and multicast a ddress detection a nd filtering
128-byte transmit FIFO, 2 Kbytes receive FIFO
Intelligent receive-side buffer selection
10-channel DMA controller
Two channels dedic ated to Et h er net transmi t a nd receive
Four channels dedicated to serial transmit and receive
Two channels at a time configurable for external peripherals
Two channels reserved
Flex ible buffe r management
Serial ports
Two fu lly-in dependent serial ports (UART, HDLC, SPI)
Digital phase locked loop (DPLL) for receive clock extractions
32-byte transmit/receive FIFOs
Internal programmable bit-rate ge nerators
Bit rates from 75-230400 in 16X mode,
Bit rates from 1200 bps-4 Mbps in 1X mode
(Note: Higher rates may be possible, depending on your design; consult
factory for mo re inform ation.)
Odd, even, or no parity
5, 6, 7, or 8 bits; 1 or 2 stop bits
Internal and external clock support
Receive-side character and buffer gap timers
Four receiv e-side data match detectors
Pr og rammable ti mers
Two independent, programmable timers (2µs to 20.7 Hours)
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NET+50/20M Chip Features
Watch-dog timer (interrupt or reset on expiration)
Bus timer
Clock genera tor
Only a simple external crystal required
Programmable phase lock loop (PLL), which generates a 44MHz
operating frequency from an 18.432 MHz crystal. Allows a range of
frequencies from 25–44 MHz, only by using ex terna l cryst als.
Direct external clock input support
Power and operating voltage
446mW maximum (typically 297mW), outputs switching, VDD max and
VCC max
3.3 volts – I/O
2.5 volts – core
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NET+50 Chip Package
CHAPTER 3
The NET+50 chip can be used in any embedded environment requiring
networking services in an Ethernet LAN. The NET+50 chip contains an integrated
ARM RISC processor, 10/100 Ethernet MAC, serial ports, IEEE 1284 parallel ports,
memory controllers, and parallel I/O. The NET+50 chip can interface with another
processor using a register or shared RAM interface. The NET+50 chip provides all
the tools required for any embedded networking application.
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NET+50 chip pinouts
16 n n n n n n n
NET+50/20M Hardware Reference
NET+50 chip pinouts
There are two var i ations of the NET+ 50 chip:
PQFP: Plastic Quad Flat Pack
BGA: Ball Grid Array
Figure 3 sh ow s th e NET +5 0 PQF P pino u t . F ig u re 4 show s t h e BGA pino ut . Table 1
through Table 8 provide the details for both pinouts.
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NET+50 Chip Package
Figure 3: NET+50 PQFP pinout
VCCDC
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
GNDAC
VCCAC
MDC/LB*
MDIO/UTPSTP*
TXCLK
TXD0/TXD
TXD1/PDN*
TXD2/NTHRES
VSSCO
VDDCO
TXD3/THIN
TXER/LTE
TXEN
COL/TXCOL
CRS/RXCRS
RXCLK
RXD0/RXD
RXD1/MANSEL
RXD2/JABR
RXD3/REVPOL
RXER/LKPOL*
RXDV/AUTMN
GNDDC
VCCDC
C0/INT0
C1/LED2*INT1
C2/LED1*INT2
C3/MUX/INT3
C4/RIB*
C5/TXCB/SPIBE*
C6/RIA*IRQO*
C7/TXCA/SPIAE*
B0/DCDB*DN2*
B1/CTSB*
GNDDC
GNDAC
RESET*
D28
D29
D30
D31
RW*
TS*
TA*
TEA*
BR*
BG*
BUSY*
TDO
TDI
TMS
TCK
TRST*
VDDCO
VSSCO
PLLTST*
XTAL1
XTAL2
PLLVSS
PLLLPF
PLLVDD
PORVSS
BISTEN*
SCANEN*
VCCDC
BCLK
GNDDC
OE*
WE*
CS0*
CS1*RAS1*
CS2*RAS2*
CS3*RAS3*
CS4*RAS4*
CAS0*SDAP
CAS1*SDW*
CAS2*SDC*
CAS3*SDR*
PD0/GPD0
PD1/GPD1
PD2/GPD2
PD3/GPD3
PD4/GPD4
PD5/GPD5
PD6/GPD6
PD7/GPD7
VCCAC
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
VCCAC
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
GNDDC
VCCDC
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
VSSCO
VDDCO
D5
D4
D3
D2
D1
D0
BE3*
BE2*
BE1*
BE0*
GNDAC
VCCAC
A27/CS0OE*
A26/CS0WE*
A25/BLAST*
A24
A23
A22
A21
A20
A19
A18
A17
A16
GNDDC
VCCDC
B2/DSRB*/DAK2*
B3/RXDB/SPIB_I
B4/RXCB/SPIB_C
B5/RSTB*
B6/DTRB*/DRQ2*
B7/TXDB/SPIB_O
A0/DCDA*/DON1*
A1/CTSA*
A2/DSRA*/DAK1*
A3/RXDA/SPIA_I
A4/RXCA/SPIA_C
A5/RSTA*
A6/DTRA*/DRQ1*
A7/TXDA/SPIA_O
GNDDC
VCCDC
PACK*/PCLKD1/GPF7
PCS*/FAULT2*/GPG7
PRW*/FAULT3*/GPF0
PBRW*/FAULT4*/GPF1
PA16/FAULT1*/GPG6
PA15/SEL4/DAK*/GPG5
PA14/SEL3/DQO*/GPF2
PA13/SEL2/DQI*/GPF3
VSSCO
VDDCO
PA12/SEL1/GPG4
PA11/PE4/GPG3
PA10/PE3/GPG2
PA9/PE2/GPG1
PA8/PE1/GPG0
PA7/BUSY4/GPH7
PA6/BUSY3/GPH6
PA5/BUSY2/GPH5
PA4/BUSY1/GPH4
PA3/ACK4*/GPH3
PA2/ACK3*/GPH2
PA1/ACK2*/GPH1
PA0/ACK1*/GPH0
PINT2*/PCLKD4/GPF4
PINT1*/PCLKD3/GPF5
PEN*/PCLKD2/GPF6
PD15/PCLKC4
PD14/PCLKC3
PD13/PCLKC2
PD12/PCLKC1
PD11/POE4*
PD10\POE3*
PD9/POE2*
PD8/POE1*
GNDAC
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
NET+50
208 PIN PQFP
NOTE: VDDCO PINS 26, 78, 130, & 175 ARE POWERED BY 2.5V
PLLVDD PIN 182 REQUIRES CLEAN 2.5V.
TSTPLL * PIN 177 HAS MAX. VIH OF 2.75V
REV H: 05/08/2001
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NET+50 chip pinouts
18 n n n n n n n
NET+50/20M Hardware Reference
Figure 4: NET+50 BGA pinout
Table Information and Tables
Table 1 through Table 8 identify and describe the pin number assignments and ball
number assignments contained in the NET+50 PQFP and BGA chips. Each table
pertains to an inte rface, and contains the following informatio n:
Signal column. Identi fies the p in name for each I /O sign al. Some s ignal s
have multiple modes and are identified accordingly. You configure the
mode through firmware using a configuration register. Some modes may
requir e hardware configuration during a RESET condition.
208 QFP (PQFP) column. Identifies the pin number assignment for a
specifi c I / O si gnal . A dagger next to the pin number indicates that
the pin is an input current so urce.
BGA column. Identifies the ball number assignment for a specific I/O
signal. A dagger next to the pin number indicates t hat the pi n is an
input current s ource.
I/O column. Indicates whether the signal is input (I), output (O), or both
(I/O).
Pi n 1 cor ner
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n n n n n n n 19
NET+50 Chip Package
OD (D r iv e ) co lu mn. Indicates the drive strength of an output buffer.
The NET+50 chip uses one of three driver types:
–2mA
–4mA
–8mA
System bus interface
Signal PQFP BGA I/O OD Description
BCLK 187 T10 O 8 Synchronous bus clock
ADDR27 CS0OE* 117†F4I/O 4 Address bus
ADDR26 CS0WE* 116F3I/O 4
ADDR25 BLAST* 115E2I/0 4
ADDR24 114D2I/O 4
ADDR23 113E3I/O 4
ADDR22 112E4I/O 4
ADDR21 111D1I/O 4
ADDR20 110C2I/O 4
ADDR19 109D3I/O 4
ADDR18 108C1I/O 4
ADDR17 107B1I/O 4
ADDR16 106B2I/O 4
ADDR15 103B3I/O 4
ADDR14 102A3†I/O 4
ADDR13 101A4I/O 4
ADDR12 100B4I/O 4
ADDR11 99C3I/O 4
ADDR10 98A5I/O 4
Ta ble 1: NET+50 PQFP/BGA Chip Pinout - System bus interface
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NET+50 chip pinouts
20 n n n n n n n
NET+50/20M Hardware Reference
ADDR9 97D4I/O 4
ADDR8 96C4I/O 4
ADDR7 95B5I/O 4
ADDR6 94A6I/O 4
ADDR5 93D5I/O 4
ADDR4 92C5I/O 4
ADDR3 91B6I/O 4
ADDR2 90A7I/O 4
ADDR1 89D6I/O 4
ADDR0 88C6I/O 4
DATA31 162 T3 I/O 4 Data bus
DATA30 161 R4 I/O 4
DATA29 160 U3 I/O 4
DATA28 159 U2 I/O 4
DATA27 155 R2 I/O 4
DATA26 154 R1 I/O 4
DATA25 153 P1 I/O 4
DATA24 152 P2 I/O 4
DATA23 151 R3 I/O 4
DATA22 150 N1 I/O 4
DATA21 149 P4 I/O 4
DATA20 148 P3 I/O 4
DATA19 147 N2 I/O 4
DATA18 146 M1 I/O 4
DATA17 145 N4 I/O 4
DATA16 142 L1 I/O 4
DATA15 141 M4 I/O 4
Signal PQFP BGA I/O OD Description
Ta ble 1: NET+50 PQFP/BGA Chip Pinout - System bus interface
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NET+50 Chip Package
DATA14 140 M3 I/O 4
DATA13 139 L2 I/O 4
DATA12 138 K1 I/O 4
DATA11 137 L4 I/O 4
DATA10 136 L3 I/O 4
DATA9 135 K2 I/O 4
DATA8 134 J1 I/O 4
DATA7 133 K4 I/O 4
DATA6 132 K3 I/O 4
DATA5 129 J4 I/O 4
DATA4 128 J3 I/O 4
DATA3 127 H2 I/O 4
DATA2 126 G1 I/O 4
DATA1 125 H4 I/O 4
DATA0 124 H3 I/O 4
TS* NO CONNECT
BE3* 123 G2 I/O 2 Byte enable D31:D24
BE2* 122 F1 I/O 2 Byte enable D23:D16
BE1* 121 G4 I/O 2 Byte enable D15:D08
BE0* 120 G3 I/O 2 Byte enable D07:D00
RW* 163 U4 I/O 2 Transfer dir ection
TA* 165R5I/O 8 Data transfer acknowledge
TEA* 166T4I/O 8 Transfer error/Last acknowledge
BR* NO CONNECT
BG* NO CONNECT
BUSY* NO CONNECT
Signal PQFP BGA I/O OD Description
Ta ble 1: NET+50 PQFP/BGA Chip Pinout - System bus interface
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NET+50 chip pinouts
22 n n n n n n n
NET+50/20M Hardware Reference
Chip select controller
Ethernet int erface
Signal PQFP BGA I/O OD Description
CS0* 191 T11 O 4 Chip select (Boot select)
CS1*/RAS1* 192 R12 O 4 Chip sel ect/DRAM RAS*
CS2*/RAS2* 193 P12 O 4 Chip select/DRAM RAS*
CS3*/RAS3* 194 U11 O 4 Chip select/DRAM RAS*
CS4*/RAS4* 195 T12 O 4 Chip select/DR AM RAS*
CAS3*/SDRAS* 199 T13 O 4 DRAM column strobe D31:24/SDRAM
RAS
CAS2*/SDCAS* 198 U12 O 4 DRAM column strobe D23:16/SDRAM
RAS
CAS1*/SDWE* 197 P13 O 8 DRAM column strobe D15:08/SDRAM
RAS
CAS0*/SD(AP) 196 R13 O 4 DRAM column strobe D07:00/SDRAM
RAS
WE* 190 R11 O 4 Write enable
OE* 189 P11 O 4 Output enable
Ta ble 2: NET+50 PQFP/BGA Chip Pinout - Chip se lect controller
Signal PQFP BGA I/O OD Description
MII 10BaseT MII 10BaseT
MDC LB* 85 D7 O 2 MII clock Loopback enable
MDIO UTPSTP* 84C7I/O 2 MII data Cable type
TXCLK TXCLK 83 B8 I TX clock
TXD0 TXD 82 A9 O 2 TX data 0 TX da ta
TXD1 PDN* (OD) 81 D8 O 2 TX data 1 Power down
Ta ble 3: NET+50 PQFP/BGA Chip Pinout - Ethernet interfac e
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NET+50 Chip Package
MIC interface
TXD2 NTHRES 80 C8 O 2 TX data 2 Normal threshold
TXD3 THIN 77 D9 O 2 TX data 3 Enable Thinnet
TXER LTE 76 C9 O 2 TX code error Link test enable
TXEN TXEN 75 B10 O 2 TX enable
COL TXCOL 74 A11 I Collision
CRS RXCRS 73 D10 I Carrier sen se
RXCLK RXCLK 72 C10 I RX clock
RXD0 RXD 71 B11 I RX data 0 RX data
RXD1 MANSE NS E 70 A12 I RX data 1 Sense jumper
RXD2 JABBER 69 D11 I R X data 2 Jabber
RXD3 RE VPOL 68 C11 I RX data 3 Reverse polarity
RXER LINKPUL* 67 B12 I RX error Link pulse
detection
RXDV AUTOMAN 66 A13 I RX data valid 10B2 selected
Signal PQFP BGA I/O OD Description
Ta ble 3: NET+50 PQFP/BGA Chip Pinout - Ethernet interfac e
Signal PQFP BGA I/O OD Description
IEEE 1284 MIC GPIO
PDATA0 PDATA0 GPIOD0 200R14I/O 2 Paral lel 1 284/ ENI/GPIO
PDATA1 PDATA1 GPIOD1 201P14I/O 2
PDATA2 PDATA2 GPIOD2 202U13I/O 2
PDATA3 PDATA3 GPIOD3 203R15I/O 2
PDATA4 PDATA4 GPIOD4 204T14I/O 2
PDATA5 PDATA5 GPIOD5 205U14I/O 2
Ta ble 4: NET+50 PQFP/BGA Chip Pinout - MIC interface
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NET+50 chip pinouts
24 n n n n n n n
NET+50/20M Hardware Reference
PDATA6 PDATA6 GPIOD6 206U15I/O 2
PDATA7 PDATA7 GPIOD7 207T15I/O 2
POE1* PDATA8 2T16I/O 2
POE2* PDATA9 3T17I/O 2
POE3* PDATA10 4R17I/O 2
POE4* PDATA11 5P15I/O 2
PCLKC1 PDATA12 6R16I/O 2
PCLKC2 PDATA13 7P17I/O 2
PCLKC3 PDATA14 8N14I/O 2
PCLKC4 PDATA15 9N15I/O 2
PCLKD1 PACK* GPIOF7 35 G16 I/O 8
PCLKD2 PEN* GPIOF6 10P16I/O 2
PCLKD3 PINT1* GPIOF5 11 N16 I/O 2
PCLKD4 PINT2* GPIOF4 12 M15 I/O 2 Or ENI DMA output PDRQIO
ACK1* PA0 GPIOH0 13 M14 I
ACK2* PA1 GPIOH1 14 N17 I
ACK3* PA2 GPIOH2 15 M16 I
ACK4* PA3 GPIOH3 16 L15 I
BUSY1 PA4 GPIOH4 17 L14 I
BUSY2 PA5 GPIOH5 18 M17 I
BUSY3 PA6 GPIOH6 19 L16 I
BUSY4 PA7 GPIOH7 20 K15 I
PE1 PA8 GPIOG0 21 K14 I
PE2 PA9 GPIOG1 22 L17 I
PE3 PA10 GPIOG2 23 K16 I
PE4 PA11 GPIOG3 24 J15 I
PSELECT1 PA12 GPIOG4 25 J14 I
Signal PQFP BGA I/O OD Description
Ta ble 4: NET+50 PQFP/BGA Chip Pinout - MIC interface
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n n n n n n n 25
NET+50 Chip Package
UARTS-SPI-GPIO
PSELECT2 PA13 GPIOF3 28 H15 I/O 2 Or ENI DMA output PDRQI*
PSELECT3 PA14 GPIOF2 29 H14 I/O 2 Or ENI DMA output PDRQO*
PSELECT4 PA15 G PIOG5 30 J17 I O r ENI DMA input PDACK*
FAULT1* PA16 GPIOG6 31 H16 I
FAULT2* PCS* GPIOG7 34 H17 I
FAULT3* PRW* GPIOF0 33 G14 I/O 2
FAULT4* PBRW* GPIOF1 32 G15 I/O 2
Signal PQFP BGA I/O OD Description
Ta ble 4: NET+50 PQFP/BGA Chip Pinout - MIC interface
Signal PQFP BGA I/O OD Description
PORTA7 TXDA 38G17I/O 2 SPI-S-TXD-O-A SPI-M-TXD-O-A
PORTA6 DTRA*/DRQ1* 39F16I/O 2
PORTA5 RTSA* 40E15I/O 2
PORTA4 RXCA 41E14I/O 2 SPI-S-CLK-I-A SPI-M-CLK-O-A*
PORTA3 RXDA 42F17I/O 2 SPI-S-RXD-I-A SPI-M-RXD-I-A
PORTA2 DSRA*/DAK1* 43E16I/O 2
PORTA1 CTSA* 44D15I/O 2
PORTA0 DCDA*/DON1* 45D14I/O 2
PORTB7 TXDB 46E17I/O 2 SPI-S-TXD-O-B SPI-M-TXD-O-B
PORTB6 DTRB*/DRQ2* 47C15I/O 2
PORTB5 RTSB* 48D16I/O 2 Reject* Ethernet packet
PORTB4 RXCB 49D17I/O 2 SPI-S-CLK-I-B SPI-M-CLK-O-B*
PORTB3 RXDB 50C17I/O 2 SPI-S-RXD-I-B SPI-M-RXD-O-B
PORTB2 DSRB*/DAK2* 51C16I/O 2
Table 5: NET+50 PQFP/BGA Chip Pinout - UARTS-SPI-GPIO
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NET+50 chip pinouts
26 n n n n n n n
NET+50/20M Hardware Reference
Clock generation/system reset
PORTB1 CTSB* 54B16I/O 2 RPSF* Ethernet frame boundary
PORTB0 DCDB*/DON2* 55A16I/O 2
PORTC7 TXCA 56A15I/O 4 SPI-S-EN-I-A SPI-M-EN-O-A
PORTC6 RIA*/IRQO* 57C14I/O 4
PORTC5 TXCB 58B15I/O 4 SPI-S-EN-I-B SPI-M-EN-O-B
PORTC4 RIB* 59A14I/O 4
PORTC3 AMUX 60D13I/O 8 Int errupt 3
PORTC2 61C13I/O 8 Interrupt 2
PORTC1 62B14I/O 8 Interrupt 1
PORTC0 63B13I/O 8 Interrupt 0
Signal PQFP BGA I/O OD Description
Table 5: NET+50 PQFP/BGA Chip Pinout - UARTS-SPI-GPIO
Signal PQFP BGA I/O OD Description
XTAL1 178 U7 I Crystal oscillator circ uit
XTAL2 179 T8 O
PLLVDD (2.5V) 182 U8 2.5 V PLL clean power
PLLLPF 181 P9 PLL loop filter capacitor
PLLVSS 180 R9 PLL clean ground
PLLTST* (2.5V) 177P8IPLL test mode
BISTEN* 184R10I Enable internal BIST operation
SCANEN* 185P10I Enable internal SCAN testing
System reset
RESET* 158T2ISystem reset
Ta ble 6: NET+50 PQFP/BGA Chip Pinout - Clock generation/system reset
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NET+50 Chip Package
JTAG port for ARM core
Power supp ly
Signal PQFP BGA I/O OD Description
TDI 171T61 Test data in
TDO 170 U5 O 2 Test data out
TMS 172R7I Test mode select
TRST* 174 R8 I Test mode reset. This is a current input sink.
TCK 173 P7 I Test mode clock
Ta ble 7: NET+50 PQFP/BGA Chip Pinout - JTAG port for ARM core
Signal Mode Pin/Ball Number Description
VCCDC 3.3V DC BGA F15, B17, C12, A2, M2, U9 I/O steady state (6 pairs)
PQFP 36, 52, 64, 104, 143, 186
VSSDC GND Retur ns BGA F14, A17, D12, A1, N3, U10
PQFP 37, 53, 65, 105, 144, 188
VCCAC 3.3V BGA A8, E1, T1, U16 I/O switching (4 pairsa)
PQFP 86, 118, 156, 208
VSSAC GND Retur ns BG A B7, F2, U1 , U17
PQFP 87, 119, 157, 1
VDDCO 2.5V BGA K17, A10, H1, T7 Core power (4 pairs)
PQFP 26, 78, 130, 175
VSSCO GND Retur ns BGA J16, B9, J2, U6
PQFP 27, 79, 131, 176
Ta ble 8: NET+50 PQFP/BGA Chip Pinout - Power supply
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Signal description summary
28 n n n n n n n
NET+50/20M Hardware Reference
Signal description summary
The signal de scri ption summa ry defines an d briefly de scribes th e signa ls inclu ded
in the interfaces in the NET+50 chip. The description tables in the section are
presented in the same order as the NET+50 chip pinout tables. For details about
any of th e signa l s/ pino ut s, se e t he appr o p ri ate chapter:
The JTAG Port for ARM Core (ARM Debugger) and Pow er sections are addressed
ful l y in their resp e c t i v e disc u s sions .
PLLVDD 2.5V BGA U8 PLL bead filtered clean power
PQFP 182
PLLVSS GND Return BGA R9
PQFP 180
PORVSS GND BGA T9 Powerup reset GND refe ren ce
PQFP 183
a. NetSilicon recommends that you use separate power pairs for AC and DC power, to prevent th e noise in the AC p ow-
er buses from reaching the DC power buses. NetSilicon recommends and uses a ferrite bead to filter the AC power
pins.
Signal Mode Pin/Ball Number Description
Ta ble 8: NET+50 PQFP/BGA Chip Pinout - Power supply
Interface Chapter
System bus Chapter 8, "Memory Controller Module"
Chip select controller Chapter 8, "Memory Controller Module"
Ethernet MII Chapter 10, "Ethernet Controller Module"
MIC Chapter 12, "MIC Controller Module"
UARTS-SPI-GPIO; GPIO ports A, B, C Chapter 6, "The GEN Module"
Clock generation Chapter 6, "The GEN Module"
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NET+50 Chip Package
System bus interface
The NET+50 chip uses the system bus interface to interface with memory-mapped
peripheral devices such as flash, SRAM, and DRAM.
Code Definition Description
BCLK Bus clock Provides the bus clock. All s ystem bus i nter face signals a re refer enced t o t he BC LK signa l.
ADDR Address bus Identifies the address of the peripheral being addressed by the current bus master. The
address bus is bi-directional.
DATA Data bus Provides the data transfer path between the NET+50 chip and external peripheral
devices.The data bus is bi-directional.
TS* Transf er st art NO C ONNE CT
BE* Byte enable Identifies which 8-bit bytes of the 32-bit data bus are active during any given system bus
memory cycle. The BE* signals are active low and bi-directional.
RW* Read/write
indicator Indicates the direction of the system bus memory cycle. RW* high identifies a read
operation; RW* low identifies a write operation. The RW* signal is
bi-directional.
TA* Transfer
acknowledge Indicates the end of the current system bus memory cycle. This signal is
bi-directional.
TEA* Transfer error
acknowledge Indicates an error termination or burst cycle termination. TEA* is bi-directional. The
NET+50 chip or the external peripheral can drive the TEA* signal.
BR* Bus request NO CONNECT
BG* Bus grant NO CONNECT
BUSY* Bus busy NO CONNECT
Ta ble 9: System bus interface signal description
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Signal description summary
30 n n n n n n n
NET+50/20M Hardware Reference
Chip select controller
The NET+50 chip supports five unique chip select configurations.
Ethernet MII
The E t h er net MII (Media I nd e penden t I nt erface ) p rovi des the connect i on between
the Ethernet PHY and the MAC (Media Access Controller).
Code Definition Description
CS0*
CS1*
CS2*
CS3*
CS4*
Chip select 0
Chip select 1
Chip select 2
Chip select 3
Chip select 4
Unique chip select outputs supported by the NET+50 chip. Each chip select can be
configured to decode a portion of the avai lable address space and can address a maximum of
256 Mbytes of address space. Th e chip selects are configured using registers in the memory
module.
CAS0*
CAS1*
CAS2*
CAS3*
Column address
strobe signals Activated when an address is dec oded by a chip select module configured for DRAM mode.
The CAS* signals are active low and provide the column address strobe function for DRAM
devices.
The CAS* signals also identify which 8-bit bytes of the 32-bit data bus are active during any
given system bus memory cycle.
WE* Write enable Active low signal indicating that a memory write cycle is in progress. This signal is activated
only during write cycles to peripherals controlled by one of the chip selects in the memory
module.
OE* Output enable Active low signal i ndicating that a memory read cycl e is in progress. T his signal is activated
only during read cycles from peripherals controlled by one of the chip selects in the memory
module.
Table 10 : Chip select controller signal description
Code Definition Description
MDC Management data
clock Provides the clock for the MDIO serial data channel. The MDC signal is a NET+50 chip
output. The maximum frequency is 2.5 MHz.
MDIO Management data
IO A bi-directional signal that provides a serial data channel between the NET+50 chip and the
external Ethernet PHY module.
TXCLK Transmit clock An input to the NET+50 chip from the external PHY module. TXCLK provides the
synchronous data clock for transmit data.
Ta ble 11: Ethernet MII signal description
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NET+50 Chip Package
MIC interface
The NET+50 chip uses the MIC interface to interface with other embedded
computer systems. The MIC interface provides various modes: GPIO, IEEE 1284,
shared RAM, and FIFO s.
The MIC interface can be configured to operate in GPIO, IEEE 1284, or ENI host
mode — but never at the sam e time. The ENI host mode supports shared RAM
and FIFO interfaces.
If this port is not used, it must be defaulted during bootstrap to a known value,
such as
(ENI Share d-1 6 RA M Mode) , by pr o vidin g input c urrent sink r e sist or s
TXD3
TXD2
TXD1
TXD0
Transmit data
signals Nibble bus used by the NET+50 chip to drive data to the external Ethernet PHY. All transmit
data signals are synchronized to TXCLK. In ENDEC mode, only TDX0 is used for transmit
data.
TXER Transmit coding
error Output asser te d by the NET+50 when an error has occurre d in the transmit data stream.
TXEN Transmit enable Asserted when the chip drives valid data on the TXD outputs. This signal is synchronized to
TXCLK.
COL Transmit
collision Input signal asserted by the external Ethernet PHY when a collision is detected.
CRS Receive carrier
sense Asserted by the external Ethernet PHY whenever the receive medium is non-idle.
RXCLK Receive clock An input to the NET+50 chip from the external PHY module. The receive clock provides the
synchronous data clock for receive data.
RXD3
RXD2
RXD1
RXD0
Receive d at a
signals Nibble bus used by the NET+50 chip to input receive data from the external Ethernet PHY.
All receive data signals are synchronized to RXCL K. In ENDEC m ode, only RXD0 is used
for receive data.
RXER Receive error Input asserted by the external Ethernet PHY when the Ethernet PHY encounters invalid
symbols from the network.
RXDV Receive data
valid Input asserted by the external Ethernet PHY when the Ethernet PHY drives valid data on the
RXD inputs.
Code Definition Description
Ta ble 11: Ethernet MII signal description
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Signal description summary
32 n n n n n n n
NET+50/20M Hardware Reference
on NET+50 pins A22, A21, and A20. Unused input pins must be terminated
acco rdin g to th e NE T+50 minimu m co nfigur a t ion.
When the MIC interface is set to GPIO or 1284 Mode, un used inputs in each of
thes e mod e s mu st be t ermi n at e d .
This section provides details for each MIC interface mode.
IEEE 1284 mode
Code Definition Description
PDATA 1284 data bus A bi-directional data bus that interfaces the NET+50 chip with the external 1284
port data and control transceivers. The NET+50 chip interfaces only with a
single 1284 port at a time.
POE1*
POE2*
POE3*
POE4*
Output enables:
1284 Channel 1
1284 Channel 2
1284 Channel 3
1284 Channel 4
Channel output enable signals that control the output enable for each specific
port data register.
PCLKC1
PCLKC2
PCLKC3
PCLKC4
Control clocks:
1284 Channel 1
1284 Channel 2
1284 Channel 3
1284 Channel 4
Channel control clock signals that are driven by the NET+50 chip to load the
1284 data bus outputs into the various 1284 control transceivers. Only one
channel control clock is active at any moment in time. The channel control
clocks are never active at the same time as any channel data clocks.
PCLKD1
PCLKD2
PCLKD3
PCLKD4
Data clocks:
1284 Channel 1
1284 Channel 2
1284 Channel 3
1284 Channel 4
Channel data clock signals that are driven by the NET+50 chip to load the 1284
data bus outputs into the various 1284 data transceivers. Only one channel data
clock is active at any moment in time. The channel data clocks are never a ctive
at the same time as any channel control clocks.
ACK1*
ACK2*
ACK3*
ACK4*
Acknowledge:
1284 Channel 1
1284 Channel 2
1284 Channel 3
1284 Channel 4
Channel ACK inputs to the NET+50 chip from the external IEEE 1284 port.
The ACK input meaning changes as the IEEE 1284 operational mode changes.
Note: For additional information about IEEE 1284 operational modes, see your
IEEE documentation.
Ta ble 12: MIC IEEE 12 84 mode signal description
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NET+50 Chip Package
ENI host mode
BUSY1*
BUSY2*
BUSY3*
BUSY4*
BUSY:
1284 Channel 1
1284 Channel 2
1284 Channel 3
1284 Channel 4
Channel BUSY inputs to the NET+50 chip from the external IEEE 1284 port.
The BUSY input meaning changes as the IEEE 1284 operational mode changes.
Note: For additional information about IEEE 1284 operational modes, see your
IEEE documentation.
PE1*
PE2*
PE3*
PE4*
ERROR:
1284 Channel 1
1284 Channel 2
1284 Channel 3
1284 Channel 4
Channel ERROR inputs to the NET+50 chip from the external IEEE 1284 port.
The ERROR input meaning changes as the IEEE 1284 operational mode
changes.
Note: For additional information about IEEE 1284 operational modes, see your
IEEE documentation.
PSELECT1*
PSELECT2*
PSELECT3*
PSELECT4*
PSELECT:
1284 Channel 1
1284 Channel 2
1284 Channel 3
1284 Channel 4
Channel PSELECT (peripheral select) inputs to the NET+50 chip from the
external IEEE 1284 port. The PSELECT input meaning changes as the IEEE
1284 operational mode changes.
Note: For additional information about IEEE 1284 operational modes, see your
IEEE documentation.
FAULT1*
FAULT2*
FAULT3*
FAULT4*
FAULT:
1284 Channel 1
1284 Channel 2
1284 Channel 3
1284 Channel 4
Channel FAULT inputs to the NET+50 chip from the external IEEE 1284 port.
The FAULT input meaning changes as the IEEE 1284 operational mode
changes.
Note: For additional information about IEEE 1284 operational modes, see your
IEEE documentation.
Code Definition Description
Ta ble 12: MIC IEEE 12 84 mode signal description
Code Definition Description
PCS* ENI chip sel ect Provides the chip enable for the ENI interf ace fr om the external proce ssor
system.
PRW* ENI read/write Driven by the external processor syst em during an ENI access cycle to
indicate the data transfer
PA[16:0] ENI address bus 17 required addr ess signals that identify th e resource being accessed. The PA
bus must be valid while PCS* is low. During DMA cycles, the PA address bus
is ignored and only the FIFO data register is accessible.
Ta ble 13: ENI host mode signal description
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Signal description summary
34 n n n n n n n
NET+50/20M Hardware Reference
MIC interface configured for GPIO mode
Full configuration information for Ports D-H appears in the GPIO Mode section in
Chapter 12, "MIC Controller Module."
PDACK*/PA15 ENI DMA acknowledge PA15 input used for the DMA acknowledge input PDACK*, when DMA
FIFO operations are enabled (when the DMAE* bit in the ENI control register
is se t to 0 ) .
PDRQO*/
PDRQO/PA14 ENI outbound FIFO DMA
request PA14 output used for the active low outbound FIFO DMA ready output
PDRQO*, when DMA FIFO operati ons are enabled. The PDRQO* signa l is
routed through PA14 only when both DMAE* and DMAE2 are set to 0 in the
ENI Control register.
PDRQI*/
PDRQI/PA13 ENI outbound FIFO DMA
request PA13 output used for the active low inbound FIFO DMA ready output
PDRQI*, when DMA FIFO operations are enabled. THE PDRQI* signal is
routed through PA13 only when both DMAE* and DMAE2 are set to 0 in the
ENI Control register.
PDATA[15:0] ENI data bus 16-bit data bus supported by ENI.
PACK* ENI acknowledge Indicates the requested ENI cycle is complete. PACK* is driven by the ENI
interface in response to an active low PCS* signal.
PINT1* ENI interrupt 1 Indicates an interrupt condition to the external ENI processor.
PINT2* ENI interrupt 2 Indicates an interrupt condition to the external ENI processor.
PBRW* ENI data buffer read/write An output that controls the data direction pin for an external data bus
transceiver.
PEN* ENI data buffer enable An output that controls the output enable pin for an external data bus
transceiver.
Code Definition Description
Ta ble 13: ENI host mode signal description
Code Definition Description
GPIOD [7:0] General purpose I/O Each pin can be configured for input, output, or level-sensitive interrupt.
GPIOF [7:0] General purpose I/O Each pin can be configured for input, output, or level-sensitive interrupt.
GPIOG [7: 0]/
GPIO [7:0] General purpose I/O Each pin can be configured input low level-sensitive interrupt.
Ta ble 14: MIC G PIO mode signal desc ription
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NET+50 Chip Package
GPIO (PORTA/B/C)
See Chapter 6, "The GEN Module," for full configuration information for
POR TA/B/C. All ports can be can be configured for general purpose I/O. The
descriptions below highlight some of each port’s special funct ions.
GPIOH [7: 0]/
GPIO [7:0] Gener al Purpose I/O Ea ch pin can be configured for input low level-sensitive interrupt .
Code Definition Description
Ta ble 14: MIC G PIO mode signal desc ription
Code Definition Description
PORTA7 Input/Output/TxDA/SPI-A-M + S-TXD-O Can be configured as the special function TxDA output.
PORTA6 Input/Output/DREQ1*/DTRA* Can be configured as the special function DREQ1* input or
the special function DTRA.
PORTA5 Input/Output/RTSA* Can be configured as the special function RTSA output.
PORTA4 Input/Output/RxCA/SPI-A-S-CLK-I/
SPI-A-M-CLK-O Can be configured for special function RxCA input or the
special function OUT1A output.
PORTA3 Input/Output/RxDA/SPI-A-S + M-RXD-I Can be configured for special function RxDA input.
PORTA2 Input/Output/DSRA*/DACK1* Can be configured for special function DSRA input or for
special function DACK1* output.
PORTA1 Input/Output/CTSA* Can be configured for special function CTSA input.
PORTA0 Input/Output/DCDA*/DONE1* Can be configured for special function DCDA input or
DONE1* I/O.
PORTB7 Input/Output/TxDB/SPI-B-M and S-TXD-O Can be configured as the special function TxDB output.
PORTB6 Input/Output/DREQ2*/DTRB* Can be configured as the special function DREQ2* input or
the special function DTRB.
PORTB5 Input/Output/REJECT*/RTSB* Can be configured as the special function REJECT input or
for special function RTSB output.
PORTB4 Input/Output/RxCB/SPI-B-M-CLK-O/
SPI-B-S-CLK-I Can be configured for special function RxCB input or special
function OUT1B.
PORTB3 Input/Output/RxDB/SPI-B-S + M-RXD-I Can be configured for special function RxDB input.
Ta ble 15: GPIO PO RTA/B/C signal description
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Signal description summary
36 n n n n n n n
NET+50/20M Hardware Reference
Clock generation and reset
The NET+50 has thr ee main clock domains:
System clock (SYSCLK)
Bit rate generation and programmable timer reference clock (XTAL)
System bus clock (BCLK)
The SYS mod u l e provi d es th e N E T+ 50 ch i p wi t h t he se c l ocks, as we l l as sy st e m
reset and boot-up resources.
PORTB2 Input/Output/DSRB*/DACK2* Can be configured for special function DSRB input or special
function DACK2* output.
PORTB1 Input/Output/CTSB*/RPSF* Can be configured for special function RPSF* output or
special function CTSB input.
PORTB0 Input/Output/DCDB*/DONE2* Can be configured for special function DCDB input or special
function DONE2* I/O.
PORTC7 Input/Output/TxCA/SPI-A-M-ENB-O/
SPI-A-S-ENB-I Can be configured f or special function TxCA input or special
function OUT2A output.
PORTC6 Input/Output/RIA*/IRQ* Can be configured as the special function RIA* input or for
special function IRQ* output.
PORTC5 Input/Output/TxCB/SPI-B-M-ENB-O/
SPI-B-S-ENB-I Can be configured for special function TxCB input or special
function OUT2B output.
PORTC4 Input/Output/RIB* Can be configured for special function RIB input.
PORTC3 Input/Output/CI3/AMUX Can be configured for special function C3 interrupt input or to
provide the DRAM address multiplexer function.
PORTC2 Input/Output/CI2 Can be configured for special function C2 interrupt input.
PORTC1 Input/Output/CI1 Can be configured for special function C1interrupt input.
PORTC0 Input/Output/CI0 Can be configured for special function C0 interrupt input.
Code Definition Description
Ta ble 15: GPIO PO RTA/B/C signal description
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NET+50 Chip Package
Test support
The PLLTST*, BISTEN*, and SCANEN* primary input pins put the NET+50 into
various test modes, for both functional and manufacturing test operations.
For more information about PLLTST*, see Chapter 6, "The GEN Module."
ARM debugger
Five pins provide a dedicated connection to the internal ARM processor core.
These fi ve si g n al s connec t to th e AR M proces so r only, and are use d for so ft wa re
development using the ARM Embedded ICE module (or similar device). These
five signals should not be confused with 1149.1 JTAG Testing.
TDI
Code Definition Description
XTAL1
XTAL2
Crystal osci ll a tor
input
Crystal osci ll a tor
output
A standard parallel-resonant crystal can be attached to these pins to provide the main input
clock to the NET+50 chip.
The oscillator frequency equals SYSCLK. XTAL1 is in the 2.5V ring and has a maximum
VIH of 2.75V. A typical 3.3V oscillator requires a 220 ohm series resistor with its output.
PLLVDD Clean PLL power Powers the internal 2.5V PLL circuit.
PLLVSS C lean PLL ground Grounds the internal PLL circuit.
PLLPF PLL loop filter Provides the PLL loop filter circui t.
RESET* System reset Resets the NET+50 chip hardware.
Ta ble 16: Clock generation and rese t signal description
Code Definition Description
PLLTST* PLL test and
disable Disables the intern al PLL when driven active low. Enables t he crystal oscillator and internal
PLL when left unconnected or driven high.
BISTEN* BIST enable Used for testing purposes only; the pin should always be left unconnected or driven high.
SCANEN* SCAN enable Used for testing purposes only; the pin should always be left unconnected or driven high.
Ta ble 17: Test support signal desc ription
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Signal description summary
38 n n n n n n n
NET+50/20M Hardware Reference
TDO
TMS
TRST*
TCK
The following figure illustrates the pin connection:
Figure 5: NET+50/ 20M reset and ARM debugger circui t
Power
This section describes the pins that provide power for various components of the
I/O output drivers and the internal NET+50 chip core.
10KR5
OUT
NETARM.158
Re quire s powe rup timi ng s equen c ing
wit h so me debugg ers when F la sh
c ont ains invalid code or is disabled.
RESET-
0R4
0R2
NOTE:
Ful l Fe atu re d D ebu g -O ption a l
TDO
R1, R2
3.3V
Useful for code development. Removes
timing and break point restrictiions.
TDI
Leaving TRST* pulled to a logic "low" on
production units is not recommended. The noise
margin on inputs at a logic "0" are only a few
tenths of a volt.
NETARM.173
OUT
3.3V
5V OR 3.3 V OPEN DRAIN
3.3V ACTIVE T TL
NETARM.174
RESET LOADS-
1K
Basic Debug - Production Units
5V ACTIVE T TL
0R1
ICETRST-
Table 1
IN
1K
D1
DIODE_SCHOTTKY
352uA CURRENT S OURC E
U1
AND1_SOT23
1
23
4
5
NETARM.172
3.3V
NETARM
10KR3
IN
0R6
NETARM.170
3 TYPICAL RESET SOURCES
429uA Max.CURR ENT SINK
ICESRST-
See Table 1
C1
.1
3.3V
HEADE R 7X2
12 34 56 78 910 11
13
12
14
C1, R5, R6, U1
3.3V
TMS
RESET_OUT-
TRST-
NETARM.171
TCK
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n n n n n n n 39
NET+50 Chip Package
Code Definition Description
VCCAC Power A/C
switching The VCCAC pins provide the 3.3V power for the switching component of the
I/O output drivers. Thes e pi ns can be fi ltered t o l ower any potential EM I. E ach VCCAC pin
has a GNDAC ground return.
VCCDC Power DC drive The VCCDC pins provide the 3.3V power for the DC component of the I/O output drivers.
These pins should not require any filtering other than standard decoupling practices. Each
VCCDC pin has a GNDDC ground return.
VDDCO Power core The VDDCO pins provide the 2.5V power for the internal NET+50 chip core. Each of these
pins must have a bypass capacitor placed as close to the pin as physically possible. Each
VDDCO pin has a VSSCO ground return.
PORVSS Power on reset Grounds the power-on-reset circuitry.
GNDAC Ground A/C
switching The GNDAC pins provide the ground for the switching component of the I/O output drivers.
These pins can be filtered to lower any potential EMI.
GNDDC Ground DC drive The GNDDC pins provide the ground for the DC component of the I/O output drivers. These
pins should not require any filtering other than standard decoupling practices.
GNDCO Ground core The GNDCO pins provide the ground for the internal NET+50 chip core. These pins should
not require any filtering other than standard decoupling practices.
Ta ble 18: Po wer signal description
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NET+50 Chip Package
Millimeter Inches
Symbol Min Nom Max Min Nom Max
A --------------- --------------- 4.10 --------------- --------------- 0.161
A10.25 --------------- --------------- 0.010 --------------- ---------------
A23.20 3.32 3.60 0.126 0.131 0.142
D 31.20 BASIC 1.228 BASIC
D128.00 BASIC 1.102 BASIC
E 31.20 BASIC 1.228 BASIC
E128.00 BASIC 1.102 BASIC
R20.13 --------------- 0.30 0.005 -------------- 0.012
R10.13 -------------- -------------- 0.005 -------------- --------------
θ10-------------- 70-------------- 7
θ12 0-------------- -------------- 0-------------- --------------
θ23 8 REF 8 REF
θ38 REF 8 REF
c 0.11 0.15 0.23 0.004 0.006 0.009
L 0.73 0.88 1.03 0.029 0.035 0.041
L11.60 REF 0.063 REF
S 0.20 -------------- -------------- 0.008 -------------- --------------
b 0.17 0.20 0.27 0.007 0.008 0.011
e 0.50 BSC. 0.020 BSC.
D2 25.50 1.004
E2 25.50 1.004
TOLERANCES OF FORM AND POSI TI ON
aaa 0.25 0.010
bbb 0.20 0.008
ccc 0.08 0.003
Table 19: PQFP di mensions
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Packaging
42 n n n n n n n
NET+50/20M Hardware Reference
BGA package
Figure 7 shows the package for the NET+50 BGA. Table 20 provides the NET+50
BGA dimensions:
Figure 7: BGA pac kage
Dimension Minimum Nominal Maximum
A --------------- --------------- 1.40
A1 0.22 0.26 0.30
A2 0.65 0.70 0.75
A3 0.25 --------------- ---------------
B -------------- - 5.50 REF --------- -- --- -
D --------------- 15.00 ---------------
D1 --------------- 12.80 ---------------
Table 20: BGA dimensions
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n n n n n n n 43
NET+50 Chip Package
E --------------- 15.00 ---------------
E1 --------------- 12.80 ---------------
P --------------- 0.80 ---------------
Dimension Minimum Nominal Maximum
Table 20: BGA dimensions
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n n n n n n n 45
Working with the CPU
CHAPTER 4
The CPU module uses an ARM7TDMI core processor, which provides high
performa nce while maintaining low power consumption and size. This chapter
describes the ARM Thumb concept and provides an overview of ARM exceptions
and hardware interrupts.
Note:
The information in this chapter applies to both the NET+50 and
NET+20M chips, unless otherwise noted.
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Thumb concept
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Thumb concept
The ARM7TDMI processor employs a unique architectural strategy known as the
Thumb, which makes the processor ideally suited to high-volume applications
with memory restrictions or applications for which code density is an issue.
The primary attribute of the Thumb is a super-reduced instruction set. The
ARM7TDMI pro cesso r ha s es sen tia lly two instruction sets:
Standard 32-bit ARM set
16-bit Thumb set
The Thumb’s 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM’s performance advantage
over a traditional 16-bit processor using 16-bit registers. Thumb code operates on
the same 32-bit register set as the ARM code, but uses only about 65% of the same
code size compiled in ARM mode.
Thumb instructions operate with the standard ARM register configuration. Each
16-bit Thumb instruction has a corresponding 32-bit ARM instruction with the
same effect o n t he proc essor model . The Thumb archi t ec t u re pr o v i des a Thumb
instruction decoder in front of the standard 32-bit ARM processor. The Thumb
instruction decoder basically remaps each 16-bit Thumb instruction into a 32-bit
standard ARM instruction. The Thumb instruction set typically requires 30% more
instructions to perform the same task as 32-bit instructions; the Thumb instruction
set, however, can fit twice as many instructions in the same code space. The net
result is a 35% decrease in overall code density.
Working with ARM exceptions
Exceptions occur whenever the normal flow of a program is halted temporarily;
for example, to service an interrupt from a peripheral. Each ARM exception causes
the ARM processor to save some state information and then jump to a location in
low memory. Before an exception can be handled, the current processor state must
be preserved so the original program can resume when the handler routine has
finished.
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Working with the CPU
Exceptions
The AR M processor can be i nt erru pt ed b y se ven basic exceptio n s :
Reset exception. After a reset condition, th e ARM7TDM I saves the
current values of PC and CPSR, then changes the value of CPSR such
that ARM mode is re-established. The system then fetches the next
instruction from 0 x 00.
Undefined exception. The ARM7TDMI takes the undefined instruction
trap when it encounters an instruction it cannot handle. This exception
can extend either the Thumb or ARM instruction set by software
emulation.
SWI excepti on. The software interrupt instruction (SWI) is used to enter
supervisor mode, u sually to request a particular superv isor instruction.
Abort exception. An abort indicates that the current memory access
cannot be completed. There are two types of abort exception:
–Prefetch. Occurs during an in struction prefetch.
–Data. Occurs during a data operand access.
IRQ. The interrupt request (I RQ) exce ption is a normal interrupt
sourced b y the NET+50 interrupt cont rolle r.
FIRQ. The fast interrupt request (FIRQ) exception supports a data
transfer or channel process. Only the GEN module timers and GEN
modu le watch-dog timer can generate a FIRQ interrupt.
See Appendix A, "ARM Exc eptions" for more information ab out these exceptions.
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Exception priorities
Several exceptions can arise at the same time. If this happens, a fixed priority
system determ ines the order in which they are handled:
Highest Priority
1Reset
2Data Abort
3FIRQ
4IRQ
5Prefetch Abort
6Undefi ned instruction, SWI
Lowest Priority
Not all exception s can occur at the same time.
Undefined instructions and SWIs are mutually exclusive, since they
each correspond to particular (non-overlapping) decoding of the
current instruction.
If a data abort occurs at the same time as a FIRQ and the FIRQ is
enabled (that is, the CPSR F flag is clear), the data abort takes priority.
ARM7TDMI enters the data abort handler and then immediately
proceeds to the FIRQ vector. A normal r eturn from FIRQ causes the data
abort handler to resume execution.
Placing data abort at a higher priority than FIRQ is necessary to ensure
that the transfer error does not escape detection. The time for this
exception entry should be added to worst-case F IRQ la tency
calculations.
Exception vector table
All exceptions re sult in the ARM processor vectoring to an address in low memory,
using the exc e pt i on vect o r ta b l e. The exce ption vector ta bl e alway s exists and
always starts at base address 0.
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Working with the CPU
All internal NET+50 peripheral interrupts are presented to the CPU using the IRQ
or FIRQ interrupt inputs. The ARM can mask various NET+50 peripheral
interrupts at the global level, using the NET+50 interrupt controller. The ARM also
can mask interrupts at the micro-level, using configuration features with the
peripheral mo dules.
All IRQ interrupts are disab l ed when the I bit is set in the ARM CPSR register.
When the I bit is cleared, those interrup ts en abled in the NET+50 interrupt
controller can assert the IRQ input to the ARM processor.
When entering an interrupt service routine (ISR), the bit is automatically set by the
ARM processor . This disables recursive interrupts. The ISR’s first task is to read the
interrupt status register, which identifies all active sources for the IRQ interrupt.
The firmware, at bootup, sets the priorities for servicing interrupts, using the bits
defined in the interrupt status register.
Vector
address Vector Description
0x0 RESET Reset vector; for initializat ion and startup
0x4 Undefined Undefined instruction encountered
0x8 SWI Software interrupt; used for entry point into the kernel
0xC Abort (Prefetch) Bus error (no response or error) fetching instructions
0x10 Abort (Data) Bus error (no response or error) fetching data
0x14 Reserved Reserved
0x18 IRQ Interrupt from NET+50 interrupt controller
0x1C FIRQ Fast interrupt from NET+50 interrupt controller
Table 21: Excepti on vector table
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Entering and exiting an exception (software action)
The ARM7TDMI processor performs specific steps when handling exceptions.
Entering an exception
When an AR M exception occurs , the processor:
1Preserves the address of the next instruction in the appropriate link register,
irrespective of the state from the exception is entered.
–If the exception has been entered from ARM state, the address of the
next instruction is copied into the link register. The address is calculated
as:
FXUUHQW3& or
FXUUHQW3&
depending on the exception —
see Table 22, “Exception entry/exit,” on pag e 51).
–If the exception has been entered from Thumb state, the value written
into the link register is the current PC (program counter), offset by a
value that lets the program resume from the correct place on return
from the exception.
2Copies the CPSR into the appropriate SPSR.
3Forces the CPSR mode bits to a value that depends on the exception.
4Forces the PC to fetch the next inst ruction from the relevant exception
vector.
5Sets the I (for IRQ interrupts) or F (for FIRQ interrupts) bits to disable
interrupts to prevent unmana geable nesting of exception s.
Note: If the processor is in Thumb state when an exception occurs, it automatically
switches into ARM state when the PC is loaded with the exception vector address.
Exiting an Exception
On completion, the ARM processor:
1Moves the link register, minus the offset where appropriate, to the PC.
The offset value varies depending on the type of exception.
2Copies the SPSR back to the CPSR.
3Clears the in terrup t disable flags, if they were set on entry.
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Working with the CPU
An explicit switch back to Thumb state is never needed. Restoring the CPSR from
the SPSR automatically sets the T bit to the value it held immediately before the
exception.
Excep tion entry / ex it summary
Tab l e 22 summarizes the PC values preserved in the relevant link registers on
exception entry and provides the recommended instruction for exiting the
exc ep t i o n ha nd ler.
Notes:
1Where PC is t he address of the BL/SWI/undefined instr uction fetch that had
the prefetch abort. BL is a “branch with link” instruction.
Return
exception Return
instruction Previous state
ARM R14a_xb
a.R14 = Link Register
b._x = The previous state of th e processor
Previous state
Thumb
R14c_xd
c.R14 = Link Register
d._x = The previous state of th e processor
Notes
BL MOV PC, R14 PC + 4 PC + 2 1
RESET NA ——4
UNDEF MOVS PC,
R14_und PC + 4 PC + 2 1
SWI MOVS PC ,
R14_svc PC + 4 PC + 2 1
ABORT P SUBS PC,
R14_abt, #4 PC + 4 PC + 4 1
ABORT D SUBS PC ,
R14_abt, #8 PC + 8 PC + 8 3
IRQ SUBS PC ,
R14_abt, #4 PC + 4 PC + 4 2
FIRQ SUBS PC,
R14_abt, #4 PC + 4 PC + 4 2
Table 22: Excepti on entry/ex it
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2Where PC is the address of the instruction that did not get executed since
the FIRQ or IRQ took priority.
3Where PC is th e address of the loa d or store instruction that generated the
data abort.
4The value saved in 5BVYF upon reset is unpredictable.
Hardware interrupts
There are two wires that go into the AR M7CPU core that can interrupt the
processor:
IRQ (normal interrupt)
FIRQ (fast interrupt)
Although the interrupts ar e basically the same, FIRQ can interrupt IRQ.
The FIRQ and IRQ Lines
The FIRQ line adds a simple, two-tier priority scheme to the interrupt system.
Most sour ces of interrupts on the NET+50 come from the IRQ line. The only
potential sources for FIRQ interrupts on the NET+50 are the two built-in time rs
and the watch-dog timer; there is no way to generate a FIRQ signal externally.
These timers are controlled by registers in the GEN module (see "Timing
Registers," beginning on page 69):
The built-in timers are controlled using the timer control registers
([))%). The corresponding bit in the Interrupt Enable
register must be set for either IRQ or FIRQ to function.
The watch-dog timer is controlled using the System Control register
([))%).
Interrupts can come from many different sources on the NET+50. The GEN
module interrupt controller manages the interrupts (see "Interrupt generation and
control," beginning on page 93, for inf ormation). Inte rrup ts are enabled/disab l ed
on a per-sour ce basis using the Interrupt Enable Register ([))%). This
register serves as a mask for the interrupt sources and ultimately contr ols whether
an interrupt from a NET+50 module can reach the IRQ line.
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Working with the CPU
Read-only registers
There are two read-o nly registers in the i nt e r r u p t co nt roll e r:
The Interrupt Status Register Raw ([))%). Indicates the
source of a NET+50 interrupt regardless of the Interrupt Enable
Register’s state. All interrupts that are active in their respective module
will be visible in the Interrupt Status Register Raw.
The Inte rrupt Status Regis t er Enabled ([))%). Identifies the
current state of all interrupt sources that are enabled. The register is
defined by performing a logical AND of the Interrupt Status Register
Raw and the Interrupt Enable Register. All the bits in the Interrupt
Status Reg ister Enable d ar e ORed together and the output is fed directly
to the IRQ line, which then interrupts th e ARM.
See "Interrupt generation and control," beginning on page 93, for more information
about these registers.
Interrupt sources
Interrupt sour ces include the following:
DMA interrupts. DMA channels 1-10, including the four sub-channels
of the Ethernet receiver. (See Chapter 9, "DMA Controller Module.")
MIC interrupts. The MIC can be operated in one of two modes: IEEE
1284 or ENI host mode. Interrupts are handled differ ently for each mode.
(See Chapter 12, "MIC Controller Module.")
Ethernet receive and trans mit. These interr upts ar e used only when the
Ethernet receiver/transmitter ar e in interrupt mode instead of DMA
mode. Ethernet interrupts are part of the Ethernet General Status
register ([)). (See Chapter 10, "Ethernet Controller
Module.")
Serial interrupts. There are many sources for serial interrupts. (See
Chapter 11, "Serial Controller Module.")
Watch-dog timer interrupts. When the wat c h-dog tim er exp i res , t he
system can gen erate either an IRQ interrupt, a FIRQ interrupt, or a
sys tem re set. (S ee the di scussi on of th e Timer re gister s in Cha pter 6, "The
GEN Module.")
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Tim e r 1 and Timer 2 interrupts. Two types of interrupts can be
generated by Timers 1 and 2. The type of interrupt is configured in the
timer control register (0xFFB0 0010/18) while the interrupt itself is
contained within the Timer Status register (0xFFB0 0014/1C). See the
discussion of the Timer Control and Timer Status regi sters in Chapter 6,
"The GEN Module.")
POR TC interrupts. The lower four pins of POR TC on the NET+50 can be
used as interrup t sources (C3, C2, C1, C0). (See the discussion of the
PORTC register in Chapter 6, "The GEN Module.")
Each of these sources is enabled/disabled within their re spective module (and
sub-modules) within the NET+50 ASIC; the interrupt con troller in the GEN
module, however, does not latch any of the interrupt signals.
Causes of inte rrup ts are latched in thei r respective sub-module until cleared.
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BBus Module
CHAPTER 5
This chapter describes the BBus module, which provides the data path between
the NET+50 internal modules.
Note:
The information in this chapter applies to both the NET+50 and
NET+20M chips, unless otherwise noted.
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BBus func tionality
BBus functionality includes:
Addr ess and mult iplexi ng logic that suppo rts t he data f low through the
NET+50 chip.
Central arbiter for all NET+50 bus masters. The CPU, DMA, MIC, and
BUS modules are all potential BBus masters. The BBus arbiter prevents
one bus master from obtaining consecutive back-to-back cycles while
another bus master is waiting. See "Cycles and BBus arbitration" on
page 56 for more information.
Internal register d ecoding f or all addressable modules. Each m odule is
given a small portion of the system address map for configuration and
status. See "Address decoding" on page 57.
Cycles an d BBus ar bitration
BBus mast ers are given owners hip in a round- robin manner. As a rule, if a
potential bus doe s not requir e the BBus r esources when its turn c omes around, that
bus is skipped until the next round-robin slot.
During a normal ( normal operand) cycle, each bus master cyc l e is allowed only
one read/ wr it e c yc l e i f an o t her bus master is wa i ti ng . Th ere are two ex c ep ti o ns to
this rule: burst transactions and read-write-modify transactions.
Order of arbitration
The order of arbitr at i o n b e tween th e bus masters i s CP U → DΜΑ → ΕΝΙ → BUS.
The BBus arbiter maintains the top-level round-robin arbitration loop; the DMA
controller maintains its own round-robin arbitration loop for the different DMA
channels.
You should expect an access pattern similar to this:
>&38@>'0$@>0,&@>&38@>'0$@>0,&@
This pattern expands as shown:
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BBus Module
>&38@>(5;'0$@>0,&@>&38@>(7;'0$@>0,&@
Not e t ha t th e expand ed p at t e r n is th e i deal r e p resen t a ti o n. The DMA channel is
governed by two mechanisms: the internal arbitration mechanism and the
context-switching mechanism. The context-switching mechanism incurs a penalty
of 13 clock cycles to switch from one channel to another, which can cause delays.
The access pattern is more likely to appear as:
>&38@>(5;'0$@>0,&@>&38@>0,&@>&38@>(7;'0$@
To properly budget the bandwidth between various modules, you must r ecognize
the limitations placed on the bus by arbitration algorithms and context-switch
delays. The sizes of the peripheral FIFOs have an impact on budgeting also, as
does control of burst acce ss modes, CPU cache, and DMA d uplex settings.
Address decoding
The CPU address map is divided to allow access to the various internal modules
and external resources routed through the internal peripherals, as shown in
Table 23.
All resourc es defined in this manner are addressed using the upper memory
addresses. Each internal module is given 1 Mbyte of addr es s space for its own
internal decoding. Each module defines its own specific register map.
Address range Module
0x0000 0000 - 0xFF7F FFFF BUS module
0xFF80 0000 - 0xFF8F FFFF EFE module
0xFF90 0000 - 0xFF9F FFFF DMA module
0xFFA0 0000 - 0xFFAF FFFF MI C module
0xFFB0 0000 - 0xFFBF FFFF GEN module
0xFFC0 0000 - 0xFFCF FFFF MEM module
0xFFD0 0000 - 0xFFDF FFFF SER module
0xFFF0 0000 - 0xFFFF FFFF Cache RAM
Table 23: BBus address de coding
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The BBus module does not allow access to any internal registers unless the
&38B6839 signal is active, which indicates that firmware is executing in supervisor
mode. The System Control register provides an override signal (the USER bit in
the GEN System Control register) to allow access to internal registers in user
mode.
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The GEN Module
CHAPTER 6
The GEN (General) module provides the NET+50 with its main system control
functions and an interrupt priority controller, as well as miscellaneous functions:
Two programmable timers with interrupt support
One prog rammab le bus-error timer
One programmable watch-dog timer
Three 8-bit programmable parallel I/O ports with interrupt support
Note:
The information in this chapter applies to both the NET+50 and
NET+20M chips, unless otherwise noted.
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Module configuration
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Module configuration
The GEN module is configured as follows:
A note about interrupts
The type of interrupt produced and the length of the watch-dog timer is
configured using the System Control r egister. The watch-dog is strobed using the
Software Service register. The corresponding bit in the Interrupt Enable register
must be set for either IRQ or FIRQ to function. See the appropriate discussions for
more information.
Address Register
0xFFB0 0000 System Control register
0xFFB0 0004 System Status register
0xFFB0 0008 PLL Control register
0xFFB0 000C Software Service register
0xFFB0 0010 Timer 1 Control register
0xFFB0 0014 Timer 1 Status regist er
0xFFB0 0018 Timer 2 Control register
0xFFB0 001C Timer 2 Status regist er
0xFFB0 0020 PORTA register
0xFFB0 0024 PORTB register
0xFFB0 0028 PORTC register
0xFFB0 0030 Interrupt Enable register
0xFFB0 0034 Interrupt Enable register – SET
0xFFB0 0038 Interrupt Enable register – CLEAR
0xFFB0 0034 Interrupt Status register – Enabled
0xFFB0 0038 Interrupt Status register – Raw
Table 24: GEN module address map
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The GEN Module
GEN module hardware initialization
Many internal NET+50 configuration features ar e application-specific and need to
be configured at powerup before the CPU begin s executing boot- u p cod e. System
bus address bits are used to do this during a powerup reset. The NET+50 provides
internal pull-up resistors on all address lines. Weak external pull-down r esistors
can b e used to c on fi g ure i n te r nal r e gi ster bi t s to a zer o st a t e.
Table 25 specifies which system bus addr ess bits control which GEN module
functions.
NET+50 chip bootstrap initialization
Many internal NET+50 chip configuration features are application-specific and
need to be co nfigured at pow erup before the CP U boo t s. The sy st e m b us add ress
bits are used for this purpose during a powerup reset. The NET+50 provides
internal pull- up r esistors on all addr ess signal s. Weak external pull-dow n re sistors
can be used to configure dif ferent internal register bits to a zero state.
Table 26 specifies which ADDR bits control which functions during bootstrap
initialization:
Address bit Function Setting
ADDR27 GEN_LENDIAN 0 - Little Endian configuration
1 - Big Endian configuration
Note: The inverte d ENDIAN bi t
ADDR27
is
loaded i n to th e LE NDIAN bit wi th i n th e System
Control register. In the System Control register,
LENDIAN=1 for Little Endian mode and
LENDIAN=0 for Big Endian mode.
ADDR26 GEN_BUSER Must be set to 1 — ARM CPU enabled;
GEN_BUSER set to 0.
ADDR25 GEN_IARB Must be set to 1 — internal system bus arbiter.
ADDR19:09 GEN_ID Product identification code
Table 25: ADDR bi ts/function control
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Address bit Function
ADDR[27] Endian configuration
0 - Little Endian configuration
1 - Big Endian configuration
The inverted ENDIAN bit (ADDR7) is loaded into the LENDIAN bit
within the system control register, where:
LENDIAN=1 (for Little Endian mode)
LENDIAN=0 (for Big Endian mode)
ADDR[26] CPU bootstrap. Must be set to 1.
ADDR[25] GEN_IARB setting. Must be set to 1.
ADDR[24:23] CS0 bootstrap setting
00 – Bootstrap disabled
01 – 32-bit SRAM port; 15 wait-states
10 – 32-bit DRAM port; 15 wait-states
11 – 16-bit SRAM port; 15 wait-states
ADDR[22:20] MIC MODE[2: 0] configurat ion bits
ADDR[19:09] GEN_ID setting
ADDR[8] Reserved
ADDR[07] MIC control PSIO*
0 = PSIO
1 = Normal
The inverted PSIO address bit (ADDR07) is loaded into the PSIO
configuration bit within the ENI Con tr ol register, where:
0=Normal
1=PSIO)
ADDR0[6] ENI Control WR_OC
ADDR[05] ENI Control DINT2*
ADDR[04] ENI Control I_OC
ADDR[03 ENI Control DMAE*
ADDR[02] Reserved
ADDR[01] ENI Control EPACK*
ADDR[00] ENI Control PULINT*
Table 26: GEN modul e ADDR bit functi on control
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The GEN Module
System registers
The GE N mod u l e uses two sys t em regi st er s :
System Control register. 32-b it read/write register. Al l control bits are
active hig h unless an aster isk (* ) appea rs in the signal name; an aster isk
indicates active low. All control bi ts are set to their respecti ve inactive
state on reset.
System Status register. 32-bit register. All bits in this register, except
LOCK, are loaded only during a hardware reset. The GEN_ID value is
not affected when an external jumper is changed — unless a hardware
reset is execut ed fir st. The LO CK bit is dy namic and changes.
System Control register
Code
(Bit #) Definition of
Code Description
LENDIAN
(D31) Configure chip to
run in Little
Endian mode
0 - Configures the NET+50 to run in Big Endian mode
1 - Configures the NET+50 to operate in Little Endian mode
Controls the Endian configuration for the NET+50 chip. During reset,
the LENDIAN bit defaults to the value defined by the inverted
ADDR27 bit (see "GEN module hardware initialization" on page 61).
Table 27: System Control register bit description
15 14 13 12 11 10 98765
43210
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
0
R/W
LENDIAN BSPEED
0
R/W
BME
0
R/W
USER IARB DMAT ST
0
R/W
BUSER DMARST
RW R/W
SWE
BSYNC
0
R/W
BCLKD SWRI SWT BMT
Address = FFB0 0000
0
R/W
0
R/W 0
R/W
R/W 0
R/W
0
R/W 0
R/W
TEALAST -- -- -- -- --
------ --
ADDR27
ADDR26 ADDR25 0
R/W 0
R/W
MISALIGN -- --
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BSPEED
(D30:29) BUS speed
configuration 00 - 1/4 speed
01 - 1/2 speed
10 - Full speed
11 - Reserved
Controls the speed of the system bus clock (BCLK) relative to the
speed of the internal system clock (SYSCLK ). BCLK can be
configured to operate at 1/4 speed, 1/2 speed, or full speed.
BCLKD
(D28) BCLK output
disable 0 - BCLK output enabled
1 - BCLK output forced to LOW state
Shuts down the operation of the BCLK signal. Turning off the BCLK
signal minimizes electro-magnet ic interfer ence (E MI) when the
BCLK signal is not required for the application.
SWE
(D24) So ftw a re wa tch -
dog enable Set to 1 to enable the watch-dog timer circuit. The watch-dog timer
can be configured, using SWRI, to generate an interrupt or reset
condition if and when the watch-dog timer expires. Once the SWE bit
is set to 1 , onl y a ha rdware rese t sets the bi t b ac k to 0 .
SWRI
(D23:22) Software wa tch -
dog reset/
interrupt select
00 - Software watch-dog causes normal (IRQ) interrupt
01 - Software watch-dog causes fast (FIRQ) interrupt
10 - Software watch-dog causes reset
11 - Reserved
Controls the action that occurs when the watch-dog timer expires.
The watch-dog can be configured to generate a normal interrupt
condition, a fast interrupt condition, or a reset condition.
SWT
(D21:20) Software wa tch -
dog timeout (in
seconds)
00 - 220/FXTAL
01 - 222/FXTAL
10 - 224/FXTAL
11 - 225/FXTAL
Controls the timeout period for the watch-dog timer. The timeout
period is a function of the FXTAL value. Se e "Internal XTAL clock
reference" on page 99 for information about the FXTAL value.
Code
(Bit #) Definition of
Code Description
Table 27: System Control register bit description
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The GEN Module
BME
(D18) Bus monitor
enable 0 - Disable bus monitor operation
1 - Enable bus monitor operation
Set to 1 to enable the bus monitor timer. Required to avoid a system
lockup condition that can occur when a bus master attempts to
address a memory space that is not decoded by any peripheral.
The bus monitor timer detects when a bus master is accessing a
peripheral and there is no transfer acknowledge (TA*) response.
When the bus monitor timer expires, the current bus cycle is
immediately terminat ed and the current s ystem bus master is issued a
data abort indicator.
BMT
(D17:16) Bus monitor
timer 00 - 128 BCLKs
01 - 64 BCLKs
10 - 32 BCLKs
11 - 16 BCLKs
Controls the timeout period for the bus monitor timer. The BMT field
generally is set to its maximum value, but it can be set to a lower value
to minimize the latency when issuing a data abort signal. The BMT
field needs to be set to a value that is larger than the anticipated
longest access time for all peripherals.
USER
(D15) Enable access to
internal chip
registers in CPU
user mode
Controls whether applications operating in ARM user mode (as
opposed to supervisor mode) can access internal registers within the
NET+50 chip.
If the USER bit is set to 0 and an application, operating in ARM
user mode, tries to access (read or write) an internal NET +50
register, the application receives a data abort.
When the USER bit is set to 1, any application can access the
NET+50 internal registers.
BUSER
(D14) Enable ARM
CPU Must be set to 0.
During reset, BUSER defaults to the value defined by ADDR26 (see
"GEN module hardware initialization" on page 61).
IARB
(D13) Define system
bus to internal
arbiter
Must be set to 1.
During reset, IARB defaults to the value defined by ADDR25 (see
"GEN module hardware initialization" on page 61).
Code
(Bit #) Definition of
Code Description
Table 27: System Control register bit description
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System registers
66 n n n n n n n
NET+50/20M Hardware Reference
DMATST
(D12) DMA module test
mode 0 - Test mode disabled
1 - Allow unrestricted access to DMA context RAM
Resets the DMA controller subsystem. Also used to allow the ARM
processor direct access to the internal context RAM found in the
DMA controll er.
When th e DM ATST bit is set to 1 , t h e DMA control ler
subsystem is held in reset and the ARM processor can access all
the internal DMA context RAM. This is useful for diagnostic
purposes.
When th e DM ATST bit is set to 0 , t h e DMA control ler
subsystem operates normally. Only the bits in the DMA control
register space can be accessed by the ARM processor.
TEALAST
(D11) Bus inter face
TEA/LAST
configuration
0 - Use TEA_pin for error indication only
1 - Use TEA_ pin for LAST word of burst sequence indicator and
error indication
Determines how the NET+50 will use the TEA* signal.
When TEALAST is set to 0, the TEA* signal is used only to
indicate a data abort.
When TEALAST is set to 1, the TEA* signal is used in
conjunction with the TA* signal to indicate either a data abort or
a burst completion.
MISALIGN
(D10) Bus er ro r on
misaligned cycles 0 - Disable misaligned data transfer bus abort generation
1 - Generate a bus abort during a misaligned transfer
When set to 1, misaligned address transfers cause a data abort to be
issued to the offending bus master. A misaligned address transfer is
defined as a half word access to an odd byte address boundary or a
full word access to either a half word or byte address boundary. This
bit is useful during software debugging to detect misaligned cycles.
DMARST
(D06) DMA module
reset 0 - DMA module operational
1 - DMA module reset
Provides a way to issue a soft reset to the DMA module without
affecting any other modules.
Setting the DMARST bit to 1 causes the DMA module to be
held in reset.
Setting the DMARST bit to 0 allows the DMA module to
operate.
Code
(Bit #) Definition of
Code Description
Table 27: System Control register bit description
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The GEN Module
System Status register
BSYNC
(D05:04) TA* input
synchronizer 00 - 1-stage synchronizer
01 - 1-stage synchronizer
10 - 2-stage synchronizer
11 - No synchronizer
Defines the level of synchronization performed within the NET+50
chip for the TA* input. The NET+50 can process the TA* input signal
using a 1-stage flip-flop synchronizer, a 2-stage synchronizer, or no
synchronizer. The 1- or 2-stage synchronizer must be used if the TA*
input is asynchronous to the BCLK signal. The 2-stage synchronizer
is better, however, as it introduces one additional BCLK of latency in
the access cycle.
If no synchronizer is used, the TA* input must be synchronous to the
BCLK signal and may not operate at or near 44 MHz. This level is not
recommended.
Code
(Bit #) Definition of
Code Description
Table 27: System Control register bit description
Code
(Bit #) Definition of
code Description
REV
(D31:24) NET+ARM chip
revision ID Identifies the version of the NET+ARM chip and its revision. All
NET+ARM chips have a REV identification (see Table 29 on
page 68.)
Table 28: System Status register bit desc ription
0
R
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Address = FFB0 0004
REV EXT POW SW RSTIO LOCK
GEN_ID
0
R0
R0
R
0
R0
R
-- ----
-- ------ --
ADDR19...ADDR9
R
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System registers
68 n n n n n n n
NET+50/20M Hardware Reference
EXT
(D32) Last reset caus e d
by external reset Indicate s that the RE SET* pin was used to cause the last hardw are
reset condition. This bit is set/reset during every hardware reset
condition.
POW
(D22) Last reset caus e d
by powerup reset Indicates that a powerup reset caused the last hardware reset
condition. The POW bit is set/reset during every hardware reset
condition.
SW
(D21) La st re set caused
by software
watch-dog timer
Indicates that a software watch-dog timeout caused the last hardware
reset condition. The SW bit is set/reset during every hardware reset
condition.
RSTIO
(D20) Last reset caus e d
by ENI RSTIO
control
Indicates that the RSTIO bit in the ENI Shared register caused the last
hardware reset condition. The RSTIO bit is set/reset during every
hardware reset condition.
LOCK
(D16) System PLL in
Lock st at e Indicates that the internal phase lock loop (PLL) is currently in a Lock
condition.
GEN_ID
(D10:00) Product ID
defined by
external resistor
jumpers
During reset, defaults to the value defined by ADDR19:09 bits (see
"GEN module hardware initialization" on page 61). The GEN_ID is
loaded only once during a hardware reset condition.
NET+50 chip device Rev I Ds
NET+5 & 10 0x00
NET+12-1 0x01
NET+15-0 0x04
NET+15-1 0x05
NET+15-2 0x06
NET+15-3 0x07
NET+15-4 0x07
NET+40-0 0x08
NET+40-1 0x09
Table 29: NET+ARM chip devices and revision IDs
Code
(Bit #) Definition of
code Description
Table 28: System Status register bit desc ription
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The GEN Module
PLL
PLL comes up for hardware reset to allow the internal system clock (SYSCLK) to
run at 44.3MHz. If you need to use a different frequency for SYSCLK, you must
use a different external configuration; that is a crystal with a different output
frequency and/or an external oscillator.
Timing Registers
The NET+50 uses four timing registers:
Software Service register
6:65
. Ackno wled ges the syst em wat ch-do g
timer. To do so, firmware must write $5A and $A5 to the SWSR using
two separate write operations. There is no restriction on the time
between the two operations, but the two operations must occ ur in the
proper sequence with the proper data values.
The SWSR is also used to request a software reset of the NET+50 chip
hardware. To request a soft reset, firmware must write $123 and $321 to
the SWSR using two separate write operations. Again, there is no
restriction on the time between the two operations and the two
operations must occur in the proper sequence with the proper data
values.
Tim e r Control registers
7LPHUDQG7LPHU
. 32-bit register(s) u sed
to provide the CPU with programmable interval timers. The timers
NET+40-2 0x0A
NET+40-3 0x0B
NET+40-4 0x0B
NET+50-1 0x19
NET+50-3 0x1B
NET+50 chip device Rev I Ds
Table 29: NET+ARM chip devices and revision IDs
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Timing Registers
70 n n n n n n n
NET+50/20M Hardware Reference
operate using the external crystal clock and an optional 9-bit prescaler.
The timers provide a 27-bit pr ogrammable down-counter mechanism.
An initial count register is loaded by the CPU to define the timeout
period. When the current counter decrements to zero, an interrupt is
provided to the CPU and the counter is reloaded. The current coun t
value can be read by the CPU at any time.
The effective value of the timeout is determined by these equations:
7,0(287 >7&@);7$/ 7&/. 735(
7,0(287 >7&@);7$/ 7&/. 735(
7,0(287 >7&@)6<6&/. 7&/. 735(
7,0(287 >7&@)6<6&/. 7&/. 735(
All bits are set to 0 on reset.
T imer Status register . 32-bit re ad-only register. The TIP (T imer Interrupt
Pending) bit is set when the current timer count register decrements to
zero. If the TIE (Timer Interrupt Ena bled) b it is set in the Timer Control
register, the CPU is interrupted. The TIP bit is cleared by writing a 1 to
the respective bit position on this regi ster.
Softwa re Se rvice regist er
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Addres s = FFB0 000 C
0
W
SWSR
0
W
SWSR
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The GEN Module
Timer Control registers
Code
(Bit #) Definition of
code Description
TE
(D31) Ti me r ena b l e Mu st b e se t to 1 t o al low the t im er to operate. Setting th e T E bi t t o 0
resets the timer and prevents it from operating. The other fields in this
register should be configured before or during the same memory
cycl e in w hic h T E is set to 1.
TIE
(D30) Timer interrup t
enable Can be set to 1 to allow the timer to interrupt the CPU. A timer
interrupt is generated when the TIP bit is set in the timer status
register.
TIRQ
(D29) Timer inte rrupt
mode 0 – Normal interrupt
1 – Fast interrupt
Controls the type of interrupt the timer will trigger. The Timer can
generate either a normal interrupt (ARM IRQ pin) or a fast interrupt
(ARM FIRQ pin).
TPRE
(D28) Timer prescaler 0 – Disable 9-bit prescaler
1 – Enable 9-bit prescaler
Determines whether the 9-bit prescaler is used in calculating the
TIMEOUT parameter. Using the prescaler allows for longer values of
TIMEOUT.
TCLK
(D27) Timer clock
source 0 – Use FXTAL as timer clock source
1 – Use FSYSCLK as timer clock source
Selects the reference clock for the timer module. The reference clock
can be based off the FXTAL clock or the FSYSCLK clock.
Table 30: Timer Cont rol register bit de finition
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Addres s = F FB0 0010 / 18
0
R/W
ITCTE TIE TIRQ TPRE TCLK
0
R/W 0
R/W 0
R/W 0
R/W 0
R/W
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Timing Registers
72 n n n n n n n
NET+50/20M Hardware Reference
)
;7$/
)
&5<67$/
)
;7$/
+]
Timer Status regi ster
ITC
(D26:00) Initial timer count Defines the TIMEOUT parameter for interrupt frequency. The
TIMEOUT period is a function of the FXTAL frequency. (See "System
clock generation" on page 97.) The effective value of the timer
TIMEOUT is determined by these equations:
7,0(287 >7&@);7$/ 7&/.
735(
7,0(287 >7&@);7$/7&/.
735(
7,0(287 >7&@)6<6&/.7&/.
735(
7,0(287 >7&@)6<6&/.7&/.
735(
Using an 18.432 crystal as an example, Table 31 identifies the
possible minimum and maximum values of the timers.
TPRE = 0 TPRE = 1
ITC = 0 ITC = 511 ITC = 0 ITC = 511
2 µS 1.1 mS 1.1 mS 568 mS
Table 31: Minimu m and max imum timer v alues
Code
(Bit #) Definition of
code Description
Table 30: Timer Cont rol register bit de finition
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Address = FFB0 0014 / 1C
0
R
CT CTIP
0
R/C
-- --
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The GEN Module
General Purpose I/O (GPIO) Registers
The GEN module provides registers to configure the personality of each set of
general purpose I/O pins:
PORTA register. Configur es each of the eig ht PORTA pins. All pins can
be configured for general purpose I/ O, as well as for spe cial functions.
PORTB register. Configures each of the eight PORTB pins. All pins can
be configured for general pur pose I/O as well as for special functions.
PORTC register. Configu res each of the eight PORTC pins. All pi ns can
be configured for general purpose I/ O, as well as for spe cial functions.
Important:
The NET+50 chip uses all 24 GPIO port pins. The NET+20M chip
uses only 16 pins. You can us e any combinatio n of pins from the
three ports, in both GPIO mode and special function mode, as long
as you use only 16 pins.
Code
(Bit #) Definition of
code Description
TIP
(D30) Timer interrup t
pending Set to 1 when t he timer i s enabled and the C TC val ue reaches 0. The
TIP can be used to generate an interrupt to the CPU as long as the TIE
bit is set in the Timer Control register. Writing a 1 to the same bit
position in this register clears the TIP bit.
Note: The TIP bit is immediately set when the TE bit is changed from
0 to 1. This is because the CTC field initially star ts out at zero, which
means an interrupt occurs immediately af ter TE transiti ons from 0 to
1. If this initial interrupt causes a problem in any specific application,
the software must be designed to ignore the first interrupt.
CTC
(D26:00) Cu rrent ti mer
count Current timer count. Each time the CTC field reaches zero, the TIP
bit is set and the CTC is reloaded with the value defined in the ITC
field. The CTC continues to count back down to 0. The TIP bit can be
used to generate an interrupt to the CPU.
Table 32: Timer Status register bit definition
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General Purpose I/O (GPIO) Registers
74 n n n n n n n
NET+50/20M Hardware Reference
PORTA Register
You can program each of the PORTA GPIO pins to be one of the following, as
applicable:
General purpose input
General purpose output
Special function input
Special function output
Table 33: "PORTA configuration" describes the possible configurations for each of
the PORTA signals. Each column in the table denotes one of the four possible
configurations for each bit. If there is no entry in one of the columns (for example,
3257$!$02'( !$',5
), the bit cannot be used in that configuration.
The MO D E f i eld i n t he PORTA regi st er (see page 78) deter mi ne s wh i ch PO RTA
bits are configured for GPIO and which are configured for special function. The
DIR field in the PORTA register controls the direction of the configuration.
When the MODE bit is set to 0, the bit is configured for GPIO.
When the MODE bit is set to 1, the bit is configured for special function.
When the DIR bit is set to 0, the bit is configured for input mode.
When the DIR bit is set to 1, the bit is configured for output mode.
PORTA Bit GPIO mode Special function mode
AMODE=0 AMODE=1
ADIR=0 ADIR=1 ADIR=0 ADIR=1
PORTA7 GPIO IN GPIO OUT TXDA
PORTA6 GPIO IN GPIO OUT DREQ1* DTRA*
PORTA5 GPIO IN GPIO OUT RTSA*
PORTA4 GPIO IN GPIO OUT SPI-S-CLK-IN-A*
RXCA-IN SPI-M-CLK-OUT-A
RXCA-OUT
OUT1A*
PORTA3 GPIO IN GPIO OUT RXDA
Table 33: PORTA configuration
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The GEN Module
General purpose I/O
The bit is configured for GPIO when the MODE bit is set to 0. The DIR setting then
determines whether the bit is input or output mode.
When both MODE and DIR are set to 0, the PORTA bit is configured
in input mode. The NET+50 processor can read the current logic value
on the PORTA bit by reading the state of the respective bit in the DATA
field.
When the M ODE bit is set to 0 and the DI R bit is se t to 1, the PORTA
bit is configured in output m ode. The NET+50 processor can set the
current logic value on the PORTA bit by setting the state of the
respective bit in the DATA field. Reading the DATA field when
configured in output mode returns the current setting of the DATA
field.
Special function mode
Special function mode is used primarily for connecting the internal NET+50 serial
ports to the external interface pins. This mode pr ovides other featur es as well.
When the MODE bi t is set to 1 and the DIR bi t i s set to 0, t h e PORTA bit
is conf igured to operate in special fu nction input mode.
When both the MODE bit and the DIR bit are set to 1, the PORTA bit is
configured to operate in special function mode.
PORTA2 GPIO IN GPIO OUT DSRA* DACK1*
PORTA1 GPIO IN GPIO OUT CTSA*
PORTA0 GPIO IN GPIO OUT DCDA*
DONE-IN1* DONE-OUT1*
PORTA Bit GPIO mode Special function mode
AMODE=0 AMODE=1
ADIR=0 ADIR=1 ADIR=0 ADIR=1
Table 33: PORTA configuration
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General Purpose I/O (GPIO) Registers
76 n n n n n n n
NET+50/20M Hardware Reference
PORTA7
Provides the transmit data output function for serial port A. The TXDA signal is
used for serial transmit data when configured to operate in UAR T, SPI, or HDLC
modes.
PORTA6
Special function input: Provides the active low DMA request input for
DMA channel 3 or 5 when that DMA channel is configured for external
channel sourcing. Used only when the REQ bit is set to 1 in the DMA
Channel 3 or DMA Channel 5 Control register.
Special function output: Provides the data terminal ready (DTR) control
signal output for serial port A. Control Register A in the SER module
configurat ion cont r ols the stat e of DTR . The DT R sign al config urati on is
active high inside the NET+50 and active low outside the NET+50. The
GEN module perfor ms inver s ion before driving the PORTA6 I/O pad.
PORTA5
Provides the request to send (R TS) control signal for serial port A. Control Register
A in the SER module con figuration controls the state of RTS. The RTS signal
configuration is active high inside the NET+50 and active low outside the NET+50.
The GEN module performs inversion before driving the PORTA5 I/ O pad.
PORTA4
Special function input: Provides one of two serial channel A features,
depending on the configuration of the serial channel.
–When the serial channel is configured for SPI slave mode, PORTA4
special function input receives the SPI slave clock signal from the
PORTA4 pin.
–When the RXSRC bit is set to 1 in the Serial Channel Bit-Rate register,
the serial channel receiver clock (RXCA) will be accepted from the
PORTA4 pin.
Special function output: Provides one of three serial channel A features,
depending on the configuration of the serial channel.
–When the serial channel is configured for SPI master mode, PORTA4
special function output drives the SPI master clock signal out the
PORTA4 pin.
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The GEN Module
–When the serial channel is not configured for SPI Master mode and the
RXEXT bit in the Serial Channel Bit-Rate register is set to 1, the serial
channel receiver clock will be driven out the PORTA4 pin.
–When the serial channel is not configured for SPI master mode and the
RXEXT bit in the Serial Channel Bit-Rate Register is set to 0, the serial
channel general purpose OUT1 signal will be driven out the PORTA4
pin. Control Register A in the SER module configuration controls the
state of OUT1. The OUT1 signal configuration is active high inside the
NET+50 and active low outside the NET+50. The GEN module
performs inve rsion be fore driving the PORTA4 I/ O pad.
PORTA3
When configured for special func tion input, the PORTA3 signal provides the
receive data (RXD) signal for serial port A. The RXD signal is used for serial
receive data when configured to operate in UART, SPI, or HDLC modes.
PORTA2
Special funct ion input: Provid es the data set r eady (DSR) signal for seri al
port A. Status Register A in the SER module configuration returns the
state of RTS. The R TS sign al status is act ive hi gh i nsid e t he NE T+5 0 and
active low outside the NET+50. The GEN module performs inversion
after receiving the PORTA2 I/O pad.
Special function output: Provides the active low DMA acknowledge
(DACK1*) signal for DMA channel 3 or 5. DACK1 is driven active low
when DMA channel 3 or 5 is performing an external DMA cycle. DMA
acknowledge is used only when the REQ bit in the DMA Channel 3 or
DMA Channel 5 Control regist er is set.
PORTA1
Provides the clear to send (CTS) signa l for serial port A. Status Register A in the
SER module configuration returns the state of CTS. The CTS signal status is active
high inside the NET+50 and active low outside the NET+50. The GEN module
performs inve rsio n after receiving the PORTA1 I/O pad.
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General Purpose I/O (GPIO) Registers
78 n n n n n n n
NET+50/20M Hardware Reference
PORTA0
Special function input: Provides the data carrier detect (DCD) signal for
serial port A, as well as the active low DMA DONE signal for DMA
channel 3 or 5.
–DCDA*. Status register A in the SER module configuration returns the
state of DCD. The DCD signal status is active high inside the NET+50
and active low outside the NET+50. The GEN module performs
inversion after receiving the PORTA0 I/O pad. When the PORTB0 pin is
being used for the DMA DONE input, the DCD information in the SER
module must b e igno red.
–DONE1*. The DMA DONE signal is driven active low by an external
peripheral when DMA channel 3 or 5 is performing an external DMA
cycl e and t hi s cycle represen t s th e fi n al t r an sfer for a giv e n b lock fr o m
the external peripheral. DMA DONE is used only when the REQ bit is
set in the DMA Channel 3 or DMA Channel 5 Control r egister. The DMA
DONE input cau se s the current DMA buffer descriptor to close and
generates an interrupt to the software (under program control).
PORTA register and bit definitions
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Address = FFB0 0020
0
R/W
DIR
0
R/W
MODE
-- DAT A
0
R/W
-- -- -- -- -- -- --
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The GEN Module
PORTB Re gister
You can progr a m ea c h of the PORTB GPIO pins to be on e o f th e fo l l o wi ng , as
applicable:
General purpose input
General purpose output
Special function input
Code
(Bit #) Definition of
code Description
MODE
(D31:24) PORTA mode
configuration Used to individually configure each of the PORTA pins to operate in
either GPIO mode or special function mode.
0 – Selects GPIO mode
1 – Selects special function mode
Each bit in the MODE field corresponds to one of the PORTA bits.
D31 controls PORTA7, D30 controls PORTA6, and
so on.
DIR
(D23:16) PORTA data
direction Used to individually configure each of the PORTA pins to operate in
either input mode or output mode.
0 – Selects input mode
1 – Selects output mode
Each bit in the DIR field corresponds to one of the PORTA bits. D23
controls PORTA7, D22 controls PORTA6, and
so on.
DATA
(D07:00) PORTA data
register Used when a PORTA bit is configured to operate in GPIO mode.
Reading the DATA field provides the current state of the GPIO
signal, regardless of its configuration mode.
Writing the DATA field define s the current state of th e GPIO
signal when the signal is defined to operate in GPIO output
mode.
Writing a DATA bit when configured in GPIO input mode or
special function mode has no ef fect.
Each bit in the DATA field corresponds to one of the PORTA bits.
D07 controls PORTA7, D06 controls PORTA6, and
so on.
Table 34: PORTA register bit definition
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General Purpose I/O (GPIO) Registers
80 n n n n n n n
NET+50/20M Hardware Reference
Special function output
Table 35: "PORTB configuration" describes the possible configurations for each of
the PORTB signals. Each column in the table denotes one of the four possible
configurations for each bit. If there is no entry in one of the columns (for example,
3257%!%02'( !%',5
), the bit cannot be used in that configuration.
The MO DE field in t he POR TB r egister (see pag e 84) de termines whi ch POR TB bit s
are configured for GPIO and which are configured for special function. The DIR
field in the PORTB register controls the dir ection of the configuration.
When the MODE bit is set to 0, the bit is configured for GPIO.
When the MODE bit is set to 1, the bit is configured for special function.
When the DIR bit is set to 0, the bit is configured for input mode.
When the DIR bit is set to 1, the bit is configured for output mode.
PORTB Bit GPIO mode Special function mode
BMODE=0 BMODE=1
BDIR=0 BDIR=1 BDIR=0 BDIR=1
PORTB7 GPIO IN GPIO OUT TXDB
PORTB6 GPIO IN GPIO OUT DREQ2* DTRB*
PORTB5 GPIO IN GPIO OUT REJECT* RTSB*
PORTB4 GPIO IN GPIO OUT SPI-S-CLK-IN-B*
RXCB-IN SPI-M-CLK-OUT-B*
RXCB-OUT
OUT1B*
PORTB3 GPIO IN GPIO OUT RXDB
PORTB2 GPIO IN GPIO OUT DSRB* DACK2*
PORTB1 GPIO IN GPIO OUT CTSB* RPSF*
PORTB0 GPIO IN GPIO OUT DCDB*
DONE-IN2* DONE-OUT2*
Table 35: PORTB co nfiguration
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The GEN Module
General purpose I/O
Remember:
POR TB GPIO pins can be configured only in the NET+50 chip. If you
are using the NET+20M chip, only the special function pins can be
configured.
The bit is configured for GPIO when the MODE bit is set to 0. The DIR setting then
determines whether the bit is input or output mode.
When both MODE and DIR are set to 0, the PORTB bit is configured
in input mode. The NET+50 processor can read the current logic value
on the PORTB bit by reading the state of the respective bit in the DATA
field.
When the M ODE bit is set to 0 and the DI R bit is se t to 1, the PORTA
bit is configured in output m ode. The NET+50 processor can set the
current logic value on the PORTA bit by setting the state of the
respective bit in the DATA field. Reading the DATA field when
configured in output mode returns the current setting of the DATA
field.
Special function mode
Special function mode is used primarily for connecting the internal serial ports to
the external interface pins. This mode provides other features as well.
When the MOD E bit is set to 1 and the DIR bit is set to 0, the PORTB bit
is conf igured to operate in special fu nction input mode.
When both the MODE bit and the DIR bit are set to 1, the PORTB bit is
configured to operate in special function output mode.
PORTB7
Provides the transmit data (TXD) signal for serial port B. The TXD signal is used
for serial transmit data when configured to operate in UART , SPI, or HDLC modes.
PORTB6
Special function input: Provides the active low DMA request (DREQ*)
input signal for DMA channel 4 or 6 when that DMA channel is
configured for external channel sourcing. Used only when the REQ bit
is set to 1 in the DMA Channel 4 or DMA Channel 6 Control Register.
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Special function output: Provides the data terminal ready (DTR) signal
for serial port B. Control Register A in the SER module configuration
cont rols the state of DTR. The DTR signal configura tion is active high
inside the NET+50 and active low outside the NET+50. The GEN module
performs inve rsio n before driving the PORTB6 I/O pad.
PORTB5
Special funct ion input: Can be configured as the special function REJECT
input used by an external Ethernet address filtering block to force the
internal NET+50 chip Ethernet MAC to reject the current incoming data
packet. See Chapter 10, "Ethernet Controller Module" for more
information.
Special function output: Provides the request to send (RTS) signal for
serial port B. Control Register A in the SER module configuration
controls the state of RTS. The RTS signal configuration is active high
inside the NET+50 and active low outside the NET+50. The GEN
module performs inversion before driving the PORTB5 I/O pad.
PORTB4
Special function input: Provides one of two serial channel B features,
depending on the configuration of the serial channel.
–When the serial channel is configured for SPI slave mode, PORTB4
special function input receives the SPI slave clock signal from the
PORTB4 pin.
–When the RXSRC bit is set to 1 in the Serial Channel Bit-Rate register,
the serial channel receiver clock (RXCB) will be accepted from the
PORTB4 pin.
Special function output: Provides one of three serial channel B features,
depending on the configuration of the serial channel.
–When the serial channel is configured for SPI master mode, PORTB4
special function output drives the SPI master clock signal out the
PORTB4 pin.
–When the serial channel is not configured for SPI master mode and the
RXEXT bit in the Serial Channel Bit-Rate Register is set to 1, the serial
channel receiver clock will be driven out the PORTB4 pin.
–When the serial channel is not configured for SPI master mode and the
RXEXT bit in the Serial Channel Bit-Rate Register is set to 0, the serial
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The GEN Module
channel general purpose OUT1 signal will be driven out the PORTB4
pin. Control Register A in the SER module configuration controls the
state of OUT1. The OUT1 signal configuration is active high inside the
NET+50 and active low outside the NET+50. The GEN module
performs inversion before driving the P ORTB4 I/ O pad.
PORTB3
When configured for special function input, the PORTB3 signal provides the
receive data (RXD) signal for serial port B. The RXD signal is used for serial receive
data when configured to operate in UART, SPI, or HDLC modes.
PORTB2
Special funct ion input: Prov ides the data set r eady (DSR) signal for se rial
port B. Status Register A in the SER module configuration returns the
state of R TS. The RTS signal status is active high inside the NET+50 and
active low outside the NET+50. The GEN module performs inversion
after receiving the POR TB2 I/O pad.
Special function output: Provides the active low DMA acknowledge
signal (DACK2*) for DMA channel 4 or 6. The DACK2 is driven active
low when DMA channel 4 or 6 is performing an external DMA cycle.
DMA acknowle dge is used onl y when the REQ bit in the D MA Channel
4 or DMA Channel 6 Control register is set.
PORTB1
Special function input: Provides the clear to send (CTS) signal for serial
port B. Status Register A in the SER module configuration returns the
state of CTS. The CTS sig nal stat us is act ive high i nside t he NET+50 and
active low outside the NET+50. The GEN module performs inversion
after receiving the PORTB1 I/O pad.
Special function output: Can be configured for special function RPSF*
output used by external Ethernet address filtering logic to identify the
receive packet start of frame boundary. The filtering logic can use this
signal to determine when the destination address can be found in the
NET+50’s MII interface. See Chapter 10, "Ethernet Controller Module"
for more information.
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NET+50/20M Hardware Reference
PORTB0
Special function input: Provides the data carrier detect (DCD) signal for
serial port B, as well as the active low DMA DONE input signal for
DMA channel 4 or 6.
–DCDB*. Status Register A in the SER module configuration returns the
state of DCD. The DCD signal status is active high inside the NET+50
and active low outside the NET+50. The GEN module performs
invers ion after r eceiving the POR TB0 I/O pad. When the POR T B0 pin is
being used for the DMA DONE input, the DCD information in the SER
module must be ig nored.
–DONE2*. The DMA DONE signal is driven active low by an external
peripheral when DMA channel 4 or 6 is performing an external DMA
cycle and this cycle represents the final transfer for a given block from
the external peripheral. DMA DONE is used only when the REQ bit is
set in DMA Channel 4 or DMA Channel 6 Control register. The DMA
DONE input causes the current DMA buffer descriptor to close and
generates an interrupt to the software (under program control).
PORTB register and bit definitions
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Address = FFB0 0024
0
R/W
DIR
0
R/W
MODE
-- DAT A
0
R/W
-- -- -- -- -- -- --
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The GEN Module
Code
(Bit #) Definition of
code Description
MODE
(D31:24) PORTB mode
configuration
NET+50. Used to individually configure each of the PORTB
pins to operate in either GPIO mode or special function mode.
NET+20M. Must be set to 1 for special function mode.
Each bit in the MODE field corresponds to one of the PORTB bits.
D31 controls PORTB7, D30 controls PORTB6, and so on.
DIR
(D23:16) PORTB dat a
direction Used to individually configure each of the PORTB pins to operate in
either input mode or output mode.
0 – Selects input mode
1 – Selects output mode
Each bit in the DIR field corresponds to one of the PORTB bits. D23
controls PORTB7, D22 controls PORTB6, and
so on.
DATA
(D07:00) PORTB dat a
register Used when a PORTB bit is configured to operate in GPIO mode.
Reading the DATA field provides the current state of the GPIO
signal, regardless of its configuration mode.
Writing the DATA field define s the current state of th e GPIO
signal when the signal is defined to operate in GPIO output
mode.
Writing a DATA bit when configured in GPIO input mode or
special function mode has no ef fect.
Each bit in the DATA field corresponds to one of the PORTB bits.
D07 controls PORTB7, D06 controls PORTB6, and
so on.
Table 36: PORTB regi ster bit defi nition
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PORTC register
You can pr ogram each of the PORTC GPIO pins to be one of the following, as
applicable:
General purpose input
General purpose output
Special function input
Special function output
Table 37: "PORTC configuration" describes the possible configurations for each of
the PO RT C sig nals. Eac h col u mn in the t a b le d en ot e s on e o f th e fo u r possi bl e
configurations for each bit. If there is no entry in one of the columns (for example,
3257&!&02'( !&',5
), the bit cannot be used in that configuration.
The MODE field in the PORTC regist er (see page 92) determines which PORTC
bits are configured for GPIO and which are configured for special function. The
DIR field in the PORTC re gister controls the direction of the GPIO configuration.
When the MODE bit is set to 0, the bit is configured for GPIO.
When the MODE bit is set to 1, the bit is configured for special function.
When the DIR bit is set to 0, the bit is configured for input mode.
When the DIR bit is set to 1, the bit is configured for output mode.
PORTC
BIT GPIO Mode Special Function Mode
CMODE=0 CMODE = 1
CDIR=0 CDIR=1 CDIR=0 CDIR=1
PORTC7 GPIO IN GPIO OUT SPI-S-ENABLE-A*
TXCA-IN SPI-M-ENABLE-A*
TXCA-OUT
OUT2A*
PORTC6 GPIO IN GPIO OUT RIA* IRQ-OUT*
PORTC5 GPIO IN GPIO OUT SPI-S-ENABLE-B*
TXCB-IN SPI-M-ENABLE-B*
TXCB-OUT
OUT2B*
PORTC4 GPIO IN GPIO OUT RIB*
Table 37: PORTC co nfiguration
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The GEN Module
General purpose I/O
The bit is configured for GPIO when the MODE bit is set to 0. The DIR setting then
determines whether the bit is input or output mode.
When both MODE and DIR are set to 0, the PORTC bit is configured
in input m ode. The NET+50 processor can read the current logic value
on the PORTC bit by reading the state of the respective bit in the DATA
field.
When the M ODE bit is set to 0 and the DI R bit is 1, the PORTC bit is
configure d in output mode. The NET+50 processor can set the current
logic value on the PORTC bit by setting the state of the respective bit in
the DATA field. Reading the DATA field when configured in output
mode retu rns the current setting of the DATA fiel d.
Special function mode
Special function mode is used primarily for connecting the internal NET+50 serial
ports to the external interface p ins. This mode also provides other miscellaneous
features.
When the MODE bit is set to 1 and t h e DIR bit is set to 0, the PO RTC bit
is conf igured to operate in special fu nction input mode.
When both MODE and DIR are set to 1, the PORTC bit is configured to
operate in Special Function Output Mode.
Interrupts
PORTC is the only register that enables, generates, and clears interrupts.
PORTC3 GPIO IN GPIO OUT CI3-0 CI3-1
PORTC2 GPIO IN GPIO OUT CI2-0 CI2-1
PORTC1 GPIO IN GPIO OUT CI1-0 CI1-1
PORTC0 GPIO IN GPIO OUT CI0-0 CI0-1
PORTC
BIT GPIO Mode Special Function Mode
CMODE=0 CMODE = 1
CDIR=0 CDIR=1 CDIR=0 CDIR=1
Table 37: PORTC co nfiguration
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NET+50/20M Hardware Reference
To enable the interrupts, set the corresponding MODE bit to 1. The
interrupts are edge-sensitive, and the transition can be selected using the
DIR bit in the same register.
To generate an interrupt on a high-to-low transition, set the DIR bit to 0.
To generate a low-to-high t ransition, se t the DI R bit to 1.
For example, to enable C1 and C2 as low-to-high interrupts, write the
following:
[))% [
When an interrupt occurs, a 1 is stored in the corresponding data portion of the
same register. Clear the interrupt by writing a 1 to the same data bit. Be sure to use
caution when using external interrupts and GPIO.
Note: Writing 0 to the least significant 4 bits in this register has no effect.
PORTC7
Special function input: Provides one of 2 serial channel A features,
depending on the configuration of the serial channel.
–When the serial channel is configured for SPI slave mode, PORTC7
special function input receives the active low SPI slave enable signal
from the PORTC7 pin.
–When the TXSRC bit is set to 1 in the Serial Channel Bit-Rate register,
the serial channel A transmit clock (TXCA) will be accepted from the
PORTC7 pin.
Special function output: Provides one of 3 serial channel A features,
depending on the configuration of the serial channel.
–When the serial channel is configured for SPI master mode, PORTC7
special function output drives the active low SPI master enable signal
out the PORTC7 pin.
–When the serial channel is not configured for SPI master mode and the
TXEXT bit is set to 1 in the Serial Channel Bit-Rate register, the serial
channel transmit clock (TXCA) will be driven out the PORTC7 pin.
–When the Serial Channel is no t co nfigu red for SPI master mode and t he
TXEXT bit is set to 0 in the Serial Channel Bit-Rate register, the serial
channel general purpose OUT2 signal will be driven out the PORTC7
pin. Control Register A in the SER module configuration controls the
state of OUT2. The OUT2 signal configuration is active high inside the
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The GEN Module
NET+50 and active low outside the NET+50. The GEN module
performs inve rsion be fore driving the PORTC7 I/O pad.
PORTC6
Special function input: Provides the ring indica tor (RI) si gnal for serial
channel A. Status Register A in the SER module configuration returns
the state of RI. The RI signal status is active high inside the NET+50 and
active low outside the NET+50. The GEN module performs inversion
after receiving the PORTC6 I/O pad.
Special function output: Provides the IRQ-OUT* signal. The IRQ-OUT*
signa l provides an acti ve low interrupt request sign al, which indicates
that an active enabled interrupt is pending at the output of the GEN
module interrupt controller. The IRQ-OUT* signal emulates the same
signal given to the ARM processor, and is typically used in
environments where the NET+50 is used in the slave coprocessor
configuration and the internal ARM processor is disabled during
bootstrap.
PORTC5
Special function input: Provides one of 2 serial channel B features,
depending on the configuration of the serial channel.
–When the serial channel is configured for SPI slave mode, PORTC5
special function input receives the active low SPI slave enable signal
from the PORTC5 pin.
–When the TXSRC bit is set to 1 in the Serial Channel Bit-Rate register,
the serial channel B transmit clock (TXCB) will be accepted from the
PORTC5 pin.
Special function output: Provides one of 3 serial channel B features,
depending on the configuration of the serial channel.
–When the serial channel is configured for SPI master mode, PORTC5
special function output drives the active low SPI master enable signal
out the PORTC5 pin.
–When the serial channel is not configured for SPI master mode and the
TXEXT bit is set to 1 in the Serial Channel Bit-Rate register, the serial
channel transmit clock (TXCB) will be driven out the PORTC5 pin.
–When the serial channel is not configured for SPI master mode and the
TXEXT bit is set to 0 in the Serial Channel Bit-Rate register, the serial
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NET+50/20M Hardware Reference
channel general purpose OUT2 signal will be driven out the PORTC5
pin. Control Register A in the SER module configuration controls the
state of OUT2. The OUT2 signal configuration is active high inside the
NET+50 and active low outside the NET+50. The GEN module
performs inve rsion be fore driving the PORTC5 I/O pad.
PORTC4
Provides the ring indicator (RI) signal for serial channel B. Status Register A in the
SER module configuration returns the state of RI. The RI signal status is active high
inside the NET+50 and active low outside the NET+50. The GEN module performs
inversion after r eceiving the PORTC4 I/O pad.
PORTC3
When configured for special function mod e, the PORTC3 signal becomes an edge-
sensitive interrupt detector. When the corresponding DIR bit is set to 0, the
PORTC3 pin dete cts high-to-low transitions on PO RTC3 and asserts an interrupt
using the PORTC PC3 bit in the GEN module Interrupt Contr ol r egister. An active
high interrupt status condition is reported in the corresponding PORTC D3 bit
position. The interrupt condition is acknowledged by writing a 1 to the D3
position of the DATA field. A new interrupt will occur on the next high-to-low
transition on PORTC3. Low-to-high transitions can also be detected by setting the
corresponding DIR bit to 1.
POR TC3 can also be configured to provide the DRAM address multiplexer
fun cti on. Thi s feature is co nt roll e d by th e AMUX and AMUX2 bi t s in th e MEM
module configuration register.
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The GEN Module
PORTC2
When configured for special function mode, the PORTC2 signal bec o mes an edg e-
sensitive interrupt detector. When the corresponding DIR bit is set to 0, the
PORTC2 pin dete cts high-to-low transitions on PO RTC2 and asserts an interrupt
using the PORTC PC2 bit in the GEN module Interrupt Contr ol r egister. An active
high interrupt status condition is reported in the corresponding PORTC D2 bit
position. The interrupt condition is acknowledged by writing a 1 to the D2
position of the DATA field. A new interrupt will occur on the next high-to-low
transition on PORTC2. Low-to-high transitions can also be detected by setting the
corresponding DIR bit to 1.
PORTC1
When configured for special function mode, the PORTC1 signal bec o mes an edg e-
sensitive interrupt detector. When the corresponding DIR bit is set to 0, the
PORTC1 pin dete cts high-to-low transitions on PO RTC1 and asserts an interrupt
using the PORTC PC1 bit in the GEN module Interrupt Contr ol r egister. An active
high interrupt status condition is reported in the corresponding PORTC D1 bit
position. The interrupt condition is acknowledged by writing a 1 to the D1
position of the DATA field. A new interrupt will occur on the next high-to-low
transition on PORTC1. Low-to-high transitions can also be detected by setting the
corresponding DIR bit to 1.
PORTC0
When configured for special function mode, the PORTC0 signal bec o mes an edg e-
sensitive interrupt detector. When the corresponding DIR bit is set to 0, the
PORTC0 pin dete cts high-to-low transitions on PO RTC0 and asserts an interrupt
using the PORTC PC0 bit in the GEN module Interrupt Contr ol r egister. An active
high interrupt status condition is reported in the corresponding PORTC D0 bit
position. The interrupt condition is acknowledged by writing a 1 to the D0
position of the DATA field. A new interrupt will occur on the next high-to-low
transition on PORTC0. Low-to-high transitions can also be detected by setting the
corresponding DIR bit to 1.
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General Purpose I/O (GPIO) Registers
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NET+50/20M Hardware Reference
PORTC register and bit definitions
Code
(Bit #) Definition of
code Description
MODE
(D31:24) PORTC mode
configuration Used to individually configure each of the PORTC pins to operate in
either GPIO mode or special function mode.
0 – Selects GPIO mode
1 – Selects special function mode
Each bit in the MODE field corresponds to one of the PORTC bits.
D31 controls PORTC7, D30 controls PORTC6, and
so on.
DIR
(D23:16) PORTC dat a
direction Used to individually configure each of the PORTC pins to operate in
either input mode or output mode.
0 – Selects input mode
1 – Selects output mode.
Each bit in the DIR field corresponds to one of the PORTC bits. D23
controls PORTC7, D22 controls PORTC6, and
so on.
MODE2
(D11:08) PORTC mode 2
configuration Must be set to 0000 to ensure correct operation of the GPIO port. If
set to any other value, the port can behave unpredictably.
Table 38: PORTC regi ster bit defi nition
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Address = FFB0 0028
0
R/W
DIR
0
R/W
MODE
-- DAT A
0
R/W
-- -- --
0
R/W
MODE2
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The GEN Module
Interrupt generation and control
The five Interrupt Contro l registers allow you to define and r eview the behavior of
the NET+50’s Interrupt Controller. Th e I nterrupt Control registers are:
Interrupt Enable register
))%
. Standard read/write registe r
that can be updated in its entirety in a single write. When written to the
fields in this register, 1s enable the corresponding interrupts and 0s
disable them.
Interrupt Enable Register — Set
))%
. 32-bit write-only register.
This register sets specific bits without af fecting the other bits. Writing a 1
to a bit position in this register sets the respective bit in the Interrupt
Enable register. A zero in any bit position has no effect.
DATA
(D07:00) PORTC dat a
register Used when a PORTC bit is configured to operate in GPIO mode.
Reading the DATA field provides the current st ate of t he si gnal,
regardless of its configuration mode.
Writing the DATA field define s the current state of th e GPIO
signal when the signal is defined to operate in GPIO output
mode.
Writing a DATA bit when configured in GPIO input mode or
special function mode has no ef fect.
When the lower four bits are used in special function mode, the
corresponding DATA bits are used to indicate a pending interrupt
condition. Pending interrupts are latched when an edge transition is
detected. A pending interrupt is identified with a 1 in the DATA field.
Writing a 1 to the same bit position within the DATA field clears the
interrupt condition.
Each bit in the DATA field corresponds to one of the PORTC bits.
D07 controls PORTC7, D06 controls PORTC6, and
so on.
Code
(Bit #) Definition of
code Description
Table 38: PORTC regi ster bit defi nition
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Interrupt generation and control
94 n n n n n n n
NET+50/20M Hardware Reference
Interrupt Enable Register — Clear
))%
. 32-bit write-only
registe r. This register clears specific bits without affecting the other bits.
Writing a 1 to a bit position in this r egister clears the respective bit in the
Interrupt Enable register. A zero in any bit position has no effect.
Interrupt Status Register — Enable d
))%
. The read-only
personality of the Interrupt Enable Register — Set register. It identifies
the c urren t sta te of all t he en able d i nte rr upt sou r ces . Th e s our c es t hat ar e
not enabled are gated off by the Enable register, and therefore do not
appear in this register.
Interrupt Status Register — Raw
))%
. The read-only
personality of the Interrupt Enable Register — Clear register. It
identifies the current state of a ll int err u pt sources re ga rdless of whether
the interrupts are enabled.
These registers, al o ng wi t h t he NE T + 50’s Interrupt Controller, control the
generation and ha nd li ng of int e rrup ts . (See "Worki ng wi t h AR M exc eptions" on
page 46 for more informat ion.)
Interrupt Control register and bit definition
All five Interrupt Control registers use the same 32-bit register layout, as shown.
Code
(Bit #) Description
DMA 1
(D31) Corresponds to interrupts sourced by DMA channel 1. See Chapter 9, "DMA Controller
Module."
Table 39: Interrupt Control register bi t definition
DMA9
15 14 13 12 11 10 9876543210
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
0
R/W
DMA3
DMA1 ENET
RX
0
R/W
DMA2
0
RW
0
RW
SER 1
RX SER2
RX SER
TX Timer 1
0
R/W
0
R/W
0
R/W
SER 1
TX Watch
Dog
0
R/W 0
R/W 0
R/W
DMA8
Timer2
-- ----
0
R/W
--
DMA4 DMA5 DMA6 DMA7 DMA10 ENET
TX
PortC
PC3 PortC
PC2 PortC
PC1 PortC
PC0
Address = FFB0 0030
0
R/W 0
R/W
0
R/W 0
RW
0
R/W 0
RW
0
R/W
0
R/W 0
R/W
0
R/W
0
R/W 0
R/W
--
--
-- -- --
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The GEN Module
DMA 2
(D30) Corresponds to interrupts sourced by DMA channel 2. See Chapter 9, "DMA Controller
Module."
DMA 3
(D29) Corresponds to interrupts sourced by DMA channel 3. See Chapter 9, "DMA Controller
Module."
DMA 4
(D28) Corresponds to interrupts sourced by DMA channel 4. See Chapter 9, "DMA Controller
Module."
DMA 5
(D27) Corresponds to interrupts sourced by DMA channel 5. Chapter 9, "DMA Controller
Module."
DMA 6
(D26) Corresponds to interrupts sourced by DMA channel 6. Chapter 9, "DMA Controller
Module."
DMA 7
(D25) Corresponds to interrupts sourced by DMA channel 7. See Chapter 9, "DMA Controller
Module."
DMA 8
(D24) Corresponds to interrupts sourced by DMA channel 8. See Chapter 9, "DMA Controller
Module."
DMA 9
(D23) Corresponds to interrupts sourced by DMA channel 9. See Chapter 9, "DMA Controller
Module."
DMA 10
(D22) Corresponds to interrupts sourced by DMA channel 10. See Chapter 9, "DMA
Controller Module."
ENET RX
(D17) Corresponds to an interrupt sourced by the Ethernet receiver. See Chapter 10, "Ethernet
Controller Module."
ENET TX
(D16) Corresponds to an interrupt sourced by the Ethernet transmitter. See Chapter 10,
"Ethernet Controller Module."
SER 1 RX
(D15) The SER 1 RX bit position corresponds to an interrupt sourced by the serial channel A
receiver. See Chapter 11, "Serial Controller Module."
SER 1 TX
(D14) Corresponds to an interrupt sourced by the serial channel A transmitter. See Chapter 11,
"Serial Controller Module."
SER 2 RX
(D13) Corresponds to an interrupt sourced by the serial channel B receiver. See Chapter 11,
"Serial Controller Module."
SER 2 TX
(D12) Corresponds to an interrupt sourced by the serial channel B transmitter. See Chapter 11,
"Serial Controller Module."
Code
(Bit #) Description
Table 39: Interrupt Control register bi t definition
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NET+50 internal clock generation
96 n n n n n n n
NET+50/20M Hardware Reference
NET+50 internal clock generation
The NET+50 chip has three main clock domains:
SYSCLK — System clock. Drives the CPU and the NET+50 internal
logic.
XTAL — Bit-rate generation and programmable timer reference clock.
Defines the serial modules.
BCLK — System Bus Clock. Defines the speed of peripheral
communication.
Watch-Dog
(D6) Corresponds to an interrupt condition sourced by the watch-dog timer. See "System
Control register" on page 63 for details about the watch-dog timer.
TIMER 1
(D5) Corresponds to an interrupt condition sourced by the TIMER 1 module. See "Timer
Status register" on page 72 for details on timer interrupts.
TIMER 2
(D4) Corresponds to an interrupt condition sourced by the TIMER 2 module. See "Timer
Status register" on page 72 for details on timer interrupts.
PORTC P C3
(D3) Corresponds to an interrupt condition caused by an edge transition detected on the
PORTC3 pin. See "PORTC3" on page 90 for more information about the PORTC edge
detection interrupts.
PORTC P C2
(D2) Corresponds to an interrupt condition caused by an edge transition detected on the
PORTC2 pin. See "PORTC2" on page 91 for more information about the PORTC edge
detection.
PORTC P C1
(D1) Corresponds to an interrupt condition caused by an edge transition detected on the
PORTC1 pin. See "PORTC1" on page 91 for more information about the PORTC edge
detection interrupts.
PORTC P C0
(D0) Corresponds to an interrupt condition caused by an edge transition detected on the
PORTC0 pin. See "PORTC0" on page 91 for more information about the PORTC edge
detection interrupts.
Code
(Bit #) Description
Table 39: Interrupt Control register bi t definition
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The GEN Module
The SYS module generates thes e t hree clocks . Figure 8 shows the clock gene ration
circuit.
Figure 8: NE T+50 chip cloc k generation
System clock generation
The system clock is prov ided by an ex ternal crystal, an internal crystal oscillator,
and an internal phase locked loop (PLL). The crystal oscillator circuit generates an
internal CMOS transition clock signal. The clock signal from the crystal oscillator is
initially divided by 5 and provided as an input to the PLL.
PLLTST*
XTAL1
Crys tal
oscillator / 5 Phase
Lock Loop
Di vide by
n
PL L conf igur ation
BCLK conf igur ation
BCLK
XTAL
SYSCLK
Di vide by
n
0
1
/ 2
/ 4
2
1
0
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NET+50 internal clock generation
98 n n n n n n n
NET+50/20M Hardware Reference
The PLL is configured to operate in multiplier mode. The PLL output is fed back
through a divider, which allows the output to operate in a multiplier mode. The
system clock frequency i s 44.3 MHz.
Important: PLL comes up fo r hardwar e r eset to allow t he interna l system c lock (SYS CLK)
to run at 44.3MHz. If you need to use a different frequency for SYSCLK, you must use a
differ ent extern al configuration; that is a crystal with a differ ent o utput fr e quency and/or
an external oscillator.
The PLL can be disabled and bypassed (or isolated) by asserting the PLLTST* pin
active low. In this mode, the system clock is provided by the XTAL1 input. When
the PLL is bypassed, a digital signal is required on the XTAL1 input, similar to the
signal produced by an external CMOS clock source.
System clock frequency definitions
The system clock frequency is defined in one of two ways , depending on mode.
Inacti ve high . When PLLTST* is inactive high (PLLTST*= 1), system
clock frequency is defined as follows:
)
6<6&/.
)
&5<67$/
3//&17
where:
–FSYSCLK identifies the frequency for ARM processor operation.
–PLLCNT represents the value loaded into the PLLCNT field of the PLL
Contro l register (PLLCNT value is 9 by default).
–FCRYSTAL identifies the frequency of the external crystal component.
Active low. When PLL is bypassed (PLLTST* = 0), system clock
frequency is defined as follows:
)
6<6&/.
)
&5<67$/
where:
–FSYSCLK identifies the frequency for ARM processor operation.
–FCRYSTAL identifies the fr equenc y of the CMOS clock i nput o n the XTAL1
pin.
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The GEN Module
Internal XTAL clock reference
The internal XTAL clock signal is created by dividing the system clock by the same
value as is loaded in the PLL multiplier. The internal XTAL clock signal is always
1/5th the frequency of the crystal input, irrespective of the PLL setting. The
internal XTAL clock is used as a reference in both the GEN and SER (Serial)
modules. With an 18.432 MHz crystal, for example, the internal XTAL timing
reference is 3.6864 MHz (useful for serial bit-rate generation and tim ers ).
Internal XTAL clock behavior can be emulated with an external oscillator; note the
conditions in the following example:
–The PLL is bypassed.
–The external oscillator is running at 44.2368 MHz.
–The PLL Control register is set up to produce that same frequency by
setting PLLCNT to 9.
With these conditions, the internal XTAL clock reference produces the 3.6864 MHz
timing reference.
Internal XTAL clock frequency definitions
Internal XTAL clock frequency is defined in one of two ways, depending on mode:
Inactive high . When PLLTST* is inactive high (PLLTST* = 1), the value
of FXTAL is defined as follows:
)
;7$/
)
&5<67$/
where:
–FXTAL identifies the ti ming r efer ence used by the GEN and SER modules.
–FCRYSTAL identifies the frequency of the external crystal component.
Active low. When PLLTST* is active low (PLLTST* = 0), the value of
FXTAL is defined as follows:
,)3//&17
)
;7$/
)
&5<67$/
(/6(
)
;7$/
)
&5<67$/
3//&17
where:
–PLLCNT represents the value loaded into the PLL Control register
(PLLCNT value is 9 by default ).
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NET+50 internal clock generation
100 n n n n n n n
NET+50/20M Hardware Reference
–FCRYSTAL identifies the fr equency o f the external TTL c lock on the XTAL1
pin.
Clock generation signals
Crystals and crystal oscillators
A standard parallel-r esonant crystal can be attached to the XT AL1 and XTAL2 pins
to provide the main input clock to the NET+50 ch ip.
Quartz crystals can be chosen from a wide range of manufacturers. The crystals’
characteristics vary significantly, depending on the ir resonance frequency. Be sure
the crystal you choose for the NET+50 chip is parallel resonance with a load
capacitance CL of 8pF. If the crystal-recommended load capacitance is greater, add
capacitors external to XTAL1 and XTAL2.
The crystal oscillator is a low-power oscillator — do not u se a ny ext e r na l
capacitors or resistor s to reduce the current driven in the crystal. If the crystal
Code
(Bit #) Description Definition
XTAL1
XTAL2
Crystal osci ll a tor
input
Crystal osci ll a tor
output
Provide the main input clock to the NET+50 chip, using a standard
parallel-resonant cryst al attac hed to the pins. See "Cryst als and
crystal oscillators," beginning on page 100, for more information.
PLLVDD Clean PLL power Powers the internal 2.5V PLL circuit. it is recommended that this pin
be provided with clean power. The PLLVDD pin has an adjacent
PLLVSS ground return.
PLLVSS Clean PLL
ground Grounds the internal PLL circuit. It is recommended that this pin be
provided with clean ground.
PLLLPF PLL loop filter Provides the PLL loop filter circuit. An external RC circuit (100 ohms
in series with a .47µF with a .047 across both) must be attached
between PLLPF and ground.
RESET* System reset Resets the NET+50 chip hardware. A valid RESET* input must be
issued for a minimum of 40ms after power reaches 3.0 volts. A
RESET* input can be issued at any time to reset the NET+50 chip.
Note: Both RESET* and TRST* must be pulsed active low after
power up and should be active at the same time. These pins can be
connected together.
Table 40: Clock generation signal descri ption
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The GEN Module
being used has a drive level smaller than the drive level specified, however, add a
series resistor between XTAL 2 and the crystal connection.
The NET+50 chip can be driven using an external TTL oscillator rather than the
XTAL1/XTAL2 crystal oscillator circuit. The TTL oscillator provides a single TTL
clock input on the XTAL1 pin. The XTAL2 pin is left unconnected in this
configuration. To use this configuration, the PLLTST* pin must be driven low.
Note:
When this configuratio n is used, the internal PLL is bypassed and
disabled.
The oscillator fr equency equals SYSCLK. XTAL1 is in the 2.5V ring and has a
maxim um VIH of 2.75V. A typical 3.3V oscillator requires a 220 ohm series resistor
with its output.
Reset circuit
The NET+50 chip has four sources of hardware r eset and one software reset:
Powerup reset
External reset
Watch-dog reset
ENI reset
Software reset
Poweru p reset
A powerup r eset comes from a special ground PAD, which produces an active
high reset pulse when the power voltage is outside specifications. The SYS module
synchronizes this signal using a 5-bit counter with asynchronous clear.
When the powerup reset is active, the counter is cleared.
When the reset is removed, the counter is allowed to count. When the
counter reaches 31 (with no additional powerup reset pulses), the
counter trig gers a hardware reset co ndition.
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Reset circuit
102 n n n n n n n
NET+50/20M Hardware Reference
Exter nal reset
It is recommended that a system include an external powerup reset cir cuit that
drives the RESET* pin active low during powerup. RESET* must be driven active
low a minimum of 40ms after V DD lines reach their minimal operating voltages.
The RESET* p ulse width must be a mi nimu m of 1us at other ti mes.
The SYS module uses a six flip-flop stage to de-glitch the RESET* input. If the
signal is low for this minimum pulse width, a har dware reset condition is
tri g g ered wh en the RESET * i n put is remov e d .
When a powerup or external reset condition is triggered, the SYS module drives
the internal hardware reset signal active for a total of 512 system clock periods.
Wa tc h- Do g r e se t
The watch-dog reset is prov ided by the watch-dog timer in the GEN module.
Once the watc h-dog timer is enabled, the Software Service register must be
accessed to r eset the watch-dog timer before it expires. When the watch-dog timer
expires, the watch-dog reset is issued.
ENI reset
An ENI reset is issued when the RSTIO bit is set in the ENI Shar ed register. The
ENI reset condition r emains active until the RSTIO bit is cleared in the ENI Shared
register. (See "ENI mode registers," beginning on page 400.)
Software reset
The software reset is issued by the CPU using the Software Service register in the
GEN module. The software reset can be used to get all internal NET+50
peripherals into a known reset state.
Rese t condi tions
Table 41 identifies which internal NET+50 modules are reset under various r eset
conditions. The PORTC4 special function output works only with software and
ENI resets.
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The GEN Module
PLLTest Mode
When the PLLTST* signal is low, the PLL is isolated and the internal system clock
is provided by the XTAL1 input. In addition, the external tester has access to all
PLL inputs. While PLLTST* and BISTEN* are both active low, the ex ternal tester
has visibility into all PLL outputs.
When the PLLTST* input is high, the
LQGLY
,
LFS
,
RXWGLY
, and
SROWVW
inputs are
provided by a firmwar e programmable register; the
HQE
input is driven low and
the
WHVW
input is driven low. The SYS_PLL_DIV signal is the output of the internal
divider.
NET+50
chip module RESET condition
Power up RESET* Watchdog ENI Software
CPU Yes Yes Yes Yes No
EFE Yes Yes Yes Yes Yes
DMA Yes Yes Yes Yes Yes
ENI Yes Yes Yes No No
GENaYes Yes Yes Yes Yes
MEM Yes Yes Yes No No
SER Yes Yes Yes Yes Yes
a. All registers in the GEN Module are reset during powerup, RESET*, watch-dog, ENI, and
software reset with a few exceptions. The following GEN Module fields are reset during the
powerup, RESET*, and watch-dog conditions only (not ENI or softwa re rese t):
BSPEED (GCR)
BCLKD (G CR)
PORTA
PORTB
PORTC
Table 41: Reset co nditions
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PLLTest Mode
104 n n n n n n n
NET+50/20M Hardware Reference
PLLTST BISTEN* PLL057 Signal NETA50 Primary I/O
0 0 SYS_PLL_DIV PORTA3 (output)
0 0 pdu PORTA4 (output)
0 0 lock PORTA5 (output)
0 0 pdd PORTA6 (output)
0 0 ck PORTA7 (output)
0 X indiv[1] PA0 (input)
0 X indiv[0] PA1 (input)
0 X icp[3] PA2 (input)
0 X icp[2] PA3 (input)
0 X icp[1] PA4 (input)
0 X icp[0] PA5 (input)
0 X outdiv[1] PA6 (input)
0 X outdiv[0] PA7 (input)
0 0 enb PA8 (input)
0 1 enb 1 (disabled mode)
1 X enb 0 (active mode)
0 X poltst[0] PA9 (input)
0 X poltst[1] PA10 (input)
0 X poltst[2] PA11 (input)
0 X poltst[3] PA12 (input)
0 X ckr TCK (input)
0 X ckdiv TD1 (input)
0 X test PA13 (input)
0 X dataload XTAL1
X X lft PLLLPF
Table 42: PLL Te st Mode Co nnections
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The GEN Module
When PLLTST* is active low, the oscillator is disabled and provides a pass-through
of the XTAL1 input as the main internal system clock.
PLLTST* osc25fm16 signal osc25fm16 value
0 onosc 0
1 onosc 1
Table 43: POR25 test mode connections
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Cache
CHAPTER 7
The NET+50 CPU module uses the ARM7TDMI stand-alone core and adds an
instruction/data cache, write protection, and pre-fetch contr ol. The CPU module
contains its own internal bus, referred to as the CBUS.
This chapter applies to the NET+50 chip only.
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CBUS and BBus system buses
108 n n n n n n n
NET+50/20M Hardware Reference
CBUS and BBus system buses
Figure 9 shows a block diagram of the CPU module structure within the NET+50
chip.
Figure 9: NE T+50 CPU co re block diagram
The CBUS and BBus s ystem buses a r e separa ted using the BIU (b us in terfac e un it).
This structure allows the CPU to execute instructions from the cache while the
BBus is being used for DMA data transfer operations.
All transactions that take place on the two buses are defined to operate in the
logical memory space. Memory access requests mapped to external memory,
through the MEM module, are considered to be in a physical addressin g context.
All internal buses, however, carry logical addresses.
BIU a nd cache c ontroller
The BIU block provides the control funct ions necessary to separa te the CBUS and
BBus. The BIU uses the configuration information provided by the cache control
registers (CCR) to determine when an external bus cycle is required instead of an
internal cache cycle.
The B IU uses the pre-fet c h c on t rol whe n t he AR M 7TD MI i s ex ecuting in Th um b
mode and the external instruction storage peripheral is configured in 32-bit mode.
Because Thumb instructions are 16 bits wide, you can use the full width of the data
bus to fetch two instructions in one cycle.
ARM7
CPU core BIU
an d cach e
controller
Cache
tags Cache
RAM
Pre-fetch
control
CCR0
CCR1
BBusCBUS
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Cache
Cache
The N ET+50 ch ip conta ins an 8- KByte m ixed inst ructi on and dat a cache. The cach e
is arranged in a four-way set associative configuration.
Figure 10: 4-wa y associated c ache
When a cache-set is not enabled for caching, it can be used as a simple block of
RAM. Each cache-set can be independently configured as a 2-KByte cache block or
a 4-KByte RAM block.
The cache tags are configur ed to identify individual 8-bit entries. This
configuration maximizes the efficiency of a low-cost 16-bit bus running ARM
Thumb c ode by minimizing th e number of unused me mo ry ac c ess es. Traditiona l
cache architectures require an entire cache-line (16 bytes per line) to be filled at a
time. The traditional architecture approach can result in unnecessary memory
cycl e s when the progra m fl o w changes direct i on . Each lin e i n th e ca c he RAM
contains a 21-bit tag, 2 control bits, an 8-bit status field, and a 32-bit data field.
See "Cache RAM" on page 114 and "Cache TAG format" on page 115 for more
information.
Tag Status 32 -bit data
Tag Status 32 -bit data
Compar ator Multiplexer
Cach e s ets 1-4
Hit Data
Tag reference Tag addres s
Phys ic al ad d re s s
31 11 92 0 1
. . .
Line 0
Line 1
Line 511
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Cache
110 n n n n n n n
NET+50/20M Hardware Reference
Cache cont rol registers
The NET+50 supports two Cache Control registers —
&&5
and
&&5
. The Cac h e
Cont rol r eg i ster identi f i es a l l th e ca c he and b uffer fe at u res for th e id en t i fied
memory blo ck.
Each control register identifies a configurable block of logical address space.
Typically, one Cache Control register identifies cacheable instructions and the
other Cache Control register identifies cacheable data, which allows you to
separate instruction and data fetch operations.
The Ca che Cont rol r egiste r selects c acheabl e addr ess block s using an addr ess mask
and compare operation. See "Cache Control registers" on page 112 for an
illustration of the register and an explanation of each bit.
Cache o peration
A read from a cacheable location results in data being taken from the cache if a
cache hit occurs. When a cache miss occurs, the cache controller r eads external
memory and attempts to put the new line into an invalid (empty) location within
the four possible cache sets. When a cache set needs to be dismissed to make room
for the new entry, a round-robin algorithm identifies which cache-set to dismiss.
Writes to areas defined as cacheable are written to the cache (when the data exists
in the cache) and external memory at the same tim e.
Cache line fill
A cache line can be filled using 8-, 16-, or 32-bit operations, depending on the
width of the bus transactions. The NET+50 chip cache controller does not force the
entire line to be filled at one time. When a cacheable location is read that is not
curr entl y in the cach e, the cac he contr oller examines the fo ur cache-s ets att ached to
the corresponding address block. The cache controller inserts the new entry into
any invalid set. If no empty sets are available, the cache controller discards one of
the current lines to make room for the new data.
When the CPU is fetching 16-bit Thumb instructions from an external 32-bit
memory device, the cache line can be filled 32 bits at a time. This process is referr ed
to as 32-bit pre-fet ching. This feature is enabled using the FRC32 control bit in the
Cache Control register (see "Cache Control r egisters" on page 1 12). When FRC32 is
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n n n n n n n 111
Cache
set, the cache contr o l l er fo rces a 32-bi t op e r an d fet c h wh enever th e ARM fet c hes
any operand on a zero byte boundary.
Cache line replacement
The appropriate, valid bits are cleared when a cache line is replaced , making the
line empty and available. Any cache lines with the INVALID or LOCK bits set (see
"Cache TAG format" on page 115) are not affected by a cache line replac ement
operation.
Cache line locking
You can lock instructions and data within the cache by writing to the cache TAG
and cache data registers. When the cache T AG is written, the LOCK bit must be set
to 1. Once cache lines are locked, the lines remain in the cache until the LOCK bit is
removed. These lines are not replaced by the round-robin algorithm.
32-b it pre-fetc h
The 32-bit pre-fetch feature offers a performance improvement for those 16-bit
Thumb applications using a 32-bit bus for instruction storage. Pre-fetch causes the
memory interface to fetch a 32-bit word each time the ARM processor fetches any
cacheable operand on a zero byte boundary. The FRC32 bit must be set to 1 in the
Cache Control register to force fetching on a zero byte boundary. When the ARM
processor fetches the next consecutive 16-bit instruction, the next instruction is
most likely available in the cache.
Cache initializatio n
Before cache can be enabled for operation, the cache TAG area must be initialized
to zero. A software loop can do this by writing zeros between byte addresses
[)))
and
[)))))&
.
While writing zeros to the cache RAM block, the CINIT bit in the GEN System
Control register must also be set. The CINIT bit must be reset to zero after the
cache RAM block has been initialized to zero.
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Cache Control registers
112 n n n n n n n
NET+50/20M Hardware Reference
Cache Control registers
The Ca che Control regi ster s,
&&5
and
&&5
, provide control for the instruction and
data cache. Eac h register selects a specific block of logical address space and
determine s how the cache is used.
Register and bit definitions
Code
(Bit #) Definition of
code Description
BASE
(D31:D24) Logical address
base Defines the base address of a logical block of memory that is to be
cached using Cache Control register configurat ion parameter s. The
MASK field (D23:D16) defines the size of the logical block of
memory. The BASE field is processed wit h a logical AND of the
MASK field and then compared w ith the upper eight bits of the CPU
bus (A31:A24) to determine which locations are to be cached with the
CCR configuration. The upper eight CPU address bits are also
processed with a logical AND of the MASK field before comparison
with the BASE field .
MASK
(D23:D16) Logical address
mask Defines the size of the cacheable region. The MASK field identifies
those bits in the BASE field definition that are used in the address
comparison operation with the CPU bus address. Only the bit
positions with 1 in the MASK field can be used in the address
comparison function.
Table 44: CCR0/CCR1 register bit definition
ENABLE SUPV ---
RESERVED WP FRC32 SET1 SET2 SET3 SET4
0
R/W 0
R/W
0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
BASE MASK
RESERVED --- --- --- ---
0
R/W
Address = FFB0 0040 / 44
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Cache
ENABLE
(D15) Enable 0 — Disable CCR configuration
1 — Enable CCR configuration
Must be set to 1 to allow the address defined by BASE and MASK to
be cacheable according to the CCR parameters.
SUPV
(D14) Supervisor-only
mode 0 — Allow both user and supervisor accesses to be cached
1 — Allow only supervisor accesses to be cached
Set to 1 to cause this CCR configuration to cache only supervisor
mode accesses. Useful for applications t hat want to cache operating
system kernel execution only.
RESERVE
D
(D13)
Reserved bit Must always be set to 0. If set to 1, can result in unpredictable
behavior of the cache controller.
WP
(D12) Write protect 0 — Allows wr it es to t his block
1 — Does not allow writes to this block
Provides the ability to write-protect a cacheable region of memory.
Generally used to protect a cacheable region of memory used solely
for instruction execution.
When the bit is set 1, writing to a cacheable region of memory causes
a data abort exception to the processor.
FRC32
(D11) Force 32-bit
prefetches 0 — Disable
1 — Force 32-bit fetches on 0 byte boundaries
Forces 32-bit operands to always be fetched when address boundaries
allow.
Should always be set to 1 when the CCR region is used with a
peripheral that is 32-bits wide.
Must be set to 0 when the CCR region is used with any
peripheral that is not 32-bit wide.
RESERVE
D
(D10:D09)
Reserved bits Must always be set to 0. If set to 1, can result in unpredictable
behavior of the cache controller.
Code
(Bit #) Definition of
code Description
Table 44: CCR0/CCR1 register bit definition
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Cache RAM
114 n n n n n n n
NET+50/20M Hardware Reference
Cache RAM
The processor can fully address internal cache RAM memory. Data aborts occur
when:
The cache RAM memory block is accessed in non-supervisor mode
when the USER bit in the GEN System Control register is set to 0 (see
"System Control register" on page 63).
The cache RAM memory block is accessed beyond its physical size.
Attempts ar e made to access the cache RAM block when t he CACHE bit
is not enabled in the GEN System Control register (see "System Control
register " on page 63).
SET1
(D03)
SET2 (D02)
SET3 (D01)
SET4 (D00)
SET1 Enable
SET2 Enable
SET3 Enable
SET4 Enable
0 — Disable SET1; 1 — Enable SET1
0 — Disable SET2; 1 — Enable SET2
0 — Disable SET3; 1 — Enable SET3
0 — Disable SET4; 1 — Enable SET4
Used typically to separate instruction and data regions, as well as
apply different amounts of cache to each region
Set to 1 attach the S ET1 (and/or S ET2, S ET3, SE T4) cache segment
to the CCR region. Each cache set can be attached to 1, 2, 3, or 4 of
the cache sets. The ability to control how many sets are attached to
each CCR allows the use of more cache sets for different memory
regions.
Code
(Bit #) Definition of
code Description
Table 44: CCR0/CCR1 register bit definition
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n n n n n n n 115
Cache
Table 45 ident ifi e s ho w t he cach e R AM memo r y block is add resse d.
The information contained in each set falls into contiguous memory locations:
Each set, if not enabled in any CCR for cache, provides 4 KBytes of
contiguous random access memory. This results in a total of 16 KBytes
of fast, 0-wait state RAM.
If 2 adjacent sets are not enabled as cache, then 8 KBytes of contiguous
RAM are available.
When a set i s en a b l ed fo r c ac he RAM, eac h en t ry i s 8 b y t es wi de. The first 4 b yt es
provide the cache TAG information; the second 4 bytes provide the cache DATA
information. The cache TAG and DATA fields ar e modified when information
needs to be locked into the cache.
Cache TAG format
Each cache line stores 32 bits of data. A cache line is always in one of two states:
valid or invalid. Each cache line can contain 0 to 4 bytes of valid data. The cache
line status bi ts id entify the state of each cache line:
When a line is invalid, the cache line is clear and lookups are ignored.
When a line is valid, it contains data cons istent with exte rnal memory.
Offset Base Address
0xFFF00000 (set1) 0xFFF01000 (Set2) 0xFFF02000 (set3) 0xFFF03000 (set4)
0 Set1 Entry1 TAG Set2 Entry1 TAG Set3 Entry1 TAG Set4 Entry1 TAG
4 Set1 Entry1 DATA Set2 Entry1 DATA Set3 Entry1 DATA Set4 Entry1 DATA
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
0xFF8 Set1 Entry512 TAG Set2 Entry512 TAG Set3 Entry512 TAG Set4 Entry512 TAG
0xFFC Set1 Entry512 Data Set2 Entry512 DATA Set3 Entry512 DATA Set4 Entry512 DATA
Ta ble 45: Cach e RAM memo ry addressing
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Cache TAG format
116 n n n n n n n
NET+50/20M Hardware Reference
Figure 10, "4-way associated cache," on page 109 provides a simplified view of
how the cache mechanism works. The caches always use logical addressing. To
determine if the logical address is currently located in the cache, address bits A31
through A2 are used to reference the cache tag or to update the cache tag field. If a
match occurs, the selected cache line is used and flagged as a hit.
Cache TAG format and definitions
Code
(Bit #) Definition of
code Description
TAG
(D31:11) Tag reference Identifies which memory location is currently stored within this cache
entry. This field is val id only when one of t he four V (valid) bit s i s set t o
1. Use the following formula to calculate the actual physical address of
the information for this cache entry:
SK\VLFDODGGUHVV
7$*__FDFKH$GGUHVV[)!!
D10 Not used
INVALID
(D09) Invalidate location 0 — Location is valid for cacheable entries
1 — Location is invalid for any cache entries
Prevents specific cache lines within a set from being used for cache
entries.
Typically used to reserve cache entries for code that will be locked down
in the cache at a later time.
Table 46: Cache tag bit definitions
TAG
_V1 V0
0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset
:
Reset
:
0
R/W
INVALID LOCK V3 V2 RESERVED
0
R/W
TAG
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Cache
LOCK
(D08) Locked state 0 — Entry not locked
1 — Entry locked in cache
Causes an entry to remain static within the cache. Can be set to 1 to have
the current entry remain in the cache set indefinitely.
Typically used to preload software functions in the cache.
V3
(D07) Byte 3 valid 0 — Byte 3 is invalid
1 — Byte 3 is valid
Set to 1 to indicate that byte 3 in this cache entry is valid.
Byte 3 refers to the least significant address byte of a 32-bit word when
operating in Big Endian mode, and to the most significant byte when
operating in Little Endian mode.
V2
(D06) Byte 2 valid 0 — Byte 2 is invalid
1 — Byte 2 is valid
Set to 1 to indicate that byte 2 in this cache entry is valid.
V1
(D05) Byte 1 valid 0 — Byte 1 is invalid
1 — Byte 1 is valid
Set to 1 to indicate that byte 1 in this cache entry is valid.
V0
(D04) Byte 0 valid 0 — Byte 0 is invalid
1 — Byte 0 is valid
Set to 1 to indicate that byte 0 in this cache entry is valid.
Byte 0 refers to the most significant address byte of a 32-bit word when
operating in Big Endian mode, and to the least significant byte when
operating in Little Endian mode.
RESERVED
(D03:D00) Reserved bits Should always be set to 0. If set to 1, can result in unpredictable behavior
of the cache controller
Code
(Bit #) Definition of
code Description
Table 46: Cache tag bit definitions
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Memory Controller Module
CHAPTER 8
This chapter explains how the NET+50 chip can be conf igured to interface with
various types of memory devices.
Note:
The information in this chapter applies to both the NET+50 and
NET+20M chips, unless otherwise noted.
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NET+50/20M Hardware Reference
MEM module features
The ME M modu l e prov i des these features:
Five chip select configurations
28-bit address bus that allows access to 256 Mbytes per chip select
8-, 16-, or 32-bit data bus sizes
Two timing variations for access to static RAM (SRAM)
Fast Page (FP) DRAM timing and EDO DRAM timing
Note:
Both FP and EDO DRAM can use one of two internal RAS/CAS
address multiplexers, which source 10-CAS or 8-CAS.
Synchronous DRAM (SDRAM) timing
Note:
SDRAM can use the internal 8-CAS internal address multiplexer.
Use of an external RAS /CAS multiple xer by all DRAM timing , allowing
any RAS/CAS combination
0 to 15 wait states
Extern ally-c ontrolled transf ers
Write protect (WP)
Memory control signals
The NET+50 uses these signals to interface with memory. This section provides a
brief description; see "Memory control signals" on page 134 for more information
about each signal.
Signal Definition
D[31:0] 32-bit data bus
A[27:0] 28-bit address bus
CS[4:0] 5 chip selects
RAS[4:0] 5 row address strobes for DRAM
Table 47: Memory c ontrol signal overvie w
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Memory Controller Module
Configur ation register s
The Memory module has four configuration registers for each of the five chip
sele ct s. These regi st er s adjust the behavior of th e memory cont rol si g n al s to
produce the optimum required for the particular memory device connected to the
NET+50.
Registers
The NE T+50 chi p us e s th ese four c on fi g u ra t i o n regi st er s :
Memory Module Co ntrol register (MMCR)
Chip Select Base Address register (CSBAR)
Chip Select Option register (CSOR)
Chip Select Option Register B (CSORB)
Table 48 lists the names and addresses of the configuration registers.
CAS[3:0] 4 column address strobes for DRAM
R/W* Read/Wri te si gn al
OE* Output enable signal
WE* Write enable signal
BE[3:0] 4 byte enable signals, one for each byte in the 32-bit data bus
TA* Transfer acknowledge
TEA* Transfer error acknowledge
Signal Definition
Table 47: Memory c ontrol signal overvie w
Address Name Description
FFC0 0000 MMCR Memory Module Configuration register
Table 48: MEM module configuration registers
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NET+50/20M Hardware Reference
Memory Module Control register (MMCR)
The MMCR controls the functionality of addr ess bits A27, A26, and A25. These
address bits can function as other than address lines, and are defined within this
r egi st e r. The MMCR also controls how DRAM-c on figu red chip select s are
r efreshed, and how the DRAM’s RAS/CAS is multiplexe d. All chip selects
configured as DRAM must be set to the same type of DRAM. The DRAM
configuration bits in this register are common to all DRAM chip selects.
FFC0 0010 BAR0 Chip Select 0 Base Address register
FFC0 0014 OR0 Chip Select 0 Option register
FFC0 0018 ORB0 Chip Select 0 Option Register B
FFC0 0020 BAR1 Chip Select 1 Base Address register
FFC0 0024 OR1 Chip Select 1 Option register
FFC0 0028 ORB1 Chip Select 1 Option Register B
FFC0 0030 BAR2 Chip Select 2 Base Address register
FFC0 0034 OR2 Chip Select 2 Option register
FFC0 0038 ORB2 Chip Select 2 Option Register B
FFC0 0040 BAR3 Chip Select 3 Base Address register
FFC0 0044 OR3 Chip Select 3 Option register
FFC0 0048 ORB3 Chip Select 3 Option Register B
FFC0 0050 BAR4 Chip Select 4 Base Address register
FFC0 0054 OR4 Chip Select 4 Option register
FFC0 0058 ORB4 Chip Select 4 Option Register B
Address Name Description
Table 48: MEM module configuration registers
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Memory Controller Module
The D RAM re fres h contr olle r alway s gener ates CA S befor e RAS r ef resh cycles. The
RFCNT, REFEN, and RCYC bits in the MMCR work together to define DRAM
refresh timing. The NET+50 will produce background refresh when accessing an
SRAM device. The RAS and CAS lines are not needed for static RAM (SRAM), so a
DRAM refresh can be accomplished when accessing SRAM.
Memory Module Control register and bit definitions
RFCNT Refresh count value
(D31:24)
Defines the refr esh period for the memory controller when Fast Page, EDO, or
SDRAMs are be ing used. All DRAM devices require a periodic refresh cycle. The
refresh cycle typically is 15 us. The NET+50 chip allows the refresh period to be
programmable.
The refresh cycle is a function of the RFCNT field. The value for FXTAL is defined
by the following equation:
5HIUHVKSHULRG >5)&17@);7$/
See "NET+50 internal clock generation" on page 96 for more information about the
FXTAL value.
REFEN DRAM refresh enable
(D23)
0 – Disable DRAM re f res h.
1 – Enable DRAM r efresh.
RCYC Refr e s h cycle count
(D22:21)
00 – Refresh cycle is 8 BCLK clocks long
(see Figure 74, "Fast Page and EDO DRAM Ref resh (RCYC = 0)," on page 443)
0
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Addres s = FFC0 0000
RFCNT REFEN RCYC AMUX AMUX2
0
R/W 0
R/W 0
R/W
0
R/W 0
R/W
-- ------ --
A27_F A26_F A25_F*
-- ------ -- -- ------ ----
0
R/W I
R/W
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NET+50/20M Hardware Reference
01 – Refresh cycle is 6 BCLK clocks long
(see Figure 75, "Fast Page and EDO DRAM Ref resh (RCYC = 1)," on page 443)
10 – Refresh cycle is 5 BCLK clocks long
(see Figure 76, "Fast Page and EDO DRAM Ref resh (RCYC = 2)," on page 444)
11 – Refresh cycle is 4 BLCK clocks long
(see Figure 77, "Fast Page and EDO DRAM Ref resh (RCYC = 3)," on page 444)
Controls the length of the refresh cycle. These settings apply only to FP/EDO
DRAM. SD RAM is always refreshed as shown in Figure 84, "SDRAM Refresh," on
page 452.
AMUX Enable external addr ess multiple x ing
(D20)
0 – Disable external addr ess multiplexing on POR TC3 for all DRAM banks
1 – Enable external address multiplexing on PORTC3 for all DRAM banks
Controls whether the NET+50 chip uses its internal DRAM address multiplexer.
When AMUX is set to 1, the NET+50 chip uses an external DRAM address
multiplexer. The RAS/CAS address select signal is routed out the PORTC3 signal.
The ext e r na l DR A M RAS /CAS address mult i plexer fun cti o n c an use th e P ORTC3
signals to determine when to switch the address multiplexer.
A27_F A27 pin functionality
(D19)
0 – The CS0OE* sig nal is driven out the ADDR27 pin
1 – The ADDR27 pin is used for address bit 27
Determines the functionality of the A27 pin. A27F can be set to source the A27
address signal or the OR-gated CS0* and OE* signals.
When A27_F is set to 0, the CS0OE* signal is driven out the A27 pin. The
CS0OE* signal is generated by an internal OR-gating of CS0* and OE.
The CS0OE* signal goes active low when both CS0* and OE* are low.
When A27_F is set to 1, t he A27 bit is sourced.
Figure 11 shows the functionality of the A27_F bit:
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Memory Controller Module
Figure 11: A27_F functionality
A26_F A26 pin functionality
(D18)
0 – The CS0WE* signal is driven out the ADDR26 pin
1 – The ADDR26 signal is used for address bit 26
Determin es the functiona lity of the A26 pin. A26_F can be set to source the A26
address signal or to the OR -gated CS0* and WE* signals.
When A26_F is set to 0, the CS0WE* signal is driven out the A26 pin.
The CS0WE* signal is generated by the internal OR-gating of the CS0*
and WE* signals. The CS0WE* signal goes active low when both CS0*
and WE* are low.
When A26_F is set to 1, t he A26 bit is sourced.
Figure 12 shows the functionality of the A26_F bit:
Figure 12: A26F functionality
OE*
CS 0* CS 0OE*
A27 A2 7 Pi n
FFC00000 D19 (high = A27)
WE*
CS 0* CS 0WE*
A26 A2 6 Pi n
FFC00000 D18 (high = A26)
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NET+50/20M Hardware Reference
A25_F Enable the A25 output
(D17)
0 – The ADDR25 pin is used as address bit 25
1 – Reserved. This bit is never set to 1.
AMUX2 Internal/External RAS/CAS Mux
(D16)
0 – Normal operation
1 – Reserved. This bit is never set to 1.
Chip Select Base Address register and bit definitions
The CSBAR defines the base starting address for the chip select and configure s
other chip select options. Each chip select can be configured in size from 4 Kbytes
to 256 Mbytes. All bits are reset to 0 on system reset. This register works in
conjunction with the Chip Select Option register MASK field.
BASE Chip select base address
(D31:12)
Determin es the starting physical address of the memory peripheral chip select.
This field represents the 20 most significant bits of the physical address. To
determine the base physical address of a memory peripheral decode space, add
three zeros to the end of this field. For example:
%$6(ILHOGYDOXH [
SOXVWKUHH]HURV [
[ VWDUWLQJSK\V LFDODG GUHVVR IWKHS HULSKHU DOFKLS VHOHFW
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Address = FFC0 0010 / 20 / 30 / 40 50
BASE
0
R/W
0
R/W
BASE PGSIZE DMODE DMUXS VWPBURSTDRSELIDLEDMUXMEXTTA
0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 1
R/W 1
R/W
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Memory Controller Module
The BASE field must be consistent with the size of the chip select as defined by the
MASK fiel d in the Chip Select Option register. The base address of a chip select
must occur on a proper boundary in relation to the peripheral memory size. If the
size of the me mory device is 4 Mb ytes, for example, the BASE field must be
configured such that the base address is located on a 4 Mbyte address.
See "Setting the Chip Select address range" on page 136 for an explanation of how
the BASE and MASK fields work together to define a chip select’s address spac e.
PGSIZE Peripheral page size
(D11:10)
00 – 64 bytes
01 – 32 bytes
10 – 16 bytes
11 – 8 bytes
Defi ne s t he pa ge si z e fo r th e at t a c he d pe ri p h er a l . Thi s field cont rols the address
burst boundary for the NET+50 memory controller. The NET+50 will not burst
through an address boundary that is larger that defined by the PGSIZE field.
DMODE DRAM mode
(D09:08)
00 – Fast Page DRAM
01 – EDO DRAM
10 – SDRAM
11 – Reserved
Selects the type of DRAM. The DMODE field is valid only when the DRSEL bit is
set to 1, indicating DRAM mode. All chip selects configured as DRAM must be set
to the same type of DRAM.
DMUXS Internal/External RAS/CAS
(D07)
0 – Internal DRAM multiplexer
1 – External DRAM multiplexer
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NET+50/20M Hardware Reference
Controls whether the NET+ARM internal address multiplexer is used for this
DRAM memory peripheral. A settin g of 1 indica tes that an external DRAM
multiplexer is to be used for this device. When set to 1, the PORTC3 pin is used to
signal to th e externa l ad dres s mul t i p l e xer when to swi t c h t he address bi t. When
the PO RTC3 signal is hig h, the ext er n al D RAM RAS/CAS address mult i p l ex er
funct i o n d r i ves the CAS add res s to t he DRAM de vi ces.
The AM UX or AMUX2 bit in the MMCR se rves as a glo bal co ntr ol whe n set. When
either of these bits is set to 1, all DRAM peripheral devices use the external address
multiplexer and the DMUXS bit is ignored.
EXTTA Enable ex ternal transfers
(D06)
0 – Internal
1 – External
Determin es how a memory cycle is terminated:
When EXTTA is set to 0, the TA* signal is an output and signals the end
of the transfer. The memory transfer time is consistent and controlled
only by the NET+ARM’s memory configuration.
When EXTTA is set to 1, the TA* signal is an input and the transfer does
not end until the external device dri ves the TA* signal low, to signal the
end of the transfer. External transfers must be used when the device
with which the NET+ARM is interfacing has an inconsistent cycle time.
Note:
When the external transfer option is selected, the synchronizer bits in
Chip Select Option Register B must be configured.
DMUXM Internal/External RAS/CAS
(D05)
0 – Mode-0 10 CAS
(see Figure 15, "DRAM Mode-0 addressing," on page 150 and Table 54: "DRAM
Mode-0 addressing" on page 151)
1 – Mode-1 8 CAS
(see Figure 16, "DRAM Mode-1 addressing," on page 153 and Table 55: "DRAM
Mode-1 addressing" on page 154)
When set to 0, the internal multiplexer option is selected. The DMUXM field offers
two options: 10 CAS with Mode-0 and 8 CAS with Mode-1.
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Memory Controller Module
IDLE Insert null clock cycle
(D04)
0 – Do not add null cycle after transfe r
1 – Add one null cycle after every transfer for this chip select
Inserts an extra BCLK cycle at the end of the memory cycle for a chip select that
has been configu red as DR AM.
Note:
Do not set the idl e bit in a non- DRAM chip sele c t.
DRSEL DRAM select
(D03)
0 – Stati c R AM
1 – DRAM
When DRSEL is set to 0, the chip select will be configured as static RAM
and the timing is based on the WSYNC and RSYNC setting.
When the DRSEL bit is set to 1, the chip select is configured as FP, EDO,
or SDRAM based on the DMODE setting.
BURST Enable burst transfers
(D02)
0 – Sing le cy c l e t ra n sfe r s only
1 – Burst cycle transfers are allowed
Controls whether the memory peripheral device supports bursting:
When BURST is set to 1, burst cycles are allowed if the current bus
master wants to execute a burst cycle. During a burst cycle, the WAIT
field controls the number of wait-states for the first memory access of
the burst and the BCYC field controls the number of wait-states for all
subsequent memory access for the burst cycle. The BSIZE field controls
the maximum number of memory cycles that the peripheral can
support. The current bus master can choose to burst a smaller number
of memory cycles. The peripheral terminates the burst, however, when
the maximum number of memory cycles defined by the BSIZE field is
reached.
When BURST is set to 0, burst cycles are not allowed.
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WP Write protect
(D01)
0 – Allow b ot h read an d wr i t e cy c l e t r an sfers
1 – Do not allow memory write-cycles
WP can be us ed t o pr event an y bu s mast er from wri t in g to the memory devic e.
When WP is set to 1, all memory write-cycles are terminated immediately with an
data abort indicator. The WP bit can be used to pr otect non-volatile memory
devices such as flash and EEPROM.
Note:
The WP bit is set to 1 on hardware reset for CS0 only.
V Valid
(D00)
0 – Disable the chip select
1 – Enable the chip select
Enables the chip select. When the V bit is set to 1, the memory contr oller uses
various fields in the Chip Select Base Address and Option registers to control the
behavior of the peripheral mem ory cycles.
Note:
For all configura tions except SDRAM, it is recom mended that you set
the valid bit last, after all other bits in the MMCR, CSBAR, CSOR and
CSORB have been configur ed.
When a chip select is configured as SDRAM, the V bit has an additional function—
it produces the SD R AM loa d -mode co mma nd . ( Se e "L oa d -M o d e p roced ure:
Setting up the Load-Mode command" on page 155 for more information.)
Chip Select Option register and bit definitions
The C SOR define s the phys ical addr es s size of the ch ip select, a nd conf igur es other
chip select options. All bits in the register ar e r eset to 0 on system reset.
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Memory Controller Module
MASK Mask address
(D31:12)
Sets the size of the memory space that the chip select will respond to. The MASK
field works in conjunction with the BASE field in the CSBAR to set the chip select’s
address space.
The memory con t roller perfo rms a logical AND of the MASK and BASE fields to
det er mi n e whether t he ad d ress spa c e i s as si g ned to the chip select. Th e M ASK
field is used to identify those addr ess bits fr om A31 through A12 that will be part
of the address space.
See "Setting the Chip Select address range" on page 136 for an explanation of how
the BASE and MASK fields work together to define a chip select’s address spac e.
WAIT Number of wait states
(D11:8)
Controls the number of wait states for all single cycle memory transfers and the
first memory cycle of a burst transaction.
All NET+ARM memory cycles are a minimum of 2 BCLK cycles. This field
identifies the additional number of BCLK cycles for all single memory cycle
transactions and the first memory cycle of a burst transaction.
Setting this 4-bit field will insert between 0 and 15 wait states in the memory
transfer.
BCYC Number of clocks for subsequent cycles
(D7:6)
00 – Burst cycles are 1 BCLK clock in length (x,1,1,1)
01 – Burst cycles are 2 BCLK clocks in length (x,2,2,2)
10 – Burst cycles are 3 BCLK clocks in length (x,3,3,3)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Addres s = FFC0 0014 / 24 / 34 / 44 / 54
MASK
0
R/W
0
R/W
MASK WAIT BCYC WSYNCRSYNC
PSBSIZE
0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W
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11 – Burst cycles are 4 BCLK clocks in length (x,4,4,4)
Controls the number of clock cycles for the secondary portion of a burst cycle. The
WAIT fiel d cont ro ls the fi rst m emory cy cle o f a burs t cycle ; the B CYC fi eld con tro ls
the subsequent cycles.
Note:
When the chip select is configured as SDRAM, the BCYC field has a
different function whe n the V bit in the CSBA R is set. BCYC helps
det erm i n e ho w t he SD R AM lo a d -mo de command is con fi g u red (see
"Setting the Chip Select address rang e" on page 136).
BSIZE Burst size
(D5:4)
00 – 2 system bus cycles in burst
01 – 4 system bus cycles in burst
10 – 8 system bus cycles in burst
11 – 16 system bus cycles in burst
Controls the maximum number of memory cycles that can occur in a burst cycle.
This field determines only the maximum number of allowable cycles; the current
bus master can choose not to burst the entire amount. If the current bus master
continues to burst, the peripheral terminates the burst when the number of
memory c ycle s reache s the maximu m a ll owed by th e BSIZ E fie l d.
Notes:
1A potential limitation for this field is the BTE field in the DMA
Control register (see page 187). If the data bus is 32 bits and the BTE
field is set to a maximum of 16 bytes, the transfer will end after 4
cycles (16 bytes), even if the BSIZE field is set to 11 (16 system bus
cycles in burst).
2When the chip select is configured as SDRAM, the BSIZE field has
a dif ferent function when the V bit in t he CSBAR is set. B SIZE helps
determine how the SDRAM load-mode command is configured
(see "Setting the Chip Select address range" on page 136).
PS Port size
(D3:2)
00 – 32-bit Port Size
01 – 16-bit Port Size
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Memory Controller Module
10 – 8-bit Port Size
11 – 32-bit Port using external Data Acknowledge
Controls the size of the d ata b u s associated with the chip select. Each chip select
can be configured to operate as an 8-bit device, a 16-bit device, or a 32-bit device.
The add res s bus ad j us t s ac c ording l y.
RSYNC Read synchronous mode
(D01)
0 – SRAM chip select read cycles will operate in asynchronous mode
1 – SRAM chip select read cycles will operate in synchronous mode
Controls the access timing of the OE* and CS* signals for SRAM timing. The
RSYNC bit is used only when the DRSEL bit is set to 0.
When RSYNC is set to 1, the memory peripheral operates in a mode in
which the OE* signal is active low inside the low t im e of CS*.
When RSYNC is set to 0, the memory peripheral operates in a mode in
whic h the O E * signa l is act ive low outs ide the low tim e of CS*.
See "SRAM Syn c Read ( WAIT = 2)" on page 427 and "SRAM Async Read (WAIT =
2)" on page 432.
WSYNC Write synchronous mode
(D00)
0 – SRAM chip select write cycles will operate in asynchronous mode
1 – SRAM chip select write cycles will operate in synchronous mode
Controls the access timing of the WE* and CS* signals for non-DRAM memory
peripherals. The WSYNC bit is used only when the DRSEL bit is set to 0.
When WSYNC is set to 1, the memory peripheral operates in a mode in
which the WE * signal is active low inside the low time of CS*.
When WSYNC is set to 0, the memory peripheral operates in a mode in
which the WE* signal is active low outside the low time of CS*.
See "SRAM Sync Write (WAIT = 2)" on page 428 and "SRAM Async Write (WAIT =
2)" on page 433.
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Chip Select Option Register B and bit definitions
Chip Select Option Register B defines the level of synchronization performed
within the NET+50 chip for TA* input. The SYNC field applies only when the
EXTTA bit in the CSBAR is set to 1, for external trans fers. The TA* input must be
synchronized with the Net+ARM’s BCLK. During external transfers, the external
device sources the TA* signal. If the external device does not use BCLK when
generating TA*, either the 1- or 2-stage s y nchronizer must be used.
SYNC TA* input synchronizer
(D1:0)
00 – No synchronizer
01 – 1-stage sync hronizer
10 – 2-stage sync hronizer
11 – Reserved
You must use the 1- or 2-stage synchronizer setting when the TA* input
is asynchronous to the BCLK signal. (The 2-stage synchronizer is better
as it introduces one additional BCLK of latency in the access cycle.)
Use the “no sy nchronizer ” setting when the TA* input is synchr onous to
the BCLK signal .
Memory control signals
Several signals interface with memory (see page 120). Their functionality and
timing depend on the register settings.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Addres s = FFC0 0018 / 28 / 38 / 48 58
SYNC
0
R/W
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- --
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Memory Controller Module
Data bus (D31:0)
The data bus provides the data transfer path between the NET+50 chip and
external devic es . The data bus can be an 8-bit, 16-bit, or 32- bit size. The PS field in
the Chip Select Option register determines the data bus size.
The address bus acts differently for each setting:
An 8-bit data bus sources all addresses, and the NET+ARM’s A0 pin
attaches to the memory’s A0 pin.
A 16-bit data bus skips odd-numbered addresses, and the NET+ARM’s
A1 p in at taches to the me mory ’s A0.
A 32-bit data bus skips all addresses that are not divisible by four, and
the NET+A RM’s A2 pin attaches to the memory’s A0.
Peripheral devices
8-bit peripheral devices must always attach to the NET+50 chip using
D31:D24. The least significant data bit for 8-bit peripherals is D24. The
least significant address bit for 8-bit peripherals is A0.
16-bit peripheral devices must always attach to the NET+50 chip using
D31:D16. The least significant data bit for 16-bit peripherals is D16. The
least significant address for 16-bit peripherals is A1.
32-bit peripheral devices must always attach to the NET+50 chip using
D31:D00. The least significant data bit for 32-bit peripherals is D0. The
least significant address bit for 32-bit peripherals is A2.
Address bus (A27:0)
The NET+ARM address bus is 28 bits long. Under most conditions, the NET+ARM
can access 256 Mbytes of address space per chip select. To access all of the address
space, the A27_F and A26_F bits in the MMCR must be set to 1; otherwise, those
address bits are lost to another function and become unavailable as address
signals.
The behavior of the addr ess bus depends on the chip select configuration. The PS
(data port size) field, DRSEL (static vs. DRAM) field and the type of RAS/CAS
multiplexer all aff ect how the address r eacts.
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The address t hat eve ntually goes to a memory device origin ates in the A R M
program counter or the DMA module.The address goes through the MEM
module, where it is adapted to work with the type of memory for which the chip
select is configured. Each of the five chip selects can be configur ed dif ferently, to
respond to different sections of the memory map and to interface with eith er
DRAM or SRAM (flash an d EEP ROM us e SR A M t imi ng ).
Three factors affect the order of the address bits that finally reach the memory
device:
Data bus size: 8-bi t, 16- bit , 32-bit
Memory type: SRAM, external MUX, DRAM, or SDRAM
DRAM address mode
Chip selects/RAS (CSx*/RAS)
There are f ive chip select signals (CS[4:0]). Each chip select is enabled low when its
address space is accessed. The chip select timing depends on the configuration.
Each chip select has four configuration registers that determine the chip selects’
properties. All five chip selects are intercha ngeable, and have identical
functionality — with the exception of CS0*, which has an additional feature. CS0*
can automatically be configured on powerup (see "CS0* boot configuration" on
page 139).
When the chip select is configured as Fast Page or EDO DRAM, the chip select
functions as the DRAM’s RAS signal. DRAM does not use a chip select signal per
se but, in many ways , the RAS (r o w addr e ss st robe) signal is simila r. The RAS
signal shares the same NET+ARM pins as the CS* signals, its timing is similar, and
its address space is decoded with the same BASE and MASK values in the Chip
Select Base Address and Chip Select Opt ion registe rs. The RAS signal goes lo w
when the row address is valid. DRAM uses this signal to internally latch the row
address.
Setting the Chip Select address range
Each chip select should be configured to respond to a dif fer ent portion of the
memory map. Do this by setting the appropriate field in the Chip Select Base
Addre ss and Chip Select Option registers.
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Memory Controller Module
The MASK field in the Chip Select Option register defines the chip
select address space.
The BASE field in the Chip Select Base Address register defines the
starting address of the chip select address space.
The B ASE a nd MA SK fi e l d s are us ed i n c ombi natio n to decode the ad dres s sp a ce
that will be assigned to a chip select. The memory controller performs a logical
$1'
of the MASK and B ASE fields to determine whe t her the address space is assigned
to the peripheral device. The MASK field identifies those address bits, from A31
through A12, tha t are used in the address decoding function.
All ones in the MASK field indicates that the process should use the
associated address bit.
All zer o s i n the MASK fi el d in dicat es that the process should ign ore the
associated address bit.
Each ch i p sel ec t ’s addr ess space is at least 4096 bytes wide. Bits [11:0] are always
part of the address space no matter how bits [31:12] are configured. Any bit set to 0
in the MASK field is also part of the address space.
To determine if a logical address is associated with a chip select, apply the
following boolean equation:
^0$6.`ELWORJLFDODGGUHVV ^%$6(`ELWORJLFDO
DGGUHVV
where:
^0$6.`
refers to the MASK field concatenated with three nibbles of 0
^%$6(`
refers to the BASE field concatenated with three nibbles of 0
refers to the logical
$1'
function
refers to th e
HTXDOWR
operator
Example
This example illustrates setting the chip select address for 16 meg space.
&KLS6HOHFW2SWLRQUHJLVWHU [));;;0HJVSDFH
To determine the amount of address space, invert the value of the mask bits and
chang e the 12 “don’t care” bits to 1:
[));;;
=>
[))))))
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If the base is set to
, the memory spac e i s from
to
[))))))
. The allowable
locations f or the base are a multiple of 16; add 1 to
[))))))
to get the correct
address increment boundary:
[)))))) [
The correct values in the Chip Select Base Address r e gister would be
[;;;
[;;;[;;;[;;;
and so on, up to
[));;;
.
Any other value is truncated to the allowable boundary. Although a truncated
valu e ca n b e u sed, th e co de c an be h ar d to r ead. Fo r e xam ple, th e v alue
[;;;
truncates to begin at
[
rather than
[
.
Memory space
The memory space associated with an individual chip select does not have to be
continuous. Using the MASK field, you can set gaps in a single chip select range,
essentially assigning the same chip select to differ ent portions of the memory map.
Example
A 16 Mbyte device can be addresses in 4 different 64 Mbytes address locations by
usin g a MA SK f iel d va lu e of
[)
. Th e pe ri pher al de vice is a dd r ess ab le a t the se
address locations:
%$6([
%$6([
%$6([
%$6([&
Table 49 provides examples of mask settings and the related address space:
Mask Size
0xFFFFF 4K
0xFFFFE 8K
0xFFFFC 16K
0xFFFF8 32K
0xFFFF0 64K
0xFFFE0 128K
Table 49: Mask settings and re lated address space
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Memory Controller Module
CS0* boot configuration
Chip select 0 (CS0*) can be configured on powerup, which allows the ARM
processor to boot from a flash or EEPROM device attached to CS0*. On powerup,
the NET+ARM r eads the addr ess bus. If an address line is floating, the NET+ARM
reads a
; if a 1K pull-down resistor is attached to the address line, the NET+ARM
reads a
.
The binary values on A24 and A23 will configure CS0* on bootup. Table 50 shows
the four possible bootup configurations for CS0*:
0xFFFC0 256K
0xFFF80 512K
0xFFF00 1M
0xFFE00 2M
0xFFC00 4M
0xFF800 8M
0xFF000 16M
0xFE000 32M
0xFC000 64M
0xF8000 128M
0xF0000 256M
Mask Size
Table 49: Mask settings and re lated address space
ADDR[24:23] CS0 bootstrap setting A27 A26
“00”Disable A27 A26
“01”32-bit SRAM port; 15 wait-states A27 A26
“10” 32-bit FP DRAM port; 15 wait-states A27 A26
“11”16-bit SRAM port; 15 wait-states CSOOE CSOWE
Table 50: CS0* bootstrap settin gs
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These bootstrap settings set the values of the A27_F and A26_F bits in the Memory
Module Configuration register, the V bit in the CS0* Chip Select Base Address
register, and the WAIT and PS fields in the CS0* Chip Select Option register, as
shown in the following table:
Column address strobes (CAS)
CAS* signals are activated when an address is deco ded by a chip select module
that is configured for DRAM mode. The signal goes low when the column addr ess
is valid. DRAM uses this signal to internally latch the column address. After
receiving the row and column addresses, DRAM combines them internally so it
can access th e co r rect wo rd. On e CAS line is provid e d f or each DRA M by t e.
The CAS* signals also identify which bytes of the 32-bit data bus ar e active during
a given memory cycle, as shown in Table 51. Note the similarity between this table
and Table 52: "BE* lane configurations " on page 142.
ADDR[24:23] A27_F A26_F WAIT PS V
00 1 1 0000 00 0
01 1 1 1111 00 1
10 1 1 1111 00 1
11 0 0 1111 01 1
CAS*
Active
data bus
lane Little Endian
byte address
Big Endian
byte address Little Endian
word address
Big Endian
word
address
CAS3* D31:D24 3 0 1 0
CAS2* D23:D16 2 1
CAS1* D15:D08 1 2 0 1
CAS0* D07:D00 0 3
CAS* lane configuration for 32-bit peripherals
CAS3* D31:D24 1 0
Table 51: CAS* lane co nfigurations
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Memory Controller Module
Read/Write (R/W*)
The R/W* signal is high for a read cycle and low for a write cycle. This signal
usually is connected to the direction pin on a data transceiver.
Output enable (OE*)
The OE* signal is an active low signal that indicates that a memory read cycle is in
progr ess . The signal’s timing is configura tion-dependent.
Writ e en able (WE *)
The WE* signal is an active low signal that indicates that a memory write cycle is
in progress. The signal’s tim i ng is co nfi g u r a ti o n -d ep e nd e nt .
Byte enable (BEx*)
The BE* signals identify which 8 bytes of the 32-bit data bus are active during any
given syst e m bus memor y cy c le. Th e BE* signa ls a re active low. The NET+ARM
has a 32-bit data bus, which allows for four byte enable signals. The byte enable
signals (BE3*, BE2*, BE1*, BE0*) control which portion of the data bus is active.
One BE* signal is active low for each valid data byte. This BE* signal is used when
the micr opr ocessor wants to transfer less than 32 bits in a memory cycle.
CAS2* D23:D16 0 1
CAS* lane configuration for 16-bit peripherals
CAS3* D31:D24
CAS* lane configuration for 8-bit peripheral
CAS*
Active
data bus
lane Little Endian
byte address
Big Endian
byte address Little Endian
word address
Big Endian
word
address
Table 51: CAS* lane co nfigurations
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NET+50/20M Hardware Reference
BE3* is active for 8-bit bytes. BE3* and BE2* ar e active for 16-byte transfers. All BE*
signals ar e active for 32-bit transfers. The CAS* signals (see "Column address
strobes (CAS)" on page 140) perform the same function when interfacing with FP
or EDO DRAM. The BE* signals ar e used as DQM signals when interfacing to
SDRAM.
Table 52 shows the r elationship between the byte enable signals and the data bus
lanes. Note the similarity between this table and Table 51: "CAS* lane
configurations" on page 140.
Tr ansfer Acknowledge (TA*)
The TA* signal indicates the end of the current system bus memory cycle. TA* is
sampled on the rising edge of BCLK.
The TA* signal is either a NET+ARM input or output.
As an output, TA* signals the
7
part of a transfer cycle, The NET+ARM
reads the data bus on the rising edge of BCLK when TA* is low.
Byte
enable
Active
data bus
lane Little Endian
byte address
Big Endian
byte address Little Endian
word address
Big Endian
word
address
BE3* D31:D24 3 0 1 0
BE2* D23:D16 2 1
BE1* D15:D08 1 2 0 1
BE0* D07:D00 0 3
BE* lane configuration for 32-bit peripherals
BE3* D31:D24 1 0
BE2* D23:D16 0 1
BE* lane configuration for 16-bit peripherals
BE3* D31:D24
BE* lane configuration for 82-bit peripherals
Table 52: BE* lane config urations
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Memory Controller Module
As an input, TA* has the same function but is provided by the external
device to tell the NET+ARM wh en to read the data bus and whe n to
terminate the tran sfer.
Tr ansfer Error Acknowledge (TEA*)
The TEA* signal is either a NET+ARM input or output, and has two functions.
As an output, TEA* can be configured to signal a bus error or the last
transfer in a burst cycle. The functionality depends on how the BURST
bit (in the CSBAR register) is set.
As an input, the TA* signal has the same functionality but the signal is
provided by the external device.
Table 53 shows the TA* and TEA* signal configuration for terminating cycles.
Basic configurations
Any of the five chip selects can be configured to any of four basic modes. The four
basic modes are stat ic RAM (SRA M), fa st pag e (FP) DRA M, ext e nde d data output
(EDO) DRAM, and synchronous DRAM (SDRAM). All ch ip selects configured as
DRAM must be configured to the s ame mode.
Signal TA* TEA*
Burst cycle termination 0 0
Normal termination 0 1
Error termination 1 0
Waiting for completion 1 1
Table 53: Peripheral cycle termination
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NET+50/20M Hardware Reference
Static RAM
Figure 13 shows the memory signals that are available when the chip select is
configured as static RAM (SRAM). There are two timing variations —
synchronous and asynchr onous — for both the read and write cycl es. See "SRAM
timing," beginning on page 426, for synchronous and asynchronous read/write
timing diagrams.
Figure 13: SRAM chip select configuration
Configuring a chip select for SRAM
Use these procedures to configure a chip select for SRAM.
Note: SET
means you must use the value specified for the register field. For
example, set the V bit mea ns sele c t 1 for the Vbit field.
CHOOSE
means you can select a value for the field from two or more
options. For exam ple, Choose either A27 or CS0OE* means set the bit (0
or 1) for the function you want to use.
ARM
Program
Counter
DMA Modul e
Ch ip S elect Decoder
Bas e Addres s
Address Mask
CS 0*
CS 2*
CS 1
*
CS 3*
CS 4*
A[27:0] (8-bi t P or t)
Memor y Modul e
A[27:1] (16-bit Port)
A[27:2] (32-bit Port)
R/W*
WE*
OE*
BE*[3:0]
T EA* ( in put or ou tput)
D[31:0]
T A * ( input or ou tpu t)
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Memory Controller Module
Memory Module Control register
For CS0* only:
1
$B)
Choose either A27 or CS0OE*.
2
$B)
Choose e i ther A26 or CS0W E*.
Chip Select Base Address register
The following fields are options for SRAM:
1
%$6(
Works with the MASK field in the Chip Select Option register to
configure address space.
2
3*6,=(
Choose the maximum page size for bursting if the BURST bit is set.
3
(;77$
Choose to allow externally-controlled transfers.
4
%8567
Choose to allow bursting.
5
:3
Choose to disable the ability to write to a device.
6
9
Set to enable the chip select. Set this bit last.
Chip Select Opt ion register
The following fields are options for SRAM:
1
0$6.
Works with the BASE field in the Chip Select Base Address register to
configure the address space.
2
:$,7
Choose to add wait states.
3
%&<&
Choose burst timing.
4
%6,=(
Choose the number of cycles in a burst.
5
36
Choose the data bus size — 8-bit, 16-bit, or 32-bit.
6
56<1&
Choose th e read transfer timing.
7
:6<1&
Choose the write transf er timing.
The field in Chip Select Option Register B is used only when the EXTTA bit is set in
the Chip Select Base Addr ess r egister.
Fast page and EDO DRAM
The only difference between fast page (FP) and EDO DRAM is the RAS and CAS
timing; see "Fast Page and EDO DRAM Timing," beginning on page 436. The two
DRAM modes are otherwise the same, and the information in this section applies
to both.
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NET+50/20M Hardware Reference
You have three options when producing the RAS/CAS addresses:
External RAS/CAS multiplexer
Mode-0 (1 0 CAS)
Mode-1 (8 CAS)
Figure 14 shows the memory signals that are available when the chip select is
configured for external DRAM multiplexing:
Figure 14: External DRAM multiplexer chip select configuration
A[27:0]
Memory Modul e
DMA Addr
AR M Addr
RAS bits
CAS bits
Ex t Mux
To DRAM
Addr Pi ns
Chip S elect Deco der
Base Addres s
Addr ess Mask
RAS1*
RAS0*
RAS3*
RAS2*
RAS4*
PORT C3
CAS * [3:0]
R/W*
WE*
OE*
BE*[3:0]
TA* (input or output)
TEA* (input or output)
D[31:0]
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Memory Controller Module
Configuring a chip select for FP or EDO DRAM
Use these procedures to configure a chip select for SRAM.
Note: SET
means you must use the value specified for the register field. For
example, set the V bit mea ns sele c t 1 for the Vbit field.
CHOOSE
means you can select a value for the field from two or more
options. For exam ple, Choose either the FP or EDO timing mode means
set the bit (0 or 1) for the function you want to use.
Memory Module Control register
Set the r efresh configuration:
1
5)&17
Set the refresh count.
2
5()(1
Set the refresh enable.
3
5&<&
Set the refresh perio d.
4
$08;
Choose an internal or ex ternal RAS/CAS mux for all DRAM chip
selects.
Chip Select Base Address register
The following fields are options for FP or EDO DRAM:
1
%$6(
Works with the MASK field in the Chip Select Option register to
configure the address space.
2
3*6,=(
Choose the maximum page size for bursting if the BURST bit is set.
3
'02'(
Choose e ither the FP or EDO timing mode.
4
'08;6
Choose either the internal or external RAS/CAS address multiplexer .
Note that this bit is for an individual chip selec t and can be superseded by
the AMUX setting in the Memory Module Control register.
5
(;77$
Choose to allow externally-controlled transfers.
6
'08;0
Choose the type of internal RAS/CAS multiplexing if the DMUXS
bit is set to internal mux setting.
7
,'/(
Choose to set a null BCLK period after each DRAM m em ory transfer.
8
'56(/
Set for DRAM tim i ng.
9
%8567
Choose to allow bursting.
10
:3
Choose to disable the ability to write to a device.
11
9
Set to enable the chip select. Set this bit last.
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NET+50/20M Hardware Reference
Chip Select Opt ion register
The following fields are options for FP or EDO RAM:
1
0$6.
Works with the BASE field in the Chip Select Base Address register.
2
:$,7
Choose to add wait states.
3
%&<&
Choose th e burst timing.
4
%6,=(
Choose the number of cycles in a burst.
5
36
Choose the data bus size — 8-bit, 16-bit, or 32-bit.
The field in Chip Select Option Register B is used only when the EXTTA bit is set in
the Chip Select Base Addr ess r egister.
External multiplex RAS/CAS addressing
The NET+ARM can be configur ed to interface with an external address
multiplexer. When in this mode, the entir e addr ess is pr ovided as it would be
when interfacing to SRAM. This mode provides enormous versatility in that
virtually any RAS/CA S address combin ation can be wired to the multiplexer.
The MEM modu l e sources th e RAS *, CAS *, a nd R/W* as usual for DRAM . T he
module also provides a signal to contr ol the external multiplexer. This signal
appears on the NET+ARM’s PORTC3 pin. The signal is low when the RAS* signal
is valid and high for the CAS address. See Figure 14, "External DRAM multiplexer
chip select configuration," on page 146.
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Memory Controller Module
DRAM Mode-0 addressing
The NET+AR M can provide an internal multiplexer to so urce the RAS/CAS
address sequence. Many DRAMs use 10 CAS addresses during memory transfers.
When the NET+ARM is conf igured in Mode-0 addressing, the MEM module
divides the lowest 20 used address bits into 10 RAS and 10 CAS signals:
A[19:0] for an 8-bit bus
A[20:1] for a 16-bit bus
A[21:2] for a 32-bit bus
Note, however, that the NET+ARM is not limited to interfacing to DRAMs with
only 10 RAS lines. The higher or der address bits that are not multiplexed can be
connected to the DRAM’s extra RAS pins.
Figure 15, "DRAM Mode-0 addressing," on page 150 shows how internal DRAM
Mode-0 addressing interacts with the MEM module.
Table 54: "DRAM Mode-0 addressing" on page 151 describes how the NET+50 chip
multiplexes the log ic al address signals through the physic al a ddr e ss sig nals
during the RAS and CAS timeframes.
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Figure 15: DRAM Mode-0 addressi ng
Bas e addres s
Addr ess mask
RAS
CAS
RAS
CAS
A12 + A[9:1]
RAS
CAS
A13 + A[10:2]
Chip s elect decoder
Internal DRAM
Multiplexing
Mode-0
16-bit data bus
A[27 :21 ] Can be us ed f or RAS or to create banks
A[19:10]
A20+ A[9:1]
A11 + A[8:0]
Internal DRAM
Multiplexing
Mode-0
8-bit data bus
A[27 :20 ] Can be us ed f or RAS or to create banks
A[18:9]
A19+ A[8:0]
Internal DRAM
Multiplexing
Mode-0
32-bit data bus
A[27 :22 ] Can be us ed f or RAS or to create banks
A[20:11]
A21+ A[10:2]
BE*[3:0]
D[31:0]
CAS * [3:0]
R/W*
WE*
OE*
T A * (input or out put )
T E A * (i nput or out put )
RAS0*
RAS1*
RAS2*
RAS3*
RAS4*
Program
counter
ARM
DMA modul e
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Memory Controller Module
Mode-0 addressing is useful for DRAMs with 10 CAS address lines.
.
Notes:
1Address lines A[27:20] can be used for extra RAS or to create banks with 8-bit DRAM
peripherals.
2Address lines A[27:21] can be used for extra RAS or to create banks with
16-bit DRAM peripherals.
3Address lines A[27:22] can be used for extra RAS or to create banks with
32-bit DRAM peripherals.
Multiplexed pins
NET+ARM
pins A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
DRAM pin A9 A8A7A6A5A4A3A2A1A0
AMUX FCTN
0 RAS 18 17 16 15 14 13 12 11 10 9
1 CAS 19 876543210
8- bit DRAM peripheral (20 Address Bits: 10 RAS and 10 CAS)
DRAM pin A9 A8A7A6A5A4A3A2A1A0
AMUX FCTN
0 RAS 19 18 17 16 15 14 13 12 11 10
1 CAS 20 987654321
16-bit DRAM periph e r al (20 Address Bits: 10 RAS a n d 10 CAS )
DRAM pin A9 A8 A7A6A5A4A3A2A1A0
AMUX FCTN
0 RAS 20 19 18 17 16 15 14 13 12 11
1 CAS21 1098765432
32-bit DRAM periph e r al (20 Address Bits: 10 RAS a n d 10 CAS )
Ta ble 54: DRAM Mode-0 addre ssing
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DRAM Mode-1 multiplexing
Many DRAMs us e 8 CAS addresses durin g memory transfers.
When the NET+ARM is configured for Mode-1 addressing the MEM
module divides A[21: 0] into 14 RAS and 8 CAS signal s when configur ed
as an 8-bit bus.
When configured as a 16-bus bit, A[21:1] is divided into 13 RAS and 8
CAS signals.
When configured as a 32-bit bus, A[21:2] is divided into 12 RAS and 8
CAS signals.
In all cases, address bits A[27:22] can be used as extra RAS or bank select signals .
EDO and FP DRAM can use either Mode-0 or Mode-1 addressing. SDRAM always
uses Mode-1 addressing.
Figure 16, "DRAM Mode-1 addressing," on page 153 shows how internal DRAM
Mode-1 addressing interacts with the MEM module.
Table 55: "DRAM Mode-1 addressing" on page 154 describes how the NET+50 chip
multiplexes the log ic al address signals through the physic al a ddr e ss sig nals
during the RAS and CAS timeframes.
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Memory Controller Module
Figure 16: DRAM Mode-1 addressing
Program
counter
ARM
DMA module
Bas e addres s
Address mas k
RAS
CAS
RAS
CAS
A[13:1]
RAS
CAS
A[13:2]
Chip s elect decoder
Internal DRAM
Multiplexing
Mode-1
16-bit data bus
A[27 :22 ] Can be used for RAS or to create banks
A[21:9]
A[8:1]
A[13:0]
Internal DRAM
Multiplexing
Mode-1
8-bit data bus
A[27 :22 ] Can be used for RAS or to create banks
A[21:8]
A[7:0]
Internal DRAM
Multiplexing
Mode-1
32-bit data bus
A[27 :22 ] Can be used for RAS or to create banks
A[21:10]
A[9:2]
BE*[3:0]
D[31:0]
CAS * [3 :0 ]
R/W*
WE*
OE*
CS 0*
CS 1*
CS 2*
CS 3*
CS 4*
T A * (i nput or out put )
TEA* (input or output)
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Mode-1 addressing is useful for DRAMs with 14RAS/8CAS addr ess lines.
Notes:
1Address lines A[27:22] can be used for extra RAS or to create banks with
8-bit DRAM peripherals.
2Address lines A[27:23] can be used for extra RAS or to create banks with
16-bit DRAM peripherals.
3Address lines A[27:24] can be used for extra RAS or to create banks with
32-bit DRAM peripherals.
Direct pins Multiplexed pins
NETARM
pin A23 A22 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
SDRAM pin A13A12A11A10 A9A8A7A6A5A4A3A2A1A0
AMUX FCTN
0 RAS 21 20 19 18 17 16 15 14 13 12 11 10 9 8
1 CAS lowlowlow10201976543210
8- bit DRAM peripheral (22 Addr Bits: 14 RAS and 8 CAS)
SDRAM pin A13 A12A11A10A9 A8A7A6A5A4A3A2A1A0
AMUX FCTN
0 RAS 22 21 20 19 18 17 16 15 14 13 12 11 10 9
1 CAS 22 lowlowlow10987654321
16-bit DRAM periph e r al ( 2 2 Add r b it s : 14 RAS and 8 CAS)
SDRAM pin A13 A12 A11A10 A9 A8 A7A6A5A4A3A2A1A0
AMUX FCTN
0 RAS 23 22 21 20 19 18 17 16 15 14 13 12 11 10
1 CAS23 22 lowlowlow1098765432
32-bit DRAM periph e r al ( 2 2 Add r b it s : 14 RAS and 8 CAS)
Ta ble 55: DRAM Mode-1 addre ssing
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Memory Controller Module
SDRAM
When the Memory interface is set to SDRAM mode, the memory device must be
initialized with the load-mode command befor e the registers are configured.
When the Load-Mode command is issued, the SDRAM looks at its address bus
and configures itself based on the number it reads. The number that appears on
the address bus depends on the BCYC and BSIZE field settings in the Chip Select
Option register.
BCYC can be set to a CAS latency of 1, 2, 3, or 4. This is the CAS latency
you want the SDRAM to respond to.
BSIZE must be set to 11, for full page. This is the only valid value at
initialization.
The NET+ARM issues the SDRAM Load-Mode command whenever the V bit is
set in the Chip Select Base Address register. You can change the BCYC and BSIZE
fields after SDRAM is initialized, but the V bit should never be toggled. Otherwise,
the SDRAM device can be inadvertently reconfigured with an erroneous setup.
Be sure the port size has been set to the proper width (PS field in the CHip Select
Option register).
Load-Mode procedure: Setting up the Load-Mode command
Note: SET
means you must use the value specified for the register field. For
example, set the refresh enable means select 1 for the REFEN field.
CHOOSE
means you can select a value for the field from two or more
options. For exam ple, Choose to allow b ursting means se t the bit (0 or 1)
for the function you want to use.
1Set the BCYC field in the Chip Select Option register to the CAS latency you
want to use:
BCYC CAS latency
00 1
01 2
10 3
11 4
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2Set the BSIZE fie ld in the Chip Select Option register to 11 for full page:
3Set the PS field in the C hip Select Option register to the proper bus size.
4Set the DRSEL field in the Chip Select Base Address register for DRAM
timing.
5Set DMODE field in the Chip Select Base Address register to SDRAM
timing mode.
6Set the V bit in the Chip Select Ba se Address register to issue the Lo ad -
Mode command.
The MEM module loads the mode register with the values shown in this table:
The next table shows the binary value that appears on the address during the
Load-Mode command, for the four CAS latency options:
BSIZE Burst length
00 2 Words (not support ed)
01 4 Words (not support ed)
10 8 Words (not support ed)
11 Full page
16-bit port
address 32-bit port
address Value and Function SDRAM field
12:10 13: 11 001 = Single access Write burst mode
9:8 10:9 00 = Standard operation Operation mode
7:5 8:6 BCYC + 1 = 001 to 100 CAS latency
4 5 0 = Sequential Burst type
3:1 4:2 111 = Full page Burst length
CAS latency setting 16-bit port address
value 32-bit port address
value
BCYC = 00, CAS lat = 1 xxx0 0100 0010 111x xx00 1000 0101 11xx
BCYC = 01, CAS lat = 2 xxx0 0100 0100 111x xx00 1000 1001 11xx
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Memory Controller Module
Only after the Load-Mode command has been configured can you configure the
chip select. Use these procedures
Memory Module Control register
Set the r efresh configuration:
1
5)&17
Set the refresh count.
2
5()(1
Set the refresh enable.
3
5&<&
Set the refresh perio d.
4
$08;
Choose an internal or ex ternal RAS/CAS mux for all DRAM chip
selects.
Chip Select Base Address register
The following fields are options for SDRAM:
1
%$6(
Works with the MASK field in the Chip Select Option register to
configure the address space.
2
3*6,=(
Choose the maximum page size for bursting if the BURST bit is set.
3
'08;6
Choose either the internal or external RAS/CAS address multiplexer .
Note that this bit is for an individual chip selec t and can be superseded by
the AMUX setting in the Memory Module Control register.
4
(;77$
Choose to allow externally-controlled transfers.
5
'08;0
Set the internal RAS/CAS multiplexing to Mode-1 if the DMUXS bit
is set to internal m ux setting.
6
,'/(
Choose to set a null BCLK period after each DRAM m em ory transfer.
7
%8567
Choose to allow bursting.
8
:3
Choose to disable the ability to write to a device.
9
9
This bit should have been set during the Load-Mode command. Do not
reset this bit.
BCYC = 10, CAS lat = 3 xxx0 0100 0110 111x xx00 1000 1101 11xx
BCYC = 11, CAS lat = 4 xxx0 0100 1000 111x xx00 1001 0001 11xx
CAS latency setting 16-bit port address
value 32-bit port address
value
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Chip Select Opt ion register
The following fields are options for SDRAM:
1
0$6.
Works with the BASE field in the Chip Select Base Address register to
configure address space.
2
:$,7
Choose to add wait states after the Precharge and Active comm ands
(see "SDRAM command descriptions" on page 161).
3
%&<&
Choose the burst timin g . The value can be changed from what it was
set to during the Load-Mode command.
4
%6,=(
Choose the number of cycles in a burst. The value can be can be
changed from what it was set to during the Load-Mode command.
5
36
This field should have been set before issuing the Load-Mode
command. Do not change the field.
The field in Chip Select Option Register B is used only when the EXTTA bit is set in
the Chip Select Base Addr ess r egister.
Figure 17, "SDRAM (Mode-1) addressing," on page 159 shows how internal
DRAM Mode-0 addressing interacts with the MEM module.
Table 56: "SDRA M (Mode-1) addressing" on page 160 describe s how the NET+50
chip multiplexes the logical address signals through the physical address signals
during the RAS and CAS timeframes.
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Memory Controller Module
Figure 17: SDRAM ( Mode-1) addre ssing
Bas e addres s
Addr ess mask
RAS
CAS
RAS
CAS
CAS 0 * + A[ 1 3 :1 ]
RAS
CAS
CAS 0 * + A[ 1 3 : 2]
Chip s elect decoder
Internal DRAM
Multiplexing
Mode-1
16-bit data bus
A[27 :22 ] Can be us ed f or RAS or to create banks
A[21:9]
A[8:1]
CAS0* + A[13:0}
Internal DRAM
Multiplexing
Mode-1
8-bit data bus
A[27 :22 ] Can be us ed f or RAS or to create banks
A[21:8]
A[7:0]
Internal DRAM
Multiplexing
Mode-1
32-bit data bus
A[27 :22 ] Can be us ed f or RAS or to create banks
A[21:10]
A[9:2]
BE*[3:0] = DQM
D[31:0]
CA S 3* = RA S
CAS 2 * = C A S
CAS 1* = WE
CA S 0* = A10/ A P
T A * (input or out put )
TEA* (input or output)
CS 0*
CS 1*
CS 2*
CS 3*
CS 4*
Program
counter
ARM
DMA modul e
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Mode-1 SDRAM multiplexing
SDRAM multiplexing is useful for SDRAMs with 14RAS/8CAS address lines.
Important:
Regarding NETARM address lines (A13), (A12), and (A11).
During CAS cycles, A13:11 are equal to 0 and must not be connected
to SDRAM bank select address lines. As an alternative, connect the
RAS address to the SDRAM pin in the same column.
Direct pins Multiplexed pins
NETARM
pin A23 A22 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
SDRAM pin A13A12 A11 A10 A9A8A7A6A5A4A3A2A1A0
AMUX FCTN
0 RAS 21 20 19 CAS0* 17 16 15 14 13 12 11 10 9 8
1 CAS 76543210
1L. Mode 11 CAS0* 9876543210
8- bit DRAM peripheral (22 Address Bits: 14 RAS and 8 CAS)
SDRAM pin A13 A12A11 A10 A9 A8A7A6A5A4A3A2A1A0
AMUX FCTN
0 RAS 22 21 20 CAS0* 18 17 16 15 14 13 12 11 10 9
1 CAS 87654321
1L. Mode 12 CAS0* 10 987654321
16-bit DRAM peripheral (22 Address bits: 14 RAS and 8 CAS)
SDRAM pin A13 A12 A11A10 A9 A8 A7A6A5A4A3A2A1A0
AMUX FCTN
0 RAS 23 22 21 CAS0* 19 18 17 16 15 14 13 12 11 10
1 CAS 98765432
1L. Mode 13 CAS0* 11 10 98765432
32-bit DRAM peripheral (22 Address bits: 14 RAS and 8 CAS)
Ta ble 56: SDRAM (Mode-1) addressing
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Memory Controller Module
Notes:
1Address lines A[27:22] can be used for extra RAS or to create banks with
8-bit DRAM peripherals.
2Address lines A[27:23] can be used for extra RAS or to create banks with
16-bit DRAM peripherals.
3Address lines A[27:24] can be used for extra RAS or to create banks with
32-bit DRAM peripherals.
SDRAM command codes
The SDRAM comm and codes are issued while the chip select input is active low,
and are registered using the low to high transition of the synchronous clock
(BCLK).
.
SDRAM command descriptions
Five signals control SDRAM functionality — chip select (CS), RAS, CAS, write
enable (WE), and A10/AP. The signals are active low, and are sampled on the
rising edge of the clock to perfo rm the function indicate d by the 5-bit code.
Load-mode. Initialize s SDRAM . The NET+ ARM produces this
command when the valid (V) bit is set in the Chip Select Base Address
register.
Command CSx* A13:0 CAS3*
RAS# CAS2*
CAS# CAS1*
WE# CAS0*
A10/AP
Inhibit1X XXXX
NOP 0X 111X
ACTIVE0Bank/Row011A10
READ0Column1010
WRITE0Column1000
Burst term0X 110X
Precharge0X 0101
Refresh0X 001X
Load mode0Op-Code0000
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When the V bit is set, the SDRAM loads the number on its address lines
into its internal mode register. NET+ARM issues the load command and
sets the address bus to produce the correct number. All SDRAM
configuration options are defaulted by the NET+ARM except CAS
latency. (See "Load-Mode procedure: Setting up the Load-Mode
command," beginning on page 155, for more information.)
Precharge. Alias row deselect command. You must deselect a row that has
been previously accessed before you can select another row. Otherwise,
two memory locations would be addressed at the same time.
Precharge is not required for every situation; for example, it is not
required when accessing a row in a different bank or accessing a
dif f erent column in the sa me row. The NetARM keeps track of previous
accesses and issues the precharge command only when needed.
Active. Latches the row and bank address into the SDRAM. This
command is similar t o RAS in an EDO DRAM.
Active is not r e qu ired for every situat io n; fo r exampl e, it is not requir ed
when accessing a different column in the same row as the previous
transfer. The NetARM keeps track of previous accesses and issues the
active command only when needed.
Write. Wr it es the d at a on t he d ata bu s to a column loca ti on provided b y
the address bus. This command is similar to CAS in an EDO DRAM.
Read. Latches the column address when issued; data will be available
either 2 or 3 clocks later (depending on the CAS latency selected). This
comm and is similar to CAS in an EDO D R AM.
No Operation (NOP). Either “no operati on” or continues the previous
operation. If this command is issued after the read command, data
continues to be sourced on each rising clock pulse (after the CAS
latency).
Burst Terminate. Must be issued at some point after a read command,
to stop the SDRAM from sourcing data two or three cycles (depending
on the CAS latency selected) after being issued. The NET+ARM reads
data at this point, even though data will continue to burst for two
cycles.
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Memory Controller Module
Burst terminate is always issued on the last data read even if there is
only one dat a wor d tha t is read (that i s, a singl e cycle rather than a burst
cycle).
Note:
If a har dwar e reset occurrs after a r ead command but before the
burst terminate command, the SDRAM device continues to drive
data onto the bus. This can caus e a data clash with the boot code.
To avoid this situation, you need to implement a burst terminate
solution. See "Burst terminate solution," beginning on page 168, for
complete information.
Inhibit. Issued when the NET+ARM is accessing other devices, such as
flash.
When the CS* line is high, SDRAM is n ot enabled. At le ast two inhib it
commands must be issued after the burst terminate command.
Otherwise, SDRAM continues to source data for two cycles after the
burst terminate command, preventing access to another memory
device.
Refresh. Performed when CS*, RAS*, and CAS* are low. The refresh
operation is the same as a CAS-before-RAS refresh in an EDO or FP
DRAM.
A10/AP Signal
The A1 0/AP (aut o prechar ge ) si g n al ha s t hree functions, depe ndi ng on which
comma nd i s is su ed . Th e si g n al i s co nn ec t ed to the SDR AM’s address A10 input.
During the active command, the signal acts as the A10 logical RAS address
signal. The CAS0* pin is driven with the logical value of A20, A19, or A18,
depending on the port size configuration defined in the Chip Select Option
register.
–A20 is driven on CAS0* for a 32-bit port size configuration.
–A19 is driven on CAS0* for a 16-bit port size configuration.
–A18 is driven on CAS0* for an 8-bit port size configuration.
During the precharge command, the signal is high (1 on the CAS0* pin) to
indicate that all banks should be precharged.
During read and w r ite commands, the signal is low to indicate that auto-
precharge should not occur; the NET+50 chip always drives 0 during read
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NET+50/20M Hardware Reference
and writ e commands. When the MEM module i s configur ed for SDRAM , the
CAS0 pin performs the precharge command.
NET+50 chip SDRAM interconnect
This section describes how to interconnect the NET+50 parts to standard 16M and
64M SDRAM components.
SDRAM x16 bursting considerations
The NET+50 chip cannot perform 16-bit burst operations from an x32 SDRAM.
Executing 16-bit Thumb code from a 32-bit SDRAM results in poor performance,
as the NET+50 chip does not perform burst operations for the 16-bit thumb
instruction fetches.
x32 SDRAM configuration
Table 57 identifies the interconnect between the NET+50 chip and SDRAM when
SDRAM is used in an x32 configuration. An x32 SDRAM configuration typically is
constructed using two x16 SDRAM components. In this table, the two components
are called “Device 1” and “Device 2.”
NET+50 chip
signal 16M SDRAM
signal 64M SDRAM
signal
CS/RAS* CS* CS*
CAS3* RAS* RAS*
CAS2* CAS* CAS*
CAS1* WE* WE*
CAS0* A10/AP A10/AP
Table 57: X32 SDRAM c onfiguration
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Memory Controller Module
BE3* UDQM* Device 1 UDQM* Device 1
BE2* LDQM* Device 1 LDQM* Device 1
BE1* UDQM* Device 2 UDQM* Device 2
BE0* LDQM* Device 2 LDQM* Device 2
A2 A0 A0
A3 A1 A1
A4 A2 A2
A5 A3 A3
A6 A4 A4
A7 A5 A5
A8 A6 A6
A9 A7 A7
A10 A8 A8
A11 A9 A9
A13 A11
A21 BA
A22 BA0
A23 BA1
BCLK CLK CLK
VCC CKE CKE
D31-D16 D15-D0 Device 1 D15-D0 Device 1
D15-D00 D15-D0 Device 2 D15-D0 Device 2
NET+50 chip
signal 16M SDRAM
signal 64M SDRAM
signal
Table 57: X32 SDRAM c onfiguration
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x16 SDRAM configuration
Table 58 identifies the interconnect between the NET+50 chip and SDRAM when
SDRAM is used in an x16 configuration. An x16 SDRAM configuration typically is
constructed using one x16 SDRAM component.
NET+50 chip
signal 16M SDRAM
signal 64M SDRAM
signal
CS/RAS* CS* CS*
CAS3* RAS* RAS*
CAS2* CAS* CAS*
CAS1* WE* WE*
CAS0* A10/AP A10/AP
BE3* UDQM* UDQM*
BE2* LDQM* LDQM*
BE1* - -
BE0* - -
A1 A0 A0
A2 A1 A1
A3 A2 A2
A4 A3 A3
A5 A4 A4
A6 A5 A5
A7 A6 A6
A8 A7 A7
A9 A8 A8
A10 A9 A9
A12 A11
Table 58: X16 SDRAM c onfiguration
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Memory Controller Module
WAIT configuration
The WAIT configuration provides the SDRAM TRCD and TRP parameters.
–When WAIT is configured with a value of 0, the active and precharge
commands can be followed immediately by another command on the
next active edge of BCLK.
–When WAIT is configured with a value larger than 0, wait states are
inserted after the active and precharge commands before another
command can be issued.
A20 BA
A21 BA0
A22 BA1
BCLK CLK CLK
VCC CKE CKE
D31-D16 D15-D0 D15-D0
NET+50 chip
signal 16M SDRAM
signal 64M SDRAM
signal
Table 58: X16 SDRAM c onfiguration
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Burst terminate solution
If the NET+ARM experiences a reset after a read command and before a burst
terminate command, SDRAM components continue to drive the data bus. This
prevents the NET+ARM from being able to reboot from CS0*. Two options are
available to avoid this situation.
Option 1 i s a three-ga te so lut io n used onl y when a hardwar e reset i s t he
only possible way to reset the application.
Opt ion 2 requires more circuit ry bu t can recover from hardware, watch-
dog , or softw are reset conditions.
Option1
Figure 18 presents both a timing diagram (top) and schematic (bottom) for the
three-gate option.
The bur s t te rm i na t e co mma n d is a sse r t ed wh enever th e c hi p sel e ct (C S* ) an d th e
write enable (WE* ) signals on the SDRAM are low. This condition occ urs only
during state 3 (B1) of the timing diagram. During normal operation (state 2), the
BUR_TERM signal is high, which allows the CAS1*/WE* * and the CS* signal (see
"SDRAM command codes " on page 161) to work in conjunction with the other
SDRAM signals to produce other SDRAM commands (for example, precharge or
active).
During reset, all GPIO lines are configured as inputs. The pullup resistor attached
to the GPIO line assures that this signal will go high during reset. After reset, the
firm war e must se t this GPIO sign al low to pr o duce t he T3 state if a ha r dwar e r e set
occurs.
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Memory Controller Module
Figure 18: Option 1
Option 2
Option 2 has additional components that give the added capability of pr oducing
the burst terminate command when the watch-dog or software reset occurs.
Figure 19 presents both a timing diagram (top) and schematic (bottom) for
option 2.
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NET+50/20M Hardware Reference
Figure 19: Option 2
If the application needs to use the internal watch-dog and software RESET
condition, additional gates are required. The same three gates as us ed in Option 1
are used with the OR gate connected to a gate-constructed buffered flip-flop and to
the output of an EOR gate. The flip-flop inhibits BUR_TERM during cold starts.
RESET* low and GPIO high leave s this flip-flop in the inhibit state.
A powerup reset condition caus es NOP command s to be issued to the SDRAM
since RESET* i s l o w an d th e G PIO is high (poweru p de fa ul t ) . Aft e r RESET* is
driven high, system initialization firmware drives the GPIO signal low. An
external RESET* input or a brownout condition causes the burst terminate
command to be issued immediately, since both RESET* and GPIO are low. The
EOR gate is forced low by its inputs being equal. The buffer ed flip-flop is for ced to
the enable mode by GPIO being low. The burst terminate command continues
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Memory Controller Module
until the GPIO is forced to a value of 1 as a result of the RESET after an internal
sampling delay. NOP commands are sent to the SDRAM until the external RESET*
signal returns to 1. The circuit becomes armed again when firmware drives the
GPIO signal to 0.
A watchd og time-out or a software RESET causes an internal hardware RESE T,
forcing the GPIO to a value of 1. Since both RESET* and GPIO are equal, the EOR
will output a low. The buffered flip-flop is still in the enable mode since RESET*
has not been driven low. The SDRAM will be issued burst terminate commands
until the GPIO bit is set to 0. Firmware must set the GPIO to a value of 0 to enable
use of the SDRA M.
The fo l l ow ing co d e example en abl e s t he GP IO fi x:
ZRUNDURXQGIRU6'5$0EXUVWWHUPLQDWHXVLQJ3257&
6HWGLUHFWLRQRI3257&WR287387
1&&B*(1SRUWFUHJ_ [
6HW&PRGHWR*3,2YDOXHWR
1&&B*(1SRUWFUHJ [EIIIIIEI
This code must be placed soon after the detection and initialization of SDRAM. It
is acceptable to enable the fix after the first read (which is likely to come during
detection) from the SDRAM.
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DMA Controller Module
CHAPTER 9
The NET+50 DMA controller supports ten DMA channels that facilitate the
movemen t of data between extern al memor y and i nternal p eripher als, mi nimizin g
CPU intervention. All ten DMA channels support both peripheral-to-memory (fly-
by) and memory-to-memory transfers. Four DMA channels support externally-
controlled transfers in both fly-by and memory-to-memory modes.
Note:
The information in this chapter applies to both the NET+50 and
NET+20M chips, unless otherwise noted.
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DMA transfers
Fly-b y operati on
There are two modes of fl y- b y op er a t i on :
Read mode. Transfers data from memory to a peripheral device.
Write mode. Transfers data from a peripheral device to memory.
When co nf igured f or f ly- by o pe rati on, the DMA co ntrolle r t ran sfer s dat a fr o m on e
of the NET+50’s internal peripherals (Ethernet, serial, 1284, and ENI) to a memory
location. The DMA controller does not touch the data — rather, it controls the flow
of data through the BBus and provides the external address for a single data
transfer operation. Each peripheral is assigned a dedicated DMA channel, as
shown in Table 59 on page 176.
Figure 20 is a simple representation of DMA fly-by mode:
Figure 20: DMA fly-by transfers
Memory-to-memory operation
When configured for memory-to-memory (read-to-write) operations, the DMA
controller transfers data between two memory locations, using a temporary
holding register between read and write operations. Two m em ory cycles are
executed; each read cycle is followed by a write cycle.
Memory
DMA
acknowledge
Address
Data
DMA
channel
Peripheral
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DMA Controller Module
Figure 21 is a simple representation of DMA memory-to-memory mode:
Figure 21: DMA memory-to-m emory transfe r
DMA module
Figure 2 2 sh ow s a blo ck d i ag r a m of th e DM A mo d ul e . The DM A mo d ule has a
centralized single state machine and a block of static RAM referred to as the context
RAM. The context R AM co nt a i ns the curren t st a t e o f ea ch DM A ch a nn el . The
single state machine supports the DMA channels in parallel by context-switching
from channel to chann el. The DMA channel arbiter determines the channel on
which the machine is operating.
Figure 22: DMA channel block diagram
Addres s DMA c hanne l
Data
Data
Holding
register
Memory
DMA channel
arbiter
DMA cont rol
state machine
BBus
Data
out
Data
in
DMA
co n text RAM
128 x 32
Bus interface
Channel
transfer
attributes
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The arbiter requires six BCLK cycles to save the current context, one cycle to switch
and six to load new context. The DMA con troller, then, requires 13 clock cycles to
transition from one channel to another before starting transfer activity. Consider
this when evaluating bus bandwidth.
Note:
The 13 DMA cycles are usually hidden by CPU instructions because
closing and opening a DM A channel is handled independently by the
DMA controller and occurs while the CPU is accessing the bus.
DMA controller assignments
Table 59 and Table 60 show how the DMA channels are used in NET+50 chip
applications. There are two basic configurations:
Configurat ion 1 is used fo r IEEE 12 84 appli cation s, whic h use one to four
IEEE 1284 p arallel ports and two serial ports.
Configurat ion 2 is us ed in MIC appl icatio ns, which provide shared RAM,
FIFO mode, and two serial ports.
The D2:D0 bits in the MIC Control register determine which modes are set; see
Table 106, “MIC configurat ions,” on page 332 for information.
DMA direction codes
FB Write — Fly-by peripheral-to-memory
FB Read — Fly-by memory-to-peripheral
MM — Memory-to-memory copy from source pointer to destination
pointer
DMA channel Configuration 1: IEEE 1284 mode DMA direction
1 Ethernet receiver FB Write
2 Eth erne t transmi tter FB Read
3 IEEE 1284 channel 1 FB Read/Write
4 IEEE 1284 channel 2 FB Read/Write
5 IEEE 1284 channel 3 FB Read/Write
Table 59: DMA IEEE 128 4 mode channel assignments
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DMA Controller Module
Important:
The NET+2 0M chip uses a configuration similar to the MIC mode
configuration, with the following changes:
DMA channel 3 is external DMA 1 instead of FIFO mode receiver/
memory-to-memory.
DMA channel 4 is external DMA 2 instead of FIFO mode transmitter/
memory-to-memory.
6 IEEE 1284 channel 4 FB Read/Write
7 SER channel 1 receiver FB Write
8 SER channel 1 transmitter FB Read
9 SER channel 2 receiver FB Write
10 SER channel 2 transmitter FB Read
DMA channel Configuration 2: MIC mode DMA direction
1 Ethernet receiver FB Write
2 Eth erne t transmi tter FB Read
3 F IFO mode receiver/ memory- to- memory FB Write
4 F IF O mod e tra ns mit ter/memory- to-memory FB Read
5 Availabl e for memory -to-memor y MM
6 Availabl e for memory -to-memor y MM
7 SER channel 1 receiver FB Write
8 SER channel 1 transmitter FB Read
9 SER channel 2 receiver FB Write
10 SER channel 2 transmitter FB Read
Table 60: DMA MIC mode channel a ssignments
DMA channel Configuration 1: IEEE 1284 mode DMA direction
Table 59: DMA IEEE 128 4 mode channel assignments
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DMA Channel
The DMA channel is configured and controlled by a combination of configurat ion
registers and a buffer descriptor. Figure 23 on page 179 shows all possible D MA
configurations, combined into one diagram:
Fly- by (perip heral- to-memo ry)
Memory-to-memory
Extern al tr ansf ers
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DMA Controller Module
Figure 23: DMA channel structure
DMA buffer descriptor
All DMA channels operate using a buffer descriptor. Each DMA channel remains
idle until the DMA channel buffer descriptor is initialized and the DMA channel is
REQ
CE
CA
BB
BTE
SINC*
DINC*
SIZE
NCIP s
NRIP s
CAIP s
WRAP s
IDONE s
LAST s
FULL s
BLEN s
ECIP s
NCIE i
ECIE i
NRIE i
CAIE i
STATE s
INDEX s
Firs t buffer des criptor
W I L S o urce b u f f er poin ter
Status FBuf fer length
Des t ination buf fer point er
Rest of th e bu ffer des criptors
D
M
A
C
H
A
N
N
E
L
BDP Reg
Memory
Location
Peripheral
Fly-by Write Peripheral
Fly-by Read Memory L ocation
Mem-to-Mem
Ext ernal Device
DMA
Controller
MODE
DREQ*
DACK*
DONE*
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enabled using the Enable bit in the Channel Control register. After the DMA
channel is starte d, additional buffer descriptors are referenced by the original
buffer descriptor.
Each DMA buf fer descriptor requires two 32-bit words for fly-by mode and four
32-bit words for memory-to-memory operations. Multiple buffer descriptors are
located in contiguous memory locations. The fir st buffer descriptor address is
provided by the DMA chann el ’s buffer descriptor pointer. Subsequent buf f er
descri ptors are next to the fir st desc ri ptor. The final buffe r descr ipt o r is define d
with its W (wrap) bit set. When the DMA channel encounters the W bit, the
channel wraps around to the first descriptor.
Each DMA channel can address a maximum of 128 fly-by buffer descriptors or 64
memory-to-memory buffer descriptors. A DMA channel configured for more than
the maxi mu m nu mber o f b uffer descr i ptor s o per a tes u npredict abl y.
Figure 24: DMA buffer descriptor — Fly-b y-mode
Figure 25: DMA buffer descriptor — Memo ry-to-memory mo de
Reserved Buffer pointer Buffer length
WI L F
31 30 29 28 16 15 0
Offset + 0
Offset + 4
Reserved S o urce buffer po inter Buffer length
WI L F
31 30 29 28 16 15 0
Offset + 0
Offset + 4
Offset + 8
Offs et + C Destination buffer pointer
Reserved
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DMA Controller Module
Source buffer pointer
The source buffer pointer field identifies the starting location of the data buffer.
The source buffer pointer can start on any byte boundary for fly-by memory-to-
peripher al operations.
The source buffer poin ter must be aligned on 32-bit boundaries to support
peripheral-to-memory operations.
Bit Description
W Whe n the W (wrap) bit is set, it inf orms the DMA con troller that this is the last buffer
descriptor within the continuous list of descriptors. The first buffer descriptor is
found using the initial DMA channel buffer descriptor pointer.
When W is not set (0), the next buffer descriptor is found using an offset from
the current buffer descriptor. An unset WRAP bit acts as a continuation
indicator; that is, when W=0, the DMA channel continues to address buffer
descriptors until it encounters buffer descriptor with W set to 1.
When W is set (1), the bit wraps around to the first buffer descriptor.
See Figure 26, "DMA Buffer descriptor structure," on page 183 for an illustration.
I When the I bit is set, it tells the DMA controller to issue an interrupt to the CPU when
the buffer is closed due to a normal channel completion. The interrupt occurs
regardless of the normal completion interrupt enable configuration for the DMA
channel.
L When the L bit is set, it informs the DMA controller that this buffer descriptor is the
last descriptor and completes an entire message frame. The DMA controller uses this
bit to signal the peripheral. Use this bit when multiple descriptors are chained
together to constitute a data frame.
FFor fly-by operations, the F bit, when set, indicates the buffer is full. A DMA
channel sets this bit after filling a buffer and clears this bit after emptying a buffer. A
DMA channel does not try to empty a buffer with the F bit clear. Similarly, a DMA
channel does not try to fill a buffer with the F bit set. When the F bit is modified by
firmware, the firmw are dri v er must wri te t o the DMA Stat us/Inter rupt Enable
register in order to activate an idle DMA channel.
For memory-to-memory operations, the F bit must be set to 1 to begin DMA
operations. Memory-to-memory transfers will not start unless the F bit is set to 1.
Table 61: DMA Buffer Bit Descript ions
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Buff er len gth
The buffer length field is used in peripheral-to-memory, memory-to-peripheral,
and memory-to-memory operations. Buffer length can be up to 32,768 bytes.
Peripheral-to-memory
Uses this field in fly-by peripheral-to-me mory operations to indicate the
maximum number of bytes available in the receive buffer pointed to by the sour ce
buffer pointer. After filling a receive buffer with peripheral data, the DMA
controller updates this field with the receive data byte count.
Memory-to-peripheral
Uses this field in fly-by memory-to-peripheral operations to indicate the number
of bytes to move from the source address pointer to the peripheral device. After
completing a transmit buf fer descriptor, the DMA controller updates this field
with the data byte count (useful during error conditions).
Memory-to-memory
Uses this field in fly-by memory-to-memory operations to indicate the number of
bytes to move from the source address pointer to the peripheral device. After
completing a transmit buf fer descriptor, the DMA controller updates this field
with the data byte count (useful during error conditions).
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DMA Controller Module
Destination address pointer
The destination address pointer is used only when the DMA channel is configured
for memory-to-memory operations, and provides the “write” address portion of
the transfer . The destination address pointer must start on the same byte boundary
as the source address pointer.
Figure 26: DMA Buffer descriptor structure
Multiple buffer descriptors are necessary when you need to provide for more bytes
than the length of a sing le buffer descriptor. Maxim um buffer length is 32,768
bytes. If the DMA channel is larger than 32,768 bytes, one or more buffer
descriptors (as needed) must be appended to the first buffer descriptor. For
example, fo r 40,000 bytes, two buffer descriptors are used.
DMA channel configuration
Each DMA channel has a block of configuration space that is mapped into the
DMA module configuration space as shown:
DMA
channel n
buffer des criptor pointer
BD 1
BD 2
BD 3
BD 4
W
0
0
0
1
Fly-by des criptor
Address Register
FF90 0000 DMA 1 buffer descriptor pointer
FF90 0010 DMA 1 A control register
Table 62: DMA channel configuration
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FF90 0014 DMA 1 A status register
FF90 0020 DMA 1 B buffer descriptor pointer
FF90 0030 DMA 1 B control register
FF90 0034 DMA 1 B Status Register
FF90 0040 DMA 1C buffer descriptor pointer
FF90 0050 DMA 1 C control register
FF90 0054 DMA 1 C status register
FF90 0060 DMA 1 D buffer descriptor pointer
FF90 0070 DMA 1 D control register
FF90 0074 DMA 1 D status register
FF90 0080 DMA 2 buffer descriptor pointer
FF90 0090 DMA 2 control register
FF90 0094 DMA 2 status register
FF90 00A0 DMA 3 buffer descriptor pointer
FF90 00B0 DMA 3 control register
FF90 00B4 DMA 3 status register
FF90 00C0 DMA 4 buffer descriptor pointer
FF90 00D0 DMA 4 control register
FF90 00D4 DMA 4 status register
FF90 00E0 DMA 5 buffer descriptor pointer
FF90 00F0 DMA 5 control register
FF90 00F4 DMA 5 status register
FF90 0100 DMA 6 buffer descriptor pointer
FF90 0110 DMA 6 control register
FF90 0114 DMA 6 status register
FF90 0120 DMA 7 buffer descriptor pointer
FF90 0130 DMA 7 control register
Address Register
Table 62: DMA channel configuration
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DMA Controller Module
DMA registers
Each DMA channel has three registers: the buffer descriptor pointer, the DMA
Control register, and the D MA Status/Interrupt Enable register. Each registe r
contains the same information for each channel. The registers are 32-bits; all bits
are set to 0 on reset for the buffer descr iptor pointer and DMA Control register.
FF90 0134 DMA 7 status register
FF90 0140 DMA 8 buffer descriptor pointer
FF90 0150 DMA 8 control register
FF90 0154 DMA 8 status register
FF90 0160 DMA 9 buffer descriptor pointer
FF90 0170 DMA 9 control register
FF90 0174 DMA 9 status register
FF90 0180 DMA 10 buffer descriptor pointer
FF90 0190 DMA 10 control register
FF90 0194 DMA 10 status register
Address Register
Table 62: DMA channel configuration
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DMA buffer descriptor pointer
The DMA buffer descriptor pointer contains the address of the first buffer
descriptor in a contiguous list of descriptors. The last descriptor in the list is
identified with the W bit set in the buffer descriptor header.
Note that DMA channel 1 is unique in that it supports four differ ent buf fer
descriptors : A, B, C, and D. Each buffer descript or contains a separate ring of
descriptors, and each buffer descriptor identifies a block of data buffers with a
different size. This feature allows the Ethernet receiver to choose the optimum
buffer size for the incoming pack et.
DMA Control register and bit definition
BDP
BDP
0
R/W
0
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Addres s = FF90 0000 / 20 / 40 / 60 / 80 / A0 / CO / E0 / 100 / 120 / 140 / 160 / 180
BTE
STATE
0
R/W
0
R
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset
:
Reset
:INDEX
0
R
MODE
CA
CE REQ SINC* DINC* SIZE
0
R/W 0
R/W
BB
0
R/W 0
R/W 0
R/W
0
R/W 0
R/W
0
W
Addres s = FF90 0010 / 30 / 50 / 70 / 90 / B0 / D0 / FO / 110 / 130 / 150 / 170 / 190
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DMA Controller Module
Code
(Bit #) Definition of
code Description
CE
(D31) DMA channel
enable Must be set only after the other channel mode bits are set. The DMA
channel begins reading the first buffer description when CE is set to 1.
CA
(D30) Channel abort
request When the channel abort (CA) bit is set, it causes the current DMA
operation to complete and the buffer to be closed. The CA bit is not
automatically cl eared after th e requested abort is complete; firmware
must clear the CA bit after rec ognizi ng CAIP activ e.
BB
(D29:28) Bus bandwidth
field 00 – 100%; no limit
01 – 75%
10 – 50%
11 – 25%
Determines how often the DMA channel can arbitrate for access to
the bus. When set to 25%, the channel can only arbitrate one out of
four times; 50% gets two out of four times; 75% gets three out of four
times; 100% allows the DMA channel to arbitrate each time.
MODE
(D27:26) DMA operation
mode 00 – Fly-by write (from peripheral-to-memory)
01 – Fly-by read (memory-to-peripheral)
10 – Memory-to-memory (source-to-destination)
11 – Reserved
Identifies the data transfer mode. Each DMA channel can be
configured to operate in either fly-by or memory-to-memory mode.
BTE
(D25:24) Burst transfer
enable: fly-by
mode and
memory-to-
memory mode
Determines whether the DMA channel can use burst transfers through
the bus. Applies to both buffer descriptor a nd peripheral data access.
For DMA channel 1, the BB, MODE, and BTE configuration must be
the same in all four control registers (A, B, C, and D).
Note: The BURST bit i n t he C hip Se lect B ase Address register f or
the chip select associated with the DMA memory location
must also be set to allow bursting. See Chapter 8, "Memory
Controller Module."
Table 63: DMA Control re gister bit definition
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BTE
continued Burst transfer
enable: fly-by
mode and
memory-to-
memory mode
Fly-by mode :
00 – 1 Operand
01 – 2 Operands
10 – 4 Operands
11 – Reserved
In fly-by mode, the BTE field controls the maximum number of
operands the DMA cont roller moves each t ime it ac quire s cont rol of
the BBUS. When perfor ming DMA to an internal peri pheral , the
operand size is always 32-bits. When performing DMA to an external
peripheral, the SIZE field defines the operand size. The DMA
controller can move information using burst cycles. If the attached
memory peripheral device cannot support bursting or the peripheral
terminates the burst, the maximum number of bytes defined by BTE
is not achieved.
Memory-to-memory mode:
00 – No burst
01 – 8 Byte burst
10 – 16 Byte burst
11 – Reserved
When operating in memory-to-memory mode, the BTE field controls
the maximum number of bytes the DMA controller moves e ach time
it acquires control of the BBUS. The DMA controller moves
information using burst cycles. If the attached source memory
peripheral device cannot support bursting or the source peripheral
terminates the burst, the maximum number of bytes defined by BTE
is not achieved.
The DMA channel always delivers to the destination peripheral the
same number of bytes read from the source peripheral regardless of
whether the destination peripheral can support bursting. If the
destination peripheral cannot support bursting, the DMA controller
issues mul tiple bus cycles to complete the dat a move.
When operating in memory-to-memory mode, the SIZE field
determines the size of each operand moved. In general, it is always
more efficient to use a size of 32 bits; different values for SIZE are
required, however, when the address alignment boundaries for the
source and destination are mismatched.
Code
(Bit #) Definition of
code Description
Table 63: DMA Control re gister bit definition
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DMA Controller Module
REQ
(D23) Channel request
source 0 – Internal Peripheral
1 – Extern al P eri p heral
Allows channels 3, 4, 5, or 6 to be attached to either an internal
peripheral or an external peripheral (THOUGHT IT WAS
EXTERNAL ONLY). When an internal peripheral is selected, the
DMA channel is attached to the peripheral defined in Table 59,
“DMA IEEE 1284 mode channel assignments,” on page 176.
When an external peripheral is selected, channels 3 or 5 interface with
an external peripheral using handshaking signals multiplexed through
PORTA. Channels 4 or 6 interface with an external peripheral using
handshaking signals multiplexed through PORTB.
When the REQ bit is set to 1 in DMA channe l 3, the REQ bit in DM A
channel 5 is ignored and always assumed to be 0. Channel 5 can
interface only with an external peripheral through PORTA with the
REQ bit in DMA channel 3 set to 0.
When the REQ bit is set to 1 in DMA channel 4, the REQ bit in
channel 6 is ignored and always assumed to be 0. Channel 6 can
interface only with an external peripheral through PORTB with the
REQ bit in DMA channel 4 set to 0.
SINC*
(D21) Source addres s
increment SINC*
0 – Increment source address pointer
1 – Do not increment source address pointer
Can be used to control whether the source address pointer is
incremented after each DMA transfer. This bit is used by the DMA
controller in all modes whenever referring to a memory address. This
bit is not applicable when the source is an internal peripheral
resource.
DINC*
(D20) Destination
address increm ent DINC*
0 – Increment destination address pointer
1 – Do not increment destination address pointer
Can be used to control whether the destination address pointer is
incremented after each DMA transfer. This bit is used by the DMA
controller in all modes whenever referring to a memory address. This
bit is are not applicable when the destination is an internal peripheral
resource.
Code
(Bit #) Definition of
code Description
Table 63: DMA Control re gister bit definition
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SIZE
(D17:16) Data operand size 00 – 32-bit
01 – 16-bit
10 – 8-bit
11 – Reserved
Used by the DMA controller whenever configured for external
request mode (REQ bit; Channels 3, 4, 5, and 6 only) or memory-to-
memory DMA mode. These bits define the size of each DMA
transaction.
STATE
(D15:10) Current DMA
channel state 000000 – IDL E
000001 – Load source buffer address
000100 – Load destination buffer address
001000 – First operand
010000 – Memory-to-memory second operand
100000 – Update buffer description
Describes the curr ent state of the DMA controlle r state machin e.
INDEX
(D09:00) Current DMA
channel buffer
descriptor index
Identifies the DMA controller’s current byte offset pointer relative to
the DMA buffer descriptor pointer.
Code
(Bit #) Definition of
code Description
Table 63: DMA Control re gister bit definition
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DMA Controller Module
DMA Status/Interrupt Enable register and bit definition
Under normal operations, only the NCIP and NRIP interrupts are used; the other
interrupts indicate a failure. The interrupts are acknowledged by writing a 1 to the
register location, which resets the interrupt condition.
The interrupt enable (IE) bits can be set to cause an interrupt to occur when the
corresponding interrupt status bit is set in the DMA Status register. The interrupt
pending (IP) bits are set to indicate begin active. These bits are clear ed by writing a
1 to the same bit locations.
Code
(Bit #) Definition of
code Description
NCIP
(D31) Norm al
completion
interrupt pending
Set when a buffer descriptor has been closed (for normal conditions)
and either the NCIE bit is set or the IDONE bit was found active in
the current buffer descriptor. A no rmal DMA channel completion
occurs when the BLEN count expires to zero or when a peripheral
device signals completion.
ECIP
(D30) Error completion
interrupt pending Set when the DMA channel encounters either a bad buffer descriptor
pointer or a bad data buffer pointer. When the ECIP bit is set, the
DMA channel stops until the ECIP bit is cleared by firmware; the
DMA channel does not advance to the next buffer descriptor.
When ECIP is cleared by firmware, the buffer descriptor is retried
from where it left off. The CA bit in the Control register can be used
to abort the current buffer descriptor and advance to the next
descriptor.
Table 64: DMA Status/Interrupt Enable register bit definition
NCIE
0
R/W
0
R
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset
:
Reset
:0
R
CAIP
ECIP
NCIP ECIE FULL
0
R/C 0
R/C
NRIP
0
R/C 0
R/W 0
R/W
0
R/W 0
R
0
R/C
NRIE CAIE WRAP IDONE LAST
BLEN
0
R0
R
0
R
Addres s = FF90 0014 /N34 / 54 / 74 / 94 / B4 / D4 / F4 / 114 / 134 / 154 / 194
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NRIP
(D29) Buffer not ready
interrupt pending Set when the DMA channel encounters a buffer descriptor whose F
bit is in the incorrect state. When the NRIP bit is set, the DMA
channel stops until the NRIP bit is cleared by firmware; the DMA
channel does not advance to the next buffer descriptor.
When NRIP is cl eared by firmware, th e bu ffe r d escri p tor is ret ri ed .
CAIP
(D28) Channel abort
interrupt pending Set when the DMA channel detects the CA bit set in the Control
register. When CAIP is set, the DMA channel stops until the CAIP bit
is cleared by firmware. The DMA channel automatically advances to
the next buffer descriptor after CAIP is cleared. The CA bit in the
Control register must be cleared, usi ng firmware , before the CAIP is
cleared.
Failure to reset the CA bit causes the subsequent buffer descriptor to
also abort.
NCIE
(D23) Norm al
completion
interrupt enable
Used to enable interr upts to be generated when the ass ociated IP bi ts
are set. In general, the NCIE is used for inbound (WRITE DMA)
operations.
The DMA buffer descriptor I bit should be used for outbound (READ
DMA) operations. The ECIE and CAIE bits should always be
enabled.
Note: NCIE and the DMA buffer descriptor I bit should not be used
at the same time.
ECIE
D22) Error c o mpletion
interrupt enable
NRIE
(D21) Buffer not ready
interrupt enable
CAIE
(D20) Channel abort
interrupt enable
WRAP
(D19) Last descriptor in
descriptor list Provided for debugging purposes only. These bits serve no useful
purpose to the firmware device driver.
IDONE
(D18) Interrupt on done
LAST
(D17) Last buffer
descriptor in
current data frame
FULL
(D16) Buffer full
indicator
BLEN
(D14:00) Remaining byte
transfer count
Code
(Bit #) Definition of
code Description
Table 64: DMA Status/Interrupt Enable register bit definition
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DMA Controller Module
Ethern et receiver considerat ions
When an Ethernet frame is received, DMA channel 1 searches the four buffer
descr ipto r s fo r the opt imu m buffer siz e. Th e se arch order is A, B, C, D. The se arch
stops as soo n as the DMA channel encounters an available buffer that is large
enough to hold the entire receive frame. The search also stops when the DMA
channel encounters a DMA Control re gister whose channel enable (CE) bit is zero.
Because interrupts are set when the DMA channel encounters buff ers that are not
ready, the device driver should be designed with the smallest buffers in the A pool
and the lar gest buffers in the D pool. The number of available pools can be
configured (from 1 to 4) with proper use of the CE bits.
An Ethernet receive FIFO overrun condition can occur (the FIFO becomes full
while receiving an Ethernet packet) if insufficient buffers are alloca ted by the
application. If this condition occurs (signaled by the NRIP bit in the DMA
Channel 1 Status register; see "Ethernet Receive Status register and bit definitions,"
beginning on page 220) you must use the following procedure to guarantee
succ essful ope r at i on:
1Set the ERXDMA bit in the Ethernet General Control register to aero.
2Set the ERX bit in the Ethernet General Control register to zero.
3Set the channel enab le bit in the DMA control register to zero.
4Add new buffers for Ethern et DMA.
5Restore the DMA Control register.
6Restore the ERX bit.
7Restore the ERXDMA bit.
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External peripheral DMA support
NET+50 DMA channels 3, 4, 5, and 6 can be set up for external DMA transfers, and
use three signals (DREQ*, DACK*, and DONE*) to facilitate communications
bet ween the N E T+ 50 and an externa l de v i ce.
Note: You can use (turn on) only one DMA channel at a time.
It is up to the external device to source or react to these three signals. Th e N E T+50
can treat the external device as a data latch and do fly-by transfers, or as a block of
memory a nd do memo ry-to-memor y tra ns fer s.
Signal description
Figure 27 is a simple timing diagram of the DREQ*, DACK*, and DONE* signals.
See "External DMA timing," beginning on page 454, for more detailed diagrams.
Figure 27: External DMA timing
Signal Description
DREQ* An input to the NET+50, sourced by the external device. All transfers are initiated when
the external device asserts DREQ* low. When the external device wants a DMA transfer
(either read or write), it asserts the DREQ* signal. The DREQ* can either stay low until
all data transfers are complete (see the first example of DREQ* in Figure 5) or be
asserted once for each transf er (see the second example of DREQ * in Fi gure 5). E ith er
method is tr eated the same by the NET+50.
Table 65: External peripheral DMA support signal descri ptions
DRE Q* (i) Example 1
DRE Q* (i) Example 2
DACK* (o)
DONE* (i/o)
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DMA Controller Module
External DMA configuration
The REQ bit in the DMA control register must be set to 1 for external source, and
the DMA sign als must be chosen at I/O Ports A or B. Every thing else is set the
same as any other DMA transfer.
The NET+50 pins that have the DREQ*, DACK*, and DONE* signals are
multifunction al and are shared with GPIO ports A and B. PORTA has the DMA
channel 3 and 5 sign als and PORTB has the DM A channel 4 and 6 signals. Select
the DMA 3 or 5 signals with the PORTA Register (0xFFB00020) and the DMA 4 or 6
signals with the PORTB Register (0xFFB00024). To set DONE* as an input, set Port
A or B bit 0 to Mode = 1 and Dir = 0. To set DONE* as an output, set Port A or B bit
0 to Mode = 1 and Dir = 1.
DACK* An input to the external device, sourced by the NET+50. After the NET+50 receives
DREQ*, and it is ready for a data transfer, it will assert DAC K* low at the same time
that it asserts the data transfer signals (ADDR, R/W, CAS, RAS, etc.). DACK* should
be used by the external device as an enable for its memory. If DACK* and R/W* are
low, the external device should take data from its memory and put it on the data bus. If
DACK* is low and R/W* is high, the external device should take the data that is on the
data bus and put it in its memory.
DONE* Either an input or an output, depending on the configuration of the direction bit in the
GPIO configuration register.
Input fo r fly-by wri te:
When the transfer is a fly-by write (exter nal device to memory), t he external device can
send DONE* to the NET+50 to indicate that it has no more data to send. The external
device should make sure that the DONE* signal it sends to the NET+50 is asserted low
while DACK* is asserted low (it should OR the DONE* signal it sends with the DACK*
signal it receives) . When the NE T +50 rec eives the D ONE * signal, i t close s the curr ent
buffer and set the NCIP (Normal Completion Interrupt Pending) bit in the DMA status
register. Th e number of bytes t hat were r eceived will be in the buffer length fi eld of the
DMA buffer descriptor.
Output for fly-by read, fly-by write, and memory-to-memory:
When the transfer is a fly-by read (memory to external device), the NET+50 can send
DONE* to the external device to indicate that the last DMA buffer has been emptied.
The NET+50 asserts the DONE* output to the external device when the L (Last) bit is
set in the buffer descriptor and the buffer has been emptied. The NCIP (Normal
Completion Interrupt Pending) bit in the DMA status register will be set.
Signal Description
Table 65: External peripheral DMA support signal descri ptions
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NET+50/20M Hardware Reference
Enable the channel 3 or 5 signals with the PORTA register:
[))% [
(enable DREQ1*, DACK1*, and
DONE1* = input)
[))%
=
[
(enable DREQ1*, DACK1*, and
DONE1* = output)
Enable the channel 4 or 6 signals with the PORTB register:
[))%
=
[
(enable DREQ2*, DACK2*, and
DONE2* = input)
[))%
=
[
(enable DREQ2*, DACK2*, and
DONE2* = output)
Fly-by mode
In fly-by mode, the NET+50 treats the external device as an I/O port that it can
write to or read from. The NET+50 provides a 16- or 32-bit data bus, a 28-bit
addre ss bus, a read/ wri t e sign al a nd the DMA tra ns fe r sign als . Fi gure 28 show s
the signal s ne e ded fo r e xtern al fly -by DMA tr a nsf ers.
Pin number
Channel signal PQFP BGA Signal name Port A n umber
DMA 3- or 5-channel signals 39 F16 DREQ1* 6
43 E16 DACK1* 2
45 D14 DONE1* 0
DMA 4- or-6-channel signals 47 C15 DREQ2* 6
51 C16 DACK3* 2
55 A16 DONE2* 0
Table 66: DMA channel signals
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DMA Controller Module
Figure 28: Hardware needed for external fly-by DMA transfers
Fly-by write
During a fly-by write cycle, the external device must provide data that will be
written to memory. When the external device has data to write, it should assert
DREQ* low. The NET+50 then asserts DACK* and R/W* low and provides the
address of the memory location where the data will be written. The NET+50
provides ADDR[ 27 : 0], R/W* and CSx* signal s to the me mo ry t o a cc omplish d a ta
transfe r s. The external device should enable the data on to the data bus when
R/W* an d DAC K * are lo w and tri-state th e d a t a wh en R/W* or D ACK * is high .
When the external device has no more data to send, it should assert DONE* low.
Fly-by read
During a fly-by read, cycle data is read from memory onto the data bus so the
external device can receive it. When the external device wants a data transfer, it
should assert DREQ* low. The NET+50 then asserts DACK* low and provides the
address of the memory location wher e the data will be read. Data is valid when
DACK* goes low.
Memory
NET + ARM Ex ter nal device
DREQ*
Enable
DONE
Direction
DATA[31:0]
DREQ*
DACK*
DONE*
R/W*
DATA[31:0]
ADDR[27:0]
CS x*
CS *
ADDR[X:0]
DATA{31:0]
R/W*
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NET+50/20M Hardware Reference
Memory-to-memory mode
In memory -to-memory mode, the NE T+50 treats the external device as an
addressable block of memory. The NET+50 provides the external device the same
signals it would in fly-by mode, and it provides the address bus and a CSx* signal
so it ca n ac ce ss the ext er na l d evi c e’s mem ory. Figure 29 shows the signals needed
for external memory-to-memory DMA transfers.
The configuration of the buffer descriptor determines which side (NET+5 0
memor y or exter n al de vi ce memo ry) sou rces the da t a. If the so urc e buffer poi n te r
points to external device memory, the destination buffer pointer must point to
NET+50 memory. The transfer is then similar to a fly-by write, and DREQ* and
DACK* will act the same as in fly-by mode.
If the source buffer pointer points to NET+50 memory, the dest ination buffer
pointer must point to external device memory. The transfer is then similar to a fly-
by read, and DREQ* and DACK* will act the same as in fly-by mode. In either
direction, the external device initiates the transfer by asserting DREQ* low, and the
NET+50 takes over and controls the memory cycles.
Figure 29: Hardware needed for external memory-to-memory DMA transfers
Memory
NET + ARM Ex ter nal device
DREQ*
Enable
DONE
Direction
DATA[31:0]
ADDR[27:0]
CS
DREQ*
DACK*
DONE*
R/W*
DATA[31:0]
ADDR[27:0]
CS x*
CS x*
CS *
ADDR[X:0]
DATA{31:0]
R/W*
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DMA Controller Module
During memory-to-memory transfer, DACK* is asserted on both the r ead and
write portion s of the transfer. On the last access, the DON E* signal also asserts on
both the r ead and write portions of the transfer.
DMA controller reset
You can set the entire DMA controller module without affecting any of the
NET+50 modules by setting the DMA r eset bit in the GEN System Control register
to 1 and then back to 0 (see "DMARST" on page 66).
The DMA controller module is also reset by all forms of hardware and software
resets.
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Ethernet Controller Module
CHAPTER 10
The Ethernet controller module is divided into two modules: the EFE module,
which provides the Ethernet front end interface, and the MAC module, which
provides the Ethernet media access controller for both 10 and 100 Mbit
applications.
Note:
The information in this chapter applies to both the NET+50 and
NET+20M chips, unless otherwise noted.
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202 n n n n n n n
NET+50/20M Hardware Reference
Ethernet (EFE) front-end module
Figure 30 shows the hardwar e blocks re quir e d in the EFE module:
Figure 30: Ethernet c ontroller module block di agram
The E FE p r ovi des th e FI FOs an d g lue logi c r e qui r ed t o in terf ac e th e MAC wi th t he
NET+50 chip architecture.
The bas i c featur es of the EF E in clude:
Control/status registers for MAC, transmitter, and receiver.
128-by te transmit FIFO.
The transmit FIFO allows the critical portion of the transmit buf fer to sit
in the FIFO while collisions occur on the Ethernet medium. This scheme
removes the nee d for the transm itter to fetch the buffer multiple tim es
from memory.
DMA
controller
module
2048 byte
receive
FIFO 128 byte
transmit
FIFO
ENET
control
state
machine
Control
status
(CONFIG)
BBus
RX110
receive Addres s
filtering/
statistics 10/100 Ethernet MAC
TX110
transmit
Ether net I /O pads
10 BaseT MII
MAC modul e
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Ethernet Controller Module
2048-byte receive FIFO.
The large receive FIFO allows the entire Ethernet frame to be received
and to wait in the FIFO while the receive byte count is analyzed. The
receive byte count is analyzed to determine the optimum buffer
descriptor for DMA transfer; the DMA channel can use one of four
dif f erently-sized r eceiv e buffers. Only successfully receiv ed frames,
with acceptable destination addresses, are co mmitted to external system
memory.
DMA interface logic.
All control and status registers required by the Ethernet module ar e provided by
the E F E lo gi c . The transmitter a nd rece i v er ea c h p rovi de a 16-bit s ta t u s wo rd af t er
processing each Ethernet frame. These status words can be provided to the CPU on
an interrupt basis, or autom atically moved to the DMA buffer descriptor for the
associated Ethernet frame.
Media access controller (MAC) module
The MAC module interfaces with the EFE module on one side and with the
Ethernet I/O pins on the other. The MAC module supports both ENDEC and
media independent interfaces (MII) under firmware control.
Basic features in the MAC include:
100 Mbit Ethernet MAC
MII inte rface
Optional 100 Mbit physical coding sublayer
10 Mbit ENDEC interface
MII management functio n
Address filtering
Statistics gathering
The MAC module pr ovides a full-function 100 Mbit Ethernet MAC that can be
connected through the MII, a 100 Mb PHY, a 10 Mb PHY, a 100 Mbit TP-PMD, or
an ENDEC.
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Ethernet controller configuration
204 n n n n n n n
NET+50/20M Hardware Reference
The MAC module provides both station address logic (SAL) and statistics
gathering (STAT) blocks:
The SAL block filters the incoming receive addresses; the filter causes
the receive packets to be accepted or rejected.
The STAT block stores statistics for discarded transmit or receive
packets.
Note:
Reading or writing the MAC configuration registers (addres s loca tion
[)) through [))'&) is unreliable without valid clocks
available on the TXCLK and RXCLK input pins.
Ethern et controller configu ration
The Ethernet controller has a block of configuration space that is mapped into the
DMA module configuration space as shown:
Address Register
FF80 0000 Ethernet General Control register
FF80 0004 Ethernet General Status register
FF80 0008 Ethernet FIFO Data register (primary address)
FF80 000C Ethernet FIFO Data register (secondary address)
FF80 0010 Ethernet Transmit Status register
FF80 0014 Ethernet Receive Status register
FF80 0400 MAC Configuration register
FF80 0404 MAC Test register
FF80 0408 PCS Configuration register
FF80 040C PCS Test register
FF80 0410 STL Configuration register
FF80 0414 STL Test register
FF80 0440 Back-to-Back IPG Gap Timer register
Table 67: Ethernet controller configuration
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Ethernet Controller Module
FF80 0444 Non Back-to-Back IPG Gap Timer register
FF80 0448 Collision Window/Collision Retry register
FF80 0460 Transmit Packet Nibble Counter register
FF80 0464 Transmit Byte Counter register
FF80 0468 Retransmit Byte Counter register
FF80 046C Transmit Random Number Generator
FF80 0470 Transmit Masked Random Number
FF80 0474 Transmit Counter Decodes
FF80 0478 Test Operate Transmit Counters
FF80 0480 Receive Byte Counter
FF80 0484 Receive Counter Decodes
FF80 0488 Test Operate Receive Counters
FF80 04C0 Link fail counter
FF80 0500 10 Mbit jabber counter
FF80 0504 10 Mbit loss of carrier counter
FF80 0540 MII command register
FF80 0544 MII address register
FF80 0548 MII write data register
FF80 054C MII read data register
FF80 0550 MII indicators register
FF80 0580 CRC error counter
FF80 0584 Alignment error counter
FF80 0588 Code error counter
FF80 058C Long frame counter
FF80 0590 Short frame counter
FF80 0594 Late co llision counter
FF80 0598 Excessive deferral counter
Address Register
Table 67: Ethernet controller configuration
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Ethernet Registers
206 n n n n n n n
NET+50/20M Hardware Reference
Ethern et Registers
There are six sta n da rd Eth er n et registers in t he Eth er n et co ntro l l er :
General Control
General Status
FIFO Data register (primary address)
FIFO Data regi ster (se condary address)
Transmit Status
Receive Statu s
Each register is a 32-bit register unless otherwise noted.
FF80 059C Maximum collision counter
FF80 05C0 SAL address filter register
FF80 05C4 SAL station address
FF80 05C8 SAL station address
FF80 05CC SAL station address
FF80 05D0 SAL Multicast hash table
FF80 05D4 SAL Multicast hash table
FF80 05D8 SAL Multicast hash table
FF80 05DC SAL Multicast hash table
Address Register
Table 67: Ethernet controller configuration
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Ethernet Controller Module
Ethernet General Control register and bit definitions
The followin g fields should be set only once, on device open:
The following fields can be ignored if using DMA mode (DMA interface logic)
rather than inte rru pt servic e mode. DMA mode provides higher performance out
of the Ethernet chip, and can be turned on and off.
ERX
ETX
ERXDMA
ETXDMA
ERXLNG
ETXWM
ERXSHT
EFULLD
ERXBAD
ERXREG
ETXREG
ERFIFOH
ETFIFOH
ERXBR
ETXBC
EXT
0
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset: 0
R/W
ERXSHT
ERXDMA
ERX EXTDMA EFFULD
0
R/W 0
R/W
ERXLNG
0
R/W 0
R/W 0
R/W
0
R/W 0
RW
0
R/W
EXTWM EXTREG ETFIFOHEXTBC
0
RW 0
RW
0
RW
ERXBADERXBR
ERFIFOHERXREG
0
R/W
0
R/W
0
R/W
MODE LB RXCINV TXCINV pNA PDN AUI_T P LNK_DIS* LPBK UT P_ST P
0
R/W 0
R/W 0
R/W 0
R/W 0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Address = FF80 0000
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Ethernet Registers
208 n n n n n n n
NET+50/20M Hardware Reference
Code
(Bit #) Definition of
code Description
ERX
(D31) Enable RX FIFO 0 – Disables inbound data flow and resets the FIFO
1 – Enables inbound data flow
Must be set to 1 t o allow data to be re ceived fr om the MAC receiver.
Can be used to reset the receive side FIFO.
ERXDMA
(D30) Ena ble rece ive
DMA 0 – Dis ables inbound DMA data request (use to stall receiver)
1 – Enables inbound DMA data request
Must be set to 1 to allow the EFE module to issue receive data move
requests to the DMA controller. This bit can be cleared to temporarily
stall receive side Ethernet DMA.
Do not set this bit when operating the Ethernet receiver in interrupt
service mode.
ERXL NG
(D29) Acce pt long (>
1518 bytes)
receive packets
When set to 1, allows packets that are larger than 1518 bytes to be
accepted by the MAC.
ERXSHT
(D28) Acce pt short (<
64 bytes) receive
packets
When set to 1, allows packets that are smaller than 64 bytes to be
accepted by the MAC. The ERXSHT bit is used primarily for
debugging.
ERXREG
(D27)Enable Receive
Data registe r
ready interrupt
Must be set to 1 to generate an interrupt when data is available in the
RX FIFO.
ERFIFOH
(D26) Ena ble rece ive
data FIFO half
full interrupt
Must be set to 1 to generate an interrupt when the RX FIFO is at least
half full (1024 bytes).
ERXBR
(D25) Ena ble rece ive
buffer ready
interrupt
Must be set to 1 to generate an interrupt when a new data packet is
available in the RX FIFO.
ERXBAD
(D24) Acce pt bad
receive packets Whe n set to 1, the ERXBAD bit allows packets rec eived in error t o
be accepted by the MAC. Bad receive packets include those packets
with CRC errors, alignment errors, and dribble errors. The ERXBAD
bit is used primarily for debugging.
ETX (D2 3 ) Enable tr an sm i t
FIFO 0 – Disables outbound data flow and resets the FIFO
1 – Enables outbound data flow
Must be set to 1 to allow data to be written to the TX FIFO. Can be
used to reset the tra nsmit side F IF O.
Table 68: Ethernet Gene ral Control register bit definition
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Ethernet Controller Module
ETXDMA
(D22) Enable transmit
DMA 0 – Disables outbound DMA data request (use to stall transmitter)
1 – Enables outbound DMA data request
Must be set to 1 to allo w the EFE mo dule to iss ue transm it data mov e
requests to the DMA controller. This bit can be cleared to temporarily
stall tran smit side E thern et DM A.
Do not set this bit when operating the Ethernet receiver in interrupt
service mode.
ETXWM
(D21:20) Transmit FIFO
water mark
before transmi t
start
00 – 25% FIFO full
01 – 50% FIFO full
10 – 75% FIFO full
11 – 100% FIFO full
Identifies the minimum number of bytes required in the transmit
FIFO before the Ethernet transmitte r tries sending the packet. A
larger watermark set ting increa ses transmi t packet latency, allowing
for more slack in the memory system FIFO fill rate.
ETXREG
(D19)Enable Tra nsm i t
Data Registe r
ready interrupt
Must be set to 1 to generate an interrupt when the TX FIFO is ready
to accept data.
ETFIFOH
(D18) Enable transmit
data FIFO half
empty interrupt
Must be set to 1 to ge nerate an interrupt when the TX FIFO is at least
half empty (< 64 bytes).
Should be set only when operating the Ethernet transmitter in
interrupt service mode instead of DMA mode. In general, DMA mode
is preferred and ETFIFOH is not required to be set.
ETXBC
(D17)Enable transmit
buff er c o mp lete
interrupt
Must be set to 1 to generate an interrupt when the transmit packet
transmission is complete.
EFULLD
(D16) Enable full
duplex operation Must be set to 1 to allow the Ethernet TX and RX DMA operations to
operate simultaneously. This bit must be set when the Ethernet link
negotiation results in full duplex operation.
Code
(Bit #) Definition of
code Description
Table 68: Ethernet Gene ral Control register bit definition
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Ethernet Registers
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NET+50/20M Hardware Reference
MODE
(D15:14) Ethernet interface
mode 00 – 10/100 Mbit MII mode
01 – Reserved
10 – 10 Mbit level 1 ENDEC mode
11 – 10 Mbit SEEQ ENDEC mode
Identifies the type of Ethernet PHY attached to the NET+50 chip. The
NET+50 chip supports two types of Ethernet PHY: the MII PHY and
the ENDEC PHY.
The NET+50 chip also supports two types of ENDEC interfaces:
In SEEQ mode, the LPBK bit is inverted before driving the
MDC pin.
In Level1 mode, the PDN signal is driven using an open-drain
output driver.
LB
(D13) MAC configured
in internal
loopback
Must be set to 1 when the MAC or PCS blocks are configured to
operate in internal loopback mode. Failure to set the LB bit in these
conditions results in erratic receive side behavior.
RXCINV
(D12) Invert the receive
cl ock in p ut Should be set to 1 only when the external Ethernet PHY generates a
clock that is inverted in phase relative to what the MAC is expecting.
This bit is not required for most commercially available PHY devices.
TXCINV
(D11) Invert the
transmit clock
input
Should be set to 1 only when the external Ethernet PHY generates a
clock that is inverted in phase relative to what the MAC is expecting.
This bit is not required for most commercially available PHY devices.
pNA
(D10) pSOS pNA buffer
descriptors 0 – Standard receiver format. The data block immediately follows the
14-byte header block.
1 – pSOS pNA receiver format
When set to 1, configures the EFE module to allow the receiver to
provide receive data that is compatible with the pSOS pNA Ethernet
header and data block formats. The pSOS pNA configuration forces
the receiver to insert 2 bytes of data padding between the 14-byte
header and the data block sections. This configuration aligns both the
header and data blocks on a 32-bit long word boundary.
D7:D0
(D07:00) ENDEC media
control bits The least significant 8 bits of the Ethernet General Control register,
used only when the MODE field is configured for ENDEC mode.
In this configuration, several NET+50 chip signals are reconfigured
to provide simple control outputs. The control outputs can be used to
manipulate control signals on the external ENDEC PHY device. See
"Media control (ENDEC mode only)" for more information.
Code
(Bit #) Definition of
code Description
Table 68: Ethernet Gene ral Control register bit definition
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Ethernet Controller Module
Media control (ENDEC mode only)
Table 69 shows the relationship between the lower bits in the Ethernet General
Control register and the NET+50 chip pin. The NET+50 chip pins can be controlled
by the ENDEC media control bits only when the MODE field is co nfigured for
ENDEC mode.
Ethernet General Status register and bit definitions
The following fields can be ignored if using DMA mode (DMA interface logic)
rather than inte rru pt servic e mode. DMA mode provides higher performance out
of the Ethernet chip, and can be turned on and off.
Data
bit Signal
name NET+50
chip pin State inversion Description
D7 PDN TXD1 SEEQ: inverted TTL
Level1: inverted open
drain
Power down mode (D07):
0 - Normal
1 - External PHY in low power mode
D6 AUI_TP[ 1] TXD2 No inversion AUI/TP selecti on (D06:D 05):
00 - Auto select (with
/1.B',6
)
01 - AUI port
10 - TP port
11 - Reserved
D5 AUI_TP[ 0] TXD3 No inversion
D4 LNK_DIS* TXER No inversion 10BaseT link pulse disable (D04):
0 - Disable link pulse detection
1 - Enable link pulse detection
D3 LPBK MDC SEEQ: inverted
Level1: inve rted Enable loopback mode (D03):
0 - Normal mode
1 - External loopback mode
D2 UTP_STP MDIO No inversion Unshielded/shielded selection (D02):
0 - STP wiring
1 - UTP wiring
Table 69: ENDEC mode media control b its
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Ethernet Registers
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NET+50/20M Hardware Reference
RXFDB
RXSKIP
RXREGR
TXREGE
RXFIFOH
TXFIFOH
RXBR
TXBC
Code
(Bit #) Definition of
code Description
RXFDB
(D29:28) Receive FIFO
data bytes
available
00 – Full-word
01 – One byte
10 – Half-word
11 – Three bytes (LENDIAN determi nes whi ch three)
Must be used in conjunction with RXREGR (D27). When RXREGR
is set, RXFDB identifies how many bytes are available in the Receive
Data registe r.
Table 70: Ethernet General Status register bit definition
0
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset: 0
R
RXFDB TXFIFOE
0
R0
R
TXREGE TXFIFOH TXBC
0
R0
R/C
0
R
RXSKIPRXBR
RXFIFOHRXREGR
0
R/C
0
R
0
R
FullDuplex MANSENSE LINKPUL* AUT OMAN
0
R0
R0
R
Address = FF80 0004
AUD_TP
0
R
31 0
0
31
Lendian = 1
Lendian = 0
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Ethernet Controller Module
RXREGR
(D27) Rec eiv e Regi st er
ready Is set to 1 whenever data is available to be read from the FIFO Data
register. This bit, when set active high, can cause an interrupt to occur
when the ERXREG bit is also set (in the Ethernet General Control
register).
The RXREGR bit is never active when RXBR (D25) is set. The
RXBR bit must be cleared to activat e RXR EGR.
RXFIFOH
(D26) Receive FIFO
half full Is set to 1 whenever the receive FIFO is at least half full (>1024
bytes). This bit, when active high, can cause an interrupt to occur
when the ERFIFOH bit is also set (in the Ethernet General Control
register).
RXBR
(D25) Receive buffer
ready Is set to 1 whenever a new packet is available in the receive FIFO.
This bit, when active high, can cause an interrupt to occur when the
ERXBR bit is also set (in the Ethernet General COntrol register).
The RXBR bit is s et as an indicat or to the i nterrupt serv ice routine to
read the Ethern et Receive Stat us register. Af ter t he Ethernet Re ceive
Status register is read, the RXBR bit can be cleared by wr iting a 1 to
the RXBR bit position in the Ethernet General Status register. After
the RXBR bit is cleared, the RXREGR and RXF IFOH bits become
active.
RXSKIP
(D24) Receive buffer
skip Can be set to 1 instead of clearing the RXBR bit. Writing to the
RXSKIP bit clears the RXBR bit and flushes the next available packet
from the receive FIFO.
This bit provides a simple means of performing receive packet
filtering in the interrupt serv ice routine . When the Ethernet Receive
Status register has been read and RXSKIP is set to 1, the interrupt
service routine can flush the packet from the FIFO rather than reading
it out of the FIFO.
TXREGE
(D19) Transmit Register
empty Is set to 1 whenever the transmit FIFO is ready to accept data. This
bit, when active high, can cause an interrupt to occur when the
ETXREGE bit is also set (in the Ethernet General Control register).
The TXREGE bit is never active while TXBC(D17) is set. The TXBC
bit must be cleared to activate TXREGE.
TXFIFOH
(D18)Transmit FIFO
half empty Is set to 1 whenever the transmit FIFO is at least half empty (<64
bytes). This bit, when active high, can cause an interrupt to occur
when the ETFIFOH bit is also set (in the Ethernet General Control
register).
Code
(Bit #) Definition of
code Description
Table 70: Ethernet General Status register bit definition
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NET+50/20M Hardware Reference
Media status bits (ENDEC mode only)
Table 71 shows the r elationship between the lower bits in the Ethernet General
Status register and the NET+50 chip pin. The NET+50 chip pins can be monitored
by the ENDEC media control bits only when the MODE field is co nfigured for
ENDEC mode.
TXBC
(D17) Transmit buffer
complete Is set to 1 when packet transmission has completed. This bit, when
active high, can cause an interrupt to occur when the ETXBC bit is
also set (in the Ethernet General Control register).
The TXBC bit is set as an indicator t o the interrupt service routine to
read the Ethernet Transmit Status register. After the Ethernet
Transmit Status register is read, the TXBC bit can be cleared by
writing a 1 to the TXBC bit position in the Ethernet General Status
register. After the TXBC bit is cleared, the TXREGE and TXFIFOH
bits become active.
TXFIFOE
(D16) Transmit FIFO
empty Is set to 1 (active) when the transmit FIFO is empty.
D15:D0
(D15:00) ENDEC media
status bits The least significant 16 bits of the Ethernet General Status register are
used only when the MODE field is configured for ENDEC mode.
In this configuration, several NET+50 chip signals are reconfigured
to provide simple status inputs. The status inputs can be used to
monitor status signals on the external ENDEC PHY device. See
"Media status bits (ENDEC mode only)" for more information.
Data bit Signal
name NET+50
chip pin Description
D15 FullDuplex RXD2 Full duplex indicator (D15):
0 - Full duplex mode
1 - Half duplex mode
D13 Mansense RXD1 Jumper sense (D13):
0 - Jumper in
1 - Jumper out
Table 71: ENDEC mode media status bits
Code
(Bit #) Definition of
code Description
Table 70: Ethernet General Status register bit definition
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Ethernet Controller Module
Ethernet FIF O Data regi ster
The Ethernet FIFO D ata register is used to interface manually with the Ethern et
FIFO instead of using DMA support. This register can be used as a diagnostic tool.
Writing to the Ethernet FIFO Data register
Writing to the Ethernet FIFO Data register loads the transmit FIFO. This register
can be written to only when the TXREGE bit (
'
) is set in the Ethernet General
Status register, indicating that space is available in the transmit FIFO.
D12 AUI_TP RXD3 10 Mbit reverse polarity indicator (D12):
0 - TP port
1 - AUI port
D11 LINKPUL* RXER 10 Mbit link pulse indicator (D11):
0 - Disable link pulse detection
1 - Enable link pulse detection
D10 Automan RXDV AUTOMAN jumper sense (D10):
0 - AUTOMAN jumper in
1 - AUTOMAN jumper out
Data bit Signal
name NET+50
chip pin Description
Table 71: ENDEC mode media status bits
15 14 13 12 11 10 9876543210
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
0
R/W
0
R/W
FIFO
FIFO
Addres s = FF80 0008 / FF80 000C
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NET+50/20M Hardware Reference
The transmit FIFO has a secondary address (
))&
) that signifies the last word
of a transmit frame; this is used for polled or interrupt-driven access to the
Ethernet transmitter, and kicks off the transmission of a short packet onto the wire.
The f irs t a nd mi ddl e wo rd s of the fra me mu st us e th e pr imar y a ddr es s (
))
).
Reading from the Ethernet FIFO Data register
Reading from the Ethernet FIFO Data regi ste r em pties the receive FIFO. The
Eth ernet Gen eral Sta tus r egister identi fies how many bytes are availa ble to be read .
The receive FIFO is available only after the RXBR (
'
) bit has been cleared in the
Eth er n et Gener al St a t u s register. The Ethe r net Rece i ve Statu s regi ster (se e
page 220) should be read before clearing the RXBR bit.
Note:
When op er a t i ng in DM A mo d e, the Rece i ve St a t u s register is read
automatically and the RXBR bit is cleared automatically.
Ethernet Transmit Status register and bit definitions
The Ethe rn e t Transmit St a t us registe r co nt a ins the status for the last complet e d
transmit buffer. The transmit buffer complete bit (TXBC,
'
) is set in the Ethernet
General Status register when a transmit frame is completed and the Ethernet
T ransmit Status register is loaded. The lower 16 bits of the Ethernet T ransmit Status
register are also loaded into the Sta tusOrIndex fiel d of the DMA buffer descriptor
when using DMA mode.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset: 0
R
TXOK TXBR TXAL TXAED TXAEC TXCRC TXLCOL TXCOLC
0
R0
R0
R0
R0
R
0
R
0
R
0
R
Address = FF80 0010
TXDEF
TXAJ
TXAUR
TXMC
0
R
0
R
0
R
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Ethernet Controller Module
Code
(Bit #) Definition of
code Description
TXOK
(D15) Transmit packet
OK
Is set to 1 when the last Ethernet packet was transmitted without
error.
Is set to 0 when the last Ethernet packet was not transmitted.
TXBR
(D14) Transmit
broadcast packet Is set to 1 to indicate that the last Ethernet packet transmitted was a
broadcast packet.
TXMC
(D13) Transmit
multicast packet Is set to 1 to indicate that the last Ethernet packet transmitted was a
multicast packet.
TXAL
(D12) Transmit abort
late c o ll i s io n Is set to 1 to indicate that the last Ethernet packet was not transmitted
successfully — packet transmission was aborted due to a late
collision problem.
TXAED
(D11) Transmit abort
excessive deferral Is set to 1 to indicate that the last Ethernet packet was not transmitted
successfully — packet transmission was aborted due to excessive
deferral. Excess ive deferral means that there was a recei ve carrier on
the Ethernet channel for a long period of time, making it impossible
for the tr a nsm it t e r to tr y to transmit.
TXAEC
(D10) Transmit abort
excessive
collisions
Is set to 1 to indicate that the last E thernet packet was not transmitted
successfully — packet transmission was aborted due to an excessive
number of collisions. The maximum number of collisions allowed is
determined by the RETRY field in the Collision Window/Collision
Retry register (see page 238).
TXAUR
(D09) Transmit abort
underrun Is set to 1 to indicate that the last E thernet packet was not transmitted
successfully — packet transmission was aborted due to a FIFO
underrun condition. A FIFO underrun condition indicates that the
DMA controller was unable to fill the FIFO at a fast enough rate
compared to the rate of transmission on the Ethernet medium, for one
of these reasons:
The DMA controller was not configured for bursting.
The memory peripheral device was not configured for bursting.
The memory peripheral device is too slow to support the
Ethernet interface.
Table 72: Ethernet Transmit Status register bit definition
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NET+50/20M Hardware Reference
Ethernet Receive Status register and bit definitions
The E thernet Receive St a t us reg ist er conta i ns the stat us for the la st co mp l et e d
r ec ei ve buffe r. The re ceive buffer co mpl e t e bi t (RX BR ,
'
) is set in the Ethernet
TXAJ
(D08) Transmit abort
jumbo Is set to 1 to indica te that the last Ethernet packet was not transm itted
successfully — packet transmission was aborted due to a jumbo
condition. The jumbo condition means the packet was too large; that
is, greater than 1518 bytes. Packets larger than 1518 bytes are not
transmitted successfully unless the HUGEN bit is set in the MAC
Configuration register (see page 225)).
TXDEF
(D06) Transmit packet
deferred Is set to 1 to indicate that the last successfully-transmitted Ethernet
packet encountered a deferral. Transmission was delayed because the
Ethernet medium was busy at the time of first transmission attempt.
TXCRC
(D05) Transmit packet
CRC erro r Is set to 1 to indicate that the last successfully-transmitted Ethernet
packet had an embedded CRC error. This condition occurs only when
the CRCEN bit in the MAC Configuration register is set to 0 (see
page 224).
When CR CEN is set to 0, t he MA C doe s no t i nsert a CRC; th e MA C
expects a precompiled CRC to be contained in the last four bytes of
the Ethernet packet. If the MAC finds that the precompi led CRC i s
incorrect, the MAC sets the TX CRC bit in the Ethernet Transmit
Status register.
TXLCOL
(D04) Transmit packet
late c o ll i s io n Is set to 1 to indicate that the MAC encountered a late collision while
trying to transmit the Ethernet packet. TXLCOL indicates only that a
late collision event has occurred; if the packet transmission was
aborted, the TXAL bit (
'
) will be set.
The MAC tries to retransmit the packet when the RTRYL bit in the
MAC Configuration register is set to 1 (see page 224) .
TXCOLC
(D03:00) Transmit packet
collision count Indicates how many collisions the MAC encountered while it was
trying to transmit the packet. TXCOLC indicates only that collision
events have occurred; if the packet transmission was aborted, the
TXAEC (
'
) bit will be set.
The MAC tries to retransm it th e p ac k et up to th e maximu m n u mb e r
of collision retries defined by the RETRY field in the Collision
Window/Collision Retry register (see page 238).
Code
(Bit #) Definition of
code Description
Table 72: Ethernet Transmit Status register bit definition
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Ethernet Controller Module
General Status register when a receive frame is completed and the Ethernet
Rece i v e St a t u s regi s t er i s lo a d ed . Th e l ow er 1 6 b i t s of the Ethe r net Recei v e St a t u s
register are also loaded into the Sta tusOrIndex fiel d of the DMA buffer descriptor
(when using DMA mode).
Code
(Bit #) Definition of
code Description
RXSIZE
(D31:16) Receive packet
size Provides the number of bytes contained in the next packet to be read
from the Ethernet receive FIFO .
When using DMA mode, the RXSIZE field is also copied to the
Buffer Length field in the DMA buffer descriptor.
RXCE
(D15) Rec eive car ri er
event Is set to 1 to indicate that the MAC received a car rier event from the
Ethernet PHY since the last time a receive packet event was record ed
in this status register. The carrier event is not associated with this
particular packet.
A carrier event is defined as any activity on the receive channel that
does not result in a packet receive attempt being made.
RXDV
(D14) Receive da ta
event Is set to 1 to indicate that, at some point since the last recorded receive
packet event, a receive data event was detected, noted, and reported
with this receive packet event. The receive data event is not
associated with this particular packet.
A receive data eve nt is an event t hat occurs wi thout a valid preamble
and start frame delimiter (SFD) in the data stream.
RXOK
(D13) Rec eive packet
OK Is set to 1 to indicate that the next packet in the receive FIFO has been
received without any errors.
RXBR
(D12) Receive
broadcast packet Is set to 1 to indicate that the next packet in the receive FIFO is a
broadcast packet.
Table 73: Ethernet Re ceive Status register bit d efinition
15 14 13 12 11 10 987 65 4 321 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
0
R
0
R
RXSIZE
RXCV
Addres s = FF80 0014
RXCE RXDV RXOK RXBR RXMC RXCRCRXDR RXLNG RXSHT ROVER
0
R0
R0
R0
R0
R0
R0
R0
R0
R0
R
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NET+50/20M Hardware Reference
RXMC
(D11) Receive multicast
packet Is set to 1 to indicate that the next packet in the receive FIFO is a
multicast packet.
RXCRC
(D10) Rec eiv e CR C
error Is set to 1 to indicate that the next packet in the receive FIFO was
received wi th a CRC erro r .
RXDR
(D09) Receive dribble
nibble Is set to 1 to indicate t hat, a t the end of th e next packet i n t he recei ve
FIFO, an additional 1 to 7 bits of data (dribble nibble) were received.
This packet is still considered valid as long as the RXCRC bit (
'
)
is not set.
RXCV
(D08) Rec eive code
violation Is set to 1 to indicate th at the Ethernet PHY as serted the RXER signal
during the data phase of this frame. RXCV indicates that the PHY
encountered invalid receive codes while receiving the data.
RXLNG
(D07) Receive long
packet Is set to 1 to indicate that the next packet in the receive FIFO is longer
than 1518 bits. A long packet is accepted only when the ERXLNG bit
(
'
) is set in the Ethernet General Control register.
RXSHT
(D06) Receive short
packet Is set to 1 to in d icate th at th e n e x t pack e t in th e receive F IF O is
smaller than 64 bytes. A short packet is accepted only when the
ERXSHT bit (
'
) is set in the Ethern et General Contro l Register.
ROVER
(D05) Rec eive overrun Is set to 1 to indicate that a receive FIFO overrun condition has
occurred. An overrun condition occurs when the FIFO becomes full
while receiving an Ethernet packet. The FIFO overrun condition
indicates that t he DMA cont roller was not able to em pty the FIFO at
a fast enough rate compared to the rate that information was received
from the Ethernet medium for one of these reasons:
The DMA controller was not configured for bursting.
The memory peripheral device was not configured for bursting.
The memory peripheral device is too slow to support the
Ethernet interface.
All of the buffers in the Ethernet recei ve buffer were exhausted.
This can happen if the application software is unable to keep up
with incoming Ethernet traffic. One solution is to add more
buffers. See "Ethernet receiver considerations" on page 193.
Code
(Bit #) Definition of
code Description
Table 73: Ethernet Re ceive Status register bit d efinition
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Ethernet Controller Module
MAC registers
The Ethernet has two MAC registers:
MAC Configuration register. A 32-bit register that contains MAC
configuration options. All bits initialize to 0 on reset.
MAC Test register. A 32-bit register used only during hardware
simulation — never under normal operation conditions. All bits
initialize to 0 on reset.
MAC Configuration register and bit definitions
Code
(Bit #) Definition of
code Description
SRST
(D15) MAC sof t res et Is set to 1 to soft -r eset the MAC module.
Note: The SRST bit has been known to be unreliable. Because the
standard NET+50 hardware and software resets all reset the
MAC, a soft reset of the MAC is not required.
INTLB
(D14) Internal loopback Places the MAC module in internal loopback mode. This
configuration is useful for diagnostic testing of the MAC module.
Note: When the INTLB is set to 1, the LB bit (
'
) in the Ethernet
General Control Register must also be set
to 1.
Table 74: MAC Configuration register bit definition
15 14 13 12 11 10 987
654 32 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
0
R/W
Addres s = FF80 0400
SRST INTLB TSTMD NOBO
0
R/W 0
R/W 0
R/W
-- -- --
-- -- -- --
-- -- -- --
-- -- -- ----
RTRYL CRCEN PADEN FULLD HUGEN
-- -- ---- -- --
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NET+50/20M Hardware Reference
TSTMD
(D13:12) Transmit test
mode 00 – Normal operation
01 – Reserved
10 – Transmitter test mode
11 – Receiv e test mode
Used for simulation of the MAC module. This field must be set to 00
for normal functional operation of the MAC module.
NOBO
(D05) No backoff 0 – Backoff enabled
1 – Backoff disabled
Can be set to 1 to disable the backoff feature. The backoff fe ature is
used when a collision is detected, and causes the MAC to wait a
random amount of time before trying retransmission.
When NOBO is set, the MAC immediately tries to retransmit after the
jamming period is complete.
RTRYL
(D04) Retry late
collision Can be set to 1 to allo w the M AC to tr y a retran smissi on when a late
collis ion is detected. When RTRYL is set to 0 and a late collision is
detected, the transmission is aborted through the TXAL bit setting in
the Ethernet Transmit Status register (see page 218).
CRCEN
(D03) Append CRC Can be set to 1 to allow the MAC to automatically append a
calculated 4-byte CRC checksum at the end of the Ethernet data
frame.
When CRCEN is set to 0, the MAC expects the last four bytes of the
Ethernet data frame to contain a precompiled valid CRC value. The
MAC verifies that the precompiled
4-byte CRC value is correct. If the MAC fi nds an incorr ect CRC
value, the MAC reports the condition by setting the TXCRC bit in the
Ethernet Transmit Status register (see page 219).
PADEN
(D02) Auto pad enable Can be set to 1 to f orce the MAC to automatical ly pad fill all Ethernet
packets that are smaller than 64 bytes. The MAC automatically
inserts zero-byte padding at the end of the Ethernet data frame to
make the Ethernet packet the minimum required 64 bytes in size.
FULLD
(D01) Full duplex
enable Must be set to 1 to enable full duplex Ethernet operation.
To operate in true Ethernet full duplex mode, firmware must set this
bit to 1 after determining that the PHY is operating in full duplex
mode. When the FULLD bit is set to 1, the MAC transmitter ignores
any and all collision indications from the TXCOL input pin.
Code
(Bit #) Definition of
code Description
Table 74: MAC Configuration register bit definition
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Ethernet Controller Module
MAC Test register and bit definitions
There are two f i eld s in the MAC Test regi st er:
SIMR (
'
). Simulation reset.
TTXEN (
'
). Test transmit enable.
Both fields, when set to 1, are used only forsimulation of the MAC module. Both
fields must be set to 0 for normal functional opera tion of the MAC module.
HUGEN
(D00) Enable huge
frames Can be set to 1 to allow the MAC to transmit Ethernet packets that are
larger than 1518 bytes in size. When HUGEN is set to 1, the MAC
transmits E thernet packets of any size. W hen HUGE N is set to 0, the
MAC aborts transmission of all packets larger than 1518 bytes and
sets the TXAJ bit in the Ethernet Transmit Sta tus regist er (s ee
page 219) to indicate this condition.
Code
(Bit #) Definition of
code Description
Table 74: MAC Configuration register bit definition
15 14 13 12 11 10 987
65 43210
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
0
R/W
Addres s = FF80 0404
0
R/W
-- -- --
-- -- -- --
-- -- -- --
-- -- -- ----
SIMR TTXEN
-- -- ---- -- ---- -- ---- -- ---- --
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224 n n n n n n n
NET+50/20M Hardware Reference
PCS registers
The Ethernet module uses two Physical Coding Sublayer (PCS) registers:
PCS Configuration register. A 32-bit register that contains PCS
confi guration options. All bits initialize to 0 on reset.
PCS Test register. A 32-bit register that is used only during hardware
simulation — never under normal operating conditions. All bits
initialize to 0 on reset.
PCS Configuration register and bit definitions
Code
(Bit #) Definition of
code Description
SRST
(D15) Soft reset Is set to 1 to soft-reset the PCS module.
The SRST bit has been known to be unreliable. The standard NET+50
hardwa re and software r esets all reset th e PCS; as such, a so ft reset of
the PCS is not required.
INTLB
(D14) Internal loopback Is used to place the PCS module in internal loopback mode. This
configuration is useful for diagnostic testing of the PCS module.
When the INTLB is set to 1, the LB bit (
'
) in t he Ethe rnet Gen eral
Control register must also be set to 1.
Table 75: PCS Configuration register bit definition
15 14 13 12 11 10 987
65432 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset: 0
R/W
Addres s = FF80 0408
0
R/W
-- -- --
-- -- -- --
-- -- -- --
-- -- -- ----
ENJAB NOCFR
-- -- -- -- -- --
-- CLKS
SRST INTLB TSTMD EXINT
0
R/W
0
R/W 0
R/W
0
R/W 0
R/W
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Ethernet Controller Module
TSTMD
(D13:12) Test mode 00 – Normal operation
01 – Reserved
10 – PE100X test mode
11 – PE10T test mode
Used for simulation of the PCS module. This field must be set to 00
for normal functional operation of the PCS module.
EXINT
(D09:08) External interface
mode 00 – MII normal operation
01 – TP–PMD mode
10 – 10 Mbit ENDEC mode
11 – Reserved
Used for all modern MII style 10/100 PHY devices.
TP–PMD mode is used for older PHY that contain their own non-
standard physical coding sublayer (PCS) circuitry.
ENDEC mode configuration is used for the older 10 Mbit-only PHY
devices that predate the MII interface standard.
CLKS
(D02) Clock select 0 – 25 MHz
1 – 44 MHz
Used by the MAC to select the divide-down-ratio for the SYS_CLK
system clock to produce the management data clock (MDC). Setting
the bit divides SYS_CLK by 14; clearing the bit divides SYS_CLK
by 10.
MDC cannot exceed the specified frequency for the chosen PHY. The
timing of the MDIO pin versus the clock at the resulting frequency
should be verified.
See "System clock generation" on page 97 for system clock frequency
information.
ENJAB
(D01) Enable jabber
protection When set to 1, enables the jabber protection logic within the PCS
when the PCS is operatin g in ENDEC mode (see "EXINT
(D09:08)"). Jabber is the condition in which a transmitter is stuck on
for longer than 50mS, preventing other stations from transmitting.
NOCFR
(D00) Disable ciphering When set to 1, disables the ciphering login within the PCS when the
PCS is operating in TP–PMD mode (see "EXINT (D09:08)"). The
ciphering operation converts the
100Base-X service data unit (SDU) into the protocol data unit (PDU).
Code
(Bit #) Definition of
code Description
Table 75: PCS Configuration register bit definition
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226 n n n n n n n
NET+50/20M Hardware Reference
PCS Test register
There are three fi el ds in the PCS Test r egister :
SIMR (
'
). Simulation reset.
DLFC (
'
). Disable link fail counter.
FRC Q (
'
). Force quiet.
All fields, when set to 1, ar e used only for simulation of the PCS module. All fields
must be set to 0 for normal functional operation of the PCS module.
STL registers
The E thernet mo du le uses two St a t i on Log i c (S T L ) regis te r s:
STL Config uration register. A 32-bit register that contains various STL
configuration options. The STL contains both the statistics (STAT) and
station address logic (SAL) blocks. All bits initialize to 0 on reset.
STL Test register. A 32-bit register that is used only during hardware
simulation — never under normal operation conditions. All bits
initialize to 0 on reset.
15 14 13 12 11 10 987
65432 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset: 0
R/W
Addres s = FF80 040C
0
R/W
-- -- --
-- -- -- --
-- -- -- --
-- -- -- ----
DLFC FRCQ
-- -- -- -- -- --
-- SIMR
0
R/W
-- --
-- -- -- --
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Ethernet Controller Module
STL Configuration register and bit definitions
Code
(Bit #) Definition of
code Description
SRST
(D15) So ft r eset Is set to 1 to soft-r eset the STL module.
Note: The SRST bit has been known to be unreliable. Because the
standard NET+50 hardware and software resets all reset the
STL, a soft reset of the STL is not required.
TSTMD
(D13:12 Test mode 00 – Normal operation
01 – Reserved
10 – Statistics module test mode
11 – Station address logic test mode
Used for simulation of the STL module. This field must be set to 00
for normal functional operation of the STL module.
AUTOZ
(D02) Auto zero
statistics 0 – Do n ot a utomatic al ly reset Statistics reg i sters to zero .
1 – Automatically res et Stati stics regi st ers to zero aft er rea ding.
Can be set to 1 to cause the Statistics registers (see "Statistics
monitoring" on page 251) to be automatically reset to 0 after reading.
When se t to 0 , the S tat istics reg i st ers m u s t b e m an u all y re se t to 0 b y
writing a 0 value to the register.
RXEN
(D01) Rec eiver enable Must be set to 1 to enable the Ethernet receiver logic. The RXEN bit
should be set to 1 after the fields in the Station Address Filter register
(see "Transmit Random Number Generator (RNG)" on page 240)
have been configured. The Ethernet receiver can be disabled at any
time by setting the RXEN bit to 0.
Table 76: STL Configuration register bit definition
15 14 13 12 11 10 987
6543210
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset: 0
R/W
Addres s = FF80 0410
0
R/W
-- -- --
-- -- -- --
-- -- -- --
-- -- -- ----
RXEN ITXA
-- -- -- -- -- --
-- AUT OZ
0
R/W
-- ----
SRST TSTMD
0
R/W
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NET+50/20M Hardware Reference
STL Test register and bit definitions
There is one field in the STL Test register — CRCO: CRC output (
'
). When set
to 1, this field is used only for simulation of the STL module. This field must be set
to 0 for normal functional operation of the module.
Transmit Control registers
There are 10 Transmit Contr ol re gisters. Each register is 32-bits, and all bits are
initialized to 0 on reset, unless otherwise noted.
ITXA
(D00) Insert transmit
source address Can be set to 1 to forc e the MAC to automatical ly insert the Ethernet
source MAC address into the Ethernet transmit packet. The MAC
address information is provided by the data configured in the Station
Address register (see "Transmit Masked Random Number (MRNG)"
on page 240). When the ITXA bit is set to 0, the 7th through 12th data
bytes in the Ethernet packet are ignored and are replaced by the size
bytes found in the Station Address register (see "Station Address
register and bit definitions" on page 256).
Code
(Bit #) Definition of
code Description
Table 76: STL Configuration register bit definition
15 14 13 12 11 10 987
6543210
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Addres s = FF80 0414
-- -- ---- -- -- ---- -- -- ---- -- -- ----
CRCO
-- --
-- --
--
0
R/W
----
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Ethernet Controller Module
Inter-Packet Ga p (IPG) regi sters
The inter-packet gap (IPG) is the measurement between the last nibble (or bit in
ENDEC mode) of frame check sequence and the first nibble (or bit in ENDEC
mode) of the p reamb le for the next pack et.
For 100 Mbyte Ethernet, the IEEE 802.3u standard requires IPG to be a
minimum of 0.96 microseconds.
For 10 Mbyte Ethernet, the IEEE 802.3u standard requires IPG to be a
minimum of 9.6 microseconds.
In the Ethernet transmit block, there are three fields that can be used to finetune
the IPG:
IPGT. The IPGT field is in the Back-to-Back IPG Gap Timer register.
IPGR1 and IPGR2. These two fields are in the Non Back-to-Back Gap
Timer register.
Back-to-Back IPG Gap Timer register
The IPGT (
'
), or back-to-back transmit IPG, spaces back-to-back transmit
packet s. The Ether n et t ran smit st at e ma ch ine has an intrinsic dela y of four
Ethernet clocks between packets. With the IPGT field set to 0, the IPG will be a
minimum of four Ethernet clocks, or
X6
, when operating at 100BT.
The IEEE 802.3u standard re quir es an IPG value of
X6
.
The recommended value for IPGT in MII mode is
[
.
Operating in MII mode
The information and examples below pertain to operating in MII mode.
15 14 13 12 11 10 987
6543210
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Addres s = FF80 0440
-- -- ---- -- -- ---- -- -- ---- -- -- ----
IPGT
-- --
-- --
--
0
R/W
---- -- --
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NET+50/20M Hardware Reference
MII mode transmit clock information
Examples of IPGT configuration for 100BT operating in MII mode
[
, or
X6
, is recommended.
Examples of IPGT configuration for 10BT operating in MII mode
[
, or
X6
is recomm en ded.
Operati n g in ENDEC mode
Clock frequency Clock period Maximum bit rate
25 MHz 40 nsec 100 Mbit
2.5 MHz 400 nsec 10 Mbit
100 Mbit IPGT 802.3 IPG
0x00 0.16 uS
0x03 0.28 uS
0x07 0.44 uS
0x0B 0.60 uS
0x0F 0.76 uS
0x14 0.96 uS
0x1F 1.40 uS
10 Mbit IPGT 802.3 IPG
0x00 1.6 uS
0x03 2.8 uS
0x07 4.4 uS
0x0B 6.0 uS
0x0F 7.6 uS
0x14 9.6 uS
0x1F 14.0 uS
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Ethernet Controller Module
When op er a t i ng i n E NDE C mod e , t he IP GT val u e s are different from MII mo d e.
The ENDEC transmit clock is 10MHz rather than 25MHz, but there is still a 4-clock
intrinsic delay in the transmitter state machine.
Examples of IPGT configuration for 10BT operating in ENDEC mode
[&
or
X6
is recommended.
Non Back-to-Back IPG Gap Timer register
The IPGR1 and IPGR2 timers begin their interval timing at the same time.
IPGR1 (
'
), or non back-to -back IPG length part I, is the interval in which the
transmitter defers if carrier sense goes high. The interval is usually set to 2/3 of the
IPGR2 value. During the period of time after IPGR1 times out but before IPGR2
times out, the transmitter does not defer if it sees carrier sense. The transmitter will
cause a collision if it has a packet to send, resulting in activation of the random
back off fairness algorithm.
10 Mbit IPGT 802.3 IPG
0x07 1.1 uS
0x0F 1.9 uS
0x3F 6.7 uS
0x5C 9.6 uS
0x5F 9.9 uS
15 14 13 12 11 10 987
6543210
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Addres s = FF80 0444
-- -- ---- -- -- ---- -- -- ---- -- -- ----
IPGR1
0
R/W
-- IPGR2
0
R/W
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NET+50/20M Hardware Reference
IPGR2 (
'
), or non back-to-back IPG length part II, spaces non back-to-back
transmit packets. For non back-to-ba ck packets, the CRS input signal is sampled.
The CRS sampling time plus the Ethernet transmit state machine delay of three
Ethernet cloc ks betw een packets results in a total intrinsic delay of 7 Ethernet
clocks when calculating IPGR2.
With the IPGR2 field set to 0, the IPG is a minimum of seven Ethernet clocks, or
X6
, when operating at 100BT.
Operating in MII mode — IPGR1
The following examples pertain to operating in MII mode.
Examples of IPGR1 configuration for 100BT operatin g in MII mode
[
, or
X6
, is recommended.
100Mbit IPGR1 802.3 IPG
0x00 0.28 uS
0x06 0.52 uS
0x07 0.56 uS
0x08 0.60 uS
0x09 0.64 uS
0x1F 1.52 uS
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Ethernet Controller Module
Examples of IPGR1 configuration for 10BT operatin g in MII mode
[
, or
X6
, is recommended.
Opera ti ng in ENDEC mo de — IPGR1
When op er a t ing i n E NDE C mode, the IPGR1 value s are different from MII mo d e.
The ENDEC transmit clock is 10MHz rather than 25MHz, but there is still a 7-clock
intrinsic delay in the transmitter state machine.
Examples of IPGR1 configuration for 10BT operatin g in ENDEC mode
[
, or
X6
, is recommended.
Operating in MII mode — IPGR2
The IEEE 802.3u standard re quir e s an IPG value of
X6
. The recomm en d ed
value for IPGR2 when operating in MII mode is
[
.
10Mbit IPGR1 802.3 IPG
0x00 0.28 uS
0x06 0.52 uS
0x07 0.56 uS
0x08 0.60 uS
0x09 0.64 uS
0x1F 1.52 uS
100Mbit IPGR1 802.3 IPG
0x07 1.4 uS
0x0F 2.2 uS
0x2F 5.4 uS
0x39 6.4 uS
0x5F 9.9 uS
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NET+50/20M Hardware Reference
Examples of IPGR2 configuration for 100BT operatin g in MII mode
[
, or
X6
, is reco mm ended.
Examples of IPGR2 configuration for 10BT operating in MII Mode
[
, or
X6
, is recommended.
Opera ti ng in ENDEC mo de — IPGR2
When op er a t i ng i n E NDE C mod e , t he IP GR2 v al u e s are di fferent f rom MII mo de.
The ENDEC transmit clock is 10MHz rather than 25MHz, but there is still a 7-clock
Ethernet clock intrinsic delay in the transmitter state machine.
100Mbit IPGR2 802.3 IPG
0x00 0.28 uS
0x03 0.40 uS
0x07 0.56 uS
0x0B 0.72 uS
0x0F 0.88 uS
0x11 0.96 uS
0x1F 1.52 uS
10 Mbit IPGR2 802.3 IPG
0x00 2.8 uS
0x03 4.0 uS
0x07 5.6 uS
0x0B 7.2 uS
0x0F 8.8 uS
0x11 9.6 uS
0x1F 15.2 uS
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Ethernet Controller Module
Examples of IPGR2 configuration for 10BT operatin g in ENDEC mode
[
, or
X6
, is recommended.
10 Mbit IPGR2 802.3 IPG
0x07 1.4 uS
0x0F 2.2 uS
0x3F 6.9 uS
0x59 9.6 uS
0x5F 10.2 uS
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NET+50/20M Hardware Reference
Collision Window/Collision Retry register
Code
(Bit #) Definition of
code Description
LCOL
(D13:08) Late collision
window Defines the number of bytes that are within the nominal slot time, or
collision window, for properly configured networks. This value
defines the number of bytes after the start frame delimiter (
6)'
) that
allow a normal collision to occur. Any collisions after the time
defined by LCOL result in a late coll is io n e v en t.
The recommended value for LCOL is
[
(
G
), wh ich results i n a
bit-time window of 512 bits when considering the 8-byte preamble/
SFD.
RETRY
(D03:00) Maximum
number of retries
after a collision
Specifies the number of retransmission attempts allowed following a
collision, before aborting the packet due to excessive collisions. The
802.3u standard specifies the
DWWHPSW/LPLW
to be
[)
(
G
) and
is the recommended value for this field.
Table 77: Collision Window/Collision Retry register bit de finition
15 14 13 12 11 10 987
6543210
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Addres s = FF80 0448
-- -- ---- -- -- ---- -- -- ---- -- -- ----
LCOL
0
R/W
-- RETRY
0
R/W
-- -- -- ----
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Ethernet Controller Module
“Simulation” regi ste rs
The remaining Transmit Control registers are used only for transmitter module
simulation. For normal functional operation of the MA C transmitter, leave the bit
settings within the registers as set.
Transmit Packet Nibble Counter (PCNT)
'
Transmit Byte Counter register (TBCT)
'
15 14 13 12 11 10 987
6543210
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Addres s = FF80 0460
-- -- ---- -- -- ---- -- -- ---- -- -- ----
PNCT
0
R/W
15 14 13 12 11 10 987
6543210
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Addres s = FF80 0464
-- -- ---- -- -- ---- -- -- ---- -- -- ----
TBCT
0
R/W
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238 n n n n n n n
NET+50/20M Hardware Reference
Retransmit Byte Counter register (RETX)
'
Transmit Random Number Generator (RNG)
'
Transmit Masked Random Number (MRNG)
'
15 14 13 12 11 10 987
6543210
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Addres s = FF80 0468
-- -- ---- -- -- ---- -- -- ---- -- -- ----
RETX
0
R/W
-- -- --
-- -- -- --
-- -- ----
15 14 13 12 11 10 987
6543210
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Addres s = FF80 046C
-- -- ---- -- -- ---- -- -- ---- -- -- ----
RNG
0
R/W
-- -- --
-- -- --
15 14 13 12 11 10 987
6543210
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Addres s = FF80 0470
-- -- ---- -- -- ---- -- -- ---- -- -- ----
MRNG
0
R/W
-- -- --
-- -- --
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Ethernet Controller Module
Transmit Counter Decodes (ECTDC)
'
Test Operate Transmit Counters (TECTCL)
'
15 14 13 12 11 10 987
6543210
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Addres s = FF80 0474
-- -- ---- -- -- ---- -- -- ---- -- -- ----
ECTDC
0
W
15 14 13 12 11 10 987
6543210
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Addres s = FF80 0478
-- -- ---- -- -- ---- -- -- ---- -- -- ----
TECTCL
0
W
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Receive Control registers
240 n n n n n n n
NET+50/20M Hardware Reference
Receive Control registers
There are three Receive Con t rol regist e r s. Each r e gi ster is a 32 -b it reg ist er, and all
bits are initialized to 0 on reset.
The Receive Control registers are used only for simulation of the MAC receiver
module. For normal functional operation of the module, leave the bit settings
within the registers as set.
Receiv e Byte C ounter (R BCT)
''
Receive Counter Decodes (ECRDC)
'
15 14 13 12 11 10 987
6543210
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Addres s = FF80 0464
-- -- ---- -- -- ---- -- -- ---- -- -- ----
RBCT
0
R/W
-- --
15 14 13 12 11 10 987
6543210
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Addres s = FF80 0484
-- -- ---- -- -- ---- -- -- ---- -- -- ----
EDRDC
0
R
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Ethernet Controller Module
Test Oper ate Receive Count ers (RECTC L)
'
15 14 13 12 11 10 987
6543210
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Addres s = FF80 0488
-- -- ---- -- -- ---- -- -- ---- -- -- ----
RECT CL
0
W
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PCS Control registers
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NET+50/20M Hardware Reference
PCS Control registers
There are three Ph ysical Sublayer Control (PCS) registers. Each register is a 32-bit
register, and all bits are initialized to 0 on reset.
The PC S Co nt rol regi st er s are use d on l y for si mu l ati o n o f th e P CS module. For
normal functional operation of the PCS module, leave the bit settings within the
r eg i ste r s as set.
Link Fail Counter (LFCT)
'
10 MB Jabber Counter (JBCT)
'
15 14 13 12 11 10 987
6543210
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Addres s = FF80 04C0
-- -- ---- -- -- ---- -- -- ---- -- -- ----
LFCT
0
R/W
-- ----
15 14 13 12 11 10 987
6543210
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Addres s = FF80 0500
-- -- ---- -- -- ---- -- -- ---- -- -- ----
JBCT
0
R
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Ethernet Controller Module
10 MB Loss of Carrier Counter (DTLB)
'
15 14 13 12 11 10 987
6543210
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Addres s = FF80 0504
-- -- ---- -- -- ---- -- -- ---- -- -- ----
DT LB
0
W
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Ethernet MII interface signals
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NET+50/20M Hardware Reference
Ethernet MII interface signals
Table 78 defines and briefly describes the signals included in the MII interface. See
Chapter 3, "NET+50 Chip Package," for more information
Code Definition Description
MDC Management data
clock Provides the clock for the MDIO serial data channel. The MDC signal
is a NET+50 chip output. The maximum frequency is 2.5 MHz.
MDIO Management data
IO A bi-directional signal that provides a serial data channel between the
NET+50 chip and the external Ethernet PHY module.
TXCLK Transmit clock An input to the NET+50 chip from the external PHY module.
TXCLK provides the synchronous data clock for transmit data. The
transmit clock operates as follows:
At 25 MHz for 100 Mbit operation
At 2.5 MHz for 10 Mbit operation
At 10 MHz in ENDEC mode
TXD3
TXD2
TXD1
TXD0
Transmit data
signals Nibble bus used by the NET+50 chip to drive data to the external
Ethernet PHY. All transmit data signals are synchronized to TXCLK.
In ENDEC mode, only TXD0 is used for transmit data.
TXER Transm i t c o d i ng
error Output asser ted by the NET+50 when an error has occurre d in the
transmit data stream. When operating at 100 Mbps, the PHY responds
to this signal by sending ´LQYDOLGFRGHV\PEROVµ on the line.
TXEN Transmit enable Asserted when the chip drives valid data on the TXD outputs. This
signal is synchronized to TXCLK.
COL Transmit
collision Input signal asserted by the external Ethernet PHY when a collision
is detected. This input must remain high for the duration of the
collision.
CRS Receive carri er
sense Asserted by the external Ethernet PHY when the receive medium is
non-idle. During half-duplex operation, this can also occur when the
transmitter is active.
Table 78: MII interf ace signals
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Ethernet Controller Module
RXCLK Receive clock An input to the NET+50 chip from the external PHY module. The
receive clock provides the synchronous data clock for receive data,
and operates as follows:
At 25 MHz for 100 Mbit operation
At 2.5 MHz for 10 Mbit operation
At 10 MHz in ENDEC mode
The receive clock must remain active a minimum of 27 bit times after
the end of each received Ethernet frame.
RXD3
RXD2
RXD1
RXD0
Rece ive d ata
signals Nibble bus used by the NET+50 chip to input receive data from the
external Ethernet PHY. All rece ive data signals are synchronized to
RXCLK.
In ENDEC mode, only RXD0 is used for receive data.
RXER Receive error Input asserted by the external Ethernet PHY when the Ethernet PHY
encounters invalid symbols from the network. This signal must be
synchronous to RXCLK.
RXDV Rec eiv e data
valid Input asserted by the external Ethernet PHY when the Ethernet PHY
drives valid data on the RXD inputs. This signal must be synchronous
to RXCL K.
Code Definition Description
Table 78: MII interf ace signals
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NET+50/20M Hardware Reference
MII Control registers
There are five MI I Con t rol registers:
MII Command regist er
MII Address register
MII Write reg ister
MII Read r e g ister
MII Indica tor s r egi s ter
Each register is a 32-bit re gister. All bits are initialized to 0 on reset unless
othe r wi se noted.
MII Command register and bit definitions
The default value for both fields in this register is 0.
Code
(Bit #) Definition of
code Description
SCAN
(D01) Automatically
scan for read data When set to 1, the MII management module performs read cycles
continuously. This is useful for monitoring link fail, for example.
RSTAT
(D00) Single scan for
read data When set to 1, the MII management module performs a single read
cycle. The read data is returned in the MII Read Data register after the
BUSY bit in the MII Indicators register has returned to a value of 0.
Table 79: MII Comm and register b it definition
15 14 13 12 11 10 987654 32 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Addres s = FF80 0540
-- -- --
-- -- -- --
-- -- -- --
-- -- -- ----
SCAN
0
R/ W
RSTAT
0
R/ W
-- -- --
-- -- -- --
-- -- -- --
-- -- --
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Ethernet Controller Module
MII Address register and bit definitions
The default value for both fields in this register is 0.
MII Write Data register and bit definition
There is one field in th e MI I Write Data register — MWTD: MII write data
(
'
).
Code
(Bit #) Definition of
code Description
DADR
(D12:08) MII PHY device
address Represents the 5-bit PHY device address field for management
cycles. Up to 31 different PHY devices can be addressed; address 0 is
reserved.
RADR
(D04:00) MII PHY register
address This field represents the 5-bit PHY register address field for
management cycles. Up to 32 registers within a single PHY device
can be addressed.
Table 80: MII Addre ss register bit def inition
15 14 13 12 11 10 98765432 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Addres s = FF80 0544
-- -- --
-- -- -- --
-- -- -- --
-- -- -- ----
RADR
0
R/ W
DADR
0
R/ W
-- ---- -- ----
15 14 13 12 11 10 98765432 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Addres s = FF80 0548
-- -- --
-- -- -- --
-- -- -- --
-- -- -- ----
MWT D
0
R/ W
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MII Control registers
248 n n n n n n n
NET+50/20M Hardware Reference
When this register is written, an MII management write cycle is performed using
the 16-bit data defined in the PHY Address register by the pre-configured PHY
device and PHY register addresses. The write operation is completed when the
BUSY bit in the MII Indicators register returns to 0.
MII Read Data register and bit definition
There is o ne f iel d i n the MII Rea d Dat a regi st e r — MRDD: MII r ead data (
'
).
The MII Read Data register provides read data aft er an MII management read
cycle. An MII management read cycle is executed by loading the PHY Address
register, then setting the READ bit in the MII Command register to 1.
Read data ia available after the BUSY bit in the MII Indicators register returns to 0.
MII Indicators register and bit definitions
15 14 13 12 11 10 98765432 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Addres s = FF80 054C
-- -- --
-- -- -- --
-- -- -- --
-- -- -- ----
MRDD
0
R
15 14 13 12 11 10 987654 32 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Addres s = FF80 0550
-- -- --
-- -- -- --
-- -- -- --
-- -- -- ----
SCAN
0
R/W
BUSY
0
R/W
-- -- ---- -- -- ---- -- -- ---- -- --
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Ethernet Controller Module
Statistics mon itoring
The statistics block (STAT) serves two purposes:
The STAT block monitors the transmit and receive status vectors from
the MAC. The status vectors identify transmit and receive packets that
have encountered errors.
The EFE module uses the STAT block to record those events. Firmware
can read the statistics errors at any time. The firmware can also
configur e t he STAT block to au tomatica lly clear t he err or counte rs whe n
they are read, using the AUTOZ bit in the STL Configuration register
(see page 229).
Code
(Bit #) Definition of
code Description
SCAN
(D01) Automatically
scan for read data
in progress
When set to 1, indicates that continuous MII management scanning
read operations are in progress.
BUSY
(D00) MII interface
BUSY with read/
write operation
When set to 1, indicates that the MII management module is currently
performing an MII management read or write cycle. This bit returns
to 0 when the operation is complete.
Table 81: MII Ind icators register bit de finition
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Statistics monitoring
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NET+50/20M Hardware Reference
Error Statistics registers
The EFE module supports eight Error S tatistics re gisters. All re gisters use D15:D00
for the counter field, as shown in the CRC Error Counter register:
CRC Error Counter register
))
– RXCRC. Incremented each
time a receive frame is discarded because it was received with a CRC
error.
The packet is discarded automatically if the ERXBAD field in the
Ethernet Genera l Contr ol r egister is set t o 0. RXCRC incr ements for each
packet received with a bad CRC, however, no matter the value in
ERXBAD.
RXCRC is clear ed automati cally when re ad, if the AUTO Z bit in the STL
Configuration register is set to 1.
Alignment Error Cou nter register
))
– RXAEC. Incremented
each time a receive frame is discar ded because it was received with an
alignment (dribble bit) error.
The packet is discarded automatically if the ERXBAD field in the
Ethernet General Contr ol r egister is set to 0. RXAEC incr ements for e ach
packet received with an alignment condition, however, no matter the
value in ERXBA D.
RXAEC is clear ed automati cally when r ead, if the AUTOZ bi t in the STL
Configuration register is set to 1.
Code Error Count er register.
))
– RXCEC. Incremented each
time a receive frame is discarded because it was received with a coding
error. A coding err or occurs when the PHY asserts the RXER input to the
NET+50 MAC.
15 14 13 12 11 10 98765432 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Addres s = FF80 0580
-- -- --
-- -- -- --
-- -- -- --
-- -- -- ----
RXCRC
0
R
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Ethernet Controller Module
The packet is discarded automatically if the ERXBAD field in the
Ethernet Gene ral Control register is set to 0. RXCEC increments for each
packet received with a coding error, however, no matter the value in
ERXBAD.
RXCEC is clear ed automaticall y when read, if the AUTO Z bit in the STL
Configuration register is set to 1.
Long F r ame Counter
))&
– RXLFC. Incremented each time a
receive frame is discarded because it was received with a length
exceeding 1518 bytes.
The packet is discarded automatically if the ERXLNG field in the
Ethernet General Control register is set to 0. RXLFC increments for each
packet received with a length greater than 1518 bytes, however, no
matter the value in ERXLNG.
RXLFC is clear ed automa tically when read, if the AUTOZ bit in the STL
Configuration register is set to 1.
Short Frame Counter
))
– RXSFC. Incremented each time a
receive frame is discarded because it was received with less than 64
bytes.
The packet is discarded automatically if the ERXSHT field in the
Ethernet General Cont rol reg ist er is set to 0. RXSFC increments for each
packet received with a length less than 64 bytes, however, no matter the
value in ERXSH T.
RXSFC is cleared automati call y when read, if the AUT O Z bit in the STL
Configuration register is set to 1.
Late Collision Counter
))
– TXLCC. Increment ed ea ch time a
transmit frame is aborted because it receives a late collision. A late
collision is a collision that occurs after the timefram e defined in the
LCOL field of the Collision Window/Collision Retry register.
TXLCC is clear ed aut omatica lly when r ead, i f the AUT OZ bit in t he STL
Configuration register is set to 1.
Excessive (Late ) Deferral Counter
))
– TXLDC. Incremented
each time a transmit frame is aborted because of excessive deferral.
Excessive deferral occurs when carrier is detected on the Ethernet receive
mediu m for l on g er t ha n ex p ec t ed .
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TXLDC is c lear ed automati cally when r ead , if t he AUT OZ bit i n the STL
Configuration register is set to 1.
Maximum Collision Counter
))&
– TXMCR . Incr emented ea ch
time a packet transmission is aborted because it received too many
collisions. The maximum number of allowable collisions is defined by
the RETRY field in the Collision Window/Collisio n Retry register.
TXM CR is cle ared automatically when read, if the AUTOZ bit in the
STL Configuration register is set to 1.
Station Address registers/multicast hash table
The E t he rn et module uses three Sta t i on Add ress informat ion re g i st er s :
Station Ad dress Filter register. A 32-bit register that contains filter
controls. The bits in this register initialize to 0 during reset.
Station Address regis t er. The NET+50 chip supports a single station
address. The station address is used by the station address logic (SAL)
for address comparison of inbound receive packets.
The station address requires three 32-bit registers to hold the 48-bit
value. Each register contains 16 bits of the 48-bit total. The first register
(low address) stores bits 47:32, the second register stores bits 31:16, and
the third register stores bits 15:00.
Multicast hash table. The MAC receiver provides the SAL logic with a
6-bit CRC value that addresses the 64-bit multicast hash table. A packet
is accepted if the curr ent r eceive frame is a multica st frame an d the 6-bit
CRC addresse s a bit in the hash tabl e that i s set to 1. Otherwise, the
packet is rejected.
The 64-bit multicast hash table requires four 32-bit registers for storage.
The first register (lower addr ess) stor es the enables for t he lower 16 CRC
addresses. The other registers store the enables for the upper 48 CRC
addr esses. The CRC addr esses ar e stor ed ri ght to left i n ascending or d er.
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Ethernet Controller Module
Station Address Filter register and bit definitions
Code
(Bit #) Definition of
code Description
PRO
(D03) Enable
promiscuous
mode (receive all
packets)
When PRO is set to 1, the MAC enters promiscuous mode. When
operating in promiscuous mode, all packets are received without any
filtering.
PRM
(D02) Acce pt all
multicast packets When PRM is set to 1, the MAC receives all multica st Ethernet
packets without any filtering.
PRA
(D01) Acc ept multicas t
packets using
hash table
When PRA is set to 1, the MAC receives only those multicast
Ethernet packets that are selected by the multicast hash table. See
"Multicast hash table entries and bit definitions" on page 257 for
details.
BROAD
(D00) Acce pt all
broadcast packets W hen BROAD is set to 1, the MAC receives all broadcast Ethe rnet
packets without any filtering.
Table 82: Station Address FIlter register bit definition
15 14 13 12 11 10 987654
32 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Addres s = FF80 05C0
-- -- ---- -- -- ---- -- -- ---- -- -- ----
-- -- --
-- -- -- --
-- -- -- --
-- PRO PRM PRA BROAD
0
R/W 0
R/W 0
R/W 0
R/W
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Station Address register and bit d efinitions
The station address bytes are loaded into the Station Address r egisters in Little
Endian format.
Station Register 1: Address bits 47: 32
Station Register 2: Address bits 31: 16
Station Addr ess Register 3: Addr ess bits 15:00
15 14 13 12 11 10 987654
32 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Addres s = FF80 05C4
-- -- --
-- -- -- --
-- -- -- --
-- -- -- ----
SA1
0
R/W
15 14 13 12 11 10 987654
32 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
-- -- ---- -- -- ---- -- -- ---- -- -- ----
SA2
0
R/W
Address = FF80 05 C8
15 14 13 12 11 10 987654
32 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Addres s = FF80 05CC
-- -- ---- -- -- ---- -- -- ---- -- -- ----
SA3
0
R/W
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Ethernet Controller Module
Multicast hash table entries and bit definitions
The multicast address bytes are loaded into the Station Address re gisters in Little
Endian format.
Hash table entries: Address bits 15:00
Hash table entries: Address bits 31:16
Code Definition of Code Description
SA1 Station Address 1 Provides the most significant (upper) 16 bits of the 48-
bit station address value.
SA2 Station Address 2 Provides the middle significant (middle) 16 bits of the
48-bit station address value.
SA3 Station Address 3 Provides the least significant (lower) 16 bits if the 48-
bit station address value.
Table 83: Station Address register bit definition
15 14 13 12 11 10 987654
32 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Addr ess = FF8 0 05D0
-- -- ---- -- -- ---- -- -- ---- -- -- ----
HT1
0
R/W
15 14 13 12 11 10 987654
32 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Addres s = FF80 05D4
-- -- ---- -- -- ---- -- -- ---- -- -- ----
HT2
0
R/W
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Hash table entries: Address bits 47:32
Hash table entries: Address bits: 63:48
Code Definition of code Description
HT1 Hash table entries [15:0] Provides the least significant 16 bits of the
64-bit hash table.
HT2 Hash table entries [31:16] Provides the lower middle significant 16 bits of the 64-
bit hash table.
HT3 Hash table entries [47:32] Provides the upper middle significant 16 bits of the 64-
bit hash table.
HT4 Hash table entries [63:48] Provides the most significant 16 bits of the 64-bit hash
table.
Table 84: Multicast hash table bit definition
15 14 13 12 11 10 987654
32 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Addres s = FF80 05D8
-- -- --
-- -- -- --
-- -- -- --
-- -- -- ----
HT3
0
R/W
15 14 13 12 11 10 987654
32 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Addres s = FF80 05DC
-- -- ---- -- -- ---- -- -- ---- -- -- ----
HT4
0
R/W
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Ethernet Controller Module
Calculating hash table entries
The following C code describes how to calculate the hash table entries based on
6-byte Ethernet destination addresses.
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Ethernet Controller Module
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n n n n n n n 263
Serial Controller Module
CHAPTER 11
The NET+50 chip supports tw o independent universal asynchronous/
synchronous receiver/transmitter channels: serial channel A and serial channel B.
Each channel supports several modes, conditions, and formats.
Note:
The information in this chapter applies to both the NET+50 and
NET+20M chips, unless otherwise noted.
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Features
Each ser i a l ch an ne l s upp o r t s th ese featu res:
Independent programmable bit-rate generator
UART, HDLC, SPI mode s
High speed data transfer
–x1 Mode: 4Mbits/sec
–x16 Mode: 230400 bits/sec
Digital phase-locked loop (DPLL)
16-bit or 32-bit CRC-CCITT generation/checking
32-byte TX FIFO
32-byte RX FIFO
Programmable data format
–5 to 8 data bits
–Odd, even, or no parity
–1, 2 stop bits
Programmable channel modes
–Normal
–Loca l loopback
–Remote loopback
–Bit order
–Programmable flags (0-15)
Control signal support
–RTS, CTS, DTR, DSR, DCD, RI
–Maskable interrupt condit ions
–Receive break detection
–Receive framing error
–Receive parity error
–Receive overrun error
–Receive FIFO ready
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Serial Controller Module
–Receive FIFO half-full
–Receive buffer close
–Transmit FIFO empty
–Transmit FIFO half-empty
–Transmit buffer close
–CTS, DSR, DCD, RI state change detection
Clock/data encoding
–NRZ
–NRZB
–NRZI-M
–NRZI-S
–FM0
–FM1
–Manchester
–Dif ferenti al Manchest er
Multi-drop capable
Figure 31 show s the modu les an d feat ures that co mpri se th e se ri al por t .
Figure 31: Serial port block diagram
Bit rate
generator
Receive
state
machine
Transmit
state
machine
32 byte
FIFO
Config
module
Serial I/O pins
32 byte
FIFO
BBus
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Bit-rate generator
Each serial channel supports an independent programmable bit-rate generator.
The bit-rate generator runs both the transmitter and receiver of a given channel (no
split-speed support).
You can configure the bit-rate generator to use the external crystal, the external
clock input, or internal system timing as its timing reference. This allows for a
wider range of bit-rates. See "Serial Channel Bit-Rate registers" on page 308 for
more information.
Serial protocols
The serial port provides support for the following protocols:
UART (Universal Asynchronous Receiver Transmitter)
HDLC
SPI
UART mode
Many applications require a simple mechanism for sending information between
two p ieces of e quipmen t. The un iversal asynchr onous rec eiver tr ansmitt er (UAR T)
protocol is the de facto standard for simple serial communications.
The UA RT framing protocol format is:
Start bit: 0
Data: 5, 6, 7, or 8 bits
Parity (opt ional): Odd or even
Stop bit: 1 or mor e
Because the transmitter and receiver operate asynchronously, the transmit and
receive clocks between them do not need to be connected. Instead, the receiver
over-samples the receive data stream by a factor of 16. Because the start bit is
always a zero, the receiver can detect when real data is presen t on the line. (When
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Serial Controller Module
the UART is not transmitting data, it transmits a continuous stream of ones —
consid ered the idle condition. When data transmission begins again, the
transmitter sends the start bit and the receiver is enabled.)
During synch ronization , the receiver waits for the start bit. When it finds the high-
to-low transition, the receiver counts eight sample times and uses this point as the
bit-center for all remaining bits in the UART frame. Each bit-time is 16 clock ticks
apart.
The UART can be configured to perform the following functions:
Enable the transmitter using th e C TS handshakin g sig na l. In this mode,
the transmitter cannot start a new UART data frame unless CTS is active. If
CTS is dropped anywhere in the middle of a UART data frame, the current
character is completed but the next character is stalled.
Signal its receiver FIFO status using the RTS handshaking signal. When
the r ece ive FIFO has onl y four characte rs o f avai lable spa ce, the RTS signal is
deasserted. The RTS and CTS pairs can be used for hardware flow control.
Operate in synchronous timing mode. When using synchronous timing
mode, a clock is provided with each bit; an over-sampling technique is not
required. In this mode, transmit and receive clocks must be connected
between two end points.
HDLC mode
The NET+50 chip HDLC controller provides these key features:
Flag/abort/idle generation and detection
Programmable flags between frames (0-15)
Auto m atic zero bit-stuffing and deletion
16-bit or 32-bit CRC-CCITT generation and checking
Four address comparison registers (both 8- and 16-bit addressing modes)
with mask
Discarded frame counters (non-matching address and bad CRC)
Detection of frames that are too long
Detection of non-octet aligned frames
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Overrun/underrun detection
Important:
The NET+50 chip does not support HDLC DMA.
The HDLC protocol provides the data link layer for many WAN networking
models such as Frame Relay, ISDN, and SDLC. The HDLC data frame is
surrounded by a pair of flag s (01111110) and a 16- or 32-b it CR C-CCITT checksum
for error detection.
The HDLC framing structure is:
FLAG: 01111110
Address: 01111110
Control: 01111110
Information:Nx8 bits
&5& 16 or 32 bits
FLAG: 01111110
Bit-stuffing
The HDLC controller uses a zero insertion/deletion scheme (r eferre d to as bit-
stuffing) in the data between flags. When the transmitter encounters five
consecutive ones () in the data stream, it automatically inserts a zero. When
the receiver encounters five consecutive ones followed by a zero, the zero is
automatically removed. The bit-stuf fing mechanism ensures that a 7E value in the
data stream is not mistaken for a starting or ending flag.
Layer 2 frame
Since layer 2 frames can be transmitted over point-to-point links, br oadcast
networks, packet networks, or circuit switch networks, an address field is needed
to carry the fram e’s destination addr ess. The address field is typically 8 or 16 bits,
depending on the data link layer protocol. The SDLC and LAPB protocols use an
8-bit address, for example, and the LAPD protocol uses a 16-bit address field. The
NET+50 chip HDLC controller can detect four different 8-bit addresses and two
different 16-bit addresses. Individual bits can be masked in the comparison
function.
Note:
The 8-bit or 16-bit control field is used to define the frame type and
flow control mechanism. The use of this field is protocol-dependent.
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Serial Controller Module
The NET+5 0 chip HDLC controller offers no hardware support for
handling this field.
Layer 3 frame
Data is transmitted in the data field. The data field contains the layer three protocol
information.
Error detection
The 16-bit or 32-bit CRC field provides error detection. The CRC is calculated on
the entire frame, including the address and control fields. The CRC most
significant bit is transmitted first. For all other octets (address, control, data), the
least significant bit is transmitted first.
SPI Mode
The SPI (serial peripheral interface) contr oller pr ovides:
Full-dup lex, synchronous interface. The master interface operates in a
broadcast mode, activating the slave interface with the select (SEL*) signal.
The master interface can also be configured to address more than one slave
interface by driving GPIO bits (in GPIO mode) using firmware rather than
hardware.
Four-wire connection (TXD, RXD, CLK, SEL*). The transmitter and receiver
use the same clock, but different clock edges. The timing reference across a
single SPI domain is provided by the master’s bit rate generator.
Character-oriented dat a cha nn el. The protocol can provide simple parallel/
serial data conversion to stream serial data between memory and a
peripheral, as well as operating multi-drop serial connections.
Master and slave configurations. The SPI port simultaneously transmits
and receives the same number of bytes. The SPI can be configured as a
master or a slave:
–SPI master generates both the (SEL*) and the clock (CLK) signals.
–SPI slave receives the SEL* and CLK signals as inputs.
The transfer of information is controlled by a single clock signal and
qualified with an enable signal. The slave transfers or accepts data only
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when the SPI enable signal is active low in conjunction with the SPI
clock signal. This allows for multiple slaves to be individ ually
address ed in a multi-drop config uration .
FIFO management
Data flow between the SPI master/slave interfaces and memory occurs through
the FIFO blocks within the SER module. Each serial port pr ovides a 32-byte
transmit FIFO and a 32-byte receive FIFO. Both the transmit and receive FIFOs are
memory-ma pped to the pr oc es so r addr e ss spa ce.
The NET+50 SPI FIFO interface is implemented as follows:
When the master SPI port is transferring data:
The master SPI port controls the SPI clock signal. The master SPI port
changes its TX data on the high-to-low transition of the SPI clock.
The slave SPI port samples RX data on the low-to-high transition of the SPI
clock.
The master SPI port drives the SPI clock signal high during the idle points
between transmit bytes and transmit packets.
When the SPI (master or slave) is receiving information:
Receive data is moved into the receive FIFO when 4 bytes have been
accumulated.
The FIFO buffer is closed on the transition of the SEL* signal from low-to-
high, when the SPI transmitter is sending a message whose length is not an
integral number of 4 bytes.
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Serial Controller Module
Transmit FIFO interface
The processor can write either 1, 2, or 4 bytes at a time to the transmit FIFO. The
number of bytes written is controlled by the data size defined by the ARM
processor as shown in these examples:
Operating in Endian modes
Big E ndian mo de conf igurat ion. Transmits first the most significant bytes in
the wor d wr it ten to the FIF O. F or exampl e, t he l ong word
[
results
in the character
[
being transmitted first and
[
being transmitted last.
Litt l e Endian mode co n f ig ur ation. Transmits first the least significant bytes
in the word written to the FIFO. For example, the long word
[
results in the character
[
being transmitted first and
[
being
transmitte d last.
Processor interrupts vs. DMA
The transmit FIFO can be filled using processor interrupts or DMA.
When using processor interrupts, the processor can write one long word (4
bytes ) of dat a to the transmit FIFO when the TR DY bit i n Serial Channel
Status Register A is active high. If the THALF bit in Serial Channel Status
Register A is active high, the processor can write four long words (16 bytes)
of data to the transmit FIFO. To facilitate an interrupt when either the TRDY
or THALF status bits are active, the processor can set one or both of the
corr espondi ng int errupt e nables — ET XRDY, ETXH ALF — in Serial Channel
Control Register A. The appropriate interrupt enable bit — SER 1 TX or SER
2 TX — in the GEN Interrupt Enable register must also be set.
Terminology What’s being written Value
C Byte using a byte pointer
FKDU[IIG FKDUGDWD
C Two bytes using a short
pointer
VKRUW[IIG VKRUWGDWD
C Four bytes using a standard long
word pointer
LQW[IIG LQWGDWD
Assemb ler Byte STRB instru ct io n s
Assemb ler Hal f wo r d STRH inst ru ct io n s
Assembler Long word STR instructions
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NET+50/20M Hardware Reference
Note:
Software should check the TXEMP TY status bit rather than the
TXHALF status bit when filling the FIFO using BYTE or HALF
WORDS.
When using the DMA c ontr oll er, the processo r must inte rface wit h the DMA
channel registers and the DMA buffer descriptor block attached to DMA
channels 8 and 10. To facilitate the use of transmit DMA, the ETXDMA bit in
Serial Channel Control Register A must be set active high and the serial
transmitter interrupts should be disabl ed.
Receive FIFO interface
The receive FIFO presents up to 4 bytes of data at a time to the processor interface.
The number of valid bytes found in the next read of the FIFO is defined by the
information found in the RXFDB field in Status Register A. The Endian rules
described for the transmit FIFO also apply for the receive FIFO (see "Operating in
Endian modes" on page 271).
When reading from the receive FIFO, the processor must perform a long word
read operation. Each time a read cycle is performed, the receive FIFO advances to
the next long wor d entry. The processor cannot read individual bytes from the
same FIFO long word entry.
Processor interrupts vs. DMA
The receive FIFO can be emptied using pr ocessor interrupts or DMA. The definition
of a data buffer is different depending on whether you are in interrupt or DMA
mode.
In interru pt mode, the data buffer is one line of the FIFO; for example, 4 bytes
(characters).
In DMA mode, the data buffer is a complete buffer descriptor.
Using processor interrupts
When us ing pr oces sor inte rrupts , the pr oce ssor can r ead o ne long w ord (4 bytes) of
data t o th e rece i ve F I FO wh en the RRDY bit i n Se r i al Ch annel Sta t us Regist er A i s
active high. This long word may have 1, 2, 3, or 4 bytes of valid data within the
word. The number of valid bytes is determined by the bit encoding found in the
RXFDB field in Status Register A. The RXFDB field must be read before the FIFO
Data register is read.
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Serial Controller Module
The RBC (receive buffer closed) bit in Serial Channel Status Register A indicates
that a r eceive data buffer has been closed and receiver status can be read fr om
Serial Status Register A. Before additional data can be read from the FIFO, the RBC
bit must be acknowledged by writing a 1 to the same bit position in Serial Status
Register A.
This is the recommended process flow for the serial port receiver interrupt service
routine:
1Read Serial Channel Status Register A.
2If RBC is true, then:
aRecord the receiver buffer closed status (if desired).
bWrite a 1 to the RBC bit position in serial status A.
cRead Serial Channel Status Register A again.
3If RRDY is true, then:
aRead the data FIFO.
bUse the RXFDB field to pick out valid bytes.
To facilitate an interrupt when either the RRDY or RBC status bits are
active, th e pr ocessor must set one or both of the correspon ding interru pt
enables — ERXD RDY, ERXBC — in Serial Chan nel Control Register A.
The appropriate interrupt enable bit — SER 1 RX, SER 2 RX — in the
GEN module Interrupt Enable register must also be set.
Using DMA
When using the DM A controller, the processor must interface with the DMA
channel r egisters and the DMA buffer descriptor block attached to DMA channels
7 and 9. To facilitate the use of receive DMA, the ERXDMA bit in Serial Channel
Control Register A must be set active high and the serial receiver interrupts should
be disabled.
SPI master mode
SPI master mode controls the flow of data between memory in the master SPI
interface and an external SPI slave peripheral. The SPI master determines the
number s of byte s fo r tra nsf er.
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Information transfer is controlled by a single SPI clock signal and qualified by an
SPI enable signal. The clock signal is an output. The SPI enable signal must be
active low for data transfer to occur, regardless of the SPI clock sign al. SPI enable
allows for multiple slaves to be individually addressed in a multi-drop
configuration.
Configuration
The GEN module must be configured to allow the SPI interface signals from the
SER module to propagate through the GEN GPIO ports (A, B and C) to the outside
of the chip. The GEN module must be configured after the SPI interface has been
configured; otherwise, there can be adverse effects on the devices connected to the
SPI interface.
Table 85 shows how to configure the GEN module GPIO ports for the two SPI
channels.
Channel GPIO Port Configuration
A PORTA3 Special function input — SPI RXD
A PORTA4 Special function output — SPI clock
A PORTA7 Special function output — SPI TXD
A PORTC7 Special function output — SPI enable.
Use this if the hardware-generat ed SPI enable signal originat ing
inside the NET+50 is needed outside the chip.
A PORTC7 or any
other available
GPIO pins
GPIO output
Use this if the slave SEL* signals (part of the four-wire SPI protocol)
are going to be generated just by firmware.
B PORTB3 Special function input — SPI RXD
B PORTB4 Special function output — SPI clock
Table 85: SPI master m ode channel A/ B configuration
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Serial Controller Module
SER module master mode configuration
Important:
The MO D E f i eld i n Se r i al Ch annel Cont rol R eg i st e r B must be set t o
‘10’ before the CE field in Serial Channel Control Register A is set to 1.
Follow these steps to configure SPI master mode for operation:
1Reset the serial port by writing a 0 to Serial Channel Control Register A.
2Configure the Serial Channel Bit-Rate register as shown:
If the size of the transmit data block is a multiple of 4, the FIFO FULL
interrupt will be generated on the low-to-high transition of the receive
B PORTB7 Special function output — SPI TXD
B PORTC5 Special function output — SPI enable
Use this if the hardware-generat ed SPI enable signal originat ing
inside the NET+50 is needed outside the chip.
B PORTC5 or any
other available
GPIO pins
GPIO output
Use this if the slave SEL* signals (part of the four-wire SPI protocol)
are going to be generated just by firmware.
Note: The configuration of PORTC5 has no other effects on the
operation of the SPI module.
Bit Configuration
EBIT 1 for enable
TMODE 1 for x1 mode
RXSRC 0 for internal
TXSRC 0 for internal
CLKMUX User-defined
TXCINV 0 for normal
RXCINV 0 for normal
CLKINV According to the specification of the connected device
N User-defined
Channel GPIO Port Configuration
Table 85: SPI master m ode channel A/ B configuration
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clock for the last bit; otherwise, interrupt will be generated on the low-
to-high transition of the chip select signal.
3Configure Serial Channel Control Register B as shown:
4Configure Serial Channel Control Register A as shown:
See "SPI timing," beginning on page 459, for SPI master mode timing information.
SPI master transmitter
The SPI master transmitter operates as follows:
Changes its TXD output on the falling edge of the SPI clock signal while the
SPI enable signal is driven active low. The SPI slave devices should sample
data on the rising edge of the SPI clock signal.
Drives the SPI enabl e signal acti ve lo w fr om the fall i ng edge of the SPI clock
for the first bit of a byte being transmitted, and inactive high after the rising
edge of the SPI clock signal during the eighth bit of the byte currently
transmitted.
Drives the SPI enable signal active low to identify when data is being
transmitted.The SPI clock signal never transitions fr om low to high while the
internal SPI enable state is inactive high. A firmware-driven SEL* can still
function.
Transmits bytes whenever data is available in the TX FIFO. When the TX
FIFO becomes empty, the SPI enable signal is driven inactive high until more
data is availa ble in the TX FIFO. This must be consid er ed when choosing the
interface’s opera ting mo de. For exam ple, buffer un derruns can oc cur while
using a hardware-controlled SEL * in an interrupt-driven en vironment,
particul arly when operating at high bit rates.
Bit Configuration
MODE 10 for master mode
BITORDR User-defined
Bit Configuration
CE 1 for enabled
WLS 11 for 8-bit operation
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Serial Controller Module
When underruns occur, the SPI interface drives the SEL* line inactive
high. In such a case, i t is reco mmended that a firmwar e-dri ven enable is
used to force the SEL* active low.
SPI master receiver
The SPI master receiver operates as follows:
Samples the RXD input on the rising edge of the SPI clock signal while the
SPI enable signal is driven active low.
Receives one byte of inbou nd data fo r each byte of transmit data sent. T he
SPI master receiver cannot receive more data than is transmitted.
When the SPI master receiver collects four bytes, those four bytes are
written to the RX FIFO. Receive data is read by the CPU or DMA
controller from the other side of the FIFO. If the SPI master transmitter
always sends data in multiples of four bytes, the SPI master receiver
operates smoothly without any restrictions.
When the SPI master tr ansmit ter sends an od d number of bytes, t he SPI
master receiver needs to wait for the fourth byte before insertion into
the FIFO. This can result in stale data sitting in the SPI master receiver.
To commit these residual bytes to the RX FIFO, the buffer and/or
character GAP timers must be used. When either timer expires, any
residual RX data bytes are immediately written to the RX FIFO. Some
delay will occur in writing the final residual bytes; the d elay is
determined by the configuration of the buffer and character GAP
timers.
SPI slave mode
SPI slave mode su pport s the per iphe r al side of an SPI int erfa ce. The SPI master
controls the numbers of bytes for transfer. The SPI slave port simultaneously
transmits and receives the same number of bytes.
Information transfer is controlled by a single SPI clock signal and qualified by an
SPI enable signal. The clock signal is an input. The SPI enable signal must be active
low, in conjunction with the SPI clock signal, for data transfer to occur. The
hardware SEL* control must be used; the slave should not use a firmware-
controlled SEL* line.
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Configuration
The GEN module must be configured to allow the SPI interface signals from the
SER module to propagate through the GEN GPIO ports (A, B and C) to the outside
of the chip. The GEN module must be configured after the SPI interface has been
configured; otherwise, there can be adverse effects on the devices connected to the
SPI interface.
Table 86 shows how to configure the GEN GPIO ports for the two SPI channels.
SER module slave mode configuration
Important:
The MO D E f i eld i n Se r i al Ch annel Cont rol R eg i st e r B must be set t o
‘11’ before the CE field in Serial Channel Control Register A is set to 1.
Follow these steps to configure SPI slave mode for operation:
1Reset the serial port by writing a 0 to Serial Channel Control Register A.
2Configure the Serial Channel Bit-Rate register as shown:
Channel GPIO Port Configuration
A PORTA3 Special function input — SPI RXD
A PORTA4 Special function input — SPI clock
A PORTA7 Special function output — SPI TXD
A PORTC7 Special function input — SPI enable
B PORTB3 Special function input — SPI RXD
B PORTB4 Special function input — SPI clock
B PORTB7 Special function output — SPI TXD
B PORTC5 Special function input — SPI enable
Table 86: SPI slave mode channel A/ B configuration
Bit Configuration
EBIT 1 for enable
TMODE 1 for x1 mode
RXSRC 1 for external
TXSRC 1 for external
CLKMUX N/A (external timing source)
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Serial Controller Module
3Configure Serial Cha nnel Control Register B as follows:
4Configure Serial Cha nnel Control Register A as follows:
See "SPI timing," beginning on page 459, for SPI slave mode timing informa tion.
SPI Slave Transmitt er
The SP I s l ave trans m i t t er op e r at es as fol l o ws:
Has the first bit ready for transmission before the SPI enable signal is
activated by the SPI master.
Changes the TXD output to the next data bit for transmission on the rising
edge of SPI clock, while the SPI enable signal is active low.
Goes through a sampling of the SPI clock input. The output changes 3 to 4
internal system clock ticks from the rising edge of the SPI clock input. The
SPI master receiver does not sample the changing data until the next rising
edge of SPI clock.
Continue s to change TXD data bits on the rising edge of SPI clock until the
SPI enable signal is driven inactive high. While the SPI enable signal is
inactive high, the TXD output remains constant.
TXCINV 0 for normal
RXCINV 0 for normal
CLKINV According to the specification of the connected device
N N/A (external timing source)
Bit Configuration
MODE 11 for slave mode
BITORDER User-defined
Bit Configuration
CE 1 for enable
WLS 11 for 8-bit operation
Bit Configuration
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SPI Sl ave Receiver
The SPI slave receiver operates as follows:
Samples the RXD input on the rising edge of the SPI clock signal while the
SPI enable signal is driven active low. The SPI slave receiver goes through a
sampling of the SPI clock input, which means the input is sampled three to
four internal system clock ticks from the ris ing edge of the SPI clo ck input.
When the SPI slave receiver collects four bytes, those four bytes are written
to the RX FIFO. Receive data is read by the CPU or DMA controller from the
other side of the FIFO. If the SPI master transmitter always sends data in
multiples of fou r bytes, the SPI sla ve re ceiver operat es smoothly without any
restrictions.
When the master SPI tr ansmit ter sends a n od d number of bytes, t he SPI
slave receiver waits for t he fourth byte b efore insertion into the FIFO.
This can result in stale data sitting in the SPI slave receiver. To commit
these residual bytes to the RX FIFO, the buffer and/or character GAP
timers must be used. When either timer expires, any residual RX data
bytes are immediately written to the RX FIFO. Note that there is some
delay in the proc ess of writing the final residual byte s. The delay is
determined by the configuration of the buffer and character GAP
timers.
General purpose I/O configurations
TheGEN module provides the physical layer connections for NMSI (Non
Multiplexed Serial Interface) and SPI. NMSI is used for UART and HDLC
protocols.
PORTA provides NMSI and SPI for serial channel A.
PORTB provides NMSI and SPI for serial channel B.
Four PORTC signals are required to support NMSI and SPI.
Each GEN module interface signal can be enabled or disabled with firmware.
NMSI
NMSI requires a minimum of two signals (TXD and RXD) but each interface can be
configured to use up to 10 signals. Table 87 shows how the GEN module interface
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Serial Controller Module
signals ar e allocated when serial channels A and B are configured to operate in
NMSI mode.
SPI
The SP I mode support s a fo ur-wire int e r f a ce . Tabl e 88 shows how t he GEN
module interface signals are configur ed when serial channels A and B are
configured to operate in SPI slave mode:
GPIO port Assignment for NMSI
PORTA7 TXDA
PORTA6 DTRA*
PORTA5 RTSA*
PORTA4 RXCA/OUT1A
PORTA3 RXDA
PORTA2 DSRA*
PORTA1 CTSA*
PORTA0 DCDA*
PORTC7 TXCA/OUT2A
PORTC6 RIA*
PORTB7 TXDB
PORTB6 DTRB*
PORTB5 RTSB*
PORTB4 RXCB/OUT1B
PORTB3 RXDB
PORTB2 DSRB*
PORTB1 CTSB*
PORTB0 DCDB*
PORTC5 TXCB/OUT2B
PORTC4 RIB*
Table 87: PORTA/B/C assignments for NMSI mode
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Table 89 shows how the GEN module in ter fa ce sig nal s are conf igu red when serial
channels A an d B are con fi g ured t o op er a t e i n SP I master mode:
Figure 32 shows SPI mas ter an d slave /G P IO signal relatio ns hips.
Each entry reflects two GPIO pins and the related special function. For example,
the entry PORTA7/B7 Data Out means PORTA7 or PORTB7, depending on which
serial channel you are using (Channel A or Channel B, respectively). Data Out is
the transmit data output function.
GPIO port Assignment for SPI slave
PORTA7 TXDA
PORTA3 RXDA
PORTA4 SPICLKA-IN
PORTC7 SPISELA-IN
PORTB7 TXDB
PORTB3 RXDB
PORTB4 SPICLKB-IN
PORTC5 SPISELB-IN
Table 88: PORTA/B/C assignments for SPI slave mode
GPIO port Assignment for SPI master
PORTA7 TXDA
PORTA3 RXDA
PORTA4 SPICLKA-OUT
PORTC7 SPISELA-OUT
PORTB7 TXDB
PORTB3 RXDB
PORTB4 SPICLKB-OUT
PORTC5 SPISELB-OUT
Table 89: PORTA/B/C assignments for SPI master mode
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Serial Controller Module
Figure 32: SPI mode /GPIO signal relationships
Serial port performance
The serial ports have a finite per fo rmance limit on their ability to handle serial
protocols. The performance is limited by the speed of the SYSCLK operating the
NET+50 chip. The configure d speed for the internal PLL defines the SYSCLK rate:
P
ORT
A7 /B 7 Data Out
PORT
C7/C5 Enable Out
P
ORT
A4/B 4 Cl ock Out
P
ORT
A3/B 3 Data In
SPI-
Mast er GPIO Pins
P
ORT
A7 /B 7 Data Out
P
ORT
C7/C5 En able In
PORT A
4/B4 Clock In
P
ORT
A3/B 3 Dat a In
SPI-Sl
ave GPIO Pins
Serial Module
Serial Module
Operating mode Serial port maximum rate
UART (x 16) SYSCLK/64
UART (x1) SYSCLK/4
SPI SYSCLK/8
HDLC SYSCLK/10
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Configuration
The serial controller module has a block of configuration space that is mapped into
the SER module configuration space as shown:
Address Register
FFD0 0000 Channel 1 Control Register A
FFD0 0004 Channel 1 Control Register B
FFD0 0008 Channel 1 Status Register A
FFD0 000C Channel 1 Bit-Rate Register
FFD0 0010 Channel 1 FIFO Data Register
FFD0 0014 Channel 1 Receive Buffer Timer
FFD0 0018 Channel 1 Receive Character Timer
FFD0 001C Channel 1 Receive Match Register
FFD0 0020 Channel 1 Receive Match Mask Register
FFD0 0024 Channel 1 Control Register C
FFD0 0028 Channel 1 Status Register B
FFD0 002C Channel 1 Status Register C
FFD0 0030 Channel 1 FIFO Data Last Register
FFD0 0040 Channel 2 Control Register A
FFD0 0044 Channel 2 Control Register B
FFD0 0048 Channel 2 Status Register A
FFD0 004C Channel 2 Bit-Rate Register
FFD0 0050 Channel 2 FIFO Data Register
FFD0 0054 Channel 2 Receive Buffer Timer
FFD0 0058 Channel 2 Receive Character Timer
FFD0 005C Channel 2 Receive Match Register
FFD0 0060 Channel 2 Receive Match Mask Register
FFD0 0064 Channel 2 Control Register C
Table 90: Serial channel configuration registers
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Serial Controller Module
Serial controller register diagrams
Figure 33 through Figure 36 present each serial contr oller register, with every bit
contained in the register. Use these diagrams to gain an understanding of how the
serial controller registers work within the s erial controller module configuration.
Legend
Annotations in the lower right corner of bit-name boxes:
V
= Status bit
L
= Interrupt. This bit can cause an interrupt with the associated status bit.
K
= HDLC onl y
Port/sig nal refer e nces:
The port references are written as
3RUW;;Q
;
= The port; f or ex ample, PortA.
Q
= The spe ci f i c bi t num ber ; for exampl e, 7.
The bit num b er app l i es to bot h por t s in the entry ; fo r exa mp le,
3RUW$%
means
PortA7 and PortB7 bits.
The signal refer ences shown with the port refere nces are formatted similarly; for
example,
7;'$%
ref ers to
7;'$
and
7;'%
. Each signal “belongs” to its respective
por t , as s ho wn :
Entry:
3RUW$%7;'$%
Meaning:
3RUW$7;'$
and
3RUW%7;'%
The registers are explained in the sections following these diagrams.
FFD0 0068 Channel 2 Status Register B
FFD0 006C Channel 2 Status Register C
FFD0 0070 Channel 2 FIFO Data Last Register
Address Register
Table 90: Serial channel configuration registers
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Figure 33: Serial Controller registers — 1
MODE
UART
HDLC
SPI Master
SPI Slave
CE
POR T A7/B7 T XDA-B
POR T A6/B6 DTR A-B
PORTA5/B5 RTSA-B
POR T C7 /C5 T XCA-B
POR T A0/B 0 DCDA -B
PORTA/B4 RXCA-B
PORTA3/B3 RXDA-B
POR T A2/B2 DSR A-B
PORTC6 /C4 RI A-B
POR T A1/B1 CTSA-B
GPIO Pin s
CT S T X
RTSRX
RTS
DT R
From RX FIFO
DSR
CT S
DCD
RI
ERX CTS
ERX DSR
ERX DCD
ERX RI
CT S I
DCDI
DSRI
RII
To/From Clock Gen
To/From Clock Gen
TXD
RXD
To T ransmitter
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Serial Controller Module
Figure 34: Serial controller registers — 2
ERFE
ERX PE
ERX BC
ERX DRDY
ERX HALF
ERXORUN
RCGT
RBGT
Receiv e Data Matching
RDM1
RDM4
RDM2
RDM3
MAT CH1
MAT CH2
MAT CH3
MAT CH4
RDMB 1
RDMB 2
RDMB 3
RDMB 4
RMMB1
RMMB2
RMMB3
RMMB4
Status
Mat ch Data Mask
BI TORDR
BGAP
CGAP
RBC
RHALF
RRDY
ROVER
ERXDMA
32-Byte
Receive
FIFO
FIFO Reg
DMA CH -7 -9
Shift Reg
BBUS
Charact er Gap Timer
RXD
s
RDEC
s
i
s
s
s
s
i
i
i
i
RPE
RFE
s
s
s
Enable
RXFDB s
ERX BRK i
RBRK s
RFULL s
i
s
s
s
BTRUN
CT RUN
BT
CT
Buff er Gap Timer
MAXLEN h
MAM2
MAM1
h
h
CHK CRC*
RX CRC
RX BCAM1
RX BCAM2
RX BCAM3
RX BCAM4
s
s
s
s
RX BCN
RXBCC
RX BCO
RX BCA
s
s
s
s
RX BCL
RX BCAB
s
s
FLAGS
IDLE s
EFDF
CRCDF
s
s
IEEF
IECE
i
i
HDLC Recei ve S tatus
h
h
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Figure 35: Serial controller registers — 3
RL
ETXRDY
ETXHAL F
ETXBC
ETXDMA
32-Byte
Transmit
FIFO
TRDY
THALF
TBC
DMA CH -8 -1 0
Shift Reg
TEMPTY
BBU S
TXD
i
i
RXD
LL RXD
STICKP
WL S
BRK
STOP
PE
EPS
Data Format
BITORDR
TENC
TPP
TEND
TPL
FIFO Data L AS T Reg h
FIFO Reg
TXBCC
TXBCU
h s
h s
NFLAG
CRC
FLAG*/IDL
TXCRC*
HDLC
From CTSTX
s
s
s
s
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Serial Controller Module
Figure 36: Serial controller registers — 4
Bit Rate Generator
T
XEXT
To PortC7-5
EBIT
TMODE
TXSRC
RX CI NV
CLKINV
RXSRC
From PortA-B4
From PortC7-5
RXEXT
To PortA-B4
N
CLKMUX
From PortA-B4
From PortC7-5
Fxtal
Fs ysclk
TX and RX CLK
RDCR
TDCR
TXCINV
RICS TICS
From RX signal
TX Clock RX Clock
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Serial Channel registers
Serial channel registers provide the basic setup for each channel. There are fiv e
serial channel registers:
Serial Channel Cont ro l Register A. All control bits are active high unless an
asterisk (*) appears in the signal name; in this case, they ar e active low. All
control bits are set to their respective inactive state on reset.
Serial Channel Control Register B. All control bits are active high unless an
asterisk (*) appears in the signal name; in this case, they ar e active low. All
control bits are set to their respective inactive state on reset.
Serial Ch annel Status Register A. All status bits are active high unless an
asterisk (*) appears in the signal name; in this case, the status bits are active
low.
The Receive Status bits (D31:16) are stuffed into the status field in the
DMA buf f er d escri pt or when DMA op era ti ons are enabled a nd a buffer
is closed. The upper 8 bits of this register (D31:24) can be cleared by
writing a 1 to the respective bit position (used when interrupt- driven).
The upper 8 bits ar e automat icall y updated whenever a r eceive buf fer is
closed.
The receive interrupt pending bits (D15:0) are cleared by writing a 1 to
the respective bit position.
Serial Channel Bit-Rate registers. Th e serial channel bit-rate registers are
32-bit registers used to configure the bit-rate for each serial channel.
The serial channel can be configured to operate using an internal or
external timing reference. When configured for internal timing, the
timing referenc e i s provided by t he b it- rat e g enera tor. When configured
for external timing, the timing reference is provided by PORTA/B/C
signals.
Serial Ch annel FIFO Registers. The Serial Channel FIFO d ata registe rs are
32-bit registers used to manually interface with the serial controller FIFOs
instead of using DMA support.
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Serial Controller Module
Serial Channel Control Register A
Important:
The NET+50 chip does not support HDLC DMA.
Code
(Bit #) Definition of
code Description
CE
(D31) Channel enable Enables/disables the serial channel. Setting the CE field to 0 resets the
port and the data FIFOs. Setting the CE to 1 enables serial channel
operation. The CE field cannot be set until the MODE field is
configured in Serial Channel Control Register B.
BRK
(D30) Send break Forces a break condition in UART mode. While BRK is set to 1, the
UART transmitter outputs a logic 0 or a space condition, on the TXD
output signal.
STICKP
(D29) Stick parity Can be used to forc e the UAR T parity fiel d to a certain state, as
defined by the EPS field, instead of a parity bit being calculated
against the data. STICKP applies only when the PE field is also set to
1.
Sett ing th e S T IC KP field to 1 fo r ce s transm ission of the static parity
value.
EPS
(D28) Even parity select 0 – Odd Parity
1 – Even Parity
Determines whether the serial channel uses odd or even parity when
calculating the parity bit in UART mode. When the STICKP field is
set, the EPS field defines the static state for the parity bit.
PE
(D27) Parity enable W hen the PE field is set, parity is enabled for the UAR T transm itter
and receiver. The transmitter gener ates proper pari ty. The rec eiver
checks for proper parity. If the receiver encounters a bad parity bit,
the RPE field is set in Serial Channel Status Register A.
Table 91: Serial Channel Cont rol Register A bit definition
CE B RK S T OP WLS CT S T X RT S RXSTICKP EPS PE RL LL OUT2 OUT1 DTR RTS
ERXBRT ERFE ERXHALF ERXBC ERXRI
ERXPE ERXORUN ERXDRDY ERXDSR ERXCTS ETRXDY ETXHALF ETXBCETXDMA
0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W
0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset: ERXDMA ERXDCD
0
R/W 0
R/W 0
R/W 0
R/W 0
R/W
Addr ess = FFD0 0000 / 40
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STOP
(D26) Number of stop
bits 0 – 1 stop bit
1 – 2 stop bits
Determines the number of stop bits in each UART transmitter.
WLS
(D25:24) Data word length
select 00 – 5 bits
01 – 6 bits
10 – 7 bits
11 – 8 bits
Determines the number of data bits in each UART data word.
CTSTX
(D23) Enabl e th e
transmitter with
active CTS
Supports hardware handshaking. When CTSTX is set, the transmitter
operates only when the external CT S signal i s in th e active st ate. A n
external device can use CTS to temporarily stall data transmission.
RTSRX
(D22) Enable active
RTS (only when
RX FIFO has
space)
Supports hardware handshaking. When RTSRX is set, the RTS
output provides the receiver FIFO almost-full condition. When the
receiver FIFO backs up, the RTS signal is dropped. The RTS output
stalls an external transmitter from delivering data.
RL
(D21) Remote loopback Provides a remote loopback feature. When the RL field is set to 1, the
TXD transmit output is c onnected to the R XD receive i nput. The RL
field immediately echoes receive data back as transmit data.
Primarily used as a test vehicle for external data equipment.
LL
(D20) Local loopback Provides an internal local loopback feature. When the LL field is set
to 1, it connects the serial channel receiver directly to the seri al
channel transmitter.
Primarily used as a test vehicle for the serial channel driver fi rmware.
OUT1/OUT2
(D19:18) General purpose
output 1/General
purpose output 2
The OUT1 and OUT2 fields provide extra miscellaneous serial
channel control signal outputs. The OUT1 and OUT2 signals can be
routed through PORTA/B/C pins using PORTA/B/C special function
modes.
DTR
(D17) Data ter min a l
ready active Controls the state of the external data terminal re ady signal.
Setting DTR to 1 causes the DTR output to go active.
Setting DTR to 0 causes the DTR output to go inactive
RTS
(D16) Request-to-send
active Controls the state of the external request-to-send signal.
Setting RTS to 1 causes the RTS output to go active.
Setting RTS to 0 causes the RTS output to go inactive
Code
(Bit #) Definition of
code Description
Table 91: Serial Channel Cont rol Register A bit definition
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Serial Controller Module
This table describes each interrupt enable bit for a receiver interrupt condition.
Each bit is read/write:
IE (D15:00) Interr upt enable The interrupt enable fields are used to enable an interrupt when the
respective status bit is set in Seri al Channel Status Register A.
Setting the IE field to 1 enables the interrupt.
Setting the IE field to 0 disables the interrupt.
Bits D15:D04 set up a receiver interrupt condition (see
Table 92).
Bits D04:D00 set up a transmitter interrupt condition (see
Table 93).
Bit # Bit name Interrupt enable description
D15 ERXB RT Receive break
D14 ERF E Receive framing error
D13 ERXP E Rece ive pari ty error
D12 ERXOR UN Receive overrun
D11 ER XDR DY Receive register ready
D10 ER XHA LF Receive FIFO half -f ull
D09 ERXB C Receive buffer closed
D08 ERXDMA UART and SPI modes only.
Enables receive DMA requests (use to pause
receiver).
Enables the receive r to interact with a DMA
channel. When configured to operate in DMA
mode, the DMA controller empties the receive
data FIFO and delivers the data to memory.
D07 ER XDC D Change in DCD int err upt enable
D06 ERXRI Chan ge in RI in t e rr up t e n ab le
D05 ERXDSR Change in DSR interrupt enable
Table 92: Interrupt enable bit definition - receiver
Code
(Bit #) Definition of
code Description
Table 91: Serial Channel Cont rol Register A bit definition
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This table describes each interrupt enable bit for a transmitter inter rupt condition.
Each bit is read/write:
Serial Channel Control Register B
Bit # Bit name Description
D04 ERXCTS Change in CTS interrupt enable
D03 ETXRDY Transmit register empt y
D02 ETXHALF Transmit FIFO half-empty
D01 ERXBC Transmit buffer closed
D00 ETXDMA UART and SPI modes only.
Enables transmit DMA r equests (use to pause
transmitter)
Enables the transmitter to interact with a DMA
channel. When configured to operate in DMA
mode, the DMA controll er lo a ds the transmit
data FIFO from memory.
Table 93: Interrupt enable bit definition - transmitter
RDM1 RDM2 RCGTRDM3 RDM4 RBGT MODE BITORDR MAM1 MAM2
RDECTENC TPL TEND TPP
0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W
0
R/W 0
R/W 0
R/W 0
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset: 0
R/W 0
R/W
Address = FFD0 0004 / 44
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Serial Controller Module
Code
(Bit #) Definition of
code Description
RDM1/2/3/4
(D31/D30/
D29/D28)
Enable receive
data match
1/2/3/4
When the serial channel is configured to operate in UART
mode, the RDM bits enabl e the receive data match comparators.
A receive data match comparison detection can be used to close
the current receive buf fer descriptor. The last byte in the current
receive data buf fer contains the match character. Each of these
bits enables the respective byte in the Receive Match regist er.
When the serial channel is configured to operate in HDLC
mode, the RDM bits enable the address match comparators.
The first character (or two characters) in the HDL C fr ame is
compared to the byte values found in the Receive Match
register. A match enables the HDLC receive packet to be
received. By setting all RDM bits to the 0 state, the HDLC
receiver effectively receives al l HDL C frames , regardl ess of an
address match. The address match comparators can be
configured as four 8-bit address values or two 16-bit address
values, using the MAM1 and MAM2 field settings
RBGT
(D27) Ena ble rece ive
buffer gap timer Enables the receive buffer gap timer. When the RBGT field is set to
1, the BGAP field in Seria l Channel Status Register A is set when the
timeout value defined in the Receive Buffer Gap T imer register has
expired. The RBGT field determines the maximum allowed time
from when the first byte is placed into the receive data buffer and
when the receive data buffer is closed.
RCGT
(D26) Ena ble rece ive
character gap
timer
Enables the receive character gap timer. When the RCGT field is set
to 1, the CGAP field in Serial Channel Status Register A is set when
the timeout value defined in the Receive Character Gap Timer
register has expired. The RCGT field determines the maximum
allowed time fr om when th e last byte i s placed int o t he recei ver data
buffer and when the receive data buffer is closed.
MODE
(D21:20) SCC mode 00 – UART Mode
01 – HDLC Mode
10 – SPI Master Mode
11 – SPI Slave Mode
Configures the serial channel to operate in UART, HDLC, or SPI
modes. The MODE field must be established before the CE bit is set
to 1 in Serial Channel Control Register A.
Table 94: Serial Channel Cont rol Register B bit definition
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BITORDR
(D19) Bit ordering 0 – Normal; Tr ansmit/ Receive LSB ( leas t significant bits) fi rst
1 – Reverse; Transmi t/Recei ve MSB (most significa nt bits) fi rs t
Controls the order in which bits are transmitted and received in the
Serial Shift regist er. The BI TO RDR field applies to all modes
(UART, HDLC , and SPI ).
When the BIT ORDR f ield is set to 0, the bits are processed LSB
first, MSB last.
When the BITORDR field is set to 1, the bits are processed
MSB fi rst, LSB last.
In HDLC mode, the processing of the CRC bit field is an
exception. The HDLC CRC bits are al ways proces sed MSB
first, LSB last.
MAM1/
MAM2
(D18/D17)
Match address
mode 1/Match
address mode 2
Used to combine two data bytes in the Receive Match register to form
a single 16-bit HDLC address match value.
Setting the MAM1 field to 1 causes RDMB1 and RDMB2 in the
Receive Match register to be combined and form a single 16-bit
address match value.
Setting the MAM2 field to 1 causes RDMB3 and RDMB4 in the
Receive Match register to be combined and form a single 16-bit
address match value.
MAM1:
0 – Match1/Match2 each 8-bit address
1 – Match1/Match2 combined for 16-bit address
MAM2:
0 – Match3/Match4 each 8-bit address
1 – Match3/Match4 combined for 16-bit address
Code
(Bit #) Definition of
code Description
Table 94: Serial Channel Cont rol Register B bit definition
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Serial Controller Module
TENC/
RDEC
(D11:09/
D08:06)
Transmit/receive
data encoding The NET+50 can be programmed to encode and decode the serial
data stream using one of the methods listed next. The transmit and
receive coding methods can be selected independently in the
transmitter and receiver .
NRZ (000) — Default. A 1 is represented by a high level for the
duration of the entire bit-time; a 0 is represented by a low level
during the entire bit-time.
NRZB (001) — NRZB is NRZ inverted; that is, a 1 is represented
by a low level during the entire bit-time and a 0 is represented by a
high level during the bit-time.
NRZI-Mark (010) — A 1 is represented by a transition at the
beginning of the bit-time; the level that appears during the previous
cell is reversed. A 0 is represented by the absence of a transition at
the beginning of the bit cell.
NRZI-Space (011) — A 0 is represented by a transition at the
beginning of the bit-time; the level that appears during the previous
cell is reversed. A 1 is represented by the absence of a transition at
the beginning of the bit cell.
FM0 (100) — A 0 is represented by a transition at the beginning of
the bit-time followed by another transition at the middle of the bit-
time. A 1 is represented by a transition only at the beginning of the
bit-time.
FM1 (101) — A 1 is represented by a transition at the beginning of
the bit-time followed by another transition at the middle of the bit-
time. A 0 is represented by a transition only at the beginning of the
bit-time.
Manchester (110) — A 1 is represented by a high level during the
first half of the bit-time and a low level during the second half of the
bit-time. A 0 is represented by a low level during the first half of t he
bit cell and a high level during the second half of the bit cell.
Differential Manchester (1 11) — A 1 is represented by a transition
at the center of the bit-time, with the opposite polarity from the
transition of the bit-time at the center of the preceding bit-time. A 0
is represented by a transition at the bit-time with the same polarity
as the transition at the center of the preceding bit-time. In both
cases, transitions at the beginning of the bit-time set up the level
required to make the correct center transition.
See Figure 37, "Data coding example," on page 300 for an example
of the transmit and receive coding methods.
Code
(Bit #) Definition of
code Description
Table 94: Serial Channel Cont rol Register B bit definition
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TPL
(D04:03) Transmit
preamble length 00 – No preamble
01 – 8 bits
10 – 16 bits
11 – 32 bits
Determines the length of the preamble pattern configured by the TPP
field.
TEND
(D02) Transmitter frame
ending 0 – TXD encoded only for valid data driven high otherwise
1 – TXD always encoded, even during IDLE bit times
Controls whether the TXD line should idle in a high state or in an
encoded ones state (which can be either high or low).
When TEND is 0, the TXD signal will be encoded during the
preamble, flag, data, and ending flag conditions; the TXD pin
idles in the high state when no data is available to transmit.
When TEND is 1, the TXD signal will always be encoded, even
while the idle 1s are being transmitted.
TPP
(D01:00) Transmit
preamble pattern 00 – All zeros
01 – Repeating 10s
10 – Repeating 01s
11 – All ones
Determines the bit pattern that prec edes the start of each transmit
frame (provided the TPL field is non-zero). The preamble pattern is
sent before the firs t flag character for the HDLC frame. The preamble
is transmitted only if the serial port is configured for HDLC mode and
to send 1s in the IDLE mode, and TPL is not set to 00. The preamble
is not sent if the port is configured to Idle Flags. The preamble is
typically transmitted to a receiving station that uses a DPLL for clock
recovery. The receiving DPLL uses the regular pattern of the
preamble to help it lock onto the received signal in a short, predictable
time period.
Code
(Bit #) Definition of
code Description
Table 94: Serial Channel Cont rol Register B bit definition
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Serial Controller Module
Figure 37: Data cod ing example
Serial Channel Status Register A
MATCH1 MATCH2 CGAPMATCH3 MATCH4 BGAP RXFDB DCD RI DSR CTS
RBRK RFE RHALF RBC RXRI
RPE ROVER RXRDY RXDSR TXCTS TRDY THALF TXBC TXEMPTY
0
R0
R0
R0
R0
R0
R0
R0
R0
R0
R0
R
0
R/C 0
R/C 0
R/C 0
R/C 0
R/C 0
R/C 0
R/C 0
R0
R0
R/C 0
R
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset: RFULL RXDCD
0
R0
R0
R/C 0
R0
R/C
Address = FFD0 0008 / 48
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Code
(Bit #) Definition of
code Description
MATCH1/
2/3/4 (D31/
D30/D29/
D28)
Character
Match1/Match2/
Match3/Match4
Set as a result of a MATCH character being configured in the Receive
Match register in conjunction with the enable receive data match bit
being set in Serial Channel Control Register B. The MATCH bit
indicates that a data match was found in the receive data stream and
the current receive data buffer has been closed. The last character in
the receive data buffer contains the actual MATCH character found.
When not using DMA, the MATCH bits are valid when the RBC bit
in this reg i st e r is set.
For UART and SPI modes only: When the receiver is configured
for DMA operation, the MATCH status bits are automatically written
to the DMA receive buffer descriptor’s status field.
BGAP
(D27) Buffer GAP t im er Set whenever the enable receive buffer gap timer is set in Serial
Channel Control Register B and the timeout value defined in the
Receive Buffer Gap Timer register has expired. This bit indicates that
the maximum allowed time has occurred since the first byte was
placed into the receive data buffer, closing that buffer.
When not using DMA, the BGAP bit is valid only when the RBC bit
in this reg i st e r is set.
For UART and SPI mode only: When the receiver is configured for
DMA operation, the BGAP status bit is automatically written to the
DMA receive buffer descriptor’s status field.
CGAP
(D26) Charact er GAP
timer S et whenever the enable re ceive characte r gap timer is set in Seri al
Channel Control Register B and the timeout value defined in the
Receive Charact er Gap Timer re gister ha s expired. This bit indicates
that the maximum allowed time has occur red since the previous byte
was placed into the receive data buffer, closing the receive data
buffer.
When not using DMA, the CGAP bit is valid only when the RBC bit
in this reg i st e r is set.
For UART and SPI mode only: When the receiver is configured for
DMA operation, the CGAP status bit is automatically written to the
DMA receive buffer descriptor’s status field.
Table 95: Serial Channel Status Regi ster A bit d efinition
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Serial Controller Module
RXFDB
(D21:20) Receive FIFO
data available 00 – Full-word
01 – One byte
10 – Half-word
11 – Three bytes (LENDIAN determi nes whi ch three)
Identifies the number of valid bytes contained in the next long word
to be read from the Serial Channel FIFO data register. The next read
of the FIFO can contain one, two, three, or four valid bytes of data.
This field must be read before the FIFO is read to determin e which
bytes of the 4-byte long word contain valid data. Normal Endian byte
ordering rules apply to the Serial Channel FIFO data register.
DCD
(D19) Current data
carrier detect state 0 – Inactiv e
1 – Active
Identifies the current st ate of the EIA data carrier detect signal.
RI
(D18) Curren t ring
indicator state 0 – Inacti ve
1 – Active
Identifies the current state of the EIA ring indicator signal.
DSR
(D17) Current data set
ready state 0 – Inactive
1 – Active
Identifies the current state of the EIA data set ready signal.
CTS
(D16) Current clear-to-
send state 0 – Inactiv e
1 – Active
Identifies the curre nt state of the EIA clear-t o-send signa l.
RXBRK
(D15) Rec eive break
interrupt pending Indicates that a UART receive break condition has been detected.
When set, the RXBRK field remains set until acknowledged. The
field is acknowledged by writing a 1 to the same bit position in Serial
Channel Status Register A.
The RXBRK status condition can be programmed to generate an
interrupt by setting ERXBRT (D15) in Serial Channel Control
Register A.
RXFE (D14) Receive framing
error interrupt
pending
Indicates that a receive framing error condition has been detected.
When set, the RXFE field remains set until acknowledged. The field
is acknowledged by writing a 1 to the same bit position in Serial
Channel Status Register A.
The RXFE status condition can be programmed to generate an
interrupt by setting ERFE (D14) in Serial Channel Control Register
A.
Code
(Bit #) Definition of
code Description
Table 95: Serial Channel Status Regi ster A bit d efinition
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RXPE (D13) Receive parity
error interrupt
pending
Indicates that a receive parity error condition has been detected.
When set, the RXPE field remains set until acknowledged. The field
is acknowledged by writing a 1 to the same bit position in Serial
Channel Status Register A.
The RXPE status condition can be programmed to generate an
interrupt by setting ERXPE (D13) in Serial Channel Control Register
A.
RXORUN
(D12) Receive overrun
interrupt pending Indicates that a receive overrun error condition has been detect ed. An
overrun condition indicates that the FIFO was full while data needed
to be written by t he recei ver. When t he FIFO is full, an y new recei ve
data will be discarded; the contents of the FIFO prior to the overrun
condition will remain the same.
When set, the RXORUN field remains set until acknowledged. The
field is acknowledged by writing a 1 to the same bit position in Serial
Channel Status Register A.
The RXORUN status condition can be programmed to generate an
interrupt by setting ERXORUN (D12) in Serial Channel Control
Register A.
RXRDY
(D11) Rec eive regi ster
ready interrupt
pending
Indicates data is available to be read from the FIFO data register.
Before rea d ing th e FIF O d ata register, the RXFDB field i n Seri al
Channel Status Register A must be read to determine how many
active bytes are available during the next read of the FIFO data
register. The RXRDY field is typically used only in interrupt-driven
applications; it is not used for DMA operation. The RRDY status
condition can be programmed to generate an interrupt by setting
ERXDRDY (D11) in Serial Channel Control Register A.
The RXRDY bit is never active whi le the RXBC bit is active. The
RXBC bit must be acknowledged to activate the RXRDY bit.
For UART and SPI mode only: When the receiver is configured t o
operate in DMA mode, the interlock between RXBC and RXRDY is
handled automatically in hardware.
RXHALF
(D10) Receive FIFO
half-full int errupt
pending
Indicates that the receive data FIFO contains at least 16 bytes. The
RXHALF field is typically used only in interrupt-driven applications;
it is not used for DMA operation. The RXHALF status condition can
be programmed to generate an interrupt by setting ERXHALF (D10)
in Seri a l C ha n nel Contro l Register A.
Code
(Bit #) Definition of
code Description
Table 95: Serial Channel Status Regi ster A bit d efinition
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Serial Controller Module
RXBC
(D09) Receive buffer
closed interrupt
pending
Indicates a receive buffer closed condition. When set, the RXBC field
remains set until acknowledged. This field is acknowledged by
writing a 1 to the same bit position in Serial Channel Status Register
A. When configured to operate in DMA mode, RXBC is
automatically acknowledged by hardware (UART and SPI modes
only). The RXBC status condition can be programmed to generate an
interrupt by setting the appropriate IE bit in Serial Channel Control
Register A.
For UART and SPI applications
The RXBC field indicates that bits D31:26 in Serial Channel Status
Register A are valid. Whi le the RXBC field is active, the RR DY bi t
is not active. T o activate RX RDY (to read t he data FIFO), the RXBC
bit must be acknowledged. This interlock between RXBC and
RXRDY is defined to allow the firmware driver to read status bits
D31:26 in Serial Channel Status Register A. When operating in DMA
mode, the D31:26 status bits are auto maticall y written to th e re ceive
DMA buffer descriptor and the interlock between RXBC and
RXRDY is handled automatically in hardwa re.
For HDLC appl ication s
The RXBC field indicates that bits D25:16 in (HDLC) Status Register
B are valid. While the RXBC field is active, the RXRDY bit is not
active. To activate RXRDY (to read the data FIFO), the RBC bit must
be acknowledged. This interlock between RXBC and RXRDY is
defined to allow the firmware driver to read the status bits D25:D16
in Status Register B.
RXFULL
(D08) Rec eive FIFO full Indi cates that the recei ve data FIFO is currently full.
RXDCD
(D07) Change in DCD
interrupt pending Indicates a state change in the EIA data carrier detect signal. When
set, the RXDCD field remains set until acknowledged. The field is
acknowledged by writing a 1 to the same bit position in Serial
Channel Status Register A. The RXDCD status condition can be
programmed to generate an interrupt by setting ERXDCD (D07) in
Serial Channel Control Register A.
RXDSR
(D05) Change in DSR
interrupt pending Indicates a state change in the EIA data set ready signal. When set,
the DSRI field remains set until acknowledged. The field is
acknowledged by writing a 1 to the same bit position in Serial
Channel Status Register A. The RXDSR status condition can be
programmed to generate an interrupt by setting ERXDSR (D05) in
Serial Channel Control Register A.
Code
(Bit #) Definition of
code Description
Table 95: Serial Channel Status Regi ster A bit d efinition
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TXCTS
(D04) Chan ge in CT S
interrupt pending Indicates a state change in the EIA clear-to-send signal. When set, the
TXCTS field remains set until acknowledged. The field is
acknowledged by writing a 1 to the same bit position in Serial
Channel Status Register A. The TXCTS status condition can be
programmed to generate an interrupt by setting ERXCTS (D04) in
Serial Channel Control Register A.
TXRDY
(D03) Transmi t register
empty interrupt
pending
Indicates data can be written to the FIFO data register. The TXRDY
field is typically used only in interrupt-driven applicati ons; it is no t
used for DMA operation. The TXRDY status condition can be
programmed to generate an interrupt by setting ETXRDY (D03) in
Serial Channel Control Register A.
The TXRDY bit is never active while the TXBC bit is active. The
TXBC bit must be acknowledged to activate the TXRDY bit.
For UART and SPI mode only: When the transmitter is configured
to operate in DMA mode, the interlock between TXBC and TXRDY
is handled automatically in hardware.
TXHALF
(D02) Transmit FIFO
half-empty
interrupt pending
Indicates that the transmit data FIFO contains room for at least 16
bytes. The TXHALF field is typically used only in interrupt-driven
applications; it is not used for DMA operation. The TXHALF status
condition can be programmed to generate an interrupt by setting
ETXHALF (D02) in Serial Channel Control Register A.
Note: Software should check the TXEMPTY status bit rather
than the TXHALF status bit when filling the FIFO using
BYTE or HALF WORDS.
Code
(Bit #) Definition of
code Description
Table 95: Serial Channel Status Regi ster A bit d efinition
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Serial Controller Module
Serial Channel Bit-Rate registers
The se ri a l ch an ne l ca n be configu red to op er a t e i n eit h er X1 mod e (sy nc hrono us)
or X16 mode (asynchr onous). When using the internal bit-rate generator, the
frequency must be properly configured to match the mode being used.
TXBC
(D01) Transmit buffer
closed interrupt
pending
Indicates a transmit buffer closed condition. When set, the TXBC
field remains set until acknowledged. The field is acknowledged by
writing a 1 to the same bit position in Serial Channel Status Register
A. When the transmitter is configured to run in DMA mode, the
TXBC bit is automatically acknowledged by hardware (for UART
and SPI modes only). The TXBC status condition can be programmed
to generate an interrupt by setting ERXBC (D01) in Serial Channel
Control Register A.
For UART and SPI applications
The TXBC field is set when the last character in the transmit FIFO has
been shifted out of the shift re g ister and th e FIF O i s cu rre ntly e m pty .
While th e TBC field is active, th e TXRDY bit is n ot active. To activate
TXRDY (to write to th e d a ta F IFO), the TXBC bit must be
acknow ledge d. Whe n operat ing in DMA mode , the interl ock between
TXBC and TXRDY is handled auto matica lly in hardwar e.
For HDLC appl ication s
The TXBC field indicates that bits D15:14 in (HDLC) Status Register
B are valid. While the TXBC field is active, the TXRDY bit is not
active. To activate TXR DY (to wri te to the data FIF O) , the TXBC
must be acknowledged. This interlock between TXBC and TXRDY
is defined to allow the firmware driver to read the status bits D15:14
in Status Register B.
TXEMPTY
(D00) Transmit FIFO
empty Indicates that the transmit data FIFO is currently empty. TXEMPTY
simply reports the status of the FIFO; it does not indicate that the
character currently in the Transmit Shift register has been transmitted.
The TXBC bit must be used for the “all-sent” condition.
Note: Software should check the TXEMPTY status bit rather
than the TXHALF status bit when filling the FIFO using
BYTE or HALF WORDS.
Code
(Bit #) Definition of
code Description
Table 95: Serial Channel Status Regi ster A bit d efinition
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When the transmitter or receiver are configur ed to use an external timing source
(TXSRC or RXSRC set to 1), the serial channel is automatically configured to
operate in X1 mode. The serial channel clock is provided directly from the
PORTA/B/C interface’s OU T1/OUT2 inputs. T he TXSRC and RXSRC bits, when
set, override any configuration setting for the POR T A4, PORTB4, and POR TC7 and
POR TC5 pins in the GEN module. Setting TXSRC to 1 overrides any setting of the
TXEXT bit (D26) in the Serial Channel Bit-Rate registers.
Figure 38 shows the relationship between CLK, TXD, and RXD. TXD is driven
active from the falling edge of the CLK signal. The RXD input is sampled using the
rising edge of the CLK signal.
Figure 38: Serial channe l X1 timing
Serial Channel Bit-Rate register
CLK
TXD
RXD
EBIT TMODE TXEXTRXSRC TXSRC RXEXT CLKINV RDCR
TICS RICS
0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W
0
R/W 0
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Address = FF D0 000C / FFD0 00 4C
N r egi ster
TDCRCLKMUX T X CINV RX CINV
0
R/W 0
R/W 0
R/W 0
R/W
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Serial Controller Module
Code
(Bit #) Definition of
code Description
EBIT
(D31) Bit-rate generator
enable Enables or disables the internal bit-rate generator. A 1 in this field
allows the bit-rate generator to operate.
TMODE
(D30) Timing mode 0 – X16 Mode (asynchronous UART timing)
1 – X1 Mode (synchronous timing)
Configures the serial channel to operate in X1 mode or X16 mode.
When the TMODE field is set to 1, additional timing configuration is
provided by the TDCR (D20:19) and RDCR (17:16) fields.
RXSRC
(D29) Rec eive clock
source 0 – Internal
1 – External (input via PORTA4/B4)
Controls the source of the receiver cl ock. The receiver clock can be
provided by an internal source, as determined by the value in the
RICS (D12) field, or by an input on PORTA4/B4.
TXSRC
(D28) Transmit clock
source 0 – Internal
1 – External (input via PORTC5/C7)
Controls the source of the transmitter clock. The transmitter clock can
be provided by an internal source, as determined by the value in the
TICS (D14) field, or by an input on PORTC5/ C7.
RXEXT
(D27) Dr ive receive
clock external 0 – Disable
1 – Enable; drive RXCLK out of PORTA4/B4
Enables the receiver clock to be driven on the PO RTA4/ B4 pin. The
PORTA4/B4 pin must be configured as special function output.
TXEXT
(D26) Dr ive tr an smit
clock external 0 – Disable
1 – Enable; drive TXCLK out of PORTC5/C7
Enables the transmitter clock to be driven on the PORTC5/C7 pin.
The PORTC5/C7 pin must be configured as special function output.
Table 96: Serial Channel Bi t-Rate register bit def inition
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NET+50/20M Hardware Reference
CLKMUX
(D25:24) BRG input clock 00 – Input clock defined by FXTAL
01 – Input clock defined by FSYSCLK
10 – Input clock defined by input on PORTA4/B4
11 – Input clock defined by input on PORTC5/C7
Controls the bit-rate generator clock source. The bit-rate generator
can be configured to use one of four clock sources: the external
crystal oscillator, the internal SYSCLK output, an input signal on the
PORTA4/B4 pin, or an input signal on the PORTC5/C7 pin. The
PORTA4/B4 or PORTC5/C7 pin must be configured as special
function input.
TXCINV
(D23) Transmit clock
invert 0 – Normal; TXD driven on falling edge of TX clock
1 – Inverted; TXD driven on rising edge of TX clock
Controls the relationship between transmit clock and transmit data.
When TXCINV is set to 0, transmit data changes relative to the high-
to-low transition of the transmit clock. When TXCINV is set to 1,
transmit data changes relative to the low-to-high transition of the
transmit clock.
RXCINV
(D22) Rec eive clock
invert 0 – Normal; RXD sampled on rising edge of RX clock
1 – Inverted; RXD sampled on falling edge of RX clock
Controls the relationship between receive clock and receive data.
When RXCINV is set to 0, the receive data input is sampled at
the low-to-high transition of the receive clock.
When RXCINV is set to 1, the receive data input is sampled at
the high-to-low transition of the receive clock.
CLKINV
(D21) Clock invert 0 - Initial value of the clock signal is low
1 - Initial value of the clock signal is high
Code
(Bit #) Definition of
code Description
Table 96: Serial Channel Bi t-Rate register bit def inition
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Serial Controller Module
TDCR/
RDCR
(D20:19/
D17:16)
Transmit/receive
divide clock rate 00 – 1x clock mode (only NRZ or NRZI allowed)
01 – 8x clock mode
10 – 16x clock mode
11 – 32x clock mode
Determine the divide ratio for the transmitt er and receiver cl ocks.
If DPLL is not used and you are not using UART mode,
select a value of 1x.
If DPLL is not used and you are using UAR T, select 8x, 16x,
or 32x (16x is recommended). In most applications, the TDCR
and RDCR configurations should match.
When the DP LL is used , the select ion of TDCR /RDCR is a
function of the transmitter encoding. The NRZ and NRZI modes
can use the 1x configuration; all other encoding must use the 8x,
16x, or 32x configuration mode. The 8x configuration provides
the highest possible data rate; the 32x mode provides the highest
possible resolution.
The TM ODE bi t ( D 3 0) in th e Bit-Ra te re gister is ma in t ain e d fo r
NET+50 family backward compatibility. When setting the TDCR or
RDCR registers to a non-zero value, the TMODE bit must be set to 1.
When the TMODE, TCDR, and RDC R fields are all set to 0, the port
defaults to 16x mode of operation.
TICS
(D14) Transmit internal
cl ock sou rce 0 – BRG
1 – DPLL
When t h e TXS RC field is set to zer o, the tra nsm i tter operates usi n g
an internal clock. There are two sources for inter nal clocks: the bit-
rate generator (BRG) and the receiver digital phase lock loop
(DPLL). The BRG uses a divider mechanism for clock generation.
The DPLL is used to extract the clock from the incoming receive data
stream . Whe n T ICS is set to 0, the transmitter uses the BR G o u tp ut
for this clock. When TICS is set to 1, the transmitter uses the extracted
clock provided by the DPLL.
Code
(Bit #) Definition of
code Description
Table 96: Serial Channel Bi t-Rate register bit def inition
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NET+50/20M Hardware Reference
Table 97 shows bit rates generated by the bit-rate generator using an 18.432 MHz
crystal and a system PLL multiplier of 9 (SYS_CLK = 44.2368 MHz). The following
equati ons were used to calculate thes e rates:
X1 mode:
)%5* );7$/>1@
SPI master uses this mode.
X16 mode:
)%5* );7$/>1@
RS232 uses this mode.
RICS
(D12) Receiver internal
cl ock sou rce 0 – BRG
1 – DPLL
When the RXSRC field is set to zero, the receiver operates using an
internal clock. There are two sources for internal clocks: the bit-rate
generator (BRG ) and the recei ver digit al phase lock loop (DPLL ).
The BRG uses a divider mechanism for clock generation. The DPLL
is used to extract the clock from the incoming receive data stream.
When RICS is set to 0, the receiver uses the BRG output for this
clock. When RICS is set to 1, the receiver uses the extracted clock
provided by the DPLL.
N Register
(D10:00) The effective frequency of the BRG is defined by these equations:
FBRG = FXTAL / [2 * 16 * (N + 1)]
Using a CLKMUX setting of 00
FBRG = FSYSCLK / [2 * (N + 1)]
Using a CLKMUX setting of 01
FBRG = FOUT1 / [2 * (N + 1)]
Using a CLKMUX setting of 10
FBRG = FOUT2 / [2 * (N + 1)]
Using a CLKMUX setting of 11
The maximum value for FOUT1 and FOUT2 is FSYSCLK/ 4.
See Table 97 on page 313 for sample bit rates.
Code
(Bit #) Definition of
code Description
Table 96: Serial Channel Bi t-Rate register bit def inition
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Serial Controller Module
:
The following shows how X1 and X16 mode values were calculated for a bit rate of
9600:
);7$/ FU\VWDO 0+] 0+]
For X1 mode:
1RU
1 RU
1 RU
1
N register
Bit-rate CLKMUX X1 mode X16 mode
75 00 n/a 1535
150 00 n/a 767
300 00 n/a 383
600 00 n/a 191
1200 00 1535 95
2400 00 767 47
4800 00 383 23
7200 00 255 15
9600 00 191 11
14400 00 127 7
19200 00 95 5
28800 00 63 3
38400 00 47 2
57600 00 31 1
115200 00 15 0
230400 01 95 5
Table 97: Bit-rate e xamples
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Receive Gap Timer registers
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NET+50/20M Hardware Reference
For X16 mode:
1RU
1 RU
1 RU
1
Serial Channel FIFO registers
Writing to the Serial Channel FIFO register loads the transmit FIFO. This register
can be written only when the transmit data register ready bit (TXRDY) is set in
Serial Channel Status Register A. Writing to the Serial Channel FIFO regis t er
automatically clears the TXRDY bit.
Reading from this register empties the receive FIFO. Data is available whenever
the RXRDY bit is set in Serial Channel Status Register A. The Serial Channel Status
register identifies how many bytes are available to be read (RXFDB field). Reading
the FIFO register automatically clears the RXRDY bit in the Serial Channel Status
register.
Receive Gap Timer registers
The SER mo dul e use s two “gap timer” registers to close out serial data buffers:
Receive Buffer Timer register. A 32-bit register; all bits are set to 0 on reset.
The receive buffer gap timer closes out a receive serial data buffer. This
timer is config ured to pr ovide an interval i n the ra nge of 100 us to 2.3 S.
DATA
0
R/W
0
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Address = FFD0 0010 / 50
DAT A
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Serial Controller Module
The timer is reset when the first character is received in a new buffer.
New characters are received while the timer operates. When the timer
reaches its programmed threshold, the receive data buffer is closed.
–If the serial channel is configured to operate in DMA mode, the DMA
channel is signaled to close the buf fer and start a new buf fer (UAR T and
SPI modes only.)
–If the serial channel is configured to operate in interrupt mode, the
expi ration of the timer causes an interrupt to be genera ted.
The Receive Buffer Timer register operates using the external crystal
clock (wit h a divide -by-5 pr esca ler) and a 9-bit pr escaler wit hin the SER
module. The register is configured with a 15-bit programmable counter.
The effective buffer timer value is defined by the following equation:
7,0(287 >%7@);7$/
Receive Character Timer register. A 32-bit register; all bits are set to 0 on
reset.
The receive character gap timer closes out a receive serial data buffer
due to a gap between characters. This timer is configured to provide an
interval in the range of 100us to 145ms. The timer is reset whenever a
character is received. When the timer reaches its programmed
threshold, the receive data buffer is closed:
–If the serial channel is configured to operate in DMA mode, the DMA
channel is signaled to close the buf fer and start a new buf fer (UAR T and
SPI modes only).
–If the serial channel is configured to operate in interrupt mode, the
expi ration of the timer causes an interrupt to be genera ted.
The Receiv e Charact er Timer regist er opera tes using the exte rnal crysta l
clock (wit h a divide -by-5 pr esca ler) and a 9-bit pr escaler wit hin the SER
module. The register is configured with a 10-bit programmable counter.
The effective buffer timer value is defined by the following equation:
7,0(287 >&7@);7$/
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NET+50/20M Hardware Reference
Receive Buffer Timer register and bit definitions
HDLC mode
When a serial channel is configured to operate in HDLC mode, the Re ceive Buffer
Timer regi st e r provides the H DLC maxi m um fra me leng t h val ue —
0$;/(1
.
Code
(Bit #) Definition of
code Description
TRUN
(D31) Enable timer to
run Set TRUN to 1 to allow the receive buffer gap timer to operate.
BT
(D14:00) BT timer The required value for the receive buffer gap timer is a function of the
channel bit-rate and the maximum receive buffer size. Th e
recommended approach is to set the buffer gap timer to a value that is
slightly larger than the amount of time required to fill the maximum
buffer size using the channel bit-rate.
The following equation can be used to define the recommended
buffer gap timer value:
%75(&200(1'('
>0$;B5;B%8)B6,=();7$/
%LW5DWH@
If the resulting value does not produce a value that fits within the
range for B T, reconsider the size se lected for MAX_RX _BUF_SIZE.
Table 98: Rece ive Buffer Timer reg ister bit definiti on
TRUN
0
R/W
0
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Address = FFD0 0014 / 54
BT
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Serial Controller Module
Receive C haracter Timer register and bit defin ition s
0
R/W
0
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Address = FFD0 0014 / 54
MAXLEN
Code
(Bit #) Definition of
code Description
TRUN
(D31) Enable timer to
run Set TRUN to 1 to allow the receive character gap timer to operate.
CT
(D09:00) CT Value The required value for the receive character timer is a function of the
channel bit-rate. The recommended approach is to set the character
timer to be a value that is 10 times the character period for the channel
bit-rate.
The following equation can be used to define the recommended
character timer value:
&75(&200(1'('
>);7$/%LW5DWH@
Table 99: Receive Character Timer register bit definition
TRUN
0
R/W
0
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Address = FFD0 0018 / 58
CT
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Receive Match registers
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NET+50/20M Hardware Reference
Receive Match registers
The SER module uses two Receive Match registers:
Receive Match register. Can be configured for either UART or HDLC:
–When configured for UART. Provides the data bytes that the receiver
uses to compare against the incoming receive data stream. If a match is
found and the appropriate match enable bit is set in Serial Channel
Contr ol Regist er B , the current receive data buffer is closed by the ser ia l
channel.
–When configured for HDLC. Provides the data bytes that the receiver
uses to compare against the incoming HDLC address (first and second
bytes of the HDLC data frame). The address comparison function is
enabled using the appropriate match enable settings in Serial Channel
Control Register B. If the address comparison function is enabled and a
match occurs, the HDLC data packet is accepted. If the address
comparison function is disabled, all HDLC packets are accepted. The
address match comparators can be configured as four 8-bit address
values o r two 16-bit a dd ress v alu es usi n g the MAM1 an d MAM2 bi ts in
Serial Channel Control Register B.
Receive Match MASK register . Can mask in divi du al bi ts with in t he R ecei ve
Match register, for both UART and HDLC configurations. This register
masks those bits in the Receive Match data register that should not be
included in the match comparison.
Receive Match register and bit definitions
RDMB1
0
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Address = FF D0 001C/ 5C
RDMB3
RDMB2
RDMB4
0
R/W
0
R/W
0
R/W
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Serial Controller Module
Receive Match MASK register and bit definitions
To mask a bit in the match comparison function, place a 1 in the same bit position
within this register.
Code (Bit #) Definition of code
RDMB1 (D31:24) Receive data match byte 1
RDMB2 (D23:16) Receive data match byte 2
RDMB3 (D15:08) Receive data match byte 3
RDMB4 (D07:00) Receive data match byte 4
Table 100: Rece ive Matc h register bi t definition
Code (Bit #) Definition of code
RMMB1 (D31:24) Receive mask match byte 1
RMMB2 (D23:16) Receive mask match byte 2
RMMB3 (D15:08) Receive mask match byte 3
RMMB4 (D07:00) Receive mask match byte 4
Table 101: Rece ive Matc h MASK register bi t definition
RMMB1
0
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Address = FFD0 0020 / 60
RMMB3
RMMB2
RMMB4
0
R/W
0
R/W
0
R/W
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Control Register C (HDLC)
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Control Register C (HDLC)
Control Register C provides the configuration bits required when the serial
channel is configured to operate in HDLC mode.
Reminder:
DMA is not supported in HDLC mode.
Code
(Bit #) Definition
of code Description
NFLAG
(D31:28) Number of
flags between
frames
(0-15)
0 – Shared flag between frames
1-15– Additional flags
Controls the minimum number of flags to be inserted between back-to-
back HDLC frames. Sett ing this field to 0 allows a single shared fl ag
between two successive HDLC frames. Additional flags are always
inserted between HDLC frames when there is no data ready to send
(conditioned by the setting of the FLAG*/IDL field).
CRC
(D23:22) CRC Mode 00 – NO CRC
01 – Reserved
10 – 16-bit CCITT CRC-16
11 – 32-bit CCITT CRC-32
Identifies the type of CRC encoding used in the HDLC frames.
RXCRC
(D21) Rec eiv e CR C 0 – Do not include CRC in recei ve data buffer
1 – Place receive CRC in receive data buffer
Controls whether the HDL C CR C fiel d is placed i nto the rec eive data
FIFO. The HDLC CRC field is required to be examined by firmware
only, for either debugging purposes or encapsulation protocols. Setting
the RXCRC fi eld to 1 causes the HDLC CRC fie ld to be inserted into
the receive FIFO.
Table 102: Control Reg ister C (HDLC ) bit definition
NFLAG
0
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset
:
Reset
:
Addres s = FFD0 0024 / 64
CRC CHKCRC*
RXCRC
0
R/W
0
R/W
TXCRC* FLAG*/IDL
0
R/W
0
R/W 0
R/W
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Serial Controller Module
Status Register B (HDLC)
Stat u s R egi st e r B provi des the stat us bits r equir ed wh en the seri al ch a nn el i s
configured to operate in HDLC mode.
The receive buffer closed (RXBC) status bits are valid only when the RXBC bit is set
in Serial Channel Status Regis t er A. The receive buffer closed status bits must be
r ead before the RXBC bit is acknowledged. The RXBC bit must be acknowledged
before subsequent receive frames can be read from the r eceive FIFO.
The transmit buffer closed (TXBC) status bits are valid only when the TXBC bit is
set in Serial Channel Status Register A. The transmit buffer closed status bits must
be read before the TXBC bit is acknowledged.
CHKCRC*
(D20) Check the
receive CR C 0 – Discard bad receive frames wi th i ncorrect CRC
1 – Allow bad receive frames to be accepted
Controls whether the HDL C CR C fiel d is checked by the receive r for
errors. When CHKCR C* is set to 0, the HDLC rece iver checks the
HDLC CRC field and tags the HDLC data packet as good or bad. When
CHKCRC* is set to 1, the HDLC receiver does not check the HDLC
frame and marks all HDLC frames as good.
TXCRC*
(D17) Transmit
CRC 0 – Send calculated CRC before closing flag
1 – Do not send calculated CRC before closing
Controls whether the transmitter inserts the HDLC CRC field at the e nd
of an HDLC frame. When TX CRC * is set to 0, the HDLC transm itter
always insert s the HDL C CR C fiel d at the end of the HDL C fr ame.
FLAG*/IDL
(D16) Send flag or
idle be tween
frames
0 – Send flags (7E) between frames
1 – Send idle (FF) between frames
Controls how the HDLC transmitter operates while no data is available
to transmit. When FLAG*/IDL is set to 0, the transmitter inserts flags
while no data is available to transmit. When FLAG*/ IDL is set to 1, the
trans mitter inserts marks while no data is avai lable to transm it. The
HDLC transmitter always sends at least one flag immediately before the
start of the HDLC frame and at least one fla g immediately after t he end
of the HDLC frame.
Code
(Bit #) Definition
of code Description
Table 102: Control Reg ister C (HDLC ) bit definition
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Status Register B (HDLC)
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NET+50/20M Hardware Reference
Reminder:
DMA is not supported in HDLC mode.
Status Register B and bit definitions
Code
(Bit #) Definition of
code Description
FLAGS
(D31) Static receive r
flag status 0 – Receiver is active or not receiving flags
1 – Receiver is IDLE receiving flags
Set to 1 when the HDLC receiver has detected that the remote
transmitter is sending continuous flags.
IDLE (D30) Static receiver
IDLE status 0 – Receiver is active or not receiving IDLE codes
1 – Receiver is IDLE receiving ID LE codes
Set to 1 when the receiver is inactive and receiving all “1”s.
Set to 0 when the receiver is actively receiving a packet or not
receiving the all “1s” condition.
RXBCAM1
(D27) Receive buffer
closed due to
address match 1
Indicates that the HDLC rece iver has found an 8-bit address
comparison match between t he first byt e of the HD LC frame and t he
value found in the RDMB1 field. The RXBCAM1 field also indicates
that the HDLC receiver has found a 16-bit address comparison match
between the first two bytes of the HDLC frame and the value found
in the RDMB1/RDMB2 fields (provided the MAM1 field is set to 1).
The RXBCAM1 field is valid only when the RBC field is set in Serial
Channel Status Register A.
Table 103: Status Register B (HDLC) bit def inition
FLAGS
0
R
15 14 13 12 11 10 9 8765432 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Addres s = FFD0 0028 / 68
RXBCN RXBCARXBCO
0
R
RXBCL
0
R
0
R0
R
RXBCABIDLE RXBCAM1RXBCAM2 RXBCCRXBCAM3RXBCAM4
0
R 0
R0
R
0
R0
R
0
R0
R
TXBCC TXBCU ONLOOP L S END
0
R 0
R
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Serial Controller Module
RXBCAM2
(D26) Receive buffer
closed due to
address match 2
Indicates that the HDLC rece iver has found an 8-bit address
comparison match between t he first byt e of the HD LC frame and t he
value found in the RDMB2 field.
The RXBCAM2 field is valid only when the RBC field is set in Serial
Channel Status Register A.
RXBCAM3
(D25) Receive buffer
closed due to
address match 3
Indicates that the HDLC rece iver has found an 8-bit address
comparison match between t he first byt e of the HD LC frame and t he
value found in the RDMB3 field. The RXBCAM3 field also indicates
that the HDLC receiver has found a 16-bit address comparison match
between the first two bytes of the HDLC frame and the value found
in the RDMB3/RDMB4 fields (provided the MAM2 field is set to 1).
The RXBCAM3 field is valid only when the RBC field is set in Serial
Channel Status Register A.
RXBCAM4
(D24) Receive buffer
closed due to
address match 4
Indicates that the HDLC rece iver has found an 8-bit address
comparison match between t he first byt e of the HD LC frame and t he
value found in the RDMB4 field.
The RXBCAM4 field is valid only when the RBC field is set in Serial
Channel Status Register A.
RXBCN
(D23) Receive buffer
closed NORMAL Indicates that the current HDLC frame was received without any
errors. The RXBCN field is valid only when the RBC field is set in
Serial Channel Status Register A.
RXBCC
(D22) Receive buffer
closed due to
CRC erro r
Indicates that the current HDLC frame was received with CRC errors.
The firmware driver can reject the packet using knowledge provided
by RXBCC.
The RXBCC field is valid only when the RBC field is set in Serial
Channel Status Register A.
RXBCO
(D21) Receive buffer
closed due to
OVERRUN er ror
Indicates that the curre nt HDL C fr ame was r eceived with a rece ive
FIFO overrun condition. An overrun condition indicates that the
receive FIFO was not emptied at a fast enough rate. The firmware
driver can reject the packet using knowledge provided by RXBCO.
The RXBCO field is valid only when the RBC field is set in Serial
Channel Status Register A.
RXBCA
(D20) Receive buffer
closed due to
ALIGNMENT
error
Indicates that the curre nt HDL C fr ame was received wi th an
alignment error condition. An alignment error condition occurs when
an HDLC frame ends on a non-8-bit boundary. The firmware driver
can reject the packet using knowledge provided by RXBCA.
The RXBCA field is valid only when the RBC field is set in Serial
Channel Status Register A.
Code
(Bit #) Definition of
code Description
Table 103: Status Register B (HDLC) bit def inition
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Status Register C (HDLC)
Status Register C provides error counter registers that are required when the serial
channel is configured to operate in HDLC mode.
RXBCL
(D19) Receive buffer
closed due to
LARGE e rr o r
Indicates that the curre nt HDL C fr ame that was received was too
long. The HDLC frame length exceeded the value programmed in the
HDLC Max Length register. The firmware driver can reject the
packet using knowledge provided by RXBCL.
The RXBCL field is valid only when the RBC field is set in Serial
Channel Status Register A.
RXBCAB
(D18) Receive buffer
closed due to
ABORT
Indicates that the curre nt HDLC fr ame was r eceived wi th an abort
error condition. An abort error condition occurs when an HDLC
receiver detects a continuous string of 8 consecutive “1”s. The
firmware driver can reject the packet using knowledge provided by
RXBCAB.
The RXBCAB field is valid only when the RBC field is set in Serial
Channel Status Register A.
TXBCC
(D15) Transmit buffer
closed due to loss
of CTS
Indicates that the curr ent HDLC transmi t frame was aborted due to a
loss of the CTS (clear-to-send) condition. The CTSTX field in Serial
Channel Control Register A must be set for this to happen. The
firmware driver can use TXBCC to indicate that the HDLC frame was
not successfully transmitted.
The TXBCC field is valid only when the TBC field is set in Serial
Channel Status Register A.
TXBCU
(D14) Transmit buffer
closed due to
UNDER RUN
error
Indicates that the current HDLC transmit frame encountered an
underrun condition. The firmware driver can use TXBCU to indicate
that the HDLC frame was not successf ully tra nsmitte d.
The TXBCU field is valid only when the TBC field is set in Serial
Channel Status Register A.
Code
(Bit #) Definition of
code Description
Table 103: Status Register B (HDLC) bit def inition
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Serial Controller Module
Status Re gister C and bit definitions
FIFO Data Register LAST (HDLC)
The FIFO Data Register LAST provides transmit data for the serial channel. This
register identifies the last data value for the current transmit data frame. W riting to
Code
(Bit #) Definition of
code Description
IEEF
(D31) Interr upt enable Setting this bit causes a receiver-interrupt to occur when the EFDF
counter reaches a value of 24.
EFDF
(D20:16) E rror fre e
discarded frame
counter
Identifies th e number of frames disca rded due to a fa ilure to match the
selected match address value. These frames did not result in a CRC
error.
The counter stops counting when it reaches the maximum value of 31.
An interrupt can be enabled when the counter reaches a value of 24.
This register is automatically cl eare d each time it is read.
IECE
(D15) Interr upt enable Setting this bit causes a receiver-in terrupt to occur when the CRCDF
counter reaches a value of 8.
CRCDF
(D03:00) CRC error
discarded frame
counter
Identifies the number of frames discarded due to a failure to match the
selected match address value. These fr ames al so resul ted in a CRC
error. Note that this counter does not include those frames with a CRC
error that had a valid matching address.
The counter stops counting when it reaches the maximum value of 15.
An interrupt can be enabled when the counter reaches a value of 8.
This register is automatically cl eare d each time it is read.
Table 104: Status Register C (HDLC) bit def inition
IEEF
0
R/W
0
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Address = FF D0 002C / 6C
CRCDF
EFDF
0
R/C
IECE
0
R/C
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this register marks the end of the data frame and identifies when to send the
closing flag in HDLC mode.
0
W
0
W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
Address = FFD0 0030 / 70
DAT A
DAT A
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Serial Controller Module
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MIC Controller Module
CHAPTER 12
This chapter applies to the NET+50 chip only.
Important:
The previ o us NET_ ARM ha rdware ma nu a l s used the te rm ENI to
reference both the ENI module, which contains the IEEE 1284 ports
and the GPIO ports, and the ENI interface, which is an address and
data bus with its own protocol and timing.
The module that contains all three interfaces is now called the Multi
Interf ac e Co nt roller, or MIC.
The Multi-Interface Controller (MIC) module provides three separate, mutually
exclusive interfaces between the NET+50 chip and external devices:
Four GPIO ports
Four IEEE 1284 ports
Four variations of the ENI Interface
Only one mode can be operational at any given time.
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MIC controller modes of operation
The MIC controller module is allocated forty NET+50 chip I/O pins. The use of
these 40 pins is determined automatically when the MICMODE configuration bits
are written in the General Control register. The configuration bits ar e written either
at boot-up with the information on the address lines or at any time with firmware.
See Chapter 3, "NET+50 Chip Package" for mor e information.
Figure 39 provides a high-level overview of the MIC contr oller module.
Figure 39: MIC cont roller high-level bl ock diagram
GPIO mode. Provides two 8-bit general p urpose input/output ports
and two 8-bit input ports. When the GPIO mode is used, the IEEE 1284
mode and the ENI mode interfaces are disabled.
IEEE 1284 mo de. Used in commercial network print server applications.
The commercial application provides a bridge between a LAN and up
to four external devices using the IEEE 1284 parallel port interface.
When the IEEE 1284 mode is used, the GPIO mode and the ENI mode
interfaces are disabled.
ENI mode s. Used in the OEM network server application. The OEM
application provides a bridge between a LAN and a shared memory or
Conf ig
block
DMA
controller
module
OEM
network
server
applicati ons
Outbound
Reg (4 bytes)
GPI O
Control
outputs Dat a buff er s Addres s
inputs Status
inputs
ENI shar ed
RAM
controller
EN I FIFO
controller
32 byte
FIFOs
16 I/O 16
inputs
Network
print s erver
applications
IEEE
1284
mode
controller
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MIC Controller Module
FIFO mode interface. The shared memory interface provides up to 64K
of random access shared RAM between the NET+50 chip and the
external system. The FIFO mode interface supports two 32-byte FIFOs,
one for each direction streaming FIFO. When any of the ENI modes are
used, the GPIO and the IEEE 1284 interface are disabled.
–The two ENI shared RAM modes provide support for shared RAM only.
–The two ENI FIFO modes support both the data-streaming FIFOs and
shared memory at the same time. Note that when the data-streaming
FIFOs are configured for DMA, the shared memory is limited to 8K
because PA13, PA14, and PA15 are reassigned for DMA handshake
signals.
MIC modes of operation
The MIC module can be set to any of these six configurations:
The MICMODE field in the General Control register controls the MIC mode of
operation. The MICMODE field can be loaded automatically during bootstrap,
using or omitting 1K ohm pulldown resistors on addr ess lines A22, A21, and A20.
The state of these thre e address lines is r ead when power is applied to the system,
and written to bits D2:D0 of the General Control register. The configuration can be
changed any time after booting by rewriting to bits D2:D0.
Table 106 lists the address line characteristics and D2:D0 values that control each
MIC configuration. See the discussions of each register for more information.
Configuration Description
GPIO interface General purpose input/output
IEEE 1284 host port Four ports
ENI host shared RAM-16 interface 16-bit shared memory only
ENI host shared RAM-8 interface 8-bit shared memory only
ENI host FIFO-16 interface 16-bit register and shared memory
ENI host FIFO-8 interface 8-bit register and shared memory
Table 105: MIC mo de settin gs
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MIC controller configuration
The MIC controller module has a block of configuration registers, as shown:
Configuration A22 A21 A20 D2 D1 D0
GPIO 1K pulldown 1K pulldown 1K pulldown 0 0 0
IEEE 1284 1K pulldown 1K pulldown Floating 0 0 1
Reserved 1K pulldown Floating 1K pulldown 0 1 0
Reserved 1K pulldown Floating Floating 0 1 1
ENI 16-bit shared RAM only Floating 1K pulldown 1K pulldown 1 0 0
ENI 8-bit shared RAM only Floating 1K pulldown Floating 1 0 1
ENI FIFO, 16-bit with shared RAM Floating Floating 1K pulldown 1 1 0
ENI FIFO, 8-bit with shared RAM Floating Floating Floating 1 1 1
Ta ble 106: MIC c onfigurations
Address Register
FFA0 0000 General Control register
FFA0 0004 General Status register
FFA0 0008 FIFO Mode FIFO Data register
FFA0 0010 IEEE 1284 Port 1 Control register
FFA0 0014 IEEE 1284 Port 2 Control Register
FFA0 0018 IEEE 1284 Port 3 Control register
FFA0 001C IEEE 1284 Port 4 Control register
FFA0 0020 IEEE 1284 Channel 1 Data register
FFA0 0024 IEEE 1284 Channel 2 Data register
FFA0 0028 IEEE 1284 Channel 3 Data register
FFA0 002C IEEE 1284 Channel 4 Data register
Table 107: MIC controller configuration registers
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MIC Controller Module
MIC module interrupts
The MIC module provides four status indicators to the GEN module for
generating an interrupt to the CPU module. The source for each of these interrupts
is a function of the mode (for example, IEEE 1284) for which the MIC module is
configured.
MIC module hardware initialization
The MICMODE bits (in the General Control register) and the MIC Contr ol register
bits are implementation-dependent. Since external hardware circuitry relies on this
configuration during reset, the MIC module allows external 1K ohm pulldown
FFA0 0030 ENI Control register
FFA0 0034 ENI Pulsed Interrupt register
FFA0 0038 ENI Shared RAM Address register
FFA0 003C ENI Shared register
FFA0 0040 GPIO PORT D register
FFA0 0044 GPIO PORT D register
FFA0 0048 GPIO PORT F register
FFA0 004C GPIO PORT G register
FFA0 0050 GPIO PORT H register
Address Register
Table 107: MIC controller configuration registers
GEN interrupt GPIO IEEE 1284 mode ENI host mode
MIC port 1 D Port 1 FIF O recei ver
MIC port 2 F Port 2 FIFO transmitter
MIC port 3 G Port 3 ENI interrupt
MIC port 4 H Port 4 ENI bus error
Table 108: MIC interrupt sources
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resistors on the addr ess lines to configure their initial values. The system bus
address bits are used to configure the values during a powerup reset.
The NET+50 chip provides internal pullup resistors on all addr ess signals. 1K ohm
external pulldown resistors can be used to configure the MICMODE (
))$
)
and MICCTL (
))$
) register bits. This list identifies which ADDR bits control
which fu nc t i o ns:
Note: The inverted PSIO address bit (ADDR7) is loaded into the PSIO
configu ration bit in the MIC Contr ol r egister. In the MIC Contr ol r egister,
1RUPDO
and
36,2
.
GPIO mode
The GPIO mode provides four 8-bit general purpose input/output ports: POR TD,
PORTF, PORTG , and PORTH.
GPIO mode is configured when the MICMODE field in the MIC General Control
register is set to 0. MICMODE can be defaulted to 0 during bootstrap by providing
1K ohm pulldown resistors on NET+50 pins A22, A21, and A20. (See "MIC module
hardware initialization" on page 333 for more information.)
Address bit Function Setting
ADDR[22:20]: MICMODE[2:0] Configuration bits
ADDR[07]: ENI control D9 PSIO* (0 = PSIO, 1 = Normal)
ADDR[06]: ENI control D6 WR_OC
ADDR[05]: ENI contro l D5 DINT2*
ADDR[04]: ENI contro l D4 I_OC
ADDR[03] : ENI control D3 DMAE*
ADDR[02]: Reserved
ADDR[01] : ENI control D1 EPACK*
ADDR[00] : ENI control D0 PULINT*
Table 109: Address bit functionality
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MIC Controller Module
GPIO mode can be used instead of IEEE 1284 mode and ENI mode. GPIO mode is
useful when parallel ports, shared RAM, or FIFO are not required. GPIO allows 32
of the 40 pins assigned to the MIC interface to be used for general purpose I/O.
Table 1 10 shows t he PQFP an d BGA pin assig nments for PORTD, PORTF, PORTG,
and PORTH.
These pins comprise four 8-bit GPIO ports:
16 GPIO pins (two 8-bit ports) can be configured for input, output, or
leve l-sensiti ve interrupt.
The other 16 GPIO pins (two 8-bit ports) can be configured as inputs or
level-sensitiv e interrupts.
GPIO function configurations
The GPIO ports can be configu red to provide any of four functions per pin: input,
output, low-level interrupt, and high-level interrupt. The ports are individually
configured and do not have to be set to the same function.
The
02'(
and
',5
bits work together to set the GPIO port configuration. The GPIO
port allows four configurations:
Data in (inpu t)
PORTD PORTF PORTG PORTH
Port PQFP BGA PQFP BGA PQFP BGA PQFP BGA
7 207 T15 35 G16 34 H17 20 K15
6 206 U15 10 P16 31 H16 19 L16
5 205 U14 11 N16 30 J17 18 M17
4 204 T14 12 M15 25 J14 17 L14
3 203 R15 28 H15 24 J15 16 L15
2 202 U13 29 H14 23 K16 15 M16
1 201 P14 32 G15 22 L17 14 N17
0 200 R14 33 G14 21 K14 13 M14
Table 110: PORTD/F/G/H PQ FP/BGA pin assignme nts
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Data out (output)
Low le vel interrupt input (low interrupt)
High level interrupt input (high interrupt)
Table 111 shows the functionality for PORTD. GPIO PORTD r equir es two registers
to configure the functionality of each of the PORTD GPIO pins:
Register
[))$
is used for input data and interrupts.
Register
[))$
produce s the output data.
Table 1 12 shows the functionality for PORTF/G/H. Each port requires only one
register to configure functionality.
FFA00040M
ODE FFA00040
DIR FFA00044
MODE FFA00044
DIR PORTD
function
0000Data input to register
))$
0101Output from register
))$
1000Low interrupt to
register
))$
1100High interrupt to
register
))$
Table 111 : PORTD confi guration
Mode Dir PORTF FFA00048 PORTG
FFA0004C PORTH
FFA00050
0 0 Input Input Input
01Output
1 0 L ow interrupt Low interrupt Low interrupt
1 1 High inte rr upt
Table 112: PO RTF/G/H configuration
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MIC Controller Module
Functions
POR TF and PORTD allow all four functions. PORTG and PORTH are limited to
data input and low-level interrupts.
When the port is configur ed as an input, the system reads the data fiel d
at the addr ess associa ted with the port to determine the lo gic level of the
signal connected to the pin.
When the port is configured as an output, the system writes to the data
field at the address associated with the port to set the logic level of the
pin’s output.
When the port is configured as a low-level or high-level interrupt, the
system reads the data field at the address associated with the port to
determine which of the eight pins caused the interrupt.
The data bit is set to h igh to indicate a valid interrupt level on the pin.
Each port is assigned to a bit in the Interrupt Status register. Any of the eight pins
in the port can set a bit in the Interrupt Status register. The following table shows
how the bi ts a re assigned:
Examples using PORTF
Here is an example of an interrupt configuration and routine using POR TF. This
exam ple al so sh ows ho w to conf igu r e th e port for all four funct ions by set ting two
port pins to each function.
Example 1: Conditions
PORTF7 and PORTF6 are inputs. A low signal is connected to PORT F7
and a high signal is connected to PORTF6.
PORTF5 and PORTF4 are outputs. PORTF5 is set high and PORTF4 is
set low.
GEN Interrupt Status Bit register GPIO port
MIC port 1 D
MIC port 2 F
MIC port 3 G
MIC port 4 H
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PORTF3 and PORTF2 are low-level interrupts. A high signal is
connected to both pins, to start.
PORTF1 and PORTF0 are high-level interrupts. A low signal is
connected to both pins, to start.
Example 2: Conditions
The signal connected to PORTF2 goes low.
The signal connected PORT0 goes high.
Either event ca n cause an interrupt ; thi s example shows both a lo w-level
and high-level interr upt. This e vent sets the IRQ sig nal to the ARM. T he
ARM issues an interrupt exception vector to address 0x18. At address
0x18, there should be a jump instruction to the interrupt service routine.
Address Action
[))$ [
Set the MIC mode to GPIO using the MIC mode General Control
register. The MICDIAG bit (D12) must be set to 1 to change the MIC
mode.
[))$ [)
Set PORTF as described in the "Example 1: Conditions" section.
Note: If the port was read at this time,
[))$
would read
[)
because PORTF7 and PORTF6 are inputs and
PORTF6 is high.
[))% [
Set the Interrupt Enable register to allow an interrupt to be caused by
PORTF. See "Interrupt generation and control" on page 93 for more
information.
At this point, the configuration is complete.
Address Action
[))% [
The Interrupt Status register is read to determine that the interrupt is
caused by PORTF. See "Interrupt generation and control" on page 93
Note that the interrupt is not latched. If the two signals that caused the
interrupt revert to their original state very quickly,
[))%
reads 0.
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MIC Controller Module
PORTD register
PORTD can be used for general purpose I/O or level-sensitive interrup t inputs.
Each of the eight PORTD GPIO pins can be individually programmed to general
purpose input, general purpose outpu t , active low interrupt, or active high
interrupt.
See Table 110: "PORTD/F/G/H PQFP/BGA pin assignments" on page
335 for PORTD GPIO bit/pin assignments.
See Table 111: "PORTD configuration" on page 336 for PORTD
configuration functionality.
General purpose I/O
When both MODE bits (
[))$
and
[))$
) are set to 0, the
respective PORTD bit is configured for either input or output.
The respective bits in the DIR field are used to control the direction of
the G PIO data .
–A DIR setting of 0 in both registers configures the input mode.
–A DIR setting of 1 in both registers configures the output mode.
When MODE and DIR ar e set to 0, the PORTD bi t is configur ed in inp ut
mode. The NET+50 processor reads the current logic value on the
PORTD pin by reading the state of the respective bit in the DATA field
of register
[))$
.
When the MODE bit is set to 0 and the DIR bit is set to 1, the PORTD bit
is conf igured in output mode . The NET+50 proce ssor sets the logic
value on the PORTD pin by setting the state of the respective bit in the
DATA field of register
[))$
. Reading the DATA field when
[))$ [)
The PORTF GPIO re gist er is read to determi n e which of the four
signals configured as interrupts caused the interrupt. In this example,
the interrupt is caused by either PORTF2 or PORTF0.
Note that the interrupt is not latched. If the two signals that caused the
interrupt revert to their original state very quickly,
[))$
reads
[)
.
Address Action
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configured in output mode returns the current setting of the DATA
field.
Interrupt Mode
When both MODE bits are set to 1, the POR TD I/O pin is used for interrupt input.
In this mode, the DIR register bits define the level sensitive state of the interrupt
input (0 for active low level or 1 for active high level), and the PORTD data r egister
provides the interrupt status. A 1 in this register indicates an active interrupt. To
clear the interrupt condition, the external signal must change to the inactive state.
PORTD asserts an interrupt to the NET+50 interrupt controller using the M IC
Port 1 connection. The MIC Port 1 interrupt is active when any one of the PORTD
interrupts is active, and r emains active until the external signal changes to the
inactive state.
PORTD registers and bit definitions
Each bit in the MODE fields corresponds to one of the NET+50 PORTD
bits. D31 controls PORTD7, D30 controls PORTD6, and so on.
Each bit in the DIR field corr esponds to one of the NET+50 PORTD bits.
D23 controls PORT D7, D22 controls PORTD6, and so on.
Each bit in the DATA field corresponds to one of the NET+50 PORTD
bits. D7 controls PORT FD, D6 controls PORTD6, and so on.
MODE
_
0
R/W
0
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
0
R/W
P ort D input an d in t errupt data
DIR
Addres s = FFA0 0040
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MIC Controller Module
Code
(Bit #) Description
MODE Used to configure each PORTD pin individually to operate in either GPIO mode or
interrupt mode. Setting the MODE bit to 0 selects GPIO mode; setting the bit to 1 selects
interrupt mode.
DIR When the MODE bit in both registers is set to 0, the DIR bit is used to configure the
PORTD pin to operate in either input mode or output mode. Setting the DIR bit to 0
selects input mode; setting the bit to 1 selects output mode.
When the MODE bit in both registers is set to 1, the DIR bit is used to configure the
PORTD pin to be either an active low interrupt input or active high interrupt. Setting the
DIR bit to 0 selects active low interrupt mode; setting the bit to 1 selects active high
interrupt mode.
DATA When the MODE bit in both registers is set to 0 for GPIO mode, the DATA bit from
register
[))$
provides the current state of the NET+50 GPIO signal (regardless
of its configuration mod e). Writing to the DA TA field in register
[))$
defines
the current state of the NET+50 GPIO signa l when the signal is de fined to operate in
GPIO output mode. Writing a DATA bit when configured in GPIO input mod e or
interrupt mode has no ef f ect.
When the MODE bit is set to 1 for interrupt mode, the corresponding DATA bits are
used to indicate a pending interrupt condition. A pending interrupt is identified with a 1
in the DATA field of register
[))$
. The external signal input must be restored
to its inactive state to remove the interrupt condition. Setting the MODE and DIR bits
to 0 can also disable the interrupt.
Table 113: GPIO PORTD register bit de finition
MODE
_
0
R/W
0
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
0
R/W
P ort D output data
DIR
Address = FFA 0 0044
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PORTF register
The PO RTF I/O register ca n be used wh en ev e r t he MI C mod u l e i s co nfigured t o
operate in GPIO mode. PORTF can be used for general purpose I/O or level-
sensitive interrupt inputs.
Each of the eight PORTF GPIO pins can be individually programmed to general
purpose input, general purpose outpu t , active low interrupt, or active high
interrupt.
See Table 110: "PORTD/F/G/H PQFP/BGA pin assignments" on page
335 for PORTF GPIO bit/pin assignments.
See Table 112 : " P O RTF/G/H con f i g u r at i o n" on page 3 36 fo r PORTF
configuration functionality.
General purpose I/O mode
When a MODE bit is s et to 0, the respectiv e PORTF bit is configured for
general purpose I/O (GPIO).
When a PORTF MODE bit is set to 0, the respective bit in the DIR field
controls the direction of the GPIO configuration:
–A DIR setting of 0 configures input mode.
–A DIR setting of 1 configures output mode.
When both MODE and DIR are set to 0, the POR TF bit is configured in
input mode. The NET+50 processor can read the current logic value on
the POR TF pin by reading the state of the r espective bit in the DATA
field.
When the MODE bit is set to 0 and the DIR bit is set to 1, the PORTF bit
is configured in output mode. The NET+50 processor sets the current
logic value on the PORT F pi n by setting the state of the r espect ive bit in
the DATA field. Reading the DATA field when configured in output
mode retu rns the current setting of the DATA fiel d.
Interrupt mode
When the MODE bit position is configured as 1, the PORTF I/O pin can be used
for interrupt input. In this mode, the DIR register bit defines the level-sensitive
state of the interrupt input (0 for active low level or 1 for active high level), and the
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MIC Controller Module
POR TF data register provides the interrupt status. A 1 in this register indicates an
active interrupt. To clear the interrupt condition, the external signal must change
to the inactive state.
PORTF asserts an interrupt to the NET+50 interrupt controller using the MIC Port
2 connection. The MIC Port 2 interrupt is active when any one of the PORTF
interrupts is active, and r emains active until the external signal changes to the
inactive state.
PORTF register and bit definitions
Each bit in the MODE field corresponds to one of the NET+50 PORTF
bits. D31 controls PORTF7, D30 controls PORTF6, and so on.
Each bit in the DIR field corresponds to one of the NET+50 PORTF bits.
D23 controls PORTF7, D22 controls PORTF6, and so on.
Each bit in the DATA field corresponds to one of the NET+50 PORTF
bits. D07 controls PORTF7, D06 controls PORTF6, and so on.
NET+50 pin GPIO mode, FMOD E=0 Interrupt mode, F MODE=1
PQFP BGA FDIR=0 FDIR=1 FDIR=0 FDIR=1
35 G16 D7 IN D7 OUT FI7-0 FI7-1
10 P16 D6 IN D6 OUT FI6-0 FI6-1
11 N16 D5 IN D5 OUT FI5-0 FI5-1
12 M15 D4 IN D4 OUT FI4-0 FI4-1
28 H15 D3 IN D3 OUT FI3-0 FI3-1
29 H14 D2 IN D2 OUT FI2-0 FI2-1
32 G15 D1 IN D1 OUT FI1-0 FI1-1
33 G14 D0 IN D0 OUT FI0-0 FI0-1
Table 114: PO RTF pin/mode/dir configuration
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Code
(Bit #) Description
MODE
(D31:24) Used to configure each of the PORTF pins to operate in either GPIO mode or interrupt
mode. Setting the MODE bit to 0 selects GPIO mode; setting the bit to 1 selects interrupt
mode.
DIR
(D23:16) When the MODE bit is set to 0, the DIR bit is used to configure the PORTF pin to
operate in either input mode or output mode. Setting the DIR bit to 0 selects input mode;
setting the bit to 1 selects output mode.
When the MODE bit is set to 1, the DIR bit is used to configure the PORTF pin to be
either active low interrupt input or active high interrupt input. Setting the DIR bit to 0
selects active low interrupt mode; setting the bit to 1 selects active high interrupt mode.
DATA
(D07:00) When the MODE bit is set to 0 for GPIO mode, the DATA bit provides the current state
of the NET+50 GPIO signal (regardless of its configuration mode). Writing the DATA
field defines the current state of the NET+50 GPIO signal when the signal is defined to
operate in GPIO output mode. Writing a DATA bit when configured in GPIO input
mode or interrupt mode has no effect.
When the MODE bit is set to 1 for interrupt mode, the corresponding DATA bits are used
to indicate a pending interrupt co ndition. A pending interrupt is identified with a 1 in the
DATA field. The external signal input must be restored to its inactive state to remove the
interrupt condition. Se tting the MODE an d DIR bits to 0 can also disa ble the interrupt.
Table 115: GPIO PORTF regi ster bit definition
MODE
_
0
R/W
0
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
0
R/W
DAT A
DIR
Address = FFA 0 0048
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MIC Controller Module
PORTG register
The PORTG I/O register can be used whenever the MIC module is configured to
operate in GPIO mode. POR TG can be used for general purpose input or level-
sensitive interrupt inputs.
Each of the eight PORTD GPIO pins can be individually programmed to general
purpose input, active low interrupt, or active high interrupt.
See Table 110: "PORTD/F/G/H PQFP/BGA pin assignments" on page
335 for PORTG GPIO bit/pin assignments.
See Table 112: "P O RTF/G/H conf i g u r at i o n" on pa g e 3 36 fo r PORTG
configuration functionality.
General purpose I/O
When a MODE bi t is set to 0, t he respect ive PORTG bit i s configur ed for
general purpose input.
When a PORT G MODE bit is set to 0, a DIR bit of 0 configures input
mode. PORTG does not support GPIO output mod e .
When both MODE and DIR are set to 0, the PO RTG pi n i s c onfig ured in
input mode. The NET+50 processor can read the current logic value on
the PORTG pin by reading the state of the respective bit in the DATA
field. PORTG does not suppo rt GPIO output m ode.
Interrupt mode
When the MODE bit position is configured as 1, the POR TG I/O pin can be used
for interrupt input. In this mode, the DIR register should be set to 0 for active low
level, and the PORTG data register provides the interrupt status. A 1 in this
register indicates an active inte rru pt. To clear the interrupt condition, the external
signal must change to the inactive state.
POR TG asserts an interrupt to the NET+50 interrupt controller using the MIC Port
2 connection. The MIC Port 2 interrupt is active when any one of the PORTG
interrupts is active and remains active until the external signal changes to the high
state.
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NET+50/20M Hardware Reference
PORTG register and bit definitions
Each bit in the MODE field corresponds to one of the NET+50 PORTG
bits. D31 controls PORTG7, D30 controls PORTG6, and so on.
Each bit in the DATA field corresponds to one of the NET+50 PORTG
bits. D07 controls PORTG7, D06 controls PORTG6, and so on.
NET+50 pin GPIO mode Inter rupt mode
PQFP BGA GMODE=0
GDIR=0 GMODE=1
GDIR=0
34 H17 D7 IN GI7-0
31 H16 D6 IN GI6-0
30 J17 D5 IN GI5-0
25 J14 D4 IN GI4-0
24 J15 D3 IN GI3-0
23 K16 D2 IN GI2-0
22 L17 D1 IN GI 1-0
21 K14 D0 IN GI0-0
Table 116: PORTG pin/m ode/dir config uration
MODE
_
0
R/W
0
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
0
R/W
DAT A
DIR
Address = FFA0 004C
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PORTH register
The PORTH I/O register can be used whenever the MIC module is configured to
operate in GPIO mode. POR TH can be used for general purpose input or level-
sensitive interrupt inputs.
Each of the eight PORTD GPIO pins can be individually programmed to general
purpose input, active low interrupt, or active high interrupt.
See Table 110: "PORTD/F/G/H PQFP/BGA pin assignments" on page
335 for PORTH GPIO bit/pin assignments.
See Table 112: "P O RTF/G/H conf i g u r at i o n" on pa g e 3 36 fo r PORTH
configuration functionality.
General purpose I/O mode
When a MODE bit i s set t o 0, t he r espe cti ve PORTH bit is conf igur ed fo r
general purpose input.
When a PORT H MODE bit is set to 0, a DIR bit of 0 configures input
mode. PO RTH does not support G PIO outpu t mode.
Code
(Bit #) Description
MODE
(D31:24) Used to individually configure each of the PORTG pins to operate in either GPIO mode
or interrupt mode. Setting the MODE bit to 0 selects GPIO mode; setting the bit to 1
selects interrupt mode.
DIR
(D23:16) Should always be se t to 0.
DATA
(D07:00) When the MODE bit is set to 0 for GPIO mode, the DATA bit provides the current state
of the NET+50 GPIO signal (regardless of its configuration mode). Writing a DATA bit
when configured in GPIO input mode or interrupt mode has no effect.
When the MODE bit is set to 1 for interrupt mode, the corresponding DATA bits are
used to indicate a pending interrupt condition. A pending interrupt is identified with a 1
in the DATA field. The external signal input must be restored to its inactive state to
remove the interrupt condition. Setting the MODE bit to 0 can also disable the interrupt.
Table 117: GPIO PORTG register bit de finition
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When both MODE and DIR are set to 0, the PORTH bit is configured in
input mode. The NET+50 processor can read the current logic value on
the PORTH bit by reading the state of the respective bit in the DATA
field. PORTH does not support GPIO output mode.
Interrupt mode
When the MODE bit position is configured as 1, the PORTH I/O pin can be used
for interrupt input. In this mode, the DIR register bit should be set to 0 for active
low level. A MODE register bit value of 1 automatically enables the interrupt, and
the PORTH data register provides the interrupt status. A 1 in this register indicates
an active interrupt. To clear the interrupt condition, the external signal must
change to the inactive state.
PORTH asserts an interrupt to the NET+50 interrupt cont roller using the MI C
Port 2 connection. The MIC Port 2 interrupt is active when any one of the PORTH
interrupts is active and remains active until the external signal changes to the high
state.
NET+50 pin GPIO mode Inter rupt mode
PQFP BGA HMODE=0
HDIR=0 HMODE=1
HDIR=0
20 K15 D7 IN GI7-0
19 L16 D6 IN GI6-0
18 M17 D5 IN GI5-0
17 L14 D4 IN GI4-0
16 L15 D3 IN GI3-0
15 M16 D2 IN GI2-0
14 N17 D1 IN GI1-0
13 M14 D0 IN GI0-0
Table 118: PO RTH pin/mode/dir configuration
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MIC Controller Module
PORTH register and bit definitions
Each bit in the MODE field corresponds to one of the NET+50 PORTH
bits. D31 controls PORTH7, D30 controls PORTH6, and so on.
Each bit in t he DIR field co rr esponds to one of the NET+50 PORTH bi ts.
D23 controls PORTH7, D22 controls PORTH6, and so on.
Each bit in the DATA field corresponds to one of the NET+50 PORTH
bits. D07 controls PORTH7, D06 controls PORTH, and so on.
Code
(Bit #) Description
MODE
(D31:24) Used to individually configure each of the PORTH pins to operate in either GPIO mode
or interrupt mode. Setting the MODE bit to 0 selects GPIO mode; setting the bit to 1
selects interrupt mode.
DIR
(D23:16) When the MODE bit is set to 0, the DIR bit is used to configure the PORTH pin. Setting
the DIR bit to 0 selects input mode.
When the MODE bit is set to 1, the DIR bit is used to configure the PORTH pin to be
an act iv e lo w in t e rr up t input. Setting t h e DIR bit t o 0 selects a ctive lo w interr u p t mo d e .
DATA
(D07:00) When the MODE bit is set to 0 for GPIO mode, the DATA bit provides the current state
of the NET+50 GPIO signal (regardless of its c onfiguration mode). Note that writing a
DATA bit when configured in GPIO input mode or interrupt mode has no effect.
When the MODE bit is set to 1 for interrupt mode, the corresponding DATA bits are
used to indicate a pending interrupt condition. A pending interrupt is identified with a 1
in the DATA field. The external signal input must be restored to its inactive state to
remove the interrupt condition. Setting the MODE and DIR bits to 0 can also disable the
interrupt.
Table 119: GP IO PORTH register bit definition
MODE
_
0
R/W
0
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
0
R/W
DAT A
DIR
Address = FFA 0 0050
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NET+50/20M Hardware Reference
IEEE 1284 host interface (4-port) module
When the MIC controller is configured in IEEE 1284 mode, the NET+50 chip
supports four IEEE 1284 parallel port interfaces. The NET+50 chip uses external
hardwar e (latching transceivers) to minimize the pin c ount r equirements. All IEEE
1284 ou tput sign als ar e shar ed betw een port s using a simple multiplexing scheme.
The NET+50 chip provides unique CLK signals to load the shared output data into
a specific 1284 port driving register.
The NET+50 IEEE 1284 interface can be used only to provide the host side of the
IEEE 1284 protocol. The NET+50 chip cannot be used to provide the peripheral
side of the IEEE 1284 protocol.
Each port requires two external 8-bit latches (a 16-bit FCT16646 device works well
in this application). One latch stores the IEEE 1284 data signals while the other
stores the IEEE 1284 contr ol signals. The NET+50 chip provides two CLK signals
per port (one for data and one for control) and one output enable. The output
enable allows input data flow (from multiple port transceive rs) for bi-directional
IEEE 1284 modes.
Figure 40 shows the external components required to implement this scheme.
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MIC Controller Module
Figure 40: IEEE 1284 external transceive rs
The IEEE 1284 data and control signals are multiplexed using a single 8-bit data
bus. Table 120 identifies the sig n al as sig nm en ts.
Data bit Data phase Control phase
D7 D7 STROBE*
D6 D6 AUTOFD*
D5 D5 INIT*
D4 D4 HSELECT*
D3 D3 PDIR
D2 D2 PIO
D1 D1 LOOPBACK
D0 D0 LOOP strobe
Table 120: IEEE 1284 data bus assignments
NCC
D(7:0)
CLKD1
CLKD2
CLKD3
CLKD4
CLCK1
CLCK2
CLCK3
CLCK4
POE1*
POE2*
POE3*
POE4*
74FCT16646
D(7:0)
CLKD1
DIR
POE1*
D(7:0)
CLCK 1
DIR
OE*
P1284
DAT A
P1284
CONT ROL
74FCT16646
74FCT16646
Single port 2 port
D(7:0)
CLKD1
DIR
POE1*
D(7:0)
CLCK1
DIR
OE*
CLKD2
DIR
POE2*
D(7:0)
CLCK2
DIR
OE*
D(7:0)
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IEEE 1284 Signals
STROBE*, AUTOFD*, INIT*, and HSELECT*. Four contr ol outputs for
the IEEE 12 84 i nter f ace: T hese sig nal s are driven through a para ll el p or t
cable.
PDIR. Defines the direction of the external data transceiver. Its state is
directly cont rolled by th e BIDIR bit in the IEEE 1284 Control register.
–When configured in the 0 state, data is driven from the external
transceiver towards the cable.
–When configur ed in the 1 state, data is r ecei ved fro m the cable (used for
bi-directional IEEE 1284 modes).
PIO. Controlled by firmware. Its state is directly controlled by the PIO
bit in the IEEE 1284 Control register.
LOOPBACK. Configures the port in external loopback mode. This
signal can be used to control the mux line in the external FCT646
devices. Its state is directly controlled by the LOOP bit in the IEEE 1284
Control register. When set to 1, the FCT646 transceivers drive inbound
data from the input latch and not the real-time (cable) interface. The
LOOP strobe signal is responsible for writing outbound data into the
inbound latch (completing the loopback path). The LOOP strobe signal
is an inverted copy of the STROBE* signal. It works automatically in
hardware.
Figure 41 provides a simple view of the IEEE 1284 controller hardware.
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MIC Controller Module
Figure 41: IEEE 1284 host controller block diagram
The IEEE 1284 control state machine works to keep the FIFOs empty by strobing
data to the parallel port using the port configuration options defined by the 1284
Port Contr ol register. The contr ol state machine must manipulate the port control
and data signals to adhere to the configured port mode. The control state machine
services all four ports in a round-robin fashion. All four ports share the same
NET+50 chip outputs. External latches are used to store the output signals.
The MIC 1284 controller interfaces with the BBus using 4-by te outbound registers
and 4-byte FIFOs (one register and FIFO per port). DMA channels 3-6 work to
keep the o ut bound r e g i st er s ful l by c au si n g a word writ e ea c h t i me o ne emp t i es .
IEEE 1284 signal cross reference
Table 121 is useful when cross-referencing the names b etween the IEEE 1 284
specification and the bit names in the NET+50 chip architecture. The input/output
column defines the direction with respect to the NET+50 chip 12 84 host inter face.
Outbound
Reg (4 bytes)
Data
buffers
MUX
Status
inputs
4-byte
FIFO
IEEE 1284
control
state
machine
Control
outputs
DMA
controller
module
Config
block
BBus
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IEEE 1284 port multiplexing
The NET+50 chip multiplexes information to the external 1284 transceivers using a
combination of the PDATA[7:0] data bus and the PCLKDx and PCLKCx clock
signals. The PCLKDx signals are used to latch the PDATA bus into the port data
transceiver. Each port is provided with a unique PCLKD signal. Similarly, the
PCLKCx signals are used to latch the PDATA bus into the port control transceiver.
Each port is also pr ovided with a unique PCLKC signal. Each of the eight PCLK
signals is unique, and two signals are never activated at the same time.
See "1284 Port Multiplexing timing," beginning on page 470, for timing
information and an illustration of the relationship between the PCLK and PDATA
signals.
IEEE 1284 mode configuration
Table 122 identifies th e mo d es fo r whic h each 1284 po r t can be co nfigured. Th e
configuration mode is provided using configuration bits in the 1284 Port Control
NET+50
chip name Host
input
output
Standard
parallel
port Nibble
mode Byte mode EPP mode ECP mode
STROBE* OUT nSTROBE nSTROBE HostClk nWRITE HostClk
AUTOFD* OUT nAUTOFEED HostBusy HostBusy nDATASTB HostAck
HSELECT* OUT nSELECTIN 1284Active 1284Active nADDRSTB 1284Active
INIT* OUT nINIT nINIT nINIT nRESET nReverseRequest
ACK* IN nACK PtrClk PtrClk nINTR PeriphClk
BUSY IN BUSY PtrBusy PtrBusy NWAIT PeriphAck
PE IN PE AckDa taR eq AckDataReq User defi ned nAckReverse
PSELECT IN SELECT Xflag Xflag User define d Xflag
FAULT* IN nERROR nDataAvail nDataAvail user defined nPerip hRequest
DATA OUT/IN DATA[8:1] Not used DATA[8:1] AD[8:1] DATA[8:1]
Ta ble 121: 1284 si gnal cross reference
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registers. The operation mode is determined by the r esults of the IEEE 1284
negotiation process, which must be done in firmware.
The NET+50 chip provides hardwar e DMA support while operating in forward
compatibility mode, forward ECP mode, and reverse ECP mode.
IEEE negotiation
The NET+50 chip does not of fer any hardware support for IEEE negotiation.
Negotiation is handled using the manual mode version of forward compatibility
mode (see "IEEE 1284 forward compatibility mode" on page 355). Negotiation
must be executed by manually manipulating the IEEE 1284 control signals
according to the IEEE 1284 specification.
IEEE 1284 forward compatibility mode
While configur ed to operate in forward compatibility mode, the 1284 interface
signals can operate in either manual or automatic mode. Manual mode is
established when the MAN bit is set to 1 in the Port Control register. Automatic
mode is established when the MAN bit is set to 0. The manual forward
compatibility mode configuration supports the IEEE 1284 negotiation function.
When configured to oper ate in automatic forward compatibility mode, each 1284
port can oper ate in one of two timing mo des. The timing modes are configured
using the FAST bit in the IEEE 1284 Port Control registers. Each timing mode is
slightly different. The timing modes are broken down into three major phases:
Mode EPP ECP BIDIR MAN
Manual forward compatibility 0001
Automatic forward compatibility 0000
Nibble mode 0000
Byte mode 0011
Forward ECP 0100
Reverse ECP 0110
EPP 1010
Table 122: IEEE 1284 mode co nfiguration
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Data setup tim e
Port strobe time
Data hold time
The AUTOFD*, HSELECT*, and INIT* outputs are statically-driven based on the
associa tive bit set ti ngs in t he Por t Cont rol regi ste r s. In manual fo rwa r d
compatibility mode, the STROBE* signal is manually controlled using the MSTB*
control bit in the Port Control r egister. The DATA signals are driven from the last
byte value written to the 1284 Channel Data register.
The ACK*, BUSY, PE, PSELECT, and FAULT* bits are manually read via the Port
Control register. The ACK* input can be configured to generate an interrupt on the
high-to-low transition on ACK*.
When the port is configured to operate in automatic mode (MAN bit set to 0), the
hardware automatically manipulates the STROBE* and DAT A signals based on the
current state of the BUSY input. Data bytes are strobed as they are written into the
channel data registers. The channel data register can be manually filled by the
processor or automatically filled using a DMA chann el (when DMAE is set to 1).
When manually loading the channel data register, the OBE status bit must be
honored. When using DMA, the DMA channel automatically honors the OBE
status bit.
See "1284 Compatibility mode timing," beginning on page 471, for information
about the relative time betw een STROBE *, DATA, and BUSY when op erating in
automatic forw ard compatibility mode. STROBE refers to the 1284 strobe
configuration found in the IEEE 1284 Port Configuration registers. The STROBE
width can be configured between 0.5 and 10 us. The STROBE widths ar e not exact
times, only minimu m tim es . Some jitter is introduced in the STROBE widths
because of the port multiplexing .
Compatibility SLOW mode
SLOW mode is configured with FAST set to 0. This mode provides a full STROBE
width of data setup time and a full STROBE width for STROBE* time. This mode
provides a min i mum of STRO BE data h old t i me. Thi s mo de also maintains dat a
hold as long as BUSY is active high.
See Table 154: "1284 Compatibility SLOW mode timing (FAST = 0)" on page 471 for
compatibility SLOW mode timing values.
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MIC Controller Module
Compatibility FAST mode
FAST mode is configured with FAST set to 1. This mode provides a full STROBE
width of data setup time and a full STROBE width for STROBE* time. This mode
provides a min i mum STROBE wi dth of dat a hol d time . Co mp a ti bl e FAST mode
does not wait for BUSY low for data hold time. STROBE* does not go low until
BUSY is low.
See Table 155: "1284 Compatibility FAST mode timing (FAST = 1)" on page 472 for
compatibility FAST mode timing values.
IEEE 1284 nibble mode
Nibble mode is the most common way to obtain reverse channel data from a
printer or peripheral device. Nibble mode data can be obtained while
compatibility forward channel data is in process. The NET+ 50 chip hardware
provides no special support for nibble mode; nibble mode must be handled by
firmware alone.
Figure 42 shows the nibble mode cycle. The nibble input is a 4-bit value that can be
read using the least significant nibble of the 1284 Port Control register. The nibble
is made up of the BUSY, PE, PSELECT, and FAULT* inputs. The steps involved are
listed after the figure.
Figure 42: Nibb le mode cycl e
1The host signals the ability to take data by asserting HostBusy low
(AUTOFD*).
2The peripheral responds by placing the first nibble on the status lines.
3The peripheral s ignals a valid nibble by asserting PtrClk low (AC K *).
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4The host sets HostBusy high to indicate that it has r eceived the nibble and is
not yet ready for another nibble.
5The peripheral sets PtrClk high to acknowledge hos t .
6States 1 through 5 repeat fo r the second nibble.
IEEE 1284 byte mode
Use the byte mode cycle as a second method for obtaining reverse channel data for
printers and peripherals. The byte mode cycle offers an advantage over the nibble
mode cycl e since an enti re byte can be transferred during a sing le cycle. The
disadvantage to byte mode is that it cannot proceed while forward channel
compatibility mode is in process.
Figure 43 describes the byte mode cycle. T he AUTOFD* and STROBE* signals are
manually manipulated.
1The host signals ability to take data by asserting HostBusy low (AUTOFD*).
2The peripheral responds by placin g first byte on data lines.
3The peripheral s ignals valid byte by asserting PtrClk low (ACK*).
4The host sets HostBusy high to indicate that it has received the byte and is
not ready for another byte yet.
5The peripheral sets PtrClk high to acknowledge the host.
6The host pulses HostClk (STROBE* via MSTB*) as an acknowledgment to
the peripheral device.
7States 1 through 5 repeat for additional bytes.
.
Figure 43: Byte mod e cycle
The transition between forward compatibility mode and byte mode
requires software intervention. When transitioning between forward
12
3
4
VA
L
I
D
D
A
T
A
AUTOFD*
ACK*
DATA
STROBE*
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MIC Controller Module
compatibility and byte mode, the firmware must set the AUTOFD*
(HostBusy) signal to 0 and the BIDIR signal to 1.
The transition between byte mode and forward compatibility mode
requires software intervention. When transitioning between byte mode
and forward compatibility mode, the firmwa re m ust wait for ACK* to
be set high by the peripheral. After ACK* is set to 1, the firmware can set
the BI DIR signal to 0. Afte r the BI DIR sign al is se t to 0, the hardware
immediately begins managing the forward channel data traffic.
IEEE 1284 forward ECP mode
When con figured to operate in forward ECP mode, each 1284 port can operate in
one of two timing modes. The timing modes are configured using the FAST bit in
the IEEE 1284 Port Control registers. Each timing mode is slightly different. The
timing modes are broken down into three major phases:
Data Setup Time
Port Strobe Time
Data Hold Time.
The AUTOFD*, HSELECT*, and INIT* outputs are statically-driven based on the
associa tive bit se tt ing s in the Po rt Control r egist e rs.
The ACK*, BUSY, PE, PSELECT, and FAUL T* bits are manually read using the Port
Control register. The ACK* input can be configured to generate an interrupt on the
high-to-low transition on ACK*.
When th e p ort i s co nf i gu red for for wa rd ECP mode , the har d w are auto ma t i ca ll y
manipulates the STROBE* and DATA signals based on the current state of the
BUSY input. Data bytes are strobed as they are written into the Channel Data
registers. The Channel Data register can be manually filled by the processor or
automatically filled using a DMA channel (when DMAE is set to 1). When
manually loading the Channel Data register, the OBE status bit must be honored.
When using DMA, the DMA channel automatically honors the OBE status bit.
See "Forward ECP mode timing," beginning on page 473, for information about the
r elative time between STROBE*, DATA, and BUSY when operating in forward
ECP mode.STROBE refers to the 1284 strobe config uration found in the IEEE 1284
port configuration registers. The STROBE width can be configured between 0.5
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and 10 us. The STROBE widths are not exact times, only minimum times. Some
jitter is introduced in the STROBE widths because of the port multiplexing.
The IEEE 1284 ECP definition provides a concept of command and data codes in
the ECP mode of operation. The host command vs. data encoding is provided by
the AUTOFD* (HostAck) control signal. When AUTOFD* is high, the byte transfer
re presen ts a dat a ope rand . Wh en AUTOFD* is low, the byte transfe r repr esents a
command operand. Command and data operands cannot be intermixed within a
single DMA buffer descriptor. The AUTOFD* signal must be manipulated by
firmwar e. Careful coordination of setting AUTOFD* and writing to the channel
data registers must be established to ensure 1284 protocol compliance.
ECP SLOW mode
SLOW mode is configured with FAST set to 0. This mode provides a full STROBE
width of data setup time. The STROBE* re mains active until BUSY becomes active.
This mode provides a minimum STROBE width of data hold time. STROBE* does
not go low until BUSY is low.
See Table 156: "1284 SLOW Forward ECP mode timing (FAST = 0)" on page 473 for
timing values.
ECP FAST mode
FAST mode is configured with FAST set to 1. This mode drives STROBE* active
immediately after data is valid. The STROBE* remains active until BUSY becomes
active. Data can change immediately after STROBE* is r emoved. STROBE* does
not go low until busy is low.
See Table 157: "1284 FAST Forward ECP mode timing (FAST = 1)" on page 473 for
timing values.
IEEE 1284 reverse ECP mode
The 1284 reverse ECP mode is a fast and effective way to obtain reverse channel
data from a 1284 peripheral. The 1284 reverse ECP mode provides hardwar e DMA
support.
The transition between forward and reverse ECP mode requires
softwar e intervention. When transit ioning between forwar d and rev erse
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MIC Controller Module
ECP mode, t h e firmware must set the INIT* (
Q5HYHUVH5HTXHVW
) signal to
0 and the BIDIR signal to 1. After the BIDIR signal is set, the hardware
immediately begins managing the reverse channel data traffic.
The transition between reverse and forward ECP mode requires
softwar e intervention. When transit ioning between r everse and forwar d
ECP mode, t h e firmware must set the INIT* (
Q5HYHUVH5HTXHVW
) signal to
1 and wait for the peripheral to respond with PE (
Q$FN5HYHUVH
) at 1.
After PE is set to 1, the firmware can set the BIDIR signal to 0. After the
BIDIR sig nal i s set to 0, the hardwar e immediat ely b egi ns manag ing the
forward channel data traffic.
The HSELECT* and INIT* outputs are statically-driven based on the associative bit
sett i ng s in th e Po r t Con t rol regis t er s. Th e ST RO B E* si gna l i s al w ay s h i gh when a
channel is configured for reverse ECP mode. The PE, PSELECT, and FAULT* bits
are manually read using the Port Control register.
When th e p ort i s co nfigured for revers e E CP mode, the hardware auto matical l y
manipulates the AUT OFD* signal based on the current state of the ACK* input.
Inbound DATA bytes are stored in the Channel Data register. When four bytes
have be en rece i ved or t he r ev e r se E CP channel i s close d , t h e i nb o un d bu ffe r ready
(IBR) bit is set in the Channel Control register. While IBR is set, the RXFDB field
identifies how many bytes are available in the Channel Data register.
The IBR bit can be configured to generate an interrupt. The IBR bit can also be used
by a DMA channel (provided DMAE is set to 1) to automatically move the data to
a receive data block.
The BUSY input provides the ECP reverse mode command/data indicator. The
hardware automatically monitors the BUSY input. When BUSY is high, an
inbound reverse channel byte is considered DA TA. The DA TA byte is moved to the
Channel Data register. When the BUSY input is sampled low, the inbound reverse
channel byte is considered command information. The command byte is placed
into the Channel Data register and the receive buffer is marked closed. The RBCC
bit is set in the Channel Command register. The RBCC bit indicates that the last
byte in the Channel Data register is a command code. The RBCC bit is
automatically cleared when the Channel Data register is read.
The reverse ECP mode provides a character timer that can be used to mark the
receive buffer as closed. Each time a byte is moved to the Channel Data register,
the character timer is reset. If the character timer reaches 10 times the STROBE
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configuration, the IBR and RBCT bits are automatically set in the Port Control
register. The RBCT bit is automatically cleared when the Channel Data register is
read. The purpose of the character timer is to guard against stale data sitting in the
Port Data register.
The R BCC a nd R BCT bi ts ar e al s o u sed t o cl os e a D MA bu ffer de sc r i pt o r. When
either bit is set, the DMA buffer descriptor is closed. The RBCC and RBCT status
bits are written to the two most significant bits (D15:14) of the DMA buffer
descriptor’s status field. The character timer begins operation when at least one
data byte has been written to the receive data block. The character timer is cleared
each time a byte is written to the Channel Data register. The purpose of the
character timer is to guar d against stale data sitting in the DMA receive data block.
Figure 44 describes the ECP reverse mode timing cycle. The INIT* signal is
controlled manually. The PE input is polled. The AUTOFD* signal is automatically
controlled by hardwar e. The ACK* and BUSY inputs are automatically monitored
by hardwar e.
Figure 44: ECP rev erse mode tim ing
1The host requests a reverse channel transfer by setting INIT* low.
2The peripheral s i gnals that it is ready to continu e by setting PE low.
3The peripheral places data on the DATA bus and drives the command/data
code on the BUSY signal.
4The peripheral as se rts ACK* low to indicate reverse channel data is ready.
5The host acknowledges the transaction by driving AUTOFD* high.
6The peripheral drives ACK* high again.
7The host drives AUTOFD* low to indicate it’s ready for the next byte.
12 34 5 678
VALID DATA
VALID DATA
ACK*
AUTOFD*
DATA
BUSY
INIT*
PE
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8The peripheral can now change the DATA bus for the next byte.
9Steps 4 through 7 are continuously repeated.
IEEE 1284 EPP mode
The EPP protocol provides another mechanism for the host to access information
in the peripheral. The EPP protocol allows the host to directly write/read
information in the peripheral device. The host can access both address and data
information in the peripheral.
When an EPP write or read cycle occurs, an interlocking handshake occurs
between the host and peripheral. During the read or write cycle, wait states are
inserted into the NET+50 chip bus client memory cycle until the transaction is
complete. The number of wait states is a function of the speed of the peripheral
device.
To execut e a n ad dres s or d at a cy c l e, th e NE T + 50 ch i p bus cl i e nt mu st access a
specific byte within the Port Data register address. The byte address is a function
of the configured Endian mode for the NET+50 chip. See "IEEE 1284 Channel Data
registers" on page 372 to identify which data byte to access. Accessing a half-wor d,
full-word, or incorrect byte location within the Port Data register, while configured
in EPP mode, results in an abort exception.
When an EPP write/ read cycle is executed by the NET+50 chip bus client, the
hardwar e automatically manipulates the STROBE*, AUTOFD*, and HSELECT*
signals. The hardware automatically monitors the BUSY input.
A DMA channel can be configured to perform EPP address and/or data write/
r ea d cycl e s . Th e DMA cha nn e l mu st be co nfigured to pe rf or m me mo ry-to-
memory operations to the proper byte address within the Port Data register. The
DMA channel mu st be con figured to not inc remen t the source or destination
address (depending on the direction).
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EPP data write cycle
Figure 45: EPP data writ e cycle
1The NET+50 chip bus client executes a write cycle to the EPP data byte
addr ess in the Por t Data r eg ister. The host issues DATA and STROBE* l ow as
a result. STROBE* low indicates a write cycle.
2The AUTOFD* signal is asserted active since BUSY is inactive. The host
does not assert AUTOFD* until BUS Y is inactive.
3The host waits for the acknowledgment from the periph eral throu gh an
active BUSY.
4The host drives AUTOFD* inactive high to acknowledge the peripheral.
5The host dr ives STROBE* inactive and tri-s tates the DATA bus to en d the
EPP write cycle.
6Steps 1 through 5 are repeated as necessary.
EPP data read cycle
Figure 46: EPP data read c ycle
1The NET+50 chip bus client executes a read cycle from the EPP data byte
address in the Port Data register. The host asserts STROBE* high as a result.
STROBE* high indicates a read cycle.
12345 6
VALID DATA
STROBE*
AUTOFD*
BUSY
DATA
1234 5 6
VALID DATA
STROBE*
AUTOFD*
BUSY
DATA
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MIC Controller Module
2The AUTOFD* signal is asserted active since BUSY is inactive. The host
does not as sert AUTOFD* until BUSY is inactive.
3The host waits for the acknowledgment from the peripheral through an
active BUSY. The peripheral drives the data b us when BUSY is driven
active.
4The host dr iv es AUTOFD* inactive high to acknowled g e the periphe ral.
Read data is latche d at this time.
5The peripheral removes BUSY and tri-states the data bus.
6Steps 1 through 5 are repeated as necessary.
EPP address write cycle
.
Figure 47: EPP add ress write cycle
1The NET+50 chip bus client executes a write cycle to the EPP address byte
addr ess in the Por t Data r eg ister. The host issues DATA and STROBE* l ow as
a result. STROBE* low indicates a write cycle.
2The HSELECT* signal is asserted active since BUSY is inactive. The host
does not assert HSELECT* until BUSY is inactive.
3The host waits for the acknowledgment from the peripheral through an
active BUSY.
4The host drives HSELECT* inactive high to acknowledge the peripheral.
5The host drives STROBE* inactive and tri-states the DATA bus to end the
EPP write cycle.
6Steps 1 through 5 are repeated as necessary.
12345 6
VALID DATA
STROBE*
HSELECT
*
BUSY
DATA
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EPP address read cycle
Figure 48: EPP address read cycle
1The NET+50 chip bus client execut es a r ead cycl e fr o m the EPP address byte
address in the Port Data register. The host asserts STROBE* high as a result.
STROBE* high indicates a read cycle.
2The HSELECT* signal is asserted active because BUSY is inactive. The host
does not assert HSELECT* until BUSY is inactive.
3The host waits for the acknowledgment from the periph eral throu gh an
active BUSY. The peripheral drives the data b us when BUSY is driven
active.
4The host drives HSELECT* inactive high to acknowledge the peripheral.
Read data is latche d.
5The peripheral removes BUSY and tri-states the data bus.
6Steps 1 through 5 are repeated as necessary.
IEEE 1284 Configuration registers
Table 123 shows the IEEE 1284 configuration registers.
1234 5 6
VALID DATA
STROBE*
HSELECT*
BUSY
DATA
Address Register
FFA0 0010 IEEE 1284 Port 1 Control register
FFA0 0014 IEEE 1284 Port 2 Control register
FFA0 0018 IEEE 1284 Port 3 Control register
FFA0 001C IEEE 1284 Port 4 Control register
FFA0 0020 IEEE 1284 Channel 1 Data register
Table 123: IEEE 1284 registers
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MIC Controller Module
IEEE 1284 Port Control registers and bit definitions
The NET+50 chip supports four IEEE 1284 Control r egisters — one register fo r
each port. This is a 32-bit register containing both contr ol and status bits. All
control/status bits are active high unless an asterisk (*) appears in the signal name;
in this case, the bit is active low. All control bits are set to their respective inactive
state on reset.
Note:
The active edge of ACK Interrupt (ACK I) is active when the
appropriate register bit is set low.
FFA0 0024 IEEE 1284 Channel 2 Data register
FFA0 0028 IEEE 1284 Channel 3 Data register
FFA0 002C IEEE 1284 Channel 4 Data register
Address Register
Table 123: IEEE 1284 registers
Code
(Bit #) Definition of
code Description
PORTE
(D31) 1284 port enable Must be set to 1 to enable the 1284 port to operate. When the PORTE
bit is set to 0, the 1284 port is held in reset.
DMAE
(D30)
1284 port DMA
request enable Must be set to active high to allow the 1284 port to issue transmit data
move requests to the DMA controller. This bit can be set to 0 to
temporarily stall 1284 DMA operations. This bit should not be set
when operating the 1284 port in interrupt service mode. In general,
the DMAE bit should be set once on device open.
Table 124: IEEE 1284 Port Control register bit definition
MAN
15 14 13 12 11 10 98 7 654 32 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset: 0
R
INTEA
DMAE
PORT E FAST HSELECT*
0
R/W 0
R/W
INTEP
0
R/W 0
R/W 0
R/W
0
R/W I
RW
0
R/W
PIO MST B* AUT OFD* INIT *
I
RW I
RW
I
RW
STROBE
LOOPECP
0
R/W R/W
0
R/W
0
R/W
IINTEF IBRIE IBR RFXDB RBCCA CK* FI FOE ACKI B U SY PE
0
R/W 0
R/W 0
R0
R
0
R
0
R/C
0
R
I
R
0
R/W
BIDIR
EPP
0
R/W
RBCT OBE PSELECT FAULT*
0
R0
R0
R0
RI
R
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INTEP
(D29) 1284 port
outbound
interrupt request
enable
Must be set to active high to generate an interrupt when the 1284 port
is ready to accept more data. Setting the INTEP bit to 1 causes an
interrupt to be generated when the OBE status bit is 1. The INTEP bit
should be set only when operating the 1284 port in interr upt service
mode instead of DMA mode.
INTEA
(D28) 1284 port
acknowledge
transition
interrupt request
enable
Must be set to active high to generate an interrupt when the 1284 port
has detected a high-to-low transition on the ACK* input. Setting the
INTEA bit to 1 causes an interrupt to be generated when the ACKI
status bit is 1.
ECP
(D27) 1284 ECP mode
of operation Must be set to 1 to allow the 1284 port to operate in the ECP mode of
operation. See "IEEE 1284 forward ECP mode" on page 359 for
details about operating the 1284 port in ECP mode
LOOP
(D26) 1284 external
loopback When the LOOP bit is set to 1, the 1284 port is configured to operate
in external loopback mode (see "IEEE 1284 external loopback mode"
on page 374).
When LOOP is set to 1, the LOOP strobe signal is asserted instead of
the STROBE* signal in the external control latch (see Table 120:
"IEEE 1284 data bus assignments" on page 351). The LOOP strobe
signal provides a low-to-high transition, allowing the 1284 outbound
data to be latched in the external latch.
The value written into the LOOP field appears on the LOOPBACK
signal in the external control latch.
STROBE
(D25:24) 1284 manual
strobe width
configuration
00 – 0.5 us
01 – 1.0 us
10 – 5.0 us
11 – 10.0 us
Defines the width of the IEEE 1284 strobe timing when the 1284 port
is configured to operate in compatibility mode. See "IEEE 1284
strobe pulse width" on page 373 for more information.
Code
(Bit #) Definition of
code Description
Table 124: IEEE 1284 Port Control register bit definition
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MIC Controller Module
MAN
(D23) 1284 manual
operation mode Must be set to 1 to manually manipulate the state of the IEEE 1284
STROBE* signal.
When MAN is set to 1, the state of the STROBE* signal is
defined by the MSTB* field.
When MAN is set to 0, the state of the STROBE* signal is
automatically controlled by hardware.
A setting of 1 is typically used to manipulate STROBE* for auto-
negotiation purposes. See "IEEE negotiation" on page 355 for more
information.
FAST
(D22) 1284 fast
configuration Used to control data setup and data hold times relative to the
STROBE* signal when the 1284 port is configured to operate in
compatibility or ECP mode of operation. See "IEEE 1284 forward
compatibility mode" on page 355 and "IEEE 1284 forward ECP
mode" on page 359 for information about configuring the FAST field.
BIDIR
(D21) 1284 direction
configuration
0 – Output mode
1 – Input mode
Controls the data direction for the 1284 port.
When BIDIR is 0, the port is configured in output mode; data is
sent from the host to the peripheral.
When BIDIR is 1, the port is configured in input mode; data is
sent from the peripheral to the host.
The value wr itten into the BIDIR fiel d appears on the PDIR signal in
the external control latch (see Table 120: "IEEE 1284 data bus
assignments" on page 351).
PIO
(D20) 1284 spare
bit Provides a spare control signal for application-specific use.
The value written into th e PIO f ield appears on the P IO signal in the
external control latch (see Table 120: "IEEE 1284 data bus
assignments" on page 351).
MSTB*
(D19) 1284 manual
strobe
configuration
Controls the state of the STROBE* signal in the outside control latch
when the MAN bit is set to 1. The MSTB* bit is used to manually
manipulate the state of the STROBE* signal. This feature is primarily
used for 1284 negotiation. See "IEEE negotiation" on page 355 for
more information.
AUTOFD*
(D18) 1284 AUTOFD*
setting Controls the state of the AUTOFD* signal in the external control
latch . Th e v a lue wr it ten into th e AUTOFD* fi eld appear s o n th e
AUTOFD* signal in the external control latch (see Table 120: "IEEE
1284 data bus assignments" on page 351).
Code
(Bit #) Definition of
code Description
Table 124: IEEE 1284 Port Control register bit definition
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INIT*
(D17) 1284 INIT*
setting Controls the state of the INIT* signal in the external control latch. The
value written into the INIT* field appears on the INIT* signal in the
external control latch (see Table 120: "IEEE 1284 data bus
assignments" on page 351).
HSELECT*
(D16) 1284 HSELECT*
setting Controls the state of the HSELECT* signal in the external control
latch . Th e va lu e writte n i n to th e HS ELECT* fie l d ap p e ars on the
HSELECT* signal in the external control latch (seeTable 120: "IEEE
1284 data bus assignments" on page 351).
INTEF
(D15) 1284 port FIFO
empty interrupt
request enable
Must be set active high to generate an interrupt when the 1284 data
FIFO is empt y. Settin g the INTE F bit to 1 c auses an int erru pt to be
generated when the FIFOE status bit is 1. The INTEF bit should be set
only when operating the 1284 port in interrupt service mode instead of
DMA mode.
EPP
(D14) 1284 EPP mode
of operation Must be set to 1 to allow the 1284 port to operate in the EPP mode of
operation. See "IEEE 1284 EPP mode" on page 363 for information
about operating the 1284 port in EPP mode.
IBRIE
(D13) 1284 inbound
buffer ready
interrupt enable
Must be set to active high to generate an interrupt when the 1284 port
inbound buffer is available for reading. Setting the IBRIE bit to 1
cause san interrupt to be generated when the IBR status bit is 1. The
IBRIE bit should be set only when operating the 1284 port in interrupt
service mode instead of DMA mode.
IBR
(D12) 1284 inbound
buffer ready Goes active high when the inbound buffer is ready to be read by the
processor. The IBR status bit is active only when the 1284 port is
configured for operation in the ECP reverse channel mode (ECP = 1;
BIDIR = 1).
RXFDB
(D11:10) 1284 inbou nd
buffer FIFO data
available
00 – Full-word
01 – One-byte
10 – Half-word
11 – Three bytes (LENDI AN det ermin es whic h three)
Must be used in conjunction with IBR. When IBR is set, this field
identifies how many bytes are available in the inbound data register.
The RXFDB field is used only when operating the r eceive 1284 port
in interrupt service mode instead of DMA mode.
RBCC
(D09) 1284 receive
buffer close
command byte
Can be set at the same time IBR is set. The RBCC bit indicates that
the last byte in the next read of the inbound data buffer is defined as
the 1284 ECP command byte. The RBCC bit is automatically cleared
when the inbound data buffer is read.
Code
(Bit #) Definition of
code Description
Table 124: IEEE 1284 Port Control register bit definition
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RBCT
(D08) 1284 receive
buffer character
timeout
Can be set at the same time IBR is set. The RB CT bit indicates a
timeout condition has caused the inbound buffer to beco me ready.
This also implies that the RX FDB fi el d will indicate that less than
four bytes will be made available during the next read of the inbound
data buffer. The timeout condition indicates there was too much time
elapsed since the receipt of the last character. The maximum time
between characters is defined by this equation:
7,0(287
6752%(FRQILJXUDWLRQ
where:
7,0(287
is the maximum time since the receipt of the last
character.
6752%(
is the time value defined by the STROBE field.
ACK*
(D07) 1284 ACK* input
state Provides the current state of the 1284 ACK* input signal. A high-to-
low transition of the ACK* input causes the ACKI status bit to be
latched active high.
FIFOE
(D06) 1284 FIFO empty
status Indicates that the 1284 Outbound Data register and FIFO are empty
of characters . An interrupt can be generated to the CPU when FIFOE
goes active high, provided the INTEF control bit is set to 1.
OBE
(D05) 1284 outbound
buffer empty Set to 1 when the 1284 outbound data buffer is ready to accept more
data. An interrupt can be generated to the CPU when OBE goes to
active high, provided the INTEP control bit is set to 1.
ACKI
(D04) 1284 ACK*
transition
detected
Set to 1 whenever a high-to-low transition is detected on the 1284
ACK* signal input. The ACKI bit remains 1 until acknowledged. To
acknowledge the ACKI bit, write a 1 in the ACK1 bit position [D4]
in the register. An interrupt can be generated to the CPU when ACKI
goes active high, provided the INTEA control bit is set to 1.
BUSY
(D03) 1284 busy input
state Provides the current state of the 1284 BUSY input signal. The BUSY
bit is one of the four bits in the 1284 reverse channel nibble.
PE
(D02) 1284 PE input
state Provides the current state of the 1284 PE input signal. The PE bit is
one of the four bits in the 1284 reverse channel nibble.
PSELECT
(D01) 1284 PSELEC T
input state Provides the current state of the 1284 PSELECT input signal. The
PSELECT bit is one of the four bits in the 1284 reverse channel
nibble.
FAULT*
(D00) 1284 FAULT*
input state Provides the current state of the 1284 FAULT* input signal. The
FAULT* bit is one of the four bits in the 1284 reverse channel nibble.
Code
(Bit #) Definition of
code Description
Table 124: IEEE 1284 Port Control register bit definition
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IEEE 1284 Channel Data registers
The IEEE 1284 Channel Data registers are 32-bit registers used to manually
interface with the IEEE 1284 FIFOs instead of using DMA support. Each port has
its own data register. These registers are used primarily as a diagno stic tool.
When writing to the C hannel Data register, the num ber of bytes written to the
FIFO is controlled by the operand mode of the ARM proc essor. The ARM
processor can write bytes, half-words, or full words to the Channel Data register.
These writes ca n be accomplished in assembler using the se instruction s
respectively: STRB, STRH, and STR. Similarly, these writes can be accomplished in
C using these constructs respectively:
FKDU[))$
VKRUW[))$
and
LQW[))$
.
When reading from the Channel Data register, all the bytes available (as defined by
the RXFDB field) must be read with a single instruction. If only a single byte is
available, then a LDRB or
FKDU
operation can be used. The LDR or
LQW
operations can also be used to read the one byte. If only a half-word is available,
then a LD RH or
VKRUW
operation can be used. The LDR or
LQW
operations
can also be used to read the half-word. When a full word is available, the LDR or
LQW
operations must be performed.
Bits R/W Bit name Description
D31:00 W DATA Outbound channel data register
D31:08 R Reserved
D31:00 R DATA ECP mode reverse mode data
D15:08 R/W DATA EPP mode address cycle
D31:00 W DATA Outbound channel data register
D31:08 R DATA Reserved
D07:00 R/W EPP mode data cycle
D07:00 R DATA Byte mode reverse channel data
Table 125: IEEE 1284 Channel Data register bit definition
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MIC Controller Module
IEEE 1284 strobe pulse width
The width of the IEEE 1284 str obe timing (used in compatibility mode) is a
function of both the external crystal frequency and the value programmed in the
STROBE field of the IEEE 1284 Control Register.
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Table 126 sh ows sample STROBE times using an 18.432 MHz crystal:
:
IEEE 1284 external loopback mode
The LOOP bit in the Port Contr ol register puts the 1284 port in an external
loopback mode. Each external strobe action forces the outbound data to be latched
in the external inbound data path.
When configured in loopback m ode, the inbound BUSY signal is connected to the
ACKI status bit. Whenever a data byte is strobed in the external data latch, the
outbound data transfer is stalled (by virtue of the internal BUSY connection) until
the ACKI status bit is serviced. This feature allows the firmware to read each
inbound data path one byte at a time. The outbound path can be either interrupt-
or DMA-driven. The inbound data path can be either interrupt-driven or polled.
ENI mode overview
The ENI is a 16-bit port with its own data and address busses, protocol and timing.
Its purpose is to allow an external device to access the NET+50’s sy stem RAM.
Figure 49 shows an external processor talking to the NET+50's RAM through the
ENI interface.
Note:
The external processor is referred to as the client where the NET+5 0
containing the ENI interface port is referred to as the host. The ex tern al
proc es so r system (c lien t) initia tes all data tr an sf ers. The ho st r e spo nds
to the client’s commands and reads or writes the client’s data into the
NET+50 system RAM.
STROBE Equation Example value
00 5 / FXTAL 0.542 us
01 10 / FXTAL 1.08 us
10 50 / FXTAL 5.42 us
11 100 / FXTAL 10.85 us
Table 126: Sample IEEE 1284 strobe widths
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MIC Controller Module
Figure 49: ENI basic functionality
The ENI's configuration can be adjusted in many ways for the client’s conve nience .
There are four EN I mode s:
8-bit sh ared RAM. Allows the client to access 65536 bytes in the NET+50
system RAM.
16-bit shared RAM. Allows the client to access 32768 word locations.
8-bit FIFO bu s and 16-bit F IFO b us. All ow shar ed R AM acce ss wit h the
memory space being either 8K, 16K, or 32K depending on the
configuration.
Each mode has additional features that ar e configure d with the seven r egisters that
configure and control the ENI interface.
ENI h ost int erface
The ENI host mode allows an external processor to access the NET+50 as a slave
memory device. The NET+50 ENI is connected to the system bus of the external
processor, which can generate four different interrupts to the NET+50. The ENI
interrupts to the NET+50 shar e the same interrupt mask location bits as the IEEE
1284 port interrupts. Sharing these location bits is not a problem because ENI can
be configured in only one mode at a time.
When the NET+50 is configured in the ENI host mode, it can be interrupted by the
external processor through the ENI Shared register. This is the ENI interrupt,
which shares the 1284 port 3 interrupt bit. If the ENI interface uses the FIFOs, they
Data
and
addr
bus
Data
and
addr
bus
RAM
External
uP system
(client)
NET + 50
(host)
ENI
port
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NET+50/20M Hardware Reference
will interrupt the NET+50 using the same bit locations as 1284 port 1 and port 2.
The ENI bus error interrupt occurs when the external pr ocessor attempts an access
to a non-existent memory location on the NET+50’s system bus. The NET +50 also
has the ability to interrupt the external processor using the PINT1 and PINT2
signals in the ENI. These signals are covered in greater detail in the ENI host port
application note available from NetSilicon.
The ENI host interface provides the interface between the NET+50 chip and a
separate processor subsystem, and acts as a host memory device to the external
processor subsystem. The ENI host interface also provides both a shared RAM
interface module and a byte-streaming FIFO module for interprocessor
communications between the NET+50 process and the extern al process or.
Figure 50 shows the signals used when interfacing to an external processor. The
ENI u s es forty N E T +5 0 pi ns. The s e a re du al functi o n pi ns that a re sh ared w i t h t he
IEEE 1284 ports.
Note:
The P before all the ENI signal names stands for printer and is a legacy
from when the ENI was consider ed strictly a printer interface.
Figure 50: NET+50 ENI host signals
The exte r nal processo r is responsible for addressing t he ENI host int erf ac e a s a
hos t p er i p h er a l , and ac t iv a t e s t he int er face using the PCS* or PD A CK * input s . T he
Shared RAM
FIFO Exter nal CPU
(master)
NetARM ENI
host interface
(slave)
PDACK*
PDRQO*
PDRQI*
PDRQIO*
PINT1*
PINT2*
PCS*
PRW
PACK*
PA[16:0]
PDAT A[15:0]
PEN*
PBRW*
Bi-directional
transceiver
Enable
direction
Contro l and
status registers
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MIC Controller Module
NET+50 ENI host inte rface services the request and responds with PACK* when
the cy c l e i s co mp l et e .
In shared RAM mode, the ENI provides a 16-bit bi-directional data bus with 17
address bits. Under normal circumstances, seventeen address bits means that you
can address 131072 locations. Bit 16 is a special case, however, and is used to access
some of t he ENI regi st er s ; i t is not ava i l a bl e fo r memor y acc e ss. Th erefore, a
maximum of 65536 memory locations can be accessed.
The sig na l s PC S* an d PRW* a re sour c ed by the cl i e nt . Th ey i ni t ia t e t he dat a
transfer, and control the data’s dir ection. The host acknowledges receiving these
signal s by issuing PACK. If the data bus need s buffering, th e sign als PEN* and
PBR W control the buffer. PINT1* and PINT2* are interrupt outputs that allow the
host to interrupt the clie nt. PINT2* can also be config ured as an interrupt inpu t
that allows the client to interrupt the host. DRQI*, DRQO*, DRQIO, and DACK are
used when ENI is configured for the FIFO mode to facilitate DMA transfers.
Signal descriptions
PCS* ENI chip select
Provides the chip enable for the ENI interface from the external processor system.
When PCS* is driven low, the ENI interface uses the PA address bus to determine
which resource is being addressed. After the ENI interface cycle is complete, the
ENI interface asserts the PACK* signal to complete the cycle. After PACK* is
asserted active, the external processor must de-assert PCS* to complete the ENI
int er fa ce cycle.
PR W* ENI read/write
Driv en by the ex tern al proc esso r sy stem during an EN I ac cess cyc le t o ind icat e th e
data transfer direction. During normal PCS* cycles, PRW* high indicates a READ
from the ENI interface; PRW* low indicates a WRITE to the ENI interface. During
DMA cycles , PRW* high indicates a WRITE to the ENI interface; PRW* low
indicates a READ from the ENI interface.
PA[16:0] ENI addr ess bus
Requir e s 17 address sig nal s t o ident ify the resource being acce sse d. T he PA bus
must be valid while PCS* is low. During DMA cycles, the PA addres s bus is
ignored and only the FIFO data register is acce ssible.
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PA16 low identifies an access to shared RAM. PA16 high identifies
access to one of the ENI registers. See "Memory map" on page 383 for a
list of the registers available in the ENI Interface.
When DMA FIFO operat ion s ar e enabled, the PA15 input is u sed for the
DMA acknowledge input PDACK*. DMA FIFO operations are enabled
when the DMAE* bit in the ENI Control register is set to 0.
When DMA FIFO operations are enabled, the PA14 output is used for
the active low outbound FIFO DMA ready output PDRQO*. The
PDRQO* signal is routed only through PA14 when both DMAE* and
DMAE2 in t he ENI Contr o l r egist er ar e set to 0. Wh en DMAE* is set low
and DMAE2 is set high, an active high version of PDRQO is routed out
the active high PINT2 pin instead. The PDRQO and PDRQI signals are
internally ORed together before driving the PINT2 pin.
When DMA FIFO operations are enabled, the PA13 output is used for
the active low inbound FIFO DMA ready output PDRQI*. The PDRQI*
signal is routed only through PA13 when both DMAE* and DMAE2 in
the ENI Control register are set to 0. When DMAE* is set low and
DMAE2 is set high, an active high version of PDRQI is routed out the
active high PINT2 pin instead. The PDRQO and PDRQI signals are
internally ORed together before driving the PINT2 pin.
PDACK* /PA15 ENI DMA a cknowledge
When DMA FIFO operations are enabled, the PA15 input is used for the DMA
acknowledge input PDAC K*. DMA FIFO operations are enabled when the
DMAE* bit in the ENI Control register is set to 0.
The PDACK* input indicates a DMA cycle is in progress. Only the FIFO data
register is accessed during a DMA cycle. During DMA cycles, the PCS* signal must
not be a sse r t ed. During DM A cy c l es, the PA bus (oth er t ha n PA15) is ignored .
During DMA cycles, the PR W* defines the data transfer direction. PR W* high
indicates a FIFO write operation; PRW* low indicates a FIFO read operation.
PDRQO */ PDR QO/PA14 ENI outboun d FI FO DMA r equest
When DMA FIFO operations are enabled, the PA14 output is us ed fo r the active
low outbound FIFO DMA ready output PDRQO*. The PDRQO* signal is only
routed through PA14 when both DMAE* and DMAE2 in the ENI control register
are set to 0. When DMAE* is set low and DMAE2 is set high, an active high version
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MIC Controller Module
of PDRQO is routed out the active high PINT2 pin instead. The PDRQO and
PDRQI signals are internally ORed together before driving the PINT2 pin.
The PDRQO*/PDRQO signal is driven active to indicate the outbound FIFO has
data available for reading. The PDRQO*/PDRQI signal is only driven active when
the outbound FIFO is not empty and the EDRDBUFRDY bit is set active high in the
ENI FIFO mode mask/status register. The FIFO m ode mask/status register is
available in the ENI address space.
PDRQI*/PDRQI/PA13 ENI Inbound FIFO DMA Request
When DMA FIFO operations are enabled, the PA13 output is us ed fo r the active
low inbound FIFO DMA ready output PDRQI*. The PDRQI* signal is only routed
through PA13 when both DMAE* and DMAE2 in the ENI Control register are set
to 0. When DMAE* is set low and DMAE2 is set high, an active high version of
PDRQI is routed out the active high PINT2 pin instead. The PDRQO and PDRQI
signals are internally “ORed” together before driving the PINT2 pin.
The PDRQI*/PDRQI signal is driven active to indicate that the inbound FIFO has
room available for writing. The PDRQI*/PDRQI signal is only driven active when
the inbound FIFO is not full and the EDWRBUFEMP bit is set active high in the
ENI FIFO mode mask/status register. The FIFO m ode mask/status register is
available in the ENI address space.
PDATA[15:0] ENI Data Bus
The ENI interface supports a 16-bit data bus. The ENI interface can be configured
to operate in 16-bit or 8-bit data mode. In 16-bit mode, all data bits are used; in 8-
bit mode only PDATA[15:8] ar e used.
In 8-bit mode, PDATA[7:0] can be used as general-purpose inputs.
PACK* ENI Acknowle dge
Driven by the ENI interface in response to an active low PCS* signal. The PACK*
signal indicates the requested ENI bus cycle is complete.
The PACK* si g n al ca n be co nf i g u red to op erate as an ac t i v e l ow ac k no wl edge
(ACK) indicator or an active high ready (RDY) indicator. This control is provided
by the EPACK* bit in the ENI Control register. The EPACK* bit can be
automatica lly initialized to its proper state upon reset by including or not
including a pulldown resistor on the A1 signal (see "MIC module hardware
initialization" on page 333). Figure 90, "ENI Shared RAM and Register Cycle
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NET+50/20M Hardware Reference
timing," on page 464 shows the differ ence between the ACK and RDY
configuration for the PACK* signal.
The PACK* signal can be configured to operate as a TTL or open-drain signal. The
TTL configura tion for the PACK * sig nal is provided by the WR_OC bit in the ENI
Control r egister. The WR_OC bit can be automatically initialized to its proper state
upon reset by including or not including a pulldown r esistor on the A6 signal (see
"MIC module hardware initialization" on page 333).
PINT1* ENI Interrupt 1
Driven active low to indicate an interrupt condition to the external ENI processor.
An interrupt condition is established when the ARM processor sets the STSINT or
VDAINT bits in the ENI Shared r egister. An interrupt condition is also determined
by the FIFO status and the FIFO interrupt enable bits in the FIFO mode mask/
status register.
The PINT1* signal is further qualified by the EHWINT and SINTP2 bits in the ENI
Shared register. The ENI Shar ed r egister is available in the ENI address space. The
EHWINT provides global interrupt enable/disable control. The SINTP2 bit
controls whether the interrupt is driven out the PINT1* pin or the PINT2* pin. The
PINT1* is driven active low only when an interrupt condition is pending, the
EHWINT bit is set to 1, and the SINTP2 bit is set to 0.
See Figure 53, "PINT1*/PINT2* interrupt pins," on page 390.
PINT2* ENI Interrupt 2
Driven active low to indicate an interrupt condition to the external ENI processor.
An interrupt condition is established when the ARM processor sets the STSINT or
VDAINT bits in the ENI Shared register. An interrupt condition is also established
based upon the FIFO status and the FIFO interrupt enable bits in the FIFO mode
mask/status register.
The PINT2* signal is further qualified by the EHWINT and SINTP2 bits in the ENI
shared register. The ENI Shared regist er is av ailable in the ENI address space. The
EHWINT provides global interrupt enable/disable control. The SINTP2 bit
controls whether the interrupt is driven out the PINT1* pin or the PINT2* pin. The
PINT2* is driven active low only when an interrupt condition is pending, the
EHWINT bit is set to 1, and the SINTP2 bit is set to 1.
The PINT2* signal can also generate an interrupt from the external ENI processor
to the ARM processor. The PINT2* pin becomes an input when the DINT2* bit is
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MIC Controller Module
set to 0 in the ENI Control register. The DINT2* bit can automatically be initialized
to its proper state on reset by including or not including a pulldown resistor on the
A5 signal (see "MIC module hardware initialization" on page 333). When DINT2*
is configured as in the pulsed interrupt input, the low-to-high transition on the
PINT2* input causes an interrupt condition to be established to the ARM
processor. The low-to-high transition on the PINT2* input causes the INTIOF bit to
be set in the Shared register for the ARM processor.
The PI N T 2 si g n al ca n also provide an acti v e hi g h D MA reque st wh en the ENI
interface is configured to operate in FIFO mode and the DMAE2 bit is set in the
ENI Control register. In this condition, the inbound and outbound DMA ready
signals are logically “ORed” together and routed through the PINT2 pin as an
active high DMA Request. When the DMAE2 bit is set, the PA14 and PA13 signals
are no longer used as DM A request outputs and return t o their shared RAM
address function, exten ding the amount of addressabl e shared RAM to 32Kb in
FIFO DMA mode.
See Figure 53, "PINT1*/PINT2* interrupt pins," on page 390.
PBRW* ENI Data Buffer Read/Write
An output used to control the data direction pin for an external data bus
transceiver. Some applications require a data bus buffer between the NET+50 chip
and the external ENI processor system. PBRW* high indicates a data transfer from
the NET+50 chip to the ENI processor; PBR W* low indicates a data transfer fr om
the ENI processor to the NET+50 chip.
The ENI interface pr ovides a clock synchronizer function for the PACK* output.
The PBRW* pin can be reconfigured as a clock input for the PACK* synchr onizer.
See "ENI Control register and bit definitions" on page 408 for more information.
PEN* ENI Data Buffer Enable
An output that contr ols the output enable pin for an external data bus transceiver.
Some applications require a data bus buff er between the NET+50 chip and the
external ENI processor system . PEN* low indicates that a data transfe r between
the NET+5 0 chip an d the ex ternal ENI processor is in progress.
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ENI shared RAM mode
When the ENI interface is configur ed for ENI host shared RAM mode, the NET+50
chip provides up to 64 Kbytes of shared RAM between the NET+50 chip and an
external device. Figure 51 shows the hardware required for the ENI shared RAM
configuration. The ENI control state machine interprets the control signals for the
configured mode to determ ine when the external CPU wants to access the shared
RAM interface.
When t he ENI shared RAM stat e ma chi ne de ter min es t hat t he e xter nal CP U wa nts
to access shared RAM, the state machine requests ownership of the BBus. When
the BBus arbiter grants the BBus to the ENI contr oller module, the state machine
translates the address provided by the external ENI device to the physical address
for the shared RAM (using values in the ENI Shared RAM Address r egister). The
stat e machine us es the tran sl a t ed ad dres s t o ac cess the p roper d ata i n externa l
RAM (either read or write). When the bus controller module completes the
external RAM cycle, the control state machine signals the external CPU to indicate
that the cycle is complete (providing read data during read cycles).
Figure 51: ENI shared RAM block diagram
The ENI shared RAM occupies a physical block within external NET+50 chip
sys tem R AM . T he ENI co nt rol le r ac ce sses the sha red RAM th rough th e EN I
interface. The NET+50 chip firmware directly accesses the shared RAM within its
system RAM.
ENI s hared RAM
state machine
Data buffers Control buf f ers Addr ess i nputs
Addr ess transl at ion
BBus
Config
block
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MIC Controller Module
Memory map
The ENI interface uses 17 address bits to access the shared RAM and various
control registers. Table 127 shows the address map from the perspective of the
external ENI.
Shared RAM
The shared RAM is accessible from the ENI interface when the ENI controller is
configured in ENI shared RAM or ENI FIFO mode. A total of 64 Kbytes of shared
RAM is nominally provided. When the interface is configured in FIFO mode and
the ENI FIFO mode DMA interface is enabled in the ENI Control r egister, a
maximum of 8 Kbytes of shared RAM is available (PA15, PA14, and PA13 are lost
to the DMA control signals ).
Each time the external ENI interface attempts to access shared RAM, the PACK*
signal is delayed while the NET+50 ENI shared RAM state machine arbitrates with
the internal NET+ 50 bus clients (CPU and DMA) for access to external memory.
After gaining access to the internal NET+ 50 BBus, the ENI shared RAM state
machine executes a memory read or memory write cycle (depending on the state
of the PRW* input) to a memory location defined by the BASE field located in the
ENI S hare d RAM A ddres s r egiste r (see "ENI Sh ar ed RAM Ad dr ess r egist er and bit
definitions" on page 415).
After the NET+50 memory subsystem completes the memory transfer for the ENI
shared RAM state machine, the PACK* signal is issued active to the external ENI
interface along with read data during a read cycle. Therefore, the length of every
shared RAM access cycle from the external ENI interface can vary. The amount of
time it takes to access shared RAM from the external ENI interface depends on
Address range A16 A2 A1 A0 Peripheral
00000 - 0FFFF 0 A2 A1 A0 Shared RAM
10000 1000Shared register
10001 1001Clear interrupts (write only)
10002 101XFIFO mode data register
10004 1100FIFO mode mask/status
Table 127: ENI in terface address m ap
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how the NET+50 memory controller is configured, the speed of various memory
devices, DMA activity, bursting configurations, and so on. See Figure 90, "ENI
Shared RAM and Register Cycl e timing," on page 464 for a detailed timing
diagram of a shared RAM transfer.
This sequence of ev en ts mak e s up an ENI shared RAM transfe r:
1The print er sends a c hip selec t (PCS*), a n addr ess (PA16:0), and a r e ad/writ e
(PRW-) signal to the NET+50.
2The NET+50 drives PACK low, enables a bi-directional data transceiver by
driving PEN low and determines the direction of that data with PBRW.
(PBRW high is data from the NET+50 to the printer)
3In the background (no P signals change while this is being done), the
NET+50 shared RAM state machine takes the address provided by the
printer and adds it to an offset (previously defined in a register) to access a
word in the DRAM. When that wo rd (copied to a shared RAM state
machine register) is ready to be taken by the printer, the NET+50 drives the
PA CK- sign al high.
4When PACK- goes high, the printer reads the word and drives PCS high.
5After PCS goes high, the NET+50 drives PEN high, ending the cycle.
Shared register
The NET+50 chip supports an 8-bit shared r egister that controls the personality of
signals and provides the NET+50 chip with the means to interrupt the ENI. The
NET+50 chip accesses this register through the ENI controller configuration space.
The ENI itself accesses this register through the ENI interface.
The shared register is accessible only when the ENI contr oller is configured to
operate in ENI shared RAM or ENI FIFO mode.
The ENI interface accesses the shared register by setting PA16 high. PA16 low
acce sses the sh ared R AM. When t he ENI is configur ed to op erate in 8-bit mode , the
shared register is accessed using PDATA 15 through PDATA 8. When the ENI is
configured to operate in 16-bit mode, the shared register is accessed using
PDATA7 through PDATA0.
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MIC Controller Module
The VDAINT and STSINT bits in the shared register are set to 0 with a hardware or
software reset from the local CPU. The other bits are set to 0 only by a hardware
reset fr om the ENI interface reset (PRESET*).
The shared register can be configured to operate in either NORMAL mode or PSIO
mode. The mode is configured using the PSIO bit in the ENI control register.
Table 128 shows the two poss ible view s fo r the sh ared r e g i ster from the exte r na l
ENI interface perspective. The register layout from the local CPU perspective
always appears in NORMAL m ode.
Figure 52 shows ho w the ENI shared r egister c an be writ t en. Bot h sides can re ad
all eight bits.
Figure 52: Writ ing to the ENI shared register
Data bit Normal mode PSIO mode
D7 RSTIO Reserved
D6 INTIOF Reserved
D5 EMMINT EMMINT
D4 EHWINT RSTIO
D3 SINTP2 CLRINT
D2 VDAINT EHWINT
D1 STSINT STSINT
D0 CLRINT INTIOF
Table 128: Shared regist er layout (ENI interface perspective onl y)
ENI Addr 10000 D7
ENI Addr 10000 D6
ENI Addr 10000 D4
ENI Addr 100001
ENI Addr 10000 D5
ENI Addr 10000 D3
ENI Addr 10000 D0
D6 INT I OF
D5 E MM I NT
D0 CL R INT
D2 V DAINT
D1 ST SINT
D3 SINT P 2
D4 E H WI NT
D7 R ST IO
(clear only)
(clear only ) FFA00030 D7 (INTP*)
FFA0003C D2
FFA0003C D1
ENI shared register
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Unlike acce ssing shar ed RAM, the Sha red r egi st er ac cess timing is alway s t he
same when accessing the Shared register from the external ENI interface. Because
the ENI hardware does not need to arbitrate with internal resources when
accessing the shared register, the shared register access timing is fast and
consistent.
ENI Shared register and bit definitions
&38 !))$&
(1, !(1,VKDUHG5 HJLVWHU VKRZQ LQ125 0$/PRG H
Code
(Bit #) Definition of
code Description
RSTIO
(D07) EN I reset
NET+50
processor
Only the external ENI interf ace can modify the RSTIO bit; the
NET+50 CPU cannot modify this bit.
The external ENI interface can set the RSTIO bit to 1 to reset the
NET+50 processor and peripherals. The processor and peripherals
remain in rese t while RST IO is set t o 1. RSTIO m ust be set ba ck to 0
to enable the NET+50 CPU to reboot.
RSTIO is used by the external interface to reset the internal NET+50
processor. The RSTIO bit does not reset either the ENI or MEM
modules within the NET+50 architecture but does reset all other
internal NET+50 modules.
The external ENI interface reads a 1 in the RST IO bit position
whenever the CLRINT bi t in this regist er is also set.
Table 129: ENI Shared register bit de finition
15 14 13 12 11 10 987 65432 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset: RSTIO INTIOF EHWINT SINTP2 VDAINT
0
0
00
0
EMMINT STSINT CLRINT
00
0
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MIC Controller Module
INTIOF
(D06)
ENI interrupt
NET+50 processor Only the external ENI interface can modify the INTIOF bit. The
NET+50 CPU cannot modify INTIOF directly.
The external ENI interf ace can set the INTIOF bit to 1 to generate an
interrupt to the NET+50 CPU. When the INTIOF bit is set to 1, the
INTP* bit in the ENI Control register is set to active low. The
IRQEN* bit in the ENI Control register can be used to allow the
INTP* status condition to generate an interrupt to the NET+50 CPU.
Both the INTP* and INTIOF bits are returned to their i na ctive state
when a 1 is written to the INTP* bit position in the ENI Control
register by the NET+50 processor. The ENI INTIOF interrupt is
routed to the GEN module Interrupt Controller through the ENI Port
3 interrupt (see "MIC module interrupts" on page 333).
EMMINT
(D05) ENI spar e
resource bit Only the external ENI interf ace can modif y the EMMINT bit. The
NET+50 CPU cannot modify EMMINT directly.
The EMMINT bit controls no hardware within the NET+50. It can be
used as a gener al-purpose control/status bit that can be c ontrolled by
the external ENI interface only.
EHWINT
(D04) ENI enable
hardware
interrupt
Only the external ENI interface can modif y the EHWINT bit. The
NET+50 CPU cannot modify EHWINT directly.
The EHWINT bit must be set to 1 by the external ENI interface to
allow either the PINT1* or PINT2* signals to generate an active low
interrupt to that interf ace. Sources of int err upt for the exter nal ENI
interface include the S TSIN T and VDAINT bits in the ENI Shar ed
register, the RDBUFRDY* and WRBUFE MP* bits in the FIFO
mask/status register, and a write by the NET+50 CPU to the pulsed
interrupt register.
SINTP2
(D03) ENI PINT1*/
PINT2* interrupt
selection
0 – PINT1*
1 – PINT2*
Only the ext ernal E NI i nte rf ace can modify t he SINT P 2 bit. The
NET+50 CPU cannot modify SINTP2 directly.
The SINTP2 bit is control led by the extern al EN I inter face to
determine which signal — PINT1* or PINT2* — is used for
interr upts to t he exte rnal EN I in terfa ce.
See Figure 53, "PINT1*/PINT2* interrupt pins," on page 390 for
more in f ormat io n.
Code
(Bit #) Definition of
code Description
Table 129: ENI Shared register bit de finition
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Clear interrupts
The Clear Interrupts Command register is accessible from the ENI interface
whenev er the ENI controller is configured to operate in ENI shared RAM or ENI
FIFO modes. The PA2 and PA1 address bits do not care when the ENI controller is
configured in ENI shared RAM mode.
VDAINT
(D02) NET+50 interrupt
to external ENI
interface
Only the internal ARM processor can modify the VDAINT bit. The
external ENI interface cannot modify VDAINT directly.
The VDAINT bit is set by the NET+50 CPU to send an interrupt to
the external ENI interface using either PINT1* or PINT2*, depending
on the value defined in SINTP2. The EHWINT bit must also be set to
active high for VDAINT to generate an interrupt to the external ENI
interface. The V DAINT interr upt condition is cleared by the ext ernal
ENI interface by setting the CLRINT bit to 1, then back to 0. The
VDAINT can also be acknowledged by having the external ENI
interface write to the cl ear interr upts memory -mapped addres s
location defined in "Memory map" on page 383.
STSINT
(D01) NET+50 interrupt
to ENI Only the internal ARM processor can modify the STSI NT bit. The
external ENI interface cannot modify STSINT directl y .
The ST SINT bi t is set by the NET +50 CPU to send a n inter rupt to the
external ENI interface using either PINT1* or PINT2*, depending on
the value defined in SINTP2. The EHWINT bit must also be set to
active high for STSINT to generate an interrupt to the external ENI
interface. The STSINT interrupt condition is cleared by the external
ENI interface by setting the CLRINT bit to 1, then back to 0. The
STSINT can also be acknowledged by having the external ENI
interface write to the cl ear interr upts memory -mapped addres s
location defined in "Memory map" on page 383.
CLRINT
(D00) ENI clear
interrupt from
NET+50
Only the external ENI interface can modif y the CLRINT bit. The
NET+50 CPU cannot modify CLRINT directly.
The CLRINT bit can be used by the external ENI interface to clear the
VDAINT and STSINT interrupt conditions. The CLRINT bit must be
set to 1, then back to 0 to clear these interrupt conditions.
Code
(Bit #) Definition of
code Description
Table 129: ENI Shared register bit de finition
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MIC Controller Module
When writing to the clear interrupt location from the external ENI interface , the
access t i ming is alw a ys the sa me — un l i k e ac c essing shared R AM ,. Be ca u se the
ENI hardware does not need to arbitrate with internal resources when writing to
the clear interrupt location, the access timing is fast and consistent.
Address interrupts
When the KYOINT bit is set in the ENI Control register, 2 additional comm and
registers are available in the ENI interface address map. One address sets an
interrupt condition from the ENI interface to the ARM processor; the other address
clears an interrupt condition from the ARM processor to the ENI interface. These
two addr ess locations occupy the uppermost two words of shared RAM.
The ENI interface uses 17 address bits to access the shared RAM and various
control registers. Table 130 shows the address map as defined from the perspective
of the exter nal E NI.
Address range A16 A2 A1 A0 Peripheral
00000 - 0FFFB 0 XXXShared RAM
0FFFC - 0FFFD010XClear interrupt to ENI
0FFFE - 0FFFF 011XSet interrupt from ENI
10000 1000Shared register
10001 1001Clear interrupts (write only)
10002 101XFIFO mode data register
10004 1100FIFO mode mask/status
Table 130: ENI in terface address m ap
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Figure 53: PINT1* /PINT2* interrupt pins
PINT1* Pin
SR-D4 EHWINT (1 = enable)
SR-D3 SINTP2 (0 = PINT1*)
SR-D2 VDAINT
SR-D1 STSIN T
I_OC A4 or 30-D4
(0= TTL)
(1= Open collector)
PLUINT * A0 or 30-D0 (0= Pulsed Int)
34 - Any Data
EIWRBUFRDY 10004-D10 (1=EN)
EIRDBUFRDY 10004-D11 (1=EN)
RDBUFRDY* 10004-D13
WRBUFEMP* 10004-D12
FFB00038-D19 (Int ENI Port-3)
PIN T2* Pin
DMAE2 30-12 (1=DMA)
DINT2* A5 or 30-5 (1= Int out)
(1=DMA)
IRQEN* 30-D2 (0=EN)
INTP* 30-D7
DREQI
ERXDMA* 0 0-D30 (0=EN)
DREQO
ETXDMA* 00- D22 (0 =EN)
DREQIO
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MIC Controller Module
ENI bus error interrupts
Figure 54shows the ENI bus error (BEI) interrupt pr ocess.
Figure 54: ENI bus error interrupt process
If the shared RAM address register
))$
is improperly configured, the ENI
device may try to access a non-existent memory location in the ENI’s RAM . If this
happens, the BEI bit will go high. The BEI bit must be cleared by writing a 1 to this
bit location. If this bit is enabled by the EBEI bit in the General Contr ol register, it
can generate an interrupt. (See "General Control register and bit definitions" on
page 401 and "General Status register and bit definitions" on page 405 for more
information about these bits.)
ENI FIFO mode module
The ENI host FIFO mode interface provides a FIFO interface between the NET+50
chip and some external CPU system. This register interface provides a streaming
bi-directional data transfer. DMA channels 3 and 4 ar e used by the NET+50 chip to
move the data between the register interface and external RAM.
DMA Channel 4 moves data from external RAM to the register interface. DMA
channel 3 moves data from the register interface to external RAM.
Figure 55 provides a view of the hardware required to support FIFO mode. The
FIFO mode control state machine is responsible for running the register interface.
BEI 04-D24
EBEI 00-D24 (1= EN)
FFB 00038-D18 (ENI BE Intr, Port-4)
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Figure 55: ENI FIFO mode block diagram
The FIFO mode interface has two 32-byte FIFOs. The DMA controllers work to
keep the output FIFO full and the input FIFO em pty.
The FIFO mode operates in a byte/word streaming manner. Data from buffers is
moved between external RAM and the FIFO mode peripheral interface
automatically, using DMA operations. In the outbound direction, the transmit
buffers can be of any size (including an odd number of bytes).
In the inbound direction, the receive buffer size must be an integral of four bytes.
This restriction is imposed to keep the receive FIFOs working ef ficiently. Without
this restriction, residual bytes can remain in the FIFO and stall the comp letion of
the recei ve d a ta bu ffer.
Figure 56 shows two NET+ARM sys te ms; on e is con fig ured in ENI FIFO mode
and is controlled by the other’s NET+ARM memo ry bus signa l.
FIFO mode
control
state
machine
Config
module
BBus
32-byte
FIFO 32-byte
FIFO
Data buf fer s Control
buffers
DMA
controller
module
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MIC Controller Module
Figure 56: Sample application
FIFO Data register
The FIFO Data register is accessible only from the ENI interface when the ENI
controller is configur ed to operate in ENI FIFO mode.
The FIFO Data register passes data between the NET+50 chip and the ENI
contr o lle r. The RDBUFRDY* a nd WRBUFEMP* flags in t he Mask/S tatu s register
are used to identify the current state of the ENI FIFO mode Data register. The FIFO
Dat a regist er mu st b e wr i t ten only when the WRBUF EM P* status bi t in th e F I FO
mask/status register is active low. The FIFO Data register can be read only when
the RDBUFRDY * sta tus bit in the FIFO Mask/Status register is active low.
The Data register can be memory-mapped using the PCS* select input. The
memory-mapped data register can be used in polled or interrupt-driven
DRAM
DRAM
Data
bus
NetARM
DMA
ch-4
DMA
ch-3
TX
FIFO RX
FIFO
FIFO mode
ENI s ection
ENI mod
circuit
PACK
BCLK
TA
CS x
R/W
A[17:1]
Bidirectional
transceiver
(245)
D[31:16] PD[15:0]
PBRW(dir)
PEN
DMA
ch-4
DMA
ch-3
(host)
Data
bus
NetARM
(client)
PortC0
PortB6
PortA6
PINT*
PDRQ0*
PDRQ1*
data reg
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NET+50/20M Hardware Reference
applications. The memory-mapped data register can also be used in DMA
applications that use the dual address, or memory-to-memory, DMA operations.
The dual addr ess (or memory-to-memory) method requires two bus cycles per
DMA operatio n: one bus cy cl e to acce ss the data register an d an ot h er b us cy cl e to
access the RAM on the controller board.
The FIFO can be configured to transport data through DMA channels, using three
signals to communicate with an external device: DREQO, DREQI, and PDACK.
These signals can be configured to act in conjunction with either 8K or 32K shar ed
RAM. Figure 57 shows the config uration from inside NET+50.
Figure 57: ENI FIFO — Transporting data through DMA channels
The data register can also be DMA-mapped using the PDACK* input. When using
the PDACK* input, all ENI address inputs are ignored and the sense of PRW* is
PINT2* Pin
DMAE2 30-12 (1=DMA)
DREQI
ERXDMA* 00-D 30 (0=EN)
DREQO
ETXDMA* 00-D22 (0=EN)
DREQIO
Outgoing Interrupts
PA14/DREQO Pin
PA13/DREQI Pin
PA15/PDACK Pin
DMAE* A3 , 30-D 3 (0= DMA)
FIFO State
Machine
Shared RAM State
Machine
PA15
PDACK
PA13
PA14
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MIC Controller Module
reversed. For DMA operations, PRW* high writes to the Data register (read from
controller memory) and PR W* low reads from the Data register (write to controller
memory). The DMA-mapped interface is used in single address, or fly-by, DMA
operations. The single addr ess method requires a single bus cycle per DMA
operation. The memory is accessed (read or write) on the controller. During DMA
memory accesses, the PDACK* signal is asserted to the ENI interface. During
DMA cycles, a PRW* high signal instructs the ENI interface to accept FIFO data
from the controller; a PR W* low signal instructs the ENI interface to provide FIFO
data to the controller.
The FIFO Data register can be configured using an 8- or 16-bit interface. When
configured for 8-bit operation, only the upper eight data bits — PDATA(15:8) —
are used.
When accessing the FIFO Data r egister from the external ENI interface, the access
timin g is al wa y s th e same — unl ik e access i n g sh ared R AM . Be ca u s e th e E NI
hardware does not need to arbitrate with internal resources when accessing the
FIFO Data register, the access timing for this data register is fast and consistent.
FIFO Mask/Status register and bit definition
The FIFO Mask/Status register is accessible only from the ENI interface when the
ENI controller is configured to operate in ENI FIFO mode.
The FIFO Mask/S t atu s regist er su ppor ts t he dat a FIF O mode tra nsf er mec h an ism
between the NET+50 chip and the ENI controller. The Mask/Status register can be
written and read by the ENI controller. All bits are reset to their inactive state on
powerup RESET.
When writing to the clear interrupt location from the external ENI interface , the
access ti ming is always the s ame — unlike a ccessing shar ed RAM. Because the ENI
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset: D ata in terface
0
R/W
ENI = > 1 0002
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NET+50/20M Hardware Reference
hardware does not need to arbitrate with internal resources when writing to the
clear interrupt location, the access timing is fast and consistent.
Code
(Bit #) Definition of
code Description
RDBUFRDY*
(D13) FIF O read buf fe r
ready
0 – Read Data Regist er is ready
1 – Read Da ta Re g ist er i s em pty
The RDBUFRD Y* status bit is active l ow when the FIFO has
data available for the external ENI interf ace for reading. The
external ENI interface must not read from the FIFO Data register
unless the RDBUFRDY * status bit is active low.
WRBUFEMP*
(D12) FIFO write buffer
empty
0 – Write Data Register is empty
1 – Write Data Register is full
The WRBUFEMP* status bit is active low when the FIFO has
available room for the external ENI interface to write a new data
word. The external ENI interface must not write to the FIFO data
register unless the WRBUFEMP* sta tus bit is active low.
EDRDBUFRD
Y
(D11)
Enable DMA
read buff er re ad y
0 – Mask read buffer ready DMA requests
1 – Enable read buffer ready DMA
The EDRDBUFRDY bit can be set by the external ENI interface
to enable an outbound FIF O DMA request to the external ENI
interface. The outbound DMA request is active when the
RDBUFRDY* status bit is active low. The outbound DMA
request signal is routed out either PA14 or PINT2, depending on
the settings of the DMAE* and DMAE2 fields in the ENI
Control register.
Table 131: FIFO Mask/ Status register bit definition
15 14 13 12 11 10 987
654
321 0
Reset: OWM
0
R/W
0
R
IWMEIWRBIFEMPRDBUFRDY* WRBUFEMP EIWRBUFEMP
EDRDBUFRDY EDWRBUFEMP
0
RI
RI
R0
R/W 0
R/W 0
R/W
0
R/W
ENI = > 1 004
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MIC Controller Module
EDWRBUFEM
P
(D10)
Enable DMA
write buffer
empty
0 – Mask write buffer empty DMA requests
1 – Enable write buff er empt y DMA
The EDWRU FEMP bit can be se t by the ext ernal ENI i nter fac e
to enable an inbound FIF O DMA request to the external ENI
interface. The inbound DMA request is active whenever the
WRBUFEMP* status bit is active low. The inbound DMA
request signal is routed out either PA13 or PINT2, depending on
the settings of the DMAE* and DMAE2 fields in the ENI
Control register.
EIRDBUFRDY
(D09) Enable read
buffer ready
interrupt
0 – Mask read buffer ready interrupt requests
1 – Enable read buffer ready interrupts
The EIRDBUF RDY bit can be set by the exter nal ENI interf ace
to enable an interrupt request to the external ENI int erf ace. The
int errupt req ue st is ac t iv e wh en th e RDBUFR DY* st atu s bit is
active low. The interrupt request signal is routed out either
PINT1* or PINT2*, depending on the setting of the SINTP2
field in the Shared re gist er.
EIWRBUFEMP
(D08) Enable write
buffer empty
interrupt
0 – Mask write buffer empty interrupt requests
1 – Enable write buff er empt y interrupts
Can be set by the external ENI interface to enable an interrupt
request to that interface. The interrupt request is active whenever
the W R BUFE MP* s tat us b it is a ctiv e lo w. T he i nter rup t r eque st
signal is routed out either PINT1* or PINT2*, depending on the
setting of the SINTP2 field in the Shared register.
OWM
(D07:06) Outbound
watermark Controls the watermark configured for the outbound FIFO
determining when the RDBUF RDY* signal becomes active low.
This results in either an int err upt or a DMA request.
00 — One operand; the RDBUFRDY* signal will be active
when at least one operand is available for reading from the
outbound FIFO.
01 — Half full; the RDBUFRDY* signal will be active
when the outbound FIFO contains at least 16 bytes of read
data.
10 — Full ; th e RDBUFR DY* si g na l wi ll be active o nly
when the outbound FIFO contains 32 bytes of read data.
Code
(Bit #) Definition of
code Description
Table 131: FIFO Mask/ Status register bit definition
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FIFO receiver interrupts
The FIFO receiver can generate interrupts if the receive buffer is either ready or
half full. Figure 58 shows the receive FIFO interrupt process:
Figure 58: ENI receive FIFO interrupt process
The FIFO mode receive register ready (RXREGR) bit gets its information from the
r eceive FIF O sta t e mac hi n e, and is asse r t ed wh en ev e r th ere is d ata that th e
NET+50 can read in the r eceive FIFO. This bit is cleared automatically when the
FIFO is read. If this bit is enabled by the ERXREG bit in the General Control
IWM
(D05:04) Inbound
watermark Controls the watermark configured for the inbound FIFO
determining when the WRBUFEMP* signal becomes active low.
This results in either an int err upt or a DMA request.
00 — One operand; the WRBUFEMP* signal will be active
when at least one operand can be written to the inbound
FIFO.
01 — Half empty; the WRBUFEMP* signal will be active
when the in bound FIFO can accept at least 16 byt es of write
data.
10 — Empty; the WRBUFEMP* signal will be active only
when the inbound FIFO can accept 32 bytes of write data.
Code
(Bit #) Definition of
code Description
Table 131: FIFO Mask/ Status register bit definition
ERXREG 00-D27 (1=EN)
RXREGR 04-D27 FFB00038-D21 (ENI RX FIFO Intr, Port-1)
ERXFIFOH 00-D26 (1=EN)
RXFIFOH 04-D26
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MIC Controller Module
register, it can generate an interrupt. (See "General Control register and bit
definitions" on page 401 and "General Status register and bit definitions" on page
405 for more information about these bits.)
The FIFO mode receive register half full (RXFIFOH) bit gets its information from
the receive FIFO state machine, and is asserted when the receive FIFO is half full.
This bit is cleared when enough data has been read from the FIFO so the FIFO is
less than half full. If this bit is enabled by the ERFIFOH bit in the General Control
register, it can generate an interrupt. (See "General Control register and bit
definitions" on page 401 and "General Status register and bit definitions" on page
405 for more information about these bits.)
FIFO transmitter interrupts
The FIFO transmitter can generate interrupts if the transmit buf fer is either ready
or half full. Figure 59 shows the transmit FIFO inte rru p t process:
Figure 59: ENI transmit FIFO interrupt process
The FIFO mode transmit register r eady (TXREGE) bit gets its information from the
transmit FIFO state machine, and is asserted when the transmit FIFO bit is empty.
This bit is automatically cleared when data is placed in the FIFO. If this bit is
enabled by the ETXREG bit in the General Control register, it can generate an
interrupt. (See "General Control register and bit definitions" on page 401 and
"General Status register and bit definitions" on page 405 for more information
about these bits.)
The FIFO mode transmit register half full (TXFIFOH) bit gets its information from
the transmit FIFO state machine, and is asserted when the transmit FIFO is half
empty. This bit is cleared when enough data has been placed in the FIFO so the
FIFO is mor e than half full. If this bit is enabled by the ETFIFOH bit in the General
TXREGE 04-D19
ETX REG 00-D19 (1= EN)
TX FIFOH 04-D1 8
ETFIFOH 00-D18 (1= EN)
ETFIFOH 00-D18 (1= EN)
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Control register, it can generate an interrupt. (See "General Control register and bit
definitions" on page 401 and "General Status register and bit definitions" on page
405 for more information about these bits.)
ENI mode registers
Table 132 shows the r e g ist e rs that co n trol the ENI interfa ce .
General Control register and bit definitions
The General Control register is a 32-bit register containing control bits that affect
the entire ENI controller m odule.
Address Register
FFA0 0000 General Control register
FFA0 0004 General Status register
FFA0 0008 FIFO mode FIFO Data register
FFA0 0030 ENI Control register
FFA0 0034 ENI Pulsed Interrupt register
FFA0 0038 ENI Shared RAM Address register
FFA0 003C ENI Shared register
Table 132: ENI controller configuration registers
EXT
15 14 13 12 11 10 987
65 4
3210
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset
:
Reset
:
ERXDMA
ERX EXTDMA
0
R/W 0
R/W
0
R/W
ETXREG ETFIFOH
0
RW 0
RW
ERFIFOHERXREG
0
R/W
0
R/W
0
R/W
BTE ENIDIAG
0
R/W 0
RADDR22
R/W
0
R/W
0
R/W
ENI mode
ADDR21
R/W ADDR20
R/W
EBEI
Addres s = FF80 0000
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MIC Controller Module
Code
(Bit #) Definition of
code Description
ERX
(D31) Ena ble rece ive
FIFO 0 – Disables inbound data flow and resets the FIFO
1 – Enables inbound data flow
Must be set to active high to allow data to be received through the
FIFO interface. The ERX bit ca n be used to reset the receive side
FIFO. In general, the ERX bit should be set once on device open.
ERXDMA
(D30)
Enable receive
FIFO DMA 0 – Disables inbound DMA data request (use to stall receiver)
1 – Enables inbound DMA data request
Must be set to active high to allow the receive FIFO to issue receive
data move requests to the DMA controller. DMA Channel 3 is used
for the ENI r eceive FIFO. Thi s bit can be cleare d to tempora rily stall
receive side FIFO DMA. This bit should not be set when operating
the receiver FIFO in interrupt service mode. I n general, the
ERXDMA bit should be set once on device open.
ERXREG
(D27) Ena ble rece ive
FIFO data ready
interrupt
Must be set to active high to generate an inte rr upt when data is
available in the receive FIFO. The ERXREG bit should be set only
when operating the receive FIFO in interrupt service mode instead of
DMA mode. The receive FIFO interrupt is routed to the GEN module
interrupt controller using the ENI Port 1 interrupt (see "MIC module
interrupts" on page 333).
ERFIFOH
(D26) Ena ble rece ive
FIFO half full
interrupt
Must be set to active high to generate an interrupt when the receive
FIFO is at least half full (16 bytes). The ERFIFOH bit should be set
only when operating the receive FIFO in interrupt service mode
instead of DMA mode. The receive FIFO interrupt is routed to the
GEN module interrupt controller using the ENI Port 1 interrupt (see
"MIC module interrupts" on page 333).
EBEI
(D24) Enable ENI bus
error interrupt Can be set to 1 to cause an A RM interrupt to occur when the BEI bit
is set to 1 in th e E NI Gen e r a l S ta tu s re gister. Th e BE I b it wi ll be set
to 1 when the ENI shared RAM module encounters a bus e rror (data
abort) condition while attempting to address shared RAM. This
typically indicates that the shared RAM pointer is invalid. The ENI
bus error interrupt is routed to the GEN module interrupt controller
using the ENI Port 4 interrupt (see "MIC module interrupts" on page
333).
Table 133: General Control regi ster bit definition
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ETXDMA
(D22) Enable transmit
FIFO DMA 0 – Disables outbound DMA data request (use to stall transmitter)
1 – Enables outbound DMA data request
Must be set to active high to allow the transmit FIFO to issue transmit
data move requests to the DMA controller. DMA Channel 4 is used
for the ENI transmit FIFO. This bit can be cleared to temporar ily stall
receive side FIFO DMA. This bit should not be set when operating
the receive FIFO in interrupt service mode. In general, the ETXDMA
bit should be set once on device open.
ETXREG
(D19) Enable transmit
FIFO Data
register ready
interrupt
Must be set to active high to generate an interrupt when the transm it
FIFO is ready to accept more data. The ETXREG bit should be set
only when operating the transmit FIFO in interrupt service mode
instea d of DM A m o de . Th e tr a n smi t FIFO inte rr u pt is r out e d to th e
GEN module interrupt controller using the ENI Port 2 interrupt (see
"MIC module interrupts" on page 333).
ETFIFOH
(D18) Enable transmit
FIFO half empty
interrupt
Must be set to active high to generate an interrupt when the transm it
FIFO is at least half empty (<16 bytes). The ETFIFOH bit should be
set only when operating the transmit FIFO in interrupt service mode
instea d of DM A m o de . Th e tr a n smi t FIFO inte rr u pt is r out e d to th e
GEN module interrupt controller using the ENI Port 2 interrupt (see
"MIC module interrupts" on page 333).
BTE
(D15:14) Burst transfer
enable
00 – No burst pre-fetching is performed
01 – Burst pre-fetching of 8 bytes can be performed when
reading from an 8-byte boundary
10 – Burst pre-fetching of 16 bytes can be performed when
reading from a 16-byte boundary
11 – Reserved
The shared RAM module supports a bursting pre-fetch option. When
the external ENI client process o r reads th e shared RAM space and
the address is on a 16- or 8-byte boundary, the NET+50 performs a
burst read pre-fetch and stores the r esult in an internal storage buf fer.
If this feature is used, subsequent sequential accesses from the client
interface resul t in increas ed performance because the anticipat ed
read operations are pre-fetched and stored in a mini-cache block. The
mini-cache is immediately flushed when accesses are no longer
sequential. This feature cannot be used if shared RAM coherency is
a concern.
Code
(Bit #) Definition of
code Description
Table 133: General Control regi ster bit definition
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MIC Controller Module
General Status register and bit definitions
The General Status register is a 32-bit register containing status bits that affect the
ENI interface.
$GGUHVV ))$
MICDIAG
(D12) Enable M IC
diagnostic mode
0 – Disable firmware change of MICMODE or MICCTL
register
1 – Enable fi rm ware ch ang e
Provides protection against accidentally modifying the MICMODE
or ENI Control register settings. Setting MICDIAG to 1 allows the
software to modify either the MICMODE field in the General
Control register or the least significant eight bits of the ENI Control
register. When MICDIAG is set to 0, neither the MICMODE nor the
least significant eight bits of the ENI Control register can be
modified.
MICMODE
(D02:00) MIC mode of
operation
000 – GPIO
001 – IEEE 1284 host mode
010 – Reserved
011 – Reserved
100 – ENI shared-16 RAM mode; 16-bit shared RAM only
101 – ENI shared-8 RAM mode; 8-bit shared RAM only
110 – ENI FIFO mode; 16-bit with 8 Kbytes shared RAM
111 – ENI FIFO mode; 8-bit with 8 Kbytes shared RAM
Configures the mode of operation for the MIC module. The
MICMODE field is automatically loaded on powerup or hardware
reset (RESET* pin) using the bootstrap configuration bits defined on
address pins A22, A21, and A20. See "MIC module hardware
initialization" on page 333 for more information on bootstrap.
Code
(Bit #) Definition of
code Description
Table 133: General Control regi ster bit definition
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ENI mode registers
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Code
(Bit #) Definition of
code Description
RXFDB
(D29:28) Receive FIFO
data available
00 – Full-word
01 – One-byte
10 – Half-word
11 – Three Bytes (LENDIAN determines which three)
Must be used in conjunction with RXREGR. When RXREGR is set,
this field identifies how many bytes are available in the Receive Data
register. The RXFDB field is used only when operating the receive
FIFO in interrupt service mode instead of DMA mode.
RXREGR
(D27)
Receive FIFO
Read Register
ready
Set to 1 whenever data is available to be read from the Receive FIFO
Data register. This bit, when active high, can cause an interrupt to
occur if the ER XREGR bi t is set in the Gene ral Co ntrol re giste r. The
RXREGR bit is used only when operating the receive FIFO in
interrupt service mode instead of DMA mode.
RXFIFOH
(D26) Receive FIFO
half full Set to 1 whenever the receive FIFO is at least half full (>16 bytes).
This bit, when active high, can cause an interrupt to occur when the
ERFIFOH bit is set. The RXFIFOH bit is used only when operating
the receive FIFO in interrupt service mode.
BEI
(D24) ENI bus err or Set to 1 when the ENI share d RAM interfac e receives a bus error
(data abort) signal when attempting to address the shared RAM in
external memory. This typica lly means tha t the s h ared RAM pointe r
is configured in the ENI Shared RAM Address register. This bit,
when active high, can cause an i nterrupt to occur if th e EBEI bit is set
in the General Control register .
TXREGE
(D19) Transmit FIFO
Register ready Set to 1 whenever the transmit FIFO is ready to accept data. This bit,
when active high, c an caus e an i nterrupt to occur i f t he ETX REG bit
is set in the General Control register. The TXREGE bit is used only
when operating the transmit FIFO in interrupt mode instead of DMA
mode.
Table 134: General Status register bit definition
15 14 13 12 11 10 987
6543210
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset
:
Reset
:
0
R
TXREGE TXFIFOH
0
R0
R
RXREGR
0
R/C
0
R
BEIRXFDB RXFIFOH
0
R
TXFIFOE
0
R
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MIC Controller Module
ENI mode FIFO Data register
The ENI mode FIFO Data r egister is a 32-bit register used by the ARM processor to
interface with the ENI mode FIFO. Writing to this r egister loads the transmit FIFO.
This register can be written only when the transmit register empty (TXREGE) bit is
set in the General Status register. Reading from this register empties the receive
FIFO. Read data is available when the RXREGR bit is set in the General Status
register. The RXFDB bit in the General Status register indicates how many bytes
are available.
When writing to the FIFO Data register, the number of bytes written to the FIFO is
cont roll e d by the operand mo de of the ARM proces so r. The ARM processor can
write bytes, half-words, or full-words to the FIFO Data register in assembler or C:
When reading from the ENI mode FIFO Data register, all bytes available (as
defined by the RXFDB field) must be r ead with a single instruction:
If only a single byte is available, an LDRB or
FKDU
operation can be
used. The LDR or
LQW
operations can also be used to read the one
byte.
TXFIFOH
(D18) Transmit FIFO
half full Set to 1 whenever the transmit FIFO is at least half empty (<16 bytes).
This bit, when active high, can cause an interrupt to occur if the
ETFIFOH bit is set in the General Control register. The TXFIFOH bit
is used only when operating the transmit FIFO in interrupt mode
instead of DMA mode.
TXFIFOE
(D16) Transmit FIFO
empty Set to 1 whenever the transmit FIFO is empty. The TXFIFOE bit
cannot be used to generate an interrupt to the ARM processor.
Code
(Bit #) Definition of
code Description
Table 134: General Status register bit definition
ARM
processor Assembler
instructions C instructions
Bytes STRB
FKDU[))$
Half-word STRH
VKRUW[))$
Full-word STR
LQW[))$
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ENI mode registers
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NET+50/20M Hardware Reference
If only a half-word is available, an LDRH or
VKRUW
operatio n can be
used. The LDR or
LQW
operations can also be used to read the half-
word.
When a full word is available, the LDR or
LQW
operations must be
performed.
ENI Control register and bit definitions
The ENI Contr ol regi ster is a 32-bi t re ad/wr ite r egi ster th at af fec ts the ope rati on of
the ENI interface. Only the ARM processor can modify the ENI Control register; it
cannot be accessed through the ENI interface. The PSIO* and least significant 7 bits
can be initialized during bootstrap by sampling the A7:A0 addr ess inputs during
reset.
15 14 13 12 11 10 9876543210
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset
:
Reset
:
0
R/W
0
R/W
FMDR
FMDR
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
0
R/W
0
R/W
SYNC
WAIT DMAE2 FAST DPACK* PSIO KYOINT INTP* WR_OCDINT2* I_OC DMAE* IRQEN* EPACK* PULINT*
0
R/W 0
R/W 0
R/W 0
R/W I
R/W
I
R/W
ADDR7
R/W ADDR6
R/W ADDR5
R/W ADDR4
R/W ADDR3
R/W ADDR1
R/W ADDR0
R/W
Addres s = FFA0 0030
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MIC Controller Module
Code
(Bit #) Definition of
code Description
SYNC
(D17:16) PACK* output
synchroniza tion
mode
Provides control over the PACK* output synchronization mode:
00 – The PACK* output is driven synchronous to the internal
SYSCLK timing domain. This configuration is directly
compatible with older NET+50 devices.
01 – The PACK* output is driven synchronous to an external
clock, which is provided as an input on the PBRW* pin. The
PACK* output is synchronized from the SYSCLK domain to
the PBRW* input clock domain using a single-rank flip-flop
structure.
10 – The PACK* output is driven synchronous to an external
clock, which is provided as an input on the PBRW* pin. The
PACK* output is synchronized from the SYSCLK domain to
the PBRW* input clock domain using a dual-rank flip-flop
structure.
11 – Reserved.
WAIT
(D15:13)
ENI added wait
states for data
setup to PACK*
Inserts additional wait states between when PDATA is made
available and PACK * is asserted. This field can be used to help t hose
environments requiring longer data settling time. This field extends
the cycle time for both read and write cycles.
DMAE2
(D12) Ena ble DM A
request through
the PINT2 pin
0 – Disable
1 – Enable
When set, drives a single active high ENI FIFO mode DMA request
signal out the PINT2 pin. The DMA request output is a logic-OR of
the inbound and outbound DMA request signals.
This configuration mode should be used only when FIFO DMA is
enabled in one direction or another — never both. The FIFO DMA
enable configuration is controlled using the FIFO mode Mask/Status
register.
When the DMAE2 configuration bit is set:
The DINT2* configuration is ignored and the ENI interface
cannot accept or issue an interrupt through the PINT2* pin.
Both PA14 and PA13 are returned to their address input
function allowing for a maximum of 32K bytes of available
shared RAM.
Table 135: ENI Control regi ster and bit definition
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FAST
(D11) ENI FAST timing
mode
0 – Classic ENI t iming
1 – Fast ENI timing
Can be set to improve performance in the ENI interface. The FAST
mode configuration removes 2 SYSCLK clocks from the ENI
interface access t iming.
Sett in g FAST to 1 re q uires the ex ternal EN I in te r fa ce to driv e
PRW* valid before PCS* or PDACK* signals are asserted.
Setting FAST to 0 allows the external ENI interface to change
PRW* slightly after PCS* or PD AC K* are asserted.
DPACK*
(D10)
DMA PACK*
generation
0 – Drive PACK* active during DMA cycles
1 – Disable PACK* during DMA cycles
Can be used to disable the assertion of PDACK* during DMA
cycles. PDACK* should be disabled during DMA cycles when the
external ENI interf ace is not designed to wait for PDACK * during
DMA cycles.
PSIO
(D09)
PSIO
configuration for
shared register
0 – Shared regist er confi gured for NORMAL mode
1 – Shared regist er configured for PSIO mode
Controls the bit formatting for the E NI Shared regi st er.
When the PSIO bit is set to 0, both the ARM processor and ENI
interface use the same bit format for the Shared register.
When the PSIO bit is set to 1, the ENI interface has an altered
view of the ENI Shared register (see Table 128: "Shared
register layout (ENI interface perspective only)" on page 385.)
The default state for PSIO is established at bootstrap by sampling the
A7 signal during reset. The inverted version of the A7 value is loaded
into the PSIO configuration bit.
KYOINT
(D08)
Kyocera interrupt
option
0 – Normal interrupt mode
1 – Kyocera interr upt. Occur s when the ENI i nterface writes to
the most significant address of shared RAM.
An alternate mechanism for the ENI interf ace to issue an interrupt to
the ARM processor. When the KY OIN T bit is set to 1, the ENI
interface can issue an ARM interr upt by writing to the most
significant word of shared RAM. The INTP* bit is set active low
when the interrupt is issued. The KYOINT bit provides a useful
means for generating an interrupt to the ARM processor when the
ENI interface cannot address the Shared register.
Code
(Bit #) Definition of
code Description
Table 135: ENI Control regi ster and bit definition
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MIC Controller Module
INTP*
(D07)
Interrupt pending Set active low when the ENI interface is sues an interrupt to the ARM
processor. The INTP* bit remains low until cleared by the ARM
processor. Th e ARM processor clear s the INTP* bi t by writing a 1 to
the same bit position in the ENI Control register. An active low
setting in INTP* causes an ARM processor interrupt when IRQEN*
(ENI Control register) is set active low and ENI3 (GEN Interrupt
Enable register) is set active high.
This bit, when low, indicates that an interrupt from the ENI is
pending. This bit is returned to the inactive state by writing a 1 in this
same bit position [D7].
WR_OC
(D06)
Wait/ready/
acknowledge
open collector
0 – Output driver is TTL; used for LN14, MIO, Kyocera, others
1 – Output driver is OPEN COLLECTOR, GCC, others
Defines the driver personality for the PACK* signal. When set to 1,
the PACK* signal is driven with an open-collector dri ver. When set
to 0, PACK* is driven with a TTL driver. The default state for
WR_OC is established at bootstrap by sampling the A6 signal during
reset.
DINT2*
(D05)
Disabled interrupt
2 to ENI
0 – INT2* pin can be used as a pulsed interrupt from the ENI;
used for MIO, LN14, others
1 – ENI can select between PINT1* or PINT2* using the
SINTP2 bit in the ENI Shared register
Controls the use of the PINT2* signal. When DINT2* is set to 1, the
PINT2* signal is an interrupt output. The ENI interface selects either
PINT1* or PINT2* using the SINTP2 bit in the ENI Shared register.
When DINT2* is set to 0, the PINT2* signal is used as a pulse
interrupt input from the ENI interface. An interrupt condition is
latched on the low-to-high transition of the PINT2* input. The
INTP* bit is set active low when the interrupt is issued. The pulsed
interrupt input feature provides a useful means for the ENI interface
to issue an interrupt to the ARM processor when the ENI int erf ace
cannot address the ENI Shared register. The default state is
established at bootstrap by sampling the A5 signal during reset.
Code
(Bit #) Definition of
code Description
Table 135: ENI Control regi ster and bit definition
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I_OC
(D04)
Interrupt(s) open
collector
0 – Output driver is TTL; used for LN14, MIO, Kyocera, others
1 – Output driver is OPEN COLLECTOR; GCC, others
Defines the driver personality for the PINT1* and PINT2* output
signals. When set to 1, the PINT1* and PINT2* output signals are
driven with an open-collector driver. When set to 0, PINT1* and
PINT2* output signals are driven with a TTL driver. The default state
is established at bootstrap by sampling the A4 signal during reset.
DMAE*
(D03)
Enabl e EN I
interface FIF O
mode DMA
signals
0 – Enable DACK*, DRQO*, and DRQI* for FIFO mode
1 – Disable FIFO mode DMA at the ENI int erf ace
Controls how the PA15, PA14, PA13, and PINT2* signals are used.
The default state for DMAE* is established at bootstrap by sampling
the A3 signal during reset.
When DMAE* is set to 0, the PA15, PA14, PA13, and PINT2*
signals change personality to provide the DMA acknowledge and
DMA request i nter face signals between the ENI F IFOs and t he E NI
interface. The DMAE2 bit determines whether the DMA request
signals are routed through PA14/PA13 or through PINT2*. When
DMAE* and DMAE2 are both low, PA15, PA14, and PA13 are
reallocated, causing the addressi ng of shared RAM to be limited to
8K bytes. When DMAE* is low and DMAE2 is high, PA15 and
PINT2* are reallocated, limiting the addressability of shared RAM to
32Kbytes.
When DMAE* is set to 1, the ENI FIFO DMA interf ace si gnals are
disabled. PA15, PA14, and PA13 are used for shared RAM
addressing only; PINT2* is used for interrupts only.
IRQEN*
(D02)
Enable interrupt
from ENI
interface
0 – Interrupts from the ENI are enabled. An interrupt condition
is set up when the ENI issues a pulsed interrupt using INT2* or
the IN T IO b i t is set in the E NI S h a red registe r.
1 – Interrupts from the ENI are disabled.
Must be set active low to enable interrupts from the ENI interface.
An interrupt from the ENI interface can be set using the INTIOF bit
in the ENI Shared regist er, the Kyocer a interrupt option, or the
pulsed interrupt option on PINT2*. A pending interrupt is identified
when the INTP* bit is active low in the ENI Control regist er. The
ENI3 bit (GEN module Interrupt Enable register) must also be set
active high to generate an ARM processor interrupt.
Code
(Bit #) Definition of
code Description
Table 135: ENI Control regi ster and bit definition
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MIC Controller Module
ENI Pulsed Interrupt register and bit definition
The ENI Pulsed Interrupt register contains no meaningful data. This addr ess is
used to issue an interrupt request to the ENI interface. An interrupt condition is set
EPACK*
(D01)
Enable ENI ACK
pulse
0 –The ACK pin is used as an active low data acknowledge
signal; used for MIO, LN14, others
1 –T he ACK pi n is used as an active l ow WAIT signal; used for
LN14, GCC, others
Controls the personality of the PACK* output. The default state is
established at bootstrap by sampling the A1 signal during reset.
When EPACK* is set to 0, the PACK* output is used as an active low
data acknowledge signal. The PACK* signal is driven inactive high
from the beginning of the ENI cycle until the end of the ENI cycle.
At the end of the ENI cycle, the PACK* signal is driven active low.
When EPACK* is set to 1, the PACK* output is used as an active
high data ready signal. The PACK* signal is immediately driven
inactive low at the start of the ENI cycl e and remains lo w until the
end of the E NI cycle. At t he end of the ENI c ycle, the PACK* signal
is driven active high to indicate ready.
PULINT*
(D00) Pulsed interrupt
enable
0 –Interrupts to the ENI are issued by writing to the Pulsed
Interrupt register; used for MIO, LN14, others
1 –I nterrupts are issued by setting the STSINT or VDAI NT bits
in the ENI Shared register; used for GCC, others
Controls how interrupts are issued from the ARM processor to the
ENI interface. This bit allows a pulsed interrupt signal to be drive out
the PINT1* or PINT2* interrupt output signals. The default state for
PULINT* is established at bootstrap by sampling the A0 signal
during reset.
When PULINT* is set low, a write to the ENI Pulsed Interrupt
register causes a 1us low-going pulse to be issued out the PINT1*
pin. This interrupt mode is useful for ENI interfaces tha t require an
edge interrupt instead of a level interrupt.
When PULI NT* is set high, interrupts to the ENI i nterface are solely
controlled by the VDAINT and STSINT bit settings in the ENI
Shared register. When either of thes e bits are set, the PINT1* or
PINT2* signal pins are driven active pins (controlled by the SINPT2
setting in the ENI Shared register).
Code
(Bit #) Definition of
code Description
Table 135: ENI Control regi ster and bit definition
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NET+50/20M Hardware Reference
up for the ENI if this reg iste r is written to while the PULINT* bit in the ENI
Control register is set to its active low state.
When the NET+50 chip is configured for MIO mode, reading this re gister provides
the cu rr ent s tatu s of the l ower 8 bits of the PDATA pins. These p ins ca n be use d for
jumper settings. The 8 data bits are presented in the least significant 8 bits of this
register.
The external ENI client processor is responsible for setting the bits in the FIFO
Mask/Statu s register (se e "FIF O Mask/Sta tus register and bit defini ti on " on page
395). The ARM processor can read the values written by the ENI client pr ocessor
by reading the ENI Pulsed Interrupt register. The lower sixteen bits in the FIFO
Mask/St atus regist er are mapped on to t he upper sixte en bit s of the ENI Pulse d
Interrupt register.
The AR M proc es so r can not modify any valu es in either the FI FO Ma sk /Stat us
register or the ENI Pulsed Interrupt register.
ENI Shared RAM Address register and bit definitions
The ENI Shared RAM Ad d ress register is a 32-bit read/write register. Th e bits in
this register are set to 0 on reset. This register prov ides the base addres s and
physical size of the shared memory window.
Shared memory is physically located so mewhere in external RAM. The specified
address offset must be on a multiple of the selected window size. The size of the
shared RAM window can be configured from 4 Kbytes to 64 Kbytes.
The base addr ess value is used by the ENI c ontr oller module when addr essing the
shared memory b l ock for the ENI interface. The effective address of the shared
memory location is the sum of the base address and the index of fset that is
151413121110987654 3210
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
0
R
FIFO Mask/Status regis ter
Address = FFA0 0034
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MIC Controller Module
pr ovided by the address inputs fr om the ENI interface. Any ENI address bits
above what is specified to be the shared RAM physical size are ignored.
Shared RAM is available to the ENI interface only when the ENABLE bit is set to 1.
The ENABLE bit must be set only after a valid BASE and RAMSIZE are
configured. Before the ENABLE bit is set, any shared RAM access from the ENI
interface is completed; write data is ignored and read data is returned with all
zeros, however.
Code
(Bit #) Definition of
code Description
BASE
(D31:12) Base address of
shared RAM Defines the base location pointer for shared RAM. Shared RAM
resides in an external memory location whose bas e address is defined
by this field. The BASE field provides the most significant 20 bits of
the base address of shared RAM. The value of the shared RAM
location can be defined in either of these two ways:
6KDUHG5$0 %$6(
%$6( 6KDUHG5$0!!
where
implies the address of operator.
!!
implie s th e shift right o p erator.
implie s the shif t left oper ato r.
ENABLE
(D08) Shared RAM
enable Must be set to 1 to allow the external ENI i nterface to address shared
RAM. While the ENABLE bit is set to 0:
The external ENI interfa ce wi ll be given a value of
[
for
all read operations to shared RAM.
Writes to shared RAM from the external ENI interface are
ignored.
Table 136: ENI Shared RAM Address regi ster bit definition
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset:
Reset:
0
R
Base
Address = FFA0 0038
Base (continued)
0
R/W 0
R/W
ENABLE RAMSIZE
0
R/W 0
R/W
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ENI mode registers
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RAMSIZE
(D03:00) Shared RAM
physical size
.
.
.
.
.
Code
(Bit #) Definition of
code Description
Table 136: ENI Shared RAM Address regi ster bit definition
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Timing
CHAPTER 13
This chapter provides the electrical specifications, or timing, integral to the
operation of the NET+50/20M chip. Timing includes information on DC and AC
characteristics, output rise and fall timing, and crystal oscillator specifications.
Note:
The information in this chapter applies to both the NET+50 and
NET+20M chips, unless otherwise noted.
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420 n n n n n n n
NET+50/20M Hardware Reference
Thermal considerations
Table 137 describes the thermal requirements for the NET+50 chip:
The average chip junction temperature (TJ) in ºC is calculated as follows:
7
-
7
$
3
'
θJA
where:
7
$
is the ambient temperature.
θJA is the package thermal resistance, junction-to-ambient, ºCW.
3
'
is the calculated power consumption.
Power consumption is calculated by the following equation:
3
'
3
,17
)
3
3
,2
)
3
6
3
where:
6
3
is the estimated number of output pads switching simultaneously.
)
3
is the operating fr equency of outputs.
Characteristic Symbol Value Unit
Thermal resistance – junction to
ambient θJA PQFP: 31
BGA: 37 ºC/W
Operating junction temperature T JMin: -40
Max: +100 ºC
Operating ambient temperature TAMin: -40
Max: +85 ºC
Storage temperature TSTG Mi n: -60
Max: +150 ºC
Core dynamic power @ VDD
(max) PINT NET+50 chip max: 7.36
NET+20M chip max: 4.95 mW/MHz
I/O dynamic power @ VCC
(max) PI/O NET+50 chip max: 5.18
NET+20M chip max: 4.95 mW/MHz
Table 137: Thermal c onsiderations
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n n n n n n n 421
Timing
Absolu te maximu m ratin gs
Table 138 iden tifies the maximum v alues for the voltag es that the NET +50 chip ca n
withstand without being damaged.
DC characteristics
Be sur e the NET+50 chip operates within the voltages defined in the next two
tables. Operating outside these voltages can result in unpredictable behavior.
Sym Parameter Conditions Min Max Unit
VDD3 DC supply voltage 2.5V core Core -0.3 3.15 V
VCC DC supply voltage 3.3V I/O Standard I/Os -0.3 4.00
VIDC input voltage -0.3 4.50 V
VODC output voltage -0.3 4.50 V
TEMP Operating free air Industrial -40 +85 ºC
TSTG Storage temperature -40 +125 ºC
Table 138: Maxi mum voltage ratings
Sym Parameter Conditions Value Unit
VDD DC supply voltage 2.5V core Min: 2.25
Typ: 2.5
Max: 2.75
V
VCC DC supply voltage I/O pads Min: 3.0
Typ: 3.3
Max: 3.6
V
VIH Input high voltage Min: 2.0
Max: 3.6 V
VIL Input low voltage Min: VSS-0.3
Max: 0.8 V
Ta ble 139: DC c haracteristics — Inputs
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DC characteristics
422 n n n n n n n
NET+50/20M Hardware Reference
IIL Input buffer VIN=VCC Min: -10
Max: 10
µA
Input buffer with current input sink Min: 99
Max: 429
IIH Input buffer VIN=VSS Min: -10
Max: 10
µA
Input buffer with current input source Min: 130
Max: 352
CIN Input capacitance Any input 7 pF
VTInput switching threshold volt a ge Any input Min: 1.4
Typ: 2.0 V
PDVCC power dissipation (@ 3.6V) FSYSCLK=44MHz Typ: 152
Max: 228 mW
PDVDD power dissipation (@ 2.75V) FSYSCLK=44MHz NET+50 chip
Typ: 216
Max: 324
NET+20M
Typ:145
Max: 218
mW
Sym Parameter Conditions Value Unit
Ta ble 139: DC c haracteristics — Inputs
Sym Parameter Conditions Min Unit
VOL Output low voltage Type: 1, IOL=2 mA; Min: 0
Max: 0.4 V
Type: 2, IOL=4mA; Min: 0
Max: 0.4 V
Type: 3, IOL=8mA; Min: 0
Max: 0.4 V
Ta ble 140: DC c haracteristics — Outputs
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n n n n n n n 423
Timing
AC characteristics
Output pad timing
The total pr opagation delay for each of the output timing characteristics in the
NET+50 chip is a function of the intrinsic delay of the path, the pad cell type, and
the load capacitance.
The total propagation delay is the sum of the intrinsic delay time and the load-
dependent delay time.
Intrinsi c d ela y i s the d el ay o f the path with no exter nal lo ad. The v al ues
shown in the timing diagram tables are intrinsic delay values.
Load-dependent delay time is a function of the output capacitive load
attached to the NET+50 chip output pin and the drive strength of the
output buffer type used on that pin. The load-dependent factors for
VOH Output high voltage Type: 1, IOH=2 mA; Min: 2.4
Max: VCC
V
Type: 2, IOH=4mA; Min: 2.4
Ma: VCC
V
Type: 3, IOH=8mA Mi n: 2.4
Max: VCC
V
IOZ High-Z leakage current VO=VSS Min: -10
Max: 10 uA
IOS Output short circuit current VCC=3.6V, VO=VCC 55 uA
VCC=3.6V, VO=VSS -55 uA
CIN Input capacitance Any input 7 pF
CIO Input/output capacitance Any I/O 7 pF
Sym Parameter Conditions Min Unit
Ta ble 140: DC c haracteristics — Outputs
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AC characteristics
424 n n n n n n n
NET+50/20M Hardware Reference
propagation delay on the low-to-high transition of the output (TPLH)
may be different than the factors for the high-to-low transition (TPHL).
Table 141 shows the factors for each pad type. The propagation delay times are
calculat ed as follows:
73/+RU73+/ ,QWULQVLFWLPHORDGGHSHQGHQWGHOD\IDFWRU&/
CL is the output load capacitance attached to the NET+50 chip output pin.
Pad Cell Load-dependent delay
factor (ns/pF) for TPLH
Load-dependent delay
factor (ns/pF) for TPHL
pc25d00u 0.178 0.123
pt33b01 0.168 0.160
pt33b01u 0.163 0.161
pt33b02 0.084 0.080
pt33b02u 0.083 0.080
pt33b03 0.042 0.040
pt33b03u 0.042 0.040
pt33d00 0.025 0.0144
pt33d00d 0.025 0.0144
pt33d00u 0.025 0.0144
pt33t01 0.168 0.160
pt33t02 0.084 0.080
pt33t03 0.042 0.084
Table 141: Ou tput load-depe ndent delay f actors
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Timing
Clock relationships
Table 142 shows the relationship between the various clocks on the NET+50 chip.
RESET* timing
Table 143 describes the values shown in Figure 60, "RESET* timing."
Figure 60: RESET* timing
Num Characteristic Symbol Min Max Unit
1 On-chip VCO system frequency FSYSCLK DC 44.3 MHz
2 VCO system cycle time TSYS 1/FSYSCLK ns
3 Crystal frequency FCRYSTAL 520MHz
4 CPU core frequency FCPU FSYSCLK MHz
5 BCLK frequency FBCLK FSYSCLK/4 FSYSCLK MHz
Table 142: Operatin g frequencies
Num Characteristic Min Max Unit
7 VDD at 3.0V to RESET* high 40 ms
8 RESET* pulse width low 10/FSYSCLK µs
9 RESET * low to VD D be low 3. 0V 8/FSYSCLK µs
Table 143: RESET t iming values
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SRAM timing
426 n n n n n n n
NET+50/20M Hardware Reference
SRAM timing
Table 144 describes the values shown in the SRAM timing diagrams (Figure 61
through Figure 69) .
Num Characteristic Min Max Unit
31 BCLK high to RW* valid 19 ns
32 BCLK high to BE* valid 1 6 ns
33 BCLK high to Address valid 4 15 ns
34 BCLK high to Data Out high impedance 17 ns
35 BCLK high to Data Out valid 18 ns
36a Data In valid to BCLK high (setup) 8 ns
36b BCLK high to Data In invalid (hold) 0 ns
37a TA* valid to BCLK high (setup) 8 ns
37b BCLK high to TA* invalid (hold) 0 ns
38a TEA* valid to BCLK high (setup) 8.5 ns
38b BCLK high to TEA* invalid (hold) 0 ns
40 BCLK high to CS* valid 16 ns
41 BCLK low to OE* valid 14 ns
42 BCLK low to WE* valid 16 ns
43 BCLK high to TA* valid 11 ns
44 BCLK high to TEA* valid 14 ns
Table 144: SRAM timing characteristics
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Timing
SRAM Sync Read (WAIT = 2)
Figure 61: SRAM Synchronous Read (WAIT = 2)
Notes:
1 There can be 0, 1, or 2 null periods between memory transfers.
2 Port size determines which byte enable signals are active:
–8-bit port = BE3*
–16-bit port = BE[3:2]
–32-bit port = BE[3:0]
T1 TW TW T2 Note-1 T1
31
4141
4040
3232
33
4444
4343
36b
36a
38b
38a
37b
37a
Note-2
BCLK
TA* (output)
TEA* (out put)
TA* (input)
TEA*/LAST* (input)
A[27:0]
BE[3:0]*
CS[4:0]*
read D[ 31:0]
Sync OE*
RW*
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SRAM timing
428 n n n n n n n
NET+50/20M Hardware Reference
SRAM Sync Write (WAIT = 2)
Figure 62: SRAM Synchronous Write (WAIT = 2)
Notes:
1 There can be 0, 1, or 2 null periods between memory transfers.
2 Port size determines which byte enable signals are active:
–8-bit port = BE3*
–16-bit port = BE[3:2]
–32-bit port = BE[3:0[
T1 TW TW T2 Note-1 T1
31
4242
3435
4040
3232
33
4444
4343
38b
38a
37b
37a
Note 2
BCLK
TA* (output)
TEA* (output)
TA* (input)
TEA*/LAST* (in put)
A[27:0]
BE[3:0]*
CS[4:0]*
write D[31:0]
Sync WE*
RW*
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n n n n n n n 429
Timing
SRAM Sync Burst Read (2-111) (WAIT = 0, BCYC = 00)
Figure 63: SRAM Synchronous Burst Read (2-111) (WAIT = 0, BCYC = 00)
Notes:
1 There can be 0, 1, or 2 null periods between memory transfers.
2 Port size determines which byte enable signals are active:
–8-bit port = BE3*
–16-bit port = BE[3:2]
–32-bit port = BE[3:0]
T1 T2 T2 T2 T2 Note-1 T1
31
4141
4040
3232
33
4444
4343
36b
36a
38b
38a
37b37a
Note-2
BCLK
TA* (output)
TEA* (output)
TA* (input)
TEA*/LAST* (input)
A[27:0]
BE[3:0]*
CS[4:0]*
read D[31:0]
Sync OE *
RW*
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SRAM timing
430 n n n n n n n
NET+50/20M Hardware Reference
SRAM Sync Burst Read (4-222) (WAIT = 2, BCYC = 01)
Figure 64: SRAM Synchronous Burst Read (4-222) (WAIT = 2, BCYC = 01)
Notes:
1 There can be 0, 1, or 2 null periods between memory transfers.
2 Port size determines which byte enable signals are active:
–8-bit port = BE3*
–16-bit port = BE[3:2]
–32-bit port = BE[3:0]
T1 TW TW T2 TW T2 TW T2 TW T2 Note-1 T1
31
4141
4040
3232
33
4444
4343
36b
36a
38b
38a
37b
37a
BCLK
TA* ( ou t put)
TEA*/LAST (output)
TA* ( i np ut )
TEA*/LAST* (input)
A[27:0]
BE[3:0]* Note-2
CS[4:0]*
read D[31:0]
Sync OE*
RW*
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n n n n n n n 431
Timing
SRAM Sync Burst Write (4-222) (WAIT = 2, BCYC = 01)
Figure 65: SRAM Synchronous Burst Write (4 -222) (WA IT = 2, BCYC = 0 1)
Notes:
1 There can be 0, 1, or 2 null periods between memory transfers.
2 Port size determines which byte enable signals are active:
–8-bit port = BE3*
–16-bit port = BE[3:2]
–32-bit port = BE[3:0]
T1 TW TW T2 TW T2 TW T2 TW T2 Note-1 T1
31
4242
3435
4040
3232
33
4444
4343
38b
38a
37b
37a
BCLK
TA* (output )
TEA*/LAST (output)
TA* (input )
TEA* /LAS T* (inp ut )
A[27:0]
BE[3:0]* (Note-2)
CS[4:0]*
write D[31:0]
Sync WE*
RW*
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SRAM timing
432 n n n n n n n
NET+50/20M Hardware Reference
SRAM Async Read (WAIT = 2)
The TW cycles are present when the WAIT field is set to 2 or more.
Figure 66: SRAM Asynchronous Read (WAIT = 2)
Notes:
1 There can be 0, 1, or 2 null periods between memory transfers.
2 Port size determines which byte enable signals are active:
–8-bit port = BE3*
–16-bit port = BE[3:2]
–32-bit port = BE[3:0]
T1 TW T2 Note-1 T1
31
4141
4040
3232
33
4444
4343
36b
36a
38b
38a
37b
37a
Note-2
BCLK
TA* (output)
TEA*/LAST (output)
TA* (input)
TEA*/LAST* (input)
A[27:0]
BE[3:0]*
CS[4:0]*
read D[31:0]
Async OE*
RW*
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Timing
SRAM Async Write (WAIT = 2)
The TW cycles are present when the WAIT field is set to 2 or more.
Figure 67: SRAM Asynchronous Write (WAIT = 2)
Notes:
1 There can be 0, 1, or 2 null periods between memory transfers.
2 Port size determines which byte enable signals are active:
–8-bit port = BE3*
–16-bit port = BE[3:2]
–32-bit port = BE[3:0]
T1 TW T2 Note-1 T1
31
4242
3435
4040
3232
33
4444
4343
38b
38a
37b
37a
Note-2
BCLK
TA* (output)
TEA* /LAS T (o utp ut )
TA* (input)
TEA*/LAST* (input)
A[27:0]
BE[3:0]*
CS[4:0]*
write D[31:0]
Async WE*
RW*
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SRAM timing
434 n n n n n n n
NET+50/20M Hardware Reference
SRAM Async Burst Read (WAIT = 2, BCYC = 01)
The TW cycles are present when the WAIT field is set to 2 or more.
Figure 68: SRAM Asynchronous Burst Read (WAIT = 2, BCYC = 01)
Notes:
1 There can be 0, 1, or 2 null periods between memory transfers.
2 Port size determines which byte enable signals are active:
–8-bit port = BE3*
–16-bit port = BE[3:2]
–32-bit port = BE[3:0]
T1 TW T2 TW T2 TW T2 TW T2 Note-1 T1
31
4141
4040
3232
33
4444
4343
36b
36a
38b
38a
37b
37a
BCLK
TA* (output)
TEA*/LAST (output)
TA* (input)
TEA*/LAST* (input)
A[27:0]
BE[3:0]* Note-2
CS[4:0]*
read D[31:0]
Async OE*
RW*
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n n n n n n n 435
Timing
SRAM Async Burst Write (WAIT = 2, BCYC = 01)
The TW cycles are present when the WAIT field is set to 2 or more.
Figure 69: SRAM Asynchronous Burst Write (WAIT = 2, BCYC = 01)
Notes:
1 There can be 0, 1, or 2 null periods between memory transfers.
2 Port size determines which byte enable signals are active:
–8-bit port = BE3*
–16-bit port = BE[3:2]
–32-bit port = BE[3:0]
T1 TW T2 TW T2 TW T2 TW T2 Note-1 T1
31
4242
3435
4040
3232
33
4444
4343
38a
38a
37b
37a
Note-2
BCLK
TA* (output)
TEA*/LAST (output)
TA* (input)
TEA*/LAST* (input)
A[27:0]
BE[3:0]*
CS[4:0]*
write D[31:0]
Async WE*
RW*
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Fast Page and EDO DRAM Timing
436 n n n n n n n
NET+50/20M Hardware Reference
Fast Page and EDO DRAM Timing
Table 145 describes the values shown in the fast page (FP) and EDO DRAM timing
diagrams (Figure 70 through Figure 77).
Num Characteristic Min Max Unit
31 BCLK high to RW* valid 19 ns
32 BCLK high to BE* valid 1 6 ns‘
33 BCLK high to Address valid 4 15 ns
34 BCLK high to Data Out high impedance 17 ns
35 BCLK high to Data Out valid 18 ns
36a Data In valid to BCLK high (setup) 8 ns
36b BCLK high to Data In invalid (hold) 0 ns
37a TA* valid to BCLK high (setup) 8 ns
37b BCLK high to TA* invalid (hold) 0 ns
38a TEA* valid to BCLK high (setup) 8.5 ns
38b BCLK high to TEA* invalid (hold) 0 ns
41 BCLK low to OE* valid 14 ns
42 BCLK low to WE* valid 16 ns
43 BCLK high to TA* valid 11 ns
44 BCLK high to TEA* valid 14 ns
45 BCLK high to PORTC3/AMUX valid 8 ns
46a BCLK low to CAS* valid 13 ns
46b BCLK high to CAS* valid 13 ns
47 BCLK lo w to RA S* v alid 16 ns
Table 145: Fast Page /EDO timing ch aracteristics
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n n n n n n n 437
Timing
Fast Page and EDO DRAM Read
Figure 70: Fast Page and EDO DRAM Read
Notes:
1 There can be 0, 1, or 2 null periods between memory transfers.
2 Port size determines which byte enable signals are active:
–8-bit port = BE3*
–16-bit port = BE[3:2]
–32-bit port = BE[3:0]
3 Port size determines which CAS* signals are active:
–8-bit port = CAS3*
–16-bit port = CAS[3:2]
–32-bit port = CAS[3:0]
T1 TW T2 Note-1 T1
31
4545
46a46a
4747
46b46a
4747
4141
3333
3232
4444
4343
36b
36a
38b
38a
37b
37a
Note-2
Note-3
Note-3
BCLK
TA* (output)
TEA*/LAST (output)
TA* (input)
TEA*/LAST* (input)
BE[3:0]*
A[27:0]
read D[31:0]1
OE*
(FP)RAS[4:0]*1
(FP)CAS[3:0]>*1
(EDO)RAS[4:0]*
(EDO)CAS[3:0]>*
PortC3/AMUX
RW*
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Fast Page and EDO DRAM Timing
438 n n n n n n n
NET+50/20M Hardware Reference
Fast Page and EDO DRAM Write
Figure 71: Fast Page and EDO DRAM Write
Notes:
1 There can be 0, 1, or 2 null periods between memory transfers.
2 Port size determines which byte enable signals are active:
–8-bit port = BE3*
–16-bit port = BE[3:2]
–32-bit port = BE[3:0]
3 Port size determines which CAS* signals are active:
–8-bit port = CAS3*
–16-bit port = CAS[3:2]
–32-bit port = CAS[3:0]
T1 TW T2 Note-1 T1
31
4545
46a46a
4747
46b46a
4747
4242
3435
33
3232
4444
4343
38b
38a
37b
37a
Note-2
Note-3
Note-3
BCLK
TA* (output)
TEA*/LAST (output)
TA* (input)
TEA*/LAST* (input)
BE[3:0]*
A[27:0]
write D[31:0]
WE*
(FP)RAS[4:0]*
(FP)CAS[3:0]*
(EDO)RAS[4:0]*
(EDO)CAS[3:0]*
PortC3/AMUX
RW*
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n n n n n n n 439
Timing
Fast Page and EDO DRAM Burst Read
Caution:
The BCYC field in the Chip Select Option register should never be set
to 00 for Fast Page/EDO DRAM.
Figure 72: Fast Page and EDO DRAM Burst Read
Notes:
1 There can be 0, 1, or 2 null periods between memory transfers.
2 Port size determines which byte enable signals are active:
–8-bit port = BE3*
–16-bit port = BE[3:2]
–32-bit port = BE[3:0]
T1 TW T2 TW T2 TW T2 TW T2 Note-1 T1
31
4545
46a46a
4747
46b46b46a
4747
4141
33
3232
4444
4343
36b
36a
38b
38a
37b
37a
Note-2
Note-3
Note-3
BCLK
TA* (output)
TEA*/LAST (output)
TA* (input)
TEA*/ LA S T* (i nput)
BE[3:0]*
A[27:0]
read D[31:0]
OE*
(FP)RAS[4:0]*
(FP)CAS[3:0]*
(EDO)RAS[4:0]*
(EDO)CAS[3:0]*
PortC3/AMUX
RW*
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Fast Page and EDO DRAM Timing
440 n n n n n n n
NET+50/20M Hardware Reference
3 Port size determines which CAS* signals are active:
–8-bit port = CAS3*
–16-bit port = CAS[3:2]
–32-bit port = CAS[3:0]
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Timing
Fast Page and EDO DRAM Burst Write
Caution:
The BCYC field in the Chip Select Option register should never be set
to 00 for Fast Page/EDO DRAM.
Figure 73: Fast Page and EDO DRAM Burst Write
Notes:
1 There can be 0, 1, or 2 null periods between memory transfers.
2 Port size determines which byte enable signals are active:
–8-bit port = BE3*
–16-bit port = BE[3:2]
–32-bit port = BE[3:0]
T1 TW T2 TW T2 TW T2 TW T2 Note-1 T1
31
4545
46a46a
4747
46b46b46a
4747
4242
3435
33
3232
4444
4343
38b
38a
37b
37a
Note-2
Note-3
Note-3
BCLK
TA* (output)
TEA*/LAST (output)
TA* (input)
TEA*/LAST* (input)
BE[3:0]*
A[27:0]
writeD[31:0]
WE*
(FP)RAS[4:0]*
(FP)CAS[3:0]*
(EDO)RAS[4:0]*
(EDO)CAS[3:0]*
PortC3/AMUX
RW*
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Fast Page and EDO DRAM Timing
442 n n n n n n n
NET+50/20M Hardware Reference
3 Port size determines which CAS* signals are active:
–8-bit port = CAS3*
–16-bit port = CAS[3:2]
–32-bit port = CAS[3:0]
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Timing
Fast Page and EDO DRAM Refresh (RCYC = 0)
Figure 74: Fast Page and EDO DRAM Refresh (RCYC = 0)
Fast Page and EDO DRAM Refresh (RCYC = 1)
Figure 75: Fast Page and EDO DRAM Refresh (RCYC = 1)
RF1 RF2 RF3 RF4 RF5 RF6 RF7 RF8 T1
4242
46b46b46b
46b46b46b
46b46b46b
46b46b46b
47474747
BCLK
CS[4:0]*
CAS3*
CAS2*
CAS1*
CAS0*
WE*
RF1 RF2 RF3 RF4 RF5 RF6 RF8
4242
46b46b46b
46b46b46b
46b46b46b
46b46b46b
47474747
BCLK
CS[4:0]*
CAS3*
CAS2*
CAS1*
CAS0*
WE*
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Fast Page and EDO DRAM Timing
444 n n n n n n n
NET+50/20M Hardware Reference
Fast Page and EDO DRAM Refresh (RCYC = 2)
Figure 76: Fast Page and EDO DRAM Refresh (RCYC = 2)
Fast Page and EDO DRAM Refresh (RCYC = 3)
Figure 77: Fast Page and EDO DRAM Refresh (RCYC = 3)
RF1 RF2 RF3 RF4 RF5 RF8
42
42
46b46b46b
46b46b
46b
46b46b46b
46b46b46b
47474747
BCLK
CS[4:0]*
CAS3*
CAS2*
CAS1*
CAS0*
WE*
RF1 RF2 RF3 RF4 RF8 T1
4242
46b46b46b
46b46b46b
46b46b46b
46b46b46b
47474747
BCLK
CS[4:0]*
CAS3*
CAS2*
CAS1*
CAS0*
WE*
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Timing
SDRAM timing
Tab l e 146 describes the values shown in the SDR AM timing diagrams (Figure 78
through Figure 85) .
Num Characteristic Min Max Unit
31 BCLK high to RW* valid 19 ns
32 BCLK high to BE* valid 1 6 ns‘
33 BCLK high to Address valid 4 15 ns
34 BCLK high to Data Out high impedance 17 ns
35 BCLK high to Data Out valid 18 ns
36a Data In valid to BCLK high (setup) 8 ns
36b BCLK high to Data In invalid (hold) 0 ns
37a TA* valid to BCLK high (setup) 8 ns
37b BCLK high to TA* invalid (hold) 0 ns
38a TEA* valid to BCLK high (setup) 8.5 ns
38b BCLK high to TEA* invalid (hold) 0 ns
40 BCLK high to CS* valid 16 ns
41 BCLK low to OE* valid 14 ns
42 BCLK low to WE* valid 16 ns
43 BCLK high to TA* valid 11 ns
44 BCLK high to TEA* valid 14 ns
Table 146: SDRAM timing values
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SDRAM timing
446 n n n n n n n
NET+50/20M Hardware Reference
SDRAM Read (CAS Latency = 1)
Figure 78: SDRAM Read (CAS Latency = 1)
Notes:
1 Port size determines which byte enable signals are active:
–8-bit port = BE3*
–16-bit port = BE[3:2]
–32-bit port = BE[3:0]
2 The precharge and active commands are not always present. Their presence depends on the
address of the previous SDRAM access .
T1 T2 T1
prechg active read bterm inhibit
31
46b46b46b
46b46b46b46b
46b46b
46b46b
4040
3232
33
3333
4545
4444
4343
36b
36a
38b
38a
37b
37a
A10
BCLK
TA* (output)
TEA*/LAST* (out put)
TA* (i nput)
TEA*/LAST* (input)
PortC3/AMUX
A[13:0]
A[27:20]
BE[3:0]*
read D[31:0]
CS [4 :0]* (C S#)
CAS3* (RAS#)
CAS2* (CAS #)
CAS1* (WE#)
CAS0* (A10/ AP)
RW*
Note 1
Note 2 Note 2
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n n n n n n n 447
Timing
SDRAM Read (CAS Latency = 2)
Figure 79: SDRAM Read (CAS Latency = 2)
Notes:
1 Port size determines which byte enable signals are active:
–8-bit port = BE3*
–16-bit port = BE[3:2]
–32-bit port = BE[3:0]
2 The precharge and active commands are not always present. Their presence depends on the
address of the previous SDRAM access .
3 If CAS Latency = 3, there are 2 NOPs between the read and burst terminate commands.
4 If CAS Latency = 3, there are 3 inhibits after burst terminate.
T1 T2 T1
prechg active read nop bterm inhibit inhibit
31
46b46b46b
46b46b46b46b
46b46b
46b46b
4040
3232
33
3333
4545
4444
4343
36b
36a
38b
38a
37b
37a
A10
BCLK
TA* (output)
TEA*/LAST* (output)
TA* (input)
TEA*/LAST* (input)
PortC3/AMUX
A[13:0]
A[27:20]
BE[3:0]*
read D[31:0]
CS[4:0]* (CS#)
CAS3* (RAS#)
CAS2* (CAS#)
CAS1* (WE#)
CAS0* (A10/AP)
RW*
Note 1
Note 2 Note 2 Note 3 Note 4
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448 n n n n n n n
NET+50/20M Hardware Reference
SDRAM Write (CAS Latency = 2)
Figure 80: SDRAM Write (CAS Latency = 2)
Notes:
1 Port size determines which byte enable signals are active:
–8-bit port = BE3*
–16-bit port = BE[3:2]
–32-bit port = [3:0]
2 The precharge and active commands are not always present. Their presence depends on the
address of the previous S D RAM access. When the active command is not present, pa ra m-
eter 35 (Write data[31:0]) is not valid until the write (T2) cycle.
T1 T2 T1
prechg active write inhibit
31
46b46b46b
46b46b46b46b
46b46b
46b46b
4040
3435
3232
33
3333
4545
4444
4343
38b
38a
37b
37a
A10
BCLK
TA* (out put )
TEA*/LAS T * (output)
TA* (inp ut )
TEA* /LA S T * (input)
PortC3/AMUX
A[13:0]
A[27:20]
BE[3:0]*
write D[31:0]
CS[4:0]* (CS#)
CAS3* (RAS#)
CAS2* (CAS #)
CAS1* (WE#)
CAS0* (A10/ AP)
RW*
Note 1
Note 2 Note 2
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n n n n n n n 449
Timing
SDRAM Burst Read (CAS Latency = 1)
Figure 81: SDRAM Burst Read (CAS Latency = 1)
Notes:
1 Port size determines which byte enable signals are active:
–8-bit port = BE3*
–16-bit port = BE[3:2]
–32-bit port = BE[3:0]
2 The precharge and active commands are not always present. Their presence depends on the
address of the previous SDRAM access .
3 If CAS Latency = 3, th ere are 5 NOPS between t he read and burst termi nate commands.
4 If CAS Latency = 3, there are 3 inhibits after burst terminate.
T1 T2 T2 T2 T2 T1
prechg active read nop nop nop bterm inhibit
31
46b46b46b
46b46b46b46b
46b46b
46b46b
4040
3232
33a
3333
4545
4444
4343
36b
36a
38b
38a
37b37a
A10
BCLK
TA* (output)
TEA*/LAST* (output)
TA* (input)
TEA*/LAST* (input)
PortC3/AMUX
A[13:0]1
A[27:20]
BE[3:0]*
read D[31:0]
CS[4 :0 ]* (CS # )
CAS3* (RAS#)
CAS2* (CAS#)
CAS1* (WE#)
CAS0* (A10/AP)
RW*
Note 3 Note 3
Note 2 Note 2
Note 1
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SDRAM timing
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NET+50/20M Hardware Reference
SDRAM Burst Read (CAS Latency = 2)
Figure 82: SDRAM Burst Read (CAS Latency = 2)
Notes:
1 Port size determines which byte enable signals are active:
–8-bit port = BE3*
–16-bit port = BE[3:2]
–32-bit port = BE[3:0]
2 The precharge and active commands are not always present. Their presence depends on the
address of the previous SDRAM access .
3 If CAS Latency = 3, there are 5 NOPs between the read and burst terminate commands.
4 If CAS Latency = 3, there are 3 inhibits after burst terminate.
T1 T2 T2 T2 T2 T1
prechg active read nop nop nop nop bterm inhibit inhibit
31
46b46b46b
46b46b46b46b
46b46b
46b46b
4040
3232
33a
3333
4545
4444
4343
36b
36a
38b
38a
37b37a
A10
BCLK
TA* (output)
TEA*/LAST* (output)
TA* (input)
TEA*/LAST* (input)
PortC3/AMUX
A[13:0]1
A[27:20]
BE[3:0]*
read D[31:0]
CS[4:0]* (CS#)
CAS3* (RAS#)
CAS2* (CAS#)
CAS1* (WE#)
CAS0* (A10/AP)
RW*
Note 1
Note 2 Note 2 Note 3 Note 4
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n n n n n n n 451
Timing
SDRAM Burst Write (CAS Latency = 2)
Figure 83: SDRAM Burst Write (CAS Latency = 2)
Notes:
1 Port size determines which byte enable signals are active:
–8-bit port = BE3*
–16-bit port = BE[3:2]
–32-bit port = BE[3:0]
2 The precharge and active commands are not always present. Their presence depends on the
address of the previous S D RAM access. When the active command is not present, pa ra m-
eter 35 (Write data[31:0]) is not valid until the write (T2) cycle.
T1 T2 T2 T2 T2 T1
prechg active write write write write inhibit
31
46b46b46b
46b46b46b46b
46b46b
46b46b
4040
3232
3435
33
3333
4545
4444
4343
38b
38a
37b37a
A10
BCLK
TA* (output)
TEA*/LAST* (output)
TA* (in put )
TEA*/LAST* (input )
PortC3/AMUX
A[13:0]
A[27:20]
write D[31:0]1
BE[3:0]*
CS[4:0]* (CS#)
CAS 3* (RAS#)
CAS2 * (CA S#)
CAS1 * (W E#)
CAS0* (A10/AP)
RW*
Note 1
Note 2 Note 2
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SDRAM timing
452 n n n n n n n
NET+50/20M Hardware Reference
SDRAM Refresh Command
Figure 84: SDRAM Refresh
Prechg Inhibit Refresh
46b
46b46b
46b46b
46b46b46b
40404040
BCLK
CS[4:0]* (CS#)
CAS3* (RAS#)
CAS2* (CAS#)
CAS1* (WE#)
CAS0* (A10/AP)
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n n n n n n n 453
Timing
SDRAM Load-Mode Command
Figure 85: SDRAM Load Mode Command
Prechg NOP Load
3333
46b46b46b
46b46b
46b46b
46b46b46b
4040
OP CODE
BCLK
CS[4:0]* (CS#)
CAS3* (RAS#)
CAS2* (CAS#)
CAS1* (WE#)
CAS0* (A10/AP)
A[13:0]
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External DMA timing
454 n n n n n n n
NET+50/20M Hardware Reference
External DMA timing
Table 147 describes the values shown in the external DMA timing diagrams
(Figure 86 and Figure 87).
Num Characteristic Min Max Unit
50 BCLK high to DACK* valid 26 ns
51 BCLK high to DONE* (output) valid 27 ns
52 DACK* low to DREQ* high 0 ns
53a DREQ* valid to BCLK high (setup) 11 ns
53b BCLK high to DREQ* valid (hold) 0 ns
54a DONE* (input) valid to BCLK high (setup) 14 ns
54b BCLK high to DONE* (input) valid (hold) 0 ns
Table 147: External D MA timing values
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n n n n n n n 455
Timing
Exter nal Fly- by DMA
Figure 86: External Fly-by DMA
Notes:
1 TheTA* signal is shown here for reference only. See the following timing diagram sections
for informatio n abo ut TA* timing :
–"SR A M timing," beginning on page 426.
–"Fast Page and EDO DRAM Timing," beginning on page 436.
–"SDRAM timing," b eginning on page 445.
2 The memory signals consist of the following types:
The timin g of these sign als d ep ends o n ho w the me mory i s c onfig ured. See the foll owing
sections for information:
–"SR A M timing," beginning on page 426.
T1 TW T2
5151
5050
54b
54a
52
53b53a
Note3
Note 1
BCLK
TA* (output or input)
Memory Signals
DREQ* [PORT(A/B)6]
DACK* [PORT(A/B)6]
DONE* [PORT(A/B)6] (output)
DONE* [PORT(A/B)6] (input)
Note 2
DATA[31:0] RW
ADDR[27:0] OE*
BE[3:0] WE*
CS/RAS[4:0] PORTC3/AMUX
CAS[3:0]
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External DMA timing
456 n n n n n n n
NET+50/20M Hardware Reference
–"Fast Page and EDO DRAM Timing," beginning on page 436.
–"SDRAM timing," b eginning on page 445.
3 The DONE* signal works as an input only when the DMA channel is configured as fly-by
write.
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n n n n n n n 457
Timing
External Memory-to-Memory DMA
Figure 87: External Memory-to-Memory DMA
Notes:
1 There is somet imes a null period bet w een memory cycles.
2 The TA* signal is shown here for reference only. See the following timing diagram sections
for informatio n abo ut TA* timing :
–"SR A M timing," beginning on page 426.
–"Fast Page and EDO DRAM Timing," beginning on page 436.
–"SDRAM timing," b eginning on page 445.
3 The memory signals consist of the following types:
T1 TW T2 Note-1 T1 TW T2
51515151
50505050 5252
53b
53a
53b
53a
Note 4
Note 5
Note 2
BCLK
TA* (input or output)
Memory Signals
CS[4 :0]* (Mem Read CS* )
CS[4 :0]* (Mem Write CS*)
DREQ * [P OR T(A/B)6]
DACK * [P OR T(A/B)6]
DONE* [POR T (A/B)6]2 (output)
Note 3
DATA[31:0] RW
ADDR[27:0] OE*
BE[3:0] WE*
CS/RAS[4:0] PORTC3/AMUX
CAS[3:0]
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External DMA timing
458 n n n n n n n
NET+50/20M Hardware Reference
The timin g of these sign als d ep ends o n ho w the me mory i s c onfig ured. See the foll owing
sections for information:
–"SR A M timing," beginning on page 426.
–"Fast Page and EDO DRAM Timing," beginning on page 436.
–"SDRAM timing," b eginning on page 445.
4 The timing of the chip select a ssociated with the buffer de scriptor’s source address depends
on how that chip select is configured.
5 The timing of the chip select associated with the buffer descriptor’s destination address de-
pends on how that chip select is configured.
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n n n n n n n 459
Timing
SPI timing
SPI Master mode 0 and 1 (two-byte transfer)
Table 148 describes the values shown in Figure 88, "SPI Master mode 0 and 1 (two-
byte transfer)."
Num Characteristic Min Max Unit
130 Data In valid to mode 0 rising clock (setup) 20 ns
131 Mode 0 rising clock to Data In valid 0 ns
132 Data In valid to mode 1 fall ing clock (setup) 20 ns
133 Mode 1 falling clock to Data In valid (hold) 0 ns
134 Enable low to mode 0 first rising clock 1.5 Bit-time
135 Enable low to mode 1 first falling clock 1.5 Bit-time
136 Mode 0 falling edge to Data Out valid -TSYS TSYS ns
137 Mode 1 rising edge to Data Out valid -TSYS TSYS ns
138 Mode 0 last falling clock to Enable high 1.5 Bit-time
139 Mode 1 last rising clock to Enable high 1.5 Bit-time
140 Enable low to Data Out val id -TSYS TSYS ns
Table 148: SPI Mast er mode 0 and 1 timi ng values
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SPI timing
460 n n n n n n n
NET+50/20M Hardware Reference
Figure 88: SPI Master mode 0 and 1 (t wo-byte transfer)
SPI Slave mode 0 and 1
Table 149 describes the values shown in Figure 89, "SPI Slave mode 0 and 1 (two-
byte transfer)."
137136140
139
138
135
134
133
132
131
130
LSB LSB
MSB MSB LSB
SPI CLK Out (mode 0)
SPI CLK Out (mode 1)
SPI En able
SPI Dat a In
SPI Data Out
MSB
MSB
Num Characteristic Min Max Unit
Mode 0
141 SPI clock high to TXD valid 3*TSYS 4*TSYS ns
142 SPI Enable low to SPI clock high (setup) 0 ns
143 RXD Input valid to SPI clock high (setup) 3.4 ns
144 SPI clock high to RXD Input change (hold) 4*TSYS ns
145 SPI clock high to SPI Enable high (hold) 4*TSYS ns
Mode 1
146 SPI clock low to TXD valid 3*TSYS 4*TSYS ns
147 SPI Enable low to SPI clock low (setup) 0 ns
148 RXD Input valid to SPI clock low (setup) 3.4 ns
Table 149: SPI Slave mode timing valu es
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n n n n n n n 461
Timing
Figure 89: SPI Slave mode 0 and 1 (two-byte transfer)
MIC timing
Table 150 describes the values shown in the MIC timing diagrams (Figure 90
through Figure 92). Note that the data shown are independent of SYS_CLK and
BCLK settings.
149 SPI clock low to RXD Input change (hold) 4*TSYS ns
150 SPI clock low to SPI Enable high (hold) 4*TSYS ns
Num Characteristic Min Max Unit
Table 149: SPI Slave mode timing valu es
146141140
150
145
147
142
149
148
144
143
MSB LSB MSB LSB
MSB LSB MSB LSB
SPI CLK Out (mode 0)
SPI CLK Out (mode 1)
SPI Enable
SPI Dat a In
SPI Data Out
Num Characteristic Note Min Max Unit
70a PCS*/PDACK * low to PRW * sample d 1 TSYS - 2.5 ns
70b PCS*/PDACK* low to PRW* hold time 1 4*TSYS ns
71 Read Data Valid to PACK* valid TSYS ns
Ta ble 150: M IC timing val ues
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MIC timing
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NET+50/20M Hardware Reference
72 PCS*/PDACK* low to PACK* low 3 TSYS 6*TSYS ns
72a PCS* low to PACK* low 4 7*TSYS Determined by shared RAM
access time ns
72b PCS*/PACK* low to PACK* low 5 2*TSYS 4*TSYS ns
72c PCS* low to PACK* valid (shared RAM only) 6 7*TSYS Determined by shared RAM
access time ns
73 PCS*/PDACK* high to PDATA high
impedance 07.84 ns
74 PCS*/PDACK* high to PACK* high 0 13 ns
75 PCS*/ PDACK * low to PACK* (wait-) low 0 14 ns
76a PCS*/PDACK* low to Write Data valid 2*TSYS ns
76b PCS*/PDACK* high to Write Data hold time 0 ns
77a PCS*/PDACK* width high (recovery) 16 ns
77b PACK* low to PCS*/PDACK* high (hold) 8 0 ns
77c PDACK* minimum low 120 ns‘
78a Address valid to PCS* low 0 ns
78b PCS* high to Address hold ti me 0 ns
79 PCS* low to PINT1/2 change (write) 3*TSYS 5*TSYS ns
80a PDACK* low to PDRQI*, PDRQO* high 5*TSYS NS
80b PDRQO* high width 5*TSYS ns
80c PDRQI* high width 4*TSYS ns
80d PDACK* low to PINT2 low 14 ns
80e PDACK* high to PINT2 high 15 ns
81 PCS*/ PDACK* low to PEN* low 2 1*TSYS 3*TSYS ns
82 PCS*/PDACK* high to PEN* high 2 0 13 ns
83 PCS*/ PDACK * low to PBRW* low 2 1*TSYS 2*TSYS ns
84a PRW* valid to PDACK* low (setup) 1 0 ns
84b PDACK* high to PRW* hold time 1 0 ns
Num Characteristic Note Min Max Unit
Ta ble 150: M IC timing val ues
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n n n n n n n 463
Timing
Notes:
1 Parameters 70a and 70b apply only when the ENI FAST bit is set to 0. When ENI FAST is
set to 1, par ameters 84a and 84b app ly.
2 The PEN* and P BRW* signals cont rol an external bi -directional dat a bus transceive r for
the PDATA bus that can drive onl y 2mA.
3 Parameter 72 applies only to ENI registers while FAST is set to 0. This specification does
not apply to shared RAM access.
4 Parameter 72a applies to all shared RAM accesses wh en FAST is set to 0. The max speci-
fication for PCS* to PACK* valid is larger for shared RAM accesses. The additional delay
depends o n the speed of the ex terna l RAM assig ned to provide the ph ysica l shared RAM.
Consequen tly, the max specificat i on for shared RAM accesse s is system-dependent.
5 Parameter 72b applies to ENI register accesses when FAST is set to 1.
6 Parameter 72c applies to ENI shared RAM accesses when FAST is set t o 1.
7 Parameter 85 applies when FAST is set to 0. Parameter 85a applies when FAST is set to 1.
8 Parameter 77c can be reduc ed to (3*TSYS) when FAST is set to 1.
85 PDACK* low to PDATA valid 7 3*TSYS 5*TSYS ns
85a PDACK* low to P DATA val id 7 1*TSYS 2*TSYS ns
Num Characteristic Note Min Max Unit
Ta ble 150: M IC timing val ues
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MIC timing
464 n n n n n n n
NET+50/20M Hardware Reference
ENI Shared RAM and Register Cycle timing
Figure 90: ENI Shared RAM and Register Cycle timing
8383
82818281
75
72
75
74
72
75
747274
72
76a73
70a70a
79
77b
71
77b
71
76b
70b70b
78b
78a
78b78a
77a77a
READ WRITE
PCS*
PINT[2:1]*
PA[15:0]
PRW*
PDATA[15:0]
PACK* (back-)
PACK* (wait-/ready)
PEN*
PBRW*
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n n n n n n n 465
Timing
ENI Single Direction DMA timing
Figure 91: ENI Single Direction DMA timing
8383
82818281
7572
75
7472
75
7472
7472
85a
85
76b76a
84b84b
80e80d80e80d
77b77b
71
77b
71
77b
73
84a
84a
80c80c80c80c
77c77c77a77c 77a77c
Memory to IO DMA IO to Memory DMA
PDACK*
PINT2
PRW*
PDATA[15:0]
PACK* (ack-)
PACK* (wait-/ready)
PEN*
PBR W*
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MIC timing
466 n n n n n n n
NET+50/20M Hardware Reference
ENI Dual Direction DMA timing
Figure 92: ENI Dual Direction DMA timing
8383
82818281
7572
75
7472
75
7472
7472
85a
85
76b76a
84b84b
80c80a
80b80a
77b77b
71
77b
71
77b
73
84a
84a
77c77c77a77c 77a77c
Memory to IO DMA IO to Memory DMA
PDACK*
PDRQI*
PDRQO*
PRW*
PDATA[15:0]
PACK* (ack-)
PACK* (wait-/ready)
PEN*
PBRW*
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n n n n n n n 467
Timing
Ethern et timi ng
Table 151 describes the values shown in the Ethernet timing diagrams (Figure 93
through Figure 95) .
Num Characteristic Min Max Unit
90 TXCLK high to TXD, TXDV, TXER valid 17 ns
91a RXD, RXER, RXDV valid to RXCLK high (setup) 8 ns
91b RXCLK high to RXD, RXER, RXDV hold time 0 ns
91c RXCLK high to RXD hold time 0 ns
92 MDC high to MDIO change 40 50 ns
93a MDIO valid to MDC high (setup) 10 ns
93b MDC high to MDIO hold time 0 ns
94 RXCLK high to RPSF* change 6.5 ns
95a REJECT* valid to RXCLK high (setup) 2.6 ns
95b REJECT* valid from RXCLK high (hold) 0 ns
96 CRS low to RXCLK idle (bit-times) 27 Bit-times
Table 151: Ethernet t iming va lues
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Ethernet timing
468 n n n n n n n
NET+50/20M Hardware Reference
Ethernet timing diagram
Figure 93: Ethernet timing
Ethernet R eceive Cloc k Idle
Figure 94: Ethernet Receive Clock Idle
92
90
90
90
93b93a
91c
91b91a
TXCLK
TXD[3:0]
TXEN
TXER
RXCLK
RXD[3:0]
RXER
RXDV
MDC
MDIO (output)
MDIO (input)
96
RXCLK
CRS
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n n n n n n n 469
Timing
Extern al Ethernet CAM Filtering
Figure 95: External Ethernet CAM Filtering
JTAG timing
Table 152 describes the values shown in Figur e 96, "JTAG timing."
Note:
TRST* has an internal current sink. On production units, do not leave
TRST* pulled low. The noise margin on inputs at a logic 0 is only a few
tenths of a volt. NetSilicon recommends tying TRST* to RESET* on
production units.
95b
95a
9494
91b
91a
5D 2 1 3456
RXCLK
RXD
RPSF* (PORTB1 )
REJECT* (PORTB5)
Num Characteristic Min Max Unit
100 TCK low to TDO valid 0 33.5 ns
101 TCLK low to TDO high impedance 0 32.3 ns
102a TDI, TMS valid to TCK high (setup) 0.72 ns
102b TCK high to TDI, TMS hold time 1.3 ns
103 TCK cycle time 31.2 ns
104 TCK pulse width 15.6 ns
105 TRST low time 27 ns
Table 152: JTAG timing values
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1284 Port Multiplexing timing
470 n n n n n n n
NET+50/20M Hardware Reference
Figure 96: JTAG timing
1284 Port Multiplexing timing
Table 153 describes the values shown in Figur e 97, "1284 Port Multiplexing
timing."
103
104 103
104
102a 102b
105105 106
100 101
TCK
TDO
TDI
,
TMS
TRST
*
10
4
Num Characteristic Min Max Unit
110 PDATA valid to PCLKDx or PCLKCx high (setup) TSYS ns
111 PCLKDx and PCLKCx time high (width) TSYS ns
112 PCLKSx and PCLKC x low to PDATA valid (hold) TSYS ns
113 PDATA high impedance to POEx* active low (read only) TSYS ns
114 POEx* minimum low time (read only) TSYS ns
114a POEx* high to PDATA driven (read only) TSYS ns
Table 153: 1284 P ort Multiplexi ng timing val ues
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Timing
Figure 97: 1284 Port Multiplexing timing
1284 Compatibility mode timing
Table 154 and table 155 describe the timing values shown in Figure 98, "1284
Compatibility m ode timing."
113 114114
111111
114a112110
112
111111
110
PCLKDx
PDATA<7:0>
PCLKCx
POEx*
Num Characteristic Min Max Unit
115 DATA valid to STROBE* low (setup) STROBE ns
116 STROBE* width low STROBE ns
117 STROBE* low to BUSY (input) high 0 ns
119 BUSY low to DATA change (hold) 3*TSYS ns
120 STROBE* high to DATA change (hold) STROBE ns
121 BUSY low to STROBE* (low) 3*TSYS ns
Table 154: 1284 Com patibility SLO W mode tim ing (FAST = 0)
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1284 Compatibility mode timing
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NET+50/20M Hardware Reference
Figure 98: 1284 Compatibility mode timing
Num Characteristic Min Max Unit
115 DATA valid to STROBE* low (setup) STROBE ns
116 STROBE* width low STROBE ns
117 STROBE* low to BUSY input (high) 0 ns
119 BUSY low to DATA change (hold) 3*TSYS ns
120 STROBE* high to DATA change (hold) 3*TSYS ns
121 BUSY low to STROBE* (low) 3*TSYS ns
Table 155: 1284 Com patibility FAST mode timing (FAST = 1)
119119
120118
116121 117 116
115
STROBE*
DATA
BUSY
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Timing
Forward ECP mode timing
Table 156 and Table 157 describe the timing values shown in Figure 99, "1284
Forward ECP mode timing."
Figure 99: 1284 Forward ECP mode timing
Num Characteristic Min Max Unit
115 DATA valid to STROBE* low (setup) STROBE ns
116 STROBE* width low STROBE ns
117 STROBE* low to BUSY (input) high STROBE ns
118 BUSY high to STROBE* high (hold) 3*TSYS ns
120 STROBE* high to DATA change (hold) STROBE ns
121 BUSY low to STROBE* (low) 3*TSYS ns
Table 156: 1284 SLO W Forward ECP m ode timing ( FAST = 0)
Num Characteristic Min Max Unit
115 DATA valid to STROBE* low (setup) 3*TSY ns
117 STROBE* low to BUSY (input) high 0 ns
118 BUSY high to STROBE* high (hold) 3*TSYS ns
120 STROBE* high to DATA change (hold) 3*TSYS ns
121 BUSY low to STROBE* (low) 3*TSYS ns
Table 157: 1284 FA ST Forward ECP mode timing (FAST = 1)
120118
121 117115
STROBE*
DATA
BUSY
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Crystal oscillator specifications
474 n n n n n n n
NET+50/20M Hardware Reference
Crystal oscillat or specifications
Quartz crystals can be chosen from a wide range of manufactur ers, and it is
difficult to specify only one rule. The crystals’ characteristics vary significantly,
depending on their resonant frequency. The choice must always be parallel
resonance for the NET+50 chip with a load capacitance CL of 8pF. If the crystal
r ecommended load capacitance is greater, additional capacitors must be added
external to XTAL1 and XTAL2 .
If the crystal used has a drive level smaller than the drive level specified, a series
resistor can be added between XTA L 2 and the crystal connection.
Instead of using the XTAL1/ XTAL2 crystal oscillator circuit, the NET+50 chip can
be driven using an external TTL oscillator. The TTL oscillator provides a single
TTL clock input on the XTAL 1 pin. The XTAL2 pin is left unconnected in this
configuration. To use this configuration, the PLL TST* pin must be driven low. Note
that when this configuration is used, the inter nal PLL is bypassed and disabled.
Table 158 details the parameters for the external crystal:
Sym Parameter Conditions Min Typ Max Unit
f0 Operating frequency 16 Mhz 16 20 Mhz
Tsu Startup tim e 2 ms
C1 Internal capacitance XTAL1/Gnd 14.8 16 17.1 pF
C2 Internal capacitance XTAL2/Gnd 14.8 16 17.1 pF
CL Local capacitance XTAL1/XTAL2 7.4 8 8.6 pF
DL Drive level 50 100 150 uW
Rs Se ries resi st ance Crystal 100 Ohm
Cs Sh unt capacitance Crystal pF
Table 158: Crystal specification
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ARM Exceptions
APPENDIX A
This appendix provides descriptions of the ARM exceptions outlined in Chapter
4, "Working with the CPU."
Note:
The information in this appendix applies to both the NET+50 and
NET+20M chips, unless otherwise noted.
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About ARM exceptions
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NET+50/20M Hardware Reference
About ARM exceptions
An exception occurs when the normal flow of a program is stopped temporarily.
There are sev en exceptio ns that ca n in t er rupt th e ARM p roce sso r :
Reset
Undefined
SWI
Prefetch abort
Data abo rt
IRQ
FIRQ
Reset ex ception
A reset exception is the highest priority exception. When the ARM is removed
from reset, the ARM7TDMI:
1Overwrites 5BVYF and 6365BVYF by copying the current values of
the PC (program counter) and CPSR into them. The value of the saved
PC and SPSR is not defined.
2Forces the CPSR M field to 10011 (Supervisor mod e), sets the I and F bits in
the CPSR, and clears the CPSR T bit (back to ARM mode).
3Forces the sy stem to fetch the next instruction from address 0x00.
4Resume s execution in ARM state.
Undefined exception
When the ARM7TDMI comes acr o ss an instruction it cannot handle, it takes the
undefined instruction trap. This exception can extend either the THUMB or ARM
instruction set by software emulation .
After emulating the failed instruction, the trap handler should execute the
following instructio n irrespective of the state (ARM or THUMB):
02963&5BXQG
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ARM Exceptions
This instruction restores the PC and CPSR, and returns to the instruction following
the undefined instruction.
SWI exception
The software interrupt instruction (SWI) is used to enter supervisor mode, usually
to request a particular supervisor function. An SWI handler should re turn by
executing the following instruction, irrespective of the state (ARM or THUMB):
02963&5BVYF
This restores the PC and CPSR, and returns to the instruction following the SWI.
Abort exception
An abo r t in di ca t es that the current memor y ac ce ss cannot b e co mp leted. It ca n be
signaled by the external ABORT input. The ARM7TDMI checks for the abort
excep t i o n dur ing memory a cc es s cy cl e s.
There are two typ e s of a bor t :
Prefetch Abort. A prefetch abort takes place during an instruction
pr efetch. If a pr efet ch abort occurs, th e pr efetch inst ruct ion is mark ed as
invalid but the exception is not taken until th e instruction reaches the
head of the pipeline. The abort does not take place, however, if the
instruction is not executed; for example, if a branch occurs while the
instruc tion is i n the pipeline.
Data Abort. A data abort takes place during a data operand access. If a
data abort occurs, the action taken depends on the instruction type:
–Single data transfer instructions (LDR, STR) write back modified base
registers; the abort handler must be aware of this.
–The swap instruction (SWP) is aborted as though it had not been
executed.
–Block data transfer instructions (LDM, STM) complete. If write-back is
set, the base is updated. If the instruction would have overwritten the
base with data (that is, the data has the base in the transfer list),
overwriting is prevented. All register overwriting is prevented after an
abort is indicated, which means that R15 (always the last register to be
transferred) is preserved in an aborted LDM instruction.
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NET+50/20M Hardware Reference
The abort mechanism allows the implementation of a demand-paged virtual
memory system. In this type of system, the processor is allowed to generate
arbitrary addresses. When the data at an address is unavailable, the Memory
Management Unit (MMU) signals an abort. The abort handler must then work out
the cause of the abort, make the requested data available, and retry the aborted
instruction. The application program needs no knowledge of the amount of
memory available to it, and its state is not affected by the abort.
The ha ndl e r ex e cu t es one of the foll ow ing i nst ructio ns, irrespect i v e o f th e st a t e
(ARM or THUMB), af ter fixing the caus e of the abort:
For a prefetch abort: 68%6 3&5BDEW
For a data abort: 68%6 3&5BDEW
IRQ excepti on
The I R Q (i n t er rupt request) exc ep t i o n i s a no r mal inter rupt so urc ed by t he
NET+50 interrupt controller. IRQ has a lower priority than FIRQ and is masked
when a FIRQ sequence is entered. You can disable the IRQ interrupt at any time by
setting the I bit in the CPSR to 1. You must be in privileged (non-user) mode to do
this, however.
The IRQ handler should leave the interrupt by executing the following instruction,
irrespective of the state (ARM or THUMB):
68%6 3&5BLUT
FIRQ exception
The FIRQ (fast interrupt r equest) exception supports a data transfer or channel
process. In ARM state, FIRQ has enough registers to remove the need for register
saving, which minim i zes context switching ove rhead.
The only two internal peripherals that can generate a FIRQ interrupt ar e the GEN
module built-in timers and the GEN module watch-dog timer.
The FIRQ handler should leave the interrupt by executing the following execution,
irrespective of the state (ARM or THUMB):
68%6 3&5BILUT
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ARM Exceptions
You can disable the FIRQ interrupt by setting the CPSR F flag to 1; you must be in
non-user mode, however. If the F flag is clear, the ARM7TDMI checks for a low
level on the ou tput of the FIRQ synchronizer at the en d of each instruction.
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NET+20M Chip Package
APPENDIX B
The NET+20M ch ip can be used in any embedded environment requiring
networking services in an Ethernet LAN. Application-specific hardware can be
attached to the NET+20M system bus for custom applications that use the
NET+20M internal RISC processor.
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NET+20M chip pinout
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NET+50/20M Hardware Reference
NET+20M chip pinout
The NET+20M is a 208 ball grid array (BGA) chip. Figure 100 shows the NET+20M
BGA pinout.
Figure 100: NE T+20M BGA p inout (bottom vi ew)
Table Information and Tables
Table 159 throug h Table 165 identify and desc ri be the ball numbe r assig n ment s
contained in the NET+2M chip. Each table pertains to an interface, and contains
the following information:
Signal column. Identi fies the p in name for each I /O sign al. Some s ignal s
have multiple modes and are identified accordingly. You configure the
mode through firmware using a configuration register. Some modes may
requir e hardware configuration during a RESET condition.
BGA column. Identifies the ball number assignment for a specific I/O
signal. A dagger next to t he pin number ind icates that t he pin is an
input current s ource.
I/O column. Indicates whether the signal is input (I), output (O), or both
(I/O).
Pi n 1 cor ner
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NET+20M Chip Package
OD (D r iv e ) co lu mn. Indicates the drive strength of an output buffer.
The NET+50 chip uses one of three driver types:
–2mA
–4mA
–8mA
System bus interface
Signal BGA I/O OD Description
BCLK T10 O 8 Synchronous bus clock
ADDR27 CS0OE* F4I/O 4 Address bus
ADDR26 CS0WE* F3I/O 4
ADDR25 BLAST* E2I/0 4
ADDR24 D2I/O 4
ADDR23 E3I/O 4
ADDR22 E4I/O 4
ADDR21 D1I/O 4
ADDR20 C2I/O 4
ADDR19 D3I/O 4
ADDR18 C1I/O 4
ADDR17 B1I/O 4
ADDR16 B2I/O 4
ADDR15 B3I/O 4
ADDR14 A3†I/O 4
ADDR13 A4I/O 4
ADDR12 B4I/O 4
ADDR11 C3I/O 4
ADDR10 A5I/O 4
Ta ble 159: NE T+20M BGA Chip Pinout - System bus i nterface
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NET+50/20M Hardware Reference
ADDR9 D4I/O 4
ADDR8 C4I/O 4
ADDR7 B5I/O 4
ADDR6 A6I/O 4
ADDR5 D5I/O 4
ADDR4 C5I/O 4
ADDR3 B6I/O 4
ADDR2 A7I/O 4
ADDR1 D6I/O 4
ADDR0 C6I/O 4
DATA31 T3 I/O 4 Data bus
DATA30 R4 I/O 4
DATA29 U3 I/O 4
DATA28 U2 I/O 4
DATA27 R2 I/O 4
DATA26 R1 I/O 4
DATA25 P1 I/O 4
DATA24 P2 I/O 4
DATA23 R3 I/O 4
DATA22 N1 I/O 4
DATA21 P4 I/O 4
DATA20 P3 I/O 4
DATA19 N2 I/O 4
DATA18 M1 I/O 4
DATA17 N4 I/O 4
DATA16 L1 I/O 4
DATA15 M4 I/O 4
Signal BGA I/O OD Description
Ta ble 159: NE T+20M BGA Chip Pinout - System bus i nterface
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NET+20M Chip Package
DATA14 M3 I/O 4
DATA13 L2 I/O 4
DATA12 K1 I/O 4
DATA11 L4 I/O 4
DATA10 L3 I/O 4
DATA9 K2 I/O 4
DATA8 J1 I/O 4
DATA7 K4 I/O 4
DATA6 K3 I/O 4
DATA5 J4 I/O 4
DATA4 J3 I/O 4
DATA3 H2 I/O 4
DATA2 G1 I/O 4
DATA1 H4 I/O 4
DATA0 H3 I/O 4
TS* NO CONNECT
BE3* G2 I /O 2 Byte enable D31:D24
BE2* F1 I/O 2 Byte enable D23:D16
BE1* G4 I /O 2 Byte enable D15:D08
BE0* G3 I /O 2 Byte enable D07:D00
RW* U4 I/O 2 Transfer direction
TA* R5I/O 8 Data transfer acknowledge
TEA* T4I/O 8 Transfer error/Last acknowledge
BR* NO CONNECT
BG* NO CONNE CT
BUSY* NO CONNECT
Signal BGA I/O OD Description
Ta ble 159: NE T+20M BGA Chip Pinout - System bus i nterface
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NET+20M chip pinout
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Chip select controller
Ethernet int erface
Signal BGA I/O OD Description
CS0* T11 O 4 Chip select (Boot select)
CS1*/RAS1* R12 O 4 Chip select/DRAM RAS*
CS2*/RAS2* P12 O 4 Chip select/DRAM RAS*
CS3*/RAS3* U11 O 4 Chip select/DRAM RAS*
CS4*/RAS4* T12 O 4 Chip select/DRAM RAS*
CAS3*/SDRAS* T13 O 4 DRAM column strobe D31:24/SDRAM RAS
CAS2*/SDCAS* U12 O 4 D RAM column strobe D23:16/ SDRAM RAS
CAS1*/SDWE* P13 O 8 DRAM column strobe D15:08/SDRAM RAS
CAS0*/SD(AP) R13 O 4 DRAM column strobe D07:00/SDRAM RAS
WE* R11 O 4 Write enable
OE* P11 O 4 Output enable
Ta ble 160: NET+20 M BGA Chip Pinout - Chip select cont roller
Signal BGA I/O OD Description
MII 10BaseT MII 10BaseT
MDC LB* D7 O 2 MII clock Loopback enable
MDIO UTPSTP* C7I/O 2 MII data Cable type
TXCLK TXCLK B8 I TX clock
TXD0 TXD A9 O 2 TX data 0 TX data
TXD1 PDN* (OD) D8 O 2 TX data 1 Power down
TXD2 NTHRES C8 O 2 TX data 2 Normal threshold
TXD3 THIN D9 O 2 TX data 3 Enable Thinnet
Ta ble 161: N ET+20M B GA Chip Pi nout - Ethernet interface
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NET+20M Chip Package
UARTS-SPI-GPIO
Important:
The NET+20M supports only 16 GPIO/special function pins. Any
combination of pins is acceptable.
TXER L TE C9 O 2 TX code error L ink test enable
TXEN TXEN B10 O 2 TX enable
COL TXCOL A11 I Collision
CRS RXCRS D10 I Carrier sense
RXCLK RXCLK C10 I RX clock
RXD0 RXD B11 I RX data 0 RX data
RXD1 MANSENSE A12 I RX data 1 Sense jumper
RXD2 JABBER D11 I RX data 2 J abber
RXD3 REVPOL C11 I RX data 3 Reverse polarit y
RXER LINKPUL* B12 I RX error Link pulse detection
RXDV AUTOMAN A13 I RX data valid 10B2 selected
Signal BGA I/O OD Description
Ta ble 161: N ET+20M B GA Chip Pi nout - Ethernet interface
Signal BGA I/O OD SPI Slave Mode SPI Master Mode
PORTA7 TXDA G17I/O 2 SPI-S-TXD-O-A SPI-M-TXD-O-A
PORTA6 DTRA*/DRQ1* F16I/O 2
PORTA5 RTSA* E15I/O 2
PORTA4 RXCA E14I/O 2 SPI-S-CLK-I-A SPI-M-CLK-O-A*
PORTA3 RXDA F17I/O 2 SPI-S-RXD-I-A SPI-M-RXD-I-A
PORTA2 DSRA*/DAK1* E16I/O 2
PORTA1 CTSA* D15I/O 2
PORTA0 DCDA* DON1* D14I/O 2
Ta ble 162: NE T+20M BGA Pinout - U ARTS-SPI-GPIO
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NET+50/20M Hardware Reference
Clock generation/system reset
PORTB7 TXDB E17I/O 2 SPI-S-TXD-O-B SPI-M-TXD-O-B
PORTB6 DTRB*DRQ2* C15I/O 2
PORTB5 RTSB* D16I/O 2 Reject* Ethernet package
PORTB4 RXCB D17I/O 2 SPI-S-CLK-I-B SPI-M-CLK-O-B*
PORTB3 RXDB C17I/O 2 SPI-S-RXD-I-B SPI-M-RXD-I-B
PORTB2 DSRB*/DAK2* C16I/O 2
PORTB1 CTSB* B16I/O 2 RPSF* Ethernet frame boundary
PORTB0 DCDB*/DON2* A16I/O 2
PORTC7 TXCA A15I/O 2 SPI-S-EN-I-A SPI-M-EN-O-A*
PORTC6 RIA*/IQRO* C14I/O 2
PORTC5 TXCB B15I/O 2 SPI-S-EN-I-B SPI-M-EN-O-B
PORTC4 RIB* A14I/O 2
PORTC3 AMUX D13I/O 8 Interr u p t 3
PORTC2 C13I/O 8 Interru pt 2
PORTC1 B14I/O 8 Interru pt 1
PORTC0 B13I/O 8 Interru pt 0
Signal BGA I/O OD SPI Slave Mode SPI Master Mode
Ta ble 162: NE T+20M BGA Pinout - U ARTS-SPI-GPIO
Signal BGA I/O OD Description
XTAL1 U7 I Crystal oscillator circuit
XTAL2 T8 O
PLLVDD (2.5V) U8 2.5 V PLL clean power
PLLLPF P9 PLL loop filter capacitor
PLLVSS R9 PLL clean ground
Ta ble 163: NE T+20M BGA Chip Pinout - Clock gene ration/system reset
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NET+20M Chip Package
JTAG port for ARM core
Power supp ly
PLLTST* (2.5V) P8IPLL test mode
BISTEN* R10I Enable internal BIST operation
SCANEN* P10I Enable internal SCAN testing
System reset
RESET* T2ISystem reset
Signal BGA I/O OD Description
Ta ble 163: NE T+20M BGA Chip Pinout - Clock gene ration/system reset
Signal BGA I/O OD Description
TDI T61 Test data in
TDO U5 O 2 Test data out
TMS R7I Test mode select
TRST* R8 I Test mode reset. This is a current input sink.
TCK P7 I Test mode clock
Ta ble 164: NET+20 M BGA Chip Pinout - JTAG port for ARM core
Signal Mode Ball Number Description
VCCDC 3.3V DC BGA F15, B17, C12, A2, M2, U9 I/O steady state (6 pairs)
VSSDC GND Retur ns BGA F14, A17, D12, A1, N3, U10
VCCAC 3.3V BGA A8, E1, T1, U16 I/O switching (4 pairsa)
VSSAC GND Retur ns BGA B7, F2, U1, U17
Ta ble 165: NET+20 M BGA Chip Pinout - Power supply
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NET+20M chip pinout
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NET+50/20M Hardware Reference
Additional information about NET+20M pins
The following pins are reserved:
All ou tputs drive TTL levels. Output s drive to 0.4 V maximum on low
and 2.4 V maximum on high.
The following pins require a 2.5 V input level:
–XTAL1 (U7)
–PLLTST (P8)
–PLLVDD (U8)
TRST* (R8) is the only pin that is an input current sink.
VDDCO 2.5V BGA K17, A10, H1, T7 Core power (4 pairs)
VSSCO GND Retur ns BGA J16, B9, J2, U6
PLLVDD 2.5V BGA U8 PLL bead filtered clean power
PLLVSS GND Return BGA R9
PORVSS GND BGA T9 Pow eru p reset GND refe ren ce
a. NetSilicon recommends that you use separate power pairs for AC and DC power, to prevent th e noise in the AC p ow-
er buses from reaching the DC power buses. NetSilicon recommends and uses a ferrite bead to filter the AC power
pins.
Signal Mode Ball Number Description
Ta ble 165: NET+20 M BGA Chip Pinout - Power supply
Must be terminated* Must be left unconnected
G14 L14 - 17 G15 and 16 P14 - 17
H16 and 17 M14, 16, an d 17 H14 and 15 R14 - 17
J14, 15, and 17 N17 M15 T14 - 17
K14 - 16 N14 - 16 U13 - 15
* These can be tied to a single input current
source resistor.
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NET+20M Chip Package
All inputs are TTL levels and are 3.3 V-tolerant, allowing integration
with 3.3 V devices.
Signal description summary
The signal de scri ption summa ry defines an d briefly de scribes th e signa ls inclu ded
in the interfaces in the NET+20M chip. The description tables in the section are
presented in the same order as the NET+20M chip pinout tables. For details about
any of th e signa l s/ pino ut s, se e t he appr o p ri ate chapter:
The JTAG port for ARM core (ARM debugger) and Power sections are addressed
ful l y in their resp e c t i v e disc u s sions .
System Bus Interface
The NET+20M chip uses the system bus interface to interface with memory-
mapped peripheral devices such as flash, SRAM, and DRAM.
Interface Chapter
System bus Chapter 8, "Memory Controller Module"
Chip select controller Chapter 8, "Memory Controller Module"
Ethernet MII Chapter 10, "Ethernet Controller Module"
UARTS-SPI-GPIO; GPIO ports A, B, C Chapter 6, "The GEN Module"
Clock generation Chapter 6, "The GEN Module"
Code Definition Description
BCLK Bus clock Provides the bus clock. All s ystem bus inter face signals a re refer enced t o t he BC LK signa l.
ADDR Address bus Identifies the address of the peripheral being addressed by the current bus master. The
address bus is bi-directional.
DATA Data bus Provides the data transfer path between the NET+20M chip and external peripheral
devices.The data bus is bi-directional.
Ta ble 166: System bus i nterface signal description
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Signal description summary
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NET+50/20M Hardware Reference
Chip select controller
The NET+20M chip supports five unique chip select configurations.
TS* Transfer st art NO CONNECT
BE* Byte enable Identifies which 8-bit bytes of the 32-bit data bus are active during any given system bus
memory cycle. The BE* signals are active low and bi-directional.
RW* Rea d/write
indicator Indicates the direction of the system bus memory cycle. RW* high identifies a read
operation; RW* low identifies a write operation. The RW* signal is
bi-directional.
TA* Transfer
acknowledge Indicates the end of the current system bus memory cycle. This signal is
bi-directional.
TEA* Transfer error
acknowledge Indicates an error termination or burst cycle termination. TEA* is bi-directional. The
NET+20M chip or the external peripheral can drive the TEA* signal.
BR* Bus request NO CONNECT
BG* Bus grant NO CONNECT
BUSY* Bus busy NO CONNECT
Code Definition Description
Ta ble 166: System bus i nterface signal description
Code Definition Description
CS0*
CS1*
CS2*
CS3*
CS4*
Chip select 0
Chip select 1
Chip select 2
Chip select 3
Chip select 4
Unique chip select outputs supported by the NET+20M chip. Each chip select can be
configured to decode a portion of the avai lable address space and can address a maximum of
256 Mbytes of address space. Th e chip selects are configured using registers in the memory
module.
CAS0*
CAS1*
CAS2*
CAS3*
Column address
strobe signals Activated when an address is dec oded by a chip select module configured for DRAM mode.
The CAS* signals are active low and provide the column address strobe function for DRAM
devices.
The CAS* signals also identify which 8-bit bytes of the 32-bit data bus are active during any
given system bus memory cycle.
WE* Write enable Active low signal indicating that a memory write cycle is in progress. This signal is activated
only during write cycles to peripherals controlled by one of the chip selects in the memory
module.
Ta ble 167: Chip select controller signal descri ption
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NET+20M Chip Package
Ethernet int erface
The E t h e r n et M I I (Medi a I nd e penden t I nt erfac e ) p rovi des th e co nnecti on b e t ween
the Ethernet PHY and the MAC (Media Access Controller).
OE* Output enable Active low signal i ndicating that a memory read cycl e is in progress. T his signal is activated
only during read cycles from peripherals controlled by one of the chip selects in the memory
module.
Code Definition Description
Ta ble 167: Chip select controller signal descri ption
Code Definition Description
MDC Management data clock Provides the clock for the MDIO serial data channel. The MDC signal is a NET+20M
chip output. The maximum frequency is 2.5 MHz.
MDIO Management data IO A bi-directional signal that provides a serial data channel between the NET+20M chip
and the external Ethernet PHY module.
TXCLK Transmit clock An input to the NET+20M chip from the external PHY module. TXCLK provides the
synchronous data clock for transmit data.
TXD3
TXD2
TXD1
TXD0
Transmit data signals Nibble bus used by the NET+20M chip to drive data to the external Ethernet PHY. All
transmit data signals are synchronized to TXCLK. In ENDEC mode, only TDX0 is
used for t ransmit data.
TXER Transmit coding error Output asserted by the NET+20M when an error has occurred in the transmit data
stream.
TXEN Transmit enable Asserted when the chip drives valid data on the TXD outputs. This signal is
synchronized to TXCLK.
COL Transmit collision Input signal asserted by the external Ethernet PHY when a collision is detected.
CRS Receive carrier sense Ass erted by the external Ethernet PHY whenever the receive medium is non-idle.
RXCLK Receive clock An input to the NET+20M chip from the external PHY module. The receive clock
provides the synchronous data clock for receive data.
Ta ble 168: Ethernet M II signal description
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Signal description summary
494 n n n n n n n
NET+50/20M Hardware Reference
GPIO (PORTA/B/C)
See Chapter 6, "The GEN Module," for full configuration information for
PORTA/B/C. All ports can be configured for general purpose I/O pins. Only
special function code s are listed.
RXD3
RXD2
RXD1
RXD0
Receive data signals Nibble bus used by the NET+20M chip to input receive data from the external
Ethernet PHY. All receive data signals ar e synchronize d to RXCLK. In ENDEC
mode, only RXD0 is used for receive data.
RXER Receive error Input asserted by the external Ethernet PHY when the Ethernet PHY encounters
invalid symbols from the network.
RXDV Receive data valid Input asserted by the external Ethernet PHY when the Ethernet PHY drives valid data
on the RXD inputs.
Code Definition Description
Ta ble 168: Ethernet M II signal description
Code Definition Description
PORTA7 Input/Output/TxDA/SPI-A-M + S-TXD-O Can be configured as the special function TxDA output.
PORTA6 Input/Output/DREQ1*/DTRA* Can be configured as the special function DREQ1* input or
the special function DTRA.
PORTA5 Input/Output/RTSA* Can be configured as the special function RTSA output.
PORTA4 Input/Output/RxCA/SPI-A-S-CLK-I/
SPI-A-M-CLK-O Can be configured for special function RxCA input or the
special function OUT1A output.
PORTA3 Input/Output/RxDA/SPI-A-S + M-RXD-I Can be configured for special function RxDA input.
PORTA2 Input/Output/DSRA*/DACK1* Can be configured for special function DSRA input or for
special function DACK1* output.
PORTA1 Input/Output/CTSA* Can be configured for special function CTSA input.
PORTA0 Input/Output/DCDA*/DONE1* Can be configured for special function DCDA input or
DONE1* I/O.
PORTB7 Input/Output/TxDB/SPI-B-M and S-TXD-O Can be configured as the special function TxDB output.
PORTB6 Input/Output/DREQ2*/DTRB* Can be configured as the special function DREQ2* input or
the special function DTRB.
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NET+20M Chip Package
Clock generation and reset
The NET+20M has three main clock domains:
System clock (SYSCLK), which drives the CPU and internal logic.
Bit rate generation and programmable timer reference clock (XTAL).
Also produces SYSCLK through the PLL when PLLTST* = 1.
PORTB5 Input/Output/REJECT*/RTSB* Can be configured as the special function REJECT input or
for special function RTSB output.
PORTB4 Input/Output/RxCB/SPI-B-M-CLK-O/
SPI-B-S-CLK-I Can be configured for special function RxCB input or special
function OUT1B.
PORTB3 Input/Output/RxDB/SPI-B-S + M-RXD-I Can be configured for special function RxDB input.
PORTB2 Input/Output/DSRB*/DACK2* Can be configured for special function DSRB input or special
function DACK2* output.
PORTB1 Input/Output/CTSB*/RPSF* Can be configured for special function RPSF* output or
special function CTSB input.
PORTB0 Input/Output/DCDB*/DONE2* Can be configured for special function DCDB input or special
function DONE2* I/O.
PORTC7 Input/Output/TxCA/SPI-A-M-ENB-O/
SPI-A-S-ENB-I Can be configured f or special function TxCA input or special
function OUT2A output.
PORTC6 Input/Output/RIA*/IRQ* Can be configured as the special function RIA* input or for
special function IRQ* output.
PORTC5 Input/Output/TxCB/SPI-B-M-ENB-O/
SPI-B-S-ENB-I Can be configured for special function TxCB input or special
function OUT2B output.
PORTC4 Input/Output/RIB* Can be configured for special function RIB input.
PORTC3 Input/Output/CI3/AMUX Can be configured for special function C3 interrupt input or to
provide the DRAM address multiplexer function.
PORTC2 Input/Output/CI2 Can be configured for special function C2 interrupt input.
PORTC1 Input/Output/CI1 Can be configured for special function C1interrupt input.
PORTC0 Input/Output/CI0 Can be configured for special function C0 interrupt input.
Code Definition Description
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Signal description summary
496 n n n n n n n
NET+50/20M Hardware Reference
System bus clock (BCLK), which drives devices external to the
NET+20M.
The SYS mod u l e provi d es th e N E T+ 20 M chi p wi t h these cl o c ks, as well a s sy stem
reset and boot-up resources.
Test support
The PLLTST*, BISTEN*, and SCANEN* primary input pins put the NET+20M into
various test modes, for both functional and manufacturing test operations.
For more information about PLLTST*, see Chapter 6, "The GEN Module."
ARM debugger
Five pins provide a dedicated connection to the internal ARM processor core.
These fi ve si g n al s connec t to th e AR M proces so r only, and are use d for so ft wa re
Code Definition Description
XTAL1
XTAL2
Crystal osci ll a tor
input
Crystal osci ll a tor
output
A standard (18.432 MHz) parallel-resonant crystal can be attached to these pins to provide
the main input clock to the NET+20M chip.
The oscillator frequency equals SYSCLK. XTAL1 is in the 2.5V ring and has a maximum
VIH of 2.75V. A typical 3.3V oscillator requires a 220 ohm series resistor with its output.
PLLVDD Clean PLL power Powers the internal 2.5V PLL circuit.
PLLVSS Clean PLL ground Grounds the internal PLL circuit.
PLLLPF PLL loop filter Provides the PLL loop filter circuit.
RESET* System reset Resets the NET+20M chip hardware.
Ta ble 169: Clock ge neration and reset signal d escription
Code Definition Description
PLLTST* PLL test and
disable Disables the intern al PLL when driven active low. Enables t he crystal oscillator and internal
PLL when left unconnected or driven high.
BISTEN* BIST enable Used for testing purposes only; the pin should always be left unconnected or driven high.
SCANEN* SCAN enable Used for testing purposes only; the pin should always be left unconnected or driven high.
Ta ble 170: Test support signal de scription
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NET+20M Chip Package
development using the ARM Embedded ICE module (or similar device). These
five signals cannot be used for 1149.1 JTAG testing of the NET+20M chip.
TDI
TDO
TMS
TRST*
TCK
The following figure illustrates the pin connection:
Figure 101: NET+50 /20M reset and A RM debugger c ircuit
Power
This section describes the pins that provide power for various components of the
I/O output drivers and the internal NET+20M chip core.
10KR5
OUT
NETARM.158
Re quire s powe rup timi ng s equen c ing
wit h so me debugg ers when F la sh
c ont ains invalid code or is disabled.
RESET-
0R4
0R2
NOTE:
Ful l Fe atu re d D ebu g -O ption a l
TDO
R1, R2
3.3V
U seful f or c ode de ve lopm ent. Removes
timing and break point restrictiions.
TDI
Leaving TRST* pulled to a logic "low" on
production units is not recommended. The noise
margin on inputs at a logic "0" are only a few
tenths of a volt.
NETARM.173
OUT
3.3V
5V OR 3.3 V OPEN DRAIN
3.3V ACTIVE T TL
NETARM.174
RESET LOADS-
1K
Basic Debug - Production Units
5V ACTIVE T TL
0R1
ICETRST-
Table 1
IN
1K
D1
DIODE_SCHOTTKY
352uA CURRENT S OURC E
U1
AND1_SOT23
1
23
4
5
NETARM.172
3.3V
NETARM
10KR3
IN
0R6
NETARM.170
3 TYPICAL RESET SOURCES
429uA Max.CURR ENT SINK
ICESRST-
See Table 1
C1
.1
3.3V
HEADE R 7X2
12 34 56 78 910 11
13
12
14
C1, R5, R6, U1
3.3V
TMS
RESET_OUT-
TRST-
NETARM.171
TCK
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Signal description summary
498 n n n n n n n
NET+50/20M Hardware Reference
Code Definition Description
VCCAC Power A/C
switching The VCCAC pins provide the 3.3V power for the switching component of the
I/O output drivers. Thes e pi ns can be fi ltered t o l ower any potential EM I. E ach VCCAC pin
has a GNDAC ground return.
VCCDC Power DC drive The VCCDC pins provide the 3.3V power for the DC component of the I/O output drivers.
These pins should not require any filtering other than standard decoupling practices. Each
VCCDC pin has a GNDDC ground return.
VDDCO Power core The VDDCO pins provide the 2.5V power for the internal NET+20M chip core. Each of these
pins must have a bypass capacitor placed as close to the pin as physically possible. Each
VDDCO pin has a VSSCO ground return.
PORVSS Power on reset Grounds the power-on-reset circuitry.
GNDAC Ground A/C
switching The GNDAC pins provide the ground for the switching component of the I/O output drivers.
These pins can be filtered to lower any potential EMI.
GNDDC Ground DC drive The GNDDC pins provide the ground for the DC component of the I/O output drivers. These
pins should not require any filtering other than standard decoupling practices.
GNDCO Ground core The GNDCO pins provide the ground for the internal NET+20M chip core. These pins
should not require any filtering other than standard decoupling practices.
Ta ble 171: Power signal descript ion
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NET+20M Chip Package
Packaging
Figure 102 shows the package for the NET+20M. Table 172 pr ovides the NET+20M
dimensions:
Figure 102: BGA pa ckage
Dimension Minimum Nominal Maximum
A --------------- --------------- 1.40
A1 0.22 0.26 0.30
A2 0.65 0.70 0.75
A3 0.25 --------------- ---------------
B -------------- - 5.50 REF --------- -- --- -
D --------------- 15.00 ---------------
Table 172: BGA dimensions
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Packaging
500 n n n n n n n
NET+50/20M Hardware Reference
D1 --------------- 12.80 ---------------
E --------------- 15.00 ---------------
E1 --------------- 12.80 ---------------
P --------------- 0.80 ---------------
Dimension Minimum Nominal Maximum
Table 172: BGA dimensions
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NET+20M Chip Package
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Index
I- n n n n n n n Index-1
Numerics
10 MB Jabber Counter (JBCT) 244
10 MB Loss of Carrier Counter
(DTLB) 245
1284 Compatibility mode
timing 471
-
472
1284 Port Multiplexing
timing 470
32-bit pre-fetch 110, 111
A
A10/AP SDRAM signal 163
abort exception 47, 477
absolu te maximum ratings 421
AC timing characteristics 423
-
425
output pad timing 423
act i ve command 162
address bits 122
A26, A26_F 125
A27, A27_F 124
address bits and function control
GEN module hardware
initialization 61
MIC module hardware
intialization 334
NET+50 bootstrap initialization 62
address bus 135
address decoding 57
addre ss interrupts 389
Alignment Error Counter register
(RXAEC) 252
arbitration order 56
ARM
debugger 38, 491, 497
exceptions 46, 475
-
479
Thumb architecture 46
ARM7TDMI 2, 107
asynchronous mode. See X16 mode
B
background refres h 123
BASE field 137
BBus module 55
-
58
address decoding 57
arbitration 56
cycles 56
functionality 56
Index
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Index-2
n n n n n n n
order of arbitration 56
system bus 108
BGA (bal l-grid-array) 1
big Endian mode configuration 271
bit-rate examples 313
bit-rate generator 266, 312
BIU controller 108
bootstrap initialization 6 1, 408
bootstrap settings 139
buffer descriptor
buffer descriptor pointer
register 186
destination address pointer 183
DMA 179
-
181
buffer length 182
memory-to-memory 182
memory-to-peripheral 182
peripheral-to-memory 182
burst terminate command 162
burst terminate solution 168
bus error interrupts 391
bus interface 8, 11
byte enable (BEx*)
lane configura tions 142
signal 141
byte mode 358
-
359
cycle diagram 358
C
cache 109
-
111
32-bit pre-fetch 110, 111
4-way associat ed cache diagram 109
control registers 110, 112
-
114
initialization 111
line fill 110
line locking 11 1
line replacement 111
operation 110
RAM 114
registers and bit definitions 112
-
114
TAG format 115
Cache Control registers 112
-
114
cache controller 108, 110
cache support 5
CAS
lane configurations 140
signals 140
CBUS
internal bus 107
system bus 10 8
channel abort 187
Channel Data registers 372
-
373
channel enable 187
Chip Select Base Address
register 126
-
130
chip select controller
pinout information 22, 486
signal descriptions 30, 492
Chip Select Option register 130
-
133
Chip Select Opti on Register B 134
chip selects
address range 136
-
139
mask settings 138
memory space 137, 138
and RAS 136
configuring for fast page or EDO
DRAM 147
-
148
config uring for SDRAM 157
-
161
configuring for SRAM 144
-
145
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I- n n n n n n n Index-3
external DRAM multi plexing
configuration 146
CISC 2
clear interrupts 388
clock generation
pinout information 26, 488
signal descriptions 496
clock generator 10, 13
clock relationships 425
Code Error Counter register
(RXCEC) 252
Coll i sion Win d ow /C o llisi on Ret r y
register 238
column address strobe s. See CAS
configuration
ENI controller 400
GEN module 60
GPIO function 335
-
339
MIC controller 332
serial controller module 284
SPI master 274
-
276
GPIO ports 274
SER module 275
SPI slave 278
-
279
configuration registers
Chip Select Base Address register
126
-
130
Chip Select Option register 1 30
-
133
Chip Select Option Register B 134
IEEE 1284 366
Memory Module Control
register 122
-
126
Control Register C (HDLC) 320
control signals
address bus 135
BE* lane conf iguration 142
byte enable (BEx*) 141
CAS 140
chip select addres s range 136
-
139
chip selects/RA S 136
CS0* boot con figuration 139
data bus 135
output enable (OE*) 141
read/write (R/W*) 141
transf er acknowledge (TA*) 142
transfer error acknowledge
(TEA*) 143
write enable (WE*) 141
control state machine 353, 382
CPU
core 8, 11
core block diagram 108
internal bus (CBUS) 107
module 45
-
54, 107
CRC Error Counter register
(RXCRC) 252
crystal os cillator specifications 474
CS0* boot con figuration 139
CSBAR. See Chip Select Base Address
register
CSOR. See Chip Select Option register
CSORB. See Chip Select Opti on
Register B
CTS han dshaking si gnal 267
customer support xxxi
D
data abort 47, 477
data bus 135
data bus peripheral devices 135
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Index-4
n n n n n n n
DC characteristics 421
-
423
inputs 421
output 422
destination addr ess pointer 183
device modules
NET+20M 4
NET+50 3
DLFC 228
DMA
controller 9, 12
controller reset 199
handshake sig nals 331
interface logic 203
interrupt sources 53
DMA Control register 186
-
190
DMA con tr oller module 1 73
-
199
buffer descriptor 179
-
181
fly-by mode 180
memory-to-memory mode 180
structure 183
buffer descriptor pointer register
186
buffer length 182
channel assignments. See IEEE 1284
configuration and MIC
configuration
channel configuration 178, 183
-
185
channel direction codes 178
channel signals 196
channels 173
Control register 186
-
190
controller assignments 176
destination address pointer 183
Ethernet receiver considerations 193
external DMA configuration 196
external fly-by hardware 197
external memory-to-memory
hardware 199
external peripheral support 194
fly-by mode 174, 197
-
198
fly-by read 174, 198
fly-by write 174, 197
IEEE 1284 configuration 176
memory-to-memory mode 174,
198
-
199
MIC configuration 176
module diagram 175
registers 185
-
193
source buffer pointer 182
Status/Interrupt Enable
register 191
-
193
transfers 174
-
175
DRAM
chip selects 122
EDO 136, 145
-
154
external multiplex RAS/CAS
addressing 148
fast page 136, 145
-
154
fast page and EDO
chip select configuration
147
-
148
timing 436
-
444
Mode-0 addressing 149
-
151
Mode-1 multiplexing 152
-
154
refresh controller 123
E
EDO DRAM 145
-
154
timing 436
-
444
Burst Read 439
Burst Write 441
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I- n n n n n n n Index-5
Read 437
Refresh (RCY C=0) 443
Refresh (RCY C=1) 443
Refresh (RCY C=2) 444
Refresh (RCY C=3) 444
Write 438
timing values 436
EFE module 201, 202
-
203
features 202
registers 206
-
222
ENDEC mode 203
operating in
IPGR1 235
IPGR2 236
IPGT 233
Endian modes 271, 272
ENI
FIFO mod e s 331
shared RAM modes 331
ENI Control register 408
-
414
ENI FIFO Data register 393
-
395
ENI FIFO Mas k/Status
register 395
-
400
ENI FIFO mod e 391
-
400
block diagram 392
Data register 393
-
395
DMA con tr ollers 392
Mask/Status register 395
-
400
sample application diagram 392
ENI host mode
signal descriptions 33
ENI mode 330
addr e s s in t e r ru p t s 389
basic functi onality 375
bus error interrupts 391
clear interrupts 388
Control register 408
-
414
FIFO Data register 407
General Control register 401
-
405
General Status register 405
-
407
host interface 375
-
377
host interface signals 376
overview 374
-
381
Pulsed Interrupt regist er 415
shared RAM 383
Shared RAM Address
register 415
-
417
shared RAM block diagram 382
shar ed RAM memory map 383
shared RAM mode 382
-
391
shared RAM state machine 382
Shared register 384
-
388
signal descriptions 377
-
381
ENI Mode FIFO D ata register 407
ENI mode registers 400
-
417
ENI Pulsed Interrupt regist er 415
ENI reset 102
ENI Shared RAM Address
register 415
-
417
ENI shared RAM mode 377
entering an exception 50
EPP mode 363
-
366
address read cycle 366
address write cycle 365
data read cycle 364
EPP data write cycle 364
Error Counter registers 325
Error Statistics registers 252
-
254
Ethernet
timing 467
-
469
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Index-6
n n n n n n n
External Ethernet CAM
Filtering 469
Receive Clock Idle 46 8
timing diagram 468
timing values 467
Ethernet controller module 201
-
262
10 MB Jabber Counter (JBCT) 244
10 MB Loss of Carrier Counter
(DTLB) 245
Coll i sion Win d ow /C o llisi on Ret r y
register 238
configuration 204
-
206
DMA interfac e logi c 203
EFE module 201, 202
-
203
Error Statistics registers 252
-
254
FIFO Data register 216
reading fr om 217
writing to 216
General Control register 207
-
212
General Status register 212
-
216
Inter-Packet GAP (IPG)
register 231
-
237
Link Fail Counter (LFCT) 244
MAC Configuration register 223
MAC module 201, 203
-
204
MAC Test register 225
MII Address register 249
MII Command register 248
MII Control registers 248
-
251
MII Indicators register 250
MII Read Data register 250
MII Write Data register 249
module diagram 202
multicast hash table 254, 257
-
262
calculating entries 259
PCS Configuration register 226
PCS Control registers 244
-
245
PCS Test register 228
Receive Byte Counter (RBCT) 242
Receive Control registers 242
-
243
Receive Counter Decodes
(ECRDC) 242
receive FIFO 203
Receive Status register 220
-
222
simulation registers 239
-
241
Station A ddress Filter register 255
Station Address register 256
statistics monitoring 251
STL Configuration register 2 28, 229
STL Test register 228, 230
Test Operate Receive Counters
(RECTCL) 243
Transmit Control registers 231
-
241
transmit FIFO 2 02
Transmit Status register 217
-
219
Ethernet FIFO Data register 216
reading from 217
writing to 216
Ethernet front-end module. See EFE
module
Ethernet General Control
register 207
-
212
Ethernet General Status
register 212
-
216
Ethernet interface
pinout information 22, 486
signal descriptions 30, 493
Ethernet MII. See Ethernet interface 30
Ethernet receive
interrupt sources 53
Ethernet Receive Status
register 220
-
222
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I- n n n n n n n Index-7
Ethernet receiver considerations 193
Ethernet transmit
interrupt sources 53
Ethernet Trans mit St atus
register 217
-
219
exceptions 46
abort 477
definition 476
entry/exit summary 51
FIRQ 478
hardware interrupts 52
IRQ 478
list of 47
priorities 48
reset 476
software action 50
SWI 477
undefined 476
vector table 48
Excessive (Late) Deferral Counter
(TXLDC) 253
exiting an exception 5 0
external DMA
timing 454
-
458
External Fly-by DMA 455
External Memory-to-Memory
DMA 457
timing values 454
external DRAM multiplexing
configuration 146
external ENI address map 389
external loopback mode 374
external multiplex RA S/CA S
addressing 148
external peripheral DMA support 194
signal description 194
external reset 102
F
fast page DRAM 145
-
154
timing 436
-
444
Burst Read 439
Burst Write 441
Read 437
Refresh (RCYC=0) 443
Refresh (RCYC=1) 443
Refresh (RCYC=2) 444
Refresh (RCYC=3) 444
Write 438
timing values 436
FIFO Dat a Re gister LAST (HDLC) 326
FIFO management 270
FIFO mode interface 331
FIFO overrun condition 193
FIFO receiver interrupts 398
FIFO transmitter interrupts 399
FIRQ interrupt 47, 52, 478
fly-by mode 197
-
198
fly-by read 198
fly-by write 197
forwa rd compatibility mode 355
-
357
compatibility FAST mod e 357
compatibility SLOW mode 356
forward ECP mode 359
-
360
ECP FAST mode 360
ECP SLOW mode 360
timing 473
FRCQ 228
net50_20_1.book Page 7 Friday, September 19, 2003 10:41 AM
Index-8
n n n n n n n
G
GEN module 59
-
105
and NMSI 280
and SPI mo de 281
bootstrap in itialization 6 1
configuration 59, 60
functionality 59
general purpose I/O. See GPIO
hardware initialization 61
Interrupt Control register and bit
definition 94
-
96
Interrupt Enable register 93
Interrupt Enable Register Clear 94
Interrupt Enable Register Set 93
interrupt generation a nd
control 93
-
96
Interrupt Status Register Enabled 94
Interrupt Statu s Register Raw 94
interrupts 60
PLL
PORTA regis ter 74
-
79
PORTB register 79
-
85
PORTC register 86
-
93
Software Service register 69, 70
System Control register 63
-
67
system registers 63
-
69
System Status register 67
-
68
Timer Control regis ters 70, 71
-
72
Timer Status register 70, 72
General Control register 401
-
405
General Status register 405
-
407
GPIO
features 10
function configuration 335
-
339
mode 330, 334
-
350
PORTA/B/C signal
descriptions 35, 494
PORT D/F/G/H functionality 33 7
GPIO configurations 280
-
283
GPIO PORTA/B/ C support 5
GPIO registers 73
-
93
PORTA r e gi s t e r 74
-
79
PORTB register 79
-
85
PORTC register 86
-
93
PORTD register 336, 339
-
341
PORTF regis ter 336, 342
-
344
PORTG register 336, 345
-
347
PORTH register 336, 347
-
350
H
hardware design
NET+20M 4
NET+50 3
hardware initia lization
GEN module 61
MIC module 333
hardware interrupts 52
FIRQ 52
IRQ 52
HDLC mode 264, 267
-
269, 295, 305, 307,
316, 318
bit stuffing 268
Control Register C 320
controller features 267
error detection 269
FIFO Data Register LAS T 326
framing structure 268
layer 2 frame 268
layer 3 frame 269
net50_20_1.book Page 8 Friday, September 19, 2003 10:41 AM
I- n n n n n n n Index-9
Status Register B 321
-
325
Status Register C 325
high speed data transfer 264
I
IEEE 1284
byte mode 358
-
359
Channel Data registers 372
-
373
configuratio n registers 366
control state machine 353
data bus assignments 351
EPP Mode 363
-
366
external loopback mode 374
external transceivers 351
forward compatibility
mode 355
-
357
forward ECP mode 359
-
360
host controller block diagram 353
host interface module 350
-
374
host mod e 3 30
nibble mode 357
-
358
Port Control registers 367
-
372
reverse ECP mode 360
-
363
signal cros s refere nce 353
signal descriptions 32
signals 352
strobe pulse width 373
IEEE 1284 Port Control
registers 367
-
372
IEEE negotiation 355
independent programma ble bit- rate
generator 264, 266
inhibit command 163
integrated Ethernet support 9, 11
internal clock generation 96
-
101
internal XTAL clock
frequency definitions 99
reference 99
Inter-Packet Gap (IPG) registers
Back-to-Back IPG Gap Timer 231
Non Back-to-Back IPG Gap
Timer 233
Interrupt Control register and bit
definition 94
-
96
interrupt enable (IE) bits 191, 293
-
294
Interrupt Enable register 93
Interrupt Enable Register Clear 94
Interrupt Enable Register Set 93
interrupt generation and control 93
-
96
interrupt service routine (ISR) 49
interrupt sources
DMA 53
Ethernet receive 53
Ethernet transmit 53
MIC 53, 333
PORTC 54
PORTD 340
PORTF 342
PORTG 345
PORTH 348
serial 53
timers 1 & 2 54
watch-do g t im e r 53
Interrupt Status Register
Enabled 53, 60, 94
Interrupt Status Register Raw 53, 94
interrupts
address 389
bus error 391
clear 388
FIFO receiver 398
net50_20_1.book Page 9 Friday, September 19, 2003 10:41 AM
Index-10
n n n n n n n
FIFO transmitter 399
GEN module 60
MIC module 333
intrinsic delay 423
IRQ interrupt 47, 52, 478
J
JTAG port for ARM core
pinout information 27, 489
JTAG timing 469
L
lane configura tion
byte enable 142
CAS 140
Late Collision Counter (TXLCC) 253
Link Fail Counter (LFCT) 244
little Endian mode configuration 271
load-d ependent delay 42 3
load-mode com man d 155, 16 1
setting up 155
-
157
timing 453
logical addresses 108, 137
logical memory space 108
Long Frame Counter (RXLFC) 253
M
MAC module 201, 203
-
204
features 203
MAC registers 223
-
225
Configuration 223
Test 225
MASK field 137
mask settings 138
Maximum Collision Coun ter (TXMCR)
254
media access controller module. See
MAC module
media independent interface. See MII
mode
MEM module 119
-
171
basic configurations 143
-
164
bootstrap settings 139
burst terminate solution 168
CAS lane con f igurations 140
Chip Select Base Address
register 126
-
130
Chip Select Option register 130
-
133
Chip Select Opti on Register B 134
config uration registers 121
-
134
control signals 1 34
-
143
fast page and EDO DRAM 145
-
154
features 120
-
121
Memory Module Control
register 122
-
126
SDRAM 155
-
164
commands 161
-
163
configuration 157
-
164
interconnect 164
-
167
SRAM 144
-
145
WAIT configuration 167
Memory (controller) module. See MEM
module
memory control signals 134
-
143
memo ry management unit (M MU) 478
Memory Module Control
register 122
-
126
memory space 137, 138
memory-to-memory mode 198
-
199
net50_20_1.book Page 10 Friday, September 19, 2003 10:41 AM
I- n n n n n n n Index-11
MIC
interrupt sources 53
timing 461
-
466
ENI Dual Dir e ction DMA 466
ENI Shared RAM and Register
Cycle 464
timing values 461
MIC controller module 329
-
417
addr e s s in t e r ru p t s 389
bus error interrupts 391
clear interrupts 388
configuration 332
ENI Control register 408
-
414
ENI FIFO Data register 393
-
395
ENI FIFO Mas k/Status
register 395
-
400
ENI FIFO mod e 391
-
400
ENI host interface 375
-
377
ENI mode 330, 374
-
381
ENI Mode FIFO Da ta register 407
ENI mode registers 400
-
417
ENI mode signal
descriptions 377
-
381
ENI Pulsed Interrupt register 415
ENI Shared RAM Address
register 415
-
417
ENI shared RAM mode 377, 382
-
391
General Control register 401
-
405
General Status register 405
-
407
GPIO function
configuration 335
-
339
GPIO m ode 330, 3 34
-
350
hardware initialization 333
IEEE 1284 byte mode 358
-
359
IEEE 1284 Channel Data
registers 372
-
373
IEEE 1284 configuration
registers 366
IEEE 1284 EPP mode 363
-
366
IEEE 1284 external loopback
mode 374
IEEE 1284 forward compatibility
mode 355
-
357
IEEE 1284 forward ECP
mode 359
-
360
IEEE 1284 host interface (4-port)
module 350
-
374
IEEE 1284 host mode 330
IEEE 1284 nibble mode 357
-
358
IEEE 1284 Port Control
registers 367
-
372
IEEE 1284 reverse ECP
mode 360
-
363
IEEE 1284 signal cross reference 353
interrupts 333
modes of operation 330, 331
overview 330
PINT1*/PINT2* in terrupt pins 39 0
PORTD register 336, 339
-
341
PORTF regis ter 336, 342
-
344
PORTG register 336, 345
-
347
PORTH register 336, 347
-
350
shared RAM 383
shar ed RAM memory map 383
Shared register 384
-
388
strobe pulse width 373
MIC interface
GPIO mode signal descriptions 34
pinout information 23
signal descriptions 31
MIC support 5
MII Address register 249
MII Command register 248
net50_20_1.book Page 11 Friday, September 19, 2003 10:41 AM
Index-12
n n n n n n n
MII Indicators register 250
MII mode 203
Control registers 248
-
251
MII Address 249
MII Command 248
MII Indicators 250
MII Read Data 250
MII Write Data 249
interface sign als 246
operating in
IPGR1 234
IPGR2 235
IPGT 232
MII Read Data register 250
MII Write Data register 249
MMCR. See Memory Module Control
register
multicast hash table 2 54, 257
-
262
calculating entries 259
multi-interface controller. See MIC
cont r o ller mod u le
N
NET+20M chip 1
applications 4
device modules 4
differences with NET+50 chip 5
features 11
-
13
hardware design 4
packaging 500
pinout 482
-
491
reserved pins 490
signal descriptions 491
-
499
NET+50 chip 1
applications 2
BGA packaging 42
bootstrap initialization 61
cache 109
-
111
cache controller 110
device modules 3
devices and revision IDs 68
differences with NET+20M chip 5
DMA channels 3 and 4 391
encoding/decoding the serial data
stream 298
features 8
-
10
hardware design 3
IEEE 1284 parallel port
interfaces 350
internal cloc k generation 96
-
101
memory device configuration 119
pinout 16
-
28
PLL test mode 103
-
105
PQFP packaging 40
reset circuit 101
-
103
SDRAM interconnect 164
-
167
signal descriptions 28
-
39
NET+50 interrupt controller 49
NET+ARM hardware block diagram 3
nibble mode 357
-
358
cycle diagram 357
NMSI 280
and GEN module ports 280
PORTA/B/C assignments 281
non multiplexed seria l in terface. See
NMSI
NOP (no operation) command 162
net50_20_1.book Page 12 Friday, September 19, 2003 10:41 AM
I- n n n n n n n Index-13
O
operating frequenc ies 425
output enable (OE*) signal 141
output load capacitance 424
P
P1284/MIC interface 9
packaging
NET+20M (BGA) 500
NET+50 BGA 42
NET+50 PQFP 40
PCS registers 226
-
228, 244
-
245
Configuration 226
Control registers 244
-
245
10 MB Jabber Counter
(JBCT) 244
10 MB Loss of Carrier Counter
(DTLB) 245
Link Fail Counter (LFCT) 244
Test 228
phase locked loop. See PLL
physical subcoding layer registers. See
PCS registers
pin support 6
pinout information
chip select controller 22, 486
clock generation 26, 488
Ethernet interface 22, 486
JTAG port for ARM core 27, 489
MIC interface 23
power 27, 489
system bus interface 19, 483
system reset 26, 488
UARTS-SPI-GPIO 25, 487
PINT1*/PINT2* interrupt pins 390
PLL 69
PLL test mode 103
-
105
PORTA r e gi s t e r 74
-
79
general purpose I/O mode 75
register and bit definition 78
-
79
special function mode 75
-
78
PORTB register 79
-
85
general purpose I/O mode 81
register and bit definition 84
-
85
special function mode 81
-
84
PORTC register 86
-
93
general purpose I/O mode 87
interrupt sources 54
register and bit definition 92
-
93
special function mode 87
-
91
PORTD register 339
-
341
general purpose I/O mode 339
interrupt mode 340
register and bit definition 340
-
341
PORTF register 342
-
344
general purpose I/O mode 342
interrupt mode 342
pin/mode/dir configuration 343
register and bit definition 343
-
344
PORTG register 345
-
347
general purpose I/O mode 345
interrupt mode 345
pin/mode/dir configuration 346
register and bit definition 346
-
347
PORTH register 347
-
350
general purpose I/O mode 347
interrupt mode 348
pin/mode/dir configuration 348
register and bit definition 349
-
350
net50_20_1.book Page 13 Friday, September 19, 2003 10:41 AM
Index-14
n n n n n n n
power
pinout information 27, 489
signal descriptions 39, 498
power and operating voltage 10, 13
powerup reset 101
PQFP (plastic-quad-flat-pack) 1
precharge command 162
prefetch abort 47, 477
R
RAS 136
read command 162
read/write (R/W*) signal 141
read-only registers 53
receive buffer gap timer
DMA mode 315
interrupt mode 315
Receive Buffer Timer
register 314, 316
-
317
HDLC mode 316
Receive Byte Counter (RBCT) 242
Receive Character Timer
register 315, 317
Receive Control registers 242
-
243
Receive Byte Counter (RBCT) 242
Receive Counter Decodes
(ECRDC) 242
Test Operate R eceive Coun ters
(RECTCL) 243
Receive Counter Decodes (ECRDC) 242
receive data coding 300
receive FIFO 203
receive FIF O interf ace 272
DMA con tr oller 273
processor interrupts 272
Receive Gap Timer registers 314
-
317
Receive Match MAS K register 318, 319
Receive Match register 318
receiver
SPI master 277
SPI slave 280
refresh
DRAM 123, 443
-
444
SDRAM 452
refresh command 163
reset circuit 101
-
103
conditions 103
ENI reset 102
external reset 102
powerup reset 101
software reset 102
watch-dog r eset 102
reset conditions 103
reset exception 47, 476
RESET* timing 425
Retransmit Byte Co unter register
(RETX) 240
reverse ECP mode 360
-
363
reverse mode timing 362
RISC 2
round-robin arbitration loop 56
RTS handshaking signal 267
S
SDRAM 155
-
164
A10/AP signal 163
chip select configuration 157
-
161
commands 161
-
163
load-mode command 132, 155
net50_20_1.book Page 14 Friday, September 19, 2003 10:41 AM
I- n n n n n n n Index-15
NET+50 chip in terconnect 164
-
167
x16 bursting consideration s 164
x16 configuration 166
x32 configuration 164
timing 445
-
453
Burst Read (CA S Laten cy=1) 449
Burst Read (CA S Laten cy=2) 450
Burst Write 451
Load-Mode Com mand 453
Read (CAS Latency=1) 446
Read (CAS Latency=2) 447
Refresh Command 452
Write 448
timing values 445
serial channel A 263
serial channel B 263
Seri al Channel Bit-Rate
registers 290, 308
-
314
X1 (synchronous) mode
bit rates 312
timing 308
X16 (asy nch r on ou s ) mode
bit-rates 312
Seri al Channel Control
Regi st er A 290, 291
-
294
Seri al Channel Control
Register B 290, 295
-
299
Serial Channel FIFO registers 290, 314
Serial Channel registers 290
-
314
Seri al Channel Statu s
Regi st er A 290, 300
-
307
serial controller module 263
-
327
bit stuffing 268
bit-rate examples 313
bit-rate generator 312
configuration 284
Control Register C (HDLC) 320
features 264
FIFO Data R egiste r Last (HDLC) 326
GPIO configurations 280
-
283
HDLC error detection 269
HDLC mode 267
-
269, 316, 318
layer 2 frame 268
layer 3 frame 269
protocols 266
Receive Buffer Timer
register 314, 316
-
317
Receive Character Timer
register 315, 317
Receive Match MASK
register 318, 319
Receive Match register 318
register diagrams 285
-
289
Serial Channel Bit-Rate
registers 290, 308
-
314
Serial Channel Control
Register A 290, 2 91
-
294
Serial Channel Control
Register B 290, 295
-
299
Serial Channel FIFO
registers 290, 314
Serial Channel Status
Register A 290, 3 00
-
307
serial port performance 283
SPI mode 269
-
280
SPI master 269, 27 3
-
277
SPI slave 269, 277
-
280
Status Register B (HD L C) 321
-
325
Status Register C (HDLC) 325
UART mode 266
-
267, 318
serial peripheral interface. See SPI
ser ia l p or t
interrupt resources 53
net50_20_1.book Page 15 Friday, September 19, 2003 10:41 AM
Index-16
n n n n n n n
module diagram 265
performance 283
receiver interrupt service
routine 273
serial ports 9, 12
serial p r otocols 2 66
share d memory interf ace 331
shared RAM 383
shared RAM mode 382
-
391
ENI shared RAM block diagram 382
memory map 383
shared RAM state machine 382
Shared register 384
-
388
register and bit definition 386
-
388
writing to 385
Short Frame Counter (RXSF C) 253
signal descriptions
ARM debugger 38, 497
chip select controller 30, 492
clock generation 496
ENI host mode 33
ENI mode 377
-
381
Ethernet interface (MII) 30, 493
external peripheral DMA 194
GPIO (PORTA/B/C) 35, 494
IEEE 1284 32, 352
MIC interface 31
MIC interface configured for GPIO
mode 34
MII interface 246
NET+20M chip 491
-
499
NET+50 chip 28
-
39
power 39, 498
system bus interface 29, 491
system reset 36, 496
test support 37 , 496
SIMR 225, 228
simulation registers
Retransmit Byte Counter register
(RETX) 240
Test Operate Transmit Counters
(TECTCL) 241
Transmit Byte Counter register
(TBCT) 239
Transmit Counter Decodes
(ECTDC) 241
Transmit Masked Random Number
(MRNG) 240
Transmit Packet Nibble Counter
(PCNT) 239
Transmit Random Number
Generator (RNG) 240
software reset 102
Software Service register 70
source buffer pointer 182
SPI
timing 459
-
461
Master mode 0 and 1 459
Slave mode 0 and 1 460
SPI mode 264, 269
-
280, 301, 304, 305,
306, 307
and GEN module ports 281
controller features 269
FIFO management 270
master and slave/GPIO signal
relationships 282
receive FIFO interface 272
SPI master 269, 27 3
-
277
configuration 274
-
276
PORTA/B/C assignments 282
receiver 277
transmitter 276
SPI slave 269, 277
-
280
net50_20_1.book Page 16 Friday, September 19, 2003 10:41 AM
I- n n n n n n n Index-17
configuration 278
-
279
PORTA/B/C assignments 282
receiver 280
transmitter 279
transmit FIF O interface 271
SRAM 144
-
145
chip select configuration 144
-
145
timing 426
-
435
Async Burst Read 434
Async Burst Write 435
Async Read 432
Async Write 433
Sync Burst Read (2-111) 429
Sync Burst Read (4-222) 430
Sync Burst Write (4-222) 431
Sync Read 42 7
Sync Write 428
timing values 426
static RA M. See SRAM
Station Address Filter register 255
station address logic (SAL) blocks 204
Station Address registers 254
-
257
Station Address Filter 255
Station Address register 256
station logic registers. See STL registers
statistics (STAT) block 251
statistics gathering (STAT) blocks 204
statistics m onitoring 251
Status Register B (HDLC) 321
-
325
Status Register C (HDLC) 325
Status/Inte rrupt Enable
register 191
-
193
STL Configuration register 228, 229
STL registers 228
-
230
STL Test register 228, 230
strobe pulse width 373
SWI exception 47, 477
synchronous mode. See X1 mode
synchronous timing mode 26 7
system bus interface
pinout information 19, 483
signal descriptions 29, 491
system clock
frequency definitions 98
generation 97
System Control register 63
-
67
system registers 63
-
69
system rese t
pinout information 26, 488
signal descriptions 36, 496
System Status register 67
-
68
T
TA* and TEA* cycle termination 143
TAG format 115
technical support xxxi
terminating cycles 143
Test Operate Receive Counters
(RECTCL) 243
Test Operate Transmit Counters
(TECTCL) 241
test support
signal descriptions 37, 496
thermal con siderations 420
Thumb architecture 46
Thumb instructions 110
Timer Control registers 71
-
72
Timer Status register 72
timers 10, 12
net50_20_1.book Page 17 Friday, September 19, 2003 10:41 AM
Index-18
n n n n n n n
timers 1 & 2
interrupt sources 54
timing registers
Software Service register 69, 70
Timer Control regis ters 70, 71
-
72
Timer Status register 70, 72
total p ropagation delay 423
transfer acknowledge (TA*) signal 142
transfer error acknowledge (TEA*)
signal 143
Transmit Byte Counter regis ter
(TBCT) 239
Transmit Control registers 231
-
241
Coll ision Wi ndow/Collis i on
Retry 238
Inter-Packet Gap (IPG) 231
-
237
simulation registers 23 9
-
241
Transmit Counter Decodes
(ECTDC) 241
transmit data coding 300
transmit FIFO 202
transmit FIF O interface 271
DMA con tr oller 272
processor interrupts 271
Transmit Masked Random Number
(MRNG) 240
Transmit Packet Nibble Counter
(PCNT) 239
Transmit Random Number Generator
(RNG) 240
trasnmitter
SPI master 276
SPI slave 279
TTXEN 225
U
UART mode 264, 266
-
267, 295, 301, 304,
305, 306, 307, 318
framing protocol 266
UARTS-SPI-GPIO
pinout information 25, 487
signal descriptions 35, 494
undefined exception 47, 476
universal asynchronous/synchronous
receiver/transmitter
channels 263
V
vector table 48
W
WAIT configuration 167
watch-dog reset 102
watch-dog timer
interrupt sources 53
write command 162
write enable (WE*) signal 141
X
X1 mode 308
bit rates 3 12
serial channel timing 308
x16 (SDRAM)
bursting considerations 164
configuration 166
X16 mode 308
bit-rates 312
x32 SDRAM configuration 164
net50_20_1.book Page 18 Friday, September 19, 2003 10:41 AM
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