SZESD7C5.0DT5G - ON Semiconductor L.L.C.

March, 2012 − Rev. 3

1Publication Order Number:

ESD7C3.3D/D

ESD7C, SZESD7C SERIES

Transient Voltage

Suppressors

Micro−Packaged Diodes for ESD Protection

The ESD7CxxD Series is designed to protect voltage sensitive

components from ESD. Excellent clamping capability, low leakage, and

fast response time make these parts ideal for ESD protection on designs

where board space is at a premium. Because of its small size, it is suited

for use in cellular phones, portable devices, digital cameras, power

supplies and many other portable applications.

Specification Features:

•Low Capacitance 6.2 pF to 13 pF

•Low Clamping Voltage

•Small Body Outline Dimensions:

0.047″ x 0.047″ (1.20 mm x 1.20 mm)

•Low Body Height: 0.020″ (0.5 mm)

•Stand−off Voltage: 3.3 V, 5 V

•Low Leakage

•Response Time < 1 ns

•ESD Rating of Class 3 (> 16 kV) per Human Body Model

•IEC61000−4−2 Level 4 ESD Protection

•SZ Prefix for Automotive and Other Applications Requiring Unique

Site and Control Change Requirements; AEC−Q101 Qualified and

PPAP Capable

•These are Pb−Free Devices

Mechanical Characteristics:

CASE: Void-free, transfer-molded, thermosetting plastic

Epoxy Meets UL 94 V−0

LEAD FINISH: 100% Matte Sn (Tin)

MOUNTING POSITION: Any

QUALIFIED MAX REFLOW TEMPERATURE: 260°C

Device Meets MSL 1 Requirements

MAXIMUM RATINGS

Rating Symbol Value Unit

IEC 61000−4−2 (ESD) Contact

Air

±8.0

±15

Total Power Dissipation on FR−5 Board

(Note 1) @ TA = 25°C

Derate above 25°C

Thermal Resistance Junction−to−Ambient

⎪

RqJA

240

1.9

525

mW/°C

°C/W

Junction and Storage Temperature Range TJ, Tstg −55 to

+150

°C

Lead Solder Temperature − Maximum

(10 Second Duration)

TL260 °C

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

1. FR−5 = 1.0 x 0.75 x 0.62 in.

See Application Note AND8308/D for further description of survivability specs.

PIN 1. CATHODE

2. CATHODE

3. ANODE

Device Package Shipping†

ORDERING INFORMATION

ESD7CxxDT5G SOT−723

(Pb−Free)

8000 /

Tape & Reel

MARKING

DIAGRAM

http://onsemi.com

SOT−723

CASE 631AA

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specifications

Brochure, BRD8011/D.

L5 = Specific Device Code

M = Date Code

L5 M

See specific marking information in the device marking

column of the table on page 2 of this data sheet.

DEVICE MARKING INFORMATION

*Date Code orientation and/or position may

vary depending upon manufacturing location.

SZESD7CxxDT5G SOT−723

(Pb−Free)

8000 /

Tape & Reel

ESD7C, SZESD7C SERIES

http://onsemi.com

ELECTRICAL CHARACTERISTICS

(TA = 25°C unless otherwise noted)

Symbol Parameter

IPP Maximum Reverse Peak Pulse Current

VCClamping Voltage @ IPP

VRWM Working Peak Reverse Voltage

IRMaximum Reverse Leakage Current @ VRWM

VBR Breakdown Voltage @ IT

ITTest Current

IFForward Current

VFForward Voltage @ IF

Ppk Peak Power Dissipation

CMax. Capacitance @VR = 0 and f = 1 MHz

*See Application Note AND8308/D for detailed explanations of

datasheet parameters. Uni−Directional TVS

IPP

VRWM

VCVBR

ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted, VF = 1.1 V Max. @ IF = 10 mA)

Device (Note 2)

Device

Marking

VRWM (V) IR (mA) @ VRWM

VBR (V) @ IT

(Note 3) IT

C (pF)

(Note 4)

C (pF)

(Note 4) VC

Max Max Min mA Typ Max

Per IEC61000−4−2

(Note 5)

ESD7C3.3DT5G L5 3.3 1.0 5.0 1.0 12 13 Figures 1 and 2

See Below

(Note 6)

ESD7C5.0DT5G L4 5.0 0.5 11 1.0 6.0 6.2

2. Include SZ−prefix devices where applicable.

3. VBR is measured with a pulse test current IT at an ambient temperature of 25°C.

4. Capacitance of one diode at f = 1 MHz, VR = 0 V, TA = 25°C.

5. For test procedure see Figures 3 and 4 and Application Note AND8307/D.

6. ESD7C5.0DT5G shown below. Other voltages available upon request.

Figure 1. ESD Clamping Voltage Screenshot

Positive 8 kV Contact per IEC61000−4−2

Figure 2. ESD Clamping Voltage Screenshot

Negative 8 kV Contact per IEC61000−4−2

ESD7C, SZESD7C SERIES

http://onsemi.com

IEC 61000−4−2 Spec.

Level

Test

Voltage

(kV)

First Peak

Current

(A)

Current at

30 ns (A)

Current at

60 ns (A)

1 2 7.5 4 2

2 4 15 8 4

3 6 22.5 12 6

4 8 30 16 8

Ipeak

90%

10%

IEC61000−4−2 Waveform

100%

I @ 30 ns

I @ 60 ns

tP = 0.7 ns to 1 ns

Figure 3. IEC61000−4−2 Spec

Figure 4. Diagram of ESD Test Setup

50 W

Cable

TVS Oscilloscope

ESD Gun

The following is taken from Application Note

AND8308/D − Interpretation of Datasheet Parameters

for ESD Devices.

ESD Voltage Clamping

For sensitive circuit elements it is important to limit the

voltage that an IC will be exposed to during an ESD event

to as low a voltage as possible. The ESD clamping voltage

is the voltage drop across the ESD protection diode during

an ESD event per the IEC61000−4−2 waveform. Since the

IEC61000−4−2 was written as a pass/fail spec for larger

systems such as cell phones or laptop computers it is not

clearly defined in the spec how to specify a clamping voltage

at the device level. ON Semiconductor has developed a way

to examine the entire voltage waveform across the ESD

protection diode over the time domain of an ESD pulse in the

form of an oscilloscope screenshot, which can be found on

the datasheets for all ESD protection diodes. For more

information on how ON Semiconductor creates these

screenshots and how to interpret them please refer to

AND8307/D.

ESD7C, SZESD7C SERIES

http://onsemi.com

PACKAGE DIMENSIONS

SOT−723

CASE 631AA

ISSUE D

DIM MIN NOM MAX

MILLIMETERS

A0.45 0.50 0.55

b0.15 0.21 0.27

b1 0.25 0.31 0.37

C0.07 0.12 0.17

D1.15 1.20 1.25

E0.75 0.80 0.85

e0.40 BSC

H1.15 1.20 1.25

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. MAXIMUM LEAD THICKNESS INCLUDES LEAD

FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM

THICKNESS OF BASE MATERIAL.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLD

FLASH, PROTRUSIONS OR GATE BURRS.

−Y−

−X−

X0.08 Y

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

L2 0.15 0.20 0.25

0.29 REF

TOP VIEW

BOTTOM VIEW

SIDE VIEW

RECOMMENDED

DIMENSIONS: MILLIMETERS

0.40

1.50

PACKAGE

OUTLINE

0.27

0.52

3X 0.36

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ESD7C3.3D/D

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