1
FEATURES
DESCRIPTION
4
5
6
7
3
2
1
8
9
15
10 16
12
14
11
13
CLOCK
RT
CT
RAMP
E/A Out
NI
INV
Error
Amp
Soft Start
ILIM / SD
VCC
GND VREF
Pwr GND
Out B
Out A
Vc
OSC PWM Latch
(Set Dom.)
R
S
1.25 V
Wide Bandwidth
Error Amp.
+
−Inhibit
ILIM
CPRTR
1 V
1.4 V
9 V
Shutdown
CPRTR
UVLO
VCC Good Gate REF
Gen
Internal
Bias 4 V VREF Good
Output
Inhibit
T
9 µA
VIN
Toggler F/F
VDG−92032−2
UC1825-SP
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............................................................................................................................................................................................... SLUS870 – JANUARY 2009
RAD-TOLERANT CLASS V, HIGH-SPEED PWM CONTROLLER
•QML-V Qualified, SMD 5962-87681•Rad-Tolerant: 30 kRad (Si) TID
(1)
The UC1825 PWM control device is optimized forhigh-frequency switched mode power supply•Compatible With Voltage- or Current-Mode
applications. Particular care was given to minimizingTopologies
propagation delays through the comparators and•Practical Operation Switching Frequencies to
logic circuitry while maximizing bandwidth and slew1 MHz
rate of the error amplifier. This controller is designedfor use in either current-mode or voltage mode•50-ns Propagation Delay-to-Output
systems with the capability for input voltage•High-Current Dual Totem Pole Outputs
feed-forward.(1.5 A Peak)
Protection circuitry includes a current limit comparator•Wide Bandwidth Error Amplifier
with a 1-V threshold, a TTL compatible shutdown•Fully Latched Logic With Double-Pulse
port, and a soft start pin which will double as aSuppression
maximum duty-cycle clamp. The logic is fully latched•Pulse-by-Pulse Current Limiting
to provide jitter-free operation and prohibit multiplepulses at an output. An undervoltage lockout section•Soft Start/Maximum Duty-Cycle Control
with 800 mV of hysteresis assures low start up•Undervoltage Lockout With Hysteresis
current. During undervoltage lockout, the outputs are•Low Start-Up Current (1.1 mA)
high impedance.
This device features totem pole outputs designed tosource and sink high peak currents from capacitive(1) Radiation tolerance is a typical value based upon initial device
loads, such as the gate of a power MOSFET. The onqualification with dose rate = 10 mrad/sec. Radiation LotAcceptance Testing is available - contact factory for details. state is designed as a high level.
BLOCK DIAGRAM
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2009, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
UC1825-SP
SLUS870 – JANUARY 2009 ...............................................................................................................................................................................................
www.ti.com
This device has limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
(1)
T
A
PACKAGE
(2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
CDIP – J 5962-8768104VEA UC1825J-SP– 55 ° C to 125 ° C
LCCC – FK 5962-8768104V2A UC1825FK-SP
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com .(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging .
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Product Folder Link(s): UC1825-SP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
INV
NI
E/A Out
Clock
RT
CT
Ramp
Soft Start
VREF 5.1 V
VCC
Out B
VC
Pwr Gnd
Out A
Gnd
ILIM/SD
3 2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
Out B
VC
NC
Pwr Gnd
Out A
E/A Out
Clock
NC
RT
CT
NI
INV
NC
ILIM/SD
Gnd V
V
Ramp
Soft Start
NC
CC
REF 5.1 V
UC1825-SP
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............................................................................................................................................................................................... SLUS870 – JANUARY 2009
J PACKAGE FK PACKAGE(TOP VIEW) (TOP VIEW)
Table 1. TERMINAL FUNCTIONS
NO.NAME I/O DESCRIPTIONJ FK
Clock 4 5 O Output of the internal oscillatorTiming capacitor connection pin for oscillator frequency programming. The timing capacitorC
T
6 8 I
should be connected to the device ground using minimal trace length.E/A Out 3 4 O Output of the error amplifier for compensationGnd 10 13 - Analog ground return pinILIM/SD 9 12 I Input to the current limit comparator and the shutdown comparatorINV 1 2 I Inverting input to the error amplifierNC 1, 6, 11, 16 - No connectionNI 2 3 I Non-inverting input to the error amplifierOut A 11 14 O High-current totem pole output A of the on-chip drive stageOut B 14 18 O High-current totem pole output B of the on-chip drive stagePwr Gnd 12 15 - Ground return pin for the output driver stageNon-inverting input to the PWM comparator with 1.25-V internal input offset. In voltageRamp 7 9 I mode operation this serves as the input voltage feed-forward function by using the CTramp. In peak current mode operation, this serves as the slope compensation input.R
T
5 7 I Timing resistor connection pin for oscillator frequency programmingSoft Start 8 10 I Soft-start input pin which also doubles as the maximum duty cycle clampPower supply pin for the output stage. This pin should be bypassed with a 0.1- µFV
C
13 17 -
monolithic ceramic low ESL capacitor with minimal trace lengths.Power supply pin for the device. This pin should be bypassed with a 0.1- µF monolithicV
CC
15 19 -
ceramic low ESL capacitor with minimal trace lengths.5.1-V reference. For stability, the reference should be bypassed with a 0.1- µF monolithicV
REF
5.1 V 16 20 O
ceramic low ESL capacitor and minimal trace length to the ground plane.
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): UC1825-SP
ABSOLUTE MAXIMUM RATINGS
(1)
RECOMMENDED OPERATING CONDITIONS
THERMAL RATINGS TABLE
UC1825-SP
SLUS870 – JANUARY 2009 ...............................................................................................................................................................................................
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UNIT
Supply voltage V
C
, V
CC
30 VDC 0.5Output current, source or sink, Out A, Out B APulse (0.5 µs) 2.0INV, NI, Ramp – 0.3 to 7Analog inputs VSoft Start, ILIM/SD – 0.3 to 6Clock output current Clock – 5Error amplifier output current E/A Out 5
mASoft-start sink current Soft Start 20Oscillator charging current R
T
– 5Power dissipation 1 WStorage temperature range – 65 to 150
° CLead temperature (soldering, 10 seconds) 300
(1) All voltages are with respect to GND; all currents are positive into, negative out of part; pin numbers refer to DIL-16 package.
over operating free-air temperature range (T
A
= T
J
= – 55 ° C to 125 ° C), unless otherwise noted.
MIN MAX UNIT
V
CC
Supply voltage 10 30 VSink/source output current (continuous or time average) 0 100 mAReference load current 0 10 mA
θ
JA
θ
JCPACKAGE
( ° C/W) ( ° C/W)
DIL-16 (J) 80 – 120 28
(1)
LCC-20 (FK) 70 – 80 20
(1)
(1) θ
JC
data values stated were derived from MIL-STD-1835B. MIL-STD-1835B states that the baseline values shown are worst case(mean + 2s) for a 60 × 60 mil microcircit device silicon die and applicable for devices with die sizes up to 14400 square mils. For devicedie sizes greater than 14400 square mils use the following values; dual-in-line, 11 ° C/W; flat pack 10 ° C/W; pin grid array, 10 ° C/W.
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Product Folder Link(s): UC1825-SP
ELECTRICAL CHARACTERISTICS
UC1825-SP
www.ti.com
............................................................................................................................................................................................... SLUS870 – JANUARY 2009
Unless otherwise stated, these specifications apply for R
T
= 3.65 k Ω, C
T
= 1 nF, V
CC
= 15 V, – 55 ° C < T
A
< 125 ° C, T
A
= T
J
PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT
REFERENCE
Output voltage T
J
= 25 ° C, I
O
= 1 mA 5.05 5.10 5.15 VLine regulation 10 V < V
CC
< 30 V 2 20 mVLoad regulation 1 mA < I
O
< 10 mA 5 20 mVTotal output variation Line, load, temperature 5.0 5.2 VOutput noise voltage 10 Hz < f < 10 kHz 50 µVShort-circuit current V
REF
= 0 V – 15 – 50 – 100 mA
OSCILLATOR SECTION
Initial accuracy T
J
= 25 ° C 360 400 440 kHzVoltage stability 10 V < V
CC
< 30 V 0.2% 2%Temperature stability T
MIN
< T
A
< T
MAX
5%Total variation Line, Temperature 340 460 kHzClock out high 3.9 4.5 VClock out low 2.3 2.9 VRamp peak
(1)
2.6 2.8 3.0 VRamp valley
(1)
0.7 1.0 1.25 VRamp valley to peak
(1)
1.6 1.8 2.1 V
ERROR AMPLIFIER
Input offset voltage 10 mVInput bias current 0.6 3 µAInput offset current 0.1 1 µAOpen-loop gain 1 V < V
O
< 4 V 60 95 dBCMRR 1.5 V < V
CM
< 5.5 V 75 95 dBPSRR 10 V < V
CC
< 30 V 85 110 dBOutput sink current V
E/AOut
= 1 V 1 2.5 mAOutput source current V
E/AOut
= 4 V – 0.5 – 1.3 mAOutput high voltage I
E/AOut
= – 0.5 mA 4.0 4.7 5.0 VOutput low voltage I
E/AOut
= 1 mA 0 0.5 1.0 VGain bandwidth product
(1)
f = 200 kHz 5 10.5 MHzSlew rate
(1)
4 9 V/ µs
PWM COMPARATOR
Ramp bias current V
Ramp
= 0 V – 1 – 5 µADuty cycle range 0% 80%E/A out zero dc threshold V
Ramp
= 0 V 1.1 1.25 VDelay to output
(1)
50 80 ns
SOFT-START
Charge current V
Soft Start
= 0.5 V 3 9 20 µADischarge current V
Soft Start
= 1 V 1 mA
CURRENT LIMIT/SHUTDOWN
Current limit/shutdown bias current 0 < V
ILIM/SD
< 4 V 15 µACurrent limit threshold 0.9 1.0 1.1 VShutdown threshold 1.25 1.40 1.55 VDelay to output
(1)
50 80 ns
(1) Parameters ensured by design and/or characterization, if not production tested.
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Product Folder Link(s): UC1825-SP
UC1825-SP
SLUS870 – JANUARY 2009 ...............................................................................................................................................................................................
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ELECTRICAL CHARACTERISTICS (continued)Unless otherwise stated, these specifications apply for R
T
= 3.65 k Ω, C
T
= 1 nF, V
CC
= 15 V, – 55 ° C < T
A
< 125 ° C, T
A
= T
J
PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT
OUTPUT
I
OUT
= 20 mA 0.25 0.40 VLow-level output voltage
I
OUT
= 200 mA 1.2 2.2 VI
OUT
= – 20 mA 13.0 13.5 VHigh-level output voltage
I
OUT
= – 200 mA 12.0 13.0 VCollector leakage V
C
= 30 V 10 500 µARise/fall time
(2)
C
L
= 1 nF 30 75 ns
UNDER-VOLTAGE LOCKOUT
Start threshold 8.8 9.2 9.6 VUVLO hysteresis 0.4 0.8 1.2 V
SUPPLY CURRENT SECTION
Startup current V
CC
= 8 V 1.1 2.5 mAI
CC
V
INV
= V
Ramp
= V
ILIM/SD
= 0 V, V
NI
= 1 V 22 33 mA
(2) Parameters ensured by design and/or characterization, if not production tested.
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Product Folder Link(s): UC1825-SP
PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS
INV
NON INV
Error Amplifier Output
VREF 5.1 V
200 W
UC1825
Simplified Schematic
1
2
3
16
100
80
60
40
40
0
−20
f − Frequency − Hz
01 K 10 K 100 K 1 M 10 M 100 M
0
OPEN LOOP FREQUENCY RESPONSE
−90
−180
Phase − °
AV− VVoltage
−
AV
0
5
4
3
2
0 0.2 0.4 0.6
10.8 1
VIN
VIOUT
− VVoltage
t − Time − ms
UNITY GAIN SLEW RATE
UC1825-SP
www.ti.com
............................................................................................................................................................................................... SLUS870 – JANUARY 2009
High speed circuits demand careful attention to layout and component placement. To ensure proper performanceof the UC1825 follow these rules:1. Use a ground plane.2. Damp or clamp parasitic inductive kick energy from the gate of driven MOSFETs. Do not allow the outputpins to ring below ground. A series gate resistor or a shunt 1-A Schottky diode at the output pin serves thispurpose.
3. Bypass V
CC
, V
C
, and V
REF
. Use 0.1- µF monolithic ceramic capacitors with low equivalent series inductance.Allow less than 1-cm of total lead length for each capacitor between the bypassed pin and the ground plane.4. Treat the timing capacitor, C
T
, like a bypass capacitor.
Figure 1. Error Amplifier
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Product Folder Link(s): UC1825-SP
Oscillator
UC1825
1.25 V
From E/A
CT
Ramp
CT
Conventional (Voltage Mode)
6
7
6
7
Oscillator
1.25 V
From E/A
ISWITCH UC1825
*
*
RSENSE
Ramp
CTCT
Current − Mode
* A small filter may be required to suppress
switch noise.
80
100
120
140
160
5
6
4
RT
CT
IR3 V IC = IR
5.1 V
Clock
TD400 mA
Blanking
UC1825
4.70
2.20
1
0.47
0.22
0.10
0.047
0.047 1 2.2 4.7 10 22 47 100
td− Deadtime − Sµ
Ct − Total Capacitance − nF
DEADTIME
vs
TOTAL CAPACITANCE
3 kΩ,
RT = 100 kΩ
4.7 nF
2.2 nF
1 nF
470 pF
10 nF
22 nF
47 nF
100 nF
100 k
10 k
1 k
100 1 k 10 k 100 k 1 M
− Timing Resistance −RTΩ
TIMING RESISTANCE
vs
FREQUENCY
f − Frequency − Hz 10 k 100 k 1 M
td− Deadtime − Sµ
f − Frequency − Hz
DEADTIME
vs
FREQUENCY
1 nF
470 pF
UC1825-SP
SLUS870 – JANUARY 2009 ...............................................................................................................................................................................................
www.ti.com
Figure 2. PWM Applications
Figure 3. Oscillator Circuit
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Product Folder Link(s): UC1825-SP
4
5
6
4
16
6
UC1825
Clock
RT
CT
Master
RT5
UC1825
Slave
Clock
VREF
RT
CT
Local
Ramp
CT
Two Units in Close Proximity
16
4
5
6
UC1825
VREF
Clock
RT
CT
Local
Ramp
Master
10 mF2N222
RT
CT
43 W0.1 mF
43 W0.1 mF
To
Other
Slaves
24 W
24 W
CT
5
6
UC1825
Slave
Local
Ramp
CT
RT
1.5 W
RT
CT
5
6
RT
43 W0.1 mF
43 W0.1 mF
470 W
Generalized Synchronization
RFF
CFF
7
UC1825
RT
VIN
16
5
6
Ramp
Clock
CT
VIN
RR9
14
11
ILIM
Shut-
Down
UC1825 Out B
Out A
CR
UC1825-SP
www.ti.com
............................................................................................................................................................................................... SLUS870 – JANUARY 2009
Figure 4. Synchronized Operation
Figure 5. Forward Technique for Off-Line Voltage Mode Application
The circuit shown in Figure 5 will achieve a constant volt-second product clamp over varying input voltages. Theramp generator components, R
T
and C
R
are chosen so that the ramp at the ILIM/SD pin crosses the 1-Vthreshold at the same time the desired maximum volt-second product is reached. The delay through thefunctional nor block must be such that the ramp capacitor can be completely discharged during the minimumdeadtime.
Figure 6. Constant Volt-Second Clamp Circuit
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Product Folder Link(s): UC1825-SP
15
13
11/14
12
10
UC1825 VCC
VC
Out
Pwr Gnd
Gnd
Simplified Schematic
15
10
5
00 40 80 120 160 200
0.2
0
−0.2
− Output Voltage − V
VO
I − Load Current − A
L
t − Time − ns
RISE/FALL TIME
CL = 1 nF
0 100 200 300 400
t − Time − ns 500
15
10
5
0
− Output Voltage − VVO
2
0
−2
I − Load Current − A
L
CL = 10 nF
RISE/FALL TIME
IO − Output Current − A
− Voltage Saturation − V
VSAT
00.5 1.5
15
10
5
01
Source
Sink
SATURATION CURVES
UC1825-SP
SLUS870 – JANUARY 2009 ...............................................................................................................................................................................................
www.ti.com
Figure 7. Output Section
The circuit in Figure 7 is useful for exercising many of the UC1825 functions and measuring their specifications.
As with any wideband circuit, careful grounding and bypass procedures should be followed. The use of a groundplane is highly recommended.
10 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): UC1825-SP
VDG−92032−2
UC1825
Clock
RL
CT
Ramp
Oscillator
E/A Out
Non INV
INV
Soft Start
Error
Amp
ILIM Shutdown
VCC
VC
Out A
Out B
Pwr Gnd
VREF 5.1 V
Gnd
2 x 1N5820
0.1 mF
0.1 mF
0.1 mF
15 V
15 V
10 mF
RT 3.65 kW
CT 1 nF
50 W
22 kW
10 kW
3.3 kW
27 kW
10 kW
27 kW
4.7 kW
4.7 kW
68 kW
10 mF
4
5
6
7
3
2
1
8
9
15
13
11
14
12
10
16
UC1825-SP
www.ti.com
............................................................................................................................................................................................... SLUS870 – JANUARY 2009
Figure 8. Open-Loop Laboratory Test Fixture
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Product Folder Link(s): UC1825-SP
1
3
4
5
9
7
6
12
INV
CLOCK
UC2835
16
2
14
11NI
15 13
10 8
SS
15 V
22 pF
120 pF 10 nF
1N 5820
150 pF
1 nF
42 V to 56 V
UDG−92033
4.7 µF
VIN
1 kΩ
1 kΩ
1 kΩ
10 kΩ
CT
470 pF
1 kΩ
8.2 kΩ
0.1 µF
1.5 kΩ
3.3 kΩ
4.3 kΩ
0.1 µF
390 Ω
100 Ω
4.7 µF
4.7 µF12 Ω
0.8 µH
VOUT 5 V
1 A to 10 A
6 µF
5:1
+
−
−
+
VCC VC
VREF
E/A Out Ramp
CT
RTPwr Gnd
Gnd
ILIM/SD
Out A
Out B
UC1825-SP
SLUS870 – JANUARY 2009 ...............................................................................................................................................................................................
www.ti.com
Figure 9. Design Example: 50 W, 48-V to 5-V DC-to-DC Converter – 1.5-MHz Clock Frequency
12 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): UC1825-SP
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
5962-8768101V2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
5962-8768101VEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
5962-8768104V2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
5962-8768104VEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
UC1825LQMLV ACTIVE LCCC FK 20 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UC1825-SP :
•Catalog: UC1825
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
PACKAGE OPTION ADDENDUM
www.ti.com 3-Mar-2009
Addendum-Page 1
MECHANICAL DATA
MLCC006B – OCTOBER 1996
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
4040140/D 10/96
28 TERMINAL SHOWN
B
0.358
(9,09)
MAX
(11,63)
0.560
(14,22)
0.560
0.458
0.858
(21,8)
1.063
(27,0)
(14,22)
A
NO. OF
MINMAX
0.358
0.660
0.761
0.458
0.342
(8,69)
MIN
(11,23)
(16,26)
0.640
0.739
0.442
(9,09)
(11,63)
(16,76)
0.962
1.165
(23,83)
0.938
(28,99)
1.141
(24,43)
(29,59)
(19,32)(18,78)
**
20
28
52
44
68
84
0.020 (0,51)
TERMINALS
0.080 (2,03)
0.064 (1,63)
(7,80)
0.307
(10,31)
0.406
(12,58)
0.495
(12,58)
0.495
(21,6)
0.850
(26,6)
1.047
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.035 (0,89)
0.010 (0,25)
12
1314151618 17
11
10
8
9
7
5
432
0.020 (0,51)
0.010 (0,25)
6
12826 27
19
21
B SQ
A SQ 22
23
24
25
20
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
IMPORTANT NOTICE
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