UC1825-SP www.ti.com............................................................................................................................................................................................... SLUS870 - JANUARY 2009 RAD-TOLERANT CLASS V, HIGH-SPEED PWM CONTROLLER FEATURES 1 * * * * * * * * * * * * (1) DESCRIPTION QML-V Qualified, SMD 5962-87681 Rad-Tolerant: 30 kRad (Si) TID (1) Compatible With Voltage- or Current-Mode Topologies Practical Operation Switching Frequencies to 1 MHz 50-ns Propagation Delay-to-Output High-Current Dual Totem Pole Outputs (1.5 A Peak) Wide Bandwidth Error Amplifier Fully Latched Logic With Double-Pulse Suppression Pulse-by-Pulse Current Limiting Soft Start/Maximum Duty-Cycle Control Undervoltage Lockout With Hysteresis Low Start-Up Current (1.1 mA) The UC1825 PWM control device is optimized for high-frequency switched mode power supply applications. Particular care was given to minimizing propagation delays through the comparators and logic circuitry while maximizing bandwidth and slew rate of the error amplifier. This controller is designed for use in either current-mode or voltage mode systems with the capability for input voltage feed-forward. Protection circuitry includes a current limit comparator with a 1-V threshold, a TTL compatible shutdown port, and a soft start pin which will double as a maximum duty-cycle clamp. The logic is fully latched to provide jitter-free operation and prohibit multiple pulses at an output. An undervoltage lockout section with 800 mV of hysteresis assures low start up current. During undervoltage lockout, the outputs are high impedance. This device features totem pole outputs designed to source and sink high peak currents from capacitive loads, such as the gate of a power MOSFET. The on state is designed as a high level. Radiation tolerance is a typical value based upon initial device qualification with dose rate = 10 mrad/sec. Radiation Lot Acceptance Testing is available - contact factory for details. BLOCK DIAGRAM CLOCK 4 RT 5 CT 6 RAMP 7 OSC PWM Latch (Set Dom.) 1.25 V R S E/A Out 3 Wide Bandwidth Error Amp. Error Amp NI 2 + INV 1 - VIN Inhibit 9 A Toggler F/F Soft Start 8 T ILIM CPRTR 1V ILIM / SD 13 Vc 11 Out A 9 14 Out B Shutdown CPRTR 12 Pwr GND 1.4 V Output Inhibit VCC 15 9V Internal Bias UVLO GND 10 4V Gate VCC Good REF Gen VREF Good 16 VREF VDG-92032-2 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2009, Texas Instruments Incorporated UC1825-SP SLUS870 - JANUARY 2009............................................................................................................................................................................................... www.ti.com This device has limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) TA -55C to 125C (1) (2) 2 PACKAGE (2) ORDERABLE PART NUMBER CDIP - J 5962-8768104VEA UC1825J-SP LCCC - FK 5962-8768104V2A UC1825FK-SP TOP-SIDE MARKING For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): UC1825-SP UC1825-SP www.ti.com............................................................................................................................................................................................... SLUS870 - JANUARY 2009 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VREF 5.1 V VCC Out B VC Pwr Gnd Out A Gnd ILIM/SD E/A Out Clock NC RT CT 4 3 2 1 20 19 18 5 6 17 16 7 8 15 14 9 10 11 12 13 Out B VC NC Pwr Gnd Out A Ramp Soft Start NC ILIM/SD Gnd INV NI E/A Out Clock RT CT Ramp Soft Start FK PACKAGE (TOP VIEW) NI INV NC V REF 5.1 V VCC J PACKAGE (TOP VIEW) Table 1. TERMINAL FUNCTIONS NAME NO. I/O DESCRIPTION J FK Clock 4 5 O Output of the internal oscillator CT 6 8 I Timing capacitor connection pin for oscillator frequency programming. The timing capacitor should be connected to the device ground using minimal trace length. E/A Out 3 4 O Output of the error amplifier for compensation Gnd 10 13 - Analog ground return pin ILIM/SD 9 12 I Input to the current limit comparator and the shutdown comparator INV 1 2 I Inverting input to the error amplifier 1, 6, 11, 16 - No connection NC NI 2 3 I Non-inverting input to the error amplifier Out A 11 14 O High-current totem pole output A of the on-chip drive stage Out B 14 18 O High-current totem pole output B of the on-chip drive stage Pwr Gnd 12 15 - Ground return pin for the output driver stage Ramp 7 9 I Non-inverting input to the PWM comparator with 1.25-V internal input offset. In voltage mode operation this serves as the input voltage feed-forward function by using the CT ramp. In peak current mode operation, this serves as the slope compensation input. RT 5 7 I Timing resistor connection pin for oscillator frequency programming Soft Start 8 10 I Soft-start input pin which also doubles as the maximum duty cycle clamp VC 13 17 - Power supply pin for the output stage. This pin should be bypassed with a 0.1-F monolithic ceramic low ESL capacitor with minimal trace lengths. VCC 15 19 - Power supply pin for the device. This pin should be bypassed with a 0.1-F monolithic ceramic low ESL capacitor with minimal trace lengths. VREF5.1 V 16 20 O 5.1-V reference. For stability, the reference should be bypassed with a 0.1-F monolithic ceramic low ESL capacitor and minimal trace length to the ground plane. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): UC1825-SP 3 UC1825-SP SLUS870 - JANUARY 2009............................................................................................................................................................................................... www.ti.com ABSOLUTE MAXIMUM RATINGS (1) UNIT Supply voltage Output current, source or sink, Out A, Out B Analog inputs VC, VCC 30 DC 0.5 Pulse (0.5 s) 2.0 INV, NI, Ramp -0.3 to 7 Soft Start, ILIM/SD -0.3 to 6 Clock output current Clock Error amplifier output current E/A Out 5 Soft-start sink current Soft Start 20 Oscillator charging current RT -5 A V -5 Power dissipation mA 1 Storage temperature range W -65 to 150 Lead temperature (soldering, 10 seconds) (1) V 300 C All voltages are with respect to GND; all currents are positive into, negative out of part; pin numbers refer to DIL-16 package. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (TA = TJ = -55C to 125C), unless otherwise noted. MIN VCC Supply voltage MAX UNIT 10 30 V Sink/source output current (continuous or time average) 0 100 mA Reference load current 0 10 mA THERMAL RATINGS TABLE (1) 4 PACKAGE JA (C/W) JC (C/W) DIL-16 (J) 80-120 28 (1) LCC-20 (FK) 70-80 20 (1) JC data values stated were derived from MIL-STD-1835B. MIL-STD-1835B states that the baseline values shown are worst case (mean + 2s) for a 60 x 60 mil microcircit device silicon die and applicable for devices with die sizes up to 14400 square mils. For device die sizes greater than 14400 square mils use the following values; dual-in-line, 11C/W; flat pack 10C/W; pin grid array, 10C/W. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): UC1825-SP UC1825-SP www.ti.com............................................................................................................................................................................................... SLUS870 - JANUARY 2009 ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for RT = 3.65 k, CT = 1 nF, VCC = 15 V, -55C < TA < 125C, TA = TJ PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT REFERENCE Output voltage TJ = 25C, IO = 1 mA 5.05 5.10 5.15 Line regulation Load regulation Total output variation Line, load, temperature 10 V < VCC < 30 V 2 20 mV 1 mA < IO < 10 mA 5 20 mV 5.2 V Output noise voltage 10 Hz < f < 10 kHz Short-circuit current VREF = 0 V -15 Initial accuracy TJ = 25C 360 Voltage stability 10 V < VCC < 30 V Temperature stability TMIN < TA < TMAX Total variation Line, Temperature 5.0 V V 50 -50 -100 mA 400 440 kHz 0.2% 2% OSCILLATOR SECTION Clock out high 5% 340 3.9 Clock out low Ramp peak (1) Ramp valley (1) Ramp valley to peak (1) 460 4.5 kHz V 2.3 2.9 V 2.6 2.8 3.0 V 0.7 1.0 1.25 V 1.6 1.8 2.1 V ERROR AMPLIFIER Input offset voltage 10 mV Input bias current 0.6 3 A Input offset current 0.1 1 A Open-loop gain 1 V < VO < 4 V 60 95 dB CMRR 1.5 V < VCM < 5.5 V PSRR 10 V < VCC < 30 V 75 95 dB 85 110 Output sink current dB VE/AOut= 1 V 1 2.5 mA Output source current VE/AOut = 4 V -0.5 -1.3 Output high voltage IE/AOut = -0.5 mA 4.0 4.7 5.0 V Output low voltage IE/AOut = 1 mA 0 0.5 1.0 V f = 200 kHz 5 10.5 MHz 4 9 V/s Gain bandwidth product (1) Slew rate (1) mA PWM COMPARATOR Ramp bias current VRamp = 0 V Duty cycle range E/A out zero dc threshold -1 0% VRamp = 0 V 1.1 Delay to output (1) -5 A 80% 1.25 V 50 80 9 20 ns SOFT-START Charge current VSoft Start Discharge current VSoft = 0.5 V Start = 1 V 3 1 A mA CURRENT LIMIT/SHUTDOWN Current limit/shutdown bias current Shutdown threshold Delay to output (1) 15 A 0.9 1.0 1.1 V 1.25 1.40 1.55 V 50 80 ns 0 < VILIM/SD < 4 V Current limit threshold (1) Parameters ensured by design and/or characterization, if not production tested. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): UC1825-SP 5 UC1825-SP SLUS870 - JANUARY 2009............................................................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) Unless otherwise stated, these specifications apply for RT = 3.65 k, CT = 1 nF, VCC = 15 V, -55C < TA < 125C, TA = TJ PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT OUTPUT Low-level output voltage High-level output voltage Collector leakage Rise/fall time (2) IOUT = 20 mA IOUT = 200 mA 0.25 0.40 V 1.2 2.2 V IOUT = -20 mA 13.0 13.5 V IOUT = -200 mA 12.0 13.0 V VC = 30 V 10 500 A CL = 1 nF 30 75 ns UNDER-VOLTAGE LOCKOUT Start threshold 8.8 9.2 9.6 V UVLO hysteresis 0.4 0.8 1.2 V SUPPLY CURRENT SECTION Startup current VCC = 8 V 1.1 2.5 mA ICC VINV = VRamp = VILIM/SD = 0 V, VNI = 1 V 22 33 mA (2) 6 Parameters ensured by design and/or characterization, if not production tested. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): UC1825-SP UC1825-SP www.ti.com............................................................................................................................................................................................... SLUS870 - JANUARY 2009 PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS High speed circuits demand careful attention to layout and component placement. To ensure proper performance of the UC1825 follow these rules: 1. Use a ground plane. 2. Damp or clamp parasitic inductive kick energy from the gate of driven MOSFETs. Do not allow the output pins to ring below ground. A series gate resistor or a shunt 1-A Schottky diode at the output pin serves this purpose. 3. Bypass VCC, VC, and VREF. Use 0.1-F monolithic ceramic capacitors with low equivalent series inductance. Allow less than 1-cm of total lead length for each capacitor between the bypassed pin and the ground plane. 4. Treat the timing capacitor, CT, like a bypass capacitor. Simplified Schematic UC1825 VREF 5.1 V 16 Error Amplifier Output 3 INV 1 NON INV 2 200 W OPEN LOOP FREQUENCY RESPONSE UNITY GAIN SLEW RATE 100 5 4 60 VIN Voltage - V AV 40 40 0 0 0 -90 -20 0 1K 10 K 100 K 1M -180 10 M 100 M 3 VIOUT Phase - A V - Voltage - V 80 2 1 0 0.2 0.4 0.6 0.8 1 t - Time - ms f - Frequency - Hz Figure 1. Error Amplifier Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): UC1825-SP 7 UC1825-SP SLUS870 - JANUARY 2009............................................................................................................................................................................................... www.ti.com Conventional (Voltage Mode) Current - Mode ISWITCH UC1825 UC1825 CT 6 6 Oscillator CT CT Oscillator 1.25 V Ramp * 1.25 V 7 7 * Ramp RSENSE From E/A CT From E/A * A small filter may be required to suppress switch noise. Figure 2. PWM Applications DEADTIME vs TOTAL CAPACITANCE UC1825 RT 5 IR IC = IR 3V CT 4.70 t d - Deadtime - S 6 5.1 V Clock Blanking 4 TD 3 k, RT = 100 k 2.20 1 0.47 0.22 0.10 400 mA 0.047 0.047 TIMING RESISTANCE vs FREQUENCY 100 160 4.7 nF 2.2 nF 1 nF 1 nF 470 pF 10 nF 22 nF 47 nF 100 nF t d - Deadtime - S R T - Timing Resistance - 2.2 4.7 10 22 47 Ct - Total Capacitance - nF DEADTIME vs FREQUENCY 100 k 10 k 1 140 120 100 470 pF 1k 100 1k 10 k 100 k 1M 80 10 k f - Frequency - Hz 100 k 1M f - Frequency - Hz Figure 3. Oscillator Circuit 8 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): UC1825-SP UC1825-SP www.ti.com............................................................................................................................................................................................... SLUS870 - JANUARY 2009 Generalized Synchronization Two Units in Close Proximity UC1825 UC1825 VREF 16 4 Clock Clock 4 RT 2N222 10 mF 16 VREF RT 5 UC1825 UC1825 Clock 4 5 RT RT 5 43 W RT 43 W CT 6 Master CT Local Ramp CT 6 CT 43 W CT 6 Master Slave RT 1.5 W 0.1 mF 5 RT 0.1 mF 24 W 0.1 mF 470 W Local Ramp To Other Slaves CT 24 W 6 CT Slave Local Ramp Figure 4. Synchronized Operation VIN UC1825 RFF 7 Ramp 16 Clock CFF 5 CT 6 RT Figure 5. Forward Technique for Off-Line Voltage Mode Application The circuit shown in Figure 5 will achieve a constant volt-second product clamp over varying input voltages. The ramp generator components, RT and CR are chosen so that the ramp at the ILIM/SD pin crosses the 1-V threshold at the same time the desired maximum volt-second product is reached. The delay through the functional nor block must be such that the ramp capacitor can be completely discharged during the minimum deadtime. UC1825 14 VIN RR ILIM ShutDown 11 Out B Out A 9 CR Figure 6. Constant Volt-Second Clamp Circuit Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): UC1825-SP 9 UC1825-SP SLUS870 - JANUARY 2009............................................................................................................................................................................................... www.ti.com Simplified Schematic 0.2 CL = 1 nF 15 VCC 0 11/14 Out 12 Pwr Gnd 10 Gnd -0.2 L 15 I V O- Output Voltage - V 13 VC - Load Current - A RISE/FALL TIME UC1825 10 5 0 0 40 80 120 160 200 t - Time - ns RISE/FALL TIME -2 L 15 I V O- Output Voltage - V 0 10 5 V SAT - Voltage Saturation - V CL = 10 nF - Load Current - A SATURATION CURVES 2 Source 15 10 5 Sink 0 0 0 100 200 300 400 500 0 t - Time - ns 0.5 1 1.5 IO - Output Current - A Figure 7. Output Section The circuit in Figure 7 is useful for exercising many of the UC1825 functions and measuring their specifications. As with any wideband circuit, careful grounding and bypass procedures should be followed. The use of a ground plane is highly recommended. 10 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): UC1825-SP UC1825-SP www.ti.com............................................................................................................................................................................................... SLUS870 - JANUARY 2009 UC1825 VCC 15 4 Clock 5 RL CT 1 nF 50 W 27 kW 4.7 kW 22 kW 27 kW Oscillator VC 13 0.1 mF 6 CT 7 Ramp Out A 11 3 E/A Out Out B 14 68 kW 2 Non INV 10 kW Error Amp 1 INV 4.7 kW 10 mF 15 V 0.1 mF RT 3.65 kW 15 V 10 mF 2 x 1N5820 Pwr Gnd 12 Gnd 10 8 Soft Start 0.1 mF VREF 5.1 V 16 10 kW 9 ILIM Shutdown 3.3 kW VDG-92032-2 Figure 8. Open-Loop Laboratory Test Fixture Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): UC1825-SP 11 UC1825-SP SLUS870 - JANUARY 2009............................................................................................................................................................................................... www.ti.com + VIN 42 V to 56 V 390 VOUT 5 V 1 A to 10 A - 0.1 F 15 13 VCC VC 15 V + 0.8 H 4.7 F 1N 5820 Out B 14 16 VREF 6 F 1 k - 10 k 2 NI 5:1 Out A 11 1 k 4.3 k 100 UC2835 1 k 1 INV ILIM/SD 9 1 nF 4.7 F 12 4.7 F 150 pF 22 pF 3 E/A Out Ramp 7 8.2 k 3.3 k 10 nF 1 k 4 CLOCK 5 RT 1.5 k CT 6 Pwr Gnd 12 Gnd SS 10 8 120 pF CT 470 pF 0.1 F UDG-92033 Figure 9. Design Example: 50 W, 48-V to 5-V DC-to-DC Converter - 1.5-MHz Clock Frequency 12 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): UC1825-SP PACKAGE OPTION ADDENDUM www.ti.com 3-Mar-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-8768101V2A ACTIVE LCCC FK 20 1 TBD 5962-8768101VEA ACTIVE CDIP J 16 1 TBD Lead/Ball Finish MSL Peak Temp (3) POST-PLATE N / A for Pkg Type A42 5962-8768104V2A ACTIVE LCCC FK 20 1 TBD 5962-8768104VEA ACTIVE CDIP J 16 1 TBD A42 UC1825LQMLV ACTIVE LCCC FK 20 TBD Call TI N / A for Pkg Type POST-PLATE N / A for Pkg Type N / A for Pkg Type Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF UC1825-SP : * Catalog: UC1825 NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product Addendum-Page 1 MECHANICAL DATA MLCC006B - OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. 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