DF2676VFC33APV - RENESAS TECHNOLOGY

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April 1st, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

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H8S/2678 Group,

H8S/2678R Group,

H8S/2676 F-ZTATTM

Hardware Manual

User’s Manual

Rev.3.00 2006.03

Renesas 16-Bit Single-Chip

Microcomputer

H8S Family/H8S/2600 Series

H8S/2676 HD64F2676

HD6432676

H8S/2675 HD6432675

H8S/2674R HD6412674R

H8S/2673 HD6432673

H8S/2670 HD6412670

The revision list can be viewed directly by

clicking the title page.

The revision list summarizes the locations of

revisions and additions. Details should always

be checked by referring to the relevant text.

Rev. 3.00 Mar 17, 2006 page ii of l

1. These materials are intended as a reference to assist our customers in the selection of the Renesas

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a third party.

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party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or

circuit application examples contained in these materials.

3. All information contained in these materials, including product data, diagrams, charts, programs and

algorithms represents information on products at the time of publication of these materials, and are

subject to change by Renesas Technology Corp. without notice due to product improvements or

other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or

an authorized Renesas Technology Corp. product distributor for the latest product information

before purchasing a product listed herein.

The information described here may contain technical inaccuracies or typographical errors.

Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising

from these inaccuracies or errors.

Please also pay attention to information published by Renesas Technology Corp. by various means,

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8. Please contact Renesas Technology Corp. for further details on these materials or the products

contained therein.

1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and

more reliable, but there is always the possibility that trouble may occur with them. Trouble with

semiconductors may lead to personal injury, fire or property damage.

Remember to give due consideration to safety when making your circuit designs, with appropriate

measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or

(iii) prevention against any malfunction or mishap.

Keep safety first in your circuit designs!

Notes regarding these materials

Rev. 3.00 Mar 17, 2006 page iii of l

General Precautions on Handling of Product

1. Treatment of NC Pins

Note: Do not connect anything to the NC pins.

The NC (not connected) pins are either not connected to any of the internal circuitry or are

used as test pins or to reduce noise. If something is connected to the NC pins, the

operation of the LSI is not guaranteed.

2. Treatment of Unused Input Pins

Note: Fix all unused input pins to high or low level.

Generally, the input pins of CMOS products are high-impedance input pins. If unused pins

are in their open states, intermediate levels are induced by noise in the vicinity, a pass-

through cu rrent f lows internally, and a malfunction may occur.

3. Processing befo re Initialization

Note: When power is first supplied, the product’s state is undefined.

The states of internal circuits are undefined until full power is supplied throughout the

chip and a low level is input on the reset pin. During the period where th e states are

undefined, the register settings and the ou tput state of each pin are also undefined. Design

your system so that it does not malfunction because of processing while it is in this

undefined state. For those products which have a reset function, reset the LSI immediately

after the power supply has been turned on.

4. Prohibition of Access to Undefined or Reserved Addresses

Note: Access to undefined or reserved addresses is prohibited.

The undefined or reserved addresses may be used to expand functions, or test registers

may have been be allocated to these addresses. Do not access these registers; the system’s

operation is not guaranteed if they are accessed.

Rev. 3.00 Mar 17, 2006 page iv of l

Configur ation of This Manual

This manu al comprises the follo wing items:

1. General Precautions on Handling of Product

2. Configuration of This Manual

3. Preface

4. Main Revisions in This Edition

5. Contents

6. Overview

7. Description of Functional Modules

• CPU and System-Control Modules

• On-Chip Peripheral Modules

The configuration of the functional description of each module differs accord ing to the

module. However, the generic style includes the following items:

i) Feature

ii) Inpu t/Output Pin

iii) Register Description

iv) Operation

v) Usage Note

When designing an application system that includes this LSI, take notes into account. Each section

includes notes in relation to the descriptions given, and usage notes are given, as required, as the

final part of each section.

8. List of Registers

9. Electrical Characteristics

10.Appendix

The list of revisions is a summary of po ints that have been revised or added to earlier versions.

This does not include all of the revised conten ts. For details, see the actual locatio n s in this

manual.

11.Index

Rev. 3.00 Mar 17, 2006 page v of l

Preface

The H8S/2678 Group and H8S/2678R Group are microcomputers (MCU) made up of the

H8S/2600 CPU employing Renesas’ original architecture as their cores, and the peripheral

functions required to configure a system.

The H8S/2600 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a

simple and optimized instruction set for high -speed operation. The H8 S/2600 CPU can handle a

16-Mbyte linear address space.

This LSI is equipped with direct memory access controller (DMAC and EXDMAC) and data

transfer controller (DTC) bus masters, ROM and RAM, a 16-bit timer pulse unit (TPU), a

programmable pulse generator (PPG), an 8-bit timer (TMR), a watchdog timer (WDT), a serial

communication interface (SCI and IrDA), a 10-bit A/D converter, an 8-bit D/A converter, and I/O

ports as on-chip peripheral modules requ ired for system configuration

A high functionality bus controller is also provided, enabling fast and easy connection of DRAM,

SDRAM, and other kinds of memory.

A single-power flash memory (F-ZTAT*) version and masked ROM version are available for

this LSI's ROM. The F-ZTAT ve r sio n provides flexib ility as it can be reprogrammed in no time to

cope with all situations from the early stages of mass production to full-scale mass production.

This is particularly applicable to application devices with specifications that will most pro bably

change.

This manual describes this LSI’s hardware.

Note: * F-ZTAT is a trademark of Renesas Technology Corp.

Target Users: Th is manual was written f or users who will be u sin g this LSI in the design of

application systems. Target users are expected to understand the fundamentals of

electrical circuits, logical circuits, and microcomputers.

Objective: This manual was wr itten to explain the hardware func tions and electrical

characteristics of this LSI to the targ et users.

Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a

detailed descr iption of the in str uction set.

Notes on reading this manu a l:

In order to understand the overall functions of the chip

Read the manual according to the contents. This manual can be roughly categorized into parts

on the CPU, system control functions, peripheral functions and electrical characteristics.

Rev. 3.00 Mar 17, 2006 page vi of l

In order to understand the details of the CPU's functions

Read the H8S/2600 Series, H8S/2000 Series Programming Manual.

In order to understand the details of a register when its name is known

Read the index that is the final part of the manual to find the page number of the entry on the

List of Re gisters.

Examples: Register name: The following notation is used for cases when the same or a

similar func tion, e.g. 16-bit timer pulse u nit or serial

communication, is implemented on more than one channel:

XXX_N (XXX is the register name and N is the channel

number)

Bit order: The MSB is on the left and th e LSB is on the right.

Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx.

Signal notation: An overbar is added to a low-active signal: xxxx

Related Manuals: The latest version s o f all r e lated manuals are available from our web site.

Please ensure you have the latest versions of all documents you require.

http://www.renesas.com

H8S/2678 Group and H8S/2678R Group manuals:

Document Title Document No.

H8S/2678 Group, H8S/2678R Group Ha rdware Manual This manual

H8S/2600 Series, H8S/2000 Series Programming Manual REJ09B0139

User's manuals for development tools:

Document Title Document No.

H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor

User's Manual REJ10B0058

H8S, H8/300 Series Simulator/Debugger User's Manual ADE-702-037

H8S, H8/300 Series High-performance Embedded Workshop,

High-performance Debugging Interface Tutorial ADE-702-231

High-performance Embedded Workshop User's Manual ADE-702-201

Rev. 3.00 Mar 17, 2006 page vii of l

Main Revisions in This Edition

Item Page Revision (See Manual for Details)

All — All references to Hitachi, Hitachi, Ltd., Hitachi

Semiconductors, and other Hitachi brand names changed to

Renesas Technology Corp. Designation for categories

changed from “series” to “group”

6.2 Input/Output Pins

Table 6.1 Pin

Configuration

124 Symbols amended

Upper column address strobe/upper data mask enable

(Before) UCAS/DQMU → (After) UCAS/DQMU

Lower column address strobe/upper data mask enable

(Before) LCAS/DQML → (After) LCAS/DQML

124 I/O description amended

Data Transfer acknowledge 0 (DMAC) (Before) DACK0 →

(After) Output

7.5.1 Transfer

Modes

Table 7.4 DMAC

Transfer Modes

288 Table 7.4 amended

Transfer Mode Transfer Source Remarks

Short

address

mode

Dual address mode

(1) Sequential mode

•Memory address incremented or

decremented by 1 or 2

•Number of transfers:

1 to 65,536

(2) Idle mode

•Memory address fixed

•Number of transfers:

1 to 65,536

(3) Repeat mode

•Memory address incremented or

decremented by 1 or 2

• Continues transfer after sending

number of transfers (1 to 256) and

restoring the initial value

•TPU channel 0 to 5

compare match/input

capture A interrupt

•SCI transmission complete

interrupt

•SCI reception complete

interrupt

•A/D converter conversion

end interrupt

•External request

•Up to 4 channels can

operate independently

•External request

applies to channel B

only

•Single address mode

applies to channel B

only

289

Transfer Mode Transfer Source Remarks

Full

address

mode

Normal mode

(1) Auto-request

•Transfer request is internally held

• Number of transfers (1 to 65,536) is

continuously sent

•Burst/cycle steal transfer can be

selected

Auto-request •Max. 2-channel

operation, combining

channels A and B

Section 10 I/O Ports

Table 10.1 Port

Functions

428 to

432 Notes amended

Modes 3*1, 7

CKE*2 DQML*2 DQMU*2 CAS*2 RAS*2 SDRAMφ*2

WE*2

432 Notes: 1. Mode 3 is not supported in H8S/2378 Group.

2. These pins are not supported in H8S/2678 Group.

Rev. 3.00 Mar 17, 2006 page viii of l

Item Page Revision (See Manual for Details)

10.2.4 Pin Functions 445 • P27/PO7/TIOCB5/(IRQ15)/EDRAK1

Description amended

(Before) IRQ5 interrupt inp ut→ (After) IRQ15 interrupt input

445 Note 2 amended

Note: 2. IRQ15 input when ITS15 = 1.

10.6.4 Pin Functions 471 • P61/TMRI1/DREQ1/IRQ9

Description amended

The pin function is switched as shown below according to the

combination of bit DMACS in PFCR2, bit P61DDR, and bit

ITS9 in ITSR.

471 • P60/TMRI0/DREQ0/IRQ8

Description amended

The pin function is switched as shown below according to the

combination of bit DMACS in PFCR2, bit P60DDR, and bit

ITS8 in ITSR.

10.7.4 Pin Functions 477 • P71/DREQ1/EDREQ1

Description amended

The pin function is switched as shown below according to the

combination of bit P71DDR and bit DMACS in PFCR2.

477 • P70/DREQ0/EDREQ0

Description amended

The pin function is switched as shown below according to the

combination of bit P70DDR and bit DMACS in PFCR2.

10.9.5 Port A Open

Drain Control Register

(PAODR)

486 Note deleted from bit table

10.9.6 Port Function

Control Register 1

(PFCR1)

486 Note * added

Note: * Only in H8S/2678R Group.

Rev. 3.00 Mar 17, 2006 page ix of l

Item Page Revision (See Manual for Details)

10.15.4 Pin

Functions 515 • PG3/CS3/RAS3/CAS, PG2/CS2/RAS2/RAS

Description amended

The pin function is switched as shown below according to the

operating mode, bit EXPE, bit PGnDDR, bit CSnE, and bits

RMTS2 to RMTS0.

515 • PG1/CS1, PG0/CS0

Description amended

The pin function is switched as shown below according to the

operating mode, bit EXPE, bit PGnDDR, and bit CSnE.

10.16.4 Pin

Functions 520 • PH1/CS5/RAS5/SDRAMφ

Description amended

The pin function is switched as shown below according to the

operating mode, DCTL pin, bit EXPE, bit CS5E, bi ts RMTS2

to RMTS0, and bit PH1DDR.

11.1 Features

Table 11.1 TPU

Functions

523 Table 11.1 amended

Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5

DTC

activation TGR

compare

match or

input capture

TGR

compare

match or

input capture

TGR

compare

match or

input capture

TGR

compare

match or

input capture

TGR

compare

match or

input capture

TGR

compare

match or

input capture

DMAC

activation TGRA_0

compare

match or

input capture

TGRA_1

compare

match or

input capture

TGRA_2

compare

match or

input capture

TGRA_3

compare

match or

input capture

TGRA_4

compare

match or

input capture

TGRA_5

compare

match or

input capture

A/D

converter

trigger

TGRA_0

compare

match or

input capture

TGRA_1

compare

match or

input capture

TGRA_2

compare

match or

input capture

TGRA_3

compare

match or

input capture

TGRA_4

compare

match or

input capture

TGRA_5

compare

match or

input capture

PPG

trigger TGRA_0/

TGRB_0

compare

match or

input capture

TGRA_1/

TGRB_1

compare

match or

input capture

TGRA_2/

TGRB_2

compare

match or

input capture

TGRA_3/

TGRB_3

compare

match or

input capture

——

11.3.9 Timer

Synchronous Register

(TSYR)

558 Bits 7, 6 initial value am ended

(Before) - → (After) All 0

15.3.9 Bit Rate

Generator (BRR)

Table 15.2

Relationships

between N Setting in

BRR and Bit Rate B

679 Table 15.2 amended

Mod e Bit Ra te Error

Smart Card

Interface Mode

B =

Error (%) =

B × S × 2

× (N + 1)

φ × 10

{}

– 1 × 100

S × 2

× (N + 1)

φ × 10

Rev. 3.00 Mar 17, 2006 page x of l

Item Page Revision (See Manual for Details)

17.4 Operation 769 Description added

[2] Set the DAOE0 bit ... The output value is expressed by the

following formula:

256

DADR contents × Vref

19.12 Usage Notes

Figure 19.12 Power-

On/Off Timing

(H8S/2678Group)

804 Figure 19.12 amended

VCC

FWE

tOSC1 Min 0 µs

Min 0 µs

tMDS*3

MD2 to MD0*1

RES

SWE bit SWE set SWE cleared

Programming/

erasing

possible

Wait time: x Wait time: 100 µs

SWE set SWE cleared

VCC

FWE

tOSC1 Min 0 µs

MD2 to MD0*1

RES

SWE bit

(2) User Program Mode

(1) Boot Mode

Programming/

erasing

possible

Wait time: x Wait time: 100 µs

tMDS*3

Section 20 Masked

ROM 810 Description amended

The operating mode enables or disables the on-chip ROM.

The operating mode is selected by the mode setting pins,

such as the FWE and MD2 to MD0 pins shown in table 3.1. ...

Rev. 3.00 Mar 17, 2006 page xi of l

Item Page Revision (See Manual for Details)

21.2.1 Connecting a

Crystal Resonator 814 Description amended

... shown in table 21.2. When a crystal resonator is used, the

range of its frequencies is from 8 to 25 MHz.

21.2.2 External Clock

Input 815 Description amended

... for the external clock. When an external clock is used, the

range of its frequencies is from 8 to 25 MHz.

24.6 Flash Memory

Characteristics

Table 24.13 Flash

Memory

Characteristics

907,

908 Table 24.13 amended and notes *7, *8, *9 adde d

Item Symbol Min Typ Max Unit Test

Conditions

Programming time*

—10 200 ms/

128 bytes

Erase time*

—50 1000 ms/

128 bytes

Reprogramming count N

WEC

100*

10,000*

—Times

Data retention time*

DRP

10 — — Years

Programming Wait time after SWE bit setting*

x1——µs

Notes: 7. Minimu m number of times for which all

characteristics are guaranteed after rewriting (Guarantee

range is 1 to minimum value).

8. Reference value for 25°C (as a guideline, rewriting should

normally function up to this value).

9. Data retention characteristic when rewriting is performed

within the specification range, including the minimum value.

C. Package

Dimensions

Figure C.1 Package

Dimensions

(FP-144H)

919 Figure C.1 replaced

Figure C.2 Package

Dimensions

(FP-144G)

920 Figure C.2 replaced

Rev. 3.00 Mar 17, 2006 page xii of l

Rev. 3.00 Mar 17, 2006 page xiii of l

Contents

Section 1 Overview............................................................................................................. 1

1.1 Features............................................................................................................................. 1

1.2 Block Diagram.................................................................................................................. 3

1.3 Pin Description.................................................................................................................. 5

1.3.1 Pin Arrangement.................................................................................................. 5

1.3.2 Pin Arrangement in Each Operating Mode.......................................................... 7

1.3.3 Pin Functions ....................................................................................................... 13

Section 2 CPU...................................................................................................................... 21

2.1 Features............................................................................................................................. 21

2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU.................................. 22

2.1.2 Differences from H8/300 CPU ............................................................................ 22

2.1.3 Differences from H8/300H CPU.......................................................................... 23

2.2 CPU Operating Modes...................................................................................................... 24

2.2.1 Normal Mode....................................................................................................... 24

2.2.2 Advanced Mode................................................................................................... 26

2.3 Address Space................................................................................................................... 28

2.4 Registers............................................................................................................................ 29

2.4.1 General Registers................................................................................................. 30

2.4.2 Program Counter (PC) ......................................................................................... 31

2.4.3 Extended Register (EXR) .................................................................................... 31

2.4.4 Condition-Code Reg ister (CCR).......................................................................... 32

2.4.5 Multiply-Accumulate Register (MAC)................................................................ 33

2.4.6 Initial Values of CPU Internal Registers.............................................................. 33

2.5 Data Formats..................................................................................................................... 34

2.5.1 General Register Data Formats............................................................................ 34

2.5.2 Memory Data Formats......................................................................................... 36

2.6 Instruction Set................................................................................................................... 37

2.6.1 Table of Instructions Classified by Function....................................................... 38

2.6.2 Basic Instruction Formats .................................................................................... 47

2.7 Addressing Modes and Effective Address Calculation..................................................... 48

2.7.1 Register Direct—Rn ............................................................................................. 49

2.7.2 Register Indirect—@ERn.................................................................................... 49

2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn).............. 49

2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn.. 50

2.7.5 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32.................................... 50

2.7.6 Immediate—#xx:8, #xx:16, or #xx:32................................................................. 51

2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC).................................... 51

Rev. 3.00 Mar 17, 2006 page xiv of l

2.7.8 Memory Indirect—@@aa:8 ................................................................................ 51

2.7.9 Effective Address Calculation ............................................................................. 53

2.8 Processing States............................................................................................................... 55

2.9 Usage Note........................................................................................................................ 56

2.9.1 Usage Notes on Bit-wise Operation Instructions................................................. 56

Section 3 MCU Operating Modes .................................................................................. 57

3.1 Operating Mode Selection ................................................................................................ 57

3.2 Register Descriptions........................................................................................................58

3.2.1 Mode Control Register (MDCR) ......................................................................... 59

3.2.2 System Control Register (SYSCR)...................................................................... 59

3.3 Operating Mode Descriptions........................................................................................... 61

3.3.1 Mode 1................................................................................................................. 61

3.3.2 Mode 2................................................................................................................. 61

3.3.3 Mode 3................................................................................................................. 61

3.3.4 Mode 4................................................................................................................. 61

3.3.5 Mode 5................................................................................................................. 62

3.3.6 Mode 6................................................................................................................. 62

3.3.7 Mode 7................................................................................................................. 62

3.3.8 Mode 10............................................................................................................... 63

3.3.9 Mode 11............................................................................................................... 63

3.3.10 Mode 12............................................................................................................... 63

3.3.11 Mode 13............................................................................................................... 63

3.3.12 Mode 14............................................................................................................... 63

3.3.13 Mode 15............................................................................................................... 63

3.3.14 Pin Functions ....................................................................................................... 63

3.4 Memory Map in Each Operating Mode ............................................................................ 65

Section 4 Exception Handling ......................................................................................... 75

4.1 Exception Handling Types and Priority............................................................................ 75

4.2 Exception Sources and Exception Vector Table............................................................... 75

4.3 Reset.................................................................................................................................. 77

4.3.1 Reset exception handling..................................................................................... 77

4.3.2 Interrupts after Reset............................................................................................ 79

4.3.3 On-Chip Peripheral Functions after Reset Release.............................................. 79

4.4 Traces................................................................................................................................ 80

4.5 Interrupts........................................................................................................................... 80

4.6 Trap Instruction............................................................................................................ ..... 81

4.7 Stack Status after Exception Handling.............................................................................. 82

4.8 Usage Note........................................................................................................................ 83

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Section 5 Interrupt Controller.......................................................................................... 85

5.1 Features............................................................................................................................. 85

5.2 Input/Output Pins.............................................................................................................. 87

5.3 Register Descriptions........................................................................................................87

5.3.1 Interrupt Control Register (INTCR)..................................................................... 88

5.3.2 Interrupt Priority Registers A to K (IPRA to IPRK)............................................ 88

5.3.3 IRQ Enable Register (IER).................................................................................. 91

5.3.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 92

5.3.5 IRQ Status Register (ISR).................................................................................... 98

5.3.6 IRQ Pin Select Register (ITSR)........................................................................... 98

5.3.7 Software Standby Release IRQ Enable Register (SSIER)................................... 100

5.4 Interrupt Sources............................................................................................................... 101

5.4.1 External Interrupts ............................................................................................... 101

5.4.2 Internal Interrupts................................................................................................. 102

5.5 Interrupt Exception Handling Vector Table...................................................................... 102

5.6 Interrupt Control Modes and Interrupt Operation............................................................. 107

5.6.1 Interrupt Control Mode 0..................................................................................... 108

5.6.2 Interrupt Control Mode 2..................................................................................... 110

5.6.3 Interrupt Exception Handling Sequence .............................................................. 112

5.6.4 Interrupt Response Times.................................................................................... 114

5.6.5 DTC and DMAC Activation by Interrupt............................................................ 115

5.7 Usage Notes...................................................................................................................... 117

5.7.1 Contention between Interrupt Generation and Disabling..................................... 117

5.7.2 Instructions that Disable Interrupts...................................................................... 118

5.7.3 Times when Interrupts are Disabled .................................................................... 118

5.7.4 Interrupts during Execution of EEPMOV Instruction.......................................... 119

5.7.5 Change of IRQ Pin Select Register (ITSR) Setting ............................................. 119

5.7.6 Note on IRQ Status Register (ISR)...................................................................... 119

Section 6 Bus Controller (BSC)...................................................................................... 121

6.1 Features............................................................................................................................. 121

6.2 Input/Output Pins.............................................................................................................. 123

6.3 Register Descriptions........................................................................................................ 125

6.3.1 Bus Width Control Register (ABWCR)............................................................... 126

6.3.2 Access State Control Register (ASTCR) ............................................................. 126

6.3.3 Wait Control Registers AH, AL, BH, and BL

(WTCRAH, WTCRAL, WTCRBH, and WTCRBL)........................................... 127

6.3.4 Read Strobe Timing Control Register (RDNCR) ................................................ 132

6.3.5 CS Assertion Period Control Registers H, L (CSACRH, CSACRL)................... 133

6.3.6 Area 0 Burst ROM Interface Control Register (BROMCRH)

Area 1 Burst ROM Interface Control Register (BROMCRL).............................. 135

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6.3.7 Bus Control Register (BCR)................................................................................ 136

6.3.8 DRAM Control Register (DRAMCR)................................................................. 138

6.3.9 DRAM Access Control Register (DRACCR)...................................................... 144

6.3.10 Refresh Control Register (REFCR) ..................................................................... 149

6.3.11 Refresh Timer Counter (RTCNT)........................................................................ 152

6.3.12 Refresh Time Constant Register (RTCOR) ......................................................... 152

6.4 Bus Control....................................................................................................................... 152

6.4.1 Area Division....................................................................................................... 152

6.4.2 Bus Specifications................................................................................................ 154

6.4.3 Memory Interfaces............................................................................................... 156

6.4.4 Chip Select Signals .............................................................................................. 157

6.5 Basic Bus Interface ........................................................................................................... 158

6.5.1 Data Size and Data Alignment............................................................................. 158

6.5.2 Valid Strobes ........................................................................................................ 160

6.5.3 Basic Operation Timing....................................................................................... 160

6.5.4 Wait Control ........................................................................................................ 169

6.5.5 Read Strobe (RD) Timing.................................................................................... 170

6.5.6 Extension of Chip Select (CS) Assertion Period.................................................. 171

6.6 DRAM Interface ............................................................................................................... 173

6.6.1 Setting DRAM Space........................................................................................... 173

6.6.2 Address Multiplexing........................................................................................... 173

6.6.3 Data Bus............................................................................................................... 174

6.6.4 Pins Used for DRAM Interface............................................................................ 175

6.6.5 Basic Timing........................................................................................................ 176

6.6.6 Column Address Output Cycle Control............................................................... 177

6.6.7 Row Address Output State Control...................................................................... 178

6.6.8 Precharge State Control ....................................................................................... 180

6.6.9 Wait Control ........................................................................................................ 181

6.6.10 Byte Access Control ............................................................................................ 184

6.6.11 Burst Operation.................................................................................................... 185

6.6.12 Refresh Control.................................................................................................... 190

6.6.13 DMAC and EXDMAC Single Address Transfer Mode and DRAM Interface.... 195

6.7 Synchronous DRAM Interface.......................................................................................... 198

6.7.1 Setting Continuous Synchronous DRAM Space.................................................. 198

6.7.2 Address Multiplexing........................................................................................... 199

6.7.3 Data Bus............................................................................................................... 200

6.7.4 Pins Used for Synchronous DRAM Interface...................................................... 200

6.7.5 Synchronous DRAM Clock................................................................................. 202

6.7.6 Basic Operation Timing....................................................................................... 202

6.7.7 CAS Latency Control........................................................................................... 204

6.7.8 Row Address Output State Control...................................................................... 206

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6.7.9 Precharge State Count.......................................................................................... 208

6.7.10 Bus Cycle Control in Write Cycle ....................................................................... 210

6.7.11 Byte Access Control ............................................................................................ 211

6.7.12 Burst Operation.................................................................................................... 214

6.7.13 Refresh Control.................................................................................................... 217

6.7.14 Mode Register Setting of Synchronous DRAM................................................... 223

6.7.15 DMAC and EXDMAC Single Address Transfer Mode and Synchronous

DRAM Interface .................................................................................................. 224

6.8 Burst ROM Interface......................................................................................................... 229

6.8.1 Basic Timing........................................................................................................ 229

6.8.2 Wait Control ........................................................................................................ 231

6.8.3 Write Access........................................................................................................ 231

6.9 Idle Cycle.......................................................................................................................... 232

6.9.1 Operation ............................................................................................................. 232

6.9.2 Pin States in Idle Cycle........................................................................................ 249

6.10 Write Data Buffer Function .............................................................................................. 249

6.11 Bus Release....................................................................................................................... 250

6.11.1 Operation ............................................................................................................. 251

6.11.2 Pin States in External Bu s Released State............................................................ 252

6.11.3 Transition Timing................................................................................................ 253

6.12 Bus Arbitration.................................................................................................................. 255

6.12.1 Operation ............................................................................................................. 255

6.12.2 Bus Transfer Timing............................................................................................ 255

6.13 Bus Controller Operation in Reset.................................................................................... 257

6.14 Usage Notes...................................................................................................................... 257

6.14.1 External Bus Release Function and All-Module-Clocks-Stopped Mode............. 257

6.14.2 External Bus Release Function and Software Standby........................................ 257

6.14.3 External Bus Release Functio n and CBR Refreshing/Auto Refresh in g............... 25 8

6.14.4 BREQO Output Timing....................................................................................... 258

6.14.5 Notes on Usage of the Synchronous DRAM ....................................................... 258

Section 7 DMA Controller (DMAC)............................................................................. 259

7.1 Features............................................................................................................................. 259

7.2 Input/Output Pins.............................................................................................................. 261

7.3 Register Descriptions........................................................................................................ 261

7.3.1 Memory Address Registers (MARA and MARB)............................................... 263

7.3.2 I/O Address Registers (IOARA and IOARB)...................................................... 263

7.3.3 Execute Transfer Count Registers (ETCRA and ETCRB) .................................. 264

7.3.4 DMA Control Registers (DMACRA and DMACRB)......................................... 265

7.3.5 DMA Band Control Registers H and L (DMABCRH an d DMABCRL)............. 272

7.3.6 DMA Write Enable Register (DMAWER).......................................................... 283

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7.3.7 DMA Terminal Control Register (DMATCR)..................................................... 285

7.4 Activation Sources............................................................................................................ 286

7.4.1 Activation by Internal Interrupt Request.............................................................. 287

7.4.2 Activation by External Request ........................................................................... 287

7.4.3 Activation by Auto-Request................................................................................. 288

7.5 Operation .......................................................................................................................... 288

7.5.1 Transfer Modes.................................................................................................... 288

7.5.2 Sequential Mode .................................................................................................. 290

7.5.3 Idle Mode............................................................................................................. 292

7.5.4 Repeat Mode........................................................................................................ 295

7.5.5 Single Address Mode........................................................................................... 298

7.5.6 Normal Mode....................................................................................................... 301

7.5.7 Block Transfer Mode........................................................................................... 304

7.5.8 Basic Bus Cycles.................................................................................................. 309

7.5.9 DMA Bus Cycles (Dual Address Mode) ............................................................. 310

7.5.10 DMA Bus Cycles (Single Address Mode)........................................................... 318

7.5.11 Write Data Buffer Function................................................................................. 324

7.5.12 Multi-Channel Operation..................................................................................... 325

7.5.13 Relation between DMAC and External Bus Requests, Refresh Cycles,

and EXDMAC ..................................................................................................... 326

7.5.14 DMAC and NMI Interrupts.................................................................................. 327

7.5.15 Forced Termination of DMAC Operation............................................................ 327

7.5.16 Clearing Full Address Mode................................................................................ 328

7.6 Interrupt Sources............................................................................................................... 329

7.7 Usage Notes...................................................................................................................... 330

7.7.1 DMAC Register Access during Operation ........................................................... 330

7.7.2 Module Stop......................................................................................................... 331

7.7.3 Write Data Buffer Function ................................................................................. 331

7.7.4 TEND Output....................................................................................................... 332

7.7.5 Activation by Falling Edge on DREQ Pin........................................................... 333

7.7.6 Activation Source Acceptance............................................................................. 334

7.7.7 Internal Interrupt after End of Transfer................................................................ 334

7.7.8 Channel Re-Setting.............................................................................................. 334

Section 8 EXDMA Controller ......................................................................................... 335

8.1 Features............................................................................................................................. 335

8.2 Input/Output Pins.............................................................................................................. 337

8.3 Register Descriptions........................................................................................................ 338

8.3.1 EXDMA Source Address Register (EDSAR)...................................................... 338

8.3.2 EXDMA Destination Address Register (EDDAR).............................................. 339

8.3.3 EXDMA Transfer Count Register (EDTCR)....................................................... 339

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8.3.4 EXDMA Mode Control Register (EDMDR)....................................................... 341

8.3.5 EXDMA Address Control Register (EDACR).................................................... 346

8.4 Operation .......................................................................................................................... 350

8.4.1 Transfer Modes.................................................................................................... 350

8.4.2 Address Modes .................................................................................................... 351

8.4.3 DMA Transfer Requests...................................................................................... 355

8.4.4 Bus Modes ........................................................................................................... 355

8.4.5 Transfer Modes.................................................................................................... 357

8.4.6 Repeat Area Function .......................................................................................... 359

8.4.7 Registers during DMA Transfer Operation.......................................................... 361

8.4.8 Channel Priority Order......................................................................................... 366

8.4.9 EXDMAC Bus Cycles (Dual Address Mode)...................................................... 369

8.4.10 EXDMAC Bus Cycles (Single Address Mode)................................................... 376

8.4.11 Examples of Oper ation Timing in Each Mode .................................................... 380

8.4.12 Ending DMA Transfer......................................................................................... 393

8.4.13 Relationship between EXDMAC and Other Bus Masters ................................... 394

8.5 Interrupt Sources............................................................................................................... 395

8.6 Usage Notes...................................................................................................................... 398

8.6.1 EXDMAC Register Access during Operation ..................................................... 398

8.6.2 Module Stop State................................................................................................ 398

8.6.3 EDREQ Pin Falling Edge Activation................................................................... 398

8.6.4 Activation Source Acceptance............................................................................. 399

8.6.5 Enabling Interrupt Requests when IRF = 1 in EDMDR ...................................... 399

8.6.6 ETEND Pin and CBR Refresh Cycle................................................................... 399

Section 9 Data Transfer Controller (DTC)................................................................... 401

9.1 Features............................................................................................................................. 401

9.2 Register Descriptions........................................................................................................ 402

9.2.1 DTC Mode Register A (MRA) ............................................................................ 403

9.2.2 DTC Mode Register B (MRB)............................................................................. 404

9.2.3 DTC Source Address Register (SAR).................................................................. 405

9.2.4 DTC Destination Address Register (DAR).......................................................... 405

9.2.5 DTC Transfer Count Register A (CRA) .............................................................. 405

9.2.6 DTC Transfer Count Register B (CRB)............................................................... 405

9.2.7 DTC Enable Registers A to G (DTCERA to DTCERG) ..................................... 405

9.2.8 DTC Vector Register (DTVECR)........................................................................ 406

9.3 Activation Sources............................................................................................................ 407

9.4 Location of Register Information and DTC Vector Table ................................................ 408

9.5 Operation .......................................................................................................................... 410

9.5.1 Normal Mode....................................................................................................... 412

9.5.2 Repeat Mode........................................................................................................ 413

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9.5.3 Block Transfer Mode........................................................................................... 414

9.5.4 Chain Transfer ..................................................................................................... 415

9.5.5 Interrupt Sources.................................................................................................. 416

9.5.6 Operation Timing................................................................................................. 417

9.5.7 Number of DTC Execution States........................................................................ 418

9.6 Procedures for Using DTC................................................................................................ 420

9.6.1 Activation by Interrupt......................................................................................... 420

9.6.2 Activation by Software ........................................................................................ 420

9.7 Examples of Use of the DTC............................................................................................ 421

9.7.1 Normal Mode....................................................................................................... 421

9.7.2 Chain Transfer ..................................................................................................... 422

9.7.3 Chain Transfer when Counter = 0........................................................................ 423

9.7.4 Software Activation ............................................................................................. 425

9.8 Usage Notes...................................................................................................................... 426

9.8.1 Module Stop Mode Setting.................................................................................. 426

9.8.2 On-Chip RAM ..................................................................................................... 426

9.8.3 DTCE Bit Setting................................................................................................. 426

Section 10 I/O Ports............................................................................................................ 427

10.1 Port 1................................................................................................................................. 432

10.1.1 Port 1 Data Direction Register (P1DDR)............................................................. 432

10.1.2 Port 1 Data Register (P1DR)................................................................................ 433

10.1.3 Port 1 Register (PORT1)...................................................................................... 433

10.1.4 Pin Functions....................................................................................................... 434

10.2 Port 2................................................................................................................................. 443

10.2.1 Port 2 Data Direction Register (P2DDR)............................................................. 443

10.2.2 Port 2 Data Register (P2DR)................................................................................ 444

10.2.3 Port 2 Register (PORT2)...................................................................................... 444

10.2.4 Pin Functions....................................................................................................... 445

10.3 Port 3................................................................................................................................. 454

10.3.1 Port 3 Data Direction Register (P3DDR)............................................................. 454

10.3.2 Port 3 Data Register (P3DR)................................................................................ 455

10.3.3 Port 3 Register (PORT3)...................................................................................... 455

10.3.4 Port 3 Open Drain Control Register (P3ODR)..................................................... 456

10.3.5 Port Function Control Register 2 (PFCR2).......................................................... 457

10.3.6 Pin Functions....................................................................................................... 458

10.4 Port 4................................................................................................................................. 461

10.4.1 Port 4 Register (PORT4)...................................................................................... 461

10.4.2 Pin Functions....................................................................................................... 461

10.5 Port 5................................................................................................................................. 462

10.5.1 Port 5 Data Direction Register (P5DDR)............................................................. 463

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10.5.2 Port 5 Data Register (P5DR)................................................................................ 463

10.5.3 Port 5 Register (PORT5)...................................................................................... 464

10.5.4 Pin Functions....................................................................................................... 464

10.6 Port 6................................................................................................................................. 467

10.6.1 Port 6 Data Direction Register (P6DDR)............................................................. 467

10.6.2 Port 6 Data Register (P6DR)................................................................................ 468

10.6.3 Port 6 Register (PORT6)...................................................................................... 468

10.6.4 Pin Functions....................................................................................................... 469

10.7 Port 7................................................................................................................................. 472

10.7.1 Port 7 Data Direction Register (P7DDR)............................................................. 472

10.7.2 Port 7 Data Register (P7DR)................................................................................ 473

10.7.3 Port 7 Register (PORT7)...................................................................................... 473

10.7.4 Pin Functions....................................................................................................... 474

10.8 Port 8................................................................................................................................. 478

10.8.1 Port 8 Data Direction Register (P8DDR)............................................................. 478

10.8.2 Port 8 Data Register (P8DR)................................................................................ 479

10.8.3 Port 8 Register (PORT8)...................................................................................... 479

10.8.4 Pin Functions....................................................................................................... 480

10.9 Port A..................................................................................................................... ........... 483

10.9.1 Port A Data Direction Register (PADDR)........................................................... 484

10.9.2 Port A Data Register (PADR).............................................................................. 485

10.9.3 Port A Register (PORTA).................................................................................... 485

10.9.4 Port A Pull-Up MOS Control Register (PAPCR)................................................ 486

10.9.5 Port A Open Drain Control Register (PAODR)................................................... 486

10.9.6 Port Function Control Register 1 (PFCR1).......................................................... 486

10.9.7 Pin Functions....................................................................................................... 488

10.9.8 Port A Input Pull-Up MOS States........................................................................ 489

10.10 Port B................................................................................................................................ 489

10.10.1 Port B Data Direction Register (PBDDR)............................................................ 490

10.10.2 Port B Data Register (PBDR) .............................................................................. 490

10.10.3 Port B Register (PORTB) .................................................................................... 491

10.10.4 Port B Pull-Up MOS Control Register (PBPCR)................................................. 491

10.10.5 Pin Functions....................................................................................................... 492

10.10.6 Port B Input Pull-Up MOS States........................................................................ 492

10.11 Port C................................................................................................................................ 493

10.11.1 Port C Data Direction Register (PCDDR)............................................................ 493

10.11.2 Port C Data Register (PCDR) .............................................................................. 494

10.11.3 Port C Register (PORTC) .................................................................................... 494

10.11.4 Port C Pull-Up MOS Control Register (PCPCR)................................................. 495

10.11.5 Pin Functions....................................................................................................... 495

10.11.6 Port C Input Pull-Up MOS States........................................................................ 496

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10.12 Port D................................................................................................................................ 496

10.12.1 Port D Data Direction Register (PDDDR)........................................................... 497

10.12.2 Port D Data Register (PDDR).............................................................................. 497

10.12.3 Port D Register (PORTD).................................................................................... 498

10.12.4 Port D Pull-up Control Register (PDPCR)........................................................... 498

10.12.5 Pin Functions....................................................................................................... 499

10.12.6 Port D Input Pull-Up MOS States........................................................................ 499

10.13 Port E ................................................................................................................................ 500

10.13.1 Port E Data Direction Register (PEDDR)............................................................ 500

10.13.2 Port E Data Register (PEDR)............................................................................... 501

10.13.3 Port E Register (PORTE)..................................................................................... 501

10.13.4 Port E Pull-up Control Register (PEPCR)............................................................ 502

10.13.5 Pin Functions....................................................................................................... 502

10.13.6 Port E Input Pull-Up MOS States ........................................................................ 503

10.14 Port F................................................................................................................................. 503

10.14.1 Port F Data Direction Register (PFDDR) ............................................................ 504

10.14.2 Port F Data Register (PFDR)............................................................................... 505

10.14.3 Port F Register (PORTF)..................................................................................... 506

10.14.4 Pin Functions....................................................................................................... 506

10.15 Port G................................................................................................................................ 510

10.15.1 Port G Data Direction Register (PGDDR)........................................................... 510

10.15.2 Port G Data Register (PGDR).............................................................................. 512

10.15.3 Port G Register (PORTG).................................................................................... 512

10.15.4 Port Function Control Register 0 (PFCR0).......................................................... 513

10.15.5 Pin Functions....................................................................................................... 513

10.16 Port H................................................................................................................................ 516

10.16.1 Port H Data Direction Register (PHDDR)........................................................... 517

10.16.2 Port H Data Register (PHDR).............................................................................. 518

10.16.3 Port H Register (PORTH).................................................................................... 518

10.16.4 Pin Functions....................................................................................................... 519

Section 11 16-Bit Timer Pulse Unit (TPU).................................................................. 521

11.1 Features............................................................................................................................. 521

11.2 Input/Output Pins.............................................................................................................. 525

11.3 Register Descriptions........................................................................................................ 526

11.3.1 Timer Control Register (TCR)............................................................................. 528

11.3.2 Timer Mode Register (TMDR)............................................................................ 533

11.3.3 Timer I/O Control Register (TIOR)..................................................................... 534

11.3.4 Timer Interrupt Enable Register (TIER).............................................................. 552

11.3.5 Timer Status Register (TSR)................................................................................ 554

11.3.6 Timer Counter (TCNT)........................................................................................ 557

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11.3.7 Timer General Register (TGR)............................................................................ 557

11.3.8 Timer Start Register (TSTR)................................................................................ 557

11.3.9 Timer Synchronous Register (TSYR).................................................................. 558

11.4 Operation .......................................................................................................................... 559

11.4.1 Basic Functions.................................................................................................... 559

11.4.2 Synchronous Operation........................................................................................ 564

11.4.3 Buffer Operation.................................................................................................. 566

11.4.4 Cascaded Operation............................................................................................. 570

11.4.5 PWM Modes........................................................................................................ 572

11.4.6 Phase Counting Mode.......................................................................................... 577

11.5 Interrupt Sources............................................................................................................... 583

11.6 DTC Activation................................................................................................................. 585

11.7 DMAC Activation............................................................................................................. 585

11.8 A/D Converter Activation................................................................................................. 585

11.9 Operation Timing.............................................................................................................. 586

11.9.1 Input/Output Timing............................................................................................ 586

11.9.2 Interrupt Signal Timing........................................................................................ 590

11.10 Usage Notes...................................................................................................................... 594

11.10.1 Module Stop Mode Setting.............................................................................. 594

11.10.2 Input Clock Restrictions................................................................................... 594

11.10.3 Caution on Cycle Setting ................................................................................. 595

11.10.4 Contention between TCNT Write and Clear Operations................................. 595

11.10.5 Contention between TCNT Write and Increment Operations.......................... 596

11.10.6 Contention between TGR Write and Compare Match..................................... 597

11.10.7 Contention between Buffer Register Write and Compare Match .................... 598

11.10.8 Contention between TGR Read and Input Capture.......................................... 599

11.10.9 Contention between TGR Write and Input Capture......................................... 600

11.10.10 Contention between Buffer Register Write and Input Capture........................ 601

11.10.11 Contention between Overflow/Underflow and Counter Clearing.................... 602

11.10.12 Contention between TCNT Write and Overflow/Underflow........................... 603

11.10.13 Multiplexing of I/O Pins .................................................................................. 603

11.10.14 Interrupts and Module Stop Mode ................................................................... 603

Section 12 Programmable Pulse Generator (PPG) .................................................... 605

12.1 Features............................................................................................................................. 605

12.2 Input/Output Pins.............................................................................................................. 607

12.3 Register Descriptions........................................................................................................ 607

12.3.1 Next Data Enable Registers H, L (NDERH, NDERL)......................................... 608

12.3.2 Output Data Registers H, L (PODRH, PODRL).................................................. 609

12.3.3 Next Data Registers H, L (NDRH, NDRL) ......................................................... 610

12.3.4 PPG Output Control Register (PCR).................................................................... 612

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12.3.5 PPG Output Mode Register (PMR)...................................................................... 613

12.4 Operation .......................................................................................................................... 615

12.4.1 Output Timing...................................................................................................... 616

12.4.2 Sample Setup Procedure for Normal Pulse Output.............................................. 617

12.4.3 Example of Normal Pulse Output (Example of Five-Phase Pulse Output).......... 618

12.4.4 Non-Overlapping Pulse Output............................................................................ 619

12.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output.............................. 621

12.4.6 Example of Non-Ov erlapping Pulse Output

(Example of Four-Phase Complementary Non-Overlapping Output).................. 622

12.4.7 Inverted Pulse Output .......................................................................................... 624

12.4.8 Pulse Output Triggered by Input Capture............................................................ 625

12.5 Usage Notes...................................................................................................................... 625

12.5.1 Module Stop Mode Setting.................................................................................. 625

12.5.2 Operation of Pulse Output Pins............................................................................ 625

Section 13 8-Bit Timers (TMR)...................................................................................... 627

13.1 Features............................................................................................................................. 627

13.2 Input/Output Pins.............................................................................................................. 629

13.3 Register Descriptions........................................................................................................ 629

13.3.1 Timer Counter (TCNT)........................................................................................ 630

13.3.2 Time Constant Register A (TCORA)................................................................... 630

13.3.3 Time Constant Register B (TCORB)................................................................... 630

13.3.4 Timer Control Register (TCR)............................................................................. 631

13.3.5 Timer Control/Status Register (TCSR)................................................................ 633

13.4 Operation .......................................................................................................................... 636

13.4.1 Pulse Output......................................................................................................... 636

13.5 Operation Timing.............................................................................................................. 637

13.5.1 TCNT Incrementation Timing ............................................................................. 637

13.5.2 Timing of CMFA and CMFB Setting when Compare-Match Occurs................. 638

13.5.3 Timing of Timer Output when Compare-Match Occurs...................................... 639

13.5.4 Timing of Compare Match Clear......................................................................... 639

13.5.5 Timing of TCNT External Reset.......................................................................... 640

13.5.6 Timing of Overflow Flag (OVF) Setting............................................................. 640

13.6 Operation with Cascaded Connection............................................................................... 641

13.6.1 16-Bit Counter Mode........................................................................................... 641

13.6.2 Compare Match Count Mode............................................................................... 641

13.7 Interrupts........................................................................................................................... 642

13.7.1 Interrupt Sources and DTC Activation ................................................................ 642

13.7.2 A/D Converter Activation.................................................................................... 642

13.8 Usage Notes...................................................................................................................... 643

13.8.1 Contention between TCNT Write and Clear........................................................ 643

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13.8.2 Contention between TCNT Write and Increment................................................ 644

13.8.3 Contention between TCOR Write and Compare Match ...................................... 645

13.8.4 Contention between Compare Matches A and B................................................. 646

13.8.5 Switching of Internal Clocks and TCNT Operation............................................. 646

13.8.6 Mode Setting with Cascaded Connection............................................................ 648

13.8.7 Interrupts in Module Stop Mode.......................................................................... 648

Section 14 Watchdog Timer............................................................................................. 649

14.1 Features............................................................................................................................. 649

14.2 Input/Output Pin................................................................................................................ 650

14.3 Register Descriptions........................................................................................................ 650

14.3.1 Timer Counter (TCNT)........................................................................................ 651

14.3.2 Timer Control/Status Register (TCSR)................................................................ 651

14.3.3 Reset Control/Status Register (RSTCSR)............................................................ 653

14.4 Operation .......................................................................................................................... 654

14.4.1 Watchdog Timer Mode........................................................................................ 654

14.4.2 Interval Timer Mode............................................................................................ 655

14.5 Interrupt Source ................................................................................................................ 656

14.6 Usage Notes...................................................................................................................... 656

14.6.1 Notes on Register Access..................................................................................... 656

14.6.2 Contention between Timer Counter (TCNT) Write and Increment..................... 658

14.6.3 Changing Value of CKS2 to CKS0...................................................................... 658

14.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode................ 658

14.6.5 Internal Reset in Watchdog Timer Mode............................................................. 659

14.6.6 System Reset by WDTOVF Signal...................................................................... 659

Section 15 Serial Communication Interface (SCI, IrDA)........................................ 661

15.1 Features............................................................................................................................. 661

15.2 Input/Output Pins.............................................................................................................. 664

15.3 Register Descriptions........................................................................................................ 664

15.3.1 Receive Shift Register (RSR) .............................................................................. 665

15.3.2 Receive Data Register (RDR).............................................................................. 665

15.3.3 Transmit Data Register (TDR)............................................................................. 666

15.3.4 Transmit Shift Register (TSR)............................................................................. 666

15.3.5 Serial Mode Register (SMR)................................................................................ 666

15.3.6 Serial Control Register (SCR).............................................................................. 670

15.3.7 Serial Status Register (SSR) ................................................................................ 673

15.3.8 Smart Card Mode Register (SCMR).................................................................... 678

15.3.9 Bit Rate Register (BRR) ...................................................................................... 679

15.3.10 IrDA Control Register (IrCR).............................................................................. 688

15.3.11 Serial Extension Mode Register (SEMR)............................................................ 689

Rev. 3.00 Mar 17, 2006 page xxvi of l

15.4 Operation in Asynchronous Mode.................................................................................... 691

15.4.1 Data Transfer Format........................................................................................... 691

15.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode 693

15.4.3 Clock.................................................................................................................... 694

15.4.4 SCI Initialization (Asynchronous Mode)............................................................. 695

15.4.5 Data Transmission (Asynchronous Mode)........................................................... 696

15.4.6 Serial Data Reception (Asynchronous Mode)...................................................... 698

15.5 Multiprocessor Communication Function......................................................................... 702

15.5.1 Multiprocessor Serial Data Transmission............................................................ 703

15.5.2 Multiprocessor Serial Data Reception ................................................................. 705

15.6 Operation in Clocked Synchronous Mode........................................................................ 709

15.6.1 Clock.................................................................................................................... 709

15.6.2 SCI Initialization (Clocked Synchronous Mode)................................................. 710

15.6.3 Serial Data Transmission (Clocked Synchronous Mode) .................................... 711

15.6.4 Serial Data Reception (Clocked Synchronous Mode).......................................... 714

15.6.5 Simultaneous Serial Data Transmission and Reception

(Clocked Synchronous Mode) ............................................................................. 716

15.7 Operation in Smart Card Interface Mode.......................................................................... 718

15.7.1 Pin Connection Example...................................................................................... 718

15.7.2 Data Format (Except for Block Transfer Mode).................................................. 719

15.7.3 Block Transfer Mode........................................................................................... 720

15.7.4 Receive Data Sampling Timing and Reception Margin ....................................... 720

15.7.5 Initialization......................................................................................................... 722

15.7.6 Data Transmission (Except for Block Transfer Mode)........................................ 723

15.7.7 Serial Data Reception (Except for Block Transfer Mode)................................... 726

15.7.8 Clock Output Control........................................................................................... 727

15.8 IrDA Operation................................................................................................................. 729

15.9 Interrupt Sources............................................................................................................... 733

15.9.1 Interrupts in Normal Serial Communication Interface Mode .............................. 733

15.9.2 Interrupts in Smart Card Interface Mode............................................................. 734

15.10 Usage Notes...................................................................................................................... 735

15.10.1 Module Stop Mode Setting.................................................................................. 735

15.10.2 Break Detection and Processing .......................................................................... 735

15.10.3 Mark State and Break Sending............................................................................. 736

15.10.4 Receive Error Flags and Transmit Operations

(Clocked Synchronous Mode Only) .................................................................... 736

15.10.5 Relation between Writes to TDR and the TDRE Flag......................................... 736

15.10.6 Restrictions on Use of DMAC or DTC................................................................ 736

15.10.7 Operation in Case of Mode Transition................................................................. 737

Rev. 3.00 Mar 17, 2006 page xxvii of l

Section 16 A/D Converter................................................................................................. 741

16.1 Features............................................................................................................................. 741

16.2 Input/Output Pins.............................................................................................................. 743

16.3 Register Descriptions........................................................................................................ 744

16.3.1 A/D Data Registers A to H (ADDRA to ADDRH).............................................. 744

16.3.2 A/D Control/Status Register (ADCSR) ............................................................... 746

16.3.3 A/D Control Register (ADCR) ............................................................................ 750

16.4 Operation .......................................................................................................................... 752

16.4.1 Single Mode......................................................................................................... 752

16.4.2 Scan Mode........................................................................................................... 752

16.4.3 Input Sampling and A/D Conversion Time ......................................................... 753

16.4.4 External Trigger Input Timing............................................................................. 756

16.5 Interrupt Source ................................................................................................................ 756

16.6 A/D Conversion Accuracy Definitions ............................................................................. 757

16.7 Usage Notes...................................................................................................................... 759

16.7.1 Module Stop Mode Setting.................................................................................. 759

16.7.2 Permissible Signal Source Impedance................................................................. 759

16.7.3 Influences on Absolute Precision ......................................................................... 760

16.7.4 Setting Range of Analog Power Supply and Other Pins...................................... 760

16.7.5 Notes on Board Design........................................................................................ 760

16.7.6 Notes on Noise Countermeasures........................................................................ 761

Section 17 D/A Converter................................................................................................. 763

17.1 Features............................................................................................................................. 763

17.2 Input/Output Pins.............................................................................................................. 765

17.3 Register Descriptions........................................................................................................ 765

17.3.1 D/A Data Registers 0 to 3 (DADR0 to DADR3)................................................. 765

17.3.2 D/A Control Registers 01 and 23 (DACR01, DACR23) ..................................... 766

17.4 Operation .......................................................................................................................... 769

17.5 Usage Notes...................................................................................................................... 770

17.5.1 Setting for Module Stop Mode............................................................................. 770

17.5.2 D/A Output Hold Function in Software Standby Mode....................................... 770

Section 18 RAM .................................................................................................................. 771

Section 19 Flash Memory (F-ZTAT Version)............................................................ 773

19.1 Features............................................................................................................................. 773

19.2 Mode Transitions.............................................................................................................. 774

19.3 Block Configuration.......................................................................................................... 778

19.4 Input/Output Pins.............................................................................................................. 781

19.5 Register Descriptions........................................................................................................ 781

Rev. 3.00 Mar 17, 2006 page xxviii of l

19.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 781

19.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 783

19.5.3 Erase Block Register 1 (EBR1) ........................................................................... 784

19.5.4 Erase Block Register 2 (EBR2) ........................................................................... 785

19.5.5 RAM Emulation Register (RAMER)................................................................... 786

19.6 On-Board Programming Modes........................................................................................ 788

19.6.1 Boot Mode........................................................................................................... 789

19.6.2 User Program Mode............................................................................................. 792

19.7 Flash Memory Emulation in RAM ................................................................................... 793

19.8 Flash Memory Programming/Erasing............................................................................... 795

19.8.1 Program/Program-Verify..................................................................................... 796

19.8.2 Erase/Erase-Verify............................................................................................... 798

19.8.3 Interrupt Handling when Programming/Erasing Flash Memory .......................... 798

19.9 Program/Erase Protection ................................................................................................. 800

19.9.1 Hardware Protection............................................................................................ 800

19.9.2 Software Protection.............................................................................................. 800

19.9.3 Error Protection.................................................................................................... 800

19.10 Programmer Mode............................................................................................................ 801

19.11 Power-Down States for Flash Memory............................................................................. 801

19.12 Usage Notes...................................................................................................................... 802

19.13 Note on Switching from F-ZTAT Version to Masked ROM Version .............................. 807

Section 20 Masked ROM.................................................................................................. 809

Section 21 Clock Pulse Generator.................................................................................. 811

21.1 Register Descriptions........................................................................................................ 811

21.1.1 System Clock Control Register (SCKCR)........................................................... 812

21.1.2 PLL Control Register (PLLCR)........................................................................... 813

21.2 Oscillator........................................................................................................................... 814

21.2.1 Connecting a Crystal Resonator........................................................................... 814

21.2.2 External Clock Input............................................................................................ 815

21.3 PLL Circuit ....................................................................................................................... 816

21.4 Frequency Divider ............................................................................................................ 817

21.5 Usage Notes...................................................................................................................... 817

21.5.1 Notes on Clock Pulse Generator.......................................................................... 817

21.5.2 Notes on Resonator.............................................................................................. 817

21.5.3 Notes on Board Design........................................................................................ 818

Section 22 Power-Down Modes...................................................................................... 819

22.1 Register Descriptions........................................................................................................ 822

22.1.1 Standby Control Register (SBYCR) .................................................................... 822

Rev. 3.00 Mar 17, 2006 page xxix of l

22.1.2 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL).................... 824

22.2 Operation .......................................................................................................................... 825

22.2.1 Clock Division Mode........................................................................................... 825

22.2.2 Sleep Mode.......................................................................................................... 826

22.2.3 Software Standby Mode....................................................................................... 826

22.2.4 Hardware Standby Mode ..................................................................................... 829

22.2.5 Module Stop Mode .............................................................................................. 830

22.2.6 All-Module-Clocks-Stop Mode ........................................................................... 831

22.3 φ Clock Output Control..................................................................................................... 831

22.4 Usage Notes...................................................................................................................... 832

22.4.1 I/O Port Status...................................................................................................... 832

22.4.2 Current Dissipation during Oscillation Stabilization Standby Period.................. 832

22.4.3 EXDMAC/DMAC/DTC Module Stop ................................................................ 832

22.4.4 On-Chip Peripheral Module Interrupts................................................................ 832

22.4.5 Writing to MSTPCR............................................................................................ 832

Section 23 List of Registers.............................................................................................. 833

23.1 Register Addresses

(by functional module, in order of the corresponding section numbers)........................... 833

23.2 Register Bits...................................................................................................................... 844

23.3 Register States in Each Operating Mode........................................................................... 856

Section 24 Electrical Characteristics.............................................................................. 865

24.1 Absolute Maximum Ratings ............................................................................................. 865

24.2 DC Characteristics ............................................................................................................ 866

24.3 AC Characteristics ............................................................................................................ 870

24.4 A/D Conversion Characteristics........................................................................................ 906

24.5 D/A Conversion Characteristics........................................................................................ 906

24.6 Flash Memory Characteristics........................................................................................... 907

24.7 Usage Note................................................................................................................. ....... 908

Appendix.................................................................................................................................. 909

A. I/O Port States in Each Pin State....................................................................................... 909

B. Product Lineup.................................................................................................................. 918

C. Package Dimensions......................................................................................................... 919

Index.......................................................................................................................................... 921

Rev. 3.00 Mar 17, 2006 page xxx of l

Figures

Section 1 Overview

Figure 1.1 H8S/2678 Group Internal Block Diagram ........................................................... 3

Figure 1.2 H8S/2678R Group Internal Block Diagram ......................................................... 4

Figure 1.3 H8S/2678 Group Pin Arrangement...................................................................... 5

Figure 1.4 H8S/2678R Group Pin Arrangement................................................................... 6

Section 2 CPU

Figure 2.1 Exception Vector Table (Normal Mode) ............................................................. 25

Figure 2.2 Stack Structure in Normal Mode ......................................................................... 25

Figure 2.3 Exception Vector Table (Advanced Mode) ......................................................... 26

Figure 2.4 Stack Structure in Advanced Mode ..................................................................... 27

Figure 2.5 Memory Map ....................................................................................................... 28

Figure 2.6 CPU Registers...................................................................................................... 29

Figure 2.7 Usage of General Registers.................................................................................. 30

Figure 2.8 Stack .................................................................................................................... 31

Figure 2.9 General Register Data Formats (1) ...................................................................... 34

Figure 2.9 General Register Data Formats (2) ...................................................................... 35

Figure 2.10 Memory Data Formats......................................................................................... 36

Figure 2.11 Instruction Formats (Examples)........................................................................... 48

Figure 2.12 Branch Address Specification in Memory Indirect Mode.................................... 52

Figure 2.13 State Transitions................................................................................................... 56

Section 3 MCU Opera t ing Modes

Figure 3.1 H8S/2676 Memory Map (1)................................................................................. 65

Figure 3.1 H8S/2676 Memory Map (2)................................................................................. 66

Figure 3.1 H8S/2676 Memory Map (3)................................................................................. 67

Figure 3.1 H8S/2676 Memory Map (4)................................................................................. 68

Figure 3.2 H8S/2675 Memory Map (1)................................................................................. 69

Figure 3.2 H8S/2675 Memory Map (2)................................................................................. 70

Figure 3.3 H8S/2673 Memory Map (1)................................................................................. 71

Figure 3.3 H8S/2673 Memory Map (2)................................................................................. 72

Figure 3.4 H8S/2670 Memory Map ...................................................................................... 73

Figure 3.5 H8S/2674R Memory Map.................................................................................... 74

Section 4 Exception Handling

Figure 4.1 Reset Sequence (Advanced Mode with On-Chip ROM Enabled) ....................... 78

Figure 4.2 Reset Sequence (Advanced Mode with On-Chip ROM Disabled)...................... 79

Figure 4.3 Stack Status after Exception Handling................................................................. 82

Rev. 3.00 Mar 17, 2006 page xxxi of l

Figure 4.4 Operation when SP Value Is Odd........................................................................ 83

Section 5 Interrupt Controller

Figure 5.1 Block Diagram of Interrupt Controller ................................................................ 86

Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0 ...................................................... 102

Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt

Control Mode 0.................................................................................................... 109

Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt

Control Mode 2.................................................................................................... 111

Figure 5.5 Interrupt Exception Handling............................................................................... 113

Figure 5.6 DTC, DMAC, and Interrupt Controller................................................................ 116

Figure 5.7 Contention between Interrupt Generation and Disabling..................................... 118

Section 6 Bus Controller (BSC)

Figure 6.1 Block Diagram of Bus Controller........................................................................ 122

Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space)..................... 132

Figure 6.3 CS and Address Assertion Period Extension

(Example of 3-State Access Space and RDNn = 0)............................................. 134

Figure 6.4 RAS Signal Assertion Timing

(2-State Column Address Output Cycle, Full Access)......................................... 144

Figure 6.5 CAS Latency Control Cycle Disable Timing during Continuous Synchronous

DRAM Space Write Access (for CAS Latency 2)............................................... 148

Figure 6.6 Area Divisions ..................................................................................................... 153

Figure 6.7 CSn Signal Output Timing (n = 0 to 7)................................................................ 158

Figure 6.8 Access Sizes and Data Alignment Control (8-Bit Access Space)........................ 159

Figure 6.9 Access Sizes and Data Alignment Control (16-bit Access Space)....................... 159

Figure 6.10 Bus Timing for 8-Bit, 2-State Access Space........................................................ 161

Figure 6.11 Bus Timing for 8-Bit, 3-State Access Space........................................................ 162

Figure 6.12 Bus Timing for 16-Bit, 2-State Access Space (Even Address Byte Access)....... 163

Figure 6.13 Bus Timing for 16-Bit, 2-State Access Space (Odd Address By te Access)......... 164

Figure 6.14 Bus Timing for 16-Bit, 2-State Access Space (Word Access)............................. 165

Figure 6.15 Bus Timing for 16-Bit, 3-State Access Space (Even Address Byte Access)....... 166

Figure 6.16 Bus Timing for 16-Bit, 3-State Access Space (Odd Address By te Access)......... 167

Figure 6.17 Bus Timing for 16-Bit, 3-State Access Space (Word Access)............................. 168

Figure 6.18 Example of Wait State Insertion Timing ............................................................. 170

Figure 6.19 Example of Read Strobe Timing.......................................................................... 171

Figure 6.20 Example of Timing when Chip Select Assertion Period Is Extended.................. 172

Figure 6.21 DRAM Basic Access Timing (RAST = 0, CAST = 0) ........................................ 176

Figure 6.22 Example of Access Timing with 3-State Column Address Output Cycle

(RAST = 0) .......................................................................................................... 177

Rev. 3.00 Mar 17, 2006 page xxxii of l

Figure 6.23 Example of Access Timing when RAS Signal Goes Low from Beginning

of Tr State (CAST = 0)......................................................................................... 178

Figure 6.24 Example of Timing with One Row Address Output Maintenance State

(RAST = 0, CAST = 0)........................................................................................ 179

Figure 6.25 Example of Timing with Two-State Precharge Cycle (RAST = 0, CAST = 0)... 180

Figure 6.26 Example of Wait State Insertion Timing (2-State Column Address Output)....... 182

Figure 6.27 Example of Wait State Insertion Timing (3-State Column Address Output)....... 183

Figure 6.28 2-CAS Control Timing (Upper Byte Write Access: RAST = 0, CAST = 0) ....... 184

Figure 6.29 Example of 2-CAS DRAM Connection............................................................... 185

Figure 6.30 Operation Timing in Fast Page Mode (RAST = 0, CAST = 0)............................ 186

Figure 6.31 Operation Timing in Fast Page Mode (RAST = 0, CAST = 1)............................ 187

Figure 6.32 Example of Operation Timing in RAS Down Mode (RAST = 0, CAST = 0)..... 188

Figure 6.33 Example of Operation Timing in RAS Up Mode (RAST = 0, CAST = 0).......... 189

Figure 6.34 RTCNT Operation ............................................................................................... 190

Figure 6.35 Compare Match Timing....................................................................................... 191

Figure 6.36 CBR Refresh Timing ........................................................................................... 191

Figure 6.37 CBR Refresh Timing (RCW1 = 0, RCW0 = 1, RLW1 = 0, RLW0 = 0) ............. 192

Figure 6.38 Example of CBR Refresh Timin g (CBRM = 1 )................................................... 193

Figure 6.39 Self-Refresh Timing............................................................................................. 194

Figure 6.40 Example of Timing when Precharge Time after Self-Refresh ing Is Extended

by 2 States............................................................................................................ 195

Figure 6.41 Example of DACK/EDACK Output Timing when DDS = 1 or EDDS = 1

(RAST = 0, CAST = 0)........................................................................................ 196

Figure 6.42 Example of DACK/EDACK Output Timing when DDS = 0 or EDDS = 0

(RAST = 0, CAST = 1)........................................................................................ 197

Figure 6.43 Relationship between φ and SDRAMφ

(when PLL fr equency multiplication factor is ×1 or ×2) ..................................... 202

Figure 6.44 Basic Access Timing of Synchronous DRAM (CAS Latency 1)......................... 203

Figure 6.45 CAS Latency Control Timing (SDWCD = 0, CAS Latency 3) ........................... 205

Figure 6.46 Example of Access Timing when Row Address Output Hold State Is 1 State

(RCD1 = 0, RCD0 = 1, SDWCD = 0, CAS Latency 2)....................................... 207

Figure 6.47 Example of Timing with Two-State Precharge Cycle

(TPC1 = 0, TPC0 = 1, SDWCD = 0, CAS Latency 2)......................................... 209

Figure 6.48 Example of Write Access Timing when CAS Latency Control Cycle Is

Disabled (SDWCD = 1)....................................................................................... 210

Figure 6.49 DQMU and DQML Control Timing

(Upper Byte Write Access: SDWCD = 0, CAS Latency 2)................................. 211

Figure 6.50 DQMU and DQML Control Timing

(Lower Byte Read Access: CAS Latency 2)........................................................ 212

Figure 6.51 Example of DQMU and DQML Byte Control..................................................... 213

Figure 6.52 Operation Timing of Burst Access (BE = 1, SDWCD = 0, CAS Latency 2)....... 215

Rev. 3.00 Mar 17, 2006 page xxxiii of l

Figure 6.53 Example of Operation Timing in RAS Down Mode (BE = 1, CAS Latency 2).. 217

Figure 6.54 Auto Refresh Timing ........................................................................................... 218

Figure 6.55 Auto Refresh Timing (TPC = 1, TPC0 = 1, RCW1 = 0, RCW0 = 1) .................. 219

Figure 6.56 Auto Refresh Timing (TPC = 0, TPC0 = 0, RLW1 = 0, RLW0 = 1)................... 220

Figure 6.57 Self-Refresh Timing (TPC1 = 1, TPC0 = 0, RCW1 = 0, RCW0 = 0,

RLW1 = 0, RLW0 = 0)........................................................................................ 221

Figure 6.58 Example of Timing when Precharge Time after Self-Refreshing Is Extended

by 2 States (TPCS2 to TPCS0 = H'2, TPC1 = 0, TPC0 = 0, CAS Latency 2)..... 222

Figure 6.59 Synchronous DRAM Mode Setting Timing ........................................................ 223

Figure 6.60 Example of DACK/EDACK Output Timing when DDS = 1 or EDDS = 1......... 225

Figure 6.61 Example of DACK/EDACK Output Timing when DDS = 0 or EDDS = 0......... 227

Figure 6.62 Example of Timing when the Read Data Is Extended by Two States

(DDS = 1, or EDDS = 1, RDXC1 = 0, RDXC0 = 1, CAS Latency 2)................. 228

Figure 6.63 Example of Burst ROM Access Timing (ASTn = 1, 2-State Burst Cycle).......... 230

Figure 6.64 Example of Burst ROM Access Timing (ASTn = 0, 1-State Burst Cycle).......... 231

Figure 6.65 Example of Idle Cycle Operation (Consecutive Reads in Different Areas)......... 232

Figure 6.66 Example of Idle Cycle Operation (Write after Read) .......................................... 233

Figure 6.67 Example of Idle Cycle Operation (Read after Write) .......................................... 234

Figure 6.68 Relationship between Ch ip Select (CS) and Read (RD)...................................... 235

Figure 6.69 Example of DRAM Full Access after External Read (CAST = 0)....................... 235

Figure 6.70 Example of Idle Cycle Operation in RAS Down Mode

(Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0)....... 236

Figure 6.71 Example of Idle Cycle Operation in RAS Down Mode (Write after Read)

(IDLC = 0, RAST = 0, CAST = 0) ...................................................................... 236

Figure 6.72 Example of Synchronous DRAM Full Access after External Read

(CAS Latency 2).................................................................................................. 237

Figure 6.73 Example of Idle Cycle Operation in RAS Down Mode (Read in Different Area)

(IDLC = 0, CAS Latency 2)................................................................................. 238

Figure 6.74 Example of Idle Cycle Operation in RAS Down Mode (Read in Different Area)

(IDLC = 1, CAS Latency 2)................................................................................. 239

Figure 6.75 Example of Idle Cycle Operation in RAS Down Mode

(Write after Read) (IDLC = 0, CAS Latency 2)................................................... 240

Figure 6.76 Example of Idle Cycle Operation after DRAM Access

(Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0)....... 241

Figure 6.77 Example of Idle Cycle Operation after DRAM Access

(Write after Read) (IDLC = 0, RAST = 0, CAST = 0) ........................................ 242

Figure 6.78 Example of Idle Cycle Operation after DRAM Write Access

(IDLC = 0, ICIS1 = 0, RAST = 0, CAST = 0)..................................................... 243

Figure 6.79 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space

Read Access (Read between Different Area) (IDLC = 0, CAS Latency 2)......... 244

Rev. 3.00 Mar 17, 2006 page xxxiv of l

Figure 6.80 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space

Write Access (IDLC = 0, ICIS1 = 0, SDWCD = 1, CAS Latency 2).................. 245

Figure 6.81 Example of Timing for Idle Cy cle Insertion in Case of Consecutive Read

and Write Accesses to DRAM Space in RAS Down Mode................................. 247

Figure 6.82 Example of Timing for Idle Cy cle Insertion in Case of Consecutive Read

and Write Accesses to Continuous Synchronous DRAM Space in RAS Down

Mode (SDWCD = 1, CAS Latency 2) ................................................................. 248

Figure 6.83 Example of Timing when Write Data Buffer Function is Used........................... 250

Figure 6.84 Bus Released State Transition Timing................................................................. 253

Figure 6.85 Bus Release State Transition Timing when Synchronous DRAM Interface........ 254

Section 7 DMA Controller (DMAC)

Figure 7.1 Block Diagram of DMAC.................................................................................... 260

Figure 7.2 Areas for Register Re-Setting by DTC (Channel 0A).......................................... 284

Figure 7.3 Operation in Sequential Mode ............................................................................. 291

Figure 7.4 Example of Sequential Mode Setting Procedure.................................................. 292

Figure 7.5 Operation in Idle Mode........................................................................................ 293

Figure 7.6 Example of Idle Mode Setting Procedure............................................................ 294

Figure 7.7 Operation in Repeat mode ................................................................................... 296

Figure 7.8 Example of Repeat Mode Setting Procedure....................................................... 297

Figure 7.9 Operation in Single Address Mode (When Sequential Mode Is Specified)......... 299

Figure 7.10 Example of Single Address Mode Setting Procedure

(When Sequential Mode Is Specified) ................................................................. 300

Figure 7.11 Operation in Normal Mode.................................................................................. 302

Figure 7.12 Example of Normal Mode Setting Procedure...................................................... 303

Figure 7.13 Operation in Block Transfer Mode (BLKDIR = 0).............................................. 305

Figure 7.14 Operation in Block Transfer Mode (BLKDIR = 1).............................................. 306

Figure 7.15 Operation Flow in Block Transfer Mode............................................................. 307

Figure 7.16 Example of Block Transfer Mode Setting Procedure .......................................... 308

Figure 7.17 Example of DMA Transfer Bus Timing.............................................................. 309

Figure 7.18 Example of Short Address Mode Transfer........................................................... 310

Figure 7.19 Example of Full Address Mode Transfer (Cycle Steal)....................................... 311

Figure 7.20 Example of Full Address Mode Transfer (Burst Mode) ...................................... 312

Figure 7.21 Example of Full Address Mode Transfer (Block Transfer Mode)....................... 313

Figure 7.22 Example of DREQ Pin Falling Edge Activated Norm al Mode Transfer............. 314

Figure 7.23 Example of DREQ Pin Falling Edge Activated Block Transfer Mode Transfer 315

Figure 7.24 Example of DREQ Pin Low Level Activated Normal Mode Transfer ................ 316

Figure 7.25 Example of DREQ Pin Low Level Activated Block Transfer Mode Transfer .... 317

Figure 7.26 Example of Single Address Mode Transfer (Byte Read)..................................... 318

Figure 7.27 Example of Single Address Mode (Word Read) Transfer................................... 319

Figure 7.28 Example of Single Address Mode Transfer (Byte Write).................................... 320

Rev. 3.00 Mar 17, 2006 page xxxv of l

Figure 7.29 Example of Single Address Mode Transfer (Word Write) .................................. 321

Figure 7.30 Example of DREQ Pin Falling Edge Activated Single Address Mode Transfer 322

Figure 7.31 Example of DREQ Pin Low Level Activated Single Address Mode Tran sfer .... 323

Figure 7.32 Example of Dual Address Transfer Using Write Data Buffer Function.............. 324

Figure 7.33 Example of Single Address Transfer Using Write Data Buffer Function............ 325

Figure 7.34 Example of Multi-Channel Transfer.................................................................... 326

Figure 7.35 Example of Procedure for Continuing Transfer on Channel Interrupted

by NMI Interrupt.................................................................................................. 327

Figure 7.36 Example of Procedure for Forcibly Terminating DMAC Operation ................... 328

Figure 7.37 Example of Procedure for Clearing Full Address Mode...................................... 328

Figure 7.38 Block Diagram of Transfer End/Transfer Break Interrupt................................... 329

Figure 7.39 DMAC Register Update Timing.......................................................................... 330

Figure 7.40 Contention between DMAC Register Update and CPU Read............................. 331

Figure 7.41 Example in Which Low Level Is Not Output at TEND Pin................................. 333

Section 8 EXDMA Controller

Figure 8.1 Block Diagram of EXDMAC .............................................................................. 336

Figure 8.2 Example of Timing in Dual Address Mode......................................................... 352

Figure 8.3 Data Flow in Single Address Mode..................................................................... 353

Figure 8.4 Example of Timing in Single Address Mode....................................................... 354

Figure 8.5 Example of Timing in Cycle Steal Mode............................................................. 356

Figure 8.6 Examples of Timing in Burst Mode..................................................................... 357

Figure 8.7 Examples of Timing in Normal Transfer Mode................................................... 358

Figure 8.8 Example of Timing in Block Transfer Mode....................................................... 359

Figure 8.9 Example of Repeat Area Function Operation...................................................... 360

Figure 8.10 Example of Repeat Area Function Operation in Block Transfer Mode............... 361

Figure 8.11 EDTCR Update Operations in Normal Transfer Mode

and Block Transfer Mode .................................................................................... 364

Figure 8.12 Procedure for Changing Register Settings in Operating Channel........................ 365

Figure 8.13 Example of Channel Priority Timing................................................................... 367

Figure 8.14 Examples of Channel Priority Timing................................................................. 368

Figure 8.15 Example of Normal Transfer Mode (Cycle Steal Mode) Transfer....................... 369

Figure 8.16 Example of Normal Transfer Mode (Burst Mode) Transfer................................ 370

Figure 8.17 Example of Block Transfer Mode (Cycle Steal Mode) Transfer......................... 371

Figure 8.18 Example of Normal Mode Transfer Activated by EDREQ Pin Falling Edge...... 372

Figure 8.19 Example of Block Transfer Mode Transfer Activated by EDREQ Pin

Falling Edge......................................................................................................... 373

Figure 8.20 Example of Normal Mode Transfer Activated by EDREQ Pin Low Level......... 374

Figure 8.21 Example of Block Transfer Mode Transfer Activated by EDREQ Pin

Low Level............................................................................................................ 375

Figure 8.22 Example of Single Address Mode (Byte Read) Transfer..................................... 376

Rev. 3.00 Mar 17, 2006 page xxxvi of l

Figure 8.23 Example of Single Address Mode (Word Read) Transfer................................... 376

Figure 8.24 Example of Single Address Mode (Byte Write) Transfer.................................... 377

Figure 8.25 Example of Single Address Mode (Word Write) Transfer .................................. 377

Figure 8.26 Example of Single Address Mode Transfer Activated by EDREQ Pin

Falling Edge......................................................................................................... 378

Figure 8.27 Example of Single Address Mode Transfer Activated by EDREQ Pin

Low Level............................................................................................................ 379

Figure 8.28 Auto Request/Cycle Steal Mode/Normal Transfer Mode

(No Contention/Dual Address Mode).................................................................. 380

Figure 8.29 Auto Request/Cycle Steal Mode/Normal Transfer Mode

(CPU Cycles/Single Address Mode).................................................................... 381

Figure 8.30 Auto Request/Cycle Steal Mode/Normal Transfer Mode

(Contention with Another Channel/Single Address Mode)................................. 381

Figure 8.31 Auto Request/Burst Mode/Normal Transfer Mode

(CPU Cycles/Dual Address Mode/BGUP = 0).................................................... 382

Figure 8.32 Auto Request/Burst Mode/Normal Transfer Mode

(CPU Cycles/Dual Address Mode/BGUP = 1).................................................... 382

Figure 8.33 Auto Request/Burst Mode/Normal Transfer Mode

(CPU Cycles/Single Address Mode/BGUP = 1).................................................. 383

Figure 8.34 Auto Request/Burst Mode/Normal Transfer Mode

(Contention with Another Channel/Single Address Mode)................................. 383

Figure 8.35 External Request/Cycle Steal Mode/Normal Transfer Mode

(No Contention/Dual Address Mode/Low Level Sensing).................................. 384

Figure 8.36 External Request/Cycle Steal Mode/Normal Transfer Mode

(CPU Cycles/Single Address Mode/Low Level Sensing) .................................... 385

Figure 8.37 External Request/Cycle Steal Mode/Normal Transfer Mode

(No Contention/Single Address Mode/Falling Edge Sensing)............................. 385

Figure 8.38 External Request/Cycle Steal Mode/Normal Transfer Mode Contention

with Another Channel/Dual Address Mode/Low Level Sensing......................... 386

Figure 8.39 External Request/Cycle Steal Mode/Block Transfer Mode

(No Contention/Dual Address Mode/Low Level Sensing/BGUP = 0)................ 387

Figure 8.40 External Request/Cycle Steal Mode/Block Transfer Mode

(No Contention/Single Address Mode/Falling Edge Sensing/BGUP = 0) ........... 388

Figure 8.41 External Request/Cycle Steal Mode/Block Transfer Mode

(CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 0).................. 389

Figure 8.42 External Request/Cycle Steal Mode/Block Transfer Mode

(CPU Cycles/Dual Address Mode/Low Level Sensing/BGUP = 1).................... 390

Figure 8.43 External Request/Cycle Steal Mode/Block Transfer Mode

(CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 1).................. 391

Figure 8.44 External Request/Cycle Steal Mode/Block Transfer Mode

(Contention with Another Channel/Dual Address Mode/Low Level Sensing).... 392

Rev. 3.00 Mar 17, 2006 page xxxvii of l

Figure 8.45 Transfer End Interrupt Logic ............................................................................... 395

Figure 8.46 Example of Procedure for Restarting Transfer on Channel in which Transfer

End Interrupt Occurred........................................................................................ 397

Section 9 Data Transfer Controller (DTC)

Figure 9.1 Block Diagram of DTC........................................................................................ 402

Figure 9.2 Block Diagram of DTC Activation Source Control............................................. 407

Figure 9.3 Correspondence between DTC Vector Address and Register Information.......... 408

Figure 9.4 Flowchart of DTC Operation............................................................................... 411

Figure 9.5 Memory Mapping in Normal Mode..................................................................... 413

Figure 9.6 Memory Mapping in Repeat Mode...................................................................... 414

Figure 9.7 Memory Mapping in Block Transfer Mode......................................................... 415

Figure 9.8 Operation of Chain Transfer................................................................................ 416

Figure 9.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode)................ 417

Figure 9.10 DTC Operation Timing (Example of Block Transfer Mode,

with Block Size of 2) ........................................................................................... 417

Figure 9.11 DTC Operation Timing (Example of Chain Transfer)......................................... 418

Figure 9.12 Chain Transfer when Counter = 0........................................................................ 424

Section 11 16-Bit Timer Pulse Unit (TPU)

Figure 11.1 Block Diagram of TPU........................................................................................ 524

Figure 11.2 Example of Counter Operation Setting Procedure............................................... 559

Figure 11.3 Free-Running Counter Operation......................................................................... 560

Figure 11.4 Periodic Counter Operation ................................................................................. 561

Figure 11.5 Example of Setting Procedure for Waveform Output by Co mpare Match .......... 561

Figure 11.6 Example of 0 Output/1 Output Operation............................................................ 562

Figure 11.7 Example of Toggle Output Operation.................................................................. 562

Figure 11.8 Example of Setting Procedure for Input Capture Op eration................................ 563

Figure 11.9 Example of Input Capture Operation................................................................... 564

Figure 11.10 Example of Synchronous Operation Setting Procedure....................................... 565

Figure 11.11 Example of Synchronous Operation.................................................................... 566

Figure 11.12 Compare Match Buffer Operation ....................................................................... 567

Figure 11.13 Input Capture Bu ffer Operation........................................................................... 567

Figure 11.14 Example of Buffer Operation Setting Procedure................................................. 568

Figure 11.15 Example of Buffer Operation (1)......................................................................... 569

Figure 11.16 Example of Buffer Operation (2)......................................................................... 570

Figure 11.17 Cascaded Operation Setting Procedure................................................................ 571

Figure 11.18 Example of Cascaded Operation (1).................................................................... 571

Figure 11.19 Example of Cascaded Operation (2).................................................................... 572

Figure 11.20 Example of PWM Mode Setting Procedure......................................................... 574

Figure 11.21 Example of PWM Mode Operation (1)................................................................ 575

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Figure 11.22 Example of PWM Mode Operation (2)................................................................ 575

Figure 11.23 Example of PWM Mode Operation (3)................................................................ 576

Figure 11.24 Example of Phase Counting Mode Setting Procedure ......................................... 577

Figure 11.25 Example of Phase Counting Mode 1 Operation................................................... 578

Figure 11.26 Example of Phase Counting Mode 2 Operation................................................... 579

Figure 11.27 Example of Phase Counting Mode 3 Operation................................................... 580

Figure 11.28 Example of Phase Counting Mode 4 Operation................................................... 581

Figure 11.29 Phase Counting Mode Application Example....................................................... 582

Figure 11.30 Count Timing in Internal Clock Operation.......................................................... 586

Figure 11.31 Count Timing in External Clock Operation......................................................... 586

Figure 11.32 Output Compare Output Timing.......................................................................... 587

Figure 11.33 Input Capture Input Signal Timing...................................................................... 587

Figure 11.34 Counter Clear Timing (Compare Match)............................................................. 588

Figure 11.35 Counter Clear Timing (Input Capture)................................................................. 588

Figure 11.36 Buffer Operation Timing (Compare Match)........................................................ 589

Figure 11.37 Buffer Operation Timing (Input Capture)............................................................ 589

Figure 11.38 TGI Interrupt Timing (Compare Match).............................................................. 590

Figure 11.39 TGI Interrupt Timing (Input Capture).................................................................. 591

Figure 11.40 TCIV Interrupt Setting Timing............................................................................ 592

Figure 11.41 TCIU Interrupt Setting Timing............................................................................ 592

Figure 11.42 Timing for Status Flag Clearing by CPU............................................................. 593

Figure 11.43 Timing for Status Flag Clearing by DTC/DMAC Activation.............................. 593

Figure 11.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode............... 594

Figure 11.45 Contention between TCNT Write and Clear Operations..................................... 595

Figure 11.46 Contention between TCNT Write and Increment Operations.............................. 596

Figure 11.47 Contention between TGR Write and Compare Match......................................... 597

Figure 11.48 Contention between Buffer Register Write and Compare Match ........................ 598

Figure 11.49 Contention between TGR Read and Input Capture.............................................. 599

Figure 11.50 Contention between TGR Write and Input Capture............................................. 600

Figure 11.51 Contention between Buffer Register Write and Input Capture............................ 601

Figure 11.52 Contention between Overflow and Counter Clearing.......................................... 602

Figure 11.53 Contention between TCNT Write and Overflow................................................. 603

Section 12 Programmable Pulse Generator (PPG)

Figure 12.1 Block Diagram of PPG ........................................................................................ 606

Figure 12.2 Overview Diagram of PPG.................................................................................. 615

Figure 12.3 Timing of Transfer and Output of NDR Contents (Example).............................. 616

Figure 12.4 Setup Procedure for Normal Pulse Output (Example)......................................... 617

Figure 12.5 Normal Pulse Output Example (Five-Phase Pulse Output).................................. 618

Figure 12.6 Non-Overlapping Pulse Output............................................................................ 619

Figure 12.7 Non-Overlapping Operation and NDR Write Timing.......................................... 620

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Figure 12.8 Setup Procedure for Non-Overlapping Pulse Output (Example)......................... 621

Figure 12.9 Non-Overlapping Pulse Output Example (Four-Phase Complementary)............ 622

Figure 12.10 Inverted Pulse Output (Example) ......................................................................... 624

Figure 12.11 Pulse Output Triggered by Input Capture (Example) .......................................... 625

Section 13 8-Bit Timers (TMR)

Figure 13.1 Block Diagram of 8-Bit Timer Module ............................................................... 628

Figure 13.2 Example of Pulse Output..................................................................................... 637

Figure 13.3 Count Timing for Internal Clock Input................................................................ 637

Figure 13.4 Count Timing for External Clock Input............................................................... 638

Figure 13.5 Timing of CMF Setting........................................................................................ 638

Figure 13.6 Timing of Timer Output....................................................................................... 639

Figure 13.7 Timing of Compare Match Clear......................................................................... 639

Figure 13.8 Timing of Clearance by External Reset............................................................... 640

Figure 13.9 Timing of OVF Setting........................................................................................ 640

Figure 13.10 Contention between TCNT Write and Clear........................................................ 643

Figure 13.11 Contention between TCNT Write and Increment................................................ 644

Figure 13.12 Contention between TCOR Write and Compare Match ...................................... 645

Section 14 Watchdog Timer

Figure 14.1 Block Diagram of WDT....................................................................................... 650

Figure 14.2 Operation in Watchdog Timer Mode................................................................... 655

Figure 14.3 Operation in Interval Timer Mode....................................................................... 656

Figure 14.4 Writing to TCNT, TCSR, and RSTCSR............................................................. 657

Figure 14.5 Contention between TCNT Write and Increment................................................ 658

Figure 14.6 Circuit for System Reset by WDTOVF Signal (Example) .................................. 659

Section 15 Serial Communication Interface (SCI, IrDA)

Figure 15.1 Block Diagram of SCI ......................................................................................... 663

Figure 15.2 Data Format in Asynchronous Communication

(Example with 8-Bit Data, Parity, Two Stop Bits) .............................................. 691

Figure 15.3 Receive Data Sampling Timing in Asynchronous Mode..................................... 693

Figure 15.4 Relation between Output Clock and Transfer Data Phase

(Asynchronous Mode) ......................................................................................... 694

Figure 15.5 Sample SCI Initialization Flowchart.................................................................... 695

Figure 15.6 Example of Operation in Transmission in Asynchronous Mode

(Example with 8-Bit Data, Parity, One Stop Bit)................................................. 696

Figure 15.7 Sample Serial Transmission Flowchart................................................................ 697

Figure 15.8 Example of SCI Operation in Reception

(Example with 8-Bit Data, Parity, One Stop Bit)................................................. 698

Figure 15.9 Sample Serial Reception Data Flowchart (1)....................................................... 700

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Figure 15.9 Sample Serial Reception Data Flowchart (2)....................................................... 701

Figure 15.10 Example of Com m unication Using Multiprocessor Form at

(Transmission of Data H'AA to Receiving Station A)......................................... 703

Figure 15.11 Sample Multiprocessor Serial Transmission Flowchart....................................... 704

Figure 15.12 Example of SCI Operation in Reception

(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) ............................ 706

Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (1) ...................................... 707

Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (2) ...................................... 708

Figure 15.14 Data Format in Clocked Synchronous Communication (For LSB-First)............. 709

Figure 15.15 Sample SCI Initialization Flowchart.................................................................... 710

Figure 15.16 Sample SCI Transmission Operation in Clocked Synchronous Mode................. 712

Figure 15.17 Sample Serial Transmission Flowchart................................................................ 713

Figure 15.18 Example of SCI Operation in Reception.............................................................. 714

Figure 15.19 Sample Serial Reception Flowchart..................................................................... 715

Figure 15.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations..... 717

Figure 15.21 Schematic Diagram of Smart Card Interface Pin Connections............................ 718

Figure 15.22 Normal Smart Card Interface Data Format.......................................................... 719

Figure 15.23 Direct Convention (SDIR = SINV = O/E = 0)..................................................... 719

Figure 15.24 Inverse Convention (SDIR = SINV = O/E = 1)................................................... 720

Figure 15.25 Receive Data Sampling Timing in Smart Card Mode

(Using Clock of 372 Times the Bit Rate)............................................................. 721

Figure 15.26 Retransfer Operation in SCI Transmit Mode....................................................... 724

Figure 15.27 TEND Flag Generation Timing in Transmission Operation................................ 724

Figure 15.28 Example of Transmission Processing Flow......................................................... 725

Figure 15.29 Retransfer Operation in SCI Receive Mode......................................................... 726

Figure 15.30 Example of Reception Processing Flow .............................................................. 727

Figure 15.31 Timing for Fixing Clock Output Level................................................................ 728

Figure 15.32 Clock Halt and Restart Procedure........................................................................ 729

Figure 15.33 Block Diagram of IrDA....................................................................................... 730

Figure 15.34 IrDA Transmit/Receive Operations ..................................................................... 731

Figure 15.35 Example of Synchronous Transmission Using DTC ........................................... 737

Figure 15.36 Sample Flowchart for Mode Transition during Transmission ............................. 738

Figure 15 .37 Port Pin States dur ing Mode Transition

(Internal Clock, Asynchronous Transmission)..................................................... 739

Figure 15 .38 Port Pin States dur ing Mode Transition

(Internal Clock, Synchronous Transmission)....................................................... 739

Figure 15.39 Sample Flowchart for Mode Transition during Reception................................... 740

Section 16 A/D Converter

Figure 16.1 Block Diagram of A/D Converter........................................................................ 742

Figure 16.2 A/D Conversion Timing ...................................................................................... 754

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Figure 16.3 External Trigger Input Timing............................................................................. 756

Figure 16.4 A/D Conversion Accuracy Definitions................................................................ 758

Figure 16.5 A/D Conversion Accuracy Definitions................................................................ 758

Figure 16.6 Example of Analog Input Circuit......................................................................... 759

Figure 16.7 Example of Analog Input Protection Circuit ....................................................... 761

Figure 16.8 Analog Input Pin Equivalent Circuit.................................................................... 762

Section 17 D/A Converter

Figure 17.1 Block Diagram of D/A Converter........................................................................ 764

Figure 17.2 Example of D/A Converter Operation ................................................................. 770

Section 19 Flash Memory (F-ZTAT Version)

Figure 19.1 Block Diagram of Flash Memory ....................................................................... 774

Figure 19.2 Flash Memory State Transitions.......................................................................... 775

Figure 19.3 Boot Mode ........................................................................................................... 776

Figure 19.4 User Program Mode............................................................................................. 777

Figure 19.5 384-kbyte Flash Memory Block Configuration (Modes 3, 4, and 7)................... 779

Figure 19.6 256-kbyte Flash Memory Block Configuration (Modes 4, 7, 10 , and 11)........... 780

Figure 19.7 Programming/Erasing Flowchart Example in User Program Mode..................... 793

Figure 19.8 Flowchart for Flash Memory Emulation in RAM................................................ 794

Figure 19.9 Example of RAM Overlap Operation.................................................................. 795

Figure 19.10 Program/Program-Verify Flowchart.................................................................... 797

Figure 19.11 Erase/Erase-Verify Flowchart.............................................................................. 799

Figure 19.12 Power-On/Off Timing (H8S/2678 Group)........................................................... 804

Figure 19.13 Power-On/Off Timing (H8S/2678R Group)........................................................ 805

Figure 19.14 Mode Transition Timing

(Example: Boot Mode → User Mode ↔ User Program Mode) .......................... 806

Section 20 Masked ROM

Figure 20.1 Block Diagram of 256-kbyte Masked ROM (HD6432676) ................................. 809

Figure 20.2 Block Diagram of 128-kbyte Masked ROM (HD6432675)................................. 809

Figure 20.3 Block Diagram of 64-kbyte Masked ROM (HD6432673)................................... 810

Section 21 Clock Pulse Generator

Figure 21.1 Block Diagram of Clock Pulse Generato r............................................................ 811

Figure 21.2 Connection of Crystal Resonator (Example) ....................................................... 814

Figure 21.3 Crystal Resonator Equivalent Circuit................................................................... 814

Figure 21.4 External Clock Input (Examples)......................................................................... 815

Figure 21.5 External Clock Input Timing............................................................................... 816

Figure 21.6 Note on Board Design for Oscillation Circuit...................................................... 818

Figure 21.7 Recommended External Circuitry for PLL Circuit.............................................. 818

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Section 22 Power-Down Modes

Figure 22.1 Mode Transitions................................................................................................. 821

Figure 22.2 Software Standby Mode Application Example.................................................... 829

Figure 22.3 Hardware Standby Mode Timing......................................................................... 830

Section 24 Electrical Characteristics

Figure 24.1 Output Load Circuit............................................................................................. 870

Figure 24.2 System Clock Timing .......................................................................................... 871

Figure 24.3 SDRAMφ Timing ................................................................................................ 872

Figure 24.4 (1) Oscillation Stabilization Timing........................................................................ 872

Figure 24.4 (2) Oscillation Stabilization Timing........................................................................ 873

Figure 24.5 Reset Input Timing .............................................................................................. 874

Figure 24.6 Interrupt Input Timing ......................................................................................... 875

Figure 24.7 Basic Bus Timing: Two-State Access.................................................................. 879

Figure 24.8 Basic Bus Timing: Three-State Access................................................................ 880

Figure 24.9 Basic Bus Timing: Three-State Access, One Wait............................................... 881

Figure 24.10 Basic Bus Timing: Two-State Access (CS Assertion Period Extended) .............. 882

Figure 24.11 Basic Bus Timing: Three-State Access (CS Assertion Period Extended)............ 883

Figure 24.12 Burst ROM Access Timing: One-State Burst Access.......................................... 884

Figure 24.13 Burst ROM Access Timing: Two-State Burst Access ......................................... 885

Figure 24.14 DRAM Access Timing: Two-State Access.......................................................... 886

Figure 24.15 DRAM Access Timing: Two-State Access, One Wait ........................................ 887

Figure 24.16 DRAM Access Timing: Two-State Burst Access................................................ 888

Figure 24.17 DRAM Access Timing: Three-State Access (RAST = 1) .................................... 889

Figure 24.18 DRAM Access Timing: Three-State Access, One Wait ...................................... 890

Figure 24.19 DRAM Access Timing: Three-State Burst Access.............................................. 891

Figure 24.20 CAS-Before-RAS Refresh Timing ...................................................................... 892

Figure 24.21 CAS-Before-RAS Refresh Timing (with Wait Cycle Insertion).......................... 892

Figure 24.22 Self-Refresh Timing (Return from Software Standby Mode: RAST = 0) ........... 893

Figure 24.23 Self-Refresh Timing (Return from Software Standby Mode: RAST = 1) ........... 893

Figure 24.24 External Bus Release Timing............................................................................... 894

Figure 24.25 External Bus Request Output Timing.................................................................. 894

Figure 24.26 Synchronous DRAM Basic Access Timing (CAS Latency 2)............................. 895

Figure 24.27 Synchronous DRAM Self-Refresh Timing.......................................................... 896

Figure 24.28 Read Data: Two-State Expansion (CAS Latency 2)............................................ 897

Figure 24.29 DMAC and EXDMAC Single Address Transfer Timing: Two-State Access ..... 899

Figure 24.30 DMAC and EXDMAC Single Address Transfer Timing: Three-State Access ... 900

Figure 24.31 DMAC and EXDMAC TEND/ETEND Output Timing...................................... 901

Figure 24.32 DMAC and EXDMAC DREQ/EDREQ Input Timing........................................ 901

Figure 24.33 EXDMAC EDRAK Output Timing..................................................................... 901

Figure 24.34 I/O Port Input/Output Timing.............................................................................. 903

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Figure 24.35 PPG Output Timing ............................................................................................. 903

Figure 24.36 TPU Input/Output Timing.................................................................................... 903

Figure 24.37 TPU Clock Input Timing..................................................................................... 904

Figure 24.38 8-Bit Timer Output Timing.................................................................................. 904

Figure 24.39 8-Bit Timer Clock Input Timing.......................................................................... 904

Figure 24.40 8-Bit Timer Reset Input Timing........................................................................... 904

Figure 24.41 WDT Output Timing............................................................................................ 905

Figure 24.42 SCK Clock Input Timing..................................................................................... 905

Figure 24.43 SCI Input/Output Timing: Synchronous Mode.................................................... 905

Figure 24.44 A/D Converter External Trigger Input Timing.................................................... 905

Appendix

Figure C.1 Package Dimensions (FP-144H).......................................................................... 919

Figure C.2 Package Dimensions (FP-144G).......................................................................... 920

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Tables

Section 1 Overview

Table 1.1 Pin Arrangement in Each Operating Mode ............................................................ 7

Table 1.2 Pin Functions..........................................................................................................13

Section 2 CPU

Table 2.1 Instruction Classification........................................................................................ 37

Table 2.2 Operation Notation................................................................................................. 38

Table 2.3 Data Transfer Instructions...................................................................................... 39

Table 2.4 Arithmetic Operations Instructions (1)................................................................... 40

Table 2.4 Arithmetic Operations Instructions (2)................................................................... 41

Table 2.5 Logic Operations Instructions................................................................................ 42

Table 2.6 Shift Instructions.................................................................................................... 42

Table 2.7 Bit Manipulation Instructions (1)........................................................................... 43

Table 2.7 Bit Manipulation Instructions (2)........................................................................... 44

Table 2.8 Branch Instructions ................................................................................................ 45

Table 2.9 System Control Instructions................................................................................... 46

Table 2.10 Block Data Transfer Instructions ........................................................................... 47

Table 2.11 Addressing Modes.................................................................................................. 49

Table 2.12 Absolute Address Access Ranges .......................................................................... 50

Section 3 MCU Opera t ing Modes

Table 3.1 MCU Operating Mode Selection............................................................................ 58

Table 3.2 Pin Functions in Each Operating Mode.................................................................. 64

Section 4 Exception Handling

Table 4.1 Exception Types and Priority................................................................................. 75

Table 4.2 Exception Handling Vector Table.......................................................................... 76

Table 4.3 Status of CCR and EXR after Trace Exception Handling...................................... 80

Table 4.4 Status of CCR and EXR after Trap In struction Exception Handling..................... 81

Section 5 Interrupt Controller

Table 5.1 Pin Configuration................................................................................................... 87

Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities................................ 103

Table 5.3 Interrupt Control Modes......................................................................................... 107

Table 5.4 Interrupt Response Times....................................................................................... 114

Table 5.5 Number of States in Interrupt Handling Routine Execution Statuses..................... 115

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Section 6 Bus Controller (BSC)

Table 6.1 Pin Configuration................................................................................................... 123

Table 6.2 Bus Specifications for Each Area (Basic Bus Interface)........................................ 155

Table 6.3 Data Buses Used and Valid Strobes....................................................................... 160

Table 6.4 Relation between Settings of Bits RMTS2 to RMTS0 and DRAM Space............. 173

Table 6.5 Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing.... 174

Table 6.6 DRAM Interface Pins............................................................................................. 175

Table 6.7 Relation between Settings of Bits RMTS2 to RMTS0 and Synchronous

DRAM Space ......................................................................................................... 198

Table 6.8 Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing.... 199

Table 6.9 Synchronous DRAM Interface Pins....................................................................... 201

Table 6.10 Setting CAS Latency.............................................................................................. 204

Table 6.11 Idle Cycles in Mixed Accesses to Normal Space and DRAM Continuous

Synchronous DRAM Space.................................................................................... 246

Table 6.12 Pin States in Idle Cycle .......................................................................................... 249

Table 6.13 Pin States in Bus Released State ............................................................................ 252

Section 7 DMA Controller (DMAC)

Table 7.1 Pin Configuration................................................................................................... 261

Table 7.2 Short Address Mode and Full Address Mode (Channel 0)..................................... 262

Table 7.3 DMAC Activation Sources .................................................................................... 286

Table 7.4 DMAC Transfer Modes.......................................................................................... 288

Table 7.5 Register Functions in Sequential Mode.................................................................. 290

Table 7.6 Register Functions in Idle Mode............................................................................ 293

Table 7.7 Register Functions in Repeat Mode ....................................................................... 295

Table 7.8 Register Functions in Single Address Mode .......................................................... 298

Table 7.9 Register Functions in Normal Mode...................................................................... 301

Table 7.10 Register Functions in Block Transfer Mode........................................................... 304

Table 7.11 DMAC Channel Priority Order.............................................................................. 325

Table 7.12 Interrupt Sources and Priority Order...................................................................... 329

Section 8 EXDMA Controller

Table 8.1 Pin Configuration................................................................................................... 337

Table 8.2 EXDMAC Transfer Modes.................................................................................... 350

Table 8.3 EXDMAC Channel Priority Order......................................................................... 366

Table 8.4 Interrupt Sources and Priority Order...................................................................... 395

Section 9 Data Transfer Controller (DTC)

Table 9.1 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs................ 409

Table 9.2 Chain Transfer Conditions..................................................................................... 412

Table 9.3 Register Function in Normal Mode........................................................................ 412

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Table 9.4 Register Function in Repeat Mode......................................................................... 413

Table 9.5 Register Function in Block Transfer Mode............................................................ 414

Table 9.6 DTC Execution Status............................................................................................ 418

Table 9.7 Number of States Required for Each Execution Status.......................................... 419

Section 10 I/O Ports

Table 10.1 Port Functions ....................................................................................................... . 428

Table 10.2 Input Pull-Up MOS States (Port A)........................................................................ 489

Table 10.3 Input Pull-Up MOS States (Port B)........................................................................ 492

Table 10.4 Input Pull-Up MOS States (Port C)........................................................................ 496

Table 10.5 Input Pull-Up MOS States (Port D)........................................................................ 499

Table 10.6 Input Pull-Up MOS States (Port E)........................................................................ 503

Section 11 16-Bit Timer Pulse Unit (TPU)

Table 11.1 TPU Functions........................................................................................................ 522

Table 11.2 Pin Configuration................................................................................................... 525

Table 11.3 CCLR2 to CCLR0 (Channels 0 and 3)................................................................... 529

Table 11.4 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5).......................................................... 529

Table 11.5 TPSC2 to TPSC0 (Channel 0)................................................................................ 530

Table 11.6 TPSC2 to TPSC0 (Channel 1)................................................................................ 530

Table 11.7 TPSC2 to TPSC0 (Channel 2)................................................................................ 531

Table 11.8 TPSC2 to TPSC0 (Channel 3)................................................................................ 531

Table 11.9 TPSC2 to TPSC0 (Channel 4)................................................................................ 532

Table 11.10 TPSC2 to TPSC0 (Channel 5)................................................................................ 532

Table 11.11 MD3 to MD0.......................................................................................................... 534

Table 11.12 TIORH_0................................................................................................................ 536

Table 11.13 TIORL_0................................................................................................................ 537

Table 11.14 TIOR_1 .................................................................................................................. 538

Table 11.15 TIOR_2 .................................................................................................................. 539

Table 11.16 TIORH_3................................................................................................................ 540

Table 11.17 TIORL_3................................................................................................................ 541

Table 11.18 TIOR_4 .................................................................................................................. 542

Table 11.19 TIOR_5 .................................................................................................................. 543

Table 11.20 TIORH_0................................................................................................................ 544

Table 11.21 TIORL_0................................................................................................................ 545

Table 11.22 TIOR_1 .................................................................................................................. 546

Table 11.23 TIOR_2 .................................................................................................................. 547

Table 11.24 TIORH_3................................................................................................................ 548

Table 11.25 TIORL_3................................................................................................................ 549

Table 11.26 TIOR_4 .................................................................................................................. 550

Table 11.27 TIOR_5 .................................................................................................................. 551

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Table 11.28 Register Combinations in Buffer Operation........................................................... 567

Table 11.29 Cascaded Combinations......................................................................................... 570

Table 11.30 PWM Output Registers and Output Pins................................................................ 573

Table 11.31 Clock Input Pins in Phase Counting Mode............................................................. 577

Table 11.32 Up/Down-Count Conditions in Phase Counting Mode 1....................................... 578

Table 11.33 Up/Down-Count Conditions in Phase Counting Mode 2....................................... 579

Table 11.34 Up/Down-Count Conditions in Phase Counting Mode 3....................................... 580

Table 11.35 Up/Down-Count Conditions in Phase Counting Mode 4....................................... 581

Table 11.36 TPU Interrupts........................................................................................................ 584

Section 12 Programmable Pulse Generator (PPG)

Table 12.1 Pin Configuration................................................................................................... 607

Section 13 8-Bit Timers (TMR)

Table 13.1 Pin Configuration................................................................................................... 629

Table 13.2 Clock Input to TCNT and Count Condition........................................................... 632

Table 13.3 8-Bit Timer Interrupt Sources ................................................................................ 642

Table 13.4 Timer Output Priorities .......................................................................................... 646

Table 13.5 Switching of Internal Clock and TCNT Operation ................................................ 647

Section 14 Watchdog Timer

Table 14.1 Pin configuration.................................................................................................... 650

Table 14.2 WDT Interrupt Source............................................................................................ 656

Section 15 Serial Communication Interface (SCI, IrDA)

Table 15.1 Pin Configuration................................................................................................... 664

Table 15.2 Relationships between N Setting in BRR and Bit Rate B...................................... 679

Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1)............................. 680

Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2)............................. 681

Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (3)............................. 682

Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (4)............................. 683

Table 15.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)............................ 684

Table 15.5 Maximum Bit Rate with External Clock Input (Asynchr onous Mode).................. 684

Table 15.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)...................... 685

Table 15.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)...... 686

Table 15.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode)

(when n = 0 and S = 372)....................................................................................... 687

Table 15.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)

(when S = 372)....................................................................................................... 687

Table 15.10 Serial Transfer Formats (Asynchronous Mode)..................................................... 692

Table 15.11 SSR Status Flags and Receive Data Handling........................................................ 699

Rev. 3.00 Mar 17, 2006 page xlviii of l

Table 15.12 Settings of Bits IrCKS2 to IrCKS0 ........................................................................ 732

Table 15.13 SCI Interrupt Sources............................................................................................. 734

Table 15.14 SCI Interrupt Sources............................................................................................. 734

Section 16 A/D Converter

Table 16.1 A/D Converter Pins................................................................................................ 743

Table 16.2 Analog Input Channels and Corresponding ADDR Registers................................ 745

Table 16.3 A/D Conversion Time (Single Mode).................................................................... 754

Table 16.4 A/D Conversion Time (Scan Mode)....................................................................... 755

Table 16.5 A/D Converter Interrupt Source............................................................................. 756

Table 16.6 Analog Pin Specifications...................................................................................... 762

Section 17 D/A Converter

Table 17.1 Pin Configuration................................................................................................... 765

Table 17.2 Control of D/A Conversion.................................................................................... 767

Table 17.3 Control of D/A Conversion.................................................................................... 769

Section 19 Flash Memory (F-ZTAT Version)

Table 19.1 Differences between Boot Mode and User Program Mode.................................... 775

Table 19.2 Pin Configuration................................................................................................... 781

Table 19.3 Erase Blocks........................................................................................................... 786

Table 19.4 Setting On-Board Programming Modes................................................................. 788

Table 19.5 Boot Mode Operation............................................................................................. 791

Table 19.6 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate

Is Possible............................................................................................................... 792

Table 19.7 Flash Memory Operating States............................................................................. 801

Section 21 Clock Pulse Generator

Table 21.1 Damping Resistance Value .................................................................................... 814

Table 21.2 Crystal Resonator Characteristics........................................................................... 815

Table 21.3 External Clock Input Conditions............................................................................ 816

Section 22 Power-Down Modes

Table 22.1 Operating Modes.................................................................................................... 820

Table 22.2 Oscillation Stabilizat ion Time Settings.................................................................. 828

Table 22.3 φ Pin State in Each Processing State ...................................................................... 831

Section 24 Electrical Characteristics

Table 24.1 Absolute Maximum Ratings................................................................................... 865

Table 24.2 DC Characteristics.................................................................................................. 866

Table 24.3 DC Characteristics.................................................................................................. 868

Rev. 3.00 Mar 17, 2006 page xlix of l

Table 24.4 Permissible Output Currents .................................................................................. 869

Table 24.5 Clock Timing ......................................................................................................... 871

Table 24.6 Control Signal Timing............................................................................................ 874

Table 24.7 Bus Timing............................................................................................................. 876

Table 24.8 Bus Timing............................................................................................................. 877

Table 24.9 DMAC and EXDMAC Timing.............................................................................. 898

Table 24.10 Timing of On-Chip Peripheral Modules................................................................. 902

Table 24.11 A/D Conversion Characteristics............................................................................. 906

Table 24.12 D/A Conversion Characteristics............................................................................. 906

Table 24.13 Flash Memory Characteristics................................................................................ 907

Rev. 3.00 Mar 17, 2006 page l of l

Section 1 Overview

Rev. 3.00 Mar 17, 2006 page 1 of 926

REJ09B0283-0300

Section 1 Overview

1.1 Features

• High-speed H8S/2600 central processing unit with an internal 16-bit architecture

Upward-co mpatib le with H8/300 and H8/300H CPUs o n an object level

Sixteen 16-bit general registers

69 basic instructions

• Various peripheral functions

DMA controller (DMAC)

EXDMA controller (EXDMAC)

Data transfer con troller (DTC)

16-bit timer-pulse unit (TPU)

Programmable pulse generator (PPG)

8-bit timer ( TMR)

Watchdog timer (WDT)

Asynchronous or clocked synchronous serial communication interface (SCI)

10-bit A/D co nverter

8-bit D/A converter

Clock pulse generator

• On-chip memory

ROM Type Model ROM RAM

Flash memory vers ion HD64F2676 256 kbytes 8 kbytes

Masked ROM version HD6432676 256 kbytes 8 kbytes

HD6432675 128 kbytes 8 kbytes

HD6432673 64 kbytes 8 kbytes

ROMless version HD6412674R — 32 kbytes

HD6412670 — 8 kbytes

• General I/O ports

I/O pins: 103

Input-onl y pins: 12

• Supports various power-down states

Section 1 Overview

Rev. 3.00 Mar 17, 2006 page 2 of 926

REJ09B0283-0300

• Compact package

Product Package (Code) Mounting Height Body Size Pin Pitch

H8S/2678 Group QFP-144 FP-144G 3.05 mm (Max.) 22.0 × 22.0 mm 0.5 mm

H8S/2678R Group LQFP-144 FP-144H 1.70 mm (Max.) 22.0 × 22.0 mm 0.5 mm

Section 1 Overview

Rev. 3.00 Mar 17, 2006 page 3 of 926

REJ09B0283-0300

1.2 Block Diagram

PE7/D7

PE6/D6

PE5/D5

PE4/D4

PE3/D3

PE2/D2

PE1/D1

PE0/D0

Internal data bus

Peripheral address bus

Peripheral data bus

PD7/D15

PD6/D14

PD5/D13

PD4/D12

PD3/D11

PD2/D10

PD1/D9

PD0/D8

Port D

PLLVcc

PLLVss

Vcc

Vss

PA7/A23

PA6/A22

PA5/A21

PA4/A20

PA3/A19

PA2/A18

PA1/A17

PA0/A16

PB7/A15

PB6/A14

PB5/A13

PB4/A12

PB3/A11

PB2/A10

PB1/A9

PB0/A8

PC7/A7

PC6/A6

PC5/A5

PC4/A4

PC3/A3

PC2/A2

PC1/A1

PC0/A0

P35/SCK1/(OE)

P34/SCK0

P33/RxD1

P32/RxD0/IrRxD

P31/TxD1

P30/TxD0/IrTxD

P57/AN15/DA3/IRQ7

P56/AN14/DA2/IRQ6

P55/AN13/IRQ5

P54/AN12/IRQ4

P53/ADTRG//IRQ3

P52/SCK2/IRQ2

P51/RxD2/IRQ1

P50/TxD2/IRQ0

P47/AN7/DA1

P46/AN6/DA0

P45/AN5

P44/AN4

P43/AN3

P42/AN2

P41/AN1

P40/AN0

Vref

AVcc

P20/PO0/TIOCA3/(IRQ8)

P21/PO1/TIOCB3/(IRQ9)

P22/PO2/TIOCC3/(IRQ10)

P23/PO3/TIOCD3/(IRQ11)

P24/PO4/TIOCA4/(IRQ12)

P25/PO5/TIOCB4/(IRQ13)

P26/PO6/TIOCA5/EDRAK0/(IRQ14)

P27/PO7/TIOCB5/EDRAK1/(IRQ15)

P10/PO8/TIOCA0

P11/PO9/TIOCB0

P12/PO10/TIOCC0/TCLKA

P13/PO11/TIOCD0/TCLKB

P14/PO12/TIOCA1

P15/PO13/TIOCB1/TCLKC

P16/PO14/TIOCA2/EDRAK2

P17/PO15/TIOCB2/TCLKD/EDRAK3

P65/TMO1/DACK1/IRQ13

P64/TMO0/DACK0/IRQ12

P63/TMCI1/TEND1/IRQ11

P62/TMCI0/TEND0/IRQ10

P61/TMRI1/DREQ1/IRQ9

P60/TMRI0/DREQ0/IRQ8

PG6/BREQ

PG5/BACK

PG4/BREQO

PG3/CS3

PG2/CS2

PG1/CS1

PG0/CS0

PF7/φ

PF6/AS

PF5/RD

PF4/HWR

PF3/LWR

PF2/LCAS/IRQ15

PF1/UCAS/IRQ14

PF0/WAIT

ROM*

(Flash memory

or mask ROM)

RAM WDT

TPU × 6 channels

TMR × 2 channels

SCI × 3 channels

8-bit D/A converter

10-bit A/D converter

PPG

MD2

MD1

MD0

EXTAL

XTAL

STBY

RES

WDTOVF

FWE*

NMI

H8S/2600 CPU

DTC

Interrupt controller

Port E

Port

P75/EDACK1/(DACK1)

P74/EDACK0/(DACK0)

P73/ETEND1/(TEND1)

P72/ETEND0/(TEND0)

P71/EDREQ1/(DREQ1)

P70/EDREQ0/(DREQ0)

Port

PH3/CS7/OE/(IRQ7)

PH2/CS6/(IRQ6)

PH1/CS5

PH0/CS4

Port

DMAC

EXDMAC

Internal address bus

P85/EDACK3/(IRQ5)

P84/EDACK2/(IRQ4)

P83/ETEND3/(IRQ3)

P82/ETEND2/(IRQ2)

P81/EDREQ3/(IRQ1)

P80/EDREQ2/(IRQ0)

Port

Bus controller

Notes:

Port

ROM is not supported in the ROMless version.

The FWE pin is used only in the F-ZTAT version. In other versions, this is an NC pin.

PLL

Clock

pulse

generator

Figure 1.1 H8S/2678 Group Internal Block Diagram

Section 1 Overview

Rev. 3.00 Mar 17, 2006 page 4 of 926

REJ09B0283-0300

PE7/D7

PE6/D6

PE5/D5

PE4/D4

PE3/D3

PE2/D2

PE1/D1

PE0/D0

PD7/D15

PD6/D14

PD5/D13

PD4/D12

PD3/D11

PD2/D10

PD1/D9

PD0/D8

Vcc

PLLVcc

PLLV

PA7/A23

PA6/A22

PA5/A21

PA4/A20

PA3/A19

PA2/A18

PA1/A17

PA0/A16

PB7/A15

PB6/A14

PB5/A13

PB4/A12

PB3/A11

PB2/A10

PB1/A9

PB0/A8

PC7/A7

PC6/A6

PC5/A5

PC4/A4

PC3/A3

PC2/A2

PC1/A1

PC0/A0

P35/SCK1/(OE)/(CKE)

P34/SCK0

P33/RxD1

P32/RxD0/IrRxD

P31/TxD1

P30/TxD0/IrTxD

P57/AN15/DA3/IRQ7

P56/AN14/DA2/IRQ6

P55/AN13/IRQ5

P54/AN12/IRQ4

P53/ADTRG//IRQ3

P52/SCK2/IRQ2

P51/RxD2/IRQ1

P50/TxD2/IRQ0

P47/AN7/DA1

P46/AN6/DA0

P45/AN5

P44/AN4

P43/AN3

P42/AN2

P41/AN1

P40/AN0

Vref

AVcc

AVss

P20/PO0/TIOCA3/(IRQ8)

P21/PO1/TIOCB3/(IRQ9)

P22/PO2/TIOCC3/(IRQ10)

P23/PO3/TIOCD3/(IRQ11)

P24/PO4/TIOCA4/(IRQ12)

P25/PO5/TIOCB4/(IRQ13)

P26/PO6/TIOCA5/EDRAK0/(IRQ14)

P27/PO7/TIOCB5/EDRAK1/(IRQ15)

P10/PO8/TIOCA0

P11/PO9/TIOCB0

P12/PO10/TIOCC0/TCLKA

P13/PO11/TIOCD0/TCLKB

P14/PO12/TIOCA1

P15/PO13/TIOCB1/TCLKC

P16/PO14/TIOCA2/EDRAK2

P17/PO15/TIOCB2/TCLKD/EDRAK3

P65/TMO1/DACK1/IRQ13

P64/TMO0/DACK0/IRQ12

P63/TMCI1/TEND1/IRQ11

P62/TMCI0/TEND0/IRQ10

P61/TMRI1/DREQ1/IRQ9

P60/TMRI0/DREQ0/IRQ8

PG6/BREQ

PG5/BACK

PG4/BREQO

PG3/CS3/RAS3/CAS

PG2/CS2/RAS2/RAS

PG1/CS1

PG0/CS0

PF7/φ

PF6/AS

PF5/RD

PF4/HWR

PF3/LWR

PF2/LCAS/IRQ15/DQML

PF1

UCAS/IRQ14/DQMU

PF0/WAIT

ROM*

(Flash memory)

RAM WDT

EXDMAC

TPU × 6 channels

Note: * ROM is not supported in the ROMless version.

SCI

× 3 channels

PPG

Port 1 Port 2 Port 4

MD2

MD1

MD0

DCTL

EXTAL

XTAL

STBY

RES

WDTOVF

NMI

H8S/2600 CPU

Interrupt controller

Port D Port E

Port APort B

Peripheral data bus

Peripheral address bus

Bus controller

Port CPort 3Port 5

DTC

P75/EDACK1/(DACK1)

P74/EDACK0/(DACK0)

P73/ETEND1/(TEND1)

P72/ETEND0/(TEND0)

P71/EDREQ1/(DREQ1)

P70/EDREQ0/(DREQ0)

PH3/CS7/OE/(IRQ7)/CKE

PH2/CS6/(IRQ6)

PH1/CS5/RAS5/SDRAMφ

PH0/CS4/RAS4/WE

DMAC

P85/EDACK3/(IRQ5)

P84/EDACK2/(IRQ4)

P83/ETEND3/(IRQ3)

P82/ETEND2/(IRQ2)

P81/EDREQ3/(IRQ1)

P80/EDREQ2/(IRQ0)

PLL

Clock

pulse

generator

Port 8 Port 6 Port G Port F

TMR × 2 channels

8-bit D/A converter

10-bit A/D converter

Internal data bus

Internal address bus

Port HPort 7

Figure 1.2 H8S/2678R Group Internal Block Diagram

Section 1 Overview

Rev. 3.00 Mar 17, 2006 page 5 of 926

REJ09B0283-0300

1.3 Pin Description

1.3.1 Pin Arrangement

MD2

P83/ETEND3/(IRQ3)

P84/EDACK2/(IRQ4)

P85/EDACK3/(IRQ5)

Vcc

PC0/A0

PC1/A1

PC2/A2

PC3/A3

PC4/A4

PC5/A5

Vss

PC6/A6

PC7/A7

PB0/A8

PB1/A9

PB2/A10

PB3/A11

Vss

PB4/A12

PB5/A13

PB6/A14

PB7/A15

PA0/A16

PA1/A17

Vss

PA2/A18

PA3/A19

PA4/A20

PA5/A21

PA6/A22

PA7/A23

NC*

P70/EDREQ0/(DREQ0)

P71/EDREQ1/(DREQ1)

P72/ETEND0/(TEND0)

P51/RxD2/IRQ1

P50/TxD2/IRQ0

PH1/CS5

PH0/CS4

PG3/CS3

PG2/CS2

PG1/CS1

PG0/CS0

STBY

Vss

XTAL

EXTAL

Vcc

PF7/φ

PLLVcc

RES

PLLVss

PF6/AS

PF5/RD

PF4/HWR

PF3/LWR

PF2/LCAS/IRQ15

PF1/UCAS/IRQ14

PF0/WAIT

P65/TMO1/DACK1/IRQ13

P64/TMO0/DACK0/IRQ12

P63/TMCI1/TEND1/IRQ1

P62/TMCI0/TEND0/IRQ1

PD0/D8

PD1/D9

PD2/D10

PD3/D11

Vss

PD4/D12

PD5/D13

PD6/D14

108

107

106

105

104

103

102

101

100

P52/SCK2/IRQ2

P53/ADTRG/IRQ3

PH2/CS6/(IRQ6)

PH3/CS7/OE/(IRQ7)

PG4/BREQO

PG5/BACK

PG6/BREQ

Vcc

P40/AN0

P41/AN1

P42/AN2

P43/AN3

Vref

AVcc

P44/AN4

P45/AN5

P46/AN6/DA0

P47/AN7/DA1

P54/AN12/IRQ4

P55/AN13/IRQ5

P56/AN14/DA2/IRQ6

P57/AN15/DA3/IRQ7

AVss

NC*

P35/SCK1/(OE)

P34/SCK0

P33/RxD1

Vss

P32/RxD0/IrRxD

P31/TxD1

P30/TxD0/IrTxD

P80/EDREQ2/(IRQ0)

P81/EDREQ3/(IRQ1)

P82/ETEND2/(IRQ2)

MD0

MD1

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

PD7/D15

PE0/D0

PE1/D1

PE2/D2

PE3/D3

Vcc

PE4/D4

PE5/D5

PE6/D6

PE7/D7

FWE*

P61/TMRI1/DREQ1/IRQ9

P60/TMRI0/DREQ0/IRQ8

P27/PO7/TIOCB5/EDRAK1/(IRQ15)

P26/PO6/TIOCA5/EDRAK0/(IRQ14)

P25/PO5/TIOCB4/(IRQ13)

P24/PO4/TIOCA4/(IRQ12)

P23/PO3/TIOCD3/(IRQ11)

P22/PO2/TIOCC3/(IRQ10)

P21/PO1/TIOCB3/(IRQ9)

P20/PO0/TIOCA3/(IRQ8)

P17/PO15/TIOCB2/TCLKD/EDRAK

P16/PO14/TIOCA2/EDRAK2

P15/PO13/TIOCB1/TCLKC

P14/PO12/TIOCA1

Vss

P13/PO11/TIOCD0/TCLKB

P12/PO10/TIOCC0/TCLKA

P11/PO9/TIOCB0

P10/PO8/TIOCA0

P75/EDACK1/(DACK1)

P74/EDACK0/(DACK0)

P73/ETEND1/(TEND1)

Vcc

NMI

WDTOVF

FP-144G

(Top view)

Notes: 1. The FWE pin is used only in the F-ZTAT version. In other versions, this is an NC pin.

2. An NC pin should be unconnected.

Figure 1.3 H8S/2678 Group Pin Arrangement

Section 1 Overview

Rev. 3.00 Mar 17, 2006 page 6 of 926

REJ09B0283-0300

MD2

P83/ETEND3/(IRQ3)

P84/EDACK2/(IRQ4)

P85/EDACK3/(IRQ5)

Vcc

PC0/A0

PC1/A1

PC2/A2

PC3/A3

PC4/A4

PC5/A5

Vss

PC6/A6

PC7/A7

PB0/A8

PB1/A9

PB2/A10

PB3/A11

Vss

PB4/A12

PB5/A13

PB6/A14

PB7/A15

PA0/A16

PA1/A17

Vss

PA2/A18

PA3/A19

PA4/A20

PA5/A21

PA6/A22

PA7/A23

NC*

P70/EDREQ0/(DREQ0)

P71/EDREQ1/(DREQ1)

P72/ETEND0/(TEND0)

P51/RxD2/IRQ1

P50/TxD2/IRQ0

PH1/CS5/RAS5/SDRAMφ

PH0/CS4/RAS4/WE

PG3/CS3/RAS3/CAS

PG2/CS2/RAS2/RAS

PG1/CS1

PG0/CS0

STBY

Vss

XTAL

EXTAL

Vcc

PF7/φ

PLLVcc

RES

PLLVss

PF6/AS

PF5/RD

PF4/HWR

PF3/LWR

PF2/LCAS/IRQ15/DQML

PF1/UCAS/IRQ14/DQMU

PF0/WAIT

P65/TMO1/DACK1/IRQ13

P64/TMO0/DACK0/IRQ12

P63/TMCI1/TEND1/IRQ1

P62/TMCI0/TEND0/IRQ1

PD0/D8

PD1/D9

PD2/D10

PD3/D11

Vss

PD4/D12

PD5/D13

PD6/D14

108

107

106

105

104

103

102

101

100

P52/SCK2/IRQ2

P53/ADTRG/IRQ3

PH2/CS6/(IRQ6)

PH3/CS7/OE/(IRQ7)

PG4/BREQO

PG5/BACK

PG6/BREQ

Vcc

P40/AN0

P41/AN1

P42/AN2

P43/AN3

Vref

AVcc

P44/AN4

P45/AN5

P46/AN6/DA0

P47/AN7/DA1

P54/AN12/IRQ4

P55/AN13/IRQ5

P56/AN14/DA2/IRQ6

P57/AN15/DA3/IRQ7

AVss

DCTL

P35/SCK1/(OE)/(CKE)

P34/SCK0

P33/RxD1

Vss

P32/RxD0/IrRxD

P31/TxD1

P30/TxD0/IrTxD

P80/EDREQ2/(IRQ0)

P81/EDREQ3/(IRQ1)

P82/ETEND2/(IRQ2)

MD0

MD1

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

PD7/D15

PE0/D0

PE1/D1

PE2/D2

PE3/D3

Vcc

PE4/D4

PE5/D5

PE6/D6

PE7/D7

Vss

P61/TMRI1/DREQ1/IRQ9

P60/TMRI0/DREQ0/IRQ8

P27/PO7/TIOCB5/EDRAK1/(IRQ15)

P26/PO6/TIOCA5/EDRAK0/(IRQ14)

P25/PO5/TIOCB4/(IRQ13)

P24/PO4/TIOCA4/(IRQ12)

P23/PO3/TIOCD3/(IRQ11)

P22/PO2/TIOCC3/(IRQ10)

P21/PO1/TIOCB3/(IRQ9)

P20/PO0/TIOCA3/(IRQ8)

P17/PO15/TIOCB2/TCLKD/EDRAK

P16/PO14/TIOCA2/EDRAK2

P15/PO13/TIOCB1/TCLKC

P14/PO12/TIOCA1

Vss

P13/PO11/TIOCD0/TCLKB

P12/PO10/TIOCC0/TCLKA

P11/PO9/TIOCB0

P10/PO8/TIOCA0

P75/EDACK1/(DACK1)

P74/EDACK0/(DACK0)

P73/ETEND1/(TEND1)

Vcc

NMI

WDTOVF

FP-144H

(Top view)

Note: * An NC pin should be unconnected.

Figure 1.4 H8S/2678R Group Pin Arrangement

Section 1 Overview

Rev. 3.00 Mar 17, 2006 page 7 of 926

REJ09B0283-0300

1.3.2 Pin Arrangement in Each Operating Mode

Table 1.1 Pin Arrangement in Each Operating Mode

Pin Name

Mode 7

No. Modes 1 and 5 Modes 2 and 6 Mode 4 EXPE = 1 EXPE = 0

Flas h Memory

Programmer

Mode

1 MD2 MD2 MD2 MD2 MD2 Vss

2 P83/ETEND3/

(IRQ3)P83/ETEND3/

(IRQ3)P83/(IRQ3)NC

3P84/EDACK2/

(IRQ4)P84/EDACK2/

(IRQ4)P84/(IRQ4)NC

4P85/EDACK3/

(IRQ5)P85/EDACK3/

(IRQ5)P85/(IRQ5)NC

5 Vcc Vcc Vcc Vcc Vcc Vcc

6 A0 A0 PC0/A0 PC0/A0 PC0 A0

7 A1 A1 PC1/A1 PC1/A1 PC1 A1

8 A2 A2 PC2/A2 PC2/A2 PC2 A2

9 A3 A3 PC3/A3 PC3/A3 PC3 A3

10 A4 A4 PC4/A4 PC4/A4 PC4 A4

11 A5 A5 PC5/A5 PC5/A5 PC5 A5

12 Vss Vss Vss Vss Vss Vss

13 A6 A6 PC6/A6 PC6/A6 PC6 A6

14 A7 A7 PC7/A7 PC7/A7 PC7 A7

15 A8 A8 PB0/A8 PB0/A8 PB0 A8

16 A9 A9 PB1/A9 PB1/A9 PB1 A9

17 A10 A10 PB2/A10 PB2/A10 PB2 A10

18 A11 A11 PB3/A11 PB3/A11 PB3 A11

19 Vss Vss Vss Vss Vss Vss

20 A12 A12 PB4/A12 PB4/A12 PB4 A12

21 A13 A13 PB5/A13 PB5/A13 PB5 A13

22 A14 A14 PB6/A14 PB6/A14 PB6 A14

23 A15 A15 PB7/A15 PB7/A15 PB7 A15

24 A16 A16 PA0/A16 PA0/A16 PA0 A16

25 A17 A17 PA1/A17 PA1/A17 PA1 A17

26 Vss Vss Vss Vss Vss Vss

Section 1 Overview

Rev. 3.00 Mar 17, 2006 page 8 of 926

REJ09B0283-0300

Pin Name

Mode 7

No. Modes 1 and 5 Modes 2 and 6 Mode 4 EXPE = 1 EXPE = 0

Flas h Memory

Programmer

Mode

27 A18 A18 PA2/A18 PA2/A18 PA2 A18

28 A19 A19 PA3/A19 PA3/A19 PA3 NC

29 A20 A20 PA4/A20 PA4/A20 PA4 NC

30 PA5/A21 PA5/A21 PA5/A21 PA5/A21 PA5 NC

31 PA6/A22 PA6/A22 PA6/A22 PA6/A22 PA6 NC

32 PA7/A23 PA7/A23 PA7/A23 PA7/A23 PA7 NC

33 NC NC NC NC NC NC

34 P70/EDREQ0/

(DREQ0)P70/EDREQ0/

(DREQ0)P70/(DREQ0)NC

35 P71/EDREQ1/

(DREQ1)P71/EDREQ1/

(DREQ1)P71/(DREQ1)NC

36 P72/ETEND0/

(TEND0)P72/ETEND0/

(TEND0)P72/(TEND0)NC

37 WDTOVF WDTOVF WDTOVF WDTOVF WDTOVF NC

38 NMI NMI NMI NMI NMI Vcc

39 Vcc Vcc Vcc Vcc Vcc Vcc

40 P73/ETEND1/

(TEND1)P73/ETEND1/

(TEND1)P73/(TEND1)NC

41 P74/EDACK0/

(DACK0)P74/EDACK0/

(DACK0)P74/(DACK0)NC

42 P75/EDACK1/

(DACK1)P75/EDACK1/

(DACK1)P75/(DACK1)NC

43 P10/PO8/TIOCA0 P10/PO8/TIOCA0 P10/PO8/TIOCA0 P10/PO8/TIOCA0 P10/PO8/TIOCA0 NC

44 P11/PO9/TIOCB0 P11/PO9/TIOCB0 P11/PO9/TIOCB0 P11/PO9/TIOCB0 P11/PO9/TIOCB0 NC

45 P12/PO10/

TIOCC0/TCLKA P12/PO10/

TIOCC0/TCLKA NC

46 P13/PO11/

TIOCD0/TCLKB P13/PO11/

TIOCD0/TCLKB NC

47 Vss Vss Vss Vss Vss Vss

48 P14/PO12/

TIOCA1 P14/PO12/

TIOCA1 NC

49 P15/PO13/

TIOCB1/TCLKC P15/PO13/

TIOCB1/TCLKC NC

50 P16/PO14/

TIOCA2/EDRAK2

P16/PO14/

TIOCA2/EDRAK2

P16/PO14/

TIOCA2/EDRAK2

P16/PO14/

TIOCA2/EDRAK2

P16/PO14/

TIOCA2 NC

Section 1 Overview

Rev. 3.00 Mar 17, 2006 page 9 of 926

REJ09B0283-0300

Pin Name

Mode 7

No. Modes 1 and 5 Modes 2 and 6 Mode 4 EXPE = 1 EXPE = 0

Flas h Memory

Programmer

Mode

51 P17/PO15/

TIOCB2/TCLKD/

EDRAK3

P17/PO15/

TIOCB2/TCLKD/

EDRAK3

P17/PO15/

TIOCB2/TCLKD/

EDRAK3

P17/PO15/

TIOCB2/TCLKD/

EDRAK3

P17/PO15/

TIOCB2/TCLKD NC

52 P20/PO0/

TIOCA3/(IRQ8)P20/PO0/

TIOCA3/(IRQ8)NC

53 P21/PO1/

TIOCB3/(IRQ9)P21/PO1/

TIOCB3/(IRQ9)NC

54 P22/PO2/

TIOCC3/(IRQ10)P22/PO2/

TIOCC3/(IRQ10)

55 P23/PO3/

TIOCD3/(IRQ11)P23/PO3/

TIOCD3/(IRQ11)

56 P24/PO4/

TIOCA4/(IRQ12)P24/PO4/

TIOCA4/(IRQ12)

57 P25/PO5/

TIOCB4/(IRQ13)P25/PO5/

TIOCB4/(IRQ13)Vss

58 P26/PO6/

TIOCA5/

EDRAK0/(IRQ14)

P26/PO6/

TIOCA5/

EDRAK0/(IRQ14)

P26/PO6/

TIOCA5/

EDRAK0/(IRQ14)

P26/PO6/

TIOCA5/

EDRAK0/(IRQ14)

P26/PO6/

TIOCA5/(IRQ14)NC

59 P27/PO7/

TIOCB5/

EDRAK1/(IRQ15)

P27/PO7/

TIOCB5/

EDRAK1/(IRQ15)

P27/PO7/

TIOCB5/

EDRAK1/(IRQ15)

P27/PO7/

TIOCB5/

EDRAK1/(IRQ15)

P27/PO7/

TIOCB5/(IRQ15)NC

60 P60/TMRI0/

DREQ0/IRQ8

P60/TMRI0/

DREQ0/IRQ8

P60/TMRI0/

DREQ0/IRQ8

P60/TMRI0/

DREQ0/IRQ8

P60/TMRI0/

DREQ0/IRQ8

61 P61/TMRI1/

DREQ1/IRQ9

P61/TMRI1/

DREQ1/IRQ9

P61/TMRI1/

DREQ1/IRQ9

P61/TMRI1/

DREQ1/IRQ9

P61/TMRI1/

DREQ1/IRQ9

62 FWE*1

Vss*2FWE*1

Vss*2

63 D7 PE7/D7 PE7/D7 PE7/D7 PE7 NC

64 D6 PE6/D6 PE6/D6 PE6/D6 PE6 NC

65 D5 PE5/D5 PE5/D5 PE5/D5 PE5 NC

66 D4 PE4/D4 PE4/D4 PE4/D4 PE4 NC

67 Vcc Vcc Vcc Vcc Vcc Vcc

68 D3 PE3/D3 PE3/D3 PE3/D3 PE3 NC

69 D2 PE2/D2 PE2/D2 PE2/D2 PE2 NC

70 D1 PE1/D1 PE1/D1 PE1/D1 PE1 NC

71 D0 PE0/D0 PE0/D0 PE0/D0 PE0 NC

72 D15 D15 D15 D15 PD7 I/O7

Section 1 Overview

Rev. 3.00 Mar 17, 2006 page 10 of 926

REJ09B0283-0300

Pin Name

Mode 7

No. Modes 1 and 5 Modes 2 and 6 Mode 4 EXPE = 1 EXPE = 0

Flas h Memory

Programmer

Mode

73 D14 D14 D14 D14 PD6 I/O6

74 D13 D13 D13 D13 PD5 I/O5

75 D12 D12 D12 D12 PD4 I/O4

76 Vss Vss Vss Vss Vss Vss

77 D11 D11 D11 D11 PD3 I/O3

78 D10 D10 D10 D10 PD2 I/O2

79 D9 D9 D9 D9 PD1 I/O1

80 D8 D8 D8 D8 PD0 I/O0

81 P62/TMCI0/

TEND0/IRQ10

P62/TMCI0/

TEND0/IRQ10

P62/TMCI0/

TEND0/IRQ10

P62/TMCI0/

TEND0/IRQ10

P62/TMCI0/

TEND0/IRQ10

82 P63/TMCI1/

TEND1/IRQ11

P63/TMCI1/

TEND1/IRQ11

P63/TMCI1/

TEND1/IRQ11

P63/TMCI1/

TEND1/IRQ11

P63/TMCI1/

TEND1/IRQ11

83 P64/TMO0/

DACK0/IRQ12

P64/TMO0/

DACK0/IRQ12

P64/TMO0/

DACK0/IRQ12

P64/TMO0/

DACK0/IRQ12

P64/TMO0/

DACK0/IRQ12

84 P65/TMO1/

DACK1/IRQ13

P65/TMO1/

DACK1/IRQ13

P65/TMO1/

DACK1/IRQ13

P65/TMO1/

DACK1/IRQ13

P65/TMO1/

DACK1/IRQ13

85 PF0/WAIT PF0/WAIT PF0/WAIT PF0/WAIT PF0 NC

86 PF1/UCAS/

IRQ14/DQMU*2PF1/UCAS/

IRQ14/DQMU*2PF1/IRQ14 NC

87 PF2/LCAS/

IRQ15/DQML*2PF2/LCAS/

IRQ15/DQML*2PF2/IRQ15 NC

88 PF3/LWR PF3/LWR PF3/LWR PF3/LWR PF3 NC

89 HWR HWR HWR HWR PF4 NC

90 RD RD RD RD PF5 NC

91 PF6/AS PF6/AS PF6/AS PF6/AS PF6 NC

92 PLLVss PLLVss PLLVss PLLVss PLLVss Vss

93 RES RES RES RES RES RES

94 PLLVcc PLLVcc PLLVcc PLLVcc PLLVcc Vcc

95 PF7/ φPF7/ φPF7/ φPF7/ φPF7/ φNC

96 Vcc Vcc Vcc Vcc Vcc Vcc

97 EXTAL EXTAL EXTAL EXTAL EXTAL EXTAL

98 XTAL XTAL XTAL XTAL XTAL XTAL

99 Vss Vss Vss Vss Vss Vss

100 STBY STBY STBY STBY STBY Vcc

Section 1 Overview

Rev. 3.00 Mar 17, 2006 page 11 of 926

REJ09B0283-0300

Pin Name

Mode 7

No. Modes 1 and 5 Modes 2 and 6 Mode 4 EXPE = 1 EXPE = 0

Flas h Memory

Programmer

Mode

101 PG0/CS0 PG0/CS0 PG0/CS0 PG0/CS0 PG0 NC

102 PG1/CS1 PG1/CS1 PG1/CS1 PG1/CS1 PG1 NC

103 PG2/CS2/

RAS2*2/RAS*2PG2/CS2/

RAS2*2/RAS*2PG2 NC

104 PG3/CS3/

RAS3*2/CAS*2PG3/CS3/

RAS3*2/CAS*2PG3 NC

105 PH0/CS4/

RAS4*2/WE*2PH0/CS4/

RAS4*2/WE*2PH0 NC

106 PH1/CS5/

RAS5*2/

SDRAMφ*2

PH1/CS5/

RAS5*2/

SDRAMφ*2

PH1/CS5/

RAS5*2/

SDRAMφ*2

PH1/CS5/

RAS5*2/

SDRAMφ*2

PH1 NC

107 P50/TxD2/IRQ0 P50/TxD2/IRQ0 P50/TxD2/IRQ0 P50/TxD2/IRQ0 P50/TxD2/IRQ0 Vss

108 P51/RxD2/IRQ1 P51/RxD2/IRQ1 P51/RxD2/IRQ1 P51/RxD2/IRQ1 P51/RxD2/IRQ1 Vss

109 P52/SCK2/IRQ2 P52/SCK2/IRQ2 P52/SCK2/IRQ2 P52/SCK2/IRQ2 P52/SCK2/IRQ2 Vcc

110 P53/ADTRG/

IRQ3

P53/ADTRG/

IRQ3

P53/ADTRG/

IRQ3

P53/ADTRG/

IRQ3

P53/ADTRG/

IRQ3

111 PH2/CS6/(IRQ6)PH2/CS6/(IRQ6)PH2/CS6/(IRQ6)PH2/CS6/(IRQ6)PH2/(IRQ6)NC

112 PH3/CS7/OE/

(IRQ7)/CKE*2PH3/CS7/OE/

(IRQ7)/CKE*2PH3/(IRQ7)NC

113 PG4/BREQO PG4/BREQO PG4/BREQO PG4/BREQO PG4 NC

114 PG5/BACK PG5/BACK PG5/BACK PG5/BACK PG5 NC

115 PG6/BREQ PG6/BREQ PG6/BREQ PG6/BREQ PG6 NC

116 Vcc Vcc Vcc Vcc Vcc Vcc

117 P40/AN0 P40/AN0 P40/AN0 P40/AN0 P40/AN0 NC

118 P41/AN1 P41/AN1 P41/AN1 P41/AN1 P41/AN1 NC

119 P42/AN2 P42/AN2 P42/AN2 P42/AN2 P42/AN2 NC

120 P43/AN3 P43/AN3 P43/AN3 P43/AN3 P43/AN3 NC

121 Vref Vref Vref Vref Vref NC

122 AVcc AVcc AVcc AVcc AVcc Vcc

123 P44/AN4 P44/AN4 P44/AN4 P44/AN4 P44/AN4 NC

124 P45/AN5 P45/AN5 P45/AN5 P45/AN5 P45/AN5 NC

125 P46/AN6/DA0 P46/AN6/DA0 P46/AN6/DA0 P46/AN6/DA0 P46/AN6/DA0 NC

126 P47/AN7/DA1 P47/AN7/DA1 P47/AN7/DA1 P47/AN7/DA1 P47/AN7/DA1 NC

127 P54/AN12/IRQ4 P54/AN12/IRQ4 P54/AN12/IRQ4 P54/AN12/IRQ4 P54/AN12/IRQ4 NC

Section 1 Overview

Rev. 3.00 Mar 17, 2006 page 12 of 926

REJ09B0283-0300

Pin Name

Mode 7

No. Modes 1 and 5 Modes 2 and 6 Mode 4 EXPE = 1 EXPE = 0

Flas h Memory

Programmer

Mode

128 P55/AN13/IRQ5 P55/AN13/IRQ5 P55/AN13/IRQ5 P55/AN13/IRQ5 P55/AN13/IRQ5 NC

129 P56/AN14/DA2/

IRQ6

P56/AN14/DA2/

IRQ6

P56/AN14/DA2/

IRQ6

P56/AN14/DA2/

IRQ6

P56/AN14/DA2/

IRQ6

130 P57/AN15/DA3/

IRQ7

P57/AN15/DA3/

IRQ7

P57/AN15/DA3/

IRQ7

P57/AN15/DA3/

IRQ7

P57/AN15/DA3/

IRQ7

131 AVss AVss AVss AVss AVss Vss

132 NC*3

DCTL*2NC*3

Vss *2

133 P35/SCK1/(OE)/

(CKE)*2P35/SCK1/(OE)/

(CKE)*2P35/SCK1 NC

134 P34/SCK0 P34/SCK0 P34/SCK0 P34/SCK0 P34/SCK0 NC

135 P33/RxD1 P33/RxD1 P33/RxD1 P33/RxD1 P33/RxD1 NC

136 Vss Vss Vss Vss Vss Vss

137 P32/RxD0/IrRxD P32/RxD0/IrRxD P32/RxD0/IrRxD P32/RxD0/IrRxD P32/RxD0/IrRxD Vcc

138 P31/TxD1 P31/TxD1 P31/TxD1 P31/TxD1 P31/TxD1 NC

139 P30/TxD0/IrTxD P30/TxD0/IrTxD P30/TxD0/IrTxD P30/TxD0/IrTxD P30/TxD0/IrTxD NC

140 P80/EDREQ2/

(IRQ0)P80/EDREQ2/

(IRQ0)P80/(IRQ0)NC

141 P81/EDREQ3/

(IRQ1)P81/EDREQ3/

(IRQ1)P81/(IRQ1)NC

142 P82/ETEND2/

(IRQ2)P82/ETEND2/

(IRQ2)P82/(IRQ2)NC

143 MD0 MD0 MD0 MD0 MD0 Vss

144 MD1 MD1 MD1 MD1 MD1 Vss

Notes: 1. The FWE pin is used only in the flash memory version of the H8S/2678 Group. In the

masked ROM and ROMless versions of the H8S/2678 Group, this is an NC pin.

2. Only for the H8S/2678R Group.

3. Only for the H8S/2678 Group.

Section 1 Overview

Rev. 3.00 Mar 17, 2006 page 13 of 926

REJ09B0283-0300

1.3.3 Pin Functions

Table 1.2 Pin Functions

Pin No.

Type Symbol

FP-144G

(H8S/2678

Group)

FP-144H

(H8S/2678R

Group) I/O Function

Power supply VCC 5, 39, 67,

96, 116 5, 39, 67,

96, 116 Input For connection to the power supply.

All VCC pins should be connec ted to

the system power supply.

VSS 12, 19, 26,

47, 76, 99,

136

12, 19, 26,

47, 76, 99,

136

Input For connection to ground. All VSS

pins should be connected to the

system power supply (0 V).

PLLVCC 94 94 Input Power supply pin for the on-chip

PLL oscillator.

PLLVSS 92 92 Input Ground pin for the on-chip PLL

oscillator.

Clock XTAL 98 98 Input For connection to a crystal

oscillator. See section 21, Clock

Pulse Generator for typical

connection diagrams for a crystal

oscillator and ext ernal clock input.

EXTAL 97 97 Input For connection to a crystal

oscillator. The EXTAL pin can also

input an external clock. See section

21, Clock Pulse Generator for

typical connection diagrams for a

crystal oscillator and external clock

input.

φ95 95 Output Supplies the system clo ck to

external dev ic es.

SDRAMφ—106 Output When a synchronous DRAM is

connected, this pin is connected to

the CLK pin of the synchronous

DRAM. For details, refer to section

6, Bus Controller (BSC).

Operating

mode control MD2

MD1

MD0

1, 144,

143 1, 144,

143 Input These pins set the operatin g mode.

These pins should not be cha nged

while the MCU is operating.

Section 1 Overview

Rev. 3.00 Mar 17, 2006 page 14 of 926

REJ09B0283-0300

Pin No.

Type Symbol

FP-144G

(H8S/2678

Group)

FP-144H

(H8S/2678R

Group) I/O Function

Operating

mode control DCTL —132 Input When this pin is driven high,

SDRAMφ dedicated to the

synchronous DRAM is output.

When not using the sync hronous

DRAM interface, drive this pin low.

The level of this pin must not be

changed during opera t ion .

System

control RES 93 93 Input When this pin is driven low, the chip

is reset.

STBY 100 100 Input When this pin is driven low, a

transition is made to hardware

standby mode.

BREQ 115 115 Input Requests chip to release the bus to

an external bus master.

BREQO 113 113 Output External bus request signal used

when an internal bus master

accesses external space when the

external bus is released.

BACK 114 114 Output Indicates that the bus has been

released to an external bus master.

FWE 62 —Input Enables/disables flash memory.

This pin is only used in the flash

memory version.

Address bus A23 to

A0 32 to 27,

25 to 20,

18 to 13,

11 to 6

32 to 27,

25 to 20,

18 to 13,

11 to 6

Output These pins output an address.

Data bus D15 to

D0 72 to 75,

77 to 80,

63 to 66,

68 to 71

72 to 75,

77 to 80,

63 to 66,

68 to 71

Input/

output These pins consti tute a bidire cti ona l

data bus.

Bus control CS7 to

CS0 112, 111,

106 to 101 112, 111,

106 to 101 Output Signals that select division areas 7

to 0 in the ex ternal address spac e.

AS 91 91 Output When this pin is low, it indicates that

address output on the address bus

is valid.

Section 1 Overview

Rev. 3.00 Mar 17, 2006 page 15 of 926

REJ09B0283-0300

Pin No.

Type Symbol

FP-144G

(H8S/2678

Group)

FP-144H

(H8S/2678R

Group) I/O Function

Bus control RD 90 90 Output When this pin is low, it indicates that

the external address space is being

read.

HWR 89 89 Output Strobe signal indicating that extern al

address space is to be writt en, and

the upper half (D15 to D8) of the

data bus is enable d.

Write enable signal for DRAM

interface space.

LWR 88 88 Output Strobe signal indicating that extern al

address space is to be writt en, and

the lower half (D7 to D0) of the data

bus is enabled .

UCAS 86 86 Output Upper column address strobe signal

for 16-bit DRAM interface space.

Column address strobe signal for 8-

bit DRAM interface space.

LCAS 87 87 Output Lower column address strobe signal

for 16-bit DRAM interface space.

DQMU —86 Output Upper data mask enable signal for

16-bit synchronous DRAM for 16-bit

synchronous DRAM interface.

Data mask enable signal for 8-bit

synchronous DRAM interface

space.

DQML —87 Output Lower-data mask enable signal for

16-bit synchronous DRAM interface

space.

RAS/

RAS2

RAS3 to

RAS5

—103 to 106 Output Row address strobe signal for the

synchronous DRAM interface.

RAS signal is a row address strobe

signal when areas 2 to 5 are set to

the continuous DRAM space.

RAS —103 Row address strobe sig nal for the

synchronous DRAM of the

synchronous DRAM interface.

Section 1 Overview

Rev. 3.00 Mar 17, 2006 page 16 of 926

REJ09B0283-0300

Pin No.

Type Symbol

FP-144G

(H8S/2678

Group)

FP-144H

(H8S/2678R

Group) I/O Function

Bus control CAS —104 Output Column address strobe signal for

the synchronous DRAM of the

synchronous DRAM interface.

WE —105 Output Write enable signal for the

synchronous DRAM of the

synchronous DRAM interface.

WAIT 85 85 Input Requests insertion of a wait state in

the bus cycle when accessing

external 3-st ate addre ss space .

(OE)112, 133 112, 133 Output Output enable signal for DRAM

interface space.

The output pins of OE and (OE) are

selected by the port function control

CKE

(CKE) —112, 133 Output Clock enable signal of the

synchronous DRAM interface

space.

The output pins of CKE and (CKE)

are selected by the port function

control register 2 (PFCR2) of port 3.

Interrupt

signals NMI 38 38 Input Nonmaskable interrupt request pin.

Fix high when not used.

IRQ15 to

IRQ0 87, 86,

84 to 81,

61, 60,

130 to 127,

110 to 107

87, 86,

84 to 81,

61, 60,

130 to 127,

110 to 107

(IRQ15)

to (IRQ0)59 to 52,

112, 111,

4 to 2,

142 to 140

59 to 52,

112, 111,

4 to 2,

142 to 140

Input These pins request a maskable

interrupt.

The input pins of DREQn and

(DREQn) are selected by the IRQ

pin select register (ITSR) of the

interrupt controller. (n = 0 to 15)

DMA controller

(DMAC) DREQ1

DREQ0

(DREQ1)

(DREQ0)

61, 60,

35, 34 61, 60,

35, 34 Input These signals request DMAC

activation.

The input pins of DREQn and

(DREQn) are selected by the IRQ

pin select register (ITSR) of the

interrupt controller. (n = 0 to 15)

Section 1 Overview

Rev. 3.00 Mar 17, 2006 page 17 of 926

REJ09B0283-0300

Pin No.

Type Symbol

FP-144G

(H8S/2678

Group)

FP-144H

(H8S/2678R

Group) I/O Function

DMA controller

(DMAC) TEND1

TEND0

(TEND1)

(TEND0)

82, 81,

40, 36 82, 81,

40, 36 Output These signals indicate the end of

DMAC data transfer.

The input pins of TENDn and

(TENDn) are selected by the port

function control register 2 (PFCR2)

of port 3. (n = 1, 0)

DACK1

DACK0

(DACK1)

(DACK0)

84, 83,

42, 41 84, 83,

42, 41 Output DMAC single address transfer

acknowle dge si gna ls.

The input pins of DACKn and

(DACKn) are selected by the port

function control register 2 (PFCR2)

of port 3. (n = 1, 0)

EXDMA

controller

(EXDMAC)

EDREQ3

EDREQ0

141, 140,

35, 34 141, 140,

35, 34 Input These signals request EXDMAC

activation.

ETEND3

ETEND0

2, 142,

40, 36 2, 142,

40, 36 Output These signals indicate the end of

EXDMAC data transfer.

EDACK3

EDACK0

4, 3, 42,

41 4, 3, 42,

41 Output EXDMAC single address transfer

acknowle dge si gna ls.

EDRAK3

EDRAK0

51, 50,

59, 58 51, 50,

59, 58 Output These signals notify an external

device of acceptance and start of

execution of a DMA transfer

request.

16-bit timer

pulse unit

(TPU)

TCLKA

TCLKB

TCLKC

TCLKD

45, 46,

49, 51 45, 46,

49, 51 Input External clock inp ut pins.

TIOCA0

TIOCB0

TIOCC0

TIOCD0

43, 44,

45, 46 43, 44,

45, 46 Input/

output TGRA_0 to TGRD_0 input capture

input/out put com pare output/PWM

output pins.

TIOCA1

TIOCB1 48, 49 48, 49 Input/

output TGRA_1 and TGRB_1 input capture

input/out put com pare output/PWM

output pins.

Section 1 Overview

Rev. 3.00 Mar 17, 2006 page 18 of 926

REJ09B0283-0300

Pin No.

Type Symbol

FP-144G

(H8S/2678

Group)

FP-144H

(H8S/2678R

Group) I/O Function

16-bit timer

pulse unit

(TPU)

TIOCA2

TIOCB2 50, 51 50, 51 Input/

output TGRA_2 and TGRB_2 input capture

input/out put com pare output/PWM

output pins.

TIOCA3

TIOCB3

TIOCC3

TIOCD3

52, 53,

54, 55 52, 53,

54, 55 Input/

output TGRA_3 to TGRD_3 input capture

input/out put com pare output/PWM

output pins.

TIOCA4

TIOCB4 56, 57 56, 57 Input/

output TGRA_4 and TGRB_4 input capture

input/out put com pare output/PWM

output pins.

TIOCA5,

TIOCB5 58, 59 58, 59 Input/

output TGRA_5 and TGRB_5 input capture

input/out put com pare output/PWM

output pins.

Programmable

pulse

generator

(PPG)

PO15 to

PO0 51 to 48,

46 to 43,

59 to 52

51 to 48,

46 to 43,

59 to 52

Output Pulse output pins.

8-bit timer TMO0

TMO1 83, 84 83, 84 Output Waveform output pins with output

compare functio n.

TMCI0

TMCI1 81, 82 81, 82 Input External event input pins.

TMRI0

TMRI1 60, 61 60, 61 Input Counter reset input pins.

Watchdog

timer (WDT) WDTOVF 37 37 Output Counter overflow signal output pin in

watchdog timer mode.

TxD2

TxD1

TxD0/

IrTxD

107, 138,

139 107, 138,

139 Output Data output pins.Serial commu-

nication

interface

(SCI)/smart

card interfac e

(SCI_0 with

IrDA function)

RxD2

RxD1

RxD0/

IrRxD

108, 135,

137 108, 135,

137 Input Data input pins .

SCK2

SCK1

SCK0

109, 133,

134 109, 133,

134 Input/

output Clock input/output pins.

Section 1 Overview

Rev. 3.00 Mar 17, 2006 page 19 of 926

REJ09B0283-0300

Pin No.

Type Symbol

FP-144G

(H8S/2678

Group)

FP-144H

(H8S/2678R

Group) I/O Function

A/D converter AN15 to

AN12,

AN7 to

AN0

130 to 127,

126 to 123,

120 to 117

130 to 127,

126 to 123,

120 to 117

Input Analog input pins for the A/D

converter.

ADTRG 110 110 Input Pin for input of an external trigger to

start A/D conversion.

D/A converter DA3 to

DA0 130, 129,

126, 125 130, 129,

126, 125 Output Analog input pins for the D/A

converter.

A/D converter,

D/A converter AVCC 122 122 Input The analog power-supply pin for the

A/D converter and D/A converter.

When the A/D converter and D/A

converter are not used, this pin

should be connected to the system

power supply (+3 V).

AVSS 131 131 Input The ground pin for the A/D

converter and D/A converter.

This pin should be connected to the

system power supply (0 V).

Vref 121 121 Input The reference voltage input pin for

the A/D converter and D/A

converter.

When the A/D converter and D/A

converter are not used, this pin

should be connected to the system

power supply (+3 V).

I/O ports P17 to

P10 51 to 48,

46 to 43 51 to 48,

46 to 43 Input/

output Eight input/output pins.

P27 to

P20 59 to 52 59 to 52 Input/

output Eight input/output pins.

P35 to

P30 133 to 135,

137 to 139 133 to 135,

137 to 139 Input/

output Six input/output pins.

P47 to

P40 126 to 123,

120 to 117 126 to 123,

120 to 117 Input Eight input pins.

Section 1 Overview

Rev. 3.00 Mar 17, 2006 page 20 of 926

REJ09B0283-0300

Pin No.

Type Symbol

FP-144G

(H8S/2678

Group)

FP-144H

(H8S/2678R

Group) I/O Function

I/O ports P57 to

P54 130 to 127 130 to 127 Input Four input pins.

P53 to

P50 110 to 107 110 to 107 Input/

output Four input/output pins.

P65 to

P60 84 to 81,

61, 60 84 to 81,

61, 60 Input/

output Six input/output pins.

P75 to

P70 42 to 40,

36 to 34 42 to 40,

36 to 34 Input/

output Six input/output pins.

P85 to

P80 4 to 2,

142 to 140 4 to 2,

142 to 140 Input/

output Six input/output pins.

PA7 to

PA0 32 to 27,

25, 24 32 to 27,

25, 24 Input/

output Eight input/output pins.

PB7 to

PB0 23 to 20,

18 to 15 23 to 20,

18 to 15 Input/

output Eight input/output pins.

PC7 to

PC0 14, 13,

11 to 6 14, 13,

11 to 6 Input/

output Eight input/output pins.

PD7 to

PD0 72 to 75,

77 to 80 72 to 75,

77 to 80 Input/

output Eight input/output pins.

PE7 to

PE0 63 to 66,

68 to 71 63 to 66,

68 to 71 Input/

output Eight input/output pins.

PF7 to

PF0 95,

91 to 85 95,

91 to 85 Input/

output Eight input/output pins.

PG6 to

PG0 115 to 113,

104 to 101 115 to 113,

104 to 101 Input/

output Seven input/output pins.

PH3 to

PH0 112, 111,

106, 105 112, 111,

106, 105 Input/

output Four input/output pins.

Section 2 CPU

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REJ09B0283-0300

Section 2 CPU

The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that

is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit

general registers, can address a 1 6-Mbyte linear address space, and is ideal for realtime control.

This section describes the H8S/2600 CPU. The usable modes and address spaces differ depending

on the product. For details on each product, refer to section 3, MCU Operating Modes.

2.1 Features

• Upward-compatible with H8 /300 and H8/300H CPUs

Can execute H8/300 and H8/300 H object programs

• General-register architecture

Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers

• Sixty-nine basic instructions

8/16/32-b it ar ithmetic and logic in str uctions

Multiply and divide instructio ns

Powerful bit-manipulatio n instructions

Multiply-and-accumulate instr uction

• Eight addressing modes

Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]

Immediate [#xx:8, #xx: 16, or #xx: 3 2]

Program-counter relative [@(d:8,PC) or @(d:16,PC)]

Memory indirect [@@aa:8]

• 16-Mbyte address space

Program: 16 Mbytes

Data: 16 Mbytes

• High-speed operation

All frequently-u sed instructions execute in one or two states

8/16/32-bit register-register add/subtract: 1 state

8 × 8-bit register-register multiply : 3 states

16 ÷ 8-bit register-register divide: 12 states

CPUS260A_020020020400

Section 2 CPU

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REJ09B0283-0300

16 × 16-bit register-register multiply: 4 states

32 ÷ 16-bit register-register divide: 20 states

• Two CPU operating modes

Normal mode*

Advanced mode

• Power-down state

Transition to power-down state by SLEEP instruction

CPU clock speed selection

Note: * Normal mo d e is not av ailable in this LSI.

2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU

The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.

• Register configuration

The MAC register is supported only by the H8S/2600 CPU.

• Basic instructions

The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the

H8S/2600 CPU.

• The number of execution states of the MULXU and MULXS instructions

Execution States

Instruction Mnemonic H8S/2600 H8S/2000

MULXU MULXU.B Rs, Rd 3 12

MULXU.W Rs, ERd 4 20

MULXS MULXS.B Rs, Rd 4 13

MULXS.W Rs, ERd 5 21

In addition, there are differences in addr ess space, CCR and EXR register fun ctions, power-down

modes, etc., depending on the model.

2.1.2 Differences from H8/300 CPU

In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements.

Section 2 CPU

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REJ09B0283-0300

• More general registers and control registers

Eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been

added.

• Expanded address space

Normal mode supports the same 64-kbyte address space as the H8/300 CPU.

Advanced mode supports a maximum 16-Mbyte address space.

• Enhanced addressing

The addressing modes have been enhanced to make effective use of the 16-Mbyte address

space.

• Enhanced instructions

Addressing modes of bit-manipulation instructions have been enhanced.

Signed multiply and divide in structions have be en added.

A multiply-and-accumulate in struction has been added.

Two-bit shift and rotate instructions have been added.

Instructio ns for saving and restoring multiple registers have been added.

A test and set instruction has been added.

• Higher speed

Basic instructions execute twice as fast.

Note: Normal mode is not av ailable in this LSI.

2.1.3 Differences from H8/300H CPU

In comparison to the H8/300H CPU, the H8S/2600 CPU has the following enhancements.

• Additional control register

One 8-bit and two 32-bit control registers have been added.

• Enhanced instructions

Addressing modes of bit-manipulation instructions have been enhanced.

A multiply-and-accumulate in struction has been added.

Two-bit shift and rotate instructions have been added.

Instructio ns for saving and restoring multiple registers have been added.

A test and set instruction has been added.

• Higher speed

Basic instructions execute twice as fast.

Section 2 CPU

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REJ09B0283-0300

2.2 CPU Operating Modes

The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a

maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address

space. The mode is selected by the mode pins.

2.2.1 Normal Mode

The exception vector table and stack have the same structure as in the H8/300 CPU.

• Address Space

The H8S/2600 CPU provides linear access to a maximum 64-kbyte address space.

• Extended Registers (En)

The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit

segments of 32-bit registers.

When En is used as a 16-bit register it can contain any value, even when the corresponding

general register (Rn) is used as an address register. If the general register is referenced in the

carry or borrow occurs, however, the valu e in the corresponding extended register (En) will be

affected.

• Instruction Set

All instructions and addressing modes can be used. Only the lower 16 bits of effective

addresses (EA) are valid.

• Exception Vector Table and Memory Indirect Branch Addresses

In normal mode the top area starting at H'0000 is allocated to the exception vector table. One

branch address is stored per 16 bits. The exception vector table in normal mode is shown in

figure 2.1. For details of the exception vector table, see section 4, Exception Handling.

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions

uses an 8-bit absolute address included in the instruction code to specify a memory op erand

that contains a branch address. In normal mode the operand is a 16-bit word operand,

providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000

to H'00FF. Note that this area is also used for the exception vector table.

• Stack Structure

When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC,

condition-code register (CCR), and extended control register (EXR) are pushed onto the stack

in exception handling, they are stored as shown in figure 2.2. EXR is not pushed onto the stack

in interrupt control mode 0. For details, see section 4, Exception Handling.

Note: Normal mode is not av ailable in this LSI.

Section 2 CPU

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REJ09B0283-0300

H'0000

H'0001

H'0002

H'0003

H'0004

H'0005

H'0006

H'0007

H'0008

H'0009

H'000A

H'000B

Reset exception vector

(Reserved for system use)

Exception vector 1

Exception vector 2

Exception

vector table

Figure 2.1 Exception Vector Table (Normal Mode)

(16 bits) EXR*

Reserved*

CCR

CCR*

(16 bits)

SP SP

(SP*

1. When EXR is not used, it is not stored on the stack.

2. SP when EXR is not used.

3. lgnored when returning.

Notes:

(b) Exception Handling(a) Subroutine Branch

)

Figure 2.2 Stack Structure in Normal Mode

Section 2 CPU

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REJ09B0283-0300

2.2.2 Advanced Mode

• Address Space

Linear access is provided to a 16-Mbyte maximum address space.

• Extended Registers (En)

The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit

segments of 32-bit registers or address registers.

• Instruction Set

All instructions and addressing modes can be used.

• Exception Vector Table and Memory Indirect Branch Addresses

In advanced mode the top area starting at H'00000000 is allocated to the exception vector table

in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in

the lower 24 bits (figure 2.3). For details of the exception vector table, see section 4, Exception

Handling.

H'00000000

H'00000003

H'00000004

H'0000000B

H'0000000C

H'00000010

H'00000008

H'00000007

Reserved

Reset exception vector

(Reserved for system use)

Exception vector table

Exception vector 1

Figure 2.3 Exception Vector Table (Advanced Mode)

Section 2 CPU

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REJ09B0283-0300

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions

uses an 8-bit absolute address included in the instruction code to specify a memory operand

that contains a branch address.

In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch

address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch

addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of

this range is also used for the exception vector table.

• Stack Structure

In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine

call, and the PC, conditio n-code register (CCR), a nd extended control register (E X R) are

pushed onto the stack in exception handling, they are stored as shown in figure 2.4. EXR is not

pushed onto the stack in interrupt control mode 0. For details, see section 4, Excep tion

Handling.

(24 bits)

EXR*

Reserved*

CCR

(24 bits)

SP SP

(SP*

Reserved

(a) Subroutine Branch (b) Exception Handling

Notes: 1. When EXR is not used, it is not stored on the stack.

2. SP when EXR is not used.

3. Ignored when returning.

)

Figure 2.4 Stack Structure in Advanced Mode

Section 2 CPU

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REJ09B0283-0300

2.3 Address Space

Figure 2.5 shows a memory map of the H8S/2600 CPU. The H8S/2600 CPU provides linear

access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte

(architecturally 4-Gbyte) address space in advanced mode. The usable modes and addr ess spaces

differ depending on the product. For details on each product, refer to section 3, MCU Operating

Modes.

Note: No r mal mode is not available in this LSI.

H'0000

H'FFFF

Note: * Normal mode cannot be used in this LSI.

H'00000000

H'FFFFFFFF

H'00FFFFFF

64 kbytes 16 Mbytes

Cannnot be

used in this LSI

Program area

Data area

(b) Advanced Mode(a) Normal Mode*

Figure 2.5 Memory Map

Section 2 CPU

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REJ09B0283-0300

2.4 Registers

The H8S/2600 CPU has the internal registers shown in figure 2.6. There are two types of registers:

general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit

extended register ( EXR), an 8-bit condition code register (CCR) , and a 64-bit multiply-accumulate

TI2I1I0

EXR

76543210

MACH

MACL

MAC

63 3241

31 0

15 0 7 0 7 0

R0H

R1H

R2H

R3H

R4H

R5H

R6H

R7H

R0L

R1L

R2L

R3L

R4L

R5L

R6L

R7L

EXR

I2 to I0

CCR

: Stack pointer

: Program counter

: Extended register

: Trace bit

: Interrupt mask bits

: Condition-code register

: Interrupt mask bit

: User bit or interrupt mask bit*

: Half-carry flag

: User bit

: Negative flag

: Zero flag

: Overflow flag

: Carry flag

: Multiply-accumulate register

ER0

ER1

ER2

ER3

ER4

ER5

ER6

ER7 (SP)

IUIHUNZVC

CCR

76543210

MAC

General Registers (Rn) and Extended Registers (En)

Control Registers (CR)

Legend:

Sign extension

----

Note: * UI cannot be used as an interrupt mask bit in this LSI.

Figure 2.6 CPU Registers

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REJ09B0283-0300

2.4.1 General Registers

The H8S/2600 CPU has eight 32-bit general registers. These general registers are all functionally

alike and can be used as bo th address registers and data registers. When a general register is used

as a data register, it can be accessed as a 32-b it, 16- bit, or 8-bit register. Figure 2.7 illustrates the

usage of the general registers. When the general registers are used as 32-bit registers or address

registers, they ar e designated by the letters ER (ER0 to ER7).

The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R

(R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit

registers. The E registers (E0 to E7) are also referred to as extended registers.

The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and

RL (R0L to R7L). These registers are functionally equivalent, prov iding a maximum sixteen 8-bit

registers.

The usage of each register can be selected independently.

General register ER7 has the function of stack pointer (SP) in addition to its general-register

function, and is used implicitly in exception handling and subroutine calls. Figure 2.8 shows th e

stack.

• Address registers

• 32-bit registers • 16-bit registers • 8-bit registers

ER registers

(ER0 to ER7)

E registers (extended registers)

(E0 to E7)

R registers

(R0 to R7)

RH registers

(R0H to R7H)

RL registers

(R0L to R7L)

Figure 2.7 Usage of General Registers

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REJ09B0283-0300

SP (ER7)

Free area

Stack area

Figure 2.8 Stack

2.4.2 Program Counter (PC)

This 24-b it coun ter indicates th e address of the next instruction the CPU will execute. Th e length

of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an

instruction is fetched, the least significant PC bit is re garded as 0. )

2.4.3 Extended Register (EX R)

EXR is an 8-bit register that can be manipulated b y the LDC, STC, ANDC, ORC, and XORC

instructions. When these instructions except for the STC instruction is executed, all interrup ts

including NMI will be masked for thr ee states after ex ecution is completed.

Bit Bit Name Initial Value R/W Description

7 T 0 R/W Trace Bit

When this bit is set to 1, a trace exception is

started each time an instruction is executed.

When this bit is cleared to 0, instructions are

executed in sequence.

6 to 3 —All 1 —Reserved

These bits are always read as 1.

R/W

These bits designate the interrupt mask level (0

to 7). For detail s, refer to section 5, Interrupt

Controller.

Section 2 CPU

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REJ09B0283-0300

2.4.4 Condition-Code Register (CCR)

This 8-bit r egister contains internal CPU statu s information , including an interrupt ma sk bit (I ) and

half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.

Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC

instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch

(Bcc) instructions.

Bit Bit Name Initial Value R/W Description

7 I 1 R/W Interrupt Mask Bit

Masks interrupts other than NMI when set to 1.

NMI is accepted regardless of the I bit setting.

The I bit is set to 1 by hardware at the start of an

exception-handling sequence. For details, refer to

section 5, Interrupt Controller.

6 UI Undefined R/W User Bit or Interrupt Mask Bit

Can be written and read by software using the

LDC, STC, ANDC, ORC, and XORC instructions.

This bit cannot be used as an interr upt mask bit

in this LSI.

5 H Undefined R/W Half-Carry Flag

When the ADD.B, ADDX.B, SUB.B, SUBX.B,

CMP.B, or NEG.B instruction is executed, this

flag is set to 1 if there is a carry or borrow at bit 3,

and cleared to 0 otherwise. When the ADD.W,

SUB.W, CMP.W, or NEG.W instruction is

executed, the H flag is set to 1 if there is a carry

or borrow at bit 11, and cleared to 0 otherwise.

When the ADD.L, SUB.L, CMP.L, or NEG.L

instruct ion is exe cut ed, the H flag is set to 1 if

there is a carry or borrow at bi t 27, and cleared to

0 otherwise.

4 U Undefined R/W User Bit

Can be written and read by software using the

LDC, STC, ANDC, ORC, and XORC instructions.

3 N Undefined R/W Negative Flag

Stores the value of the most significant bit of data

as a sign bit.

Section 2 CPU

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REJ09B0283-0300

Bit Bit Name Initial Value R/W Description

2 Z Undefined R/W Zero Flag

Set to 1 to indicate zero data, and cleared to 0 to

indicate non-zero data.

1 V Undefined R/W Overflow Flag

Set to 1 when an arithmetic overflow oc curs, and

cleared to 0 otherwise.

0 C Undefined R/W Carry Flag

Set to 1 when a carry occurs, and cleared to 0

otherwise. Us ed by:

• Add instructions, to indicate a carry

• Subtract instructions, to indicate a borrow

• Shift and rotate instructions, to indicate a

carry

The carry flag is also used as a bit accumulator

by bit manipulation instructions.

2.4.5 Multiply-Accumulate Register (MAC)

This 64-b it register stores the results of multiply -and-accumulate operation s. It consists of two 32-

bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the upper bits are

a sign extension.

2.4.6 Initial Values of CPU Internal Registers

When the reset exception handling loads the start address from the vector address, PC is

initialized, the T bit in EXR is cleared to 0, and the I bits in EXR and CCR are set to 1 . However,

the gener a l r egisters and the other CCR bits are not initialized. The initial value of SP (E R7) is

undefined. SP should therefore be initialized by using the MOV.L instruction immediately after a

reset.

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2.5 Data Formats

The H8S/2600 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit

(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2,

…, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two

digits of 4-bit BCD data.

2.5.1 General Register Data Formats

Figure 2.9 shows the data fo rmats in general registers.

MSB LSB

7043

Don't care

7043

Don't care

65432710

Don't care 65432710

Don't care

RnH

RnL

RnH

RnL

RnH

RnL

Data Type Register Number Data Format

Byte data

4-bit BCD data

1-bit data

Upper Lower

Figure 2.9 General Register Data Formats (1)

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15 0

MSB LSB

15 0

MSB LSB

31 16

MSB

15 0

LSB

En Rn

ERn

RnH

RnL

MSB

LSB

: General register ER

: General register E

: General register R

: General register RH

: General register RL

: Most significant bit

: Least significant bit

Data Type Data FormatRegister Number

Word data

Longword data

Legend:

ERn

Figure 2.9 General Register Data Formats (2)

Section 2 CPU

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2.5.2 Memory Data Formats

Figure 2.10 shows the data formats in memory. The H8S/2600 CPU can access word data and

longword data in memory, but word or longword data must begin at an even address. If an attempt

is made to access word or longword data at an odd address, no address error occurs but the least

significant bit of the address is regarded as 0, so the access starts at the preceding address. This

also applies to instruction fetches.

When ER7 is used as an address register to access the stack, the operand size should be word size

or longword size.

76 543210

MSB LSB

MSB

LSB

Data Type Address

1-bit data

Byte data

Word data

Address L

Address 2M

Address 2M+1

Longword data Address 2N

Address 2N+1

Address 2N+2

Address 2N+3

Data Format

Figure 2.10 Memory Data Formats

Section 2 CPU

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REJ09B0283-0300

2.6 Instruction Set

The H8S/2600 CPU has 69 types of instructions. The instructions are classified by function in

table 2.1.

Table 2.1 Instruction Classification

Function Instructions Size Types

Data transfer MOV B/W/L 5

POP*1, PUSH*1W/L

LDM, STM L

MOVFPE*3, MOVTPE*3B

ADD, SUB, CMP, NEG B/W/L 23Arithmetic

operations ADDX, SUBX, DAA, DAS B

INC, DEC B/W/L

ADDS, SUBS L

MULXU, DIVXU, MULXS, DIVXS B/W

EXTU, EXTS W/L

TAS*4B

MAC, LDMAC, STMAC, CLRMAC —

Logic operations AND, OR, XOR, NOT B/W/L 4

Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR B/W/L 8

Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,

BIAND, BOR, BIOR, BXOR, BIXOR B14

Branch Bcc*2, JMP, BSR, JSR, RTS — 5

System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP — 9

Block data transfer EEPMOV — 1

Total: 69

Legend:

B: Byte

W: Word

L: Longword

Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn,

@-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L

ERn, @-SP.

2. Bcc is the general name for conditional branch instructions.

3. Cannot be us ed in this LSI.

4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

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2.6.1 Table of Instructions Classified by Function

Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in

tables 2.3 to 2.10 is defined below.

Table 2.2 Operation Notation

Symbol Description

Rd General register (destination)*

Rs General register (source)*

Rn General register*

ERn General register (32-bit register)

MAC Multiply-accumulate register (32-bit register)

(EAd) Destination operand

(EAs) Source operand

EXR Extended register

CCR Condition-code register

N N (negative) flag in CCR

Z Z (zero) flag in CCR

V V (overflow) flag in CCR

C C (carry) flag in CCR

PC Program counter

SP Stack pointer

#IMM Immediate data

disp Displacement

+ Addition

–Subtraction

×Multiplication

÷Division

∧Logical AND

∨Logical OR

⊕Logical exclusive OR

→Move

¬NOT (logical complement)

:8/:16/:24/:32 8-, 16-, 24-, or 32-bit length

Note: *General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0

to R7, E0 to E7), and 32-bit registers (ER0 to ER7).

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Table 2.3 Data Transfer Instructions

Instruction Size*Function

MOV B/W/L (EAs) → Rd, Rs → (EAd)

Moves data between two general registers or between a general register

and memory, or moves immediate data to a general register.

MOVFPE B Cannot be used in this LSI.

MOVTPE B Cannot be used in this LSI.

POP W/L @SP+ → Rn

Pops a general register from the stack. POP.W Rn is identical to MOV.W

@SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn.

PUSH W/L Rn → @–SP

Pushes a general register onto the stack. PUSH.W Rn is identical to

MOV.W Rn, @ –SP. PUSH.L ERn is identical to MOV.L ERn, @–SP.

LDM L @SP+ → Rn (register list)

Pops two or more general registers from the stack.

STM L Rn (register list) → @–SP

Pushes two or more general registers onto the stack.

Note: *Size refers to the operand size.

B: Byte

W: Word

L: Longword

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Table 2.4 Arithmetic Operations Instructions (1)

Instruction Size*Function

ADD

SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd

Performs addition or subtraction on data in two general registers, or on

immediate data and data in a general register. (Immediate byte data

cannot be subtracted from byte data in a general register. Use the SUBX

or ADD instructio n.)

ADDX

SUBX B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd

Performs addition or subtraction with carry or borrow on byte data in two

general registers, or on immediate data and data in a general register.

INC

DEC B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd

Increments or decrements a general register by 1 or 2. (Byte operands

can be incremented or decrem en ted by 1 only.)

ADDS

SUBS L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd

Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.

DAA

DAS B Rd (decimal adjust) → Rd

Decimal-adjusts an addition or subtraction result in a general register by

referring to the CCR to produce 4-bit BCD data.

MULXU B/W Rd × Rs → Rd

Performs unsigned multiplication on data in two general registers:

either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.

MULXS B/W Rd × Rs → Rd

Performs signed multiplication on data in two general registers:

either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.

DIVXU B/W Rd ÷ Rs → Rd

Performs unsigned division on data in two general registers:

either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or

32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder.

Note: *Size refers to the operand size.

B: Byte

W: Word

L: Longword

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Table 2.4 Arithmetic Operations Instructions (2)

Instruction Size*1Function

DIVXS B/W Rd ÷ Rs → Rd

Performs signed division on data in two general registers:

either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or

32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder.

CMP B/W/L Rd – Rs, Rd – #IMM

Compares data in a general register with data in another general register

or with immediate data, and sets CCR bits acco rding to the result.

NEG B/W/L 0 – Rd → Rd

Takes the two's complement (arithmetic complement) of data in a

general register.

EXTU W/L Rd (zero extension) → Rd

Extends the lower 8 bits of a 16-bit register to word size, or the lower 16

bits of a 32-bit register to longword size, by padding with zeros on the

left.

EXTS W/L Rd (sign extension) → Rd

Extends the lower 8 bits of a 16-bit register to word size, or the lower 16

bits of a 32-bit register to longword si ze, by extend ing the sign bit.

TAS*2B@ERd – 0, 1 → (<bit 7> of @ERd)

Tests memory contents, and sets the most significant bit (bit 7) to 1.

MAC — (EAs) × (EAd) + MAC → MAC

Performs signed multiplication on memory contents and adds the result

to the multiply-accumulate register. The following operations can be

performed:

16 bits × 16 bits + 32 bits → 32 bits, saturating

16 bits × 16 bits + 42 bits → 42 bits, non-saturating

CLRMAC —0 → MAC

Clears the multiply-accumulate register to zero.

LDMAC

STMAC LRs → MAC, MAC → Rd

Transfers data between a general register and a multiply-accumulate

Notes: 1.Size refers to the operand size.

B: Byte

W: Word

L: Longword

2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

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Table 2.5 Logic Operations Instructions

Instruction Size*Function

AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd

Performs a logical AND operation on a general register and another

general register or immediate data.

OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd

Performs a logical OR operation on a general register and another

general register or immediate data.

XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd

Performs a logical exclusive OR operation on a general register and

another general register or immediate data.

NOT B/W/L ¬ (Rd) → (Rd)

Takes the one's complement (logical complement) of general register

contents.

Note: *Size refers to the operand size.

B: Byte

W: Word

L: Longword

Table 2.6 Shift Instructions

Instruction Size*Function

SHAL

SHAR B/W/L Rd (shift) → Rd

Performs an arithmetic shift on general register contents.

1-bit or 2-bit shift is possible.

SHLL

SHLR B/W/L Rd (shift) → Rd

Performs a logical shift on general register contents.

1-bit or 2-bit shift is possible.

ROTL

ROTR B/W/L Rd (rotate) → Rd

Rotates general register contents.

1-bit or 2-bit rotation is possible.

ROTXL

ROTXR B/W/L Rd (rotate) → Rd

Rotates general register contents through the carry flag.

1-bit or 2-bit rotation is possible.

Note: *Size refers to the operand size.

B: Byte

W: Word

L: Longword

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Table 2.7 Bit Manipulation In structions (1 )

Instruction Size*Function

BSET B 1 → (<bit-No.> of <EAd>)

Sets a specified bit in a general register or memory operand to 1. The bit

number is specified by 3-bit immediate data or the lower three bits of a

general register.

BCLR B 0 → (<bit-No.> of <EAd>)

Clears a specified bit in a general register or memory operand to 0. The

bit number is specified by 3-bit immediate data or the lower three bits of a

general register.

BNOT B ¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)

Inverts a specified bit in a general register or memory operand. The bit

number is specified by 3-bit immediate data or the lower three bits of a

general register.

BTST B ¬ (<bit-No.> of <EAd>) → Z

Tests a specified bit in a general register or memory operand and sets or

clears the Z flag accord ing ly. The bit number is spe cif ied by 3-bi t

immediate data or the lower three bits of a general register.

BAND

BIAND

C ∧ (<bit-No.> of <EAd>) → C

ANDs the carry flag with a specified bit in a general register or memory

operand and stores the result in the carry flag.

C ∧ ¬ (<bit-No.> of <EAd>) → C

ANDs the carry flag with the inverse of a specified bit in a general

The bit number is specified by 3-bit immediate data.

BOR

BIOR

C ∨ (<bit-No.> of <EAd>) → C

ORs the carry flag with a specified bit in a general register or memory

operand and stores the result in the carry flag.

C ∨ ¬ (<bit-No.> of <EAd>) → C

ORs the carry flag with the inverse of a specified bit in a general register

or memory operand and stores the result in the carry flag.

The bit number is specified by 3-bit immediate data.

Note: *Size refers to the operand size.

B: Byte

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Table 2.7 Bit Manipulation In structions (2 )

Instruction Size*Function

BXOR

BIXOR

C ⊕ (<bit-No.> of <EAd>) → C

Exclusive-O Rs the carry flag with a specif ied bit in a genera l regist er or

memory operand and stores the result in the carry flag.

C ⊕ ¬ (<bit-No.> of <EAd>) → C

Exclusive-ORs the carry flag with the inverse of a specified bit in a

general register or memory operand and stores the result in the carry

flag.

The bit number is specified by 3-bit immediate data.

BLD

BILD

(<bit-No.> of <EAd>) → C

Transfers a specified bit in a general register or memory operand to the

carry flag.

¬ (<bit-No.> of <EAd>) → C

Transfers the inverse of a specified bit in a general register or memory

operand to the carry flag.

The bit number is specified by 3-bit immediate data.

BST

BIST

C → (<bit-No.> of <EAd>)

Transfers the carry flag value to a specified bit in a general register or

memory operand.

¬ C → (<bit-No.> of <EAd>)

Transfers the inverse of the carry flag value to a specified bit in a general

The bit number is specified by 3-bit immediate data.

Note: *Size refers to the operand size.

B: Byte

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Table 2.8 Branch Instructions

Instruction Size Function

Bcc —Branches to a specified address if a specified condition is true. The

branching conditions are listed below.

Mnemonic Description Condition

BRA (BT) Always (true) Always

BRN (BF) Never (false) Never

BHI High C ∨ Z = 0

BLS Low or same C ∨ Z = 1

BCC (BHS) Carry clear

(high or same) C = 0

BCS (BLO) Carry set (low) C = 1

BNE Not equal Z = 0

BEQ Equal Z = 1

BVC Overflow clea r V = 0

BVS Overflow set V = 1

BPL Plus N = 0

BMI Minus N = 1

BGE Greater or equal N ⊕ V = 0

BLT Less than N ⊕ V = 1

BGT Greater than Z ∨ (N ⊕ V) = 0

BLE Less or equal Z ∨ (N ⊕ V) = 1

JMP —Branches unconditionally to a specified address.

BSR —Branches to a subroutine at a specified address.

JSR —Branches to a subroutine at a specified address.

RTS —Returns from a subroutine.

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Table 2.9 System Control Instructions

Instruction Size*Function

TRAPA —Starts trap-instruction exception handling.

RTE —Returns from an exception-handling routine.

SLEEP —Causes a transition to a power-down state.

LDC B/W (EAs) → CCR, (EAs) → EXR

Moves the contents of a general register or memory, or immediate data

to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size

transfers are performed between them and memory. The upper 8 bits are

valid.

STC B/W CCR → (EAd), EXR → (EAd)

Transfers CCR or EXR contents to a general register or memory.

Although CCR and EXR are 8-bit registers, word-size transfers are

performed between them and memory . The upper 8 bits are valid.

ANDC B CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR

Logically ANDs the CCR or EXR contents with immediate data.

ORC B CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR

Logically ORs the CCR or EXR contents with immediate data.

XORC B CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR

Logically exclusive-ORs the CCR or EXR contents with immediate data.

NOP —PC + 2 → PC

Only increments the program counter.

Note: *Size refers to the operand size.

B: Byte

W: Word

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Table 2.10 Block Data Transfer Instructions

Instruction Size Function

EEPMOV.B

EEPMOV.W

—

if R4L ≠ 0 then

Repeat @ER5+ → @ER6+

R4L–1 → R4L

Until R4L = 0

else next;

if R4 ≠ 0 then

Repeat @ER5+ → @ER6+

R4–1 → R4

Until R4 = 0

else next;

Transfers a data block. Starting from the address set in ER5, transfers

data for the number of bytes set in R4L or R4 to the address location set

in ER6.

Execution of the next instruction begins as soon as the transfer is

completed.

2.6.2 Basic Instruction Formats

The H8S/2600 Series instructions consist of 2-byte (1-word) units. An instruction consists of an

operation field (op), a register field (r), an effective address extension (EA), and a condition field

(cc).

Figure 2.11 shows examples of instruction formats.

• Operation Field

Indicates the function of the instruction, the addressing mode, and the operation to be carried

out on the operand. The operation field always includes the first four bits of the instruction.

Some instructions have two operation fields.

• Register Field

Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or

4 bits. Some instructions have two register fields. Some have no register field.

• Effective Addr ess Extension

8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.

• Condition Field

Specifies the branching condition of Bcc instructions.

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op rn rm

NOP, RTS, etc.

ADD.B Rn, Rm, etc.

MOV.B @(d:16, Rn), Rm, etc.

rn rm

EA (disp)

op cc EA (disp) BRA d:16, etc.

(1) Operation field only

(2) Operation field and register fields

(3) Operation field, register fields, and effective address extension

(4) Operation field, effective address extension, and condition field

Figure 2.11 Instruction Formats (Examples)

2.7 Addressing Modes and Effective Address Calculation

The H8S/2600 CPU supports the eight addressing modes listed in table 2.11. The usable address

modes are different in each instruction.

Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer

instructions can use all addressing modes except prog ram-counter relative and memory indirect.

Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to

specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or

immediate (3-bit) addressing mode to specify a bit number in the operand.

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Table 2.11 Addressing Modes

No. Addressing Mode Symbol

1 Register direct Rn

2 Register indirect @ERn

3 Register indirect with displacement @(d:16,ERn)/@(d:32,ERn)

4 Register indirect with post-increment

@–ERn

5 Absolute address @aa:8/@aa:16/@aa:24/@aa:32

6 Immediate #xx:8/#xx:16/#xx:32

7 Program-counter relative @(d:8,PC)/@(d:16,PC)

8 Memory indirect @@aa:8

2.7.1 Register Direct—Rn

The register field of the instruction code specifies an 8-, 16-, or 32-bit general register containing

the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to

E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.

2.7.2 Register Indirect—@ERn

The register field of the instruction code specifies an address register (ERn) which contains the

address of the operand on memory. If the address is a program instruction address, the lower 24

bits are valid and the upper 8 bits are all assumed to be 0 (H'00).

2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)

A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn)

specified by the register field of the instruction code, and the sum gives the address of a memory

operand. A 16-bit displacement is sign-extended when added.

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2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn

specifies an address register (ERn) which contains the address of a memory operand. After the

operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the

address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for

longword transfer instruction. For word or longword transfer instruction, the register value should

be even.

address register (ERn) specified by the register field in the instruction code, and the result

becomes the address of a memory operand. The result is also stored in the address register. Th e

value subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer

instruction. For word or longword transfer instruction, the register value should be even.

2.7.5 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32

The instruction code contains the absolute address of a memory operand. The absolute address

may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long

(@aa:32). Table 2.12 indicates the accessible absolute address ranges.

To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits

(@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF).

For a 16-bit abso lute address, the upper 16 bits are a sign extension. A 32-bit absolute address can

access the entire address space.

A 24-bit absolute address (@aa:24) indicates the address of a prog ram instruction. The upper 8

bits are all assumed to be 0 (H'00).

Table 2.12 Absolute Address Access Ranges

Absolute Address Normal Mode*Advanced Mode

Data address 8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF

16 bits (@aa:16) H'0000 to H'FFFF H'000000 to H'007FFF,

H'FF8000 to H'FFFFFF

32 bits (@aa:32) H'000000 to H'FFFFFF

Program instruction

address 24 bits (@aa:24)

Note: *Not available in this LSI.

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2.7.6 Immediate—#xx:8, #xx:16, or #xx:32

The instruction code contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as

an operand.

The ADDS, SUBS, INC, and DEC instructions con tain immediate data implicitly. Some bit

manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit

number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a

vector address.

2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC)

This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in

the instruction code is sign-extended and added to the 24-bit PC contents to generate a branch

address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to

be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the

next instruction, so the po ssible branching range is −126 to +128 bytes ( –63 to +64 words) or

−32766 to +32768 bytes (−16383 to +16384 words) from the branch instruction. The resulting

value should be an even number.

2.7.8 Memory Indirect—@@aa:8

This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit

absolute address specifying a memory operand. This memory operand contains a branch address.

The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255

(H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode).

In normal mode the memory operand is a word operand and the branch address is 16 bits long. In

advanced mode the memory operand is a longword operand, the first byte of which is assumed to

be all 0 (H'00). Note that the first part of the address range is also the exception vector area. For

further details, refer to section 4, Exception Handling.

If an odd address is specified in word or longword memory access, or as a branch address, the

least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched

at the address preceding the specified address. (For further information, see section 2.5.2, Memory

Data Formats.)

Note: Normal mode is not available in this LSI.

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Specified

by @aa:8 Specified

by @aa:8

Branch address

Reserved

(a) Normal Mode

(a) Advanced Mode

Note: * Normal mode is not available in this LSI.

Figure 2.12 Branch Address Specification in Memory Indirect Mode

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2.7.9 Effective Address Calculation

Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal

mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address.

Note: Normal mode is not available in this LSI.

Table 2.13 Effective Address Calculation (1)

Offset

31 0

31 23

3Register indirect with displacement

@(d:16,ERn) or @(d:32,ERn)

op disp

op rn

31 0

Don't care

31 23

31 0

Don't care

31 0

disp

31 0

31 23

31 0

Don't care

31 23

31 0

Don't care

Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)

General register contents

Sign extension

pre-decrement

• Register indirect with post-increment @ERn+

• Register indirect with pre-decrement @-ERn

1, 2, or 4

Operand Size

Byte

Word

Longword

Operand is general register contents.

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Table 2.13 Effective Address Calcula tion (2)

op 31 23

31 0

Don't care

abs

@aa:8 7

H'FFFF

op 31 23

31 0

Don't care

@aa:16

@aa:24

@aa:32

abs 15

31 23

31 0

Don't care

31 23

31 0

Don't care

abs

op IMM

#xx:8/#xx:16/#xx:32

Addressing Mode and Instruction Format

Absolute address

Immediate

Effective Address Calculation Effective Address (EA)

Sign extension

Operand is immediate data.

31 23

Program-counter relative

@(d:8,PC)/@(d:16,PC)

Memory indirect @@aa:8

• Normal mode*

• Advanced mode

31 0

Don't care

23 0

disp

31 23

31 0

Don't care

disp

abs 31 0

abs

H'000000 7

15 31 23

31 0

Don't care 15

H'0016

op abs 31 0

abs

H'000000 7

Note: * Normal mode is not available in this LSI.

PC contents

Sign

extension

Memory contents

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2.8 Processing States

The H8S/2600 CPU has five main processing states: the reset state, exception handling state,

program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state

transitions.

• Reset Sta t e

The CPU and on-chip peripheral modules are all initialized and stop. When the RES input goes

low, all current processing stops and the CPU enters the reset state. All interrupts are masked

in the reset state. Reset exception handling starts when the RES signal changes from low to

high. For details, refer to section 4, Exception Handling.

The reset state can also be entered by a watchdog timer ov erflow.

• Exception-Handling State

The exception-handling state is a transient state that occurs when the CPU alters the normal

processing flow due to an exception source, such as, a reset, trace, interrupt, or trap instruction.

The CPU fetches a start address (vector) from the exception vector table and branches to that

address. For further details, refer to section 4, Exception Handling.

• Program Execution State

In this state the CPU executes program instructions in sequence.

• Bus-Released State

In a product which has a bus master other than the CPU, such as a direct memory access

controller (DMAC) and a data transfer controller (DTC), the bus-released state occurs when

the bus has been released in response to a bu s request from a bus master other than the CPU.

While the bus is re leased, the CPU halts op e r a tions.

• Program stop state

This is a power-down state in which the CPU stops operating. The program stop state occurs

when a SLEEP instruction is executed or the CPU enters hardware standby mode. For further

details, refer to section 22, Power-Down Mo des.

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Exception

handling state

Bus-released state

Software standby

mode

Reset state*

Sleep mode

Power down state*

Program execution state

End of bus request

Bus request

RES = High

STBY = High,

RES = Low

Reset state

Hardware standby

mode*

End of bus request

Bus request

Request for exception handling

Interrupt request

External interrupt request

SSBY = 0

SLEEP

instruction

SSBY = 1

SLEEP instruction

End of exception handling

Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low.

A transition can also be made to the reset state when the watchdog timer overflows.

2. In every state, when the STBY pin becomes low, the hardware standby mode is entered.

3. For details, refer to section 22, Power-Down Modes.

Figure 2.13 State Transitions

2.9 Usage Note

2.9.1 Usage Notes on Bit-wise Operation Instructions

The BSET, BCLR, BNOT, BST, and BIST instructions are used to read data in byte-wise, op er a te

the data in bit- wise, and write the result of the bit- wise operation in bit-wise again . Therefore,

special care is necessary to use these instructions for the registers and the ports that include write-

only bit.

The BCLR instruction can be used to clear the flags in the internal I/O registers to 0. In this time,

if it is obvious that the flag has been set to 1 in the interrupt handler, there is no need to read the

flag beforehand.

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Section 3 MCU Operati ng Mo des

3.1 Operating Mode Selection

The H8S/2678 Group has twelve operating modes (modes 1, 2, 4 to 7, and 10 to 15). All operating

modes are available for the flash memory version. Modes 1, 2, and 4 to 7 are available in the

masked ROM version. Modes 1 and 2 are available in the ROMless version.

The H8S/2678R Group has seven operating modes (modes 1 to 7). All operating modes are

available for the flash memory version. Modes 1 and 2 are available in the ROMless version.

These modes are determined by the mode pin (MD2 to MD0) setting.

Modes 1, 2, and 4 to 6 are externally expanded modes in which the CPU can access an external

memory and peripheral devices. In the externally expanded mode, each area can be switched to 8-

bit or 16-bit address space by the bus controller. If one of areas is set to 16-bit address space, the

bus mode is 16 bits. If all areas are set to 8-bit address space, the bus mode is 8 bits.

Mode 7 is a single-chip activation externally expanded mode in which the CPU can switch to

access an external memory and peripheral devices at the beginning of a program execution.

Modes 3, 10, and 11 are boot modes in which the flash memory can be accessed.

Modes 12 to 15 are user program modes in which the flash memory can be accessed.

For details, refer to section 19, Flash Memory (F-ZTAT Version).

Do not change the FWE and MD2 to MD0 pin settings during operation.

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Table 3.1 MCU Operating Mode Selection

External Data

Bus

MCU

Operating

Mode*1FWE*2MD2 MD1 MD0

CPU

Operating

Mode Description On-Chip

ROM Initial

Width Max.

Value

1 0 0 0 1 Advanced Expanded mode with

on-chip ROM disabled Di sabled 16 bits 16 bits

2 0 0 1 0 Advanced Expanded mode with

on-chip ROM disabled Di sabled 8 bits 16 bits

3 — 0 1 1 Advanced Boot mode Enabled — 16 bits

4 0 1 0 0 Advanced Expanded mode with

on-chip ROM enabled Enabled 8 bits 16 bits

5 0 1 0 1 Advanced Expanded mode with

on-chip ROM enabled Enabled 16 bits 16 bits

6 0 1 1 0 Advanced Expanded mode with

on-chip ROM enabled Enabled 8 bits 16 bits

7 0 1 1 1 Advanced Single-chip mode Enabled — 16 bits

10 1 0 1 0 Advanced Boot mode Enabled 8 bits 16 bits

11 1 0 1 1 Advanced Boot mode Enabled — 16 bits

12 1 1 0 0 A dvanced User program mode Enabled 8 bits 16 bits

13 1 1 0 1 A dvanced User program mode Enabled 16 bits 16 bits

14 1 1 1 0 A dvanced User program mode Enabled 8 bits 16 bits

15 1 1 1 1 A dvanced User program mode Enabled — 16 bits

Notes: 1. Modes 1, 2, 4 to 7, and 10 to 15 are supported in the H8S/26 78 Group.

Modes 1 to 7 are supported in the H8S/2678R Group.

2. The FWE pin setting is available only in the H8S/2678 Group. The FWE pin is not

available in the H8S/2678R Group.

3.2 Register Descriptions

The following registers are related to the operating mode.

• Mode control register (MDCR)

• System control register (SYSCR)

Section 3 MCU Operating Modes

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3.2.1 Mode Control Register (MDCR)

MDCR monitors the current operating mode of the H8S/2678 Group chip.

Bit Bit Name Initial Value R/W Descriptions

7 to

3— All 0 — Reserved

These bits are always read as 0 and cannot be

modified.

MDS2

MDS1

MDS0

—*

Mode Select 2 to 0

These bits indicate the input levels at pins MD2 to

MD0 (the current operating mode). Bits MDS2 to

MDS0 correspond to MD2 to MD0. MDS2 to MDS0

are read-only bits and they cannot be written to. The

mode pin (MD2 to MD0) input levels are latched into

these bits when MDCR is read. These latches are

canceled by a reset.

Note: *Determined by pins MD2 to MD0.

3.2.2 System Control Register (SYSCR)

SYSCR selects saturating o r non-saturating calculation for the MAC instruction, controls CPU

access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2), sets

external bus mode, and enables or disables on-chip RAM.

Bit Bit Name Initial Value R/W Descriptions

7, 6 — All 1 R/W Reserved

The initial value shou ld not be modi fied .

5 MACS 0 R/W MAC Saturation

Selects either saturating or non-saturating calculation

for the MAC instruction.

0: Non-saturating calculation for MAC instruction

1: Saturating calculation for MAC instruction

4— 0 R/WReserved

The initial value shou ld not be modi fied .

Section 3 MCU Operating Modes

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Bit Bit Name Initial Value R/W Descriptions

3 FLSHE 0 R/W Flash Memory Control Register Enable

Controls CPU access to the flash memory control

registers (FLMCR1, FLMCR2, EBR1, and EBR2). If

this bit is set to 1, the flash memory control registers

can be read/written to. If this bi t is cleared to 0, the

flash memory control registers are not selected. At

this time, the contents of the flash memory control

registers are maintained. This bit should be written to

0 other than flash memory version.

0: Flash memory control registers are not selected

for area H'FFFFC8 to H'FFFFCB

1: Flash memory control registers are selected for

area H'FFFFC8 to H'FFFFCB

2— 0 — Reserved

This bit is always read as 0 and cann ot be modif ied.

1 EXPE — R/W External Bus Mode Enable

Sets external bus mode.

In modes 1, 2, and 4 to 6, this bi t is fixed at 1 and

cannot be modified. In mode 3* and 7, this bit has an

initial value of 0, and can be read and written.

Writing of 0 to EXPE when its value is 1 should only

be carried out when an external bus cycle is not

being executed.

0: External bus disabled

1: External bus enabled

0 RAME 1 R/W RAM Enable

Enables or disables the on-chip RAM. The RAME bit

is initialized when the reset status is released.

0: On-chip RAM is disabled

1: On-chip RAM is enabled

Note: *Mode 3 is available only in the F-ZTAT version of H8S/2678R Group.

Section 3 MCU Operating Modes

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3.3 Operating Mode Descriptions

3.3.1 Mode 1

The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.

Ports A to C function as an address bus, ports D and E function as a data bus, and parts of ports F

to H carry bus control signals.

The initial bus mod e after a reset is 16 bits, with 1 6-bit access to all areas. However, if 8-bit access

is designated for all areas by the bus controller, the bus mode switches to 8 bits.

3.3.2 Mode 2

The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.

Ports A to C function as an address bus, ports D and E function as a data bus, and parts of ports F

to H carry bus control signals.

The initial bus mod e after a reset is 8 bits, with 8-bit access to all areas. However, if 16-bit access

is designated for all areas by the bus controller, the bus mode switches to 16 bits and port E

functions as a data bus.

3.3.3 Mode 3

This mode is a boot mode of the flash memory. This mode is the same as mode 7, except for

accessing to the flash memory. Mode 3 is available only in the flash memory version of the

H8S/2678R Group.

3.3.4 Mode 4

The CPU can access a 16-Mbyte address space in advanced mode. Th e on-chip ROM is enabled.

The program in the on-chip ROM connected to the first half of area 0 is executed.

Ports A to C function as inpu t ports immediately after a reset, but can be set to function as an

address bus. For details, see section 10, I/O Ports. Ports D and E function as a data bus, and parts

of ports F to H carry bus control signals.

The initial bus mod e after a reset is 8 bits, with 8-bit access to all areas. However, if 16-bit access

is designated for any area by the bus controller, the bus mode switches to 16 bits and port E

functions as a data bus. In the flash memory version, user program mode is entered by setting 1 to

the SWE bit of FLMCR1.

Section 3 MCU Operating Modes

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3.3.5 Mode 5

The CPU can access a 16-Mbyte address space in advanced mode. Th e on-chip ROM is enabled.

The program in an external ROM connected to the first half of area 0 is executed.

Ports A to C function as an address bus, ports D and E function as a data bus, and parts of ports F

to H carry bus control signals.

The initial bus mod e after a reset is 16 bits, with 1 6-bit access to all areas. However, if 8-bit access

is designated for any area by the bus controller, the bus mode switches to 8 bits.

In the flash memory version, user program mode is entered by setting 1 to the SWE bit of

FLMCR1.

3.3.6 Mode 6

The CPU can access a 16-Mbyte address space in advanced mode. Th e on-chip ROM is enabled.

The program in an external ROM connected to the first half of area 0 is executed.

Ports A to C function as an address bus, ports D and E function as a data bus, and parts of ports F

to H carry bus control signals.

The initial bus mod e after a reset is 8 bits, with 8-bit access to all areas. However, if 16-bit access

is designated for any area by the bus controller, the bus mode switches to 16 bits and port E

functions as a data bus.

In the flash memory version, user program mode is entered by setting 1 to the SWE bit of

FLMCR1.

3.3.7 Mode 7

The CPU can access a 16-Mbyte address space in advanced mode. Th e on-chip ROM is enabled,

and the chip starts up in single-chip mode. External addresses cannot be used in single-chip mode.

The initial mod e after a reset is single-chip mod e, with all I/O ports available for use as

input/outpu t ports. However, the mode can be switched to externally expanded mode by setting 1

to the EXPE bit of SYSCR and then the external address space is enabled. When externally

expanded mode is selected, all areas are in itially designated as 16-bit access space. The function of

pins in ports A to H is the same as in externally expanded mode with on-chip ROM enabled .

In the flash memory version, user program mode is entered by setting 1 to the SWE bit of

FLMCR1.

Section 3 MCU Operating Modes

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3.3.8 Mode 10

This is flash memory boot mode. This mode is the same as mode 4, except for accessing to the

flash memory. Mode 10 is available only in the flash memory version of the H8S/2678 Group.

3.3.9 Mode 11

This is flash memory boot mode. This mode is the same as mode 7, except for accessing to the

flash memory. Mode 11 is available only in the flash memory version of the H8S/2678 Group.

3.3.10 Mode 12

This is flash memory user program mode. This mode is the same as mode 4, except for accessing

to the flash memory. Mode 12 is available only in the flash memory version of the H8S/2678

Group.

3.3.11 Mode 13

This is flash memory user program mode. This mode is the same as mode 5, except for accessing

to the flash memory. Mode 13 is available only in the flash memory version of the H8S/2678

Group.

3.3.12 Mode 14

This is flash memory user program mode. This mode is the same as mode 6, except for accessing

to the flash memory. Mode 14 is available only in the flash memory version of the H8S/2678

Group.

3.3.13 Mode 15

This is flash memory user program mode. This mode is the same as mode 7, except for accessing

to the flash memory. Mode 15 is available only in the flash memory version of the H8S/2678

Group.

3.3.14 Pin Functions

The pin functions of ports A to H are switched according to operating mode. Table 3.2 shows the

pin functions in each operating mode.

Section 3 MCU Operating Modes

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Table 3.2 Pin Functions in Each Operat ing Mode

Port Mode

1Mode

2Mode

3Mode

4Mode

5Mode

6Mode

7Mode

10 Mode

11 Mode

12 Mode

13 Mode

14 Mode

PA7 to

PA5 P*/A P*/A P*/A P*/A P*/A P*/APort A

PA4 to

PA0 AA

P*/A P*/A

P*/A P*/A P*/A

P*/A

Port B A A P*/A P*/A A A P*/A P*/A P*/A P*/A A A P*/A

Port C A A P*/A P*/A A A P*/A P*/A P*/A P*/A A A P*/A

Port D D D P*/D P*/D D D P*/D D P*/D D D D P*/D

Port E P/D *P*/D P*/D P*/D P/D*P*/D P*/D P*/D P*/D P*/D P/D*P*/D P*/D

PF7,

PF6 P/C*P*/C P/C*P/C*P/C*P*/C P/C*P/C*P/C*

PF5,

PF4 CC CCC C CCC

PF3 P/C*P/C*P/C*P/C*P/C*P/C*P/C*P/C*P/C*

Port F

PF2 to

PF0 P*/C P*/C

P*/C

P*/C P*/C P*/C

P*/C

P*/C P*/C P*/C

P*/C

PG6 to

PG1 P*/C P*/C P*/C P*/C P*/C P*/C P*/C P*/C P*/CPort G

PG0 P/C*P/C*

P*/C

P*/C P/C*P/C*

P*/C

P/C*

P*/C

P*/C P/C*P/C*

P*/C

Port H P*/C P*/C P*/C P*/C P*/C P*/C P*/C P*/C P*/C P*/C P*/C P*/C P*/C

Legend: P: I/O port

A: Address bus output

D: Data bus input/output

C: Control signals, clock input/output

Notes: Modes 1, 2, 4 to 7, 10 to 15 are supported in H8S/2678 Group.

Modes 1 to 7 are supported in H8S/2678R Group.

*After reset

Section 3 MCU Operating Modes

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3.4 Memory Map in Each Operating Mode

Figures 3.1 to 3.6 show memory maps for each product.

H'000000

H'FFA000

H'FFC000

H'000000

H'FFA000

H'FFC000

H'FFFC00

External

address space

On-chip RAM/external

address space*

External address space

Internal I/O registers

External address space

Internal I/O registers

On-chip ROM

On-chip RAM/external

address space*

External address space

Internal I/O registers

External address space

Internal I/O registers

H'FFFFFF

H'FFFC00

H'FFFF00

H'FFFF20 H'FFFFFF

H'FFFF00

H'FFFF20

H'040000

External

address space

RAM: 8 kbytes

Modes 1 and 2

(expanded modes

with on-chip ROM disabled)

ROM: 256 kbytes

RAM: 8 kbytes

Mode 4

(expanded mode

with on-chip ROM enabled)

Note: * This area is specified as an external address area by clearing the RAME bit of SYSCR to 0.

Figure 3.1 H8S/2676 Memory Map (1)

Section 3 MCU Operating Modes

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H'000000

H'FFA000

H'FFC000

H'000000

H'FFA000

H'FFC000

H'FFFC00

External

address space

On-chip RAM/external

address space*

External

address space

External address space

Internal I/O registers

External address space

Internal I/O registers

On-chip ROM

On-chip RAM/external

address space*

External address

space/reserved area

External address

space/reserved area

Internal I/O registers

H'FFFFFF

H'FFFC00

H'FFFF00

H'FFFF20 H'FFFFFF

H'FFFF00

H'FFFF20

H'040000

H'100000

H'140000

External address

space/reserved area*

On-chip ROM

ROM: 256 kbytes

RAM: 8 kbytes

Modes 5 and 6

(external ROM activation

expanded modes

with on-chip ROM enabled)

ROM: 256 kbytes

RAM: 8 kbytes

Mode 7

(single-chip activation

expanded mode

with on-chip ROM enabled)

Notes: 1. This area is specified as an external address area by clearing the RAME bit of SYSCR to 0.

2. When EXPE = 1, external address space; when EXPE = 0, reserved area.

3. When EXPE = 1, external address space when RAME = 0, on-chip RAM when RAME = 1.

When EXPE = 0, on-chip RAM area.

Figure 3.1 H8S/2676 Memory Map (2)

Section 3 MCU Operating Modes

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H'000000

H'FFA000

H'FFC000

H'000000

H'FFA000

H'FFC000

H'FFFC00

On-chip RAM*2

External

address space

External address space

Internal I/O registers

External address space

Internal I/O registers

On-chip ROM

On-chip RAM*2

External address

space/reserved area

External address

space/reserved area

Internal I/O registers

H'FFFFFF

H'FFFC00

H'FFFF00

H'FFFF20 H'FFFFFF

H'FFFF00

H'FFFF20

H'040000H'040000

External address

space/reserved area*1

On-chip ROM

ROM: 256 kbytes

RAM: 8 kbytes

Mode 10 Boot mode

(expanded mode

with on-chip ROM enabled)

ROM: 256 kbytes

RAM: 8 kbytes

Mode 11 Boot mode

(single-chip activation expanded mode

with on-chip ROM enabled)

Notes: 1. When EXPE = 1, external address space; when EXPE = 0, reserved area.

2. On-chip RAM is used for flash memory programming. Do not clear the RAME bit in SYSCR to 0.

Figure 3.1 H8S/2676 Memory Map (3)

Section 3 MCU Operating Modes

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REJ09B0283-0300

H'000000

H'FFA000

H'FFC000

H'000000

H'FFA000

H'FFC000

H'FFFC00

On-chip RAM*

External

address space

External address space

Internal I/O registers

External address space

Internal I/O registers

On-chip ROM

On-chip RAM*

External address

space/reserved area

External address

space/reserved area

Internal I/O registers

H'FFFFFF

H'FFFC00

H'FFFF00

H'FFFF20 H'FFFFFF

H'FFFF00

H'FFFF20

H'040000H'040000

External address

space/reserved area*

On-chip ROM

ROM: 256 kbytes

RAM: 8 kbytes

Mode 12 User program mode

(expanded mode

with on-chip ROM enabled)

ROM: 256 kbytes

RAM: 8 kbytes

Mode 15 User program mode

(single-chip activation

expanded mode

with on-chip ROM enabled)

Notes: 1. When EXPE = 1, external address space; when EXPE = 0, reserved area.

2. On-chip RAM is used for flash memory programming. Do not clear the RAME bit in SYSCR to 0.

H'000000

H'FFA000

H'FFC000

External

address space

On-chip RAM*

External

address space

External address space

Internal I/O registers

External address space

Internal I/O registers

H'FFFFFF

H'FFFC00

H'FFFF00

H'FFFF20

H'100000

H'140000

On-chip ROM

ROM: 256 kbytes

RAM: 8 kbytes

Modes 13 and 14 User program mode

(external ROM activation

expanded modes

with on-chip ROM enabled)

Figure 3.1 H8S/2676 Memory Map (4)

Section 3 MCU Operating Modes

Rev. 3.00 Mar 17, 2006 page 69 of 926

REJ09B0283-0300

H'000000

H'FFA000

H'FFC000

H'000000

H'FFA000

H'FFC000

H'FFFC00

External

address space

On-chip RAM/external

address space*

External address space

Internal I/O registers

External address space

Internal I/O registers

On-chip ROM

On-chip RAM/external

address space*

External address space

Internal I/O registers

External address space

Internal I/O registers

H'FFFFFF

H'FFFC00

H'FFFF00

H'FFFF20 H'FFFFFF

H'FFFF00

H'FFFF20

H'020000

External

address space

RAM: 8 kbytes

Modes 1 and 2

(expanded modes

with on-chip ROM disabled)

ROM: 128 kbytes

RAM: 8 kbytes

Mode 4

(expanded mode

with on-chip ROM enabled)

Note: * This area is specified as an external address area by clearing the RAME bit of SYSCR to 0.

Figure 3.2 H8S/2675 Memory Map (1)

Section 3 MCU Operating Modes

Rev. 3.00 Mar 17, 2006 page 70 of 926

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H'000000

H'FFA000

H'FFC000

H'000000

H'FFA000

H'FFC000

H'FFFC00

External

address space

On-chip RAM/external

address space*1

External

address space

External address space

Internal I/O registers

External address space

Internal I/O registers

On-chip ROM

On-chip RAM/external

address space*3

External address

space/reserved area

External address

space/reserved area

Internal I/O registers

H'FFFFFF

H'FFFC00

H'FFFF00

H'FFFF20 H'FFFFFF

H'FFFF00

H'FFFF20

H'020000

H'100000

H'120000

External address

space/reserved area*2

On-chip ROM

ROM: 128 kbytes

RAM: 8 kbytes

Modes 5 and 6

(external ROM activation

expanded modes

with on-chip ROM enabled)

ROM: 128 kbytes

RAM: 8 kbytes

Mode 7

(single-chip activation

expanded mode

with on-chip ROM enabled)

Notes: 1. This area is specified as an external address area by clearing the RAME bit of SYSCR to 0.

2. When EXPE = 1, external address space; when EXPE = 0, reserved area.

3. When EXPE = 1, external address space when RAME = 0, on-chip RAM when RAME = 1.

When EXPE = 0, on-chip RAM area.

Figure 3.2 H8S/2675 Memory Map (2)

Section 3 MCU Operating Modes

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H'000000

H'FFA000

H'FFC000

H'000000

H'FFA000

H'FFC000

H'FFFC00

External

address space

On-chip RAM/external

address space*

External address space

Internal I/O registers

External address space

Internal I/O registers

On-chip ROM

On-chip RAM/external

address space*

External address space

Internal I/O registers

External address space

Internal I/O registers

H'FFFFFF

H'FFFC00

H'FFFF00

H'FFFF20 H'FFFFFF

H'FFFF00

H'FFFF20

H'010000

External

address space

RAM: 8 kbytes

Modes 1 and 2

(expanded modes

with on-chip ROM disabled)

ROM: 64 kbytes

RAM: 8 kbytes

Mode 4

(expanded mode

with on-chip ROM enabled)

Note: * This area is specified as an external address area by clearing the RAME bit of SYSCR to 0.

Figure 3.3 H8S/2673 Memory Map (1)

Section 3 MCU Operating Modes

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H'000000

H'FFA000

H'FFC000

H'000000

H'FFA000

H'FFC000

H'FFFC00

External

address space

On-chip RAM/external

address space*

External

address space

External address space

Internal I/O registers

External address space

Internal I/O registers

On-chip ROM

On-chip RAM/external

address space*

External address

space/reserved area

External address

space/reserved area

Internal I/O registers

H'FFFFFF

H'FFFC00

H'FFFF00

H'FFFF20 H'FFFFFF

H'FFFF00

H'FFFF20

H'010000

H'100000

H'110000

External address

space/reserved area*

On-chip ROM

ROM: 64 kbytes

RAM: 8 kbytes

Modes 5 and 6

(external ROM activation

expanded modes

with on-chip ROM enabled)

ROM: 64 kbytes

RAM: 8 kbytes

Mode 7

(single-chip activation

expanded mode

with on-chip ROM enabled)

Notes: 1. This area is specified as an external address area by clearing the RAME bit of SYSCR to 0.

2. When EXPE = 1, external address space; when EXPE = 0, reserved area.

3. When EXPE = 1, external address space when RAME = 0, on-chip RAM when RAME = 1.

When EXPE = 0, on-chip RAM area.

Figure 3.3 H8S/2673 Memory Map (2)

Section 3 MCU Operating Modes

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H'000000

H'FFA000

H'FFC000

External

address space

On-chip RAM/external

address space*

External address space

Internal I/O registers

External address space

Internal I/O registers

H'FFFFFF

H'FFFC00

H'FFFF00

H'FFFF20

RAM: 8 kbytes

Modes 1 and 2

(expanded modes

with on-chip ROM disabled)

Note: * This area is specified as an external address area by clearing the RAME bit of SYSCR to 0.

Figure 3.4 H8S/2670 Memory Map

Section 3 MCU Operating Modes

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H'000000

H'FF4000

H'FFC000

External

address space

On-chip RAM/external

address space*

External address space

Internal I/O registers

External address space

Internal I/O registers

H'FFFFFF

H'FFFC00

H'FFFF00

H'FFFF20

RAM: 32 kbytes

Modes 1 and 2

(expanded modes

with on-chip ROM disabled)

Note: * This area is specified as an external address area by clearing the RAME bit of SYSCR to 0.

Figure 3.5 H8S/2674R Memory Map

Section 4 Exception Handling

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Section 4 Exception Handling

4.1 Exception Handling Types and Priority

As table 4.1 indicates, exception handling may be caused by a reset, trace, interrupt, or trap

instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions

occur simultaneously, they are accepted and processed in order of priority. Exception sources, the

stack structure, and operation of the CPU vary depending on the interrupt control mode. For

details on the interrupt control mode, r efer to section 5, Interrupt Con tr oller.

Table 4.1 Exception Types and Priority

Priority Exception Type Start of Exception Handling

High Reset Starts immediately after a low-to-high transition at the RES

pin, or when the watchdog timer overflows. The CPU enters

the reset state when the RES pin is low.

Trace*1Starts when execution of the current instruction or exception

handling ends, if the trace (T) bit in the EXR is set to 1.

Direct transition*2Starts when the direct transition occurs by execution of the

SLEEP instruction.

Interrupt Starts when execution of the current instruction or exception

handling ends, if an interrupt request has been issued.*3

Low Trap instruction*4Started by execution of a trap instructio n (TRAPA)

Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not

executed afte r execution of an RTE instruction.

2. Not available in this LSI.

3. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC

instruction execution, or on completion of reset exception handling.

4. Trap instruction exception handling requests are accepted at all times in program

execution stat e.

4.2 Exception Sources and Exception Vector Table

Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception

sources and their vector addresses. Since the usable modes differ depending on the product, for

details on each product, refer to section 3, MCU Operating Modes.

Section 4 Exception Handling

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Table 4.2 Exception Handling Vector Table

Vector Address*1

Exception Source Vector Number Normal Mode*2Advanced Mode

Power-on reset 0 H'0000 to H'0001 H'0000 to H'0003

Manual reset *21 H'0002 to H'0003 H'0004 to H'0007

Reserved for system use 2 H'0004 to H'0005 H'0008 to H'000B

3 H'0006 to H'0007 H'000C to H'000F

4 H'0008 to H'0019 H'0010 to H'0013

Trace 5 H'000A to H'000B H'0014 to H'0017

Interrupt (direct transition)*26 H'000C to H'000D H'0018 to H'001B

Interrupt (NMI) 7 H'000E to H'000F H'001C to H'001F

Trap instruction (#0) 8 H'0010 to H'0011 H'0020 to H'0023

(#1) 9 H'0012 to H'0013 H'0024 to H'0027

(#2) 10 H'0014 to H'0015 H'0028 to H'002B

(#3) 11 H'0016 to H'0017 H'002C to H'002F

Reserved for system use 12 H'0018 to H'0019 H'0030 to H'0033

13 H'001A to H'001B H'0034 to H'0037

14 H'001C to H'001D H'0038 to H'003B

15 H'001E to H'001F H'003C to H'003F

External interrupt IRQ0 16 H'0020 to H'0021 H'0040 to H'0043

IRQ1 17 H'0022 to H'0023 H'0044 to H'0047

IRQ2 18 H'0024 to H'0025 H'0048 to H'004B

IRQ3 19 H'0026 to H'0027 H'004C to H'004F

IRQ4 20 H'0028 to H'0029 H'0050 to H'0053

IRQ5 21 H'002A to H'002B H'0054 to H'0057

IRQ6 22 H'002C to H'002D H'0058 to H'005B

IRQ7 23 H'002E to H'002F H'005C to H'005F

IRQ8 24 H'0030 to H'0031 H'0060 to H'0063

IRQ9 25 H'0032 to H'0033 H'0064 to H'0067

IRQ10 26 H'0034 to H'0035 H'0068 to H'006B

IRQ11 27 H'0036 to H'0037 H'006C to H'006F

IRQ12 28 H'0038 to H'0039 H'0070 to H'0073

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Vector Address*1

Exception Source Vector Number Normal Mode*2Advanced Mode

External interrupt IRQ13 29 H'003A to H'003B H'0074 to H'0077

IRQ14 30 H'003C to H'003D H'0078 to H'007B

IRQ15 31 H'003E to H'003F H'007C to H'007F

Internal interrupt*332



H'0040 to H'0041



H'00C6 to H'00C7

H'0080 to H'0083



H'018C to H'018F

Notes: 1. Lower 16 bits of the address.

2. Not available in this LSI.

3. For details of internal interrupt vectors, see section 5.5, Interrupt Exception Handling

Vector Table.

4.3 Reset

A reset has the h ighest exception p r iority. When the RES pin goes low, all processing halts and

this LSI enters the re set. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at

power-up. To reset the chip during operation, hold the RES pin low for at least 20 states. A reset

initializes the internal state of the CPU and the registers of on-chip peripheral modules.

The chip can also be reset by overflow of the watchdog timer. For details see section 1 4,

Watchdog Timer.

The interrupt control mode is 0 immediately after reset.

4.3.1 Reset exception handling

When the RES pin goes high after being held low for the necessary time, this LSI star ts r e set

exception handling as follows:

1. The internal state of the CPU and the registers of the on-chip peripheral modules are

initialized, the T bit is clear ed to 0 in EXR, and the I bit is set to 1 in EXR and CCR.

2. The reset exception handling vector address is read and transferred to the PC, and program

execution starts from the address indicated by the PC.

Figures 4.1 and 4.2 show examples of the reset sequence.

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RES

High

Vector fetch Internal

processing Prefetch of first

program instruction

(1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002)

(2)(4) Start address (contents of reset exception handling vector address)

(5) Start address ((5)=(2)(4))

(6) First program instruction

Internal

address bus

Internal read

signal

Internal write

signal

Internal data

bus

(1)

(2) (4) (6)

(3) (5)

Figure 4.1 Reset Sequence (Advanced Mode with O n- Chip ROM Enabled)

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RES

HWR, LWR

D15 to D0

High

* * *

Address bus

Vector fetch Internal

processing Prefetch of first

program instruction

(1)

(2) (4) (6)

(3) (5)

(1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002)

(2)(4) Start address (contents of reset exception handling vector address)

(5) Start address ((5)=(2)(4))

(6) First program instruction

Note: * Seven program wait states are inserted.

Figure 4.2 Reset Sequence (Advanced Mode with On- C hip ROM Disa bled)

4.3.2 Interrupts after Reset

If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC an d

CCR will not be saved correctly , leadin g to a program crash. To prevent this, all interrupt requests,

including NMI, are disabled immediately after a reset. Since the first instruction of a program is

always executed immediately after the reset state en ds, make sure that this in str uction initializes

the stack pointer (example: MOV.L #xx: 32, SP).

4.3.3 On-Chip Peripheral Functions after Reset Release

After reset release, MSTPCR is initialized to H'0FFF and all modules except the DMAC,

EXDMAC and the DTC enter module stop mode.

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Consequently, on-chip peripheral module registers cannot be read or written to. Register reading

and writing is enabled when module stop mode is exited.

4.4 Traces

Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control

mode 0, irrespective of the state of the T bit. For details on interrupt control modes, see section 5,

Interrupt Controller.

If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on

completion of each instruction. Trace mode is not affected by interrupt masking. Table 4.3 shows

the state of CCR and EXR after execution of trace exception handling. Trace mode is canceled by

clearing the T bit in EXR to 0. Th e T bit saved on the stack retains its value of 1, and when control

is returned from the trace exception handling routine by the RTE instruction, trace mode resumes.

Trace exception handling is not carried out after execution of the RTE instruction.

Interrupts are accepted even within the trace exception handling routine.

Table 4.3 Status of CCR and EXR after Trace Exception Handling

CCR EXR

Interrupt Control Mode I UI I2 to I0 T

0 Trace exception handling cannot be used.

21——0

Legend:

1: Set to 1

0: Cleared to 0

—: Retains value prior to execution.

4.5 Interrupts

Interrupts are controlled by the interrupt contro ller . The in ter rup t controller has two interrupt

control modes and can assign interrupts other than NMI to eight priority/mask levels to enable

multiplexed interrupt control. The sou r ce to start interrupt exception handling and the vector

address differ depending on the product. For details, refer to section 5, Interrupt Controller.

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The interrupt excep tion handling is as follo ws:

1. The values in the program counter (PC), condition code register (CCR), and exten ded register

(EXR) are saved in the stack.

2. The interr upt mask bit is updated and th e T bit is cleared to 0.

3. A vector address corresponding to the interrupt source is generated, the start address is loaded

from the vector table to the PC, and program execution starts from that address.

4.6 Trap Instruction

Trap instruction exception handling starts when a TRAPA instructio n is executed. Trap instru ction

exception handling can be executed at all times in the program execution state.

The trap instr uction exception handling is as follows:

1. The values in the program counter (PC), condition code register (CCR), and exten ded register

(EXR) are saved in the stack.

2. The interr upt mask bit is updated and th e T bit is cleared to 0.

3. A vector address corresponding to the interrupt source is generated, the start address is loaded

from the vector table to the PC, and program execution starts from that address.

The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector

number from 0 to 3, as specified in the instruction code.

Table 4.4 shows the status of CCR and EXR after execution of trap instruction exception handling.

Table 4.4 Sta tus of CCR and EXR after Trap Instruction Exception Handling

CCR EXR

Interrupt Control Mode I UI I2 to I0 T

01———

21——0

Legend:

1: Set to 1

0: Cleared to 0

—: Retains value prior to execution.

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4.7 Stack Status after Exception Handling

Figure 4.3 shows the stack after completion of trap instruction exception handling and interrupt

exception handling.

CCR

CCR*

PC (16 bits)

EXR

Reserved*

CCR

CCR*

PC (16 bits)

CCR

PC (24 bits)

EXR

Reserved*

CCR

PC (24 bits)

(a) Normal Modes*

(b) Advanced Modes

Interrupt control mode 0 Interrupt control mode 2

Notes: 1.

2. Ignored on return.

Normal modes are not available in this LSI.

Figure 4.3 Stack Status after Ex ception Handling

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4.8 Usage Note

When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The

stack should always be accessed by word transfer instruction or longword tran sfer instruction, and

the value of the stack pointer (SP, ER7) should always be kept even. Use the following

instruc tions to save registe rs:

PUSH.W Rn (or MOV.W Rn, @-SP)

PUSH.L ERn (or MOV.L ERn, @-SP)

Use the following instructions to restore registers:

POP.W Rn (or MOV.W @SP+, Rn)

POP.L ERn (or MOV.L @SP+, ERn)

Setting SP to an odd value may lead to a malfunction. Figure 4.4 shows an example of operation

when the SP value is odd.

CCR:

PC:

R1L:

SP:

Condition code register

Program counter

General register R1L

Stack pointer

CCR

SP SP R1L H'FFFEFA

H'FFFEFB

H'FFFEFC

H'FFFEFD

H'FFFEFE

H'FFFEFF

PC PC

TRAP instruction executed

SP set to H'FFFEFF Data saved above SP

MOV.B R1L, @-ER7

Contents of CCR lost

Address

Legend:

Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode.

Figure 4.4 Operation when SP Value Is Odd

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Section 5 Interrupt Controller

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Section 5 Interrupt Controller

5.1 Features

• Two interrupt control modes

Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the

interrupt control register (INTCR).

• Priorities settable with IPR

An interru pt priority register ( I PR) is provided for settin g interrupt prior ities. Eight priority

levels can be set for each module for all interrupts except NMI. NMI is assigned the highest

priority level of 8, and can be accepted at all times.

• Independent vect or address es

All interrupt sources are assigned independent vector addresses, making it unnecessary for the

source to b e identified in the interrupt handling routine.

• Seventeen external interrupts

NMI is the highest-priority interrupt, and is accepted at all times. Rising edg e or falling edge

can be selected for NMI. Falling edge, rising edge, or both edge detection, or level sensing, can

be selected for IRQ15 to IRQ0.

• DTC and DMAC control

DTC and DMAC activations are performed by means of interrupts.

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A block diagram of the interrupt controller is shown in figure 5.1.

INTCR

NMI input

IRQ input

Internal

interrupt

sources

SWDTEND

to TEI

INTM1 INTM0

NMIEG

NMI input unit

IRQ input unit

ISR

ISCR

ITSR IER

IPR

Interrupt controller

Priority

determination

Interrupt

request

Vector

number

I2 to I0 CCR

EXR

CPU

Legend:

ISCR: IRQ sense control register

IER: IRQ enable register

ISR: IRQ status register

IPR: Interrupt priority register

INTCR: Interrupt control register

ITSR: IRQ pin select register

SSIER: Software standby release IRQ enable register

SSIER

Figure 5.1 Block Diagram of Interrupt Controller

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5.2 Input/Output Pins

Table 5.1 shows the pin configuration of the interrupt controller.

Table 5.1 Pin Configuration

Name I/O Function

NMI Input Nonmaskable external interrupt

Rising or falling edge can be selected.

IRQ15 to IRQ0 Input Maskable exter nal interrupt s

Rising, falli ng, or both edge s, or level sen si ng, can be

selected.

5.3 Register Descriptions

The interrupt co ntroller has the followin g registers.

• Interrupt control register (INTCR)

• IRQ sense control register H (ISCRH)

• IRQ sense control register L (ISCRL)

• IRQ enable register (IER)

• IRQ status register (ISR)

• IRQ pin select register (ITSR)

• Software standby release IRQ enable register (SSIER)

• Interrupt priority register A (IPRA)

• Interrupt priority reg ister B (IPRB)

• Interrupt priority reg ister C (IPRC)

• Interrupt priority register D (IPRD)

• Interrupt priority r e g ister E (IPRE)

• Interrupt priority register F ( IPRF)

• Interrupt priority register G (IPRG)

• Interrupt priority register H (IPRH)

• Interrupt priority register I (IPRI)

• Interrupt priority register J (IPRJ)

• Interrupt priority register K (IPRK)

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5.3.1 Interrupt Control Register (INTCR)

INTCR selects the interrupt control mode, and the detected edge for NMI.

Bit Bit Name Initial Value R/W Description

7, 6 — All 0 R/W Reserved

These bits can be read from or written to.

However, the write value should always be 0.

4INTM1

INTM0 0

0R/W

R/W Interrupt Control Select Mode 1 and 0

These bits select either of two interrupt control

modes for the interrupt controller.

00: Interrupt control mode 0

Interrupts are contr oll ed by I bit.

01: Setting prohibited.

10: Interrupt control mode 2

Interrupts are controlled by bits I2 to I0, and

IPR.

11: Setting prohibited.

3 NMIEG 0 R/W NMI Edge Select

Selects the input edge for the NMI pin.

0: Interrupt request generated at falling edge of

NMI input

1: Interrupt request generated at rising edge of

NMI input

2 to 0 — All 0 R/W Reserved

These bits can be read from or written to.

However, the write value should always be 0.

5.3.2 Interrupt Priority Registers A to K (IPRA to IPRK)

IPR are eleven 16-bit readable/writable reg ister s that set priorities ( levels 7 to 0) for interr upts

other than NMI.

The correspondence between interrupt sources and IPR settings is shown in table 5.2 (Interrupt

Sources, Vector Ad dresses, and Interrupt Priorities). Setting a value in the range from H'0 to H'7

in the 3-bit groups of bits 14 to 12, 10 to 8, 6 to 4, and 2 to 0 sets the priority of the corresponding

interrupt. IPR should be read in word size.

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Bit Bit Name Initial Value R/W Description

15 — 0 — Reserved

This bit is always read as 0 and cann ot be

modified.

IPR14

IPR13

IPR12

R/W

Sets the priority of the corresponding interrupt

source.

000: Priority level 0 (Lowest)

001: Priority level 1

010: Priority level 2

011: Priority level 3

100: Priority level 4

101: Priority level 5

110: Priority level 6

111: Priority level 7 (Highest)

11 — 0 — Reserved

This bit is always read as 0 and cann ot be

modified.

IPR10

IPR9

IPR8

R/W

Sets the priority of the corresponding interrupt

source.

000: Priority level 0 (Lowest)

001: Priority level 1

010: Priority level 2

011: Priority level 3

100: Priority level 4

101: Priority level 5

110: Priority level 6

111: Priority level 7 (Highest)

7— 0 — Reserved

This bit is always read as 0 and cann ot be

modified.

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Bit Bit Name Initial Value R/W Description

IPR6

IPR5

IPR4

R/W

Sets the priority of the corresponding interrupt

source.

000: Priority level 0 (Lowest)

001: Priority level 1

010: Priority level 2

011: Priority level 3

100: Priority level 4

101: Priority level 5

110: Priority level 6

111: Priority level 7 (Highest)

3— 0 — Reserved

This bit is always read as 0 and cann ot be

modified.

IPR2

IPR1

IPR0

R/W

Sets the priority of the corresponding interrupt

source.

000: Priority level 0 (Lowest)

001: Priority level 1

010: Priority level 2

011: Priority level 3

100: Priority level 4

101: Priority level 5

110: Priority level 6

111: Priority level 7 (Highest)

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5.3.3 IRQ Enable Register (IER)

IER controls enabling and disabling of interrupt requests IRQ15 to IRQ0.

Bit Bit Name Initial Value R/W Description

15 IRQ15E 0 R/W IRQ15 Enable

The IRQ15 interrupt requ est is ena bled when

this bit is 1.

14 IRQ14E 0 R/W IRQ14 Enable

The IRQ14 interrupt requ est is ena bled when

this bit is 1.

13 IRQ13E 0 R/W IRQ13 Enable

The IRQ13 interrupt requ est is ena bled when

this bit is 1.

12 IRQ12E 0 R/W IRQ12 Enable

The IRQ12 interrupt requ est is ena bled when

this bit is 1.

11 IRQ11E 0 R/W IRQ11 Enable

The IRQ11 interrupt requ est is ena bled when

this bit is 1.

10 IRQ10E 0 R/W IRQ10 Enable

The IRQ10 interrupt requ est is ena bled when

this bit is 1.

9 IRQ9E 0 R/W IRQ9 Enable

The IRQ9 interrupt request is enabled when this

bit is 1.

8 IRQ8E 0 R/W IRQ8 Enable

The IRQ8 interrupt request is enabled when this

bit is 1.

7 IRQ7E 0 R/W IRQ7 Enable

The IRQ7 interrupt request is enabled when this

bit is 1.

6 IRQ6E 0 R/W IRQ6 Enable

The IRQ6 interrupt request is enabled when this

bit is 1.

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Bit Bit Name Initial Value R/W Description

5 IRQ5E 0 R/W IRQ5 Enable

The IRQ5 interrupt request is enabled when this

bit is 1.

4 IRQ4E 0 R/W IRQ4 Enable

The IRQ4 interrupt request is enabled when this

bit is 1.

3 IRQ3E 0 R/W IRQ3 Enable

The IRQ3 interrupt request is enabled when this

bit is 1.

2 IRQ2E 0 R/W IRQ2 Enable

The IRQ2 interrupt request is enabled when this

bit is 1.

1 IRQ1E 0 R/W IRQ1 Enable

The IRQ1 interrupt request is enabled when this

bit is 1.

0 IRQ0E 0 R/W IRQ0 Enable

The IRQ0 interrupt request is enabled when this

bit is 1.

5.3.4 IRQ Sense Control Registers H and L (ISCRH, I SCRL)

ISCR select the source that generates an interrupt request at pins IRQ15 to IRQ0.

• ISCRH

Bit Bit Name Initial Value R/W Description

14 IRQ15SCB

IRQ15SCA 0

0R/W

R/W IRQ15 Sense Control B

IRQ15 Sense Control A

00: Interrupt request generated at IRQ15 input

low level

01: Interrupt request generated at falling edge

of IRQ15 input

10: Interrupt request generated at rising edge of

IRQ15 input

11: Interrupt request generated at both falling

and rising edges of IRQ15 input

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Bit Bit Name Initial Value R/W Description

12 IRQ14SCB

IRQ14SCA 0

0R/W

R/W IRQ14 Sense Control B

IRQ14 Sense Control A

00: Interrupt request generated at IRQ14 input

low level

01: Interrupt request generated at falling edge

of IRQ14 input

10: Interrupt request generated at rising edge of

IRQ14 input

11: Interrupt request generated at both falling

and rising edges of IRQ14 input

10 IRQ13SCB

IRQ13SCA 0

0R/W

R/W IRQ13 Sense Control B

IRQ13 Sense Control A

00: Interrupt request generated at IRQ13 input

low level

01: Interrupt request generated at falling edge

of IRQ13 input

10: Interrupt request generated at rising edge of

IRQ13 input

11: Interrupt request generated at both falling

and rising edges of IRQ13 input

8IRQ12SCB

IRQ12SCA 0

0R/W

R/W IRQ12 Sense Control B

IRQ12 Sense Control A

00: Interrupt request generated at IRQ12 input

low level

01: Interrupt request generated at falling edge

of IRQ12 input

10: Interrupt request generated at rising edge of

IRQ12 input

11: Interrupt request generated at both falling

and rising edges of IRQ12 input

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Bit Bit Name Initial Value R/W Description

6IRQ11SCB

IRQ11SCA 0

0R/W

R/W IRQ11 Sense Control B

IRQ11 Sense Control A

00: Interrupt request generated at IRQ11 input

low level

01: Interrupt request generated at falling edge

of IRQ11 input

10: Interrupt request generated at rising edge of

IRQ11 input

11: Interrupt request generated at both falling

and rising edges of IRQ11 input

4IRQ10SCB

IRQ10SCA 0

0R/W

R/W IRQ10 Sense Control B

IRQ10 Sense Control A

00: Interrupt request generated at IRQ10 input

low level

01: Interrupt request generated at falling edge

of IRQ10 input

10: Interrupt request generated at rising edge of

IRQ10 input

11: Interrupt request generated at both falling

and rising edges of IRQ10 input

2IRQ9SCB

IRQ9SCA 0

0R/W

R/W IRQ9 Sense Control B

IRQ9 Sense Control A

00: Interrupt request generated at IRQ9 input

low level

01: Interrupt request generated at falling edge

of IRQ9 input

10: Interrupt request generated at rising edge of

IRQ9 input

11: Interrupt request generated at both falling

and rising edges of IRQ9 input

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Bit Bit Name Initial Value R/W Description

0IRQ8SCB

IRQ8SCA 0

0R/W

R/W IRQ8 Sense Control B

IRQ8 Sense Control A

00: Interrupt request generated at IRQ8 input

low level

01: Interrupt request generated at falling edge

of IRQ8 input

10: Interrupt request generated at rising edge of

IRQ8 input

11: Interrupt request generated at both falling

and rising edges of IRQ8 input

• ISCRL

Bit Bit Name Initial Value R/W Description

14 IRQ7SCB

IRQ7SCA 0

0R/W

R/W IRQ7 Sense Control B

IRQ7 Sense Control A

00: Interrupt request generated at IRQ7 input

low level

01: Interrupt request generated at falling edge

of IRQ7 input

10: Interrupt request generated at rising edge of

IRQ7 input

11: Interrupt request generated at both falling

and rising edges of IRQ7 input

12 IRQ6SCB

IRQ6SCA 0

0R/W

R/W IRQ6 Sense Control B

IRQ6 Sense Control A

00: Interrupt request generated at IRQ6 input

low level

01: Interrupt request generated at falling edge

of IRQ6 input

10: Interrupt request generated at rising edge of

IRQ6 input

11: Interrupt request generated at both falling

and rising edges of IRQ6 input

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Bit Bit Name Initial Value R/W Description

10 IRQ5SCB

IRQ5SCA 0

0R/W

R/W IRQ5 Sense Control B

IRQ5 Sense Control A

00: Interrupt request generated at IRQ5 input

low level

01: Interrupt request generated at falling edge

of IRQ5 input

10: Interrupt request generated at rising edge of

IRQ5 input

11: Interrupt request generated at both falling

and rising edges of IRQ5 input

8IRQ4SCB

IRQ4SCA 0

0R/W

R/W IRQ4 Sense Control B

IRQ4 Sense Control A

00: Interrupt request generated at IRQ4 input

low level

01: Interrupt request generated at falling edge

of IRQ4 input

10: Interrupt request generated at rising edge of

IRQ4 input

11: Interrupt request generated at both falling

and rising edges of IRQ4 input

6IRQ3SCB

IRQ3SCA 0

0R/W

R/W IRQ3 Sense Control B

IRQ3 Sense Control A

00: Interrupt request generated at IRQ3 input

low level

01: Interrupt request generated at falling edge

of IRQ3 input

10: Interrupt request generated at rising edge of

IRQ3 input

11: Interrupt request generated at both falling

and rising edges of IRQ3 input

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Bit Bit Name Initial Value R/W Description

4IRQ2SCB

IRQ2SCA 0

0R/W

R/W IRQ2 Sense Control B

IRQ2 Sense Control A

00: Interrupt request generated at IRQ2 input

low level

01: Interrupt request generated at falling edge

of IRQ2 input

10: Interrupt request generated at rising edge of

IRQ2 input

11: Interrupt request generated at both falling

and rising edges of IRQ2 input

2IRQ1SCB

IRQ1SCA 0

0R/W

R/W IRQ1 Sense Control B

IRQ1 Sense Control A

00: Interrupt request generated at IRQ1 input

low level

01: Interrupt request generated at falling edge

of IRQ1 input

10: Interrupt request generated at rising edge of

IRQ1 input

11: Interrupt request generated at both falling

and rising edges of IRQ1 input

0IRQ0SCB

IRQ0SCA 0

0R/W

R/W IRQ0 Sense Control B

IRQ0 Sense Control A

00: Interrupt request generated at IRQ0 input

low level

01: Interrupt request generated at falling edge

of IRQ0 input

10: Interrupt request generated at rising edge of

IRQ0 input

11: Interrupt request generated at both falling

and rising edges of IRQ0 input

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5.3.5 IRQ Status Register (ISR)

ISR is an IRQ15 to IRQ0 interrupt request flag register.

Bit Bit Name Initial Value R/W Description

IRQ15F

IRQ14F

IRQ13F

IRQ12F

IRQ11F

IRQ10F

IRQ9F

IRQ8F

IRQ7F

IRQ6F

IRQ5F

IRQ4F

IRQ3F

IRQ2F

IRQ1F

IRQ0F

R/(W)*

[Setting condition]

When the interrupt source selected by ISCR

occurs

[Clearing cond iti ons ]

• Cleared by reading IRQnF flag when IRQnF

= 1, then writing 0 to IRQnF flag

• When interrupt ex cept ion handling is

executed when low-level detection is set

and IRQn input is high

• When IRQn interrupt ex cept ion handling is

executed when falling, rising, or both-edge

detect ion is set

• When the DTC is activated by an IRQn

interrupt, and the DISEL bit in MRB of the

DTC is cleared to 0 (n=15 to 0)

Note: *Only 0 can be written, to clear the flag.

5.3.6 IRQ Pin Select Register (ITSR)

ITSR selects input pins IRQ15 to IRQ0.

Bit Bit Name Initial Value R/W Description

15 ITS15 0 R/W Selects IRQ15 input pin.

0: PF2

1: P27

14 ITS14 0 R/W Selects IRQ14 input pin.

0: PF1

1: P26

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Bit Bit Name Initial Value R/W Description

13 ITS13 0 R/W Selects IRQ13 input pin.

0: P65

1: P25

12 ITS12 0 R/W Selects IRQ12 input pin.

0: P64

1: P24

11 ITS11 0 R/W Selects IRQ11 input pin.

0: P63

1: P23

10 ITS10 0 R/W Selects IRQ10 input pin.

0: P62

1: P22

9 ITS9 0 R/W Selects IRQ9 input pin.

0: P61

1: P21

8 ITS8 0 R/W Selects IRQ8 input pin.

0: P60

1: P20

7 ITS7 0 R/W Selects IRQ7 input pin.

0: P57

1: PH3

6 ITS6 0 R/W Selects IRQ6 input pin.

0: P56

1: PH2

5 ITS5 0 R/W Selects IRQ5 input pin.

0: P55

1: P85

4 ITS4 0 R/W Selects IRQ4 input pin.

0: P54

1: P84

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Bit Bit Name Initial Value R/W Description

3 ITS3 0 R/W Selects IRQ3 input pin.

0: P53

1: P83

2 ITS2 0 R/W Selects IRQ2 input pin.

0: P52

1: P82

1 ITS1 0 R/W Selects IRQ1 input pin.

0: P51

1: P81

0 ITS0 0 R/W Selects IRQ0 input pin.

0: P50

1: P80

5.3.7 Software St andby Release IRQ Enable Register (SSIER)

SSIER selects the IRQ pins used to recover from the software standby state.

Bit Bit Name Initial Value R/W Description

SSI15

SSI14

SSI13

SSI12

SSI11

SSI10

SSI9

SSI8

SSI7

SSI6

SSI5

SSI4

SSI3

SSI2

SSI1

SSI0

R/W

Software Standby Release IRQ Setting

These bits select the IRQn pins used to recover

from the software standby state.

0: IRQn requests are not sampled in the

software standby state (Initial value when n =

15 to 3)

1: When an IRQn request occurs in the

software standby state, the chip recovers

from the software standby state after the

elapse of the oscillation settling time (Initial

value when n = 2 to 0) (n = 15 to 0)

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5.4 Interrupt Sources

5.4.1 External Interrupts

There are seventeen external interrupts: NMI and IRQ15 to IRQ0. These interrupts can be used to

restore the chip from software standby mode.

NMI Interrupt : Nonmaskable interrupt request (NMI) is the highest-priority interrupt, and is

always accepted by the CPU regardless of the interrupt control mode or the status of the CPU

interrupt m a sk bits. The NMI E G bit in INTCR can be used to select whether an interrupt is

requested at a r isin g edge or a falling edge on the NMI pin.

IRQ15 to IRQ0 Interrupts: Interrupts IRQ15 to IRQ0 are requested by an input signal at pins

IRQ15 to IRQ0. Interrupts IRQ15 to IRQ0 have the following features:

• Using ISCR, it is p ossible to select whether an interrupt is generated by a low level, fallin g

edge, rising edge, or both edges, at pins IRQ15 to IRQ0.

• Enabling or disabling of interrupt requests IRQ15 to IRQ0 can be selected with IER.

• The interrupt pr iority level can be set with IPR.

• The status of interrupt requests IRQ15 to IRQ0 is indicated in ISR. ISR flags can be cleared to

0 by software.

When IRQ15 to IRQ0 interrupt requests occur at low level of IRQn, the corresponding IRQ should

be held low until an interrupt handling starts. Then the corresponding IRQ should be set to high in

the interru pt handling routine and clear th e I RQn F bit (n = 0 to 15) in ISR to 0. Interrupts may not

be executed when the corresponding IRQ is set to high before the interrupt handling starts.

Detection of IRQ15 to IRQ0 interrupts does not depend on whether the relevant pin has been set

for input or output. However, when a pin is used as an external interrupt input pin, do not clear the

corresponding DDR to 0 and use the pin as an I/O pin for another function.

A block diagram of interrupts IRQ15 to IRQ0 is shown in figure 5.2.

Section 5 Interrupt Controller

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IRQn interrupt

request

IRQnE

IRQnF

Clear signal

Edge/

level detection

circuit

IRQnSCA, IRQnSCB

IRQn

input

Note: n = 15 to 0

Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0

5.4.2 Internal Interrupts

The sources for internal interrupts from on-chip peripheral modules have the following features:

• For each on-chip peripheral module there are flags that indicate the interrupt request status,

and enable bits that select enabling or disabling of these interrupts. They can be controlled

indepen dently. When the enable bit is set to 1 , an interrupt request is issu ed to the interrupt

controller.

• The interrupt pr iority level can be set by means o f IPR.

• The DMAC and DTC can be activated by a TPU, SCI, or other interrupt request.

• When the DMAC or DTC is activated by an in terru pt request, it is not affected by the interrupt

control mode or CPU interrupt mask bit.

5.5 Interrupt Exception Handling Vector Table

Table 5.2 shows in terrupt exception ha ndling sources, vector add r esses, and interrupt prio rities.

For default priorities, the lower the vector number, the high e r the prio r ity. When interrupt con trol

mode 2 is set, priorities among modules can be set by means of the IPR. Modules set at the same

priority will conform to their default priorities. Priorities within a module are fixed.

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Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities

Vector

Address*

Interrupt

Source

Origin of

Interrupt

Source Vector

Number Advanced

Mode IPR Priority DTC

Activation DMAC

Activation

NMI 7 H'001C —High ——External

pin IRQ0 16 H'0040 IPRA14 to IPRA12 —

IRQ1 17 H' 0044 IPRA 10 to IPRA8 —

IRQ2 18 H' 0048 IPRA 6 to IPRA4 —

IRQ3 19 H' 004C IPRA2 to IPRA0 —

IRQ4 20 H' 0050 IPRB 14 to IPRB12 —

IRQ5 21 H' 0054 IPRB 10 to IPRB8 —

IRQ6 22 H' 0058 IPRB 6 to IPRB4 —

IRQ7 23 H' 005C IPRB2 to IPRB0 —

IRQ8 24 H'0060 IPRC14 to IPRC12 —

IRQ9 25 H'0064 IPRC10 to IPRC8 —

IRQ10 26 H'0068 IPRC6 to IPRC4 —

IRQ11 27 H'006C IPRC2 to IPRC0 —

IRQ12 28 H'0070 IPRD14 to IPRD12 —

IRQ13 29 H'0074 IPRD10 to IPRD8 —

IRQ14 30 H'0078 IPRD6 to IPRD4 —

IRQ15 31 H'007C IPRD2 to IPRD0 —

DTC SWDTEND 32 H'0080 IPRE14 to IPRE12 —

WDT WOVI 33 H'0084 IPRE10 to IPRE8 ——

—Reserved for

system use 34 H'0088 IPRE6 to IPRE4 ——

Refresh

controller CMI 35 H' 008C IPRE2 to IPRE0 ——

36 H'0090 ———Reserved for

system use 37 H'0094

IPRF14 to IPR F1 2

——

A/D ADI 38 H'0098 IPRF10 to IPRF8

—Reserved for

system use 39 H'009C Low ——

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Vector

Address*

Interrupt

Source

Origin of

Interrupt

Source Vector

Number Advanced

Mode IPR Priority DTC

Activation DMAC

Activation

TPU_0 TGI0A 40 H'00A0 IPRF6 to IPRF4 High

TGI0B 41 H'00A4 —

TGI0C 42 H'00A8 —

TGI0D 43 H'00AC —

TCI0V 44 H'00B0 ——

45 H'00B4 ——

46 H'00B8 ——

—Reserved for

system use

47 H'00BC

IPRF6 to IPRF4

——

TPU_1 TGI1A 48 H'00C0 IPRF2 to IPRF0

TGI1B 49 H'00C4 —

TCI1V 50 H'00C8 ——

TCI1U 51 H'00CC ——

TPU_2 TGI2A 52 H'00D0 IPRG14 to IPRG12

TGI2B 53 H'00D4 —

TCI2V 54 H'00D8 ——

TCI2U 55 H'00DC ——

TPU_3 TGI3A 56 H'00E0 IPRG10 to IPRG8

TGI3B 57 H'00E4 —

TGI3C 58 H'00E8 —

TGI3D 59 H'00EC —

TCI3V 60 H'00F0 ——

61 H'00F4 ——

62 H'00F8 ——

—Reserved for

system use

63 H'00FC ——

TPU_4 TGI4A 64 H'0100 IPRG6 to IPRG4

TGI4B 65 H'0104 —

TCI4V 66 H'0108 ——

TCI4U 67 H'010C Low ——

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Vector

Address*

Interrupt

Source

Origin of

Interrupt

Source Vector

Number Advanced

Mode IPR Priority DTC

Activation DMAC

Activation

TPU_5 TGI5A 68 H'0110 IPRG2 to IPRG0 High

TGI5B 69 H'0114 —

TCI5V 70 H'0118 ——

TCI5U 71 H'011C ——

TMR_0 CMIA0 72 H'0120 IPRH14 to IPRH12 —

CMIB0 73 H'0124 —

OVI0 74 H'0128 ——

—Reserved for

system use 75 H'012C ——

TMR_1 CMIA1 76 H'0130 IPRH10 to IPRH8 —

CMIB1 77 H'0134 —

OVI1 78 H'0138 ——

—Reserved for

system use 79 H'013C ——

DMAC DMTEND0A 80 H'0140 IPRH6 to IPRH4 —

DMTEND0B 81 H'0144 —

DMTEND1A 82 H'0148 —

DMTEND1B 83 H'014C —

EXDMAC EXDMTEND0 84 H'0150 IPRH0 to IPRH0 ——

EXDMTEND1 85 H'0154 IPRI 14 to IPRI12 ——

EXDMTEND2 86 H'0158 IPRI10 to IPRI8 ——

EXDMTEND3 87 H'015C IPRI6 to IPRI4 ——

SCI_0 ERI0 88 H'0160 I PRI2 to IPRI0 ——

RXI0 89 H'0164

TXI0 90 H'0168

TEI0 91 H'016C ——

SCI_1 ERI1 92 H'0170 IPRJ14 to IPRJ12 ——

RXI1 93 H'0174

TXI1 94 H'0178

TEI1 95 H'017C Low ——

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Vector

Address*

Interrupt

Source

Origin of

Interrupt

Source Vector

Number Advanced

Mode IPR Priority DTC

Activation DMAC

Activation

SCI_2 ERI2 96 H'0180 IPRJ10 to IPRJ8 High ——

RXI2 97 H'0184 —

TXI2 98 H'0188 —

TEI2 99 H'018C ——

—100 H'0190 IPRJ6 to IPRJ4 ——Reserved for

system use 101 H'0194 ——

102 H'0198 ——

103 H'019C ——

—104 H'01A0 IP RJ2 to IPRJ0 ——

Reserved for

system use 105 H'01A4 ——

106 H'01A8 ——

107 H'01AC ——

108 H'01B0 IP RK14 to IPRK12 ——

109 H'01B4 ——

110 H'01B8 ——

111 H'01BC ——

112 H'01C0 IPRK10 to IPRK8 ——

113 H'01C4 ——

114 H'01C8 ——

115 H'01CC ——

116 H'01D0 IPRK6 to IPRK4 ——

117 H'01D4 ——

118 H'01D8 ——

119 H'01DC Low ——

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Vector

Address*

Interrupt

Source

Origin of

Interrupt

Source Vector

Number Advanced

Mode IPR Priority DTC

Activation DMAC

Activation

—120 H'01E0 IP RK2 to IPRK0 Hi gh ——

Reserved for

system use 121 H'01E4 ——

122 H'01E8 ——

123 H'01EC ——

124 H'01F0 ——

125 H'01F4 ——

126 H'01F8 ——

127 H'01EC Low ——

Note: *Lower 16 bits of the start address.

5.6 Interrupt Control Modes and Interrupt Operation

The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2.

Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is

selected by INTCR. Table 5.3 shows the differences between interrupt control mode 0 and

interrupt control mode 2.

Table 5.3 Interrupt Control Modes

Interrupt

Control Mode Priority Setting

Registers Interrupt

Mask Bits Description

0 Default I The priorities of interrupt sources are fixed at

the default settings.

Interrupt sources except for NMI is masked by

the I bit.

2 IPR I2 to I0 8 priority levels except for NMI can be set with

IPR.

8-level interrupt ma sk con trol is perform e d by

bits I2 to I0.

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5.6.1 Interrupt Contro l Mode 0

In interrupt control mode 0, interrupt requests except for NMI is masked by the I bit of CCR in th e

CPU. Figure 5.3 shows a flowchart of the interrupt acceptance operation in this case.

1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an

interrupt r equ est is sent to the interrupt controller.

2. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held

pending. If the I bit is cleared, an interrupt request is accepted.

3. Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to

the priority system is accepted, and other interrupt requests are held pending.

4. When the CPU accepts an interrupt request, it starts interrupt exception handling after

execution of the current in struction has been completed.

5. The PC and CCR a re saved to the stack are a by interrupt exc eption han dling. Th e PC saved on

the stack shows the address of the first in struction to be executed after returning from th e

interrup t handling routine.

6. Next, the I bit in CCR is set to 1. This masks all interrupts except NMI.

7. The CPU generates a vector address for the accepted interrupt and starts execution of th e

interrupt handling routine at the address indicated by the contents of the vector address in the

vector table.

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Program execution status

Interrupt generated?

NMI

IRQ0

IRQ1

TEI_2

I = 0

Save PC and CCR

I ← 1

Read vector address

Branch to interrupt handling routine

Yes

Yes No

Yes

Hold

pending

Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance

in Interrupt Control Mode 0

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5.6.2 Interrupt Contro l Mode 2

In interrupt control mode 2, mask control is done in eight levels for interrupt requests except fo r

NMI by compar ing the EXR interrupt mask level (I2 to I0 bits) in the CPU and the IPR setting.

Figure 5.4 shows a flowchart of the interrupt acceptance operation in this case.

1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an

interrupt r equ est is sent to the interrupt controller.

2. When interrupt reque sts are sent to the interrupt controller, the interrup t with the highest

priority according to the interrupt priority levels set in IPR is selected, and lower-priority

interrupt requests are held pending. If a number of interrupt requests with the same priority are

generated at the same time, the interrupt request with the highest priority according to the

priority system shown in table 5.2 is selected.

3. Next, the priority of the selected interrupt request is compared with the interrupt mask level set

in EXR. An interr upt request with a priority no higher than the mask leve l set at th at time is

held pending, and only an interrupt request with a priority higher than the in ter rup t m ask level

is accepted.

4. When the CPU accepts an interrupt request, it starts interrupt exception handling after

execution of the current in struction has been completed.

5. The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC

saved on the stack shows the address of the first instruction to be executed after returning from

the interru pt handling routine.

6. The T bit in EXR is clear ed to 0. The interrupt mask level is rewritten with the priority level of

the accepted interrupt.

If the accepted interrupt is NMI, the interrupt mask level is set to H'7.

7. The CPU generates a vector address for the accepted interrupt and starts execution of th e

interrupt handling routine at the address indicated by the contents of the vector address in the

vector table.

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Yes

Program execution status

Interrupt generated?

NMI

Level 6 interrupt?

Mask level 5

or below?

Level 7 interrupt?

Mask level 6

or below?

Save PC, CCR, and EXR

Clear T bit to 0

Update mask level

Read vector address

Branch to interrupt handling routine

Hold

pending

Level 1 interrupt?

Mask level 0?

Yes

No Yes

Yes

Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance

in Interrupt Control Mode 2

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5.6.3 Interrupt Except ion Handling Sequence

Figure 5.5 shows the interrupt exception handling sequence. The example shown is for the case

where interrupt control mode 0 is set in advanced mode, and the program area and stack area are

in on-chip m emor y.

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(14)(12)(10)(6)(4)(2)

(1) (5) (7) (9) (11) (13)

Interrupt handling

routine instruction

prefetch

Internal

operation

Vector fetch

stack

Instruction

prefetch Internal

operation

Interrupt

acceptance

Interrupt level determination

Wait for end of instruction

Interrupt

request signal

Internal

address bus

Internal

read signal

Internal

write signal

Internal

data bus

(3)

(1)

(2) (4)

(3)

(5)

(7)

Instruction prefetch address (Not executed.

This is the contents of the saved PC, the return address.)

Instruction code (Not executed.)

Instruction prefetch address (Not executed.)

SP-2

SP-4

Saved PC and saved CCR

Vector address

Interrupt handling routine start address (Vector address contents)

Interrupt handling routine start address ((13) = (10)(12))

First instruction of interrupt handling routine

(6) (8)

(9) (11)

(10) (12)

(13)

(14)

(8)

Figure 5.5 Interrupt Exception Handling

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5.6.4 Interrupt Response Times

Table 5.4 shows interrupt response times - the interval between generation of an interrupt request

and execution of th e f ir st in str uction in the interrupt handling routine. The execution status

symbols used in table 5.4 are explained in table 5.5.

This LSI is capable of fast word transfer to on-chip memory, and have the program area in on-chip

ROM and the stack area in on-chip RAM, enabling high-speed processing.

Table 5.4 Interrupt Response Times

Normal Mode*5Advanced Mode

No. Execution Status

Interrupt

control

mode 0

Interrupt

control

mode 2

Interrupt

control

mode 0

Interrupt

control

mode 2

1 Interrupt priority determination *133 33

2 Number of wait states until executing

instruct ion end s*21 to 19 +2 ·SI1 to 19+2·SI1 to 19+2·SI1 to 19+2·SI

3 PC, CCR, EXR s tack save 2·SK3·SK2·SK3·SK

4 Vector fetch SISI2·SI2·SI

5 Instruction fetch*32·SI2·SI2·SI2·SI

6 Internal processing*422 22

Total (using on-chip memory) 11 to 31 12 to 32 12 to 32 13 to 33

Notes: 1. Two states in case of internal interrupt.

2. Refers to MULXS and DIVXS instructions.

3. Prefetch after interrupt acceptance and interrupt handling routine prefetch.

4. Internal processing after interrupt acceptance and internal processing after vector fetch.

5. Not available in this LSI.

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Table 5.5 Number of Stat es in Interrupt Handling Routine Execution Sta tuses

Object of Access

External Device

8-Bit Bus 16-Bit Bus

Symbol Internal

Memory 2-State

Access 3-State

Access 2-State

Access 3-State

Access

Instruction fetch SI1 4 6+2m 2 3+m

Branch address read SJ

Stack manipulation SK

Legend:

m: Number of wait states in an external device ac cess

5.6.5 DTC and D MAC Activation by Int errupt

The DTC and DMAC can be activated by an interrupt. In this case, the following options are

available:

• Interrupt request to CPU

• Activation req uest to DTC

• Activation req uest to DMAC

• Selection of a number of the above

For details of interrupt requests that can be used to activate the DTC and DMAC, see table 5.2 and

section 9, Data Transfer Controller (DTC) and section 7, DMA Controller (DMAC).

Figure 5.6 shows a block diagram of the DTC, DMAC, and interrupt controller.

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DMAC

Selection

circuit

DTCER

DTVECR

Control logic

Determination of

priority CPU

DTC

Select

signal

IRQ

interrupt

On-chip

supporting

module

Disable

signal

Clear signal

Interrupt controller I, I2 to I0

Interrupt source

clear signal

Interrupt

request DTC activation

request vector

number

CPU interrupt

request vector

number

SWDTE

clear signal

Clear signal

Figure 5.6 DTC, DMAC, and Interrupt Controller

(1) Selection of Interrupt Source: The activation factors for each channel of DMAC are selected

by DTF3 to DTF0 bits of DMACR. The DTA bit of DMABCR can be used to select whether the

selected activation f actors are managed by DMAC. By setting the DTA bit to 1, th e interrupt

factor which were the activation factor for that DMAC do not act as the DTC activation factor or

the CPU interru pt factor.

Interrupt factors other than the interrupts managed by the DMAC are selected as DTC activation

source or CPU interrupt source by the DTCE bit of DTCERA to DTCERF of DTC.

By specifyin g the DISEL bit of the DTC's MRB, it is possible to clear the DTCE b it to 0 after

DTC data transfer, and request a CPU interrupt.

If DTC carries out the designate number of data transfers and the transfer counter reads 0, after

DTC data transfer, the DTCE bit is also cleared to 0, an d an in terru pt is requested to the CPU.

(2) Determination of Priority: The DTC activation source is selected in accordance with the

default priority order, and is not affected by mask or priority levels. See table 9.1 for the respective

priority. DMAC inputs activation factor directly to each channel.

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(3) Operation Order: If the same interrupt is selected as a DTC activation source and a CPU

interrup t so urce, the DTC data transfer is per formed first, followed by CPU interrupt exceptio n

handling.

If the same interrupt is selected as the DMAC activation factor and as the DTC activation factor or

CPU interrupt factor, these operate independently.

Table 5.6 shows the interrupt factor clear control and selection of interrupt factors by specification

of the DTA bit of DMAC’s DMABCR, the DTCE bit of DTC’s DTCERA to DTCERH, and the

DISEL bit of DTC’s MRB.

Table 5.6 Interrupt Source Selection and Clearing Control

Settings

DMAC DTC Interrupt Sources Selection/Clearing Control

DTA DTCE DISEL DMAC DTC CPU

00*X

10 X

1** XX

Legend:

: The relevant interrupt is use d. Interru pt sourc e clear ing is perfo rm ed.

(The CPU should clear the source flag in the interrupt handling routine.)

: The relevant interrupt is used. The interrupt source is not cleared.

X : The relevant interrupt cannot be used .

* :Don’t care

Note: The SCI or A/D converter interrupt source is cleared when the DMAC or DTC reads or

writes to the prescribed register, and is not dependent upon the DTA bit or DISEL bit.

5.7 Usage Notes

5.7.1 Contention between Interrupt Generation and Disabling

When an inter rupt enable bit is cleared to 0 to m ask interrupts, the maskin g becomes effective

after execution of the instruction.

When an inter r upt enable bit is cleared to 0 by an instr uction such as BCLR or MOV, if an

interrupt is generated during execution o f the instr uction, the interrupt concerned will still be

enabled on completio n of the instruction, an d so interrupt exception handling for that interrupt will

be executed on completion of the instruction. However, if there is an interrupt request of higher

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priority than that interrupt, interrup t exception handling will be executed for the higher-priority

interrupt, and the lower-priority interrupt will b e igno red. The same also applies when an interrupt

source flag is cleared to 0. Figure 5.7 shows an example in which the TCIEV bit in the TPU’s

TIER_0 register is clear ed to 0. The above contention will not occur if an enable bit o r interr upt

source flag is clear ed to 0 while the interrupt is masked .

Internal

address bus

Internal

write signal

TCIEV

TCFV

TCIV

interrupt signal

TIER_0 write cycle by CPU TCIV exception handling

TIER_0 address

Figure 5.7 Contention between Interrupt Generation and Disabling

5.7.2 Instructions that Disable Interrupts

Instructions that disable in terrupts are LDC, ANDC, ORC, and XORC. After any o f these

instruction s is ex ecuted, all interrupts in clu ding NMI are disabled and the next instruction is

always executed. When the I bit is set by one of these instructions, the new value becomes valid

two states after execution of the instruction ends.

5.7.3 Times when Interrupts are Disabled

There are times when interrupt acceptance is disabled by the interrupt controller.

The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has

updated the mask level with an LDC, ANDC, ORC, or XORC instruction.

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5.7.4 Interrupts during Execution of EEPMOV Instruction

Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.

With the EEPMOV.B instruction, an in ter rupt request (including NMI) issued d urin g the transfer

is not accepted until the tran sfer is completed.

With the EEPMOV.W ins tr uction, if an interr upt r e quest is issued d u ring the transfer, interrup t

exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this

case is the address of the next instruction. Therefore, if an interrupt is generated during execution

of an EEPMOV.W instruction, the following coding should be used.

L1: EEPMOV.W

MOV.W R4,R4

BNE L1

5.7.5 Change of IRQ Pin Select Register (ITSR) Set ting

When the ITSR setting is changed, an edge occurs internally and the IRQnF bit (n = 0 to 15) of

ISR may be set to 1 at the unintended timing if the selected pin level before the ch ange is different

from the selected pin lev el af ter the ch ange. If the I RQn interrupt request (n = 0 to 15) is enabled,

the interrupt exception handling is execu ted. To prev ent the unintended interrupt, ITSR setting

should be changed while the IRQn interrupt request is disabled, then the IRQnF bit should be

cleared to 0.

5.7.6 Note on IRQ Status Register (ISR)

Since IRQnF flags may be set to 1 depending on the pin states after a reset, be sure to read from

ISR after a reset and then write 0 to clear the IRQnF flags.

Section 5 Interrupt Controller

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Section 6 Bus Controller (BSC)

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Section 6 Bus Controller (BSC)

This LSI has an on-chip bus controller (BSC) that manages the external address space divided into

eight areas.

The bus controller also has a bus arbitration function, and controls the operation of the internal bus

mastership—the CPU, DMA controller (DMAC), EXDMA controller (EXDMAC), and d ata

transfer controller (DTC).

6.1 Features

• Manages external address space in area units

Manages the external address space divided into eight areas of 2 Mbytes

Bus specifications can be set independently for each area

Burst ROM, DRAM, or synchronous DRAM* interface can be set

• Basic bus interface

Chip select sign a ls (CS0 to CS7) can be output for areas 0 to 7

8-bit access or 16-bit access can be selected for each area

2-state access or 3-state access can be selected for each area

Program wait states can be inserted for each area

• Burst ROM interface

Burst ROM interface can be set independently for areas 0 and 1

• DRAM interface

DRAM interface can be set for areas 2 to 5

• Synchronous DRAM interface

Continuous synchronous DRAM space can be set for areas 2 to 5

• Bus arbitration function

Includes a bus arbiter that arbitrates bus mastership between the CPU, DMAC, and DTC

Note: * The Synchronous DRAM interface is not supported in the H8S/2678 Group.

BSCS202A_010020020400

Section 6 Bus Controller (BSC)

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A block diagram of the bus controller is shown in figure 6.1.

Area decoder

Internal address bus

EXDMAC address bus

CS7 to CS0

WAIT

BREQ

BACK

BREQO

External bus

control signals

Internal bus control signals

Internal data bus Control registers

Address

selector

External bus

arbiter

External bus controller

Internal bus

arbiter

Internal bus controller

Internal bus master bus request signal

EXDMAC bus request signal

Internal bus master bus acknowledge signal

EXDMAC bus acknowledge signal

CPU bus request signal

DTC bus request signal

DMAC bus request signal

CPU bus acknowledge signal

DTC bus acknowledge signal

DMAC bus acknowledge signal

ABWCR ASTCR

WTCRAH WTCRAL

WTCRBH WTCRBL

RDNCR

DRAMCR

Legend:

ABWCR : Bus width control register

ASTCR : Access state control register

WTCRAH, WTCRAL,

WTCRBH, and WTCRBL : Wait control registers AH, AL, BH, and BL

RDNCR : Read strobe timing control register

CSACRH and CSACRL : CS assertion period control registers

BROMCRH : Area 0 burst ROM interface control register

Note: * DRACCR is an 8-bit register in the H8S/2678 Group and a 16-bit register in the H8S/2678R Group.

BROMCRL : Area 1 burst ROM interface control register

BCR : Bus control register

DRAMCR : DRAM control register

DRACCR : DRAM access control register

REFCR : Refresh control register

RTCNT : Refresh timer counter

RTCOR : Refresh time constant register

REFCR

RTCNT RTCOR

CSACRH CSACRL

BROMCRH BROMCRL

BCR

DRACCR*

Figure 6.1 Block Diagram of Bus Controller

Section 6 Bus Controller (BSC)

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6.2 Input/Output Pins

Table 6.1 shows the pin configuration of the bus controller.

Table 6.1 Pin Configuration

Name Symbol I/O Function

Address strobe AS Output Strobe signal indicating that basic bus interface

space is accessed and address output on

address bus is enabled.

Read RD Output Strobe signal indicating that basic bus interface

sp ace is being read.

High write/write enable HWR Output Strobe signal indicating that basic bus interface

space is written to, and upper half (D15 to D8)

of data bus is enabled or DRAM interface

space write enable signal.

Low write LWR Output Strobe signal indicating that basic bus interface

space is written to, and lower half (D7 to D0) of

data bus is enable d.

Chip select 0 CS0 Output Strobe signal indicatin g that area 0 is select ed.

Chip select 1 CS1 Output Strobe signal indicatin g that area 1 is select ed

Chip select 2/row address

strobe 2/row address

strobe*

CS2/

RAS2/*

RAS*

Output Strobe signal indicatin g that area 2 is select ed,

DRAM row address strobe signal when area 2

is DRAM interface space or areas 2 to 5 are set

as continuous DRAM interface space, or row

address strobe sig nal of the syn chro nou s

DRAM when the synchronous DRAM interface

is selected.

Chip select 3/row address

strobe 3/column address

strobe*

CS3/

RAS3/*

CAS*

Output Strobe signal indicatin g that area 3 is select ed,

DRAM row address strobe signal when area 3

is DRAM interface space, or column address

strobe signal of the synchronous DRAM when

the synchronous DRAM interface is selected.

Chip select 4/row address

strobe 4/write enable*CS4/

RAS4/*

WE*

Output Strobe signal indicatin g that area 4 is select ed,

DRAM row address strobe signal when area 4

is DRAM interface space, or write enable signal

of the synchronous DRAM when the

synchronous DRAM interface is selected.

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Name Symbol I/O Function

Chip select 5/row address

strobe 5/SDRAMφ*CS5/

RAS5/*

SDRAMφ*

Output Strobe signal indicatin g that area 5 is select ed,

DRAM row address strobe signal when area 5

is DRAM interface space, or dedicated clock

signal for the synchronous DRAM when the

synchronous DRAM interface is selected.

Chip select 6 CS6 Output Strobe signal indicatin g that area 6 is select ed.

Chip select 7 CS7 Output Strobe signal indicatin g that area 7 is select ed.

Upper column address

strobe/upper data mask

enable

UCAS/

DQMU*Output 16-bit DRAM interfac e space upper column

address strobe sig nal, 8-bit DRAM interface

space column address strobe signal, upper

data mask signal of 16-bit synchronous DRAM

interface space, or data mask signal of 8-bit

synchronous DRAM interface space.

Lower column address

strobe/lower data mask

enable

LCAS/

DQML*Output 16-bit DRAM interface space lower co lum n

address strobe signal or lower data mask signal

for the 16-bit synchronous DRAM interface

space.

Output enable/clock

enable OE/CKE*Output Output enable signal for the DRAM interface

space or clock enable signal for the

synchronous DRAM interface space.

Wait WAIT Input Wait request signal when accessing external

space.

Bus request BREQ Input Request signal for release of bus to external

bus master.

Bus request acknowledge BACK Output Acknowledge signal indicating that bus has

been released to external bus master.

Bus request output BREQO Output External bus request signal used when internal

bus master ac cesses external address space

when external bus is rele as ed.

Data transfer acknowledge

1 (DMAC) DACK1 Output Data transfer acknowledge signal for single

address transfer by DMAC channel 1.

Data transfer acknowledge

0 (DMAC) DACK0 Output Data transfer acknowledge signal for single

address transfer by DMAC channel 0.

Data transfer acknowledge

3 (EXDMAC) EDACK3 Output Data transfer acknowledge signal for single

address transfer by EXDMAC channel 3.

Data transfer acknowledge

2 (EXDMAC) EDACK2 Output Data transfer acknowledge signal for single

address transfer by EXDMAC channel 2.

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Name Symbol I/O Function

Data transfer acknowledge

1 (EXDMAC) EDACK1 Output Data transfer acknowledge signal for single

address transfer by EXDMAC channel 1.

Data transfer acknowledge

0 (EXDMAC) EDACK0 Output Data transfer acknowledge signal for single

address transfer by EXDMAC channel 0.

Note: *These pins are not supported in the H8S/2678 Group.

6.3 Register Descriptions

The bus controller has the following registers.

• Bus width control register (ABWCR)

• Access state control register (ASTCR)

• Wait control r e gister AH (WTCRAH)

• Wait control register AL (WTCRAL)

• Wait control re gister BH (WTCRBH)

• Wait control register BL (WTCRBL)

• Read strobe timing control register (RDNCR)

• CS assertion period control register H (CSACRH)

• CS assertion period control register L (CSACRL)

• Area 0 burst ROM interface control register (BROMCRH)

• Area 1 burst ROM interface control register (BROMCRL)

• Bus control register (BCR)

• DRAM control register (DRAMCR)

• DRAM access control register (DRACCR)

• Refresh control register (REFCR)

• Refresh timer counter (RTCNT)

• Refresh time constant register (RTCOR)

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6.3.1 Bus Width Co ntrol Register (ABWCR)

ABWCR designates each area in the external address space as either 8-bit access space or 16-bit

access space.

Bit Bit Name Initial Value*R/W Description

ABW7

ABW6

ABW5

ABW4

ABW3

ABW2

ABW1

ABW0

1/0

R/W

Area 7 to 0 Bus Width Control

These bits select whether the corresponding

area is to be designated as 8-bit access space

or 16-bit access space.

0: Area n is designated as 16-bit access space

1: Area n is designated as 8-bit access space

(n = 7 to 0)

Note: *In modes 2, 4, and 6, ABWCR is initialized to 1. In modes 1, 5, and 7, ABWCR is

initialized to 0.

6.3.2 Access State Control Register (ASTCR)

ASTCR designates each area in the external address space as either 2-state access space or 3-state

access space.

Bit Bit Name Initial Value R/W Description

AST7

AST6

AST5

AST4

AST3

AST2

AST1

AST0

R/W

Area 7 to 0 Access State Control

These bits select whether the corresponding

area is to be designated as 2-state access

space or 3-state access space. Wait state

insertion is enabled or disabled at the same

time.

0: Area n is designated as 2-state access space

Wait state insert ion in area n acce ss is

disabled

1: Area n is designated as 3-state access space

Wait state insert ion in area n acce ss is

enabled (n = 7 to 0)

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6.3.3 Wait Control Registers AH, AL, BH, and BL (WTCRAH, WTCRAL, WTCRBH,

and WTCRBL)

WTCRA and WTCRB select the number of program wait states for each area in the external

address space.

In addition, CAS latency is set when a synchronous DRAM is connected.

• WTCRAH

Bit Bit Name Initial Value R/W Description

15 — 0 R Reserved

This bit is always read as 0 and cann ot be

modified.

W72

W71

W70

R/W

Area 7 Wait Control 2 to 0

These bits select the number of program wait

states when acce ssing area 7 while AST7 bit in

ASTCR = 1.

000: Program wait not inserted

001: 1 program wait state inserted

010: 2 program wait states inserted

011: 3 program wait states inserted

100: 4 program wait states inserted

101: 5 program wait states inserted

110: 6 program wait states inserted

111: 7 program wait states inserted

11 — 0 R Reserved

This bit is always read as 0 and cann ot be

modified.

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Bit Bit Name Initial Value R/W Description

W62

W61

W60

R/W

Area 6 Wait Control 2 to 0

These bits select the number of program wait

states when acce ssing area 6 while AST6 bit in

ASTCR = 1.

000: Program wait not inserted

001: 1 program wait state inserted

010: 2 program wait states inserted

011: 3 program wait states inserted

100: 4 program wait states inserted

101: 5 program wait states inserted

110: 6 program wait states inserted

111: 7 program wait states inserted

• WTARAL

Bit Bit Name Initial Value R/W Description

7— 0 R Reserved

This bit is always read as 0 and cann ot be

modified.

W52

W51

W50

R/W

Area 5 Wait Control 2 to 0

These bits select the number of program wait

states when acce ssing area 5 while AST5 bit in

ASTCR = 1.

000: Program wait not inserted

001: 1 program wait state inserted

010: 2 program wait states inserted

011: 3 program wait states inserted

100: 4 program wait states inserted

101: 5 program wait states inserted

110: 6 program wait states inserted

111: 7 program wait states inserted

3— 0 R Reserved

This bit is always read as 0 and cann ot be

modified.

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Bit Bit Name Initial Value R/W Description

W42

W41

W40

R/W

Area 4 Wait Control 2 to 0

These bits select the number of program wait

states when acce ssing area 4 while AST4 bit in

ASTCR = 1.

000: Program wait not inserted

001: 1 program wait state inserted

010: 2 program wait states inserted

011: 3 program wait states inserted

100: 4 program wait states inserted

101: 5 program wait states inserted

110: 6 program wait states inserted

111: 7 program wait states inserted

• WTCRBH

Bit Bit Name Initial Value R/W Description

15 — 0 R Reserved

This bit is always read as 0 and cann ot be

modified.

W32

W31

W30

R/W

Area 3 Wait Control 2 to 0

These bits select the number of program wait

states when acce ssing area 3 while AST3 bit in

ASTCR = 1.

000: Program wait not inserted

001: 1 program wait state inserted

010: 2 program wait states inserted

011: 3 program wait states inserted

100: 4 program wait states inserted

101: 5 program wait states inserted

110: 6 program wait states inserted

111: 7 program wait states inserted

11 — 0 R Reserved

This bit is always read as 0 and cann ot be

modified.

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Bit Bit Name Initial Value R/W Description

W22

W21

W20

R/W

Area 2 Wait Control 2 to 0

These bits select the number of program wait

states when acce ssing area 2 while AST2 bit in

ASTCR = 1.

A CAS latency is set when the synchronous

DRAM is connecte d*. The setting of area 2 is

reflected to the setting of areas 2 to 5. A CAS

latency can be set regardless of whether or not

an ASTCR wait state insertion is enabled.

000: Program wait not inserted

001: 1 program wait state inserted

010: 2 program wait states inserted

011: 3 program wait states inserted

100: 4 program wait states inserted

101: 5 program wait states inserted

110: 6 program wait states inserted

111: 7 program wait states inserted

000: Synchronous DRAM of CAS latency 1 is

connected to areas 2 to 5.

001: Synchronous DRAM of CAS latency 2 is

connected to areas 2 to 5.

010: Synchronous DRAM of CAS latency 3 is

connected to areas 2 to 5.

011: Synchronous DRAM of CAS latency 4 is

connected to areas 2 to 5.

1XXX: Setting prohibited.

Note: *The synchronous DRAM interface is not supported in the H8S/2678 Group.

Legend: x: Don’t care.

Section 6 Bus Controller (BSC)

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• WTCRBL

Bit Bit Name Initial Value R/W Description

7— 0 R Reserved

This bit is always read as 0 and cann ot be

modified.

W12

W11

W10

R/W

Area 1 Wait Control 2 to 0

These bits select the number of program wait

states when acce ssing area 1 while AST1 bit in

ASTCR = 1.

000: Program wait not inserted

001: 1 program wait state inserted

010: 2 program wait states inserted

011: 3 program wait states inserted

100: 4 program wait states inserted

101: 5 program wait states inserted

110: 6 program wait states inserted

111: 7 program wait states inserted

3— 0 R Reserved

This bit is always read as 0 and cann ot be

modified.

W02

W01

W00

R/W

Area 0 Wait Control 2 to 0

These bits select the number of program wait

states when acce ssing area 0 while AST0 bit in

ASTCR = 1.

000: Program wait not inserted

001: 1 program wait state inserted

010: 2 program wait states inserted

011: 3 program wait states inserted

100: 4 program wait states inserted

101: 5 program wait states inserted

110: 6 program wait states inserted

111: 7 program wait states inserted

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6.3.4 Read Strobe Timing Control Register (RDNCR)

RDNCR selects the read strobe signal (RD) negation timing in a basic bus interface read access.

Bit Bit Name Initial Value R/W Description

RDN7

RDN6

RDN5

RDN4

RDN3

RDN2

RDN1

RDN0

R/W

Read Strobe Timing Control 7 to 0

These bits set the negation timing of the read

strobe in a corresponding area read access.

As shown in figure 6.2, the read strobe for an

area for which the RDNn bit is set to 1 is negated

one half-state earlier than that for an area for

which the RDNn bit is cleared to 0. The read data

setup and hold time specific ations are also one

half-state earlier.

0: In an area n read access, the RD is negated at

the end of the read cycle

1: In an area n read access, the RD is negated

one half-state before the end of the read cycle

(n = 7 to 0)

Bus cycle

Data

RDNn = 0

RDNn = 1

Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space)

Section 6 Bus Controller (BSC)

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6.3.5 CS

CSCS

CS Assertion Period Control Registers H, L (CSACRH, CSACRL)

CSACRH and CSACRL select whether or not the assertion period of the basic bus interface chip

select signals (CSn) and address signals is to be extended. Extending the assertion period of the

CSn and address signals allows flexible interf acing to external I/O devices.

• CSACRH

Bit Bit Name Initial Value R/W Description

CSXH7

CSXH6

CSXH5

CSXH4

CSXH3

CSXH2

CSXH1

CSXH0

R/W

CS and Address Signal Assertion Period

Control 1

These bits specify whether or not the T

cycle is

to be inserted (see figure 6.3). When an area

for which the CSXHn bit is set to 1 is accessed,

a one-state Th cycle, in whic h only the CSn and

address signals are asserted, is inserted before

the normal access cycle.

0: In area n basic bus interface access, the CS

and address assert ion peri od (Th) is not

extended

1: In area n basic bus interface access, the CS

and address assert ion peri od (Th) is ext end ed

(n = 7 to 0)

• CSACRL

Bit Bit Name Initial Value R/W Description

CSXT7

CSXT6

CSXT5

CSXT4

CSXT3

CSXT2

CSXT1

CSXT0

R/W

CS and Address Signal Assertion Period

Control 2

These bits specify whether or not the Tt cycl e

shown in figure 6.3 is to be inserted. When an

area for which the CSXTn bit is set to 1 is

accessed, a one-st ate Tt cycle, in which only

the CSn and address signals are asserted, is

inserted before the normal access cycle.

0: In area n basic bus interface access, the CS

and address assert ion peri od (Tt) is not

extended

1: In area n basic bus interface access, the CS

and address assert ion peri od (Tt) is extended

(n = 7 to 0)

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Address

T1T2T3Tt

Bus cycle

Data

HWR, LWR

Write

Data

Read

Figure 6.3 CS

CSCS

CS and Address Assertion P eriod Exte nsion (Example of 3-Stat e Access Space

and RDNn = 0)

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6.3.6 Area 0 Burst ROM Interface Control Register (BROMCRH)

Area 1 Burst ROM Interface Control Register (BROMCRL)

BROMCRH an d BROMCRL are used to mak e burst ROM interface settings. Area 0 and area 1

burst ROM interface settin gs can be made independen tly in BROMCRH and BROMCRL,

respectively.

Bit Bit Name Initial Value R/W Description

7 BSRMn 0 R/W Burst ROM Interface Select

Selects the basic bus interface or burst ROM

interface.

0: Basic bus interface space

1: Burst ROM interface space

BSTSn2

BSTSn1

BSTSn0

R/W

Burst Cycle Select

These bits select the num ber of bur st cy cle

states.

000: 1 state

001: 2 states

010: 3 states

011: 4 states

100: 5 states

101: 6 states

110: 7 states

111: 8 states

3, 2 —All 0 R/W Reserved

These bits are always read as 0. The initial

value should not be changed.

0BSWDn1

BSWDn0 0

0R/W

R/W Burst Word Number Select

These bits select the number of words that can

be burst-accessed on the burst ROM interface.

00: Maximum 4 words

01: Maximum 8 words

10: Maximum 16 words

11: Maximum 32 words (n = 1 or 0)

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6.3.7 Bus Control Register (BCR)

BCR is used for idle cycle settings, selection of the external bus released state protocol, enabling

or disabling of the write data buffer function, and enabling or disabling of WAIT pin input.

Bit Bit Name Initial Value R/W Description

15 BRLE 0 R/W External Bus Release Enable

Enables or disables external bus release.

0: External bus release disabled

BREQ, BACK, and BREQO pins can be used

as I/O ports

1: External bus release enabled

14 BREQOE 0 R/W BREQO Pin Enable

Controls outputting the bus request signal

(BREQO) to the external bus master in the

external bus released state, when an internal

bus master pe rforms an external address space

access, or when a refresh request is generated.

0: BREQO output disabled

BREQO pin can be used as I/O port

1: BREQO output enabled

13 —0R/WReserved

This bit can be read from or written to.

However, the write value should always be 0.

12 IDLC 1 R/W Idle Cycle State Number Select

Specifies the number of states in the idle cycle

set by ICIS2 to ICIS0.

0: I dle cycle comprises 1 st ate

1: Idle cycle comprises 2 states

11 ICIS1 1 R/W Idle Cycle Insert 1

When consecutive external read cycles are

performed in different area s, an idle cy cle ca n

be inserted between the bus cycles.

0: Idle cycle not inserted

1: Idle cycle inserted

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Bit Bit Name Initial Value R/W Description

10 ICIS0 1 R/W Idle Cycle Insert 0

When an external read cycle and external write

cycle are performed co nse cutively, an idle cycle

can be inserted between the bus cycles.

0: Idle cycle not inserted

1: Idle cycle inserted

9 WDBE 0 R/W Write Data Buffer Enable

The write data buffer function can be used for

an external write cycle or DMAC single address

transfer cycle.

0: Write data buffer function not used

1: Write data buffer function used

8WAITE0 R/WWAIT Pin Enable

Selects enablin g or disabl ing of wa it input by

the WAIT pin.

0: Wait input by WAIT pin disabl ed

WAIT pin can be used as I/O port

1: Wait input by WAIT pin enabled

—0R/WReserved

These are readable/writable bits, but the write

value should always be 0.

2 ICIS2 0 R/W Idle Cycle Insert 2

When an external write cy cle and ext ernal read

cycle are performed co nse cutively, an idle cycle

can be inserted between the bus cycles.

0: Idle cycle not inserted

1: Idle cycle inserted

Note: Bit 2 is a reserved bit in the H8S/2678

Group. This bit is reada ble /wr ita ble, but

the write value should always be 0.

1, 0 —All 0 R/W Reserved

These bits can be read from or written to.

However, the write value should always be 0.

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6.3.8 DRAM Control Register (DRAMCR)

DRAMCR is used to make DRAM/synchronous DRAM* interface settings.

Note: * The synchronous DRAM interface is not supported in the H8S/2678 Group.

Bit Bit Name Initial Value R/W Description

15 OEE 0 R/W OE Output Enable

The OE signal used when EDO page mode

DRAM is connected can be output from the

(OE) pin. The OE signal is common to all areas

designated as DRAM space.

When the synchronous DRAM is connected,

the CKE signal can be output from the (OE) pin.

The CKE signal is common to the continuous

synchronous DRAM spac e.

0: OE/CKE signal output disabled

(OE)/(CKE) pin can be used as I/O port

1: OE/CKE signal output enabled

14 RAST 0 R/W RAS Assertion Timing Select

Selects whether, in DRAM access, the RAS

signal is asserted from the start of the Tr cycl e

(rising edge of φ) or from the falling edge of φ.

Figure 6.4 shows the relationship between the

RAST bit setting and the

AS assertion timing.

The setting of this bit applies to all areas

designated as DRAM space.

0: RAS is asserted from φ falling edge in Tr

cycle

1: RAS is asserted from start of Tr cycle

13 —0R/WReserved

This bit can be read from or written to.

However, the write value should always be 0.

Section 6 Bus Controller (BSC)

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Bit Bit Name Initial Value R/W Description

12 CAST 0 R/W Column Address Output Cycle Number Select

Selects whether the column address output

cycle in DRAM access comprises 3 states or 2

states. The setting of this bit applies to all areas

designated as DRAM space.

0: 2 states

1: 3 states

11 —0R/WReserved

This bit can be read from or written to.

However, the write value should always be 0.

RMTS2

RMTS1

RMTS0

R/W

DRAM/Continuous Synchronous DRAM Space

Select

These bits designate DRAM/continuous

synchronous DRAM space for areas 2 to 5.

When continuous DRAM space is set, it is

possible to connect large-capacity DRAM

exceeding 2 Mbytes per area. In this case, the

RAS signal is output from the CS2 pin.

When continuous synchronous DRAM space is

set, it is possible to connect large-capacity

synchronous DRAM exceeding 2 Mbytes per

area. In this case, the RAS, CAS, and WE

signals are output from CS2, CS3, and CS4

pins, respec tively. When synchronous DRAM

mode is set, the mode registers of the

synchronous DRAM can be set.

000: Normal space

001: Normal space in areas 3 to 5

DRAM space in area 2

010: Normal space in areas 4 and 5

DRAM space in areas 2 and 3

011: DRAM space in areas 2 to 5

100: Continuous synchronous DRAM space

(setting prohibited in the H8S/2678 Group)

101: Synchronous DRAM mode setting (setting

prohibited in the H8S/2678 Group)

110: Setting prohibited

111: Continuous DRAM space in areas 2 to 5

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Bit Bit Name Initial Value R/W Description

7 BE 0 R/W Burst Access Enable

Selects enabling or disabling of burst access to

areas designated as DRAM/continuous

synchronous DRAM space. DRAM/continuous

synchronous DRAM space burst access is

performed in fast page mode. When using EDO

page mode DRAM, the OE signal must be

connected.

0: Full access

1: Access in fast page mode

6 RCDM 0 R/W RAS Down Mode

When access to DRAM space is interrupted by

an access to normal bus space, an access to

an internal I/O register, etc., this bit selects

whether the RAS signal is held low whil e

waiting for the next DRAM access (RAS down

mode), or is driven high again (RAS up mode).

The setting of this bit is valid only when the BE

bit is set to 1.

If this bit is cleared to 0 when set to 1 in the

AS down state, the

AS down state is clear ed

at that point, and RAS goes high.

When continuous synchronous DRAM space is

set, reading from and writing to this bit is

enabled. However, the setting does not affect

the operation.

0: RAS up mode selected for DRAM space

access

1: RAS down mode selected for DRAM space

access

Section 6 Bus Controller (BSC)

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Bit Bit Name Initial Value R/W Description

5 DDS 0 R/W DMAC Single Address Transfer Option

Selects whether full access is always performed

or burst access is enabled when DMAC single

address transfer is perform ed on the

DRAM/synchronous DRAM interface.

When the BE bit is cleared to 0 in DRAMCR,

disabling DRAM/synchronous DRAM burst

access, DMAC single address transfer is

performed in full access mode regardless of the

setting of this bit.

This bit has no effect on other bus master

external accesses or DMAC dual address

transfers.

0: Full access is always executed

1: Burst access is enabled

4 EDDS 0 R/W EXDMAC Single Address Transfer Option

Selects whether full access is always performed

or burst access is enabled when EXDMAC

single address transfer is perfo rm ed on the

DRAM/synchronous DRAM interface.

When the BE bit is cleared to 0 in DRAMCR,

disabling DRAM/synchronous DRAM burst

access, EXDMAC single address transfer is

performed in full access mode regardless of the

setting of this bit.

This bit has no effect on other bus master

external accesses or EXDMAC dual address

transfers.

0: Full access is always executed

1: Burst access is enabled

3—0R/WReserved

This bit can be read from or written to.

However, the write value should always be 0.

Section 6 Bus Controller (BSC)

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Bit Bit Name Initial Value R/W Description

MXC2

MXC1

MXC0

R/W

Address Multiplex Select

These bits select the size of the shift toward the

lower half of the row address in row

address/column address multiplexing. In burst

operation on the DRAM/synchronous DRAM

interface, these bits also select the row address

bits to be us ed for comparison.

When the MXC2 bit is set to 1 while continuous

synchronous DRAM space is set, the address

precharge setting command (Precharge-sel) is

output to the upper column address. For details,

refer to sections 6.6.2 and 6.7.2, Address

Multiplexing.

DRAM interface

000: 8-bit shift

• When 8-bit acce ss spa ce is des ign ated:

Row address bits A23 to A8 used for

comparison

• When 16-bit access space is designated:

Row address bits A23 to A9 used for

comparison

001: 9-bit shift

• When 8-bit acce ss spa ce is des ign ated:

Row address bits A23 to A9 used for

comparison

• When 16-bit access space is designated:

Row address bits A23 to A10 used for

comparison

010: 10-bit shift

• When 8-bit acce ss spa ce is des ign ated:

Row address bits A23 to A10 used for

comparison

• When 16-bit access space is designated:

Row address bits A23 to A11 used for

comparison

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Bit Bit Name Initial Value R/W Description

011: 11-bit shift

• When 8-bit acce ss spa ce is des ign ated:

Row address bits A23 to A11 used for

comparison

When 16-bit access space is designated:

Row address bits A23 to A12 used for

comparison

Synchronous DRAM interface

100: 8-bit shift

• When 8-bit acce ss spa ce is des ign ated:

Row address bits A23 to A8 used for

comparison

• When 16-bit access space is designated:

Row address bits A23 to A9 used for

comparison

The precharge-sel is A15 to A9 of the

column addr es s.

101: 9-bit shift

• When 8-bit acce ss spa ce is des ign ated:

Row address bits A23 to A9 used for

comparison

• When 16-bit access space is designated:

Row address bits A23 to A10 used for

comparison

The precharge-sel is A15 to A10 of the

column addr es s.

110: 10-bit shift

• When 8-bit acce ss spa ce is des ign ated:

Row address bits A23 to A10 used for

comparison

• When 16-bit access space is designated:

Row address bits A23 to A11 used for

comparison

The precharge-sel is A15 to A11 of the

column addr es s.

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Bit Bit Name Initial Value R/W Description

111: 11-bit shift

• When 8-bit acce ss spa ce is des ign ated:

Row address bits A23 to A11 used for

comparison

• When 16-bit access space is designated:

Row address bits A23 to A12 used for

comparison

The precharge-sel is A15 to A12 of the

column addr es s.

Address

RAST = 0 RAS

RAST = 1 RAS

TrTc1 Tc2

UCAS, LCAS

Bus cycle

Row address Column address

Figure 6.4 RAS

RASRAS

RAS Signal Assertion Timing

(2-State Column Address Output Cycle, Full Access)

6.3.9 DRAM Access Control Register (DRACCR)

DRACCR is used to set the DRAM/synchronous DRAM interface bus specifications.

Note: The synchronous DRAM interface is not supported in the H8S/2678 Group.

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• H8S/2678 Group

Bit Bit Name Initial Value R/W Description

7 DRMI 0 R/W Idle Cycle Insertion

An idle cycle can be in serted after a DRAM

read cycle when a continuous normal space

access cy cle follows a DRAM re ad cycle. Id le

cycle insertion conditions, setting of number of

states, etc., comply with settings of bits ICIS1,

ICIS0, and IDLC in BCR register

0: Idle cycle not inserted

1: Idle cycle inserted

6—0R/WReserved

This bit can be read from or written to.

However, the write value should always be 0.

4TPC1

TPC0 0

0R/W

R/W Precharge State Control

These bits select the number of states in the

RAS precharge cycle in normal access and

refreshing.

00: 1 state

01: 2 states

10: 3 states

11: 4 states

3, 2 —All 0 R/W Reserved

These bits can be read from or written to.

However, the write value should always be 0.

0RCD1

RCD0 0

0R/W

R/W RAS-CAS Wait Control

These bits select a wait cycle to be inserted

between the RAS assert cycle and CAS assert

cycle.

00: Wait cycle not inserted

01: 1-state wait cycle inserted

10: 2-state wait cycle inserted

11: 3-state wait cycle inserted

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• H8S/2678R Group

Bit Bit Name Initial Value R/W Description

15 DRMI 0 R/W Idle Cycle Insertion

An idle cycle can be in serted after a

DRAM/synchronous DRAM access cycle when

a continuous normal space access cycle follows

a DRAM/sync hronous DRAM a ccess cycle. Idl e

cycle insertion conditions, setting of number of

states, etc., comply with settings of bits ICIS2,

ICIS1, ICIS0, and IDLC in BCR register

0: Idle cycle not inserted

1: Idle cycle inserted

14 —0R/WReserved

This bit can be read from or written to.

However, the write value should always be 0.

12 TPC1

TPC0 0

0R/W

R/W Precharge State Control

These bits select the number of states in the

RAS precharge cycle in normal access and

refreshing.

00: 1 state

01: 2 states

10: 3 states

11: 4 states

11 SDWCD 0 R/W CAS Latency Control Cycle Disabled during

Continuous Synchronous DRAM Space Write

Access

Disables CAS latency control cycle (Tc1)

inserted by WTCR settings during sy nchronous

DRAM write access (see figure 6.5).

0: Enables CAS latency control cycle

1: Disables CAS latency control cycle

10 —0R/WReserved

This bit can be read from or written to.

However, the write value should always be 0.

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Bit Bit Name Initial Value R/W Description

8RCD1

RCD0 0

0R/W

R/W RAS-CAS Wait Control

These bits select a wait cycle to be inserted

between the RAS assert cycle and CAS assert

cycle. A 1- to 4-state wait cycle can be inserted.

00: Wait cycle not inserted

01: 1-state wait cycle inserted

10: 2-state wait cycle inserted

11: 3-state wait cycle inserted

7 to 4 —All 0 R/W Reserved

These bits can be read from or written to.

However, the write value should always be 0.

3 CKSPE 0 R/W Clock Suspend Enable

Enables clock suspend mode for extend read

data during DMAC and EXDMAC single

address transfer with the synchronous DRAM

interface.

0: Disables clo ck su spe nd mode

1: Enables clock suspend mode

2—0R/WReserved

This bit can be read from or written to.

However, the write value should always be 0.

0RDXC1

RDXC0 0

0R/W

R/W Read Data Extension Cycle Number Selection

Selects the number of read data extension

cycle (Tsp) in ser ti on state in clock susp end

mode. These bits are valid when the CKSPE bit

is set to 1.

00: Inserts 1state

01: Inserts 2state

10: Inserts 3state

11: Inserts 4state

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RAS

SDWCD 0

CAS

DQMU, DQML

CKE

Data bus

Address bus

PALL ACTV NOP WRIT NOP

Column address

Row address

Precharge-sel

Row address

Column address

High

RAS

SDWCD 1

CAS

DQMU, DQML

CKE

Data bus

Address bus

PALL ACTV NOP WRIT

Row address

Precharge-sel

Row address

Column address

High

Figure 6.5 CAS Latency Cont rol Cycle Disable Timing during Continuous Synchrono us

DRAM Space Write Access (for CAS Latency 2)

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6.3.10 Refresh Control Register (REFCR)

REFCR specifies DRAM/synchronous DRAM interface refresh control.

Note: The synchronous DRAM interface is not supported in the H8S/2678 Group.

Bit Bit Name Initial Value R/W Description

15 CMF 0 R/(W)*Compare Match Flag

Status flag that indicates a matc h between the

values of RTCNT and RTCOR.

[Clearing cond iti ons ]

• When 0 is written to CMF after reading CMF

= 1 while the RFSHE bit is cleared to 0

• When CBR refreshing is executed while the

RFSHE bit is set to 1

[Setting condition]

When RTCOR = RTCNT

14 CMIE 0 R/W Compare Match Interrupt Enable

Enables or disables interrupt requests (CMI) by

the CMF flag when the CMF flag is set to 1.

This bit is valid when refresh control is not

performed. When the refresh control is

performed, this bit is always cleared to 0 and

cannot be modified.

0: Interrupt request by CMF flag disabled

1: Interrupt request by CMF flag enabled

12 RCW1

RCW0 0

0R/W

R/W CAS-RAS Wait Control

These bits select the number of wait cycles to

be inserted between the CAS assert cycle and

RAS assert cycle in a DRAM/synchronous

DRAM refresh cycle.

00: Wait state not inserted

01: 1 wait state inserted

10: 2 wait states inserted

11: 3 wait states inserted

Note: *Only 0 can be written, to clear the flag.

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Bit Bit Name Initial Value R/W Description

11 —0R/WReserved

This bit can be read from or written to.

However, the write value should always be 0.

RTCK2

RTCK1

RTCK0

R/W

Refresh Counter Clock Select

These bits select the clock to be used to

increment the refresh counter. When the input

clock is selected with bits RTCK2 to RTCK0,

the refresh counter begins counting up.

000: Count operation halted

001: Count on φ/2

010: Count on φ/8

011: Count on φ/32

100: Count on φ/128

101: Count on φ/512

110: Count on φ/2048

111: Count on φ/4096

7 RFSHE 0 R/W Refresh Control

Refresh control can be performed. When

refresh control is not performed, the refresh

timer can be used as an interval timer.

0: Refresh control is not performed

1: Refresh control is performed

6 CBRM 0 R/W CBR Refresh Control

Selects CBR refreshing performed in parallel

with other external accesses, or execution of

CBR refreshing alone.

When the continuous synchronous DRAM

space is set, this bit can be read/written, bu t the

setting contents do not affect operations.

0: External access during CAS-before-RAS

refreshing is enabled

1: External access during CAS-before-RAS

refreshing is disabled

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Bit Bit Name Initial Value R/W Description

4RLW1

RLW0 0

0R/W

R/W Refresh Cycle Wait Control

These bits select the number of wait states to

be inserted in a DRAM interface CAS-be fore-

RAS refresh cycle/synchronous DRAM

interface auto-refre sh cycle. This setting applies

to all areas designated as DRAM/continuous

synchronous DRAM spac e.

00: No wait state inserted

01: 1 wait state inserted

10: 2 wait states inserted

11: 3 wait states inserted

3 SLFRF 0 R/W Self-Refresh Enable

If this bit is set to 1, DRAM/synchronous DRAM

self-refresh mode is selected when a transition

is made to the software standby state. This bit

is valid when the RFSHE bit is set to 1,

enabling refres h operations. It is cleared after

recovery from software standby mode.

0: Self-refreshing is disabled

1: Self-refreshing is enabled

TPCS2

TPCS1

TPCS0

R/W

Self-Refresh Precharge Cycle Control

These bits select the number of states in the

precharge cycle immediately after self-

refreshing.

The number of states in the precharge cycle

immediately after self-refreshing are added to

the number of states set by bits TPC1 and

TPC0 in DRACCR.

000: [TPC set value] states

001: [TPC set value + 1] states

010: [TPC set value + 2] states

011: [TPC set value + 3] states

100: [TPC set value + 4] states

101: [TPC set value + 5] states

110: [TPC set value + 6] states

111: [TPC set value + 7] states

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6.3.11 Refresh Timer Counter (RTCNT)

RTCNT is an 8-bit readable/writable up-counter. RTCNT counts up using the internal clock

selected by bits RTCK2 to RTCK0 in REFCR.

When RTCNT matches RTCOR (compare match), the CMF flag in REFCR is set to 1 and

RTCNT is cleared to H'00. If the RFSHE bit in REFCR is set to 1 at this time, a refresh cycle is

started. If th e RFSHE bit is cleared to 0 and th e CMI E bit in REFCR is set to 1, a com pare match

interrupt (CMI) is generated.

RTCNT is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

6.3.12 Refresh Time Constant Register (RTCOR)

RTCOR is an 8-bit readable/writable register that sets th e period for compare match op e r a tions

with RTCNT.

The values of RTCOR and RTCNT are constantly compared, and if they match, the CMF flag in

REFCR is set to 1 and RTCNT is cleared to H'00.

RTCOR is initialized to H'FF by a reset and in hardware standby mod e. It is not initialized in

software standby mode.

6.4 Bus Control

6.4.1 Area Division

The bus controller divides the 16-Mbyte address space into eight areas, 0 to 7, in 2-Mbyte units,

and performs bus control for external address space in area units. Chip select signals (CS0 to CS7)

can be output for each area. In normal mode, a part of area 0, 64-kbyte address space, is

controlled . Figur e 6.6 shows an outline o f the m e mor y map.

Note: Normal mode is not av ailable in this LSI.

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Area 0

(2 Mbytes)

H'000000

H'FFFFFF

(1) (2)

H'0000

H'1FFFFF

H'200000 Area 1

(2 Mbytes)

H'3FFFFF

H'400000 Area 2

(2 Mbytes)

H'5FFFFF

H'600000 Area 3

(2 Mbytes)

H'7FFFFF

H'800000 Area 4

(2 Mbytes)

H'9FFFFF

H'A00000 Area 5

(2 Mbytes)

H'BFFFFF

H'C00000 Area 6

(2 Mbytes)

H'DFFFFF

H'E00000 Area 7

(2 Mbytes)

H'FFFF

Advanced mode Normal mode*

Note: * Not available in this LSI

Figure 6.6 Area Divisions

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6.4.2 Bus Specifications

The external address space bus specifications consist of five elements: bus width, number of

access states, number of program wait states, read strobe timing, and chip select (CS) assertion

period extension states. The bus width and number of access states for on-chip memory and

internal I/O registers are fixed, and are not affected by the bus controller.

Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit

bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected

functions as a 16-bit access space. If all areas are designated as 8-bit access space, 8-bit bus mode

is set; if any area is designated as 16-bit access space, 16-bit bus mode is set.

Number of Access States: Two or three access states can be selected with ASTCR. An area for

which 2-state access is selected functions as a 2-state access space, and an area for which 3-state

access is selected functions as a 3-state access space. With the DRAM or synchronous DRAM

interface and burst ROM interface, the number of access states may be determined without regard

to the setting of ASTCR.

When 2-state access space is designated, wait insertion is disabled. When 3-state access space is

designated, it is possible to insert program waits by means of the WTCRA and WTCRB, and

external waits by means of the WAIT pin.

Note: The synchronous DRAM interface is not supported in the H8S/2678 Group.

Number of Program Wait States: When 3-state access space is designated by ASTCR, the

number of progr am wait states to be inserted automatically is selected with WTC RA and WTCRB.

From 0 to 7 program wait states can be selected. Table 6.2 shows the bus specifications (bus

width, and number of access states and program wait states) for each basic bus interface area.

Section 6 Bus Controller (BSC)

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Table 6.2 Bus Specifications for Each Area (Basic Bus Interface)

ABWCR ASTCR WTCRA, WTCRB Bus Specifications (Basic Bus Interface)

ABWn ASTn Wn2 Wn1 Wn0 Bus Width Access

States Program Wait

States

00——— 16 2 0

1000 3 0

10 2

100 4

10 6

10——— 820

1000 3 0

10 2

100 4

10 6

(n = 0 to 7)

Read Strobe Timi ng: RDNCR can be used to select either of two negation timings (at the end of

the read cycle or one half-state before the end of the read cycle) for the read strobe (RD) used in

the basic bus interface space.

Chip Select ( CS

CSCS

CS) Assertion Period Extension States: Some external I/O devices require a setup

time and hold time between address and CS signals and strobe signals such as RD, HWR, and

LWR. CSACR can be used to insert states in which only the CS, AS, and address signals are

asserted before and after a basic bus space access cycle.

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6.4.3 Memory Interfaces

The memory interfaces in this LSI comprise a basic bus interface that allows direct connection of

ROM, SRAM, and so on; a DRAM interface that allows direct connection of DRAM; a

synchronous DRAM interface* that allows direct connection of synchronous DRAM; and a burst

ROM interface that allows direct connection of burst ROM. The interface can be selected

independently for each area.

An area for which the basic bus interface is designated functions as normal space, an area for

which the DRAM interface is designated functions as DRAM space, an area for which the

synchronous DRAM interface is designated functions as continuous synchronous DRAM space,

and an area for which the burst ROM interface is designated functions as burst ROM space.

The initial state of each area is b a sic bus interface, 3-state access space. The initial bu s width is

selected according to the operating mode.

Note: * The synchronous DRAM interface is not supported in the H8S/2678 Group.

Area 0: Area 0 includes on-chip ROM in expanded mode with on-chip ROM enabled and the

space excluding on-chip ROM is external address space, and in expanded mode with on-chip

ROM disabled, all of area 0 is external address space.

When area 0 external space is accessed, the CS0 signal can be output.

Either basic bus interface or burst ROM interface can be selected for area 0.

Area 1: In externally expanded mode, all of area 1 is external address space.

When area 1 external address space is accessed, the CS1 signal can be output.

Either basic bus interface or burst ROM interface can be selected for area 1.

Areas 2 to 5: In externally expanded mode, areas 2 to 5 are all external address space.

When area 2 to 5 external space is accessed, signals CS2 to CS5 can be output.

Basic bus interface, DRAM interface, or synchronous DRAM interface can be selected for areas 2

to 5. With the DRAM interface, signals CS2 to CS5 are used as RAS signals.

If areas 2 to 5 are designated as continuous DRAM space, large-capacity (e.g. 64-Mbit) DRAM

can be connected. In this case, the CS2 signal is used as the RAS signal for the continuous DRAM

space.

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If areas 2 to 5 are designated as continuous synchronous DRAM space, large-capacity (e.g. 64-

Mbit) synchronous DRAM can be connected. In this case, the CS2, CS3, CS4, and CS5 pins are

used as the RAS, CAS, WE, and CLK signals for the continuous synchronous DRAM space. The

OE pin is used as the CKE signal.

Area 6: In externally expanded mode, all of area 6 is external space.

When area 6 external space is accessed, the CS6 signal can be output.

Only the basic bus interface can be used for area 6.

Area 7: Area 7 includes the on-chip RAM and internal/O registers. In externally expanded mode,

the space excluding the on-chip RAM and internal I/O registers is external address space. The on-

chip RAM is enabled when the RAME bit is set to 1 in the system control register (SYSCR); when

the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding addresses are in

external address space.

When area 7 external address space is accessed, the CS7 signal can be output.

Only the basic bus interface can be used for the area 7 memory interface.

6.4.4 Chip Select Signals

This LSI can ou tput ch ip select signals (CS0 to CS7) for areas 0 to 7. The signal outputs low when

the corresponding external space area is accessed. Figure 6.7 shows an example of CS0 to CS7

signals output timing.

Enabling or disabling of CS0 to CS7 signals output is set by the data direction register (DDR) bit

for the port corresponding to the CS0 to CS7 pins.

In expanded mode with on-chip ROM disabled, the CS0 pin is placed in the output state after a

reset. Pins CS1 to CS7 are placed in the input state after a reset and so the corresponding DDR bits

should be set to 1 when outputting signals CS1 to CS7.

In expanded mode with on-chip ROM enabled, pins CS0 to CS7 are all placed in the input state

after a reset and so the corresponding DDR bits should be set to 1 when outpu tting signals CS0 to

CS7.

When areas 2 to 5 are designated as DRAM space, outputs CS2 to CS5 are used as RAS signals.

When areas 2 to 5 are designated as continuous synchronous DRAM space in the H8S/2678R

Group, output s CS2 to CS5 are used as RAS, CAS, WE, and CLK signals.

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Bus cycle

T1T2T3

Area n external address

Address bus

CSn

Figure 6.7 CSn

CSnCSn

CSn Signal Output Timing (n = 0 to 7)

6.5 Basic Bus Interface

The basic bus interface enables direct connection of ROM, SRAM, and so on.

6.5.1 Data Size and Data Alignment

Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus

controller has a data alignment function, and when accessing external address space, controls

whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus

specifications for the area being accessed (8-bit access space or 16-bit access space) and the data

size.

8-Bit Access Space: Figure 6.8 illustrates data alig nment control for the 8-bit access sp ace. With

the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of

data that can be accessed at one time is one byte: a word access is performed as two byte accesses,

and a longword access, as four byte accesses.

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D15 D8 D7 D0

Upper data bus Lower data bus

Byte size

Word size 1st bus cycle

2nd bus cycle

Longword

size

1st bus cycle

2nd bus cycle

3rd bus cycle

4th bus cycle

Figure 6.8 Access Sizes and Data Alignment Control (8-Bit Access Space)

16-Bit Access Space: Figure 6. 9 illustrates data alignment control for the 16-bit access space.

With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are

used for accesses. The amount of data that can be accessed at one time is one byte or one word,

and a longword access is executed as two word accesses.

In byte access, whether the upper or lower data bus is used is determined by whether the address is

even or odd. The upper data bus is used for an even address, and the lower data bus for an odd

address.

D15 D8 D7 D0

Upper data bus Lower data bus

Byte size

Word size

1st bus cycle

2nd bus cycle

Longword

size

• Even address

Byte size • Odd address

Figure 6.9 Access Sizes and Data Alignment Control (16-bit Access Space)

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6.5.2 Valid Strobes

Table 6.3 shows the data buses used and valid strobes for the access spaces.

In a read, the RD signal is valid for both the upper and the lower half of the data bus. In a write,

the HWR signal is valid for the upper half of the data bus, and the LWR signal f or the lower half.

Table 6.3 Data Buses Used and Valid Strobes

Area Access

Size Read/

Write Address Valid

Strobe Upper Data Bus

(D15 to D8) Lower Data Bus

(D7 to D0)

Byte Read —RD Valid Invalid

8-bit access

space Write —HWR Hi-Z

Byte Read Even RD Valid Invalid16-bit access

space Odd Invalid Valid

Write Even HWR Valid Hi-Z

Odd LWR Hi-Z Valid

Word Read —RD Valid Valid

Write —HWR, LWR Valid Valid

Notes: Hi-Z: High-impedance state

Invalid: Input state; input value is ignored.

6.5.3 Basic Operation Timing

8-Bit, 2-State Access Space: Figure 6.10 shows the bus timing for an 8-bit, 2-state access space.

When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The

LWR pin is always fixed high. Wait states can be inserted.

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Bus cycle

Address bus

CSn

D15 to D8 Valid

D7 to D0 Invalid

Read

HWR

LWR

D15 to D8 Valid

D7 to D0 High impedance

Write

High

Notes: 1. n = 0 to 7

2. When RDNn = 0

Figure 6.10 Bus Timing for 8-Bit, 2-State Access Space

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8-Bit, 3-State Access Space: Figure 6.11 shows the bus timing for an 8-bit, 3-state access space.

When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The

LWR pin is always fixed high. Wait states can be inserted.

Bus cycle

T1T2

Address bus

CSn

D15 to D8 Valid

D7 to D0 Invalid

Read

HWR

LWR

D15 to D8 Valid

D7 to D0

Write

High

High impedance

Notes: 1. n = 0 to 7

2. When RDNn = 0

Figure 6.11 Bus Timing for 8-Bit, 3-State Access Space

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16-Bit, 2-State Access Space: Figures 6.12 to 6.14 show bus timings for a 16-bit, 2-state access

space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used

for odd addresses, and the lower half (D7 to D0) for even addresses. Wait states cannot be

inserted.

Bus cycle

Address bus

CSn

D15 to D8 Valid

D7 to D0 Invalid

Read

HWR

LWR

D15 to D8 Valid

D7 to D0

Write

High

High impedance

Notes: 1. n = 0 to 7

2. When RDNn = 0

Figure 6.12 Bus Timing for 16-Bit, 2-State Access Space

(Even Address Byte Access)

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Bus cycle

Address bus

CSn

D15 to D8 Invalid

D7 to D0 Valid

Read

HWR

LWR

D15 to D8

D7 to D0 Valid

Write

High

High impedance

Notes: 1. n = 0 to 7

2. When RDNn = 0

Figure 6.13 Bus Timing for 16-Bit, 2-State Access Space

(Odd Address Byte Access)

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Bus cycle

Address bus

CSn

D15 to D8 Valid

D7 to D0 Valid

Read

HWR

LWR

D15 to D8 Valid

D7 to D0 Valid

Write

Notes: 1. n = 0 to 7

2. When RDNn = 0

Figure 6.14 Bus Timing for 16-Bit, 2-State Access Space

(Word Access)

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16-Bit, 3-State Access Space: Figures 6.15 to 6.17 show bus timings for a 16-bit, 3-state access

space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used

for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be

inserted.

Bus cycle

Address bus

CSn

D15 to D8 Valid

D7 to D0 Invalid

Read

HWR

LWR

D15 to D8 Valid

D7 to D0

Write

High

High impedance

Notes: 1. n = 0 to 7

2. When RDNn = 0

Figure 6.15 Bus Timing for 16-Bit, 3-State Access Space

(Even Address Byte Access)

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Bus cycle

Address bus

CSn

D15 to D8 Invalid

D7 to D0 Valid

Read

HWR

LWR

D15 to D8

D7 to D0 Valid

Write

High

High impedance

Notes: 1. n = 0 to 7

2. When RDNn = 0

Figure 6.16 Bus Timing for 16-Bit, 3-State Access Space

(Odd Address Byte Access)

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Bus cycle

Address bus

CSn

D15 to D8 Valid

D7 to D0 Valid

Read

HWR

LWR

D15 to D8 Valid

D7 to D0 Valid

Write

Notes: 1. n = 0 to 7

2. When RDNn = 0

Figure 6.17 Bus Timing for 16-Bit, 3-State Access Space

(Word Access)

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6.5.4 Wait Control

When accessing external space, this LSI can extend the bus cycle by inserting one or more wait

states (Tw). There are two ways of inserting wait states: program wait insertio n and pin wait

insertion using the WAIT pin.

Program Wait Insertion: From 0 to 7 wait states can be inser ted automatically between the T2

state and T3 state on an individual area basis in 3- state access space, according to the settings in

WTCRA and WTCRB.

Pin Wait Insertion: Se tting the WAITE bit to 1 in BCR enables wa it input by means of the

WAIT pin. When external space is accessed in this state, a program wait is first inserted in

accordance with the settings in WTCRA and WTCR B. If the WAIT pin is low at the falling edge

of φ in the last T2 or Tw state, another Tw state is inserted. If the WAIT pin is held low, Tw states are

inserted un til it goes high. This is useful when inserting sev e n or mor e Tw states, or when changing

the number of Tw states to be inserted for different external devices. The WAITE bit setting applies

to all areas. Figure 6.18 shows an example of wait state insertion timing.

The settings after a reset are: 3-state access, insertion of 7 program wait states, and WAIT input

disabled.

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By program wait

Address bus

Data bus Read data

Read

HWR, LWR

Write data

Write

WAIT

Data bus

By WAIT pin

Notes: 1. Downward arrows indicate the timing of WAIT pin sampling.

2. When RDN = 0

Figure 6.18 Example of Wait State Insertion Timing

6.5.5 Read Strobe (RD

RDRD

RD) Timing

The read strobe (RD) timing can be changed for individual areas by setting bits RDN7 to RDN0 to

1 in RDNCR. Figure 6.19 shows an example of the timing when the read strobe timing is changed

in basic bus 3-state access space.

When the DMAC or EXDMAC is used in single address mode, note that if the RD timing is

changed by setting RDNn to 1, the RD timing will change relative to the rise of DACK or

EDACK.

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Bus cycle

Address bus

CSn

Data bus

DACK,

EDACK

Data bus

RDNn = 0

RDNn = 1

Figure 6.19 Example of Read Strobe Timing

6.5.6 Extension of Chip Select (CS

CSCS

CS) Assertion Period

Some external I/O devices require a setup time and hold time between address and CS signals and

strobe signals such as RD, HWR, and LWR. Settings can be made in the CSACR register to insert

states in which only the CS, AS, and address signals are asserted before and after a basic bus space

access cycle. Extension of the CS assertion period can be set for individual areas. With the CS

assertion extension period in write access, the data setup and hold times are less stringent since the

write data is outp ut to the data bus.

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Figure 6.20 shows an example of the timing when the CS assertion period is extended in basic bus

3-state access space.

Address bus

Bus cycle

Data bus

HWR, LWR

Write

Data bus

CSn

Read

(when

RDNn = 0) Read data

Write data

Figure 6.20 Example of Timing when Chip Select Assertion Period Is Extended

Both extension state Th inserted before the basic bus cycle and extension state Tt inserted after the

basic bus cycle, or only one of these, can be specified for individual areas. Insertion or non-

insertion can be specified for the Th state with the upper 8 bits (CSXH7 to CSXH0) in the CSACR

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6.6 DRAM Interface

In this LSI, external space areas 2 to 5 can be designated as DRAM space, and DRAM interfacing

performed. The DRAM interface allows DRAM to be directly connected to this LSI. A DRAM

space of 2, 4, or 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR. Burst

operation is also possible, using fast page mode.

6.6.1 Setting DRAM Space

Areas 2 to 5 are designa ted as DRAM space by setting bits RMTS2 to RMTS0 in DRAMCR. The

relation between the settings of bits RMTS2 to RMTS0 and DRAM space is shown in table 6.4.

Possible DRAM space setting s are: on e area (area 2), two areas (areas 2 and 3), four areas (areas 2

to 5), and continuous area (areas 2 to 5).

Table 6.4 Relation between Settings of Bits RMTS2 to RMT S0 and DRAM Spa ce

RMTS2 RMTS1 RMTS0 Area 5 Area 4 Area 3 Area 2

0 1 Normal space Normal space Normal space DRAM space

0 Normal space Normal space DRAM space DRAM space

1 DRAM space DRAM spac e DRAM space DRAM space

0 Continuous synchronous DRAM space*

1 Mode register settings of sy nchronous DRAM*

0 Reserved (setting prohibited)

1 Continuous

DRAM space Continuous

DRAM space

Note: *Reserved (setting prohibited) in the H8S/2678 Group.

With continuous DRAM space, RAS2 is valid. The bus specifications (bus width, number of wait

states, etc.) for continuous DRAM space conform to the settings for area 2.

6.6.2 Address M ult iplexing

With DRAM space, the row address and co lu mn addr ess are mu ltiplexed. In address multiplex ing,

the size of the shift of the row address is selected with bits MXC2 to MXC0 in DRAMCR. Tab le

6.5 shows the relation between the settings of MXC2 to MXC0 and the shif t size.

The MXC2 bit should be cleared to 0 when the DRAM interface is used.

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Table 6.5 Relation between Set tings of Bits MXC2 t o MXC0 and Ad dress Multiplexing

DRAMCR Address Pins

MXC2 MXC1 MXC0 Shift

Size A23

A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 8 bits A23

A16

A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A80

1 9 bits A23

A16

A15 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9

0 10 bits A23

A16

A15 A14 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10

1 11 bits A23

A16

A15 A14 A13 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11

Row

address

1xx Reserved (setting prohibited)

0*xx —A23

A16

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0Column

address

1*xx Reserved (setting prohibited)

Legend: x: Don’t care

Note: *In the H8S/2678 Group, address pins are A23 to A0.

6.6.3 Data Bus

If a bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is

designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM

space. In 16-bit DRAM space, ×16-bit configuration DRAM can be connected directly.

In 8-bit DRAM space the upper half of the data bus, D15 to D8, is enabled, while in 16-bit DRAM

space both the upper and lower halves of the data bus, D15 to D0, are enabled.

Access sizes and data alignment are the same as for the basic bus interface: see section 6.5.1, Data

Size and Data Alignment.

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6.6.4 Pins Used for DRAM Interface

Table 6.6 shows the pins used for DRAM interfacing and their functions. Since the CS2 to CS5

pins are in the input state after a reset, set the corresponding DDR to 1 when RAS2 to RAS5

signals are output.

Table 6.6 DRAM Interface Pins

Pin With DRAM

Setting Name I/O Function

HWR WE Write enable Output Write enable for DRAM space

access

CS2 RAS2/RAS Row address strobe 2/

row address strobe Output Row address strobe when area

2 is designated as DRAM space

or row address strobe when

areas 2 to 5 are designated as

continuous DRAM space

CS3 RAS3 Row address strobe 3 Output Row address strobe when area

3 is designated as DRAM space

CS4 RAS4 Row address strobe 4 Output Row address strobe when area

4 is designated as DRAM space

CS5 RAS5 Row address strobe 5 Output Row address strobe when area

5 is designated as DRAM space

UCAS UCAS Upper column address

strobe Output Upper column address strobe

for 16-bit DRAM space access

or column address strobe for 8-

bit DRAM space access

LCAS LCAS Lower column address

strobe Output Lower column address strobe

signal for 16-bit DRAM space

access

RD, OE OE Output enable Output Output enable signal for DRAM

space access

WAIT WAIT Wait Input Wait request signal

A15 to A0 A15 to A0 Address pins Output Row address/column address

multiplexed output

D15 to D0 D15 to D0 Data pins I/O Data input/output pins

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6.6.5 Basic Timing

Figure 6.21 shows the basic access timing for DRAM space.

The four states of the basic timing consist of one Tp (precharge cycle) state, one Tr (row address

output cycle) state, and the Tc1 and two Tc2 (column address output cycle) states.

RASn (CSn)

Read

Write

UCAS, LCAS

WE (HWR)

OE (RD)

Data bus

WE (HWR)

OE (RD)

Data bus

Address bus

TrTc1 Tc2

Row address

High

Column address

Note: n = 2 to 5

Figure 6.21 DRAM Basic Access Timing (RAST = 0, CAST = 0)

When DRAM space is accessed, the RD signal is output as the OE signal for DRAM. When

connecting DRAM provided with an EDO page mode, the OE signal should be connected to the

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(OE ) pin of the DRAM. Setting the OEE bit to 1 in DRAMCR enables the OE signal for DRAM

space to be output from a dedicated OE pin. In this case, the OE signal for DRAM space is output

from both the RD pin and the (OE) pin, but in external read cycles for other than DRAM space,

the signal is output only from the RD pin.

6.6.6 Column Address Output Cycle Control

The column address output cycle can be changed from 2 states to 3 states by setting the CAST bit

to 1 in DRAMCR. Use the setting that gives the op timum specification values (CAS pulse width,

etc.) according to the DRAM connected and the operating frequency of this LSI. Figure 6.22

shows an example of the timing when a 3-state column address output cycle is selected.

RASn (CSn)

Read

Write

UCAS, LCAS

WE (HWR)

OE (RD)

Data bus

WE (HWR)

OE (RD)

Data bus

Address bus

Row address Column address

High

Note: n = 2 to 5

Figure 6.22 Example of Access Timing with 3-State Column Address Output Cycle

(RAST = 0)

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6.6.7 Row Address O ut put State Contro l

If the RAST bit is set to 1 in DRAMCR, the RAS signal goes low from the beginning of the Tr

state, and the row address hold time and DRAM read access time are changed relative to the fall of

the RAS signal. Use the optimum setting according to the DRAM connected and the operating

frequency of this LSI. Figure 6.23 shows an example of the timing when the RAS signal goes low

from the beginning of the Tr state.

RASn (CSn)

Read

Write

UCAS, LCAS

WE (HWR)

OE (RD)

Data bus

WE (HWR)

OE (RD)

Data bus

Address bus

Row address Column address

High

Note: n = 2 to 5

Figure 6.23 Example of Access Timing when RAS

RASRAS

RAS Signal Goes Low

from Beginning of Tr State (CAST = 0)

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If a row address hold time or read access time is necessary, mak in g a setting in bits RCD1 and

RCD0 in DRA CCR allows from one to th ree Trw states, in which ro w add r ess output is maintained,

to be inserted between the Tr cycle, in which the RAS signal goes low, and the Tc1 cycle, in which

the column address is output. Use the setting that gives the optimum row address signal hold time

relative to the f a llin g edge of the RAS signal according to the DRAM connected and the operating

frequency of this LSI. Figure 6.24 shows an example of the timing when one Trw state is set.

RASn (CSn)

Read

Write

UCAS, LCAS

WE (HWR)

OE (RD)

Data bus

WE (HWR)

OE (RD)

Data bus

Address bus

TrTrw Tc1 Tc2

Row address Column address

High

Note: n = 2 to 5

Figure 6.24 Example of Timing with O ne Ro w Address Output Maintenance State

(RAST = 0, CAST = 0)

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6.6.8 Precharge State Control

When DRAM is accessed, a RAS precharge time must be secured. With this LSI, one Tp state is

always inserted when DRAM space is accessed. From one to four Tp states can be selected by

setting bits TPC1 and TPC0 in DRAC CR. Set the optimu m number of Tp cycles according to the

DRAM connected and the operating frequency of this LSI. Figure 6.25 shows the timing when

two Tp states are inserted. The setting of bits TPC1 and TPC0 is also valid for Tp states in refresh

cycles.

RASn (CSn)

Read

Write

UCAS, LCAS

WE (HWR)

OE (RD)

Data bus

WE (HWR)

OE (RD)

Data bus

Address bus

Row address Column address

High

Note: n = 2 to 5

Figure 6.25 Example of Timing with Two-State Precharge Cycle

(RAST = 0, CAST = 0)

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6.6.9 Wait Control

There are two ways of inserting wait states in a DRAM access cycle: program wait insertion and

pin wait insertion using the WAIT pin.

Wait states are inser ted to extend the CAS assertion period in a read access to DRAM space, and

to extend the write data setup time relativ e to the f a lling edge of CAS in a write access.

Program Wait Insertion: When the bit in ASTCR corresponding to an area designated as DRAM

space is set to 1, from 0 to 7 wait states can be inserted automatically between the Tc1 state and Tc2

state, according to the settings in registers WTCRA an d WTCRB.

Pin Wait Insertion: When the WAITE bit in BCR is set to 1 and the ASTCR bit is set to 1, wait

input by means of the WAIT pin is enabled. When DRAM space is accessed in this state, a

program wait (Tw) is first inserted. If the WAIT pin is low at the falling edge of φ in the last Tc1 or

Tw state, another Tw state is inserted. If the WAIT pin is held low, Tw states are inserted until it

goes high.

Figures 6.26 and 6.27 show examples of wait cycle insertion timing in the case of 2-state and 3-

state column address output cycles.

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By program wait

Address bus

WAIT

By WAIT pin

RASn (CSn)

Read

Write

UCAS, LCAS

WE (HWR)

OE (RD)

Data bus

WE (HWR)

OE (RD)

Data bus

Row address Column address

High

Notes: Downward arrows indicate the timing of WAIT pin sampling.

n = 2 to 5

Figure 6.26 Example of Wait State Insertion Timing

(2-State Column Address Output)

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By program wait

Address bus

WAIT

By WAIT pin

RASn (CSn)

Read

Write

UCAS, LCAS

WE (HWR)

OE (RD)

Data bus

WE (HWR)

OE (RD)

Data bus

Row address Column address

High

Notes: Downward arrows indicate the timing of WAIT pin sampling.

n = 2 to 5

Figure 6.27 Example of Wait State Insertion Timing

(3-State Column Address Output)

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6.6.10 Byte Access Control

When DRAM with a ×16-bit configuration is connected, the 2-CAS access method is used for the

control signals needed for byte access. Figure 6.28 shows the control timing for 2-CAS access, and

figure 6.29 shows an example of 2-CAS DRAM connection.

High-Z

RASn (CSn)

UCAS

LCAS

WE (HWR)

OE (RD)

Upper data bus

Lower data bus

Address bus

Note: n = 2 to 5

Row address Column address

Write data

High

Figure 6.28 2-CAS Control Timing

(Upper Byte Write Access: RAST = 0, CAST = 0)

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This LSI

(Address shift size

set to 10 bits)

RASn (CSn)

2-CAS type 16-Mbit DRAM

1-Mbyte × 16-bit configuration

10-bit column address

RAS

UCAS UCAS

LCAS LCAS

HWR (WE)WE

RD (OE)OE

A9 A8

A10 A9

A8 A7

A7 A6

A6 A5

A5 A4

A4 A3

A3 A2

A2 A1

A1 A0

D15 to D0 D15 to D0

Row address input:

A9 to A0

Column address input:

A9 to A0

Figure 6.29 Example of 2-CAS DRAM Connection

6.6.11 Burst Operation

With DRAM, in addition to full access (no rmal access) in which data is accessed by outputting a

row address for each access, a fast page mode is also provided which can be used when making

consecutive accesses to the same row address. This mode enables fast (burst) access of data by

simply changing the column address after the row address has been output. Burst access can be

selected by setting the BE bit to 1 in DRAMCR.

Burst Access (Fast Page Mode): Figures 6.30 and 6.31 show the operation timing for burst

access. When there are consecutive access cycles for DRAM space, the CAS signal and column

address output cycles (two states) continue as long as the row address is the same for consecutive

access cycles. The row address used for the comparison is set with bits MXC2 to MXC0 in

DRAMCR.

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TrTc1 Tc2 Tc1 Tc2

RASn (CSn)

Read

Write

UCAS, LCAS

WE (HWR)

OE (RD)

Data bus

WE (HWR)

OE (RD)

Data bus

Address bus

Note: n = 2 to 5

Row address Column address 1 Column address 2

High

Figure 6.30 Operation Timing in Fast Page Mode

(RAST = 0, CAST = 0)

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TrTc1 Tc2 Tc3 Tc1 Tc2 Tc3

RASn (CSn)

Read

Write

UCAS, LCAS

WE (HWR)

OE (RD)

Data bus

WE (HWR)

OE (RD)

Data bus

Address bus

Note: n = 2 to 5

Row address Column address 1 Column address 2

High

Figure 6.31 Operation Timing in Fast Page Mode

(RAST = 0, CAST = 1)

The bus cycle can also be ex tended in burst access by inserting wait states. The wait state insertion

method and timing are the same as for full access. For details see section 6.6.9, Wait Control.

RAS Down Mode and RAS Up Mode: Even when burst operation is selected, it may happen that

access to DRAM space is not continuous, but is interrupted by access to another space. In this

case, if the RAS signal is held low during the access to the other space, burst operation can be

resumed when the same row address in DRAM space is accessed again.

• RAS Down Mode

To select RAS down mode, set both the RCDM bit and the BE bit to 1 in DRAMCR. If access

to DRAM space is interrupted and another space is accessed, the RAS signal is held low

during the access to the other space, and burst access is performed when the row address of the

next DRAM space access is the same as the row address of the pr evious DRAM space access.

Figure 6.32 shows an example of the timing in RAS down mode.

Note, however, that the RAS signal will go high if:

 a refresh operation is initiated in the RAS down state

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 self-refreshing is performed

 the chip enters software standby mode

 the external bus is released

 the RCDM bit or BE b it is clear ed to 0

If a transition is made to the all-module-clocks-stopped mode in the RAS down state, the clock

will stop with RAS low. To enter the all-module-clocks-stopped mode with RAS high, the

RCDM bit must be cleared to 0 before executing the SLEEP instruction.

Normal space

read DRAM space

read

TpTrTc1 Tc2 T1T2

DRAM space read

Tc1 Tc2

Note: n = 2 to 5

RASn (CSn)

UCAS, LCAS

Data bus

Address bus Row address Column address 1 Column address 2External address

Figure 6.32 Example of Operation Timing in RAS Down Mode

(RAST = 0, CAST = 0)

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• RAS Up Mode

To select RAS up mode, clear the RCDM bit to 0 in DRAMCR. Each time access to DRAM

space is interrupted and another space is accessed, the RAS signal goes high again. Burst

operation is only performed if DRAM space is continuous. Figure 6.33 shows an example of

the timing in RAS up mode.

Normal space

read

DRAM space

read

DRAM space read

Note: n = 2 to 5

RASn (CSn)

UCAS, LCAS

Data bus

Address bus Row address Column address 1 Column address 2 External address

Figure 6.33 Example of Operation Timing in RAS Up Mode

(RAST = 0, CAST = 0)

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6.6.12 Refresh Control

This LSI is provided with a DRAM refresh control function. CAS-before-RAS (CBR) refreshing

is used. In addition, self-refreshing can be executed when the chip enters the software standby

state.

Refresh control is enabled when any area is designated as DRAM space in accordance with the

setting of bits RMTS2 to RMTS0 in DRAMCR.

CAS-before-RAS (CBR) Refreshing: To select CBR re f reshing, set th e RFSHE bit to 1 in

REFCR.

With CBR refreshing, RTCNT counts up using the input clock selected by bits RTCK2 to RTCK0

in REFCR, and when the count matches the value set in RTCOR (compare match), refresh control

is performed. At the same time, RTCNT is reset and starts counting up again from H'00.

Refreshing is thus repeated at fixed intervals determined by RTCOR and bits RTCK2 to RTCK0.

Set a value in RTCOR an d bits RTCK2 to RTCK0 that will meet the refreshing interval

specification for the DRAM used.

When bits RTCK2 to RTCK0 in REFCR are set, RTCNT starts counting up. RTCNT and RTCOR

settings should therefore be completed before setting bits RTCK2 to RTCK0. RTCNT operation is

shown in figure 6.3 4, compare match timing in figure 6.35, and CBR refre sh timing in figur e 6.36.

When the CBRM bit in REFCR is cleared to 0, access to external space other than DRAM space is

performed in parallel during the CBR refresh period.

RTCOR

H'00

Refresh request

RTCNT

Figure 6.34 RTCNT Operation

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RTCNT

RTCOR N

H'00

Refresh request

signal and CMF bit

setting signal

Figure 6.35 Compare Match Timing

CSn (RASn)

Rc1

Rc2

UCAS, LCAS

Figure 6.36 CBR Refresh Timing

A setting can be made in bits RCW1 and RCW0 in REFCR to delay RAS signal output by one to

three cycles. Use bits RLW1 and RLW0 in REFCR to adjust the width of the RAS signal. The

settings of bits RCW1, RCW0, RLW1, and RLW0 are valid only in refresh operations.

Figure 6.37 shows the timing when bits RCW1 and RCW0 are set.

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CSn (RASn)

Rrw

Rc1

UCAS, LCAS

Rc2

Figure 6.37 CBR Refresh Timing

(RCW1 = 0, RCW0 = 1, RLW1 = 0, RLW0 = 0)

Depending on the DRAM used, modification of the WE signal may not be permitted during the

refresh period. In this case, the CBRM bit in REFCR should be set to 1. The bus controller will

then insert refresh cycles in appropriate breaks between bus cycles. Figure 6.38 shows an example

of the timin g when the CBRM bit is set to 1. In this case the CS signal is not controlled, and

retains its valu e prior to the start of the refresh period.

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A23 to A0

HWR (WE)

CAS

Normal space access request

RAS

Refresh period

Figure 6.38 Example of CBR Refresh Timing (CBRM = 1)

Self-Refreshing: A self-refresh mode (battery backup mode) is provided for DRAM as a kind of

standby mode. In this mode, refresh timing and refresh addresses are generated within the DRAM.

To select self-refreshing, set the RFSHE bit and SLFRF bit to 1 in REFCR. When a SLEEP

instruction is executed to enter softwar e standby mode, the CAS and RAS signals are output and

DRAM enters self-refresh mode, as shown in figure 6.39.

When software standby mode is exited, the SLFRF bit is cleared to 0 and self-refresh mode is

exited automatically. If a CBR refresh r e quest occurs when ma king a transition to sof twar e

standby mode, CBR refreshing is executed, then self-refresh mode is entered.

When using self-refresh mode, the OPE bit must not be cleared to 0 in the SBYCR register.

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TRp

TRr

UCAS, LCAS

Software

standby TRc3

HWR (WE)

CSn (RASn)

Note: n = 2 to 5

High

Figure 6.39 Self-Refresh Timing

In some DRAMs provided with a self-refresh mode, the RAS signal precharge time immediately

after self-refreshing is longer than the normal precharge time. A setting can be made in bits

TPCS2 to TPCS0 in REFCR to make the precharge time immediately after self-refreshing from 1

to 7 states longer than the normal precharge time. In this case, too, normal precharging is

performed according to the settin g of bits TPC1 and TPC0 in DRACCR, and therefore a settin g

should be made to give the optimum post-self-refresh precharge time, including this time. Figure

6.40 shows an example of the timing when the precharge time immediately after self-refreshing is

extended by 2 states.

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DRAM space write

rc3

rp1

rp2

Software

standby

Note: n = 2 to 5

RASn (CSn)

UCAS, LCAS

OE (RD)

WR (HWR)

Data bus

Address bus

Figure 6.40 Example of Timing when Precharge Time after Self-Refreshing Is Extended

by 2 Stat es

Refreshing and All-Module-Clo c ks-Stopped Mode: In this LSI, if the ACSE b it is set to 1 in

MSTPCRH, and then a SLEEP instruction is executed with the setting for all peripheral module

clocks to be stopped (MSTPCR = H'FFFF) or for operation of the 8-bit timer module alone

(MSTPCR = H'FFFE), and a transition is made to the sleep state, the all-module-clocks-stopped

mode is entered, in which the bus controller and I/O port clocks are also stopped. As the bus

controller clock is also stopped in this mode, CBR refreshing is no t exe cuted. If DRAM is

connected extern ally and DRAM data is to be retained in sleep mode, the ACSE bit must be

cleared to 0 in MSTPCRH.

6.6.13 DMAC and EXDMAC Si ngle Address Transfer Mode and DRAM Interf ace

When burst mode is selected on the DRAM interface, the DACK and EDACK output timing can

be selected with the DDS and EDDS bits in DRAMCR. When DRAM space is accessed in DMAC

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or EXDMAC single address mode at the same time, these bits select whether or not burst access is

to be performed.

When DDS = 1 or EDDS = 1: Burst access is performed by determining the address only,

irrespective of the bus master. With the DRAM interface, the DACK or EDACK output goes low

from the Tc1 state.

Figure 6.41 shows the DACK or EDACK output timing for the DRAM interface when DDS = 1 or

EDDS = 1.

RASn (CSn)

Read

Write

UCAS, LCAS

WE (HWR)

OE (RD)

Data bus

WE (HWR)

OE (RD)

Data bus

DACK or EDACK

Address bus

Note: n = 2 to 5

Row address Column address

High

Figure 6.41 Example of DACK

DACKDACK

DACK/EDACK

EDACKEDACK

EDACK Output Timing when DDS = 1 or EDDS = 1

(RAST = 0, CAST = 0)

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When DDS = 0 or EDDS = 0: When DRAM space is accessed in DMAC or EXDMAC single

address transfer mode, full access (normal access) is always performed. With the DRAM interface,

the DACK or EDACK output goes low from the Tr state.

In modes other than DMAC or EXDMAC single address transfer mode, bu rst access can be used

when accessing DRAM space.

Figure 6.42 shows the DACK or EDACK output timing for the DRAM interface when DDS = 0 or

EDDS = 0.

RASn (CSn)

Read

Write

UCAS, LCAS

WE (HWR)

OE (RD)

Data bus

WE (HWR)

OE (RD)

Data bus

DACK or EDACK

Address bus

Note: n = 2 to 5

Row address Column address

High

Figure 6.42 Example of DACK

DACKDACK

DACK/EDACK

EDACKEDACK

EDACK Output Timing when DDS = 0 or EDDS = 0

(RAST = 0, CAST = 1)

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6.7 Synchronous DRAM Interface

In the H8S/2678R Group, external address space areas 2 to 5 can be designated as continuous

synchronous DRAM space, and synchronous DRAM interfacing performed. The synchronous

DRAM interface allows synchronous DRAM to be directly connected to th is LSI. A synchronous

DRAM space of up to 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR.

Synchronous DRAM of CAS latency 1 to 4 can be conn ected.

Note: The synchronous DRAM interface is not supported in the H8S/2678 Group.

6.7.1 Setting Continuous Synchronous DRAM Spac e

Areas 2 to 5 are design ated as continuous synch ron ous DRAM sp ace by setting bits RMTS2 to

RMTS0 in DRAM CR. The relation between the settings of bits RMTS2 to RMTS0 and

synchronous DRAM space is shown in table 6.7. Possible synchronous DRAM interface settings

are and continuous area (areas 2 to 5).

Table 6.7 Relation between Settings of Bits RMTS2 to RMT S0 and Synchronous DRAM

Space

RMTS2 RMTS1 RMTS0 Area 5 Area 4 Area 3 Area 2

0 1 Normal space Normal space Normal space DRAM space

0 Normal space Normal space DRAM space DRAM space

1 DRAM space DRAM spac e DRAM space DRAM space

0 Continuous synchronous DRAM space0

1 Mode settings of synchronous DRAM

0 Reserved (setting prohibited)

1 Continuous DRAM space

With continuous synchronous DRAM space, CS2, CS3, CS4 pins are used as RAS, CAS, WE

signal. The (OE) pin of the synchronous DRAM is used as the CKE signal, and the CS5 pin is

used as synchronous DRAM clock (SDRAMφ). The bus specifications for continuous

synchronou s DRAM space co nform to the settings for area 2. The pin wait and program wait for

the continuous synchronous DRAM are invalid.

Commands for the synchronous DRAM can be sp ecified by combining RAS, CAS, WE, and

address-precharge-setting command (Prechrge-sel) output on the upper column addresses.

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Commands that are supported by this LSI are NOP, auto-refresh (REF), self-refresh (SELF), all

bank precharge (PALL), row address strobe bank -active (ACTV), read (READ), write (WRIT),

and mode-register write (MRS). Commands for bank control canno t be used.

6.7.2 Address M ult iplexing

With continuous synchronous DRAM space, the row address and column address are multiplexed.

In address mu ltiplexing, th e size of the shift of the row address is selected with bits MXC2 to

MXC0 in DRAM CR. The address-precharge-setting com m a nd ( Pr echrge-sel) can be output on the

upper column address. Table 6.8 shows the relation between the settings of MXC2 to MXC0 and

the shift size. The MXC2 bit should be set to 1 when the synchronous DRAM interface is used.

Table 6.8 Relation between Set tings of Bits MXC2 t o MXC0 and Ad dress Multiplexing

DRAMCR Address Pins

MXC2 MXC1 MXC0 Shift

Size A23 to

A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 x x Reserved (setting prohibited)

0 8 bits A23 to

A16 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A80

1 9 bits A23 to

A16 A15 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9

0 10 bi ts A23 to

A16 A15 A14 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10

Row

address 1

1 11 bi ts A23 to

A16 A15 A14 A13 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11

0 x x Reserved (setting prohibited)

0—A23 to

A16 PPPPPPPA8A7A6A5A4A3A2A1A00

1—A23 to

A16 PPPPPPA9A8A7A6A5A4A3A2A1A0

0—A23 to

A16 PPPPPA10A9A8A7A6A5A4A3A2A1A0

Column

address 1

1—A23 to

A16 PPPPA11A10A9A8A7A6A5A4A3A2A1A0

Legend:

X: Don’t care

P: Precharge-sel

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6.7.3 Data Bus

If the ABW2 bit in ABWCR corresponding to an area designated as continuous synchronous

DRAM space is set to 1, area 2 to 5 are designated as 8-bit continuous synchronous DRAM space;

if the bit is cleared to 0, the areas are designated as 16-bit continuous synchronous DRAM space.

In 16-bit continuous synchronous DRAM space, ×16-bit configuration synchronous DRAM can be

connected directly.

In 8-bit continuous synchronous DRAM space the upper half of the data bus, D15 to D8, is

enabled, while in 16-bit continuous synchronous DRAM space both the upper and lower halves of

the data bus, D15 to D0, are enab led.

Access sizes and data alignment are the same as for the basic bus interface: see section 6.5.1, Data

Size and Data Alignment.

6.7.4 Pins Used for Synchronous DRAM Interface

Table 6.9 shows pins used for the synchronous DRAM interface and their functions. To enable the

synchronous DRAM interface, fix the DCTL pin to 1. Do not vary the DCTL pin during operation.

Since the CS2 to CS4 pins are in the input state after a reset, set DDR to 1 when RAS, CAS, and

WE signals are output. For details, see section 10, I/O Ports. Set the OEE bit of the DRAMCR

Section 6 Bus Controller (BSC)

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Table 6.9 Synchronous DRAM Interface Pins

With

Synchronous

DRAM Setting Name I/O Function

CS2 RAS Row address strobe Output Row address strobe when

areas 2 to 5 are designated

as continuous synchronous

DRAM space

CS3 CAS Column address

strobe Output Column address strobe when

areas 2 to 5 are designated

as continuous synchronous

DRAM space

CS4 WE Write enable Output Write enable strobe when

areas 2 to 5 are designated

as continuous synchronous

DRAM space

CS5 SDRAMφClock Output Clock only for sy nchronous

DRAM

(OE) (CKE) Clock enable Output Clock enable signal when

areas 2 to 5 are designated

as continuous synchronous

DRAM space

UCAS DQMU Upper data mask

enable Output Upper data mask enable for

16-bit continuous

synchronous DRAM space

access/data mask enable for

8-bit continuous synchronous

DRAM space access

LCAS DQML Lower data mask

enable Output Lower data mask enable

signal for 16-bit continuous

synchronous DRAM space

access

A15 to A0 A15 to A0 Address pins Output Row address/column

address multiplexed output

pins

D15 to D0 D15 to D0 Data pins I/O Data input/output pins

DCTL DCTL Device control pin Input Output enable pin for

SDRAMφ

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6.7.5 Synchronous DRAM Clock

When the DCTL pin is fixed to 1, synchronous clock (SDRAMφ) is output from the CS5 pin.

When the fre quency multiplication factor of the PLL circuit of this LSI is set to ×1 or ×2,

SDRAMφ is 90° phase shift from φ. Therefore, a stable margin is ensured for the synchronous

DRAM that operates at the rising edge of clocks. Figure 6.43 shows the relationship between φ

and SDRAMφ. When the frequency multiplicatio n factor of the PLL circuit is ×4, the phase of

SDRAMφ and that of φ are the same.

When the CLK pin of the synchronous DRAM is directly connected to SDRAMφ of this LSI, it is

recommended to set the frequency multiplication factor of the PLL circuit to ×1 or ×2.

Note: SDRAMφ output timing is sho w n when the frequency multiplicatio n factor of the PLL

circuit is ×1 or ×2.

SDRAMø

Tcyc

1/4 Tcyc (90˚)

Figure 6.43 Relationship between φ

φφ

φ and SDRAMφ

φφ

φ (when PLL frequency multiplication

factor is ×

××

×1 or ×

××

×2)

6.7.6 Basic Operation Timing

The four states of the basic timing consist of one Tp (precharge cycle) state, one Tr (row address

output cycle) state, and the Tc1 and two Tc2 (column address output cycle) states.

When areas 2 to 5 are set for the continuous synchronous DRAM space, settings of the WAITE bit

of BCR, RAST, CA ST, RCDM bit s of DRAMCR, and the CBRM bit of RE FCR are ignored.

Figure 6.44 shows the basic timing for synchronous DRAM.

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SDRAMφ

RAS

Read

CAS

CKE

PALL ACTV READ NOP

DQMU, DQML

Data bus

Address bus

Row address

Column address Column address

Precharge-sel Row address

High

RAS

Write

CAS

CKE

PALL ACTV NOP WRIT

DQMU, DQML

Data bus

High

Figure 6.44 Ba sic Access Timing of Synchronous DRAM (CAS Latency 1)

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6.7.7 CAS Latency Control

CAS latency is controlled by settings of the W22 to W20 bits of WTCRB. Set the CAS late ncy

count, as shown in table 6.10, by the setting of synchronous DRAM. Depending on the setting, the

CAS latency control cycle (Tc1) is inserted. WTCRB can be set regardless o f the setting of the

AST2 bit of ASTCR. Figure 6.45 shows the CAS latency control timing when synchronous

DRAM of CAS latency 3 is connected.

The initial value of W22 to W20 is H'7. Set the register according to the CAS latency of

synchronous DRAM to be connected.

Table 6.10 Setting CAS Latency

W22 W21 W20 Description CAS Latency Control Cycl e

Inserted

0 0 0 Connect synchronous DRAM of

CAS latency 1 0 state

1 Connect synchronous DRAM of

CAS latency 2 1 state

1 0 Connect synchronous DRAM of

CAS latency 3 2 states

1 Connect synchronous DRAM of

CAS latency 4 3 states

1 0 0 Reserved (must not used) —

1 Reserved (must not used) —

1 0 Reserved (must not used) —

1 Reserved (must not used) —

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SDRAMφ

RAS

Read

CAS

CKE

PALL ACTV READ NOP

DQMU, DQML

Data bus

Address bus

cl1

cl2

Row address

Column address Column address

Precharge-sel Row address

High

RAS

Write

CAS

CKE

PALL ACTV NOP NOPWRIT

DQMU, DQML

Data bus

High

Figure 6.45 CAS Latency Control Timing (SDWCD = 0, CAS Latency 3)

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6.7.8 Row Address O ut put State Contro l

When the command interval specification from the ACTV command to the next READ/WRIT

command cannot be satisfied, 1 to 3 states (Trw) that output the NOP command can be inserted

between the Tr cycle that outputs the ACTV command and the Tc1 cycle that outputs the column

address by setting the RCD1 and RCD0 bits of DRACCR. Use the optimum setting for the wait

time according to the synchronous DRAM connected and the operating frequency of this LSI.

Figure 6.46 shows an example of the timing when the one Trw state is set.

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SDRAM

RAS

Read

CAS

CKE

PALL ACTV NOP READ NOP

DQMU, DQML

Data bus

Address bus

Row address

Column

address Column address

Precharge-sel

Row address

High

RAS

Write

CAS

CKE

PALL ACTV NOP NOPWRIT

DQMU, DQML

Data bus

High

Figure 6.46 Example of Access Timing when Row Address Output Hold State Is 1 State

(RCD1 = 0, RCD0 = 1, SDWCD = 0, CAS Latency 2)

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6.7.9 Precharge State Count

When the interval specification from the PALL command to the next ACTV/REF command

cannot be satisfied, from one to four Tp states can be selected by setting bits TPC1 and TPC0 in

DRACCR. Set the optimum number of Tp cy cles according to the synchronous DRAM connected

and the operating frequency of this LSI. Figure 6.47 shows the timing when two Tp states are

inserted.

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The setting of bits TPC1 and TPC0 is also valid for Tp states in refresh cycles.

SDRAM

RAS

Read

CAS

CKE

PALL NOP ACTV READ NOP

DQMU, DQML

Data bus

Address bus

Row addressColumn address Column address

Precharge-sel

Row address

High

RAS

Write

CAS

CKE

PALL NOP NOPACTV NOPWRIT

DQMU, DQML

Data bus

High

Figure 6.47 Example of Timing with Two-State Precharge Cycle

(TPC1 = 0, TPC0 = 1, SDWCD = 0, CAS Latency 2)

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6.7.10 Bus Cycle Control in Write Cycle

By setting the SDWCD bit of the DRACCR to 1, the CAS latency control cycle (Tc1) that is

inserted by the WTCRB register in th e wr ite access of the synchronous DRAM can be disabled.

Disabling the CAS latency control cycle can reduce the write-access cycle count as compared to

synchronous DRAM read access. Figure 6.48 shows the write access timing when the CAS latency

control cycle is disabled.

SDRAMφ

RAS

CAS

CKE

PALL ACTV WRITNOP

DQMU, DQML

Data bus

Address bus

TrTc1 Tc2

Row address

Column address Column address

Precharge-sel Row address

High

Figure 6.48 Example of Write Access Timing when CAS Latency Control Cycle Is Disabled

(SDWCD = 1)

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6.7.11 Byte Access Control

When synchronous DRAM with a ×16-bit configuration is connected , DQMU and DQML are

used for the control signals needed for byte access.

Figures 6.49 and 6.50 show the control timing for DQM, and figure 6.51 shows an example of

connection of byte control by DQMU and DQML.

SDRAMφ

RAS

CAS

CKE

PALL ACTV NOP NOPWRIT

DQMU

DQML

Lower data bus

Upper data bus

Address bus

Row address

Column address Column address

Precharge-sel Row address

High

High-Z

Figure 6.49 DQMU and DQML Control Timing

(Upper Byte Write Access: SDWCD = 0, CAS Latency 2)

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SDRAMφ

RAS

CAS

CKE

PALL ACTV READ NOP

DQMU

DQML

Lower data bus

Upper data bus

Address bus

Row address

Column address Column address

Precharge-sel Row address

High

High-Z

Figure 6.50 DQMU and DQML Control Timing

(Lower Byte Read Access: CAS Latency 2)

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This LSI

(Address shift size set to 8 bits)

CS2 (RAS)

CS3 (CAS)

CS4 (WE)

16-Mbit synchronous DRAM

1-Mword × 16 bits × 4-bank configuration

8-bit column address

RAS

CAS

UCAS (DQMU)

LCAS (DQML)

A9 A8

A10 A9

A8 A7

A12 A11

Notes: 1. Bank control is not available.

2. The CKE and CS pins must be fixed to 1 when the power supply is input.

3. The CS pin must be fixed to 0 before accessing synchronous DRAM.

A21 A12 (BS0)

A23 A13 (BS1)

CS5 (SDRAMø) CLK

DQML

DQMU

A11 A10

A7 A6

A6 A5

A5 A4

A4 A3

A3 A2

A2 A1

DCTL

I/O PORT

D15 to D0 DQ15 to DQ0

OE (CKE) CKE

Row address

input: A11 to A0

Column address

input: A7 to A0

Bank select

address: A13/A12

Figure 6.51 Example of DQMU and DQML Byte Control

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6.7.12 Burst Operation

With synchronous DRAM, in addition to full access (normal access) in which data is accessed by

outputting a row address for each access, burst access is also provided which can be used when

making consecutive accesses to the same row address. This access enables fast access of data by

simply changing the column address after the row address has been output. Burst access can be

selected by setting the BE bit to 1 in DRAMCR.

DQM has the 2-cycle latency when synchronous DRAM is read. Therefore, the DQM signal

cannot be specified to the Tc2 cycle data output if Tc1 cycle is performed for second or following

column addr ess when the CAS latency is set to 1 to issue the READ command. Do not set the BE

bit to 1 when synchronous DRAM of CAS latency 1 is connected.

Burst Access Operation Timing: Figure 6.52 shows the operation timing for burst access. When

there are consecutive access cycles for continuous synchronous DRAM space, the column address

output cycles continue as long as the row address is the same for consecutive access cycles. The

row addr ess used for the comparison is set with bits MXC2 to MXC0 in DRAMCR.

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SDRAM

RAS

Read

CAS

CKE

PALL ACTV READ READNOP NOP

DQMU, DQML

Data bus

Address bus

TrTc1 Tcl T

Row address

Column

address 1 Column address Column address 2

Precharge-sel

Row address

High

RAS

Write

CAS

CKE

PALL ACTV NOP NOP NOPWRIT WRIT

DQMU, DQML

Data bus

High

Figure 6.52 Operation Timing of Burst Access

(BE = 1, SDWCD = 0, CAS Latency 2)

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RAS Down Mode: Even when burst operation is selected, it may happen that access to continuous

synchronous DRAM space is not continuous, but is interrupted by access to another space. In this

case, if the row address active state is held during the access to the other space, the read or write

command can be issued without ACTV command generation similarly to DRAM RAS down

mode.

To select RAS down mode, set the BE b it to 1 in DRAMCR regard less of the RCDM bit settings.

The operation corresponding to DRAM RAS up mode is not supported by this LSI.

Figure 6.53 shows an example of the timing in RAS down mode.

Note, however, the next continuous synchronous DRAM space access is a full access if:

• a refresh oper ation is initiated in the RAS down state

• self-refreshing is performed

• the chip enters software standby mode

• the external bus is released

• the BE bit is cleared to 0

• the mode register of the synchronous DRAM is set

There is synchronous DRAM in which time of the active state of each bank is restricted. If it is not

guaranteed that other row address are accessed in a period in which program execution ensures the

value (software standby, sleep, etc.), auto refresh or self refresh must be set, and the restrictions of

the maximum active state time of each bank must be satisfied. When refresh is not used, programs

must be developed so that the bank is not in the active state for more than the specified time.

Section 6 Bus Controller (BSC)

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Address bus

External address

Column address Column address 2

External address

Row

address

Column

address

Data bus

TrTc1 Tcl Tc2 Tc1 Tc2

Continuous synchronous

DRAM space read Continuous synchronous

DRAM space read

External

space read

T2Tcl

RAS

CAS

CKE High

PALL ACTV READ NOP NOPREAD

DQMU, DQML

Precharge-sel

Row

address

Figure 6.53 Example of Operation Timing in RAS Down Mode

(BE = 1, CAS Latency 2)

6.7.13 Refresh Control

This LSI is provided with a synchronous DRAM refresh control function. Auto refreshing is used.

In addition, self- refreshing can be executed when the chip enter s the software standby state.

Refresh control is enabled when any area is designated as continuous synchronous DRAM space

in accordance with the settin g of bits RMTS2 to RMTS0 in DRAMCR.

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Auto Refreshing: To select auto refreshing, set the RFSHE bit to 1 in REFCR.

With auto refreshing, RTCNT counts up using the input clock selected by bits RTCK2 to RTCK0

in REFCR, and when the count matches the value set in RTCOR (compare match), refresh control

is performed. At the same time, RTCNT is reset and starts counting up again from H'00.

Refreshing is thus repeated at fixed intervals determined by RTCOR and bits RTCK2 to RTCK0.

Set a value in RTCOR an d bits RTCK2 to RTCK0 that will meet the refreshing interval

specification for the synchronous DRAM used.

When bits RTCK2 to RTCK0 are set, RTCNT starts counting up. RTCNT and RTCOR settings

should therefore be completed before setting bits RTCK2 to RTCK0. Auto refresh timing is shown

in figure 6.54.

Since the refresh counter operation is the same as the operation in the DRAM interface, see

section 6.6.12, Refresh Control.

When the continuous synchronous DRAM space is set, access to external space other than

continuous synchronous DRAM space cannot be performed in parallel during the auto refresh

period, since the setting of the CBRM bit of REFCR is ignored.

TRp

SDRAMφ

RAS

CAS

CKE

PALL NOPREF

Address bus

TRr TRc1 TRc2

Precharge-sel

High

Figure 6.54 Auto Refresh Timing

Section 6 Bus Controller (BSC)

Rev. 3.00 Mar 17, 2006 page 219 of 926

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When the interval specification from the PLL command to the REF command cannot be satisfied,

setting the RC W1 and RCW0 b its of REFCR enables one to th r ee wait states to be inserted after

the TRp cycle that is set b y the TPC1 and TPC0 bits of DRACCR. Set th e optimum num ber of

waits according to the synchronous DRAM connected and the operating frequency of this LSI.

Figure 6.55 shows the timing when one wait state is inserted. Since the setting of bits TPC1 and

TPC0 of DRACCR is also valid in refresh cycles, the command interval can be extended by th e

RCW1 and RCW0 bits after the precharge cycles.

Rp1

SDRAMφ

RAS

CAS

CKE

PALL NOP REF NOP

Address bus

Rp2

Rrw

Rc1

Rc2

Precharge-sel

High

Figure 6.55 Auto Refresh Timing

(TPC = 1, TPC0 = 1, RCW1 = 0, RCW0 = 1)

Section 6 Bus Controller (BSC)

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When the inter val specification from the REF co mmand to the ACTV cannot b e satisf ied , setting

the RLW1 and RLW0 bits of REFC R enables one to three wait states to be inserted in the refresh

cycle. Set the optimum number of waits according to the synchronous DRAM connected and the

operating frequ ency of this LSI. Figure 6.56 shows the timing when one wait state is inserted.

TRp

SDRAMφ

RAS

CAS

CKE

PALL REF NOP

Address bus

TRr TRr1 TRcw TRc2

Precharge-sel

High

Figure 6.56 Auto Refresh Timing

(TPC = 0, TPC0 = 0, RLW1 = 0, RLW0 = 1)

Self-Refreshing: A self-refresh mode (battery backup mode) is provided for synchronous DRAM

as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within

the synchronous DRAM.

To select self-refreshing, set the RFSHE bit to 1 in REFCR. When a SLEEP instruction is

executed to enter software standby mode, the SELF command is issued, as shown in figure 6.57.

When software standby mode is exited, the SLFRF bit in REFCR is cleared to 0 and self-refresh

mode is exited automatically. If an auto refresh request occurs when making a transition to

software standby mode, auto refreshing is executed, then self-refresh mode is entered.

Section 6 Bus Controller (BSC)

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REJ09B0283-0300

When using self-refresh mode, the OPE bit must not be cleared to 0 in SBYCR.

SDRAMφ

Precharge-sel

Address bus

CAS

Software standby T

Rc2

CKE

RAS

NOPSELFPALL

Figure 6.57 Self-Refresh Timing

(TPC1 = 1, TPC0 = 0, RCW1 = 0, RCW0 = 0, RLW1 = 0, RLW0 = 0)

In some synchronous DRAMs provided with a self-refresh mode, the interval between clearing

self-refreshing and the next command is specified. A setting can be made in bits TPCS2 to TPCS0

in REFCR to make the precharge time after self-refreshing from 1 to 7 states longer than the

normal precharge time. In this case, too, normal precharging is performed according to the setting

of bits TPC1 and TPC0 in DRACCR, and therefore a setting should be made to give the optimum

post-self-refresh precharge time, including this time. Figure 6.58 shows an example of the timing

when the precharge time after self-refreshing is extended by 2 states.

Section 6 Bus Controller (BSC)

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Rc2

SDRAM

RAS

CAS

CKE

NOP PALL NOPACTV NOP NOP

DQMU, DQML

Data bus

Address bus

Rp1

Rp2

Row address

Column address

Precharge-sel Row address

Continuous synchronous DRAM space write

Software

standby

Figure 6.58 Example of Timing when Precharge Time after Self-Refreshing Is Extended

by 2 States (TPCS2 to TPCS0 = H'2, TPC1 = 0, TPC0 = 0, CAS Latency 2)

Refreshing and All-Module-Clo c ks-Stopped Mode: In this LSI, if the ACSE b it is set to 1 in

MSTPCRH, and then a SLEEP instruction is executed with the setting for all peripheral module

clocks to be stopped (MSTPCR = H'FFFF) or for operation of the 8-bit timer module alone

(MSTPCR = H'FFFE), and a transition is made to the sleep state, the all-module-clocks-stopped

mode is entered, in which the bus controller and I/O port clocks are also stopped.

As the bus controller clock is also stopped in this mode, auto refreshing is not executed. If

synchro nou s DRAM is connected externally and DRAM data is to be retained in sleep mode, the

ACSE bit must be cleared to 0 in MSTPCR.

Softwa re St andby: When a transition is made to normal software standby, the PLL command is

not output. If synchronous DRAM is connected and DRAM data is to be retained in software

standby, self-refreshing mu st be set.

Section 6 Bus Controller (BSC)

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6.7.14 Mode Register Setting of Synchronous DRAM

To use synchronous DRAM, mode must be set after power-on. To set mode, set the RMTS2 to

RMTS0 bits in DRAMCR to H'5 and enable the synchronous DRAM mode register setting. After

that, access the continuous synchronous DRAM space in bytes. When th e value to be set in the

synchronous DRAM mode register is X, value X is set in the synchronous DRAM mode register

by writing to the continuous synchronous DRAM space of address H'400000 + X for 8-bit bus

configuration synchronous DRAM and by writing to the continuous synchronous DRAM space of

address H'400000 + 2X for 16-bit bus configuration synchronous DRAM.

The value of the address signal is fetch ed at the issuance time of th e MRS command as the setting

value of the mode register in the synchronous DRAM. Mode of burst read/burst write in the

synchronous DRAM is not supported by this LSI. For setting the mode register of the synchronous

DRAM, set the burst r ead/single write with th e burst length of 1. Fig ure 6 .59 shows the setting

timing of the mode in the synchronous DRAM.

SDRAMφ

RAS

CAS

CKE

PALL MRS NOPNOP

Address bus

Mode setting value

Precharge-sel

High

Figure 6.59 Synchrono us DRAM Mode Setting Timing

Section 6 Bus Controller (BSC)

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6.7.15 DMAC and EXDMAC Si ngle Address Transfer Mode and Synchronous DRAM

Interface

When burst mode is selected on the synchronous DRAM interface, the DACK and EDACK output

timing can be selected with the DDS and EDDS bits in DRAMCR. When continuous synchronous

DRAM space is accessed in DMAC/EXDMAC single address mode at the same time, these bits

select whether or not burst access is to be performed. The establishment time for the read data can

be extended in the clock suspend mode irrespective of the settings of the DDS and EDDS bits.

(1) Output Timing of DACK

DACKDACK

DACK or EDACK

EDACKEDACK

EDACK

When DDS = 1 or EDDS = 1: Burst access is performed by determining the address only,

irrespective of the bus master. With the synchronous DRAM interface, the DACK or EDACK

output goes low from the Tc1 state.

Figure 6.60 shows the DACK or EDACK output timing for the synchronous DRAM interface

when DDS = 1 or EDDS = 1.

Section 6 Bus Controller (BSC)

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SDRAMφ

RAS

Read

CAS

CKE

PALL ACTV READ NOP

DQMU, DQML

Data bus

Address bus

Row address

Column address

Precharge-sel Row address

High

RAS

Write

CAS

CKE

PALL ACTV NOP NOPWRIT

DQMU, DQML

DACK or RDACK

Data bus

High

Figure 6.60 Example of DACK

DACKDACK

DACK/EDACK

EDACKEDACK

EDACK Output Timing when DDS = 1 or EDDS = 1

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When DDS = 0 or EDDS = 0: When continuous synchronous DRAM space is accessed in

DMAC or EXDMAC single address transfer mode, full access (normal access) is always

performed. With the synchronous DRAM interface, the DACK or EDACK output goes low from

the Tr state.

In modes other than DMAC or EXDMAC single address transfer mode, bu rst access can be used

when accessing continuous synchronous DRAM space.

Figure 6.61 shows the DACK or EDACK output timing for the synchronous DRAM interface

when DDS = 0 or EDDS = 0.

Section 6 Bus Controller (BSC)

Rev. 3.00 Mar 17, 2006 page 227 of 926

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SDRAMφ

RAS

Read

CAS

CKE

PALL ACTV READ NOP

DQMU, DQML

Data bus

Address bus

TrTc1 Tcl Tc2

Row address

Column address

Precharge-sel Row address

High

RAS

Write

CAS

CKE

PALL ACTV NOP NOPWRIT

DQMU, DQML

DACK or RDACK

Data bus

High

Figure 6.61 Example of DACK

DACKDACK

DACK/EDACK

EDACKEDACK

EDACK Output Timing when DDS = 0 or EDDS = 0

Section 6 Bus Controller (BSC)

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(2) Read Data Extension

If the CKSPE bit is set to 1 in DRACCR when the continuous synchronous DRAM space is read-

accessed in DMAC/EXDMAC single address mode, the establishment time for the read data can

be extended by clock suspend mode. The number of states for insertion of the read data extension

cycle (Tsp) is set in bits RDXC1 and RDXC0 in DRACCR. Be sure to set th e OEE bit to 1 in

DRAMCR when the read data will be ex tended . The extension o f the r ead data is n ot in

accordance with the bits DDS and EDDS.

Figure 6.62 shows the timing chart when the read data is extended by two cycles.

Address bus

SDRAMφ

Column address

Row

address

Row

address

Column

address

Data bus

sp2

sp1

RAS

CAS

CKE

PALL ACTV NOP

READ

DQMU, DQML

DACK or EDACK

Precharge-sel

Figure 6.62 Example of Timing when the Read Data Is Extended by Two States

(DDS = 1, or EDDS = 1, RDXC1 = 0, RDXC0 = 1, CAS Latency 2 )

Section 6 Bus Controller (BSC)

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6.8 Burst ROM Interface

In this LSI, external space areas 0 and 1 can be designated as burst ROM space, and burst ROM

interfacing performed. The burst ROM space interface enables ROM with burst access capability

to be accessed at high speed.

Areas 1 and 0 can be designated as burst ROM space by means of bits BSRM1 and BSRM0 in

BROMCR. Continuous burst accesses of 4, 8, 16, or 32 words can be performed, according to the

setting of the BSWD11 and BSWD10 bits in BROMCR. From 1 to 8 states can be selected for

burst access.

Settings can be made independently for area 0 and area 1.

In burst ROM interface space, burst access covers only CPU read accesses.

6.8.1 Basic Timing

The number of access states in the in itial cycle (full access) on the burst ROM interface is

determined by the basic bus interface settings in ASTCR, ABWCR, WTCRA, WTCRB, and

CSACRH. When area 0 or area 1 is designated as burst ROM interface space, the settings in

RDNCR and CSACRL are ignored.

From 1 to 8 states can be selected for the burst cycle, according to the setting s o f bits BSTS02 to

BSTS00 and BSTS12 to BSTS10 in BROMCR. Wait states cannot be inserted. Burst access of up

to 32 words is performed, according to the settings of bits BSTS01, BSTS00, BSTS11, an d

BSTS10 in BROM CR.

The basic access timing for burst ROM space is shown in figures 6.63 and 6.64 .

Section 6 Bus Controller (BSC)

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Upper address bus

Lower address bus

CSn

Data bus

Full access

Burst access

Note: n = 1 and 0

Figure 6.63 Example of Burst ROM Access Timing

(ASTn = 1 , 2-Stat e Burst Cy cle)

Section 6 Bus Controller (BSC)

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Upper address bus

Lower address bus

CSn

Data bus

T2T1T1

Full access

Burst access

Note: n = 1 and 0

Figure 6.64 Example of Burst ROM Access Timing

(ASTn = 0 , 1-Stat e Burst Cy cle)

6.8.2 Wait Control

As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT

pin can be used in the initial cycle (full access) on the burst ROM interface. See section 6.5 .4,

Wait Control. Wait states cannot be inserted in a burst cycle.

6.8.3 Write Access

When a write access to burst ROM interface space is executed, burst access is interrupted at that

point and the write access is executed in line with th e basic b us interface settings. Write accesses

are not performed in burst mode even though burst ROM space is designated.

Section 6 Bus Controller (BSC)

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6.9 Idle Cycle

6.9.1 Operation

When this LSI accesses external space, it can insert an idle cycle (Ti) between bus cycles in the

following three cases: (1) when read accesses in different areas occur consecutively, (2) when a

write cycle occurs immediately after a read cycle, and (3) when a read cycle occurs immediately

after a write cycle (in the H8S/2678R Group, it cannot insert an idle cycle in the condition (3)).

Insertion of a 1-state or 2-state idle cycle can be selected with the IDLC bit in BCR. By inserting

an idle cycle it is po ssible, for example, to avoid data collisions between ROM, etc., with a long

output floating time, and high-speed memory, I/O interfaces, and so on.

Consecutive Reads in Different Areas: If consecutive reads in different areas occur while the

ICIS1 bit is set to 1 in BCR, an idle cycle is inserted at the start of the second read cycle.

Figure 6.65 shows an example of the operation in this case. In this example, bus cycle A is a read

cycle for ROM with a long output floating time, and bus cycle B is a read cycle for SRAM, each

being located in a different area. In (a), an idle cycle is not in ser ted , and a collision occurs in bus

cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,

and a data collision is prevented.

Address bus

Bus cycle A

Data bus

Bus cycle B

Long output floating time Data collision

(a) No idle cycle insertion

(ICIS1 = 0)

Address bus

Bus cycle A

Data bus

Bus cycle B

(b) Idle cycle insertion

(ICIS1 = 1, initial value)

CS (area A)

CS (area B)

CS (area A)

CS (area B)

Idle cycle

Figure 6.65 Example of Idle Cycle Operation

(Consecutive Reads in Different Areas)

Section 6 Bus Controller (BSC)

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Write after Read: If an external write occurs after an external read while th e ICIS0 bit is set to 1

in BCR, an idle cycle is inserted at the start of the write cycle.

Figure 6.66 shows an example of the operation in this case. In this example, bus cycle A is a read

cycle for ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an

idle cycle is not in ser ted , and a collision occurs in bus cycle B between the read data from ROM

and the CPU write d ata. I n (b), an idle cycle is inserted, and a data collisio n is prevented.

Address bus

Bus cycle A

Data bus

Bus cycle B

Long output floating time Data collision

(a) No idle cycle insertion

(ICIS0 = 0)

Address bus

Bus cycle A

Data bus

Bus cycle B

(b) Idle cycle insertion

(ICIS0 = 1, initial value)

HWR

CS (area A)

CS (area B)

CS (area A)

CS (area B)

Idle cycle

Figure 6.66 Example of Idle Cycle Operation (Write after Read)

Read after Write: If an external read occurs after an external write while th e ICIS2 bit is set to 1

in BCR, an idle cycle is inserted at the start of the read cycle.

Figure 6.67 shows an example of the operation in this case. In this example, bus cycle A is a CPU

write cycle and bus cycle B is a read cycle from an external device. In (a), an id le cycle is not

inserted, and a collision occurs in bus cycle B between th e CPU write data and read data from an

external dev ice. In (b), an idle cy cle is inserted, and a data collision is prevented.

Note: In the H8S/2678 Group, an idle cycle cannot be inserted in the condition (3).

Section 6 Bus Controller (BSC)

Rev. 3.00 Mar 17, 2006 page 234 of 926

REJ09B0283-0300

Address bus

Bus cycle A

Data bus

Bus cycle B

Long output floating time Data collision

(a) No idle cycle insertion

(ICIS2 = 0)

Address bus

Bus cycle A

Data bus

Bus cycle B

(b) Idle cycle insertion

(ICIS2 = 1, initial value)

HWR

HWR, LWR

CS (area A)

CS (area B)

CS (area A)

CS (area B)

Idle cycle

Figure 6.67 Example of Idle Cycle Operation (Read after Write)

Relationship between Chip Select (CS

CSCS

CS) Signal and Read (RD

RDRD

RD) Signal: Depending on the

system’s load conditions, the RD signal may lag behind the CS signal. An example is shown in

figure 6.68. In this case, with the setting for no idle cycle insertion (a), there may be a period of

overlap between the bus cycle A RD signal and the bus cycle B CS signal. Setting idle cycle

insertion, as in ( b), howev e r , will p revent any overlap between the RD and CS signals. In the

initial state after reset re lease, idle cycle insertion (b) is set.

Section 6 Bus Controller (BSC)

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Address bus

Bus cycle A

Bus cycle B

Overlap period between CS (area B)

and RD may occur

(a) No idle cycle insertion

(ICIS1 = 0)

Address bus

Idle cycle

Bus cycle A

Bus cycle B

(b) Idle cycle insertion

(ICIS1 = 1, initial value)

CS (area A)

CS (area B)

CS (area A)

CS (area B)

Figure 6.68 Relationship between Chip Select (CS

CSCS

CS) and Read (RD

RDRD

RD)

Idle Cycle in Case of DRAM Space Access after Normal Space Access: In a DRAM space

access following a normal space access, the settings of bits ICIS2 (not available in the H8 S/2678

Group), ICIS1, ICIS0, and IDLC in BCR are valid. However, in the case of consecutive reads in

different areas, for example, if the second read is a full access to DRAM space, only a Tp cycle is

inserted, and a Ti cycle is not. The timing in this case is shown in f igure 6.69.

Address bus

External read

Data bus

T2T3TpTr

DRAM space read

Tc1 Tc2

Figure 6.69 Example of DRAM Full Access after External Read

(CAST = 0)

In burst access in RAS down mode, the settings o f bits ICIS2 (not available in the H8S/2678

Group), ICIS1, ICIS0, and IDLC are valid and an idle cycle is inserted. The timing in this case is

illustrated in f igures 6.70 and 6.71.

Section 6 Bus Controller (BSC)

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Address bus

RAS

UCAS, LCAS

External read

Idle cycle

Data bus

DRAM space readDRAM space read

Figure 6.70 Example of Idle Cycle Operation in RAS Down Mode

(Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0)

Address bus

RAS

HWR

UCAS, LCAS

External read

Idle cycle

Data bus

DRAM space writeDRAM space read

Figure 6.71 Example of Idle Cycle Operation in RAS Down Mode

(Write after Read) (IDLC = 0, RAST = 0, CAST = 0 )

Section 6 Bus Controller (BSC)

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Idle Cycle in Case of Continuous Synchronous DRAM Space Access after Normal Space

Access: In a continuous synchronous DRAM space access following a normal space access, the

settings of bits ICIS2, ICIS1, ICIS0, and IDLC in BCR are valid. However, in the case of

consecutive reads in different areas, for example, if the second read is a full access to continuous

synchronous DRAM space, only Tp cycle is inserted, and Ti cycle is not. The timing in this case is

shown in figure 6.72.

Note: In the H8S/2678 Group, the synchronous DRAM interface is not supported.

Address bus

Column address

Row

address

Row

address

Column

address

Data bus

T2T3TpTrTc2

External space read Synchronous DRAM space read

Tcl

Tc1

RAS

CAS

CKE

PALL ACTV NOP

NOP READ

DQMU, DQML

Precharge-sel

Figure 6.72 Example of Synchronous DRAM Full Access after External Read

(CAS Latency 2)

In burst access in RAS down mo de, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC are valid

and an idle cycle is inserted. However, in read access, note that the timings of DQMU and DQML

differ according to the settings of the IDLC bit. The timing in this case is illustrated in figu r es 6.7 3

Section 6 Bus Controller (BSC)

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REJ09B0283-0300

and 6.74. In write access, DQMU and DQML are not in accordance with the settings of th e IDLC

bit. The timing in this case is illustrated in figure 6.75.

Address bus External addressColumn address 1 Column address 2

External address

Row

address

Column

address

Idle cycle

Data bus

Continuous synchronous

DRAM space read External space read Continuous synchronous

DRAM space read

RAS

CAS

HWR, LWR

CKE High

High

PALL ACTV READ NOP NOPREAD

DQMU, DQML

Precharge-sel

Row

address

Figure 6.73 Example of Idle Cycle Operation in RAS Down Mode

(Read in Different Area) (IDLC = 0, CAS Latency 2)

Section 6 Bus Controller (BSC)

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Address bus

Idle cycle

Data bus

Continuous synchronous

DRAM space read External space read Continuous synchronous

DRAM space read

RAS

CAS

HWR, LWR

CKE High

High

PALL ACTV READ NOP NOPREAD

DQMU, DQML

Precharge-sel

Row

address

Row

address

Column

address

External address

Column address 1 Column address 2

Figure 6.74 Example of Idle Cycle Operation in RAS Down Mode

(Read in Different Area) (IDLC = 1, CAS Latency 2)

Section 6 Bus Controller (BSC)

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Address bus

Idle cycle

Data bus

Continuous synchronous

DRAM space read External space read Continuous synchronous

DRAM space write

RAS

CAS

HWR, LWR

CKE High

High

PALL ACTV READ NOP NOPWRIT

DQMU, DQML

Precharge-sel

Row

address

Row

address

Column

address

External address

Column address 1 Column address 2

Figure 6.75 Example of Idle Cycle Operation in RAS Down Mode

(Write after Read) (IDLC = 0, CAS Latency 2)

Idle Cycle in Case of Normal Space Access after DRAM Space Access:

• Normal space access after DRAM space read access

While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after DRAM space access is

disabled. Idle cycle insertion after DRAM space access can be enabled by setting th e DRMI bit to

1. The conditions and number of states of the idle cycle to be in serted are in accordance with the

settings of bits ICIS1, ICIS0, and IDLC in BCR are valid. Figures 6.76 and 6.77 show examples of

idle cycle oper a tion wh en the DRMI bit is set to 1.

Section 6 Bus Controller (BSC)

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When the DRMI bit is cleared to 0, an idle cycle is not inserted after DRAM space access even if

bits ICIS1 and ICIS0 are set to 1.

Address bus

RAS

UCAS, LCAS

External read

Idle cycle

Data bus

DRAM space readDRAM space read

Figure 6.76 Example of Idle Cycle Operation after DRAM Access

(Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0)

Section 6 Bus Controller (BSC)

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Address bus

RAS

HWR, LWR

UCAS, LCAS

External write

Idle cycle

Data bus

DRAM space readDRAM space read

Figure 6.77 Example of Idle Cycle Operation after DRAM Access

(Write after Read) (IDLC = 0, RAST = 0, CAST = 0 )

• Normal space access after DRAM space write access

While the ICIS2 bit is set to 1 in BCR (there is no ICRS2 bit in the H8S/2678 Group, therefore

this setting cannot be made) and a normal space read access occurs after DRAM space write

access, idle cycle is inserted in the first read cycle. The number of states of the idle cycle to be

inserted is in accord an ce with the setting of the IDLC bit. It does not depend on the DRMI bit in

DRACCR. Figure 6.78 shows an example of idle cycle operation when the ICIS2 bit is set to 1.

Section 6 Bus Controller (BSC)

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Address bus

RAS

HWR, LWR

UCAS, LCAS

External space read

Idle cycle

Data bus

DRAM space readDRAM space read

Figure 6.78 Example of Idle Cycle Operation after DRAM Write Access

(IDLC = 0, ICIS1 = 0, RAST = 0 , CAST = 0)

Idle Cycle in Case of Normal Space Access After Co nt inuous Synchronous DRAM Space

Access:

Note: In the H8S/2678 Group, the synchronous DRAM interface is not supported.

• Normal space access after a continuous synchronous DRAM space read access

While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after continuous synchronous

DRAM space read access is disabled. Idle cycle insertion after continuous synchronous DRAM

space read access can be enabled by setting the DRMI bit to 1. The conditions and number of

states of the idle cycle to be inserted are in accordance with the settings of bits ICIS1, ICIS0, and

IDLC in RCR. Figure 6.79 shows an example of id le cycle operation when the DRMI bit is set to

1. When the DRMI bit is cleared to 0, an idle cycle is not inserted after continuous synchronous

DRAM space read access even if bits ICIS1 and ICIS0 are set to 1.

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Address bus

Idle cycle

Data bus

Continuous synchronous

DRAM space read External space read Continuous synchronous

DRAM space read

RAS

CAS

CKE High

PALL ACTV READ NOP NOPREAD

DQMU, DQML

Precharge-sel

External address

Column address 1 Column address 2

Row

address

Row

address

Column

address

Figure 6.79 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space

Read Access (Read between Different Area) (IDLC = 0, CAS Latency 2)

• Normal space access after a continuous synchronous DRAM space write access

If a normal space read cycle occurs after a continuous synchronous DRAM space write access

while the ICIS2 bit is set to 1 in BCR, idle cycle is inser ted at the start of the r ead cycle. The

number of states o f the idle cycle to be inserted is in accordan ce with the setting of bit IDLC. It is

not in accordance with the DRMI bit in DRACCR.

Figure 6.80 sh ows an example of idle cycle opera tion when the ICIS2 bit is set to 1.

Section 6 Bus Controller (BSC)

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Address bus

Idle cycle

Data bus

Continuous synchronous

DRAM space write External space read Continuous synchronous

DRAM space read

RAS

CAS

HWR, LWR

CKE High

PALL ACTV NOP WRIT NOP NOPREAD

DQMU, DQML

Precharge-sel

External address

Column

address Column address 2

Row

address

Row

address

Column

address

Figure 6.80 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space

Write Access (IDLC = 0, ICIS1 = 0, SDWCD = 1, CAS Latency 2)

Table 6.11 shows whether there is an idle cycle insertion or not in the case of mixed accesses to

normal space and DRAM space/continuous synchronous DRAM space.

Section 6 Bus Controller (BSC)

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Table 6.11 Idle Cycles in Mixed Accesses to Normal Spa ce and DRAM Continuous

Synchronous DRAM Spac e

Previous Access Next Access ICIS2*ICIS1 ICIS0 DRMI IDLC Idle cycle

—0———Disabled

—1——0 1 state inserted

Normal space read

(different area)

1 2 states inserted

—0———Disabled

—1——0 1 state inserted

DRAM/continuous

synchronous DRA M*

space read 1 2 states inserted

——0——Disabled

——1—0 1 state inserted

Normal space write

1 2 states inserted

——0——Disabled

——1—0 1 state inserted

Normal space read

DRAM/continuous

synchronous DRA M*

space write 1 2 states inserted

—0———Disabled

—1—0—Disabled

1 0 1 state inserted

Normal space read

1 2 states inserted

—0———Disabled

—1—0—Disabled

1 0 1 state inserted

DRAM/continuous

synchronous DRA M*

space read

1 2 states inserted

——0——Disabled

——10—Disabled

1 0 1 state inserted

Normal space write

1 2 states inserted

——0——Disabled

——10—Disabled

1 0 1 state inserted

DRAM/continuous

synchronous DRA M*

space read

DRAM/continuous

synchronous DRA M*

space write

1 2 states inserted

0————Disabled

1———0 1 stat e ins erted

Normal space read

1 2 states inserted

0————Disabled

1———0 1 stat e ins erted

Normal space write

DRAM/continuous

synchronous DRA M*

space read 1 2 states inserted

Section 6 Bus Controller (BSC)

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Previous Access Next Access ICIS2*ICIS1 ICIS0 DRMI IDLC Idle cycle

0————Disabled

1———0 1 stat e ins erted

Normal space read

1 2 states inserted

0————Disabled

1———0 1 stat e ins erted

DRAM/continuous

synchronous DRA M*

space write

DRAM/continuous

synchronous DRA M *

space read 1 2 states inserted

Note: *In the H8S/2678 Group, the synchronous DRAM interface is not supported.

Setting the DRMI b it in DRACCR to 1 enables an idle cycle to be in ser ted in the case of

consecutive read and write operations in DRAM/continuous synchronous DRAM space burst

access. Figures 6.81 and 6.82 show an example of the timing for idle cycle insertion in the case of

consecutive read and write accesses to DRAM/continuous synchronous DRAM space.

Address bus

Idle cycle

Data bus

DRAM space writeDRAM space read

RASn (CSn)

UCAS, LCAS

WE (HWR)

OE (RD)

Note: n = 2 to 5

Figure 6.81 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and

Write Accesses to DRAM Space in RAS Down Mode

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Address bus

Idle cycle

Data bus

TrTc1 Tcl Tc2

Continuous synchronous

DRAM space write

Continuous synchronous

DRAM space read

Tc2

TiTc1

RAS

CAS

CKE High

PALL ACTV READ NOP WRIT

DQMU, DQML

Precharge-sel

External address

Column

address

Row

address

Column

address

Figure 6.82 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and

Write Accesses to Continuous Sy nchronous DRAM Space in RAS Down Mode

(SDWCD = 1, CAS Latency 2)

Section 6 Bus Controller (BSC)

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6.9.2 Pin States in Idle Cycle

Table 6.12 shows the pin states in an idle cycle.

Table 6.12 Pin Sta tes in Idle Cycle

Pins Pin State

A23 to A0 Contents of following bus cycle

D15 to D0 High impedance

CSn (n = 7 to 0) High*1 *2

UCAS, LCAS High*2

AS High

RD High

(OE)High

HWR, LWR High

DACKn (n = 1, 0) High

EDACKn (n = 3 to 0) High

Notes: 1. Remains low in DRAM space RAS down mode.

2. Remains low in a DRAM space refresh cycle.

6.10 Write Data Buffer Function

This LSI has a write da ta buffer function for the external data bus. Usin g the write data buffer

function enables external writes and DMA single address mode transfers to be executed in parallel

with internal accesses. The write da ta b uffer function is made available by setting the WDBE bit

to 1 in BCR.

Figure 6.83 sh ows an example of the timing when the write data buffer function is u sed . When this

function is used, if an external write or DMA single address mode transfer continues for two states

or longer, and there is an internal access next, an external write only is executed in the first state,

but from the next state onward an internal access (on-chip memory or internal I/O register

read/write) is execu ted in parallel with the external write rather than waiting until it ends.

Section 6 Bus Controller (BSC)

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Internal address bus

A23 to A0

External write cycle

HWR, LWR

On-chip memory read Internal I/O register read

Internal read signal

CSn

D15 to D0

External address

Internal memory

External space

write

Internal I/O register address

Figure 6.83 Example of Timing when Write Data Buffer Function is Used

6.11 Bus Release

This LSI can release the external bus in response to a bus request from an external device. In the

external bus released state, internal bus masters except the EXDMAC continue to operate as long

as there is no external access. If any of the following requests are issued in the external bus

released state, the BREQO signal can be driven low to output a bus request externally.

• When an internal bus master wants to perform an external access

• When a refresh request is generated

• When a SLEEP instruction is executed to place the chip in software standby mode or all-

module-cloc ks -s topped mode

Section 6 Bus Controller (BSC)

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6.11.1 Operation

In externally expanded mode, the bus can be released to an external device by setting the BRLE

bit to 1 in BCR. Dr iving the BREQ pin low issues an external bus request to this LSI. When th e

BREQ pin is sam pled, at the prescr ibed timing the BACK pin is driven low, and the address bus,

data bus, and bus control signals are placed in the high-impedance state, establishing the external

bus released state.

In the external bus released state, internal bus masters except the EXDMAC can perform accesses

using the internal bus. When an internal bus master wants to make an external access, it

temporarily defers initiation of the bus cycle, and waits f or the bus request from the external bus

master to be canceled. If a refresh request is generated in the ex ternal bus released state, or if a

SLEEP instruction is executed to place the chip in software standby mode or all-module-clocks-

stopped mode, refresh control and software standby or all-module-clocks-stopped control is

deferred un til th e bus request f rom the external bus master is canceled.

If the BREQOE bit is set to 1 in BCR, the BREQO pin can be driven low when any of the

following requests are issued, to request cancellation of the bus request externally.

• When an internal bus master wants to perform an external access

• When a refresh request is generated

• When a SLEEP instruction is executed to place the chip in software standby mode or all-

module-cloc ks -s topped mode

When the BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the

external bus released state is terminated.

If an external bus release request and external access occur simultaneously, the order of priority is

as follows:

(High) External bus release > External access by internal bus master (Low)

If a refresh request and external bus release request occur simultaneously, the order of priority is

as follows:

(High) Refresh > External bus release (Low)

Section 6 Bus Controller (BSC)

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6.11.2 Pin States in External Bus Released State

Table 6.13 shows pin states in the external bus released state.

Table 6.13 Pin States in Bus Released State

Pins Pin State

A23 to A0 High impedance

D15 to D0 High impedance

CSn (n = 7 to 0) High impedance

UCAS, LCAS High impedance

AS High impedance

RD High impedance

(OE) High impedance

HWR, LWR High impedance

DACKn (n = 1, 0) High

EDACKn (n = 3 to 0) High

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6.11 .3 Tra nsition Timi ng

Figure 6. 84 shows the timing fo r tran sition to the bus released state.

CPU

cycle

External bus released state

External space

access cycle

Address bus

HWR, LWR

BREQ

BACK

BREQO

High-Z

[1] [2] [3] [5][4] [6] [7] [8]

[1] Low level of BREQ signal is sampled at rise of ø.

[2] Bus control signal returns to be high at end of external space access cycle.

At least one state from sampling of BREQ signal.

[3] BACK signal is driven low, releasing bus to external bus master.

[4] BREQ signal state is also sampled in external bus released state.

[5] High level of BREQ signal is sampled.

[6] BACK signal is driven high, ending external bus release cycle.

[7] When there is external access or refresh request of internal bus master during external

bus release while BREQOE bit is set to 1, BREQO signal goes low.

[8] Normally BREQO signal goes high 1.5 states after rising edge of BACK signal.

Data bus

Figure 6.84 Bus Released State Transition Timing

Figure 6. 85 shows the timing fo r tran sition to the bus released state with the synchro nous DRAM

interface.

Section 6 Bus Controller (BSC)

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CPU

cycle

External bus released state

External space read

Address bus

DQMU, DQML

BREQ

BACK

BREQO

High-Z

NOP PALL NOP NOP

[1] [2] [3] [5][4] [6][8] [7] [9]

[1] Low level of BREQ signal is sampled at rise of f.

[2] PLL command is issued.

[3] Bus control signal returns to be high at end of external space access cycle.

At least one state from sampling of BREQ signal.

[4] BACK signal is driven low, releasing bus to external bus master..

[5] BREQ signal state is also sampled in external bus released state.

[6] High level of BREQ signal is sampled.

[7] BACK signal is driven high, ending external bus release cycle.

[8] When there is external access or refresh request of internal bus master during

external bus release while the BREQOE bit is set to 1, BREQO signal goes low.

[9] BREQO signal goes high 1.5 states after rising edge of BACK signal. If BREQO

signal is asserted because of auto-refreshing request, it retains low until auto-refresh cycle starts up.

Data bus

High-Z

Precharge-sel

High-Z

RAS

CKE High-Z

CAS High-Z

SDRAMφ

Row

address

Figure 6.85 Bus Release State Transition Timing when Synchronous DRAM Interface

Section 6 Bus Controller (BSC)

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6.12 Bus Arbitration

This LSI has a bus arbiter that arbitrates bus mastership operations (bus arbitration).

There are four bus masters—the CPU, DTC, DMAC, and EXDMAC—that perform read/write

operations when they have possession of the bus. Each bus master requests the bus by means of a

bus requ est signal. The bus arbiter determines priorities at the prescribed timing , and permits use

of the bus by means of a bus request acknowledge signal. The selected bus master then takes

possession of the bus and begins its operation.

6.12.1 Operation

The bus arbiter detects the bus masters’ bus request signals, and if the bus is requested, sends a bus

request acknowledge signal to the bus master. If there are bus requests from more than one bus

master, the bus request acknowledg e signal is sent to the on e with the highest priority. When a bus

master receives the bus request acknowledge signal, it takes possession of the bus un til that signal

is canceled.

The order of pr iority of the bus mastership is as follows:

(High) EXDMAC > DMAC > DTC > CPU (Low)

An internal bus access by internal bu s masters except the EXDMAC and external bus release, a

refresh when the CBRM bit is 0, and an ex ternal bus access by the EXDMAC can be executed in

parallel.

If an external bus release request, a refresh request, and an external access by an internal bus

master occur simultaneously, the order of priority is as f ollows:

(High) Refresh > EXDMAC > External bus release (Low)

(High) External bus release > External access by internal bus master except EXDMAC (Low)

As a refresh when the CBRM bit in REFCR is cleared to 0 and an external access other than to

DRAM space by an internal bus master can be executed simultaneously, there is no relative order

of priority f or th ese two operations.

6.12.2 Bus Transfer Timing

Even if a bus request is received from a bus master with a higher priority than that of the bus

master that has acquired the bus and is currently operating, the bus is not necessarily transferred

immediately. There are specific timings at which each bus master can relinquish the bus.

Section 6 Bus Controller (BSC)

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CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC,

DMAC, or EXDMAC, the bus arbiter transfers the bus to the bus master that issued the request.

The timing for tr ansfer of the bus is as follows:

• The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in

discrete operations, as in the case of a longword-size access, the bus is not transferred between

the component operations.

• With bit manipulation instructions such as BSET and BCLR, the sequence of operations is:

data read (read), relevant bit manipulation operation (modify), write-back (write). The bus is

not transferred during this read-modify-write cycle, which is executed as a series of bus cycles.

• If the CPU is in sleep mode, the bus is transferred immediately.

DTC: The DTC sends the bus arbiter a request for the bus when an activation request is generated.

The DTC can release the bus after a vector read, a register information read (3 states), a single data

transfer, or a register information write (3 states). It does not release the bus during a register

information read (3 states), a single data tran sfer, or a register information write (3 states).

DMAC: The DMAC sends the bus arbiter a request for the bus when an activation request is

generated.

In the case of an external request in short address mode or no rmal mode, and in cycle steal mode,

the DMAC releases the bus after a single transfer.

In block transfer mode, it releases the bus after transfer of one block, and in burst mode, after

completion of the transfer. However, in the event of an EXDMAC or external bus release request,

which have a high er pr iority than the DMAC, the bus may be tran sferred to the bus master even if

block or burst transfer is in progress.

EXDMAC: The EXDMAC sends the bus arbiter a request for the bus when an activation request

is generated.

As the EXDMAC is used exclusively for transfers to and from the external bus, if the bus is

transferred to the EXDMAC, internal accesses by other internal bus masters are still executed in

parallel.

In normal transfer mode or cycle steal transfer mode, the EXDMAC releases the bus after a single

transfer.

In block transfer mode, it releases the bus after transfer of one block, and in burst transfer mode,

after comp letion of the transfer. By setting the BGUP bit to 1 in EDMDR, it is possible to specif y

Section 6 Bus Controller (BSC)

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temporary release of the bus in the event of an external access request from an internal bus master.

For details see section 8, EXDMA Controller.

External Bus Release: When the BREQ pin goes low and an external bus release request is issued

while the BRLE bit is set to 1 in BCR, a bus r equest is sent to the bus arbiter.

External bus release can be perf ormed on completion of an external bus cycle.

6.13 Bus Controller Operation in Reset

In a reset, this LSI, including the bus controller, enters the reset state immediately, and any

executing bus cycle is aborted.

6.14 Usage Notes

6.14.1 External Bus Release Functio n and All-Module- Clocks-St opped Mode

In this LSI, if the ACSE bit is set to 1 in MSTPCR, and then a SLEEP instruction is executed with

the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFF) or for operation of

the 8-bit timer module alone (MSTPCR = H'FFFE), and a transition is made to the sleep state, the

all-module-clocks-stopped mode is entered in which the clock is also stopped for the bus

controller and I/O ports. In this state, the external bus release function is halted. To use the

external bus release function in sleep mode, the ACSE bit in MSTPCR must be cleared to 0.

Conversely, if a SLEEP instruction to place the chip in all-module-clocks-stopped mode is

executed in the external bus released state, the transition to all-module-clocks-stopped mode is

deferred and performed until after the bus is reco v ered.

6.14.2 External Bus Release Function and Software Standby

In this LSI, internal bus master operation does not stop even while the bus is released, as long as

the program is running in on-chip ROM, etc., and no external access occurs. If a SLEEP

instruction to place the chip in software standby mode is executed while the external bus is

released, the transition to software standby mode is deferred and performed after the bus is

recovered.

Also, since clock oscillation halts in software standby mode, if BREQ goes low in th is mode,

indicating an extern al bus release request, the r equ est cannot be answered until th e chip h a s

recovered from the software standby state.

Section 6 Bus Controller (BSC)

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6.14.3 External Bus Release Function and CBR Refreshing/Auto Refreshing

CBR refreshing/auto refreshing cannot be executed while the external bus is released. Setting the

BREQOE bit to 1 in BCR before hand enables the BREQO signal to be output when a CBR

refresh/auto refresh request is issued.

Note: In the H8S/2678 Group, the auto refresh control is not supported.

6.14.4 BREQO

BREQOBREQO

BREQO Output Timing

When the BREQOE b it is set to 1 an d the BREQO signal is output, BREQO may go low before

the BACK signal.

This will occur if the next external access reque st or CBR refresh request occur s while internal bus

arbitration is in progress after the chip samples a low lev e l of BREQ.

6.14.5 Notes on Usage of the Synchronous DRAM

Setting of Synchrono us DRAM Interfa ce: The DCTL pin must be fixed to 1 to enable the

synchronous DRAM interface. Do not change the DCTL pin during operation.

Connection Cloc k: Be sure to set the clock to be connected to the synchronous DRAM to

SDRAMφ.

WAIT

WAITWAIT

WAIT Pin: In the continuous synchronous DRAM space, insertion of the wait state by the WAIT

pin is disabled rega rdless of the setting of the WA ITE bit in BCR.

Bank Contro l: This LSI cannot carry out the bank control of the synchronous DRAM. All banks

are selected.

Burst Access: The burst read/burst write mode of the synchron ous DRAM is not supported. When

setting the mode register of the synchronous DRAM, set to the burst read/single write and set the

burst length to 1.

CAS Latency: When connecting a synchronous DRAM having CAS latency of 1, set the BE bit

to 0 in th e DRAMCR.

Section 7 DMA Controller (DMAC)

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Section 7 DMA Controller (DMAC)

This LSI has a bu ilt- in DMA controller (DMAC) which can carry out data transfer on up to 4

channels.

7.1 Features

• Selectable as short address mode or full address mode

 Short address mode

Maximum of 4 channels can be used

Dual address mode or single address mode can be selected

In dual address mode, one of the two addresses, transfer source and transfer destination, is

specified as 24 bits and the other as 16 bits

In single address mode, tran sfer source or transfer destination address only is specified as

24 bits

In single address mode, tran sfer can be performed in one bus cycle

Choice of sequential mode, idle mode, or repeat mode for dual address mode and single

address mode

 Full address mode

Maximum of 2 channels can be used

Transfer source and transfer destination addresses as specified as 24 bits

Choice of normal mode or block transfer mode

• 16-Mbyte address space can be specified directly

• Byte or word can be set as the transfer unit

• Activation sources: internal interrupt, external request, auto-request (depending on transfer

mode)

Six 16-bit timer-pulse unit (TPU) compare match/in put capture interrupts

Serial communication interface (SCI_0, SCI_1) transmission complete interrupt, reception

complete interr upt

A/D converter conversion end interrupt

External request

Auto-request

• Module stop mode can be set

DMAS260A_010020020400

Section 7 DMA Controller (DMAC)

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A block diagram of the DMAC is shown in figure 7.1.

Internal address bus

Address buffer

Processor

Internal interrupts

TGI0A

TGI1A

TGI2A

TGI3A

TGI4A

TGI5A

TXI0

RXI0

TXI1

RXI1

ADI

External pins

DREQ0

DREQ1

TEND0

TEND1

DACK0

DACK1

Interrupt signals

DMTEND0A

DMTEND0B

DMTEND1A

DMTEND1B

Control logic

DMAWER

DMACR1B

DMACR1A

DMACR0B

DMACR0A

DMATCR

DMABCR

Data buffer

Internal data bus

MAR_0AH IOAR_0A

ETCR_0A

MAR_0BH IOAR_0B

ETCR_0B

MAR_1AH IOAR_1A

ETCR_1A

MAR_1BH

MAR_0AL

MAR_0BL

MAR_1AL

MAR_1BL

IOAR_1B

ETCR_1B

Legend:

DMAWER : DMA write enable register

DMATCR : DMA terminal control register

DMABCR : DMA band control register (for all channels)

DMACR : DMA control register

MAR : Memory address register

IOAR : I/O address register

ETCR : Execute transfer count register

Channel 0Channel 1

Channel 0AChannel 0BChannel 1AChannel 1B

Module data bus

Figure 7.1 Block Diagram of DMAC

Section 7 DMA Controller (DMAC)

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7.2 Input/Output Pins

Table 7.1 shows the DMAC pin configuration.

Table 7.1 Pin Configuration

Channel Pin Name Symbol I/O Function

0 DMA request 0 DREQ0 Input Channel 0 external request

DMA transfer acknowledge 0 DACK0 Output Channel 0 single address

transfer acknowledge

DMA transfer end 0 TEND0 Output Channel 0 transfer end

1 DMA request 1 DREQ1 Input Channel 1 external request

DMA transfer acknowledge 1 DACK1 Output Channel 1 single address

transfer acknowledge

DMA transfer end 1 TEND1 Output Channel 1 transfer end

7.3 Register Descriptions

• Memory address register_0AH (MAR_0AH)

• Memory address register_0AL (MAR_0AL)

• I/O address register_0A (IOAR_0A)

• Transfer count register_0A (ECTR_0A)

• Memory address register_0BH (MAR_0BH)

• Memory address register_0BL (MAR_0BL)

• I/O address register_0B (IOAR_0B)

• Transfer count register_0B (ECTR_0B)

• Memory address register_1AH (MAR_1AH)

• Memory address register_1AL (MAR_1AL)

• I/O address register_1A (IOAR_1A)

• Transfer count register_1A (ETCR_1B)

• Memory address register_1BH (MAR_1BH)

• Memory address register_1BL (MAR_1BL)

• I/O address register_1B (IOAR_1B)

• Transfer count register_1B (ETCR_1B)

• DMA control register_0A (DMACR_0A)

• DMA control register_0B (DMACR_0B)

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• DMA control register_1A (DMACR_1A)

• DMA control register_1B (DMACR_1B)

• DMA band control register H (DMABCRH)

• DMA band control register L (DMABCRL)

• DMA write enable register (DMAWER)

• DMA terminal contr ol register (DMATCR)

The functions of MAR, IOAR, ETCR, DMACR, and DMABCR differ according to the transfer

mode (short address mode or full address mode). The transfer mode can be selected by means of

the FAE1 and FAE0 bits in DMABCRH. The register configurations for short address mode and

full address mode of channel 0 are shown in table 7.2.

Table 7.2 Short Address Mode and Full Address Mo de (Channel 0)

FAE0 Description

0 Short address mode specified (channels 0A and 0B operate independently)

Channel 0A

MAR_0AH Specifies transfer source/transfer destination address

Specifies transfer destination/transfer source address

Specifies number of transfers

Specifies transfer size, mode, activation source.

Specifies transfer source/transfer destination address

Specifies transfer destination/transfer source address

Specifies number of transfers

Specifies transfer size, mode, activation source.

IOAR_0A

ETCR_0A

DMACR_0A

Channel 0B

MAR_0BH

MAR_0AL

MAR_0BL

IOAR_0B

ETCR_0B

DMACR_0B

1 Full address mode specified (channels 0A and 0B operate in combination as channel 0)

Channel 0

MAR_0AH Specifies transfer source address

Specifies transfer destination address

Not used

Specifies number of transfers

Specifies number of transfers (used in block transfer

mode only)

Specifies transfer size, mode, activation source, etc.

IOAR_0A

ETCR_0A

DMACR_0A

MAR_0BH

MAR_0AL

MAR_0BL

IOAR_0B

ETCR_0B

DMACR_0B

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7.3.1 Memory Addre ss Registers (MARA and MARB)

MAR is a 32-bit readable/writable register that specifies the source address (transfer source

address) or destination address (transfer destination address). MAR consists of two 16-bit registers

MARH and MARL. The upper 8 bits of MARH are reserved: they are always read as 0, and

cannot be modified.

The DMA has four MAR registers: MAR_0A in channel 0 (channel 0A), MAR_0B in channel 0

(channel 0B), MAR_1A in channel 1 (channel 1A), and MAR_1B in channel 1 (channel 1B).

MAR is not initialized by a reset or in standby mode.

Short Address Mo de: In short address mode, MARA and MARB operate independently.

Whether MAR functions as the source address register or as the destination address register can be

selected by means of the DTDIR bit in DMACR.

MAR is incremented or decremented each time a byte or word transfer is executed, so that the

address specified by MAR is constantly updated.

Full Address Mode: In full address mode, MARA functions as the source address register, and

MARB as the destination address register.

MAR is incremented or decremented each time a byte or word transfer is executed, so that the

source or destination address is constantly updated.

7.3.2 I/O Address Registers (IOARA and IOARB)

IOAR is a 16-bit readable/writable register that specifies the lower 16 bits of the source address

(transfer source address) or destination address (transfer destination address). The upper 8 bits of

the transfer address are automatically set to H'FF.

The DMA has four IOAR registers: IOAR_0A in channel 0 (channel 0A), IOAR_0B in channel 0

(channel 0B), IOAR_1A in channel 1 (channel 1A), and IOAR_1B in channel 1 (channel 1B).

Whether IOAR functions as the source address register or as the destination address register can

be selected by mean s of the DTDIR bit in DMACR.

IOAR is not incremented or decremen ted each time a data transfer is executed, so the address

specified by IOAR is fixed.

IOAR is not initialized by a reset or in standby mode.

IOAR can be used in short address mode but not in full address mode.

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7.3.3 Execute Transfer Count Registers (ETCRA and ETCRB)

ETCR is a 16-bit readable/writable register that specifies the number of transfers.

The DMA has four ETCR registers: ETCR_0A in channel 0 (channel 0A), ETCR_0B in channel 0

(channel 0B), ETCR_1A in channel 1 (channel 1A), and ETCR_1B in channel 1 (channel 1B).

ETCR is not initialized by a reset or in standby mode.

Short Address Mo de: The function of ETCR in sequential mode and idle mode differs from that

in repeat mode.

In sequential mode and idle mode, ETCR functions as a 16 -bit transfer counter. ETCR is

decremented by 1 each time a transfer is performed, and when the count reaches H'00, the DTE bit

in DMABCRL is cleared, and transfer ends.

In repeat mode, ETCRL functions as an 8-bit transfer counter and ETCRH functions as a transfer

count holding register. ETCRL is decremented by 1 each time a transfer is performed, and when

the count reaches H'00, ETCRL is loaded with the value in ETCRH. At this point, MAR is

automatically r e stored to the value it had when the count was started. The DTE bit in DMABCRL

is not cleared, and so tr ansfers can be performed repeatedly until th e DTE bit is cleared by the

user.

Full Address Mode: The function of ETCR in normal mode differs from that in block transfer

mode.

In normal mode, ETCRA functions as a 16-bit transfer counter. ETCRA is decremented by 1 each

time a data transfer is performed, and transfer ends when the count reaches H'0000. ETCRB is not

used in normal mode.

In block transfer mode, ETCRAL functions as an 8-bit block size counter and ETCRAH functions

as a block size holding register. ETCRAL is decremented by 1 each time a 1-byte or 1-word

transfer is performed, and when the count reaches H'00, ETCRAL is loaded with the value in

ETCRAH. So by setting the block size in ETCRAH and ETCRAL, it is possible to repeatedly

transfer blocks consisting of any desired number of bytes or words.

In block transfer mode, ETCRB functions as a 16-bit block transfer counter. ETCRB is

decremented by 1 each time a block is transferred, and transfer ends when the count reaches

H'0000.

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7.3.4 DMA Control Registers (DMACRA and DMACRB)

DMACR controls the operation of each DMAC channel.

The DMA has four DMACR registers: DMACR_0A in channel 0 (channel 0A), DMACR_0B in

channel 0 (channel 0B), DMACR_1A in channel 1 (channel 1A), and DMACR_1B in channel 1

(channel 1B).

In short address mode, channels A and B operate independently, and in full address mode,

channels A and B operate together. The bit functions in the DMACR registers differ according to

the transfer mode.

Short Address Mo de:

• DMACR_0A, DMACR_0B, DMACR_1A, and DMARC_1B

Bit Bit Name Initial Value R/W Description

7 DTSZ 0 R/W Data Transfer Size

Selects the size of data to be transferred at one

time.

0: Byte-size transfer

1: Word-size transfer

6 DTID 0 R/W Data Transfer Increment/Decrement

Selects incrementing or decrementing of MAR

after every data transfer in sequential mode or

repeat mode. In idle mode, MAR is neither

incremented nor decremented.

0: MAR is incremented after a data transfer

(Initial value)

• When DTSZ = 0, MAR is incremented by 1

• When DTSZ = 1, MAR is incremented by 2

1: MAR is decremented after a data transfer

• When DTSZ = 0, MAR is decremented by 1

• When DTSZ = 1, MAR is decremented by 2

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Bit Bit Name Initial Value R/W Description

5 RPE 0 R/W Repeat Enable

Used in combination with the DTIE bit in

DMABCR to select the mode (sequential, idle,

or repeat) in which transfer is to be performed.

• When DTIE = 0 (no transfer end interrupt)

0: Transfer in sequential mode

1: Transfer in repeat mode

• When DTIE = 1 (with transfer end interrupt)

0: Transfer in sequential mode

1: Transfer in idle mode

4 DTDIR 0 R/W Data Transfer Direction

Used in combination with the SAE bit in

DMABCR to specify the data transfer direction

(source or destination). The function of this bit

is therefore different in dual address mode and

single address mode.

• When SAE = 0

0: Transfer with MAR as source address and

DACK pin as write strobe

1: Transfer with DACK pin as read strobe and

MAR as destination address

• When SAE = 1

0: Transfer with MAR as source address and

IOAR as destination address

1: Transfer with IOAR as source address and

MAR as destination address

DTF3

DTF2

DTF1

DTF0

R/W

Data Transfer Factor 3 to 0

These bits select the data transf er factor

(activation source). There are some differences

in activation sources for channel A and channel

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Bit Bit Name Initial Value R/W Description

• Channel A

0000: Setting prohibited

0001: Activated by A/D converter conversion

end interrupt

0010: Setting prohibited

0011: Setting prohibited

0100: Activated by SCI channel 0 transmission

complete interrupt

0101: Activated by SCI channel 0 reception

complete interrupt

0110: Activated by SCI channel 1 transmission

complete interrupt

0111: Activated by SCI channel 1 reception

complete interrupt

1000: Activated by TPU channel 0 compare

match/input capture A interrupt

1001: Activated by TPU channel 1 compare

match/input capture A interrupt

1010: Activated by TPU channel 2 compare

match/input capture A interrupt

1011: Activated by TPU channel 3 compare

match/input capture A interrupt

1100: Activated by TPU channel 4 compare

match/input capture A interrupt

1101: Activated by TPU channel 5 compare

match/input capture A interrupt

1110: Setting prohibited

1111: Setting prohibited

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Bit Bit Name Initial Value R/W Description

• Channel B

0000: Setting prohibited

0001: Activated by A/D converter conversion

end interrupt

0010: Activated by DREQ pin rising edge input

(detected as a low level in the first

transfer after transfer is enabled)

0011: Activated by DREQ pin low-level input

0100: Activated by SCI channel 0 transmission

complete interrupt

0101: Activated by SCI channel 0 reception

complete interrupt

0110: Activated by SCI channel 1 transmission

complete interrupt

0111: Activated by SCI channel 1 reception

complete interrupt

1000: Activated by TPU channel 0 compare

match/input capture A interrupt

1001: Activated by TPU channel 1 compare

match/input capture A interrupt

1010: Activated by TPU channel 2 compare

match/input capture A interrupt

1011: Activated by TPU channel 3 compare

match/input capture A interrupt

1100: Activated by TPU channel 4 compare

match/input capture A interrupt

1101: Activated by TPU channel 5 compare

match/input capture A interrupt

1110: Setting prohibited

1111: Setting prohibited

The same factor can be selected for more than

one channel. In this case, activation starts with

the highest-priority channel according to the

relative channel priorities. For relative channel

priorities, see section 7.5.12, Multi-Channel

Operation.

Section 7 DMA Controller (DMAC)

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Full Address Mode:

• DMACR_0A and DMACR_1A

Bit Bit Name Initial Value R/W Description

15 DTSZ 0 R/W Data Transfer Size

Selects the size of data to be transferred at one

time.

0: Byte-size transfer

1: Word-size transfer

13 SAID

SAIDE 0

0R/W

R/W Source Address Increment/Decrement

Source Address Increment/Decrement Enable

These bits specif y whet her source address

decremented, or left unchanged, when data

transfer is performed.

00: MARA is fixed

01: MARA is incremented after a data transfer

• When DTSZ = 0, MARA is incremented by 1

• When DTSZ = 1, MARA is incremented by 2

10: MARA is fixed

11: MARA is decremented after a data transfer

• When DTSZ = 0, MARA is decremented by

• When DTSZ = 1, MARA is decremented by

11 BLKDIR

BLKE 0

0R/W

R/W Block Direction

Block Enable

These bits specify whether normal mode or

block transfer mode is to be used for data

transfer. If block transfer mode is specified, the

BLKDIR bit specifies whether the source side or

the destination side is to be the block area.

x0: Transfer in normal mode

01: Transfer in block transfer mode (destination

side is block area)

11: Transfer in block transfer mode (source side

is block area)

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Bit Bit Name Initial Value R/W Description

All 0 R/W Reserved

These bits can be read from or written to.

However, the write value should always be 0.

Legend:

x: Don't care

• DMACR_0B and DMACR_1B

Bit Bit Name Initial Value R/W Description

70R/WReserved

This bit can be read from or written to.

However, the write value should always be 0.

5DAID

DAIDE 0

0R/W

R/W Destination Address Increment/Decrement

Destination Address Increment/Decrement

Enable

These bits specify whether destination address

decremented, or left unchanged, when data

transfer is performed.

00: MARB is fixed

01: MARB is incremented after a data transfer

• When DTSZ = 0, MARB is incremented by 1

• When DTSZ = 1, MARB is incremented by 2

10: MARB is fixed

11: MARB is decremented after a data transfer

• When DTSZ = 0, MARB is decremented by

• When DTSZ = 1, MARB is decremented by

4— 0 R/WReserved

This bit can be read from or written to.

However, the write value should always be 0.

DTF3

DTF2

DTF1

DTF0

R/W

Data Transfer Factor 3 to 0

These bits select the data trans fer fact or

(activation source). The factors that can be

specified di ffer between normal mode and block

transfer mode.

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Bit Bit Name Initial Value R/W Description

• Normal Mode

0000: Setting prohibited

0001: Setting prohibited

0010: Activated by DREQ pin falling edge input

(detected as a low level in the first

transfer after transfer is enabled)

0011: Activated by DREQ pin low-level input

010x: Setting prohibited

0110: Auto-request (cycle steal)

0111: Auto-request (burst)

1xxx: Setting prohibited

• Block Transfer Mode

0000: Setting prohibited

0001: Activated by A/D converter conversion

end interrupt

0010: Activated by DREQ pin falling edge input

(detected as a low level in the first

transfer after transfer is enabled)

0011: Activated by DREQ pin low-level input

0100: Activated by SCI channel 0 transmission

complete interrupt

0101: Activated by SCI channel 0 reception

complete interrupt

0110: Activated by SCI channel 1 transmission

complete interrupt

0111: Activated by SCI channel 1 reception

complete interrupt

1000: Activated by TPU channel 0 compare

match/input capture A interrupt

1001: Activated by TPU channel 1 compare

match/input capture A interrupt

1010: Activated by TPU channel 2 compare

match/input capture A interrupt

1011: Activated by TPU channel 3 compare

match/input capture A interrupt

1100: Activated by TPU channel 4 compare

match/input capture A interrupt

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Bit Bit Name Initial Value R/W Description

1101: Activated by TPU channel 5 compare

match/input capture A interrupt

1110: Setting prohibited

1111: Setting prohibited

The same factor can be selected for more than

one channel. In this case, activation starts with

the highest-priority channel according to the

relative channel priorities. For relative channel

priorities, see section 7.5.12, Multi-Channel

Operation.

Legend:

x: Don't care

7.3.5 DMA Band Control Registers H and L (DMABCRH a nd DMABCRL)

DMABCR controls the operation of each DMAC channel. The bit functions in the DMACR

registers differ according to the transfer mode.

Short Address Mo de:

• DMABCRH

Bit Bit Name Initial Value R/W Description

15 FAE1 0 R/W Full Address Enable 1

Specifies whether channel 1 is to be used in

short address mode or full address mode. In

short address mode, ch annels 1A and 1B can

be used as independent channels .

0: Short address mode

1: Full address mode

14 FAE0 0 R/W Full Address Enable 0

Specifies whether channel 0 is to be used in

short address mode or full address mode. In

short address mode, ch annels 0A and 0B can

be used as independent channels .

0: Short address mode

1: Full address mode

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Bit Bit Name Initial Value R/W Description

13 SAE1 0 R/W Single Address Enable 1

Specifies whether channel 1B is to be used for

transfer in dual address mode or single address

mode. This bi t is invalid in full address mode.

0: Dual address mode

1: Single address mode

12 SAE0 0 R/W Single Address Enable 0

Specifies whether channel 0B is to be used for

transfer in dual address mode or single address

mode. This bi t is invalid in full address mode.

0: Dual address mode

1: Single address mode

DTA1B

DTA1A

DTA0B

DTA0A

R/W

Data Transfer Acknowledge 1B

Data Transfer Acknowledge 1A

Data Transfer Acknowledge 0B

Data Transfer Acknowledge 0A

These bits enable or disable clearing when

DMA transfer is performed for the internal

interrupt source selected by the DTF3 to DTF0

bits in DMACR.

It the DTA bit is set to 1 when DTE = 1, the

internal interr upt sour ce is cle ared aut omatic all y

by DMA transfer. When DTE = 1 and DTA = 1,

the internal interrupt source does not issue an

interrupt request to the CPU or DTC.

If the DTA bit is cleared to 0 when DTE = 1, the

internal interr upt sour ce is not cle ared when a

transfer is performed, and can issue an

interrupt request to the CPU or DTC in parallel.

In this case, the interrupt source should be

cleared by the CPU or DTC transfer.

When DTE = 0, the inter nal inte rrupt so urce

issues an interrupt request to the CPU or DTC

regardless of the DTA bit setting.

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• DMABCRL

Bit Bit Name Initial Value R/W Description

DTE1B

DTE1A

DTE0B

DTE0A

R/W

Data Transfer Enable 1B

Data Transfer Enable 1A

Data Transfer Enable 0B

Data Transfer Enable 0A

If the DTIE bit is set to 1 when DTE = 0, the

DMAC regards this as indicating the end of a

transfer, and issues a transfer end interrupt

request to the CPU or DTC.

When DTE = 1, data transfer is enabled and the

DMAC waits for a request by the activation

source selected by the DTF3 to DTF0 bits in

DMACR. When a request is issued by the

activation source, DMA transfer is executed.

[Clearing cond iti ons ]

• When initialization is performed

• When the specified number of transfers

have been co mpleted in a transfer mode

other than repeat mode

• When 0 is written to the DTE bit to forcibly

suspend the transfer, or for a similar reason

[Setting condition]

When 1 is written to the DTE bit after reading

DTE = 0

DTIE1B

DTIE1A

DTIE0B

DTIE0A

R/W

Data Transfer End Interrupt Enable 1B

Data Transfer End Interrupt Enable 1A

Data Transfer End Interrupt Enable 0B

Data Transfer End Interrupt Enable 0A

These bits enable or disable an interrupt to the

CPU or DTC when transfer ends. If the DTIE bit

is set to 1 when DTE = 0, the DMAC regards

this as indicating the end of a transfer, and

issues a transfer end interrupt request to the

CPU or DTC.

A transfer end interrupt can be canc eled either

by clearing the DTIE bit to 0 in the interrupt

handling routine, or by performing processing to

continue transfer by setting the transfer counter

and address register again, and then setting the

DTE bit to 1.

Section 7 DMA Controller (DMAC)

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Full Address Mode:

• DMABCRH

Bit Bit Name Initial Value R/W Description

15 FAE1 0 R/W Full Address Enable 1

Specifies whether channel 1 is to be used in

short address mode or full address mode.

In full address mode, channels 1A and 1B are

used together as channel 1.

0: Short address mode

1: Full address mode

14 FAE0 0 R/W Full Address Enable 0

Specifies whether channel 0 is to be used in

short address mode or full address mode.

In full address mode, channels 0A and 0B are

used together as channel 0.

0: Short address mode

1: Full address mode

13, 12 — All 0 R/W Reserved

These bits can be read from or written to.

However, the write value should always be 0.

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Bit Bit Name Initial Value R/W Description

11 DTA1 0 R/W Data Transfer Acknowledge 1

These bits enable or disable clearing when

DMA transfer is performed for the internal

interrupt source selected by the DTF3 to DTF0

bits in DMACR of channel 1.

It the DTA1 bit is set to 1 when DTE1 = 1, the

internal interr upt sour ce is cle ared aut omatic all y

by DMA transfer. When DTE1 = 1 and DTA1 =

1, the internal interrupt source does not issue

an interrupt request to the CPU or DTC.

It the DTA1 bit is cleared to 0 when DTE1 = 1,

the internal interrupt source is not cleared when

a transfer is performed, and can issue an

interrupt request to the CPU or DTC in parallel.

In this case, the interrupt source should be

cleared by the CPU or DTC transfer.

When DTE1 = 0, the internal interrupt source

issues an interrupt request to the CPU or DTC

regardless of the DTA1 bi t setting.

The state of the DTME1 bit does not affect the

above operations.

10 — 0 R/W Reserved

This bit can be read from or written to.

However, the write value should always be 0.

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Bit Bit Name Initial Value R/W Description

9 DTA0 0 R/W Data Transfer Acknowledge 0

These bits enable or disable clearing when

DMA transfer is performed for the internal

interrupt source selected by the DTF3 to DTF0

bits in DMACR of channel 0.

It the DTA0 bit is set to 1 when DTE0 = 1, the

internal interr upt sour ce is cle ared aut omatic all y

by DMA transfer. When DTE0 = 1 and DTA0 =

1, the internal interrupt source does not issue

an interrupt request to the CPU or DTC.

It the DTA0 bit is cleared to 0 when DTE0 = 1,

the internal interrupt source is not cleared when

a transfer is performed, and can issue an

interrupt request to the CPU or DTC in parallel.

In this case, the interrupt source should be

cleared by the CPU or DTC transfer.

When DTE0 = 0, the internal interrupt source

issues an interrupt request to the CPU or DTC

regardless of the DTA0 bi t setting.

The state of the DTME0 bit does not affect the

above operations.

8— 0 R/WReserved

This bit can be read from or written to.

However, the write value should always be 0.

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• DMABCRL

Bit Bit Name Initial Value R/W Description

7 DTME1 0 R/W Data Transfer Master Enable 1

Together with the DTE1 bit, this bit controls

enabling or disabling of data tran sfer on

channel 1. When both the DTME1 bit and DTE1

bit are set to 1, transfer is enabled for channel

If channel 1 is in the middle of a burst mode

transfer when an NMI interrupt is generated, the

DTME1 bit is cleared, the transfer is interrupted,

and bus mastership passes to the CPU. When

the DTME1 bit is subsequently set to 1 again,

the interrupted transfer is resumed. In block

transfer mode, howe ver, the DTME1 bit is not

cleared by an NMI interrupt, and transfer is not

interrupted.

[Clearing cond iti ons ]

• When initialization is performed

• When NMI is input in burst mode

• When 0 is written to the DTME1 bit

[Setting condition]

When 1 is written to DTME1 after reading

DTME1 = 0

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Bit Bit Name Initial Value R/W Description

6 DTE1 0 R/W Data Transf er Enable 1

Enables or disables DMA transfer for the

activation source selected by the DTF3 to DTF0

bits in DMACR of channel 1.

When DTE1 = 0, data transfer is disabled and

the activation sour ce is ignored. If the activati on

source is an internal interrupt, an interrupt

request is issued to the CPU or DTC. If the

DTIE1 bit is set to 1 when DTE1 = 0, the DMAC

regards this as indicating the end of a transfer,

and issues a transfer end interrupt request to

the CPU.

When DTE1 = 1 and DTME1 = 1, data transfer

is enabled and the DMAC waits for a request by

the activation source. When a request is issued

by the activation source, DMA transfer is

executed.

[Clearing cond iti ons ]

• When initialization is performed

• When the specified number of transfers

have been completed

• When 0 is written to the DTE1 bit to forcibly

suspend the transfer, or for a similar reason

[Setting condition]

When 1 is written to the DTE1 bit after reading

DTE1 = 0

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Bit Bit Name Initial Value R/W Description

5 DTME0 0 R/W Data Transfer Master Enable 0

Together with the DTE0 bit, this bit controls

enabling or disabling of data tran sfer on

channel 0. When both the DTME0 bit and DTE0

bit are set to 1, transfer is enabled for channel

If channel 0 is in the middle of a burst mode

transfer when an NMI interrupt is generated, the

DTME0 bit is cleared, the transfer is interrupted,

and bus mastership passes to the CPU. When

the DTME0 bit is subsequently set to 1 again,

the interrupted transfer is resumed. In block

transfer mode, however, the DTME0 bit is not

cleared by an NMI interrupt, and transfer is not

interrupted.

[Clearing cond iti ons ]

• When initialization is performed

• When NMI is input in burst mode

• When 0 is written to the DTME0 bit

[Setting condition]

When 1 is written to DTME0 after reading

DTME0 = 0

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Bit Bit Name Initial Value R/W Description

4 DTE0 0 R/W Data Transf er Enable 0

Enables or disables DMA transfer for the

activation source selected by the DTF3 to DTF0

bits in DMACR of channel 0.

When DTE0 = 0, data transfer is disabled and

the activation sour ce is ignored. If the activati on

source is an internal interrupt, an interrupt

request is issued to the CPU or DTC. If the

DTE0 bit is cleared to 0 when DTIE0 = 1, the

DMAC regards this as indicating the end of a

transfer, and issues a transfer end interrupt

request to the CPU.

When DTE0 = 1 and DTME0 = 1, data transfer

is enabled and the DMAC waits for a request by

the activation source. When a request is issued

by the activation source, DMA transfer is

executed.

[Clearing cond iti ons ]

• When initialization is performed

• When the specified number of transfers

have been completed

• When 0 is written to the DTE0 bit to forcibly

suspend the transfer, or for a similar reason

[Setting condition]

When 1 is written to the DTE0 bit after reading

DTE0 = 0

3 DTIE1B 0 R/W Data Transfer Interrupt Enable 1B

Enables or disables an interrupt to the CPU or

DTC when transfer on channel 1 is interrupted.

If the DTME1 bit is cleared to 0 when DTIE1B =

1, the DMAC regards this as indicating a break

in the transfer, and issues a transfer break

interrupt request to the CPU or DTC.

A transfer break interrupt can be canceled

either by clearing the DTIE1B bit to 0 in the

interrupt handling routine, or by pe rforming

processing to continue transfer by setting the

DTME1 bit to 1.

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Bit Bit Name Initial Value R/W Description

2 DTIE1A 0 R/W Data Transfer End Interrupt Enable 1A

Enables or disables an interrupt to the CPU or

DTC when transfer ends. If the DTE1 bit is

cleared to 0 when DTIE1A= 1, the DMAC

regards this as indicating the end of a transfer,

and issues a transfer end interrupt request to

the CPU or DTC.

A transfer end interrupt can be canc eled either

by clearing the DTIE1A bit to 0 in the interrupt

handling routine, or by performing processing to

continue transfer by setting the transfer counter

and address register again, and then setting the

DTE1 bit to 1.

1 DTIE0B 0 R/W Data Transfer Interrupt Enable 0B

Enables or disables an interrupt to the CPU or

DTC when transfer on channel 1 is interrupted.

If the DTME0 bit is cleared to 0 when DTIE0B=

1, the DMAC regards this as indicating a break

in the transfer, and issues a transfer break

interrupt request to the CPU or DTC.

A transfer break interrupt can be canceled

either by clearing the DTIE0B bit to 0 in the

interrupt handling routine, or by pe rforming

processing to continue transfer by setting the

DTME0 bit to 1.

0 DTIE0A 0 R/W Data Transfer End Interrupt Enable 0A

Enables or disables an interrupt to the CPU or

DTC when transfer ends. If the DTE0 bit is

cleared to 0 when DTIE0A = 1, the DMAC

regards this as indicating the end of a transfer,

and issues a transfer end interrupt request to

the CPU or DTC.

A transfer end interrupt can be canc eled either

by clearing the DTIE0A bit to 0 in the interrupt

handling routine, or by performing processing to

continue transfer by setting the transfer counter

and address register again, and then setting the

DTE0 bit to 1.

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7.3.6 DMA Write Enable Register (DMAWER)

The DMAC can activate the DTC with a tr ansfer end interru pt, rewrite the channel on which the

transfer ended using a DTC chain transfer, and then reactivate the DTC. DMAWER applies

restrictions for changing all bits of DMACR, and specific bits for DMATCR and DMABCR for

the specific channel, to prevent inadvertent rewriting of registers other than those for the channel

concerned. The restrictions applied by DMAWER are valid for the DTC.

Bit Bit Name Initial Value R/W Description

All 0 — Reserved

These bits are always read as 0 and cannot be

modified.

3 WE1B 0 R/W Write Enable 1B

Enables or disables writes to all bits in

DMACR1B, bits 11, 7, and 3 in DMABCR, and

bit 5 in DMATCR.

0: Writes are disabled

1: Writes are enabled

2 WE1A 0 R/W Write Enable 1A

Enables or disables writes to all bits in

DMACR1A, and bits 10, 6, and 2 in DMABCR.

0: Writes are disabled

1: Writes are enabled

1 WE0B 0 R/W Write Enable 0B

Enables or disables writes to all bits in

DMACR0B, bits 9, 5, and 1 in DMABCR, and bit

4 in DMATCR.

0: Writes are disabled

1: Writes are enabled

0 WE0A 0 R/W Write Enable 0A

Enables or disables writes to all bits in

DMACR0A, and bits 8, 4, and 0 in DMABCR.

0: Writes are disabled

1: Writes are enabled

Figure 7.2 shows the transfer areas for activating the DTC with a channel 0A transfer end interrupt

request, and reactivating channel 0A. The address register and count register areas are set again

during the first DTC transfer, then the control register area is set again during the second DTC

Section 7 DMA Controller (DMAC)

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chain transfer. When re-setting the control register area, perform masking by setting bits in

DMAWER to prevent modification of the contents of other channels.

DTC

MAR_0A

IOAR_0A

ETCR_0A

MAR_0B

IOAR_0B

ETCR_0B

MAR_1A

IOAR_1A

ETCR_1A

MAR_1B

IOAR_1B

ETCR_1B

DMATCR

DMACR_0B

DMACR_1B

DMAWER

DMACR_0A

DMACR_1A

DMABCR

Second transfer area

using chain transfer

First transfer area

Figure 7.2 Areas for Register Re-Setting by DTC (Channel 0A)

Writes by the DTC to bits 15 to 12 ( FAE and SAE) in DMABCR are invalid regardless of the

DMAWER settings. These bits should be changed, if necessary, by CPU processing.

In writes by the DTC to bits 7 to 4 (DTE) in DMABCR, 1 can be written without first reading 0.

To reactivate a channel set to full address mode, write 1 to both Write Enable A and Wr ite Enable

B for the channel to be reactivated.

MAR, IOAR, and ETCR can alway s b e written to regar dless of the DMAWER setting s. Wh en

modifying these registers, the channel to be modified should be halted.

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7.3.7 DMA Terminal Control Register (DMATCR)

DMATCR controls enabling or disabling of output from the DMAC transfer end pin. A port can

be set for output automatically, and a transfer end signal output, by setting the appropriate bit. The

TEND pin is available only for channel B in short address mode. Except for the block transfer

mode, a transfer end signal asserts in the transfer cycle in which the transfer counter contents

reaches 0 regardless of the activation source. In the block transfer mode, a transfer end signal

asserts in the transfer cycle in which the block counter contents reaches 0.

Bit Bit Name Initial Value R/W Description

7, 6 All 0 Reserved

These bits are always read as 0 and cannot be

modified.

5 TEE1 0 R/W Transfer End Enable 1

Enables or disables transfer end pin 1 (TEND1)

output.

0: TEND1 pin output disabled

1: TEND1 pin output enabled

4 TEE0 0 R/W Transfer End Enable 0

Enables or disables transfer end pin 0 (TEND0)

output.

0: TEND0 pin output disabled

1: TEND0 pin output enabled

All 0 Reserved

These bits are always read as 0 and cannot be

modified.

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7.4 Activation Sources

DMAC activation sources consist of internal interrupt requests, external requests, and auto-

requests. The DMAC activation sources that can be specified depend on the transfer mode and

channel, as shown in table 7.3.

Table 7.3 DMAC Activation Sources

Short Address Mode Full Address Mode

Activation Source Channels

0A and 1A Channels

0B and 1B Normal

Mode

Block

Transfer

Mode

ADI O O X O

TXI0 O O X O

RXI0 O O X O

TXI1 O O X O

RXI1 O O X O

TGI0A O O X O

TGI1A O O X O

TGI2A O O X O

TGI3A O O X O

TGI4A O O X O

Internal

interrupts

TGI5A O O X O

DREQ pin falling edge input X O O OExternal

requests DREQ pin low-level input X O O O

Auto-request X X O X

Legend:

O: Can be specified

X: Cannot be specified

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7.4.1 Activation by Internal Interrupt Request

An interrupt request selected as a DMAC activation source can also simultaneously generate an

interrupt request for the CPU or DTC. For details, see section 5, Interrupt Controller.

With activation by an internal interrupt request, the DMAC accepts the interrupt request

independently of the interrupt controller. Consequently, interrupt controller priority settings are

irrelevant.

If the DMAC is activated by a CPU interrupt source or an interrupt request that is not used as a

DTC activation source (DTA = 1), the interrupt request flag is cleared automatically by the DMA

transfer. With ADI, TXI and RXI interrupts, however, the interrupt source flag is not cleared

unless the relevant register is accessed in a DMA transfer. If the same interrupt is used as an

activation source for more than one channel, the interrupt request flag is cleared when the highest-

priority channel is activated. Transfer requests for other channels are held pending in the DMAC,

and activation is carried out in order of priority.

When DTE = 0 after comp letion of a transfer, an interrupt request from the selected activation

source is no t sent to the DMAC, regardless o f the DTA bit setting. In this case, the relevant

interrup t r equ e st is sent to the CPU or DTC.

When an interrupt request signal f or DMAC activation is also used for an interrupt re quest to the

CPU or DTC activation ( DTA = 0), the interrupt requ e st f lag is not cleared by the DMAC.

7.4.2 Activation by External Request

If an external request (DREQ pin) is specified as a DMAC activation source, the relevant port

should be set to input mode in advance. Level sensing or edge sensing can be used for external

requests.

External request operation in normal mode of short address mode or full address mode is

described below.

When edge sen sing is selected, a byte or word is transferred each time a high-to-low transition is

detected on the DREQ pin. The next data transfer may not be performed if the next edge is input

before data tran sf er is completed.

When level sensin g is selected, the DMAC stands b y for a transfer r equest while the DREQ pin is

held high. While the DREQ pin is held low, tr ansfers continu e in su ccession, with the bus being

released each time a byte or word is transferred. If the DREQ pin goes high in the middle of a

transfer, the transfer is interrupted and the DMAC stands by for a transfer request.

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7.4.3 Activation by Auto-Request

Auto-req uest is activated by reg ister settin g only, and transfer continue s to the end. With auto-

request activation, cycle steal mode or burst mode can be selected.

In cycle steal mode, the DMAC releases the bus to another bus master each time a byte or word is

transferred. DMA and CPU cycles are usually repeated alternately. In burst mode, the DMAC

keeps po ssession of the bus until the end of the tr ansfer so that tran sf er is pe r formed continuously.

7.5 Operation

7.5.1 Transfer Modes

Table 7.4 lists th e DMAC tr ansfer mod e s.

Table 7.4 DMAC Transfer Modes

Transfer Mode Transfer Source Remarks

Short

address

mode

Dual address mode

(1) Sequential mode

•Memory address i ncrem ent ed or

decremented by 1 or 2

•Number of transfers :

1 to 65,536

(2) Idle mode

•Memory address fi xed

•Number of transfers :

1 to 65,536

(3) Repeat mode

•Memory address i ncrem ent ed or

decremented by 1 or 2

•Continues transf er aft er sending

number of transfers (1 to 256) and

restoring the initi al v al ue

•TPU channel 0 to 5

compare match/input

capture A interrupt

•SCI tran s mis sio n comple te

interrupt

•SCI rec eption complete

interrupt

•A/D converter conversion

end interrupt

•External request

•Up to 4 channels can

operate independently

•External request

applies to channel B

only

•Single address mode

applies to channel B

only

Single address mode

•1-byte or 1-word transfer for a single

transfer request

•1-bus cycl e transf er by means of

DACK pin instead of using addres s

for specifying I/O

•Sequential mode, idle mode, or

repeat mode can be specified

•External request

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Transfer Mode Transfer Source Remarks

Normal mode

(1) Auto-reques t

•Transfer request is int ernal ly hel d

•Number of transfers (1 to 65,536) is

continuously sent

•Burst/cycle steal transfer can be

selected

Auto-request

Full

address

mode

(2) External request

•1-byte or 1-word transfer for a single

transfer request

•Number of transfers : 1 to 65,536

External request

Block transfer mode

•Transfer of 1-block, size selected for

a single transfer request

•Number of transfers : 1 to 65,536

•Source or destinati on can be

selected as bl ock area

•Block size: 1 to 256 bytes or word

•TPU channel 0 to 5 compare

match/input capture A

interrupt

•SCI tran s mis sio n comple te

interrupt

•SCI rec eption complete

interrupt

•A/D converter conversion end

interrupt

•External request

•Max. 2-channel

operation, combining

channels A and B

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7.5.2 Sequential Mo de

Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode,

MAR is updated after each byte or word transfer in response to a single transfer request, and this is

executed the number of times specified in ETCR. One address is specified by MAR, and the other

by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR.

Table 7.5 summarizes register functions in sequential mode.

Table 7.5 Register Functions in Sequential Mode

Function

23 0

MAR

Source

address

Destination

address

Start address of

transfer destination

or transfer source

Incremented/

decremented

every transfer

23 0

IOAR

H'FF

Destination

address

Source

address

Start address of

transfer source or

transfer destination

Fixed

015 ETCR

Transfer counter Number of transfers Decremented

every transfer;

transfer ends

when count

reaches H'0000

MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is

incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the

lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF.

Figure 7. 3 illu str a tes operation in sequential mo de.

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Address T

Address B

Transfer IOAR

1 byte or word transfer performed in

response to 1 transfer request

Legend:

Address T = L

Address B = L + (–1)

DTID

· (2

DTSZ

· (N – 1))

Where: L = Value set in MAR

N = Value set in ETCR

Figure 7.3 Operat ion in Sequential Mode

The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a

data transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and data

transfer ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or

DTC. The maximum number of transfers, when H'0000 is set in ETCR, is 65,536.

Transfer requests (activation sources) consist of external requests, SCI transmission complete and

reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts.

Figure 7.4 shows an example of the setting procedure for sequential mode.

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Sequential mode setting

Set DMABCRH

Set transfer source

and transfer destination

addresses

Set number of transfers

Set DMACR

Read DMABCRL

Set DMABCRL

Sequential mode

[1]

[2]

[3]

[4]

[5]

[6]

[1] Set each bit in DMABCRH.

• Clear the FAE bit to 0 to select short address

mode.

• Specify enabling or disabling of internal

interrupt clearing with the DTA bit.

[2] Set the transfer source address and transfer

destination address in MAR and IOAR.

[3] Set the number of transfers in ETCR.

[4] Set each bit in DMACR.

• Set the transfer data size with the DTSZ bit.

• Specify whether MAR is to be incremented or

decremented with the DTID bit.

• Clear the RPE bit to 0 to select sequential

mode.

• Specify the transfer direction with the DTDIR

bit.

• Select the activation source with bits DTF3 to

DTF0.

[5] Read the DTE bit in DMABCRL as 0.

[6] Set each bit in DMABCRL.

• Specify enabling or disabling of transfer end

interrupts with the DTIE bit.

• Set the DTE bit to 1 to enable transfer.

Figure 7.4 Example of Sequential Mode Setting Pro cedure

7.5.3 Idle Mode

Idle mod e can be specified by setting the RPE bit in DMACR and DTIE bit in DMABCRL to 1. In

idle mode, one by te or word is transferred in response to a single transfer request, and this is

executed the number of times specified in ETCR. One address is specified by MAR, and the other

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by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.6

summarizes re gister functions in idle mode.

Table 7.6 Register Functions in Idle Mode

Function

23 0

MAR

Source

address

Destination

address

Start address of

transfer destination

or transfer source

Fixed

23 0

IOAR

H'FF

Destination

address

Source

address

Start address of

transfer source or

transfer destination

Fixed

015 ETCR

Transfer counter Number of transfers Decremented

every transfer;

transfer ends

when count

reaches H'0000

MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is

neither incremented nor decremented by a data transfer. IOAR specifies the lower 16 bits of the

other address. The upper 8 bits of IOAR have a value of H'FF.

Figure 7. 5 illu str a tes operation in idle mode.

Transfer IOAR

1 byte or word transfer performed in

response to 1 transfer request

MAR

Figure 7.5 Operation in Idle Mode

The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a

transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and data transfer

ends. If the DTIE bit is set to 1 at this time, an interrupt re quest is sen t to the CPU or DTC. The

maximum number of transfers, when H'0000 is set in ETCR, is 65,536.

Transfer requests (activation sources) consist of external requests, SCI transmission complete and

reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts.

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Figure 7.6 shows an example of the setting procedure for idle mode.

Idle mode setting

Set DMABCRH

Set transfer source

and transfer destination

addresses

Set number of transfers

Set DMACR

Read DMABCRL

Set DMABCRL

Idle mode

[1]

[2]

[3]

[4]

[5]

[6]

[1] Set each bit in DMABCRH.

• Clear the FAE bit to 0 to select short address

mode.

• Specify enabling or disabling of internal

interrupt clearing with the DTA bit.

[2] Set the transfer source address and transfer

destination address in MAR and IOAR.

[3] Set the number of transfers in ETCR.

[4] Set each bit in DMACR.

• Set the transfer data size with the DTSZ bit.

• Specify whether MAR is to be incremented or

decremented with the DTID bit.

• Set the RPE bit to 1.

• Specify the transfer direction with the DTDIR

bit.

• Select the activation source with bits DTF3 to

DTF0.

[5] Read the DTE bit in DMABCRL as 0.

[6] Set each bit in DMABCRL.

• Set the DTIE bit to 1.

• Set the DTE bit to 1 to enable transfer.

Figure 7.6 Example of Idle Mode Setting Procedure

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7.5.4 Repeat Mode

Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit in

DMABCRL to 0. In repeat mode, MAR is updated after each byte or word transfer in response to

a single transfer request, and this is executed the number of times specified in ETCRL. On

completion of the specified number of transfers, MAR and ETCRL are automatically restored to

their original settings and operation continues. One address is sp ecified by MAR, and the other by

IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.7

summarizes register functions in repeat mode.

Table 7.7 Register Functio ns in Repeat Mo de

Function

23 0

MAR

Source

address

Destination

address

Start address of

transfer destination

or transfer source

Incremented/

decremented

every transfer.

Initial setting is

restored when

value reaches

H'0000

23 0

IOAR

H'FF

Destination

address

Source

address

Start address of

transfer source or

transfer destination

Fixed

ETCRH

ETCRL

Holds number of

transfers

Transfer counter

Number of transfers

Fixed

Decremented

every transfer.

Loaded with

ETCRH value

when count

reaches H'00

MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is

incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the

lower 16 bits of the other address. The upper 8 bits of IOAR have a value of H'FF. The number of

transfers is specified as 8 bits by ETCRH and ETCRL. The maximum number of transfers, when

H'00 is set in both ETCRH and ETCRL, is 256.

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In repeat mode, ETCRL functions as the transfer counter, and ETCRH is used to hold the number

of transfers. ETCRL is decremented by 1 each time a data transfer is executed, and when its value

reaches H'00, it is loaded with the value in ETCRH. At the same time, the value set in MAR is

restored in accordance with th e values of the DTSZ and DTID bits in DMACR. The MAR

restoration operation is as shown below.

MAR = MAR – (–1)DTID · 2DTSZ · ETCRH

The same value should be set in ETCRH and ETCRL.

In repeat mode, oper ation contin ues until the DTE bit in DMABCRL i s cleared . To end the

transfer operation, therefore, the DTE bit should be cleared to 0. A transfer end interrupt request is

not sent to th e CPU or DTC. By setting th e DTE bit to 1 again after it has been cleared , the

operation can be restarted from the transfer after that terminated when the DTE bit was cleared.

Figure 7. 7 illu str a tes operation in repeat mode.

Address T

Address B

Transfer IOAR

1 byte or word transfer performed in

response to 1 transfer request

Legend:

Address T = L

Address B = L + (–1)

DTID

· (2

DTSZ

· (N – 1))

Where: L = Value set in MAR

N = Value set in ETCR

Figure 7.7 Operation in Repeat mode

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Transfer requests (activation sources) consist of external requests, SCI transmission complete and

reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts.

External requests can only be specified for channel B.

Figure 7.8 shows an example of the setting procedure for repeat mode.

Repeat mode setting

Set DMABCRH

Set transfer source

and transfer destination

addresses

Set number of transfers

Set DMACR

Read DMABCRL

Set DMABCRL

Repeat mode

[1]

[2]

[3]

[4]

[5]

[6]

[1] Set each bit in DMABCRH.

• Clear the FAE bit to 0 to select short address

mode.

• Specify enabling or disabling of internal

interrupt clearing with the DTA bit.

[2] Set the transfer source address and transfer

destination address in MAR and IOAR.

[3] Set the number of transfers in both ETCRH and

ETCRL.

[4] Set each bit in DMACR.

• Set the transfer data size with the DTSZ bit.

• Specify whether MAR is to be incremented or

decremented with the DTID bit.

• Set the RPE bit to 1.

• Specify the transfer direction with the DTDIR

bit.

• Select the activation source with bits DTF3 to

DTF0.

[5] Read the DTE bit in DMABCRL as 0.

[6] Set each bit in DMABCRL.

• Clear the DTIE bit to 0.

• Set the DTE bit to 1 to enable transfer.

Figure 7.8 Ex ample of Repeat Mode Setting Procedure

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7.5.5 Single Address Mode

Single address mode can only be specif ied fo r channel B. Th is m ode can be specified by settin g

the SAE bit in DMABC RH to 1 in short addr ess mode.

One address is specified by MAR, and the other is set automatically to the data transfer

acknowledge pin (DACK). The transfer direction can be specified by the DTDIR bit in DMACR.

Table 7.8 summarizes register functions in single address mode.

Table 7.8 Register Functions in Single Address Mode

Function

23 0

MAR

Source

address

Destination

address

Start address of

transfer destination

or transfer source

See sections

7.5.2, Sequential

Mode, 7.5.3, Idle

Mode, and 7.5.4,

Repeat Mode.

DACK pin Write

strobe Read

strobe (Set automatically

by SAE bit; IOAR

is invalid)

Strobe for

external dev ice

015 ETCR

Transfer counter Number of transfers See sections

7.5.2, Sequential

Mode, 7.5.3, Idle

Mode, and 7.5.4,

Repeat Mode.

MAR specifies the start address of the transfer source or transfer destination as 24 bits. IOAR is

invalid; in its place the strobe for external devices (DACK) is output.

Figure 7. 9 illustrates operation in sing le add ress mode (when sequential mode is specif ied).

Section 7 DMA Controller (DMAC)

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Address T

Address B

Transfer DAC

1-byte or -word transfer performed in

response to 1 transfer request

Legend:

Address T = L

Address B = L + (–1)

DTID

· (2

DTSZ

· (N – 1))

Where: L = Value set in MAR

N = Value set in ETCR

Figure 7.9 Operat ion in Single Address Mode (When Sequentia l Mode Is Spec ified)

Figure 7.10 shows an example of the setting procedure for single address mode (when sequential

mode is specified).

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Single address

mode setting

Set DMABCRH

Set transfer source and

transfer destination

addresses

Set number of transfers

Set DMACR

Read DMABCRL

Set DMABCRL

Single address mode

[1]

[2]

[3]

[4]

[5]

[6]

[1] Set each bit in DMABCRH.

• Clear the FAE bit to 0 to select short address

mode.

• Set the SAE bit to 1 to select single address

mode.

• Specify enabling or disabling of internal

interrupt clearing with the DTA bit.

[2] Set the transfer source address/transfer

destination address in MAR.

[3] Set the number of transfers in ETCR.

[4] Set each bit in DMACR.

• Set the transfer data size with the DTSZ bit.

• Specify whether MAR is to be incremented or

decremented with the DTID bit.

• Clear the RPE bit to 0 to select sequential

mode.

• Specify the transfer direction with the DTDIR

bit.

• Select the activation source with bits DTF3 to

DTF0.

[5] Read the DTE bit in DMABCRL as 0.

[6] Set each bit in DMABCRL.

• Specify enabling or disabling of transfer end

interrupts with the DTIE bit.

• Set the DTE bit to 1 to enable transfer.

Figure 7.10 Example of Single Address Mode Setting Pro cedure

(When Sequential Mode Is Specified)

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7.5.6 Normal Mode

In normal mode, transfer is performed with channels A and B used in combination. Normal mode

can be specified by setting the FAE bit in DMABCRH to 1 and clearing the BLKE bit in

DMACRA to 0. In normal mode, MAR is updated after data transfer of a byte or word in response

to a single transfer request, and this is executed the number of times specified in ETCRA. The

transfer source is specified by MARA, and the transfer destination by MARB. Table 7.9

summarizes register functions in normal mode.

Table 7.9 Register Functions in Normal Mode

23 0

MARA

Source address

transfer source Incremented/

decremented ev ery

transfer, or fixed

23 0

MARB

Destination

address register Start address of

transfer destination Incremented/

decremented ev ery

transfer, or fixed

015 ETCRA

Transfer counter Number of transfers Decremented every

transfer; transfer ends

when count reaches

H'0000

MARA and MARB specify the start addresses of the transfer source and transfer destination,

respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or

word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be

set separately f or MARA and MARB.

The number of transfers is specified by ETCRA as 16 bits. ETCRA is decremented by 1 each time

a transfer is performed, and when its value reaches H'0000 the DTE bit in DMABCRL is cleared

and transfer ends. If the DTIE bit in DMABCRL is set to 1 at this time, an interrupt request is sent

to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCRA, is 65,536.

Figure 7. 11 illustrates oper a tion in normal mode.

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Address T

Address B

Transfer Address T

Legend:

Address

Where:

Address B

= L

+ SAIDE · (–1)

SAID

· (2

DTSZ

· (N – 1))

= L

+ DAIDE · (–1)

DAID

· (2

DTSZ

· (N – 1))

= Value set in MARA

= Value set in MARB

= Value set in ETCRA

Figure 7.11 Operation in Normal Mode

Transfer requests (activation sources) are external requests and auto-requests. With auto-request,

the DMAC is only activated by register setting, and the specified number of transfers are

performed automatically. With auto-request, cycle steal mode or burst mode can be selected. In

cycle steal mode, the bus is released to another bus master each time a transfer is performed. In

burst mode, the bus is held continuously until transfer ends.

Figure 7.12 shows an example of the setting procedure for normal mode.

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Normal mode setting

Set DMABCRH

Set transfer source and

transfer destination

addresses

Set number of transfers

Set DMACR

Read DMABCRL

Set DMABCRL

Normal mode

[1]

[2]

[3]

[4]

[5]

[6]

[1] Set each bit in DMABCRH.

• Set the FAE bit to 1 to select full address

mode.

• Specify enabling or disabling of internal

interrupt clearing with the DTA bit.

[2] Set the transfer source address in MARA, and

the transfer destination address in MARB.

[3] Set the number of transfers in ETCRA.

[4] Set each bit in DMACRA and DMACRB.

• Set the transfer data size with the DTSZ bit.

• Specify whether MARA is to be incremented,

decremented, or fixed, with the SAID and

SAIDE bits.

• Clear the BLKE bit to 0 to select normal

mode.

• Specify whether MARB is to be incremented,

decremented, or fixed, with the DAID and

DAIDE bits.

• Select the activation source with bits DTF3 to

DTF0.

[5] Read DTE = 0 and DTME = 0 in DMABCRL.

[6] Set each bit in DMABCRL.

• Specify enabling or disabling of transfer end

interrupts with the DTIE bit.

• Set both the DTME bit and the DTE bit to 1 to

enable transfer.

Figure 7.12 Example of Normal Mode Setting Procedure

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7.5.7 Block Transfer Mode

In block transfer mode, data transfer is performed with channels A and B used in combination.

Block tr ansfer mode can be specif ied by setting the FAE bit in DM A BCRH and th e BLKE bit in

DMACRA to 1. In block tran sfer mode, a data transfer of the specified block size is carried out in

response to a single transfer request, and this is executed for the number of times specified in

ETCRB. The transfer source is specified by MARA, and the transfer destination by MARB. Either

the transfer source or the transfer destination can be selected as a block area (an area composed of

a number of bytes or words). Table 7.10 summarizes register functions in block transfer mode.

Table 7.10 Register Functions in Block Transfer Mode

23 0

MARA

Source address

transfer source Incremented/decremented

every transfer, or fixed

23 0

MARB

Destination

address register Start address of

transfer

destination

Incremented/decremented

every transfer, or fixed

ETCRAH

ETCRAL

Holds block

size

Block size

counter

Block size

Fixed

Decremented every

transfer; ETCRH value

copied when count

reaches H'00

15 0

ETCRB

Block transfer

counter Number of block

transfers Decremented every block

transfer; transfer ends

when count reaches

H'0000

MARA and MARB specify the start addresses of the transfer source and transfer destination,

respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or

word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be

set separately for MARA and MARB. Whether a block is to be designated for MARA or for

MARB is specified by the BLKDIR bit in DMACRA.

To specify the number of transfers, if M is the size of one block (where M = 1 to 256) and N

transfers are to be performed (where N = 1 to 65,536), M is set in both ETCRAH and ETCRAL,

and N in ETCRB.

Figure 7.13 illustrates opera tion in block transfer mode when MARB is designated as a block area.

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Address TA

Address BA

Transfer

Address TB

Address BB

1st block

2nd block

Nth block

Block area

Consecutive transfer

of M bytes or words

is performed in

response to one

request

Legend:

Address

Where:

= LA

= LB

= LA + SAIDE · (–1)SAID · (2DTSZ · (M·N – 1))

= LB + DAIDE · (–1)DAID · (2DTSZ · (N – 1))

= Value set in MARA

= Value set in MARB

= Value set in ETCRB

= Value set in ETCRAH and ETCRAL

Figure 7.13 Operation in Block Transfer Mode (BLKDIR = 0)

Figure 7.14 illustrates opera tio n in block transfer mode when MARA is designated as a block area.

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Address T

Address B

Transfer

Address T

Address B

1st block

2nd block

Nth block

Block area

Consecutive transfer

of M bytes or words

is performed in

response to one

request

Legend:

Address

Where:

= L

+ SAIDE · (–1)

SAID

· (2

DTSZ

· (N – 1))

= L

+ DAIDE · (–1)

DAID

· (2

DTSZ

· (M·N – 1))

= Value set in MARA

= Value set in MARB

= Value set in ETCRB

= Value set in ETCRAH and ETCRAL

Figure 7.14 Operation in Block Transfer Mode (BLKDIR = 1)

ETCRAL is decremented by 1 each time a byte or word transfer is performed. In response to a

single transfer request, burst transfer is performed until the value in ETCRAL reaches H'00.

ETCRAL is then loaded with the value in ETCRAH. At this time, th e value in the MAR register

for which a block designation has been given by the BLKDIR bit in DMACRA is restored in

accordance with the DTSZ, SAID/DAID, and SAIDE/DAIDE bits in DMACR.

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ETCRB is decremented by 1 after every block transfer, and when the count reaches H'0000 the

DTE bit in DMABCRL is cleared an d transfer ends. If the DTIE bit in DMABCRL i s set to 1 at

this point, an interrupt request is sent to the CPU or DTC.

Figure 7.15 shows the operation flow in block transfer mode.

Acquire bus

ETCRAL = ETCRAL – 1

Transfer request?

ETCRAL = H'00

Release bus

BLKDIR = 0

ETCRAL = ETCRAH

ETCRB = ETCRB – 1

ETCRB = H'0000

Start

(DTE = DTME = 1)

Read address specified by MARA

MARA = MARA + SAIDE·(–1)

SAID

·2

DTSZ

Write to address specified by MARB

MARB = MARB + DAIDE·(–1)

DAID

·2

DTSZ

MARB = MARB

–

DAIDE·(

–

DAID

·2

DTSZ

·ETCRAH

MARA = MARA

–

SAIDE·(–1)

SAID

·2

DTSZ

·ETCRAH

Yes

Clear DTE bit to 0

to end transfer

Figure 7.15 Operation Flow in Block Transfer Mode

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Transfer requests (activation sources) consist of external requests, SCI transmission complete and

reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts.

Figure 7.16 shows an example of the setting procedure for block transfer mode.

Block transfer

mode setting

Set DMABCRH

Set transfer source

and transfer destination

addresses

Set number of transfers

Set DMACR

Read DMABCRL

Set DMABCRL

Block transfer mode

[1]

[2]

[3]

[4]

[5]

[6]

[1] Set each bit in DMABCRH.

• Set the FAE bit to 1 to select full address

mode.

• Specify enabling or disabling of internal

interrupt clearing with the DTA bit.

[2] Set the transfer source address in MARA, and

the transfer destination address in MARB.

[3] Set the block size in both ETCRAH and

ETCRAL. Set the number of transfers in

ETCRB.

[4] Set each bit in DMACRA and DMACRB.

• Set the transfer data size with the DTSZ bit.

• Specify whether MARA is to be incremented,

decremented, or fixed, with the SAID and

SAIDE bits.

• Set the BLKE bit to 1 to select block transfer

mode.

• Specify whether the transfer source or the

transfer destination is a block area with the

BLKDIR bit.

• Specify whether MARB is to be incremented,

decremented, or fixed, with the DAID and

DAIDE bits.

• Select the activation source with bits DTF3 to

DTF0.

[5] Read DTE = 0 and DTME = 0 in DMABCRL.

[6] Set each bit in DMABCRL.

• Specify enabling or disabling of transfer end

interrupts to the CPU with the DTIE bit.

• Set both the DTME bit and the DTE bit to 1 to

enable transfer.

Figure 7.16 Example of Block Transfer Mode Setting Procedure

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7.5.8 Basic Bus Cycles

An example of the basic DMAC bus cycle timing is shown in figure 7.17. In this example, word-

size transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When the

bus is transferred from the CPU to the DMAC, a source address read and destination address write

are performed. The bus is not released in response to another bus request, etc., between these read

and write operations. As like CPU cycles, DMA cycles conform to the bus controller settings.

The address is not output to the external address bus in an access to on-chip memory or an internal

I/O register.

Address bus

DMAC cycle (1-word transfer)

LWR

HWR

Source

address Destination address

CPU cycle CPU cycle

Figure 7.17 Example of DMA Transfer Bus Timing

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7.5.9 DMA Bus Cycles (Dual Address Mode)

Short Address Mo de: Figure 7.18 shows a transfer example in which TEND output is enabled

and byte-size sho rt address mode tr an sfer (sequential/idle/rep eat mode) is performed from external

8-bit, 2-state access space to internal I/O space.

DMA

read

Address bus

LWR

TEND

HWR

Bus release Last transfer

cycle

DMA

write DMA

dead

DMA

read DMA

write

DMA

read DMA

write

Bus release Bus release Bus

release

Figure 7.18 Example of Short Address Mode Transfer

A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is

released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.

In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead

cycle is inserted after the DMA write cycle.

In repeat mode, when TEND output is enabled, TEND output goes low in the transfer end cycle.

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Full Address Mode (Cycle Steal Mode): Figure 7.19 shows a transfer example in which TEND

output is enabled and word-size full address mode transfer (cycle steal mode) is performed from

external 16-bit, 2-state access space to external 16-bit, 2-state access space.

DMA

read

Address bus

LWR

TEND

HWR

Bus release Last transfer

cycle

DMA

write DMA

read DMA

write DMA

read DMA

write DMA

dead

Bus release Bus release Bus

release

Figure 7.19 Example of Full Address Mode Transfer (Cycle Steal)

A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is

released. While the bus is released, one bus cycle is executed by the CPU or DTC.

In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead

cycle is inserted after the DMA write cycle.

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Full Address Mode (Burst Mode): Figure 7.20 shows a transfer example in which TEND output

is enabled and word-size full address mode transfer (burst mode) is performed from external 16-

bit, 2-state access space to external 16-bit, 2-state access space.

DMA

read

Address bus

LWR

TEND

HWR

Bus release

DMA

write DMA

dead

DMA

read DMA

write DMA

read DMA

write

Bus release

Burst transfer Last transfer cycle

Figure 7.20 Example of Full Address Mode Transfer (Burst Mode)

In burst mode, one-by te or one-word transfers are executed consecutiv ely until transfer ends.

In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead

cycle is inserted after the DMA write cycle.

If a request from another higher-priority channel is generated after burst transfer starts, that

channel h a s to wait until the burst transfer ends.

If an NMI interru pt is generated while a channe l designated for burst transfer is in the transfer

enabled state, the DTME bit in DMABCRL is cleared and the channel is placed in the transfer

disabled state. If burst transfer has already been activated inside the DMAC, the bus is released on

completion of a one- byte or one-word transfer with in the burst transfer, and burst transfer is

suspended. If the last transfer cycle of the burst transfer has already been activated inside the

DMAC, execution continues to the end of the transfer even if the DTME bit is cleared.

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Full Address Mode (Block Transfer Mode): Figure 7.21 shows a transfer example in which

TEND output is enabled and word-size full address mode transfer (block transfer mode) is

performed from internal 16-bit, 1-state access space to external 16-bit, 2-state access space.

DMA

read

Address bus

LWR

TEND

HWR

Bus release Block transfer Last block transfer

DMA

write DMA

read DMA

write DMA

dead DMA

read DMA

write DMA

read DMA

write DMA

dead

Bus

release

Bus release

Figure 7.21 Example of Full Address Mode Transfer (Block Transfer Mode)

A one-block transfer is performed for a single transfer request, and after the transfer the bus is

released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.

In the transfer end cycle of each block (the cycle in which the transfer counter reaches 0), a one-

state DMA dead cycle is inserted after the DMA write cycle. Ev en if an NMI interrupt is generated

during data tr an sfer, block transfer operation is not affected until data transfer for one b lock has

ended.

DREQ

DREQDREQ

DREQ Pin Falling Edge Act ivation Timing : Set th e DTA bit in DMABCRH to 1 for the channel

for which the DREQ pin is selected.

Figure 7.22 shows an ex ample of normal mode transfer activated by the DREQ pin falling edge.

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DMA

read

Address

bus

DREQ

Idle Write Idle

Bus release

DMA

control

Channel

Write Idle

Transfer source

Request

[1] [3][2] [4] [6][5] [7]

Acceptance resumes

DMA

write Bus

release DMA

read DMA

write Bus

release

Request

Transfer destination

Transfer source

Transfer destination

Read Read

Request clear periodRequest clear period

Minimum

of 2 cycles Minimum

of 2 cycles

[1] Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,

and the request is held.

[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.

[3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts.

[4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the write cycle

is completed.

(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)

Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.

Figure 7.22 Example of DREQ

DREQ DREQ

DREQ Pin Falling Edge Activa ted Normal Mode Transf er

DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the

end of the DMABCR write cycle for setting the transfer enabled state as the starting point.

When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is

possible, the re quest is held in the DMAC. Then , when activation is initiated in the DMAC, the

request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin

high level sampling has been completed by the time the DMA write cycle ends, acceptance

resumes after the end of th e write cycle, DREQ pin low level sampling is performed again, and

this opera tion is repeated until the transfer ends.

Figure 7.23 shows an example of block transfer mode transfer activated by the DREQ pin falling

edge.

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DMA

read

Address

bus

DREQ

Idle Write

Bus release

DMA

control

Channel

Write

Transfer source

Request

[1] [3][2] [4] [6][5] [7]

Acceptance resumes

DMA

dead

1 block transfer

IdleDead Dead

DMA

write

Bus

release

DMA

read DMA

write DMA

dead Bus

release

Transfer source

Request

Acceptance resumes

1 block transfer

Transfer destinationTransfer destination

ReadIdleRead

Minimum

of 2 cycles Minimum

of 2 cycles

Request clear periodRequest clear period

[1] Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,

and the request is held.

[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.

[3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts.

[4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the dead cycle

is completed.

(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)

Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.

Figure 7.23 Example of DREQ

DREQDREQ

DREQ Pin Falling Edge Act ivated Block Tra nsfer Mode Transf er

DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the

end of the DMABCR write cycle for setting the transfer enabled state as the starting point.

When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is

possible, the re quest is held in the DMAC. Then , when activation is initiated in the DMAC, the

request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin

high level sampling has been completed by the time the DMA dead cycle ends, acceptance

resumes after the end of th e dead cycle, DREQ pin low level sampling is performed again, and this

operation is repeated until the transf er end s.

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DREQ

DREQDREQ

DREQ Pin Low Level Act i vation Timing (Normal Mo de): Set the DTA bit in DMABC RH to 1

for the chann e l for which the DREQ pin is selected.

Figure 7.24 shows an ex ample of normal mode transfer activated by the DREQ pin low level.

DMA

read DMA

write

Address

bus

DREQ

Idle Write Idle

Bus

release

DMA

control

Channel

Write Idle

Transfer source

Bus

release DMA

read DMA

write Bus

release

Request

[1] [3][2] [4] [6][5] [7]

Acceptance resumes

Transfer destination Transfer source Transfer destination

Request

Request clear periodRequest clear period

Read Read

Minimum

of 2 cycles Minimum

of 2 cycles

[1] Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,

and the request is held.

[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.

[3] [6] The DMA cycle is started.

[4] [7] Acceptance is resumed after the write cycle is completed.

(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)

Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.

Figure 7.24 Example of DREQ

DREQDREQ

DREQ Pin Low Level Activated Normal Mode Transfer

DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the

end of the DMABCR write cycle for setting the transfer enabled state as the starting point.

When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is

possible, the re quest is held in the DMAC. Then , when activation is initiated in the DMAC, the

request is cleared. After the end of the write cycle, acceptance resumes, DREQ pin low level

sampling is performed again, and this operation is re peated until the transfer en ds.

Figure 7.25 shows an example of block transfer mode transfer activated by DREQ pin low level.

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DMA

read DMA

write

Address

bus

DREQ

Idle Write

Bus release

DMA

control

Channel

Write

Transfer source

Request

[1] [3][2] [4] [6][5] [7]

Acceptance resumes

DMA

dead

Bus

release

DMA

read DMA

write DMA

dead Bus

release

1 block transfer

IdleDead Dead

1 block transfer

Acceptance resumes

Request

Minimum

of 2 cycles Minimum

of 2 cycles

Transfer source

Read

Request clear period

Read

Request clear period

Transfer destination

Idle

[1] Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,

and the request is held.

[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.

[3] [6] The DMA cycle is started.

[4] [7] Acceptance is resumed after the dead cycle is completed.

(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)

Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.

Figure 7.25 Example of DREQ

DREQDREQ

DREQ Pin Low Level Activated Block Transfer Mode Transfer

DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the

end of the DMABCR write cycle for setting the transfer enabled state as the starting point.

When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is

possible, the re quest is held in the DMAC. Then , when activation is initiated in the DMAC, the

request is cleared. After the end of the dead cycle, acceptance resumes, DREQ pin low level

sampling is performed again, and this operation is re peated until the transfer en ds.

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7.5.10 DMA Bus Cycles (Sing le Address Mode)

Single Address Mode (Read): Figure 7.26 shows a transfer example in which TEND output is

enabled and byte-size single address mode transfer (read) is performed from external 8-bit, 2-state

access space to an external device.

DMA read

Address bus

DMA

dead

DACK

TEND

Bus

release

DMA read DMA read DMA read

Bus

release Bus

release

Last transfer

cycle

Figure 7.26 Example of Single Address Mode Transfer (Byte Read)

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Figure 7.27 shows a transfer example in which TEND output is enabled and word-size single

address mode transfer (read) is performed from external 8-bit, 2-state access space to an external

device.

DMA read

Address bus

DMA read DMA read DMA

dead

TEND

DACK

Bus

release Bus

release

Last transfer

cycle

Figure 7.27 Example of Single Address Mode (Word Read) Transfer

A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is

released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.

In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead

cycle is inserted after the DMA write cycle.

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Single Address Mode (Write ) : Figure 7.28 shows a transfer example in which TEND output is

enabled and byte-size single address mode transfer (write) is performed from an external device to

external 8-bit, 2-state access space.

DMA write

Address bus

DMA

dead

HWR

DACK

TEND

Bus

release

LWR

DMA write DMA write DMA write

Bus

release Bus

release

Last transfer

cycle

Figure 7.28 Example of Single Address Mode Transf er (Byte Write)

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Figure 7.29 shows a transfer example in which TEND output is enabled and word-size single

address mode transfer (write) is performed from an external device to external 8-bit, 2-state access

space.

DMA write

Address bus

DMA write DMA write DMA

dead

HWR

TEND

DACK

Bus

release

LWR

Bus

release Bus

release

Last transfer

cycle

Figure 7.29 Example of Single Address Mode Transfer (Word Write)

A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is

released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.

In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead

cycle is inserted after the DMA write cycle.

DREQ

DREQDREQ

DREQ Pin Falling Edge Act ivation Timing : Set th e DTA bit in DMABCRH to 1 for the channel

for which the DREQ pin is selected.

Figure 7.30 shows an example of single address mode transfer activated by the DREQ pin falling

edge.

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DREQ

Bus release DMA single DMA single

Address bus

DMA control

Channel

[2]

DACK

Transfer source/

destination

Idle Idle Idle

[1] [3] [5][4] [6] [7]

Acceptance resumesAcceptance resumes

Bus release Bus release

Transfer source/

destination

Request Request Request clear

period

Request clear

period

Minimum of

2 cycles Minimum of

2 cycles

SingleSingle

[1] Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,

and the request is held.

[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.

[3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts.

[4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the single

cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of φ, and

the request is held.)

Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.

Figure 7.30 Example of DREQ

DREQDREQ

DREQ Pin Falling Edge Act ivated Single Address Mode Transfer

DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the

end of the DMABCR write cycle for setting the transfer enabled state as the starting point.

When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is

possible, the re quest is held in the DMAC. Then , when activation is initiated in the DMAC, the

request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin

high level sampling has been completed by the time the DMA single cycle ends, acceptance

resumes after the end of th e single cycle, DREQ pin low level sampling is performed again, and

this opera tion is repeated until the transfer ends.

DREQ

DREQDREQ

DREQ Pin Low Level Activation Timing: Set the DTA bit in DMABCRH to 1 for th e channel

for which the DREQ pin is selected.

Section 7 DMA Controller (DMAC)

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Figure 7.31 shows an example of single address mode transfer activated by the DREQ pin low

level.

DREQ

Bus release DMA single

Address bus

DMA control

Channel

[2]

DACK

Transfer source/

destination

Idle Idle Idle

[1] [3] [5][4] [6] [7]

Acceptance resumesAcceptance resumes

Bus release DMA single Bus

release

Transfer source/

destination

Request Request Request clear

period

Request clear

period

Single Single

Minimum of

2 cycles

Minimum of

2 cycles

[1] Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,

and the request is held.

[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.

[3] [6] The DMAC cycle is started.

[4] [7] Acceptance is resumed after the single cycle is completed.

(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)

Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.

Figure 7.31 Example of DREQ

DREQDREQ

DREQ Pin Low Level Act ivated Single Addres s Mode Transfer

DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the

end of the DMABCR write cycle for setting the transfer enabled state as the starting point.

When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is

possible, the re quest is held in the DMAC. Then , when activation is initiated in the DMAC, the

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request is cleared. After the end of the single cycle, acceptance resumes, DREQ pin low level

sampling is performed again, and this operation is re peated until the transfer en ds.

7.5.11 Write Data Buffer Function

DMAC internal-to-external dual address transfers and single address transfers can be executed at

high speed using the write data buffer function, enabling system throughput to be improved.

When the WDBE bit of BCR in the bus controller is set to 1, enabling the write data buffer

function, dual address transfer external write cycles or single address transfers and internal

accesses (on-chip memory or internal I/O registers) are executed in parallel. Internal accesses are

independent of the bu s master, and DMAC dead cycles are regarded as internal accesses.

A low level can always be output from the TEND pin if the bus cycle in which a low leve l is to be

output from the TEND pin is an external bus cycle. However, a low level is not output from the

TEND pin if the bus cycle in wh ich a low level is to be output from the TEND pin is an internal

bus cycle, and an external write cycle is executed in parallel with this cycle.

Figure 7.32 shows an example of burst mode transfer from on-chip RAM to external memory

using the write data buffer function.

Internal address

Internal read signal

HWR, LWR

TEND

External address

DMA

read DMA

write DMA

read DMA

write DMA

read DMA

write DMA

read DMA

write DMA

dead

Figure 7.32 Example of Dual Address Transfer Using Write Data Buffer Function

Figure 7.33 shows an example of single address transfer using the write data buffer function. In

this example, the CPU program area is in on-chip memory.

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Internal address

Internal read signal

DACK

External address

DMA

read DMA

single CPU

read DMA

single CPU

read

Figure 7.33 Example of Single Address Transfer Using Write Data Buffer Function

When the write data buffer function is activated, the DMAC recognizes that the bus cycle

concerned has ended, and starts the next operation. Therefore, DREQ pin sampling is started one

state after the start of the DMA write cycle or single address transfer.

7.5.12 Multi-Channel Operation

The DMAC channel priority order is: channel 0 > channel 1, and channel A > channel B. Table

7.11 summarizes the priority order for DMAC channels.

Table 7.11 DMAC C ha nnel P r iority Order

Short Address Mode Full Address Mode Priority

Channel 0A Channel 0 High

Channel 0B

Channel 1A Channel 1

Channel 1B Low

If transfer requests are issued simultaneously for more than one channel, or if a transfer request for

another channel is issued during a transfer, when the bus is released, the DMAC selects the

highest-priority channel from among those issuing a request according to the priority order shown

in table 7.11. During burst transfer, or when one block is being transferred in block transfer, the

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channel will not be changed until the end of the transf er. Figure 7.34 shows a transfer example in

which transfer requests are issued simultaneously for channels 0A, 0B, and 1.

DMA read DMA write DMA read DMA write DMA read DMA write DMA

read

Address bus

HWR

LWR

DMA control

Channel 0A

Channel 0B

Channel 1

Idle Write Idle Read Write Idle Write Read

Request

hold

Request

hold

Bus

release Channel 0A

transfer Bus

release Channel 0B

transfer Channel 1 transfer

Bus

release

Request

hold

Read

Selection

Non-

selection

Selection

Request clear

Read

Figure 7.34 Example of Multi-Channel Transfer

7.5.13 Relation between DMAC and External Bus Requests, Refresh Cycles,

and EXDMAC

When the DMAC accesses external space, contention with a refresh cycle, EXDMAC cycle, or

external bu s release cycle may arise. In this case, the bus contro ller will suspend the transfer and

insert a refresh cycle, EXDMAC cycle, or external bus release cycle, in accordance with the

external bus priority order, even if the DMAC is executing a burst transfer or block transfer. (An

external access by the DTC or CPU, which has a lower priority than the DMAC, is not executed

until the DMAC releases th e external bus.)

When the DMAC transfer mode is dual address mode, the DMAC releases the external bus after

an external write cycle. The external read cycle and external write cycle are inseparable, and so the

bus cannot be released between these two cycles.

When the DMAC accesses internal space (on-ch ip memory or an internal I/O register), the DMAC

cycle may be executed at the same time as a refresh cycle, EXDMAC cycle, or external bus

release cycle.

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7.5.14 DMAC and NMI Interrupts

When an NMI interrupt is requested, burst mode transfer in full address mode is interrupted. An

NMI interrupt does not affect the operation of the DMAC in other modes.

In full address mode, transfer is enabled for a channel when both the DTE bit and DTME bit are

set to 1. With burst mode setting, the DTME bit is cleared when an NMI interrupt is r e quested.

If the DTME bit is cleared during burst mode tr ansfer , the DMAC discontinues transfer on

completion of the 1-byte or 1-word transfer in progress, then releases the bus, which passes to the

CPU.

The channel on which transfer was interrupted can be restarted by setting the DTME bit to 1 again.

Figure 7.35 shows the procedur e for continuing transfer when it has been interrupted by an NMI

interrupt on a channel designated for burst mode transfer.

Resumption of

transfer on interrupted

channel

Set DTME bit to 1

Transfer continues

[1]

[2]

DTE = 1

DTME = 0

Transfer ends

Yes

[1]

[2]

Check that DTE = 1 and

DTME = 0 in DMABCRL.

Write 1 to the DTME bit.

Figure 7.35 Example of Procedure for Continuing Transfer on Channel Interrupted

by NMI Interrupt

7.5.15 Forced Termination of DMAC Operation

If the DTE bit in DMABCRL is cleared to 0 for the channel currently operating, the DMAC stops

on completion of the 1-byte or 1-word transfer in progress. DMAC operation resumes when the

DTE bit is set to 1 again. In full address mo de, the same applies to the DTME bit in DMABCRL.

Figure 7.36 shows the procedure for forcibly terminating DMAC operation by so ftware.

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Forced termination

of DMAC

Clear DTE bit to 0

Forced termination

[1]

[1] Clear the DTE bit in DMABCRL to 0.

To prevent interrupt generation after forced

termination of DMAC operation, clear the DTIE bit

to 0 at the same time.

Figure 7.36 Example of Procedure for Forcibly Terminating DMAC Operation

7.5.16 Clearing Full Address Mode

Figure 7. 37 shows the procedure for r e leasing and initializing a channel designated for full ad dress

mode. After full address mode has been cleared, the channel can be set to another transfer mode

using the appropriate setting procedure.

Clearing full

address mode

Stop the channel

Initialize DMACR

Clear FAE bit to 0

Initialization;

operation halted

[1]

[2]

[3]

[1] Clear both the DTE bit and DTME bit in

DMABCRL to 0, or wait until the transfer ends

and the DTE bit is cleared to 0, then clear the

DTME bit to 0. Also clear the corresponding

DTIE bit to 0 at the same time.

[2] Clear all bits in DMACRA and DMACRB to 0.

[3] Clear the FAE bit in DMABCRH to 0.

Figure 7.37 Example of Procedure for Clearing Full Address Mode

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7.6 Interrupt Sources

The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 7.12

shows the interrupt sources and their priority order.

Table 7.12 Interrupt Sources and P riority Order

Interrupt Source

Interrupt Name Short Address Mode Full Address Mode Interrupt

Priority Order

DMTEND0A Interrupt due to end of

transfer on channel 0A Interrupt due to end of

transfer on channel 0 High

DMTEND0B Interrupt due to end of

transfer on channel 0B Interrupt due to break in

transfer on channel 0

DMTEND1A Interrupt due to end of

transfer on channel 1A Interrupt due to end of

transfer on channel 1

DMTEND1B Interrupt due to end of

transfer on channel 1B Interrupt due to break in

transfer on channel 1 Low

Enabling or disabling of each interrupt source is set by means of the DTIE bit in DMABCRL for

the corresponding channel in DMABCRL, and interrupts from each source are sent to the interrupt

controller independently. The priority of transfer end interrupts on each channel is decided by the

interrupt controller, as shown in table 7.12.

Figure 7.38 shows a block diagram of a transfer end/transfer break interrupt. An interrupt is

always generated when the D TIE bit is set to 1 w hile the DTE bit in DMA BCRL is cleared to 0.

DTE/

DTME

DTIE

Transfer end/transfer

break interrupt

Figure 7.38 Block Diagram of Transfer End/Transfer Break Interrupt

In full address mode, a transfer break interrupt is generated when the DTME bit is cleared to 0

while the DTIEB b it is set to 1. In both short address mod e and full address mode, DMABCR

should be set so as to prevent the occurrence of a combination that constitutes a condition for

interrupt generation during setting.

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7.7 Usage Notes

7.7.1 DMAC Register Access during Operation

Except for forced term ination of the DMAC, the operating ( in cludin g tran sf er waiting state)

channel setting should not be changed. The operating channel setting should only be changed

when transfer is disabled. Also, DMAC registers should not be written to in a DMA transfer.

DMAC register reads during operation (including the transfer waiting state) are described below.

• DMAC control starts one cycle befo re the bus cycle, with output of the internal address.

Consequently, MAR is updated in the bus cycle before DMA transfer. Figu re 7.39 shows an

example of the update timing for DMAC registers in dual address transfer mode.

[1] Transfer source address register MAR operation (incremented/decremented/fixed)

Transfer counter ETCR operation (decremented)

Block size counter ETCR operation (decremented in block transfer mode)

[2] Transfer destination address register MAR operation (incremented/decremented/fixed)

[2'] Transfer destination address register MAR operation (incremented/decremented/fixed)

Block transfer counter ETCR operation (decremented, in last transfer cycle of

a block in block transfer mode)

[3] Transfer address register MAR restore operation (in block or repeat transfer mode)

Transfer counter ETCR restore (in repeat transfer mode)

Block size counter ETCR restore (in block transfer mode)

Note: In single address transfer mode, the update timing is the same as [1].

The MAR operation is post-incrementing/decrementing of the DMA internal address value.

[3]

[2'][2] [1]

[1]

DMA transfer cycle

DMA read DMA read

DMA write DMA write DMA

dead

DMA Internal

address

DMA control

DMA register

operation

DMA last transfer cycle

Transfer

source

Transfer

source

Idle Idle IdleRead Read Dead

Write Write

Transfer

destination Transfer

destination

Figure 7.39 DMAC Register Update Timing

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• If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC

[2]

[1]

Note: The lower word of MAR is the updated value after the operation in [1].

CPU longword read DMA transfer cycle

MAR upper

word read MAR lower

word read DMA read DMA write

DMA internal

address

DMA control

DMA register

operation

Transfer

source

Idle

Read Write Idle

Transfer

destination

Figure 7.40 Contention between DMAC Register Upda te a nd CPU Read

7.7.2 Module Stop

When the MSTP13 bit in MSTPCRH is set to 1, the DMAC clock stops, and the module stop state

is entered. Howev e r , 1 cannot b e written to th e MSTP13 bit if any of the DMAC channels is

enabled. This setting should therefore be made when DMAC operation is stopped.

When the DMAC clock stops, DMAC register accesses can no longer be made. Since the

following DMAC register settings are valid even in the module stop state, they should be

invalidated, if necessary, before a module stop.

• Transfer end/break in terrupt (DTE = 0 and DTIE = 1)

• TEND pin enable (TEE = 1)

• DACK pin enable (FAE = 0 and SAE = 1)

7.7.3 Write Data Buffer Function

When the WDBE bit of BCR in the bus controller is set to 1, enabling the write data buffer

function, dual address transfer external write cycles or single address transfers and internal

accesses (on-chip memory or internal I/O registers) are executed in parallel.

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• Write data buf fer function and DMAC register setting

If the setting of a register that controls extern al accesses is changed during execution of an

external access by means of the write data buffer function, the external access may not be

performed normally. Registers that control external accesses should only be manipulated when

external reads, etc., are used with DMAC operation disabled, and the operation is not

performed in parallel with external access.

• Write data buffer function and DMAC operation timing

The DMAC can start its next operation during external access using the write data buffer

function. Consequently, the DREQ pin sampling timing, TEND output timing, etc., are

different from the case in which the write data buffer function is disabled. Also, internal bus

cycles maybe hidden, and not visible.

7.7.4 TEND

TENDTEND

TEND Output

If the last transfer cycle is for an internal address, note that even if low-level output at the TEND

pin has been set, a low level may not be output at the TEND pin under the following external bus

conditions since the last transfer cycle (internal bus cycle) and the external bus cycle are executed

in parallel.

1. EXDMAC cycle

2. Write cycle with wr ite buffer mode enabled

3. DMAC single address cycle for a different channel with write buffer mode enabled

4. Bus release cycle

5. CBR refresh cycle

Figure 7.41 shows an example in which a low level is not output from the TEND pin in case 2

above.

If the last transfer cycle is an external address cycle, a low level is output at the TEND pin in

synchronization with the bus cycle.

However, if the last transfer cycle and a CBR refresh occur simultaneously, note that although the

CBR refresh and the last transfer cycle may be executed consecutively, TEND may also go low in

this case for the refresh cycle.

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Internal address

Internal read signal

External address

HWR, LWR

Internal write signal

TEND

Not output

DMA

read

External write by CPU, etc.

DMA

write

Figure 7.41 Example in Which Low Level Is Not Output at TEND

TENDTEND

TEND Pin

7.7.5 Activat ion by Falling Edg e on DREQ

DREQDREQ

DREQ Pin

DREQ pin falling edge detection is performed in synchronization with DMAC internal operations.

The opera tion is as f ollows:

[1] Activation re quest wait state: Waits for detection of a low level on the DREQ pin, and

switches to [2 ].

[2] Transfer wait state: Waits for DMAC d a ta tr ansfer to become possible, and switches to [ 3].

[3] Activation request disabled state: Waits for detection of a high level on the DREQ pin, and

switches to [1 ].

After DMAC transfer is enabled, a transition is made to [1]. Thus, initial activatio n after transfer is

enabled is performed on detection of a low level.

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7.7.6 Activation Source Acceptance

At the start of activation source acceptance, a low level is detected in both DREQ pin falling edge

sensing and lo w level sensing. Similarly, in the case of an internal inter rup t, th e interrupt request is

detected. Therefore, a requ est is accepted from an internal interrupt or DREQ pin low level that

occurs before write to DMABCRL to enable transfer.

When the DMAC is activated, take any necessary steps to prevent an internal interrupt or DREQ

pin low level remaining from the end of the previous transfer, etc.

7.7.7 Internal Interrupt after End of Transfer

When the DTE bit in DMABCRL is cleared to 0 at the end of a transfer or by a forcible

termination , the selected internal interrupt re quest will b e sent to the CPU or DTC ev en if the

DTA bit in DMABCRH is set to 1.

Also, if intern al DMAC activation has already been initiated when operation is forcibly

terminated, the transfer is executed but flag clearing is not performed for the selected internal

interrupt even if the DTA bit is set to 1.

An internal interrupt request following the end of transfer or a forcible termination should be

handled by the CPU as necessary.

7.7.8 Channel Re-Sett ing

To reactivate a number of channels when multiple channels are enabled, u se exclu siv e hand ling o f

transf e r end interrupts, a nd perfor m DMABCR co ntrol b it opera tions exclusively.

Note, in particu lar , that in cases where multiple interru pts are generated between reading and

writing of DMABCR, and a DMABCR operation is performed during new interrupt handling, the

DMABCR write data in the original in ter rup t handling routine will b e incor r ect, and the write ma y

invalidate th e r e sults of the operations by the multiple interrup ts. Ensure that overlapping

DMABCR opera tions are not perfo rmed by multiple interrupts, and that there is no separation

between read and write oper ations by the use of a bit-manipulation instruction.

Also, when the DTE and DTME bits ar e clear ed by the DMAC or ar e wr itten with 0, they must

first be read while cleared to 0 before the CPU can write 1 to them.

Section 8 EXDMA Controller

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Section 8 EXDMA Controller

This LSI has a bu ilt- in four-channel external bus transf er DMA contr oller (EXDMAC). The

EXDMAC can carry out high-speed data transfer, in place of the CPU, to and from external

devices and ex ternal m emory with a DACK (DMA transf er notification) facility.

8.1 Features

• Direct specification of 16-Mbyte address space

• Selection of byte or word transfer data length

• Maximum number of transfers: 16M (16,777,215)/infinite (free-running)

• Selection of dual address mode or single address mode

• Selection of cycle steal mode or burst mode as bus mode

• Selection of normal mode or block transfer mode as transfer mode

• Two kinds of transfer requests: external request and auto-request

• An interrupt request can be sent to the CPU at the end of the specified number of transfers.

• Repeat area designation function:

• Operation in para llel with internal bus master:

• Acceptance of a transfer request and the start of transfer processing can be reported to an

external device via the EDRAK pin.

• Module stop mode can be set.

Figure 8.1 shows a block diagram of the EXDMAC.

EDMA260A_010020020400

Section 8 EXDMA Controller

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Bus controller

Internal data bus

Interrupt request

signals to CPU

for individual

channels

External pins

EDMDR

EDACR EDTCR

EDDAR

EDSAR

Processor

Address buffer

Data buffer

Control logic

Module data bus

EDREQ

EDRAK

ETEND

EDACK

Legend:

EDSAR: EXDMA source address register

EDDAR: EXDMA destination address register

EDTCR: EXDMA transfer count register

EDMDR: EXDMA mode control register

EDACR: EXDMA address control register

Figure 8.1 Block Diagram of EXDMAC

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8.2 Input/Output Pins

Table 8.1 shows the EXDMAC pin configuration.

Table 8.1 Pin Configuration

Channel Name Abbre-

viation I/O Function

0 EXDMA transfer request 0 EDREQ0 Input Channel 0 external request

EXDMA transfer

acknowle dge 0 EDACK0 Output Channel 0 single address transfer

acknowledge

EXDMA transfer end 0 ETEND0 Output Channel 0 transfer en d

EDREQ0 acceptance

acknowledge EDRAK0 Output Notification to ex ternal device of

channel 0 external request

acceptance and start of execution

1 EXDMA transfer request 1 EDREQ1 Input Channel 1 external request

EXDMA transfer

acknowle dge 1 EDACK1 Output Channel 1 single address transfer

acknowledge

EXDMA transfer end 1 ETEND1 Output Channel 1 transfer en d

EDREQ1 acceptance

acknowledge EDRAK1 Output Notification to ex ternal device of

channel 1 external request

acceptance and start of execution

2 EXDMA transfer request 2 EDREQ2 Input Channel 2 external request

EXDMA transfer

acknowle dge 2 EDACK2 Output Channel 2 single address transfer

acknowledge

EXDMA transfer end 2 ETEND2 Output Channel 2 transfer en d

EDREQ2 acceptance

acknowledge EDRAK2 Output Notification to ex ternal device of

channel 2 external request

acceptance and start of execution

3 EXDMA transfer request 3 EDREQ3 Input Channel 3 external request

EXDMA transfer

acknowle dge 3 EDACK3 Output Channel 3 single address transfer

acknowledge

EXDMA transfer end 3 ETEND3 Output Channel 3 transfer en d

EDREQ3 acceptance

acknowledge EDRAK3 Output Notification to ex ternal device of

channel 3 external request

acceptance and start of execution

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8.3 Register Descriptions

The EXDMAC has the followin g registers.

• EXDMA source address register_0 (EDSAR_0)

• EXDMA destination ad dress register_0 (EDDAR_0 )

• EXDMA transfer count register_0 (EDTCR_0)

• EXDMA mode control register_0 (EDMDR_0)

• EXDMA address control register_0 (EDACR_0)

• EXDMA source address register_1 (EDSAR_1)

• EXDMA destination ad dress register_1 (EDDAR_1 )

• EXDMA transfer count register_1 (EDTCR_1)

• EXDMA mode control register_1 (EDMDR_1)

• EXDMA address control register_1 (EDACR_1)

• EXDMA source address register_2 (EDSAR_2)

• EXDMA destination ad dress register_2 (EDDAR_2 )

• EXDMA transfer count register_2 (EDTCR_2)

• EXDMA mode control register_2 (EDMDR_2)

• EXDMA address control register_2 (EDACR_2)

• EXDMA source address register_3 (EDSAR_3)

• EXDMA destination ad dress register_3 (EDDAR_3 )

• EXDMA transfer count register_3 (EDTCR_3)

• EXDMA mode control register_3 (EDMDR_3)

• EXDMA address control register_3 (EDACR_3)

8.3.1 EXDMA Source Address Register (EDSAR)

EDSAR is a 32-bit readable/writable register that specifies the transfer source address. An address

update function is provided that updates the register contents to the next transfer source address

each time transfer processing is performed. In single address mode, the EDSAR value is ignored

when a device with DACK is specified as the transfer source. The upper 8 bits of EDSAR are

reserved; they are always read as 0 and cannot be modified.

EDSAR can be read at all times by the CPU. When reading EDSAR for a channel on which

EXDMA transfer processing is in progress, a longword-size read must be executed. Do not write

to EDSAR for a channel on which EXDMA transfer is in pro gress. The initial values of EDSAR

are undefined.

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8.3.2 EXDMA Destination Address Register (EDDAR)

EDDAR is a 32-bit readable/writable register that specifies the transfer destin ation address. An

address update function is provided that updates the register contents to the next transfer

destination address each time tran sfer processing is performed. In single address mode, the

EDDAR value is ignored when a device with DACK is specified as the transfer destination. The

upper 8 bits of EDDAR are reserved; they are always read as 0 and cannot be modified.

EDDAR can be read at all times by the CPU. When reading EDDAR for a channel on which

EXDMA transfer processing is in progress, a longword-size read must be executed. Do not write

to EDDAR for a channel on wh ich EXDMA transfer is in progress. The initial values of EDDAR

are undefined.

8.3.3 EXDMA Transfer Count Register (EDTCR)

EDTCR specifies the number of tran sfers. The function differs according to the transfer mode. Do

not write to EDTCR for a channel on which EXDMA transfer is in progress.

Normal Transfer Mode:

Bit Bit Name Initial Value R/W Description

— All 0 — Reserved

These bits are always read as 0 and cannot be

modified.

All 0 R/W 24-Bit Transfer Counter

These bits specify the number of transfers.

Setting H'000001 specifies one transfer. Setting

H'000000 means no specification for the

number of transfers, and the transfer counter

function is halted. In t his case, there is no

transfer end interrupt by the transfer counter.

Setting H'FFFFFF specifies the maximum

number of transfers, that is 16,777,215. Duri ng

EXDMA transfer, this counter shows the

remaining number of transfers. This counter

can be read at all times. When reading EDTCR

for a channel on which EXDMA transfer

processing is in progres s, a longword-s iz e read

must be exec uted.

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Block Tra nsfer Mode:

Bit Bit Name Initial Value R/W Description

— All 0 — Reserved

These bits are always read as 0 and cannot be

modified.

Undefined R/W Block Size

These bits specify the block size (number of

bytes or number of words) for block transfer.

Setting H'01 specifies one as the block, while

setting H'00 specifies the maximum block size,

that is 256. The register value al ways indicates

the specified block size.

Undefined R/W 16-Bit Transfer Counter

These bits specify the number of block

transfers. Setting H'0001 specifies one block

transfer. Setting H'0000 means no specification

for the number of transfers, and the transfer

counter function is halted. In this case, there is

no transfer end interrupt by the transfer counter.

Setting H'FFFF specifies the maximum number

of block transfers, that is 65,535. Duri ng

EXDMA transfer, this counter shows the

remaining number of block transfers.

Section 8 EXDMA Controller

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8.3.4 EXDMA Mode Control Register (EDMDR)

EDMDR controls EXDMAC operations.

Bit Bit Name Initial Value R/W Description

15 EDA 0 R/(W) EXDMA Active

Enables or disables data transfer on the

corresponding channel. When this bit is set to

1, this indicates that an EXDMA operation is in

progress.

When auto request mode is specified (by bits

MDS1 and MDS0), transfer processing begins

when this bit is set to 1. With external requests,

transfer processing begins when a transfer

request is issued after this bit has been set to 1.

When this bit is cleared to 0 during an EXDMA

operation, transfer is hal ted. If this bit is cle ared

to 0 during an EXDMA operation in block

transfer mode, transfer processing is continued

for the currently executing one-block transfer,

and the bit is cleared on completion of the

currently executing one-block transfer.

If an external source that ends (aborts) transfer

occurs, this bit is automatically cleared to 0 and

transfer is terminated. Do no t change the

operating mode, transfer method, or other

parameters while this bit is set to 1.

0: Data transfer disabled on corresponding

channel

[Clearing cond iti ons ]

• When the specified number of transfers end

• When operation is halted by a repeat area

overflow interrupt

• When 0 is written to EDA while EDA = 1

(In block transfer mode, write is effective

after end of one-block transfer)

• Reset, NMI interrupt, hardware standby

mode

1: Data transfer enabled on corresponding

channel

Note: The value written in the EDA bit may not

be effective immediately.

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Bit Bit Name Initial Value R/W Description

14 BEF 0 R/(W)*Block Transfer Error Flag

Flag that indicates the occurrence of an error

during block transfer. If an NMI interrupt is

generated during block transfer, the EXDMAC

immediately terminates the EXDMA operation

and sets this bit to 1. The address registers

indicate the next transfer addresses, but the

data for which transfer has been performed

within the block si ze is los t.

0: No block transfer error

[Clearing cond iti on]

Writing 0 to BEF after reading BEF = 1

1: Block transfer error

[Setting condition]

NMI interrupt during block transfer

13 EDRAKE 0 R/W EDRAK Pin Output Enable

Enables output from the EDREQ

acknowledge/execution start (EDRAK) pin.

0: EDRAK pin output disabled

1: EDRAK pin output enabled

12 ETENDE 0 R/W ETEND Pin Output Enable

Enables output from the EXDMA transfer end

(ETEND) pin.

0: ETEND pin output disabled

1: ETEND pin output enabled

11 EDREQS 0 R/W EDREQ Select

Specifies low level sensing or falling edge

sensing as the sampling method for the

EDREQ pin used in external request mode.

0: Low level sensin g (Low level sen si ng is used

for the first tran sfer after transfer is enabled.)

1: Falling edge sensing

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Bit Bit Name Initial Value R/W Description

10 AMS 0 R/W Address Mode Select

Selects single address mode or dual address

mode. When single address mode is selected,

the EDACK pin is valid.

0: Dual address mode

1: Single address mode

8MDS1

MDS0 0

0R/W

R/W Mode Select 1 and 0

These bits specify the activation source, bus

mode, and tran sfer mode.

00: Auto request, cycle steal mode, normal

transfer mode

01: Auto request, burst mode, normal tran sfer

mode

10: External request, cycle steal mode, normal

transfer mode

11: External request, cycle steal mode, block

transfer mode

7 EDIE 0 R/W EXDMA Interrupt Enable

Enables or disables interrupt requests. When

this bit is set to 1, an interrupt is request ed

when the IRF bit is set to 1. The interrupt

request is cleared by clearing this bi t or the IRF

bit to 0.

0: Interrupt request is not generated

1: Interrupt request is generated

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Bit Bit Name Initial Value R/W Description

6IRF 0 R/(W)

*Interrupt Request Flag

Flag indicating that an interrupt request has

occurred and transfer has ended.

0: No interrupt request

[Clearing cond iti ons ]

• Writing 1 to the EDA bit

• Writing 0 to IRF after reading IRF = 1

1: Interrupt request occurrence

[Setting conditions]

• Transfer end interrupt request generated by

transfer counter

• Source address repeat area overflow

interrupt request

• Destination address repeat area overflow

interrupt request

5 TCEIE 0 R/W Transfer Counter End Interrupt Enable

Enables or disables transfer end interrupt

requests by the transfer counter. When transfer

ends according to the transfer counter while this

bit is set to 1, the IRF bit is set to 1, indicating

that an interrupt request has occurred.

0: Transfer end interrupt requests by transfer

counter are disabled

1: Transfer end interrupt requests by transfer

counter are enabled

4 SDIR 0 R/W Single Address Direction

Specifies the data transfer direction in single

address mode. In dual address mode, the

specification by this bit is ignored.

0: Transfer direction: EDSAR → external devi ce

with DACK

1: Transfer direction: Ex ternal device with

DACK → EDDAR

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Bit Bit Name Initial Value R/W Description

3 DTSIZE 0 R/W Data Transmit Size

Specifies the size of data to be transferred.

0: Byte-size

1: Word-size

2 BGUP 0 R/W Bus Give-Up

When this bit is set to 1, the bus can be

transferred to an internal bus mastership in

burst mode or block transfer mode. This setting

is ignored in normal mode and cycle steal

mode.

0: Bus is not released

1: Bus is transferred if requested by an internal

bus master

1, 0 — All 0 R/W Reserved

These bits can be read from or written to.

However, the write value should always be 0.

Note: *Only 0 can be written, to clear the flag.

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8.3.5 EXDMA Address Contro l Reg ister (EDACR)

EDACR specifies address register incrementing/decrementing and use of the repeat area function.

Bit Bit Name Initial Value R/W Description

14 SAT1

SAT0 0

0R/W

R/W Source Address Update Mode

These bits specify incrementing/decrementing

of the transfer source addr es s (EDSAR). When

an external device with DACK is designated as

the transfer source in single address mode, the

sp ecification by these bits is ignored.

0X: Fixed

10: Incremented (+1 in byte transfer, +2 in word

transfer)

11: Decremented (–1 in byte transfer, –2 in

word transfer)

13 SARIE 0 R/W Source Address Repeat Interrupt Enable

When this bit is set to 1, in the event of source

address repeat area overflow, the IRF bit is set

to 1 and the EDA bit cleared to 0 in EDMDR,

and transfer is terminated. If the EDIE bit in

EDMDR is 1 when the IRF bit in EDMDR is set

to 1, an interrupt request is sent to the CPU.

When used together with block transfer mode, a

source address repeat interrupt is requested at

the end of a block-size transfer. If the EDA bit is

set to 1 in EDMDR for the channel on which

transfer is terminated by a source address

repeat interrupt, transfer can be resumed from

the state in which it ended. If a source address

repeat area has not been designated, this bit is

ignored.

0: Source address repeat interrupt is not

requested

1: When source address repeat area overflow

occurs, the IRF bit in EDMDR is set to 1 and

an interrupt is requested

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Bit Bit Name Initial Value R/W Description

SARA4

SARA3

SARA2

SARA1

SARA0

R/W

Source Address Repeat Area

These bits specify the source address (EDSAR)

repeat area. The repeat area function updates

the specified lower address bits, leaving the

remaining upper address bits always the same.

A repeat area size of 2 bytes to 8 Mbytes can

be specified. The setting interval is a power-of-

two number of bytes. When repeat area

overflow results from incrementing or

decrementing an address, the lower address is

the start addres s of the repeat area in the case

of address incrementing, or the last address of

the repeat area in the case of address

decrementin g. If the SARIE bit is set to 1, an

interrupt can be requested when repeat area

overflow occurs.

00000: Not designated as repeat area

00001: Lower 1 bit (2-byte area) designated as

repeat area

00010: Lower 2 bits (4-byte area) designated

as repeat area

00011: Lower 3 bits (8-byte area) designated

as repeat area

00100: Lower 4 bits (16-byte area) designated

as repeat area

: :

10011: Lower 19 bits (512-kbyte area)

designated as repeat area

10100: Lower 20 bits (1-Mbyte area)

designated as repeat area

10101: Lower 21 bits (2-Mbyte area)

designated as repeat area

10110: Lower 22 bits (4-Mbyte area)

designated as repeat area

10111: Lower 23 bits (8-Mbyte area)

designated as repeat area

11XXX: Setting prohibited

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Bit Bit Name Initial Value R/W Description

6DAT1

DAT0 0

0R/W

R/W Destination Address Update Mode

These bits specify incrementing/decrementing

of the transfer destination address (EDDAR).

When an external device with DACK is

designated as the transfer destination in single

address mode, the specification by these bits is

ignored.

0X: Fixed

10: Incremented (+1 in byte transfer, +2 in word

transfer)

11: Decremented (–1 in byte transfer, –2 in

word transfer)

5 DARIE 0 R/W Destination Address Repeat Interrupt Enable

When this bit is set to 1, in the event of

destinat ion addr es s repeat area overflow the

IRF bit is set to 1 and the EDA bit cleared to 0

in EDMDR, and transfer is terminated. If the

EDIE bit in EDMDR is 1 when the IRF bit in

EDMDR is set to 1, an interrupt request is sent

to the CPU. When used together with block

transfer mode, a destination address repeat

interrupt is requested at the end of a block-size

transfer. If the EDA bit is set to 1 in EDMDR for

the channel on which transfer is terminated by a

destinat ion addr es s repeat interr upt, tran sfer

can be resumed from the state in which it

ended. If a destination address repeat area has

not been designated, this bit is ignored.

0: Destination address repeat interrupt is not

requested

1: When destination address repeat area

overflow occurs, the IRF bit in EDMDR is set

to 1 and an interrupt is requested

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Bit Bit Name Initial Value R/W Description

DARA4

DARA3

DARA2

DARA1

DARA0

R/W

Destination Address Repeat Area

These bits specify the destination address

(EDDAR) repeat area. The repeat area function

updates the spe cif ied lower address bits,

leaving the remaining upper address bits

always the same. A repeat area size of 2 bytes

to 8 Mbytes can be specified. The setting

interval is a power-of-two number of byte s.

When repeat area overflow results from

incrementing or decrementing an address, the

lower address is the start addre s s of the repeat

area in the case of address incrementing, or the

last address of the repeat area in the case of

address decrementing. If the DARIE bit is set to

1, an interrupt can be requested when repeat

area overflow occurs.

00000: Not designated as repeat area

00001: Lower 1 bit (2-byte area) designated as

repeat area

00010: Lower 2 bits (4-byte area) designated

as repeat area

00011: Lower 3 bits (8-byte area) designated

as repeat area

00100: Lower 4 bits (16-byte area) designated

as repeat area

: :

10011: Lower 19 bits (512-kbyte area)

designated as repeat area

10100: Lower 20 bits (1-Mbyte area)

designated as repeat area

10101: Lower 21 bits (2-Mbyte area)

designated as repeat area

10110: Lower 22 bits (4-Mbyte area)

designated as repeat area

10111: Lower 23 bits (8-Mbyte area)

designated as repeat area

11XXX: Setting prohibited

Legend:

x: Don't care

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8.4 Operation

8.4.1 Transfer Modes

The transfer modes of the EXDMAC are summarized in table 8.2.

Table 8.2 EXDMAC Transfer Modes

Address Registers

Transfer Mode Transfer

Origin Number of

Transfers Source Destination

Auto request mode

• Burst/ cy cle stea l

mode

Auto

request

Normal

transfer

mode

External request

mode

• Cycle steal mode

External

request

1 to

16,777,215

or no

specification

Dual

address

mode

Block

transfer

mode

External request

mode

• Burst transfer of

sp ecified block

size for a single

transfer request

• Block size: 1 to

256 bytes or

words

External

request 1 to 65,535

or no

specification

EDSAR EDDAR

Single

address

mode

• Direct data transfer to/from exter nal de vic e usin g

EDACK pin instead of source or destination address

• Above transfer mode can be specified in addition to

address register setting

• One transfer possible in one bus cycle

(Transfer mode variations are the same as in dual address

mode.)

EDSAR/

EDACK

EDACK/

EDDAR

The transfer mode can be set independently for each channel.

In normal transfer mode, a one-byte or one-word transfer is executed in response to one transfer

request. With auto requests, burst or cy cle steal transfer mode can be set. In burst transfer mode,

continuous, hig h-speed transfer can be performed until the specified number of transfers have been

executed or the transfer enable bit is cleared to 0.

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In block transfer mode, a transfer of the specified block size is executed in response to one transfer

request. The block size can be from 1 to 256 bytes or words. Within a block, transfer can be

performed at the same high speed as in block transfer mode.

When the “no specification” setting (EDTCR = H'000000) is made for the number of transfers, the

transfer counter is halted and there is no limit on the number of transfers, allowing transfer to be

performed endlessly.

Incrementing or decrementing the memory address by 1 or 2, or leaving the address unchanged,

can be specified independently for each address register.

In all transfer modes, it is possible to set a repeat area comprising a power-of-two number of

bytes.

8.4.2 Address Modes

Dual Address Mode: In dual address mode, both the transfer source and transfer destination are

specified by registers in the EXDMAC, and one transfer is executed in two bus cycles.

The transfer source address is set in the source address register (EDSAR), and the transfer

destination address is set in the tran sfer destination address register (EDDAR).

In a transfer operation, the value in external memory specified by the transfer source address is

read in the first bus cycle, and is wr itten to the external memory specified by the transfer

destination address in the next bus cycle.

These consecutive read and write cy cles are indivisible: another bus cycle (external access by an

internal bus master, refresh cycle, or external bus release cycle) does not occur between these two

cycles.

ETEND pin output can be enabled or disabled by means of the ETENDE bit in EDMDR. ETEND

is output for two consecutive bus cycles. The EDACK signal is not output.

Figure 8.2 shows an example of the timing in dual address mode.

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Address bus

ETEND

EXDMA

read cycle EXDMA

write cycle

EDSAR EDDAR

Figure 8.2 Example of Timing in Dual Address Mode

Single Address Mode: In single address mode, the EDACK signal is used instead of the source or

destination address register to transfer data directly between an external device and external

memory. In this mode, the EXDMAC accesses the transfer source or transfer destination external

device by outpu tting the external I/O strobe signal (EDACK), and at the same time accesses the

other external device in the transfer by outputting an address. In this way, DMA transfer can be

executed in one bus cycle. In the example of transfer between external memory and an external

device with DACK shown in figure 8.3, data is output to the data bus by the external device and

written to external memory in the same bus cycle.

The transfer direction, that is whether the external device with DACK is the transfer source or

transfer destination, can be specif ied with th e SDI R b it in EDMDR. Transfer is perfor m e d from

the external memory (EDSAR) to the external device with DACK when SDIR = 0, and from the

external device with DACK to the external memory (EDDAR) when SDIR = 1.

The setting in the source or destination address register not used in the transfer is ignored.

The EDACK pin becomes valid automatically when single address mode is selected. The EDACK

pin is active-low. ETEND pin output can be enabled or disabled by means of the ETENDE bit in

EDMDR. ETEND is output for one bus cycle.

Figure 8.3 shows the data flow in single address mode, and figure 8.4 shows an example of the

timing.

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Microcomputer

Data flow

External

address bus External

data bus

EXDMAC

EDACK

EDREQ

External

memory

External device

with DACK

Figure 8.3 Data Flow in Single Address Mode

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EXDMA cycle

EDSAR Address to external memory space

RD signal to external memory space

Data output from external memory

Address bus

EDACK

ETEND

Data bus

EXDMA cycle

EDDAR Address to external memory space

WR signal to external memory space

Address bus

Transfer from external memory to external device with DACK

Transfer from external device with DACK to external memory

EDACK

ETEND

Data bus Data output from external device

with DACK

Figure 8.4 Example of Timing in Single Address Mode

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8.4.3 DMA Transfer Requests

Auto Request Mode: I n auto request mode, transfer request sig nals are automatically generated

within the EXDMAC in cases where a transfer request signal is not issued from outside, such as in

transfer between two memories, or between a peripheral module that is not capable of generating

transfer requests and memory. In auto req uest mode, transfer is started wh en the EDA bit is set to

1 in EDMDR.

In auto request mode, either cycle steal mode or burst mode can be selected as the bus mode.

Block transfer mode cannot be used.

External Request Mode: In external request mode, transfer is started by a transfer request signal

(EDREQ) from a device external to this LSI. DMA transfer is started when EDREQ is input while

DMA transfer is enabled (EDA = 1).

The transfer request source need not be the data transfer source or data transfer destination.

The transfer request signal is accepted via the EDREQ pin. Either falling edge sensing or low level

sensing can be selected for the EDREQ pin by means of the EDREQS bit in EDMDR (low level

sensing when EDREQS = 0, falling edge sensing when EDREQS = 1).

Setting the EDRAKE bit to 1 in EDMDR enables a signal confirming transfer request acceptance

to be output from the EDRAK pin. The EDRAK signal is output when acceptance and transfer

processing has been started in response to a single external request. The EDRAK signal enables

the external d evice to d e termine the timing of EDREQ signal negation, and makes it possible to

provide handshaking between the transfer request source and the EXDMAC.

In external request mode, block transfer mode can be used instead of burst mode. Block transfer

mode allows continuous execution (burst operation) of the specified number of transfers (the block

size) in response to a single transfer request. In block transfer mode, the EDRAK signal is output

only once for a one-block transfer, since the transfer request via the EDREQ pin is for a block

unit.

8.4.4 Bus Modes

There are two bus modes: cycle steal mode and burst mode. When the activation source is an auto

request, either cycle steal mode or burst mode can be selected. When the activation source is an

external request, cycle steal mode is used.

Cycle Steal Mode: In cycle steal mode, the EXDMAC releases the bus at the end of each transfer

of a transfer unit (byte, word, or block). If there is a subsequent transfer request, the EXDMAC

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takes back the bus, performs another transfer-unit transfer, and then releases the bus again. This

procedure is re p eated until the transfer end conditio n is satisfied.

If a transfer request occurs in another ch annel during DMA transfer, the bus is temporarily

released, then transfer is performed on the channel for which the transfer request was issued. If

there is no external space bus request from another bus master, a one-cycle bus release interval is

inserted. For details on the operation when there are requests for a number of channels, see section

8.4.8, Channel Priority Order.

Figure 8.5 shows an example of the timing in cycle steal mode.

CPU CPU CPU CPUEXDMAC EXDMAC

Bus returned temporarily to CPU

EDREQ

EDRAK

Bus cycle

Transfer conditions:

• Single address mode, normal transfer mode

• EDREQ low level sensing

• CPU internal bus master is operating in external space

Figure 8.5 Example of Timing in Cycle Steal Mode

Burst Mode : In burst mode, once the EXDMAC acquires the bus it continues transferring data,

without releasing the bus, until the transfer end condition is satisfied. There is no burst mode in

external request mode.

In burst mod e, once tr ansfer is started it is not interrupted even if there is a transfer r equ est f rom

another channel with higher priority. When the burst mode channel finishes its transfer, it releases

the bus in the next cycle in the same way as in cycle steal mode.

When the EDA bit is clear ed to 0 in EDMDR, DMA transfer is halted. However, DMA transfer is

executed for all transfer requests generated within the EXDMAC u p until the EDA bit was cleared

to 0.

If a repeat area overflow interrupt is generated, the EDA bit is cleared to 0 and transfer is

terminated.

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When the BGUP bit is set to 1 in EDMDR, the bus is released if a bus re q uest is issued by anoth e r

bus mastership during burst transfer. If there is no bus request, burst transfer is executed even if

the BGUP bit is se t to 1.

Figure 8.6 shows examples of the timing in burst mode.

CPU CPU CPU CPU

Bus cycle

EXDMAC operates alternately with CPU

EXDMAC EXDMAC EXDMAC

Transfer conditions:

Auto request mode, BGUP = 1

CPU CPU CPU CPU

Bus cycle

CPU cycle not generated

EXDMAC EXDMAC EXDMAC

Transfer conditions:

Auto request mode, BGUP = 0

Figure 8.6 Examples of Timing in Burst Mode

8.4.5 Transfer Modes

There are two transfer modes: normal transfer mode and block transfer mode. When the activation

source is an external request, either normal transfer mode or block transfer mode can be selected.

When the activation source is an auto request, normal transfer mode is used.

Normal Transfer Mode: In normal transfer mode, transfer of one transfer unit is processed in

response to one transfer request. EDTCR functions as a 24-bit transfer counter.

The ETEND signal is output only for th e last DMA transfer. The EDRAK signal is output each

time a transfer request is accepted and tran sfer processing is started.

Figure 8.7 shows examples of DMA transfer timing in normal transfer mode.

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Read Write Read Write

EXDMA

transfer cycle Last EXDMA

transfer cycle

Bus cycle

ETEND

Transfer conditions:

Dual address mode, auto request mode

EXDMA EXDMA

EDRAK

EDREQ

Bus cycle

EDACK

Transfer conditions:

Single address mode, external request mode

Figure 8.7 Examples of Timing in Normal Transf er Mode

Block Tra nsfer Mode: In block transfer mode, the number of bytes or words specified by the

block size is transferred in response to one transfer request. The upper 8 bits of EDTCR specify

the block size, and the lower 16 bits function as a 16-bit transfer counter. A block size of 1 to 256

can be specified. During transfer of a block, transfer requests for other higher-priority channels are

held pending. When transfer of one block is completed, the bus is released in the next cycle.

When the BGUP bit is set to 1 in EDMDR, the bus is released if a bus re q uest is issued by anoth e r

bus mastership during block transfer.

Address register values are updated in the same way as in normal mode. There is no function for

restoring the initial address register values after each block transfer.

The ETEND signal is output for each block transfer in the DMA transfer cycle in which the block

ends. The EDRAK signal is output once for one transfer request (for transfer of one block).

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Caution is required when setting the repeat area overflow interrupt of the repeat area function in

block transfer mode. See section 8.4.6, Repeat Area Function, for details.

Block transfer is aborted if an NMI interrupt is generated. See section 8.4.12, Ending DMA

Transfer, for details.

Figure 8.8 shows an example of DMA transfer timing in block transfer mode.

CPUCPU CPU EXDMAC EXDMAC EXDMAC CPU

Bus cycle

EDRAK

ETEND

EDREQ

CPU cycle not generated

One-block transfer cycle

Transfer conditions:

• Single address mode

• BGUP = 0

• Block size (EDTCR[23:16]) = 3

Figure 8.8 Example of Timing in Block Transfer Mode

8.4.6 Repeat Area Function

The EXDMAC has a function for designating a repeat area for source addresses and/or destination

addresses. When a repeat area is designated, the address register values repeat within the range

specified as the repeat area. Normally, when a ring buffer is involved in a transfer, an operation is

required to restore the address register value to the buffer start address each time the address

the repeat area function is used, the operation that restores the address register value to the buffer

start address is p erformed automatically within th e EXDMAC.

The repeat area function can be set independently for the source address register and the

destination address register.

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The source address repeat area is specified by bits SARA4 to SARA0 in EDACR, and the

destination address repeat area by bits DARA4 to DARA0 in EDACR. The size of each repeat

area can be specified independently.

When the address register value is the last address in the repeat area and repeat area overflow

occurs, DMA transfer can be temporarily halted and an interrupt request sent to the CPU. If the

SARIE bit in EDACR is set to 1, when the source address register overflows the repeat area, the

IRF bit is set to 1 and the EDA bit cleared to 0 in EDMDR, and transf er is terminated. If EDIE = 1

in EDMDR, an interrupt is requested. If the DARIE bit in EDACR is set to 1, the above applies to

the destination address register.

If the EDA bit in EDMDR is set to 1 during interrupt generation, tr ansfer is resumed. Figure 8.9

illustrates the operation o f the r e peat area function.

External memory

Repeated

Repeat area overflow

interrupt can be

requested

Range of

EDSAR values

H'23FFFE

H'23FFFF

H'240000

H'240001

H'240002

H'240003

H'240004

H'240005

H'240006

H'240007

H'240008

H'240009

H'240000

H'240001

H'240002

H'240003

H'240004

H'240005

H'240006

H'240007

When lower 3 bits (8-byte area) of EDSAR are designated as repeat area

(SARA4 to SARA0 = 3)

Figure 8.9 Example of Repeat Area Function Operation

Caution is required when the repeat area overflow interrupt function is used together with block

transfer mode. If transfer is always terminated when repeat area overflow occurs in block transfer

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mode, the block size must be a power of two, or alternatively, the address register value must be

set so that the end of a block coincides with the end of the repeat area range.

If repeat area overflow occurs while a block is being transferred in block transfer mode, the repeat

interrupt r equ est is held pending until the end of the block, and transfer overrun will occur. Figure

8.10 shows an example in which block transfer mode is used together with the repeat area

function.

External memory Range of

EDSAR values First block

transfer Second block

transfer

H'23FFFE

H'23FFFF

H'240000

H'240001

H'240002

H'240003

H'240004

H'240005

H'240006

H'240007

H'240008

H'240009

H'240000

H'240001

H'240002

H'240003

H'240004

H'240005

H'240006

H'240007

H'240000

H'240001

H'240002

H'240003

H'240004

H'240000

H'240001

H'240005

H'240006

H'240007

Interrupt

requested

Block transfer

in progress

When lower 3 bits (8-byte area) of EDSAR are designated as repeat area (SARA4 to SARA0 = 3),

and block size of 5 (EDTCR[23–16] = 5) is set in block transfer mode

Figure 8.10 Example of Repeat Area Function Operation in Block Transfer Mode

8.4.7 Registers during DMA Transfer Operation

EXDMAC register values are updated as DMA transfer processing is performed. The updated

values depend on various settings and the transfer status. The following registers and bits are

updated: EDSAR, EDDAR, EDTCR, and bits EDA, BEF, and IRF in EDMDR,

EXDMA Source Address Register (EDSAR): When the EDSAR address is accessed as the

transfer source, after the EDSAR value is outpu t, EDSAR is updated with the address to be

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accessed next. Bits SAT1 and SAT0 in EDACR specify incrementing or decrementing. The

address is fixed when SAT1 = 0, incremented when SAT1 = 1 and SAT0 = 0, and decremented

when SAT1 = 1 and SAT0 = 1.

The size of the increment or decrement is determined by the size of the data transferred. When the

DTSIZE bit in EDMDR = 0, th e data is byte-size and the address is in cr em ented or decremented

by 1; when DTSIZE = 1, the data is word-size and the address is incremented or decremented by

When a repeat area setting is made, the operation conforms to that setting. The upper part of the

address set for the repeat area function is fixed, and is not affected by address updating.

When EDSAR is read during a transfer operation, a longword access must be used. During a

transfer operation, EDSAR may be updated without regard to accesses from the CPU, and the

correct values may not be read if the upper and lower words are read separately. In a longword

access, the EXDMAC buffers the EDSAR value to ensure that the correct value is output.

Do not write to EDSAR for a channel on which a transfer operation is in progress.

EXDMA Destination Ad dress Register (EDDAR): When the EDDAR address is accessed as the

transfer destination, after the EDDAR value is output, EDDAR is updated with the address to be

accessed next. Bits DAT1 and DAT0 in EDACR specify incrementing or decrementing. The

address is fixed when DAT1 = 0, incremented when DAT1 = 1 and DAT0 = 0, and decremented

when DAT1 = 1 and DAT0 = 1.

The size of the increment or decrement is determined by the size of the data transferred. When the

DTSIZE bit in EDMDR = 0, th e data is byte-size and the address is in cr em ented or decremented

by 1; when DTSIZE = 1, the data is word-size and the address is incremented or decremented by

When a repeat area setting is made, the operation conforms to that setting. The upper part of the

address set for the repeat area function is fixed, and is not affected by address updating.

When EDDAR is read during a transfer operation, a longword access must be used. During a

transfer operation, EDDAR may be updated without regard to accesses from the CPU, and the

correct values may not be read if the upper and lower words are read separately. In a longword

access, the EXDMAC buffers the EDDAR value to ensure that the correct value is output.

Do not write to EDDAR for a channel on which a transfer operation is in progress.

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EXDMA Transfer Count Register (EDTCR): When a DMA transfer is performed, the value in

EDTCR is decremented by 1. However, when the EDTCR value is 0, transfers are not counted and

the EDTCR value does not change.

EDTCR functions differently in block transfer mode. The upper 8 bits, EDTCR[23:16], are used to

specify the block size, and their value does not change. The lower 16 bits, EDTCR[15:0], function

as a transfer counter, the value of which is decremented by 1 when a DMA transfer is performed.

However, when the EDTCR[15:0] value is 0, transfers are not counted and the EDTCR[15:0]

value does not change.

In normal transfer mode, all of the lower 24 bits of EDTCR may change, so when EDTCR is read

by the CPU during DMA transfer, a longword access must be used. During a transfer operation,

EDTCR may be updated without regard to accesses from the CPU, and the co rrect values may not

be read if the upper and lower words are read separately. In a longword access, the EXDMAC

buffer s the EDTCR valu e to ensure that the correct value is output.

In block transfer mode, the upper 8 bits are never updated, so there is no problem with using word

access.

Do not write to EDTCR f or a channel on which a transfer operation is in progress. If there is

contention between an address update associated with DMA transfer and a write by the CPU, the

CPU write has pr iority.

In the event of contention between an EDTCR update from 1 to 0 and a write (of a nonzero value)

by the CPU, the CPU wr ite value has pr iority as the EDTCR value, but transfer is terminated.

Transfer does not end if the CPU writes 0 to EDTCR.

Figure 8.11 shows EDTCR update operations in normal transfer mode and block transfer mode.

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23 0

0EDTCR Fixed 23 0

Before update After update

23 0

1 to H'FFFFFFEDTCR –1 23 0

0 to H'FFFFFE

EDTCR

EDTCR in normal transfer mode

EDTCR in block transfer mode

Fixed

Before update After update

23 15 016

1 to H'FFFF

Block

size

EDTCR –1

23 15 016

Block

size

23 15 016

0 to H'FFFE

Block

size

23 15 016

Block

size

Figure 8.11 EDTCR Update Operations in Normal Transfer Mode and

Block Transfer Mode

EDA Bit in EDMDR: The EDA bit in EDMDR is written to by the CPU to con tr ol enabling and

disabling of data transfer, but may be cleared automatically by the EXDMAC due to the DMA

transfer status. There are also periods during transfer when a 0-write to the EDA bit by the CPU is

not immediately effective.

Condition s for EDA bit clearing by the EXDMAC include the following :

• When the EDTCR value changes from 1 to 0, and transfer ends

• When a repeat area overflo w interrupt is requested, and transfer ends

• When an NMI interrupt is generated, and transfer halts

• A reset

• Hardware standby mode

• When 0 is written to the EDA bit, and transfer halts

When transf er is halted by writing 0 to the EDA bit, the EDA bit remains at 1 during the DMA

transfer period. In block transfer mode, since a block-size transfer is carried out without

interrup tion, the EDA bit remains at 1 from the time 0 is written to it u ntil the end of the current

block-size transfer.

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In burst mod e, tr ansfer is halted for up to three DMA tran sf ers following the bus cycle in which 0

is written to the EDA b it. The EDA bit remains set to 1 f rom the time of the 0-write until the end

of the last DMA cycle.

Writes (except to the EDA bit) are prohibited to registers of a channel f or wh ich the EDA bit is set

to 1. When changing register settings after a 0-write to the EDA bit, it is necessary to co nfirm that

the EDA bit has been cleared to 0.

Figure 8.12 shows the procedure for changing register settings in an operating channel.

Read EDA bit

Write 0 to EDA bit

Change register settings

EDA bit = 0?

1. Write 0 to the EDA bit in EDMDR.

2. Read the EDA bit.

3. Confirm that EDA = 0. If EDA = 1, this

indicates that DMA transfer is in progress.

4. Write the required set values to the

registers.

Yes

Changing register settings

in operating channel

changes completed

Figure 8.12 Procedure for Changing Register Settings in Operating Channel

BEF Bit in EDMDR: In block transfer mode, the specified number of transfers (equ ivalent to the

block size) is performed in response to a single transfer request. To ensure that the correct number

of transfers is carried out, a block-size transfer is always executed, except in the event of a reset,

transition to standby mode, or generation of an NMI interrupt.

If an NMI interrupt is generated during block transfer, operation is halted midway through a

block-size tr an sfer and the EDA bit is cleared to 0 , termin ating the transfer operation. In th is case

the BEF bit, which indicates the occurrence of an error during block transfer, is set to 1.

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IRF Bit in EDMDR: The IRF bit in EDMDR is set to 1 when an inter rupt request source o ccurs.

If the EDIE bit in EDMDR is 1 at this time, an interr upt is r equested.

The timing for setting the IRF bit to 1 is when the EDA bit in EDMDR is cleared to 0 and transfer

ends following the end of the DMA transfer bus cycle in which the source generating the interrupt

occurred.

If the EDA bit is set to 1 and transfer is resum e d during interrupt h a ndling, the IRF bit is

automatically cleared to 0 and the interrupt request is cleared.

For details on interrupts, see section 8.5, Interrupts Sources.

8.4.8 Channel Prio rit y Order

The priority order of the EXDMAC channels is: channel 0 > channel 1 > channel 2 > channel 3.

Table 8.3 shows the EXDMAC channel priority order.

Table 8.3 EXD MAC Channel Priority Order

Channel Priority

Channel 0 High

Channel 1

Channel 2

Channel 3 Low

If transfer requests occur simultaneously for a nu mber of channels, the highest-priority channel

according to the priority order in table 8.3 is selected for transfer.

Transfer Requests from Multiple Channels (Except Auto Request Cycle Steal Mode): If

transfer requests for different channels are issued during a transfer operation, the highest-priority

channel (excluding the currently transferring channel) is selected. The selected channel begins

transfer after the currently transferring channel releases the bus. If there is a bus requ est from a bus

mastership o ther than the EXDMAC at this time, a cy cle f or the other bus mastership is initiated.

If there is no other bus request, the bus is released for one cycle.

Channels are not switched during burst transfer or transfer of a block in block transfer mode.

Figure 8.13 shows an example of the transfer timing when transfer requests occur simultaneously

for channels 0, 1, and 2. The example in the figure is for external request cycle steal mode.

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Channel 0 transfer

Idle

Bus

release

Address bus

EXDMA control

Channel 0

Channel 1

Channel 1 transfer Channel 2 transfer

Channel 2Channel 0 Channel 1

Channel 2Channel 0

Request

held Selected

Request

held Request

held

Not

selected Selected

Channel 1

Request cleared

Bus

release

Channel 2

Figure 8.13 Example of Channel Priority Timing

Transfer Requests from Multiple Channels in Aut o Request Cy cle St eal Mode: If transfer

requests for different channels are issued during a transfer in auto request cycle steal mode, the

operation depends on the channel priority. If the channel that made the transfer request is of higher

priority than the channel currently performing transfer, the channel that made the transfer request

is selected.

If the channel that made the transfer request is o f lower priority than the channel currently

performing transfer, that channel’s transfer request is held pending, and the currently transferring

channel remains selected.

The selected channel begins transfer after the currently transferring channel releases the bus. If

there is a bus request from a bus mastership other than the EXDMAC at this time, a cycle for the

other bus mastership is initiated. If there is no other bus request, the bus is released for one cycle.

Figure 8.14 shows examples of transfer timing in cases that include auto request cycle steal mode.

Section 8 EXDMA Controller

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Channel 0 Channel 0 Channel 0 Channel 1 Channel 1

Bus

Conditions (1)

Channel 0: Auto request, cycle steal mode

Channel 1: External request, cycle steal mode, low level activation

Channel 0

EDA bit

Channel 1/

EDREQ1 pin

Channel 2 Channel 2 Channel 1 Channel 1Channel 2 Channel 1

Bus

Conditions (2)

Channel 1: External request, cycle steal mode, low level activation

Channel 2: Auto request, cycle steal mode

Channel 1/

EDREQ1 pin

Channel 2

EDA bit

Channel 2 Channel 2 Channel 0 Channel 2Channel 0

Bus

Conditions (3)

Channel 0: Auto request, cycle steal mode

Channel 2: Auto request, cycle steal mode

Note: *: Bus release

Channel 0

EDA bit

Channel 2

EDA bit

**** *

*** *

** * *

Figure 8.14 Examples of Channel Priority Timing

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8.4.9 EXDMAC Bus Cycles (Dua l Address Mode)

Normal Transfer Mode (Cycle Steal Mode): Figure 8.15 shows an example of transfer when

ETEND output is enabled, and word-size, normal transfer mode (cycle steal mode) is performed

from external 16-bit, 2-state access space to external 16-bit, 2-state access space.

After one byte o r word has been transferred, the bus is released. While the bus is re leased , one

CPU, DMAC, or DTC bu s cy cle is initiated.

DMA read

HWR

ETEND

LWR

DMA write DMA read DMA write DMA read DMA write

Address bus

Bus

release Bus

release

Bus

release Bus

release Last transfer

cycle

Figure 8.15 Example of Normal Transfer Mode (Cycle Steal Mode) Transfer

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Normal Transfer Mode (Burst Mo de): Figure 8.16 shows an example of transfer when ETEND

output is enabled, and word-size, normal transfer mode (burst mode) is performed from extern al

16-bit, 2-state access space to external 16-bit, 2-state access space.

In burst mode, one-by te or one-word transfers are executed continuously until transfer end s.

Once burst transfer starts, requests from other channels, even of higher priority, are held pending

until transf er ends.

DMA read

HWR

ETEND

LWR

DMA write DMA read DMA write DMA read DMA write

Address bus

Bus

release Bus

release

Last transfer cycle

Burst transfer

Figure 8.16 Example of Normal Transfer Mode (Burst Mode) Transfer

If an NMI interru pt is generated while a channel designated for burst transfer is enabled for

transfer, the EDA bit is cleared and transfer is disabled. If a block transfer has already been

initiated within th e EXDMAC, the bus is released on completion of the currently execu ting byte or

word transfer, and burst transfer is aborted. If the last transfer cycle in burst transfer has been

initiated within th e EXDMAC, tr ansfer is executed to the end even if the EDA bit is cleared.

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Block Tran sfer Mode (Cycle Steal Mode): Figure 8.17 shows an example of transfer when

ETEND output is enabled, and word-size, block transfer mode (cycle steal mode) is performed

from external 16-bit, 2-state access space to external 16-bit, 2-state access space.

One block is transferred in response to one transfer request, and after the transfer, the bus is

released. While the b us is released, one or more CPU, DMAC, or DTC bus cycles are initiated.

DMA

read

HWR

ETEND

LWR

DMA

write

Address bus

Bus

release Bus

release

Last block transfer

DMA

read

Block transfer

DMA

write DMA

read DMA

write DMA

read DMA

write

Figure 8.17 Example of Block Transfer Mode (Cycle Steal Mode) Transfer

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EDREQ

EDREQEDREQ

EDREQ Pin Falling Edge Activat ion Timing: Figure 8.18 shows an example of normal mode

transfer activated by the EDREQ pin falling edge.

DMA read DMA write

Address bus

EDREQ

Write Idle

Bus release

Transfer

destination

DMA control

Channel

Write Idle

Transfer source Transfer source

Bus release DMA read DMA write Bus release

Request Request

[1] [3][2] [4] [5] [6] [7]

Acceptance

resumed

Acceptance

resumed

Read Read

Idle

[1] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of φ, and request is held.

[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.

[3], [6] DMA cycle start; EDREQ pin high level sampling is started at rise of φ.

[4], [7] When EDREQ pin high level has been sampled, acceptance is resumed after completion of write cycle.

(As in [1], EDREQ pin low level is sampled at rise of ø, and request is held.)

Transfer

destination

Request clearance period Request clearance period

Minimum 3 cycles Minimum 3 cycles

Figure 8.18 Example of Normal Mode Transfer Activated by EDREQ

EDREQEDREQ

EDREQ Pin Falling Edge

EDREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the

EDMDR write cycle for setting the transfer-enabled state.

When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible,

the request is held within the EXDMAC. Then when activation is initiated with in the EXDMAC,

the request is cleared, and EDREQ pin high level sampling for edge sensing is started. If EDREQ

pin high level sampling is completed by the end of the DMA write cycle, acceptance resumes after

the end of the write cycle, and EDREQ pin low level sampling is performed again; this sequence

of operation s is repeated until the end of the transfer .

Figure 8.19 shows an example of block transfer mode transfer activated by the EDREQ pin falling

edge.

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DMA read DMA write

Address bus

EDREQ

Idle Write

Bus release

Transfer

destination

DMA control

Channel

WriteIdle

Transfer source Transfer

destination

Transfer source

Request Request

Minimum 3 cycles

Acceptance

resumed Acceptance

resumed

Read

Bus release DMA read DMA write Bus release

One block transfer One block transfer

Idle

[1] [4] [5] [6] [7][3][2]

[1] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of φ, and request is held.

[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.

[3], [6] DMA cycle start; EDREQ pin high level sampling is started at rise of φ.

[4], [7] When EDREQ pin high level has been sampled, acceptance is resumed after completion of dead cycle.

(As in [1], EDREQ pin low level is sampled at rise of φ, and request is held.)

Read

Request clearance period Request clearance period

Minimum 3 cycles

Figure 8.19 Example of Block Transfer Mode Transfer Activated

by EDREQ

EDREQEDREQ

EDREQ Pin Falling Edge

EDREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the

EDMDR write cycle for setting the transfer-enabled state.

When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible,

the request is held within the EXDMAC. Then when activation is initiated with in the EXDMAC,

the request is cleared, and EDREQ pin high level sampling for edge sensing is started. If EDREQ

pin high level sampling is completed by the end of the DMA write cycle, acceptance resumes after

the end of the write cycle, and EDREQ pin low level sampling is performed again; this sequence

of operation s is repeated until the end of the transfer .

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EDREQ

EDREQEDREQ

EDREQ Pin Low Level Activation Timing: Figure 8.20 shows an example of normal mode

transfer activated by the EDREQ pin low level.

DMA read DMA write

Address bus

EDREQ

Idle Write Idle

Bus release

DMA control

Channel

Write Idle

Transfer source

Bus release DMA read DMA write

Request

Read Read

Transfer

destination Transfer source Transfer

destination

Bus release

[1] [3][2] [4] [6][5] [7]

Acceptance

resumed Acceptance

resumed

[1] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of φ, and request is held.

[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.

[3], [6] DMA cycle is started.

[4], [7] Acceptance is resumed after completion of write cycle.

(As in [1], EDREQ pin low level is sampled at rise of φ, and request is held.)

Minimum 3 cycles Request

Minimum 3 cycles

Request clearance period Request clearance period

Figure 8.20 Example of Normal Mode Transfer Activated by EDREQ

EDREQEDREQ

EDREQ Pin Low Level

EDREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the

EDMDR write cycle for setting the transfer-enabled state.

When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible,

the request is held within the EXDMAC. Then when activation is initiated with in the EXDMAC,

the request is cleared. At the end of the write cycle, acceptance resumes and EDREQ pin low level

sampling is p e r formed again; this sequ ence of operations is repeated until the end of the transfer.

Figure 8.21 shows an example of block transfer mode transfer activated by the EDREQ pin low

level.

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DMA read DMA write

Address bus

EDREQ

Idle Write

Bus release

DMA control

Channel

WriteIdleRead

Bus release DMA read DMA write

One block transfer One block transfer

Idle

Transfer

destination

Transfer source Transfer

destination

Transfer source

[1] [3][2] [4] [6][5] [7]

Acceptance

resumed Acceptance

resumed

Bus release

[1] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of φ, and request is held.

[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.

[3], [6] DMA cycle is started.

[4], [7] Acceptance is resumed after completion of dead cycle.

(As in [1], EDREQ pin low level is sampled at rise of φ, and request is held.)

Minimum 3 cycles

Request Request

Read

Minimum 3 cycles

Request clearance period Request clearance period

Figure 8.21 Example of Block Transfer Mode Transfer Activated by EDREQ

EDREQEDREQ

EDREQ Pin Lo w Level

EDREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the

EDMDR write cycle for setting the transfer-enabled state.

When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible,

the request is held within the EXDMAC. Then when activation is initiated with in the EXDMAC,

the request is cleared. At the end of the write cycle, acceptance resumes and EDREQ pin low level

sampling is p e r formed again; this sequ ence of operations is repeated until the end of the transfer.

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8.4.10 EXDMAC Bus Cycles (Single Address Mode)

Single Address Mode (Read): Figure 8.22 shows an example of transfer when ETEND output is

enabled, and byte-size, single address mode transfer (read) is performed from external 8-bit, 2-

state access space to an external device.

ETEND

Address bus

Bus release Bus release Bus releaseLast

transfer

cycle

DMA read

EDACK

DMA readDMA readDMA read

Bus releaseBus release

Figure 8.22 Example of Single Address Mode (Byte Read) Transfer

Figure 8.23 shows an ex ample of transfer when ETEND output is enabled, and word-size, single

address mode transfer (read) is perf ormed from external 8-bit, 2-state access space to an external

device.

DMA read

ETEND

Address bus

Bus release Bus release Bus

release

Last transfer cycle

EDACK

Bus release

DMA readDMA read

Figure 8.23 Example of Single Address Mode (Word Read) Transfer

After one byte or word has been transferred in response to one transfer request, the bus is released.

While the bus is released , one or more CPU, DMAC, or DTC bu s cy cles ar e initiated.

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Single Address Mode (Write ) : Figure 8.24 shows an ex ample of transfer when ETEND output is

enabled, and byte-size, single address mode transfer (write) is performed from an external device

to external 8-bit, 2-state access space.

HWR

ETEND

Address bus

Bus release Bus release Bus releaseLast

transfer

cycle

DMA write

EDACK

DMA writeDMA writeDMA write

Bus releaseBus release

LWR

Figure 8.24 Example of Single Address Mode (Byte Write) Transfer

Figure 8.25 shows an ex ample of transfer when ETEND output is enabled, and word-size, single

address mode transfer (write) is performed from an external device to external 8-bit, 2-state access

space.

DMA write

HWR

ETEND

Address bus

Bus release Bus release Bus

release

Last transfer cycle

EDACK

Bus release

DMA writeDMA write

LWR

Figure 8.25 Example of Single Address Mode (Word Write) Transfer

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After one byte or word has been transferred in response to one transfer request, the bus is released.

While the bus is released , one or more CPU, DMAC, or DTC bu s cy cles ar e initiated.

EDREQ

EDREQEDREQ

EDREQ Pin Falling Edge Activat ion Timing: Figure 8.26 shows an example of single address

mode transfer activated by the EDREQ pin falling edge.

DMA single

Address bus

EDREQ

Idle

Bus release

DMA control

Channel

Transfer source/

destination Transfer source/

destination

Bus release

Idle

DMA single Bus release

Single Single Idle

EDACK

[1] [3][2] [4] [6][5] [7]

Acceptance

resumed Acceptance

resumed

[1] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of φ, and request is held.

[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.

[3], [6] DMA cycle start; EDREQ pin high level sampling is started at rise of φ.

[4], [7] When EDREQ pin high level has been sampled, acceptance is resumed after completion of single cycle.

(As in [1], EDREQ pin low level is sampled at rise of φ, and request is held.)

Request

clearance period Request

clearance period

Minimum 3 cycles

Request Minimum 3 cycles

Request

Figure 8.26 Example of Single Address Mode Transfer Activated by EDREQ

EDREQEDREQ

EDREQ Pin

Falling Edge

EDREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the

EDMDR write cycle for setting the transfer-enabled state.

When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible,

the request is held within the EXDMAC. Then when activation is initiated with in the EXDMAC,

the request is cleared, and EDREQ pin high level sampling for edge sensing is started. If EDREQ

pin high level sampling is comp leted by the end of the DMA single cycle, acceptance resumes

after the end of the single cycle, and EDREQ pin low level sampling is performed again; this

sequence of ope r ations is re p eated until the end of the transfer.

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EDREQ

EDREQEDREQ

EDREQ Pin Lo w Le vel Activation Timing: Figure 8.27 shows an example of single address

mode transfer activated by the EDREQ pin low level.

Single Single

DMA single

Address bus

EDREQ

Idle

Bus release

DMA control

Channel

Transfer source/

destination Transfer source/

destination

Bus release

Idle

DMA single Bus release

Idle

EDACK

[1] [3][2] [4] [6][5] [7]

Acceptance

resumed Acceptance

resumed

Request

clearance period Request

clearance period

Request Request

Minimum 3 cycles Minimum 3 cycles

[1] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of φ, and request is held.

[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.

[3], [6] DMA cycle is started.

[4], [7] Acceptance is resumed after completion of single cycle.

(As in [1], EDREQ pin low level is sampled at rise of φ, and request is held.)

Figure 8.27 Example of Single Address Mode Transfer Activated by EDREQ

EDREQEDREQ

EDREQ Pin Lo w Level

EDREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the

EDMDR write cycle for setting the transfer-enabled state.

When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible,

the request is held within the EXDMAC. Then when activation is initiated with in the EXDMAC,

the request is cleared. At the end of the single cycle, acceptance resumes and EDREQ pin low

level sampling is performed again; th is sequence of operations is re peated until the end of the

transfer.

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8.4.11 Examples of Operation Timing in Each Mode

Auto Request/Cyc le St eal Mode/Normal Transfer Mode: When the EDA bit is set to 1 in

EDMDR, an EXDMA transfer cycle is started a minimum of three cycles later. There is a one-

cycle bus release interval between the end of a one-transfer-unit EXDMA cycle and the start of the

next transfer.

If there is a transfer request for another channel of higher priority, the transfer request by the

original channel is held pending, and transfer is performed on the higher-priority channel from the

next transfer. Transfer on the original channel is resumed on completion of the higher-priority

channel transfer.

Figures 8. 28 to 8.30 sho w ope r a tion timing examples f or various conditions.

φ pin

ETEND

Bus cycle

CPU

operation

EDA bit

EXDMA

read

EDA = 1

write

EXDMA

write EXDMA

read EXDMA

write EXDMA

read EXDMA

write

3 cycles 1 cycle Last transfer cycle

Internal bus space

cycles

Bus release

Bus

release

Bus

release

Figure 8.28 Auto Request/Cycle Steal Mode/Normal Transfer Mode

(No Cont ention/Dual Address Mode)

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φ pin

EDACK

Bus cycle

CPU

operation

ETEND

CPU cycle

EXDMA single

transfer cycle

External

space

CPU cycle CPU cycle CPU cycle

1 bus cycle

Last transfer cycle

EXDMA single

transfer cycle EXDMA single

transfer cycle

External spaceExternal spaceExternal space

Figure 8.29 Auto Request/Cycle Steal Mode/Normal Transfer Mode

(CPU Cycles/Single Address Mode)

φ pin

Bus cycle

Current

channel

EDACK

Other

channel

transfer

request

(EDREQ)

EXDMA

single cycle

1 cycle 1 cycle 1 cycle

Higher-priority channel EXDMA cycle

EXDMA

single cycle

EXDMA

single cycle

EXDMA

single cycle

Bus

release

Bus

release

Bus

release

Bus

release

Bus

release

Figure 8.30 Auto Request/Cycle Steal Mode/Normal Transfer Mode

(Contention with Another Channel/Single Address Mode)

Section 8 EXDMA Controller

Rev. 3.00 Mar 17, 2006 page 382 of 926

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Auto Request/Burst Mode/Normal Transfer Mode: When the EDA bit is set to 1 in EDMDR,

an EXDMA transfer cycle is started a minimum of three cycles later. Once transfer is started, it

continu es (as a burst) until th e transfer end condition is satisf ied.

If the BGUP bit is 1 in EDMDR, the bus is transferred in the event of a bus request from another

bus master.

Transfer requests for other channels are held pending until the end of transfer on the curren t

channel.

Figures 8. 31 to 8.34 sho w ope r a tion timing examples f or various conditions.

φ pin

ETEND

Bus cycle

CPU

operation

EDA bit

EXDMA

read

EXDMA

write EXDMA

read EXDMA

write EXDMA

read EXDMA

write

External

space External

space

Repeated

Last transfer cycle

CPU cycle CPU cycle CPU cycle

Figure 8.31 Auto Request/Burst Mode/Normal Transfer Mode

(CPU Cycles/Dual Address Mode/BGUP = 0)

φ pin

Bus cycle

CPU

operation

EXDMA

read

EXDMA

write EXDMA

read EXDMA

write EXDMA

read EXDMA

write

External

space External

space

1 bus cycle 1 bus cycle

CPU cycle CPU cycle CPU cycle CPU cycle

Figure 8.32 Auto Request/Burst Mode/Normal Transfer Mode

(CPU Cycles/Dual Address Mode/BGUP = 1)

Section 8 EXDMA Controller

Rev. 3.00 Mar 17, 2006 page 383 of 926

REJ09B0283-0300

CPU cycle CPU cycle CPU cycle CPU cycle CPU cycle

External

space External

space

1 bus cycle Last transfer cycle

φ pin

EDACK

Bus cycle

CPU

operation

ETEND

EXDMA

single cycle EXDMA

single cycle

Figure 8.33 Auto Request/Burst Mode/Normal Transfer Mode

(CPU Cycles/Single Address Mode/BGUP = 1)

φ pin

Bus cycle

Original

channel

EDACK

Original

channel

ETEND

Other

channel

transfer

request

(EDREQ)

EXDMA single

transfer cycle EXDMA single

transfer cycle

1 cycleLast transfer

cycle

Other channel EXDMA cycle

Bus release Bus

release

Bus

release

Figure 8.34 Auto Request/Burst Mode/Normal Transfer Mode

(Contention with Another Channel/Single Address Mode)

Section 8 EXDMA Controller

Rev. 3.00 Mar 17, 2006 page 384 of 926

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External Request/Cycle Steal Mode/Normal Transfer Mode: In external request mode, an

EXDMA transfer cycle is started a minimum of three cycles after a transfer request is accepted.

The next transfer request is accepted after the end of a one-transfer-unit EXDMA cycle. For

external bus space CPU cycles, at least two bus cycles are generated before the next EXDMA

cycle.

If a transfer request is generated for another channel, an EXDMA cycle for the other channel is

generated before the next EXDMA cycle.

The EDREQ pin sensing timing is different for low level sensing and falling edge sensing. The

same applies to transfer request acceptance and transfer start timing.

Figures 8. 35 to 8.38 sho w ope r a tion timing examples f or various conditions.

φ pin

EDREQ

EDRAK

ETEND

Bus cycle

EDA bit

Bus release Bus release Bus release

EXDMA

read

EXDMA

write EXDMA

read EXDMA

write

Last transfer cycle3 cycles

Figure 8.35 External Request/Cycle Steal Mode/Normal Transfer Mode

(No Cont ention/Dual Address Mode/Low Lev e l Sensing)

Section 8 EXDMA Controller

Rev. 3.00 Mar 17, 2006 page 385 of 926

REJ09B0283-0300

φ pin

EDREQ

EDACK

ETEND

EDRAK

Bus cycle

CPU

operation

Last transfer cycle2 bus cycles

CPU cycle

External

space External

space

EXDMA single

transfer cycle EXDMA single

transfer cycle

CPU cycle CPU cycle CPU cycle CPU cycle CPU cycle

Figure 8.36 External Request/Cycle Steal Mode/Normal Transfer Mode

(CPU Cycles/Single Address Mode/Low Level Sensing)

φ pin

EDREQ

EDACK

EDRAK

Bus cycle

EDREQ

acceptance

internal

processing

state

Bus release Bus release Bus release

Start of high

level sensing Start of high

level sensing

EXDMA single

transfer cycle EXDMA single

transfer cycle

Edge confirmation

Start of transfer

processing

Edge confirmation

Start of transfer

processing

Edge confirmation

Start of transfer

processing

Figure 8.37 External Request/Cycle Steal Mode/Normal Transfer Mode

(No Cont ention/Single Addre ss Mode/Falling Edge Sensing)

Section 8 EXDMA Controller

Rev. 3.00 Mar 17, 2006 page 386 of 926

REJ09B0283-0300

φ pin

Original

channel

EDREQ

Original

channel

EDRAK

Other

channel

EDREQ

Other

channel

EDRAK

Bus cycle

3 cycles

1 cycle 1 cycle

EXDMA transfer

cycle

Bus release Other channel

transfer cycle

EXDMA

read

EXDMA

write

EXDMA

read

EXDMA

write

Bus

release

Bus

release

Figure 8.38 External Request/Cycle Steal Mode/Normal Transfer Mode Contention

with Another Channel /Dual Address Mode/Low Level Sensing

External Request/Cycle Steal Mode/Block Transfer Mode: In block transfer mode, transfer of

one block is performed continuously in the same way as in burst mode. The timing of the start of

the next block transfer is the same as in normal transfer mode.

If a transfer request is generated for another channel, an EXDMA cycle for the other channel is

generated before the next block transfer.

The EDREQ pin sensing timing is different for low level sensing and falling edge sensing. The

same applies to transfer request acceptance and transfer start timing.

Figures 8. 39 to 8.44 sho w ope r a tion timing examples f or various conditions.

Section 8 EXDMA Controller

Rev. 3.00 Mar 17, 2006 page 387 of 926

REJ09B0283-0300

φ pin

EDREQ

EDRAK

ETEND

Bus cycle

EDA bit

Bus release Bus release

EXDMA

read EXDMA

write EXDMA

read EXDMA

write EXDMA

read EXDMA

write EXDMA

read EXDMA

write EXDMA

read EXDMA

write

Last transfer

in block

1-block-size transfer period Last block

Last transfer cycle

3 cycles

Repeated Bus

release

Repeated

Figure 8.39 External Request/Cycle Steal Mode/Block Transfer Mode

(No Cont ention/Dual Address Mode/Low Lev e l Sensing/B GUP = 0)

Section 8 EXDMA Controller

Rev. 3.00 Mar 17, 2006 page 388 of 926

REJ09B0283-0300

φ pin

EDREQ

EDRAK

EDACK

Bus cycle

ETEND

Bus release Bus release

Last transfer

in block

1-block-size transfer period Last block

Last transfer cycle3 cycles

EXDMA single

transfer cycle

EXDMA single

transfer cycle

EXDMA single

transfer cycle

EXDMA single

transfer cycle

EXDMA single

transfer cycle

Repeated Repeated Bus

release

Figure 8.40 External Request/Cycle Steal Mode/Block Transfer Mode

(No Cont ention/Single Addre ss Mode/Falling Edge Sensing /BGUP = 0)

Section 8 EXDMA Controller

Rev. 3.00 Mar 17, 2006 page 389 of 926

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φ pin

EDREQ

EDRAK

EDACK

Bus cycle

CPU

operation

ETEND

1-block-size transfer period 1-block-size transfer period

Last transfer

in block

Last transfer

in block 2 bus cycles

EXDMA single

transfer cycle EXDMA single

transfer cycle

External

space External

space

External

space

CPU

cycle CPU

cycle

External

space

Repeated Repeated

Figure 8.41 External Request/Cycle Steal Mode/Block Transfer Mode

(CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 0)

Section 8 EXDMA Controller

Rev. 3.00 Mar 17, 2006 page 390 of 926

REJ09B0283-0300

φ pin

EDREQ

EDRAK

Bus cycle

CPU

operation

ETEND

1-block-size transfer period

1 bus cycle

CPU

cycle CPU

cycle

External

space External

space

External

space

EXDMA

read EXDMA

write EXDMA

read EXDMA

read

EXDMA

write EXDMA

read EXDMA

write

1 bus cycle

1 bus cycle Last transfer

in block

External

space External

space

Repeated

Figure 8.42 External Request/Cycle Steal Mode/Block Transfer Mode

(CPU Cycles/Dua l Address Mode/Low Leve l Sensing/BG UP = 1)

Section 8 EXDMA Controller

Rev. 3.00 Mar 17, 2006 page 391 of 926

REJ09B0283-0300

φ pin

EDREQ

EDRAK

Bus cycle

CPU

operation

EDACK

ETEND

1-block-size transfer period

1 bus cycle

CPU

cycle CPU

cycle

External

space External

space

CPU

cycle CPU

cycle

External

space External

space

External

space

1 bus cycle

1 bus cycle Last transfer

in block

EXDMA

transfer cycle EXDMA

transfer cycle

Repeated

Figure 8.43 External Request/Cycle Steal Mode/Block Transfer Mode

(CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 1)

Section 8 EXDMA Controller

Rev. 3.00 Mar 17, 2006 page 392 of 926

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φ pin

EDREQ

EDRAK

ETEND

Bus cycle

Other

channel

EDREQ

Other

channel

EDRAK

Bus release EXDMA

read EXDMA

write EXDMA

read EXDMA

write EXDMA

read EXDMA

write EXDMA

read EXDMA

write

Last transfer

in block Last transfer

in block

1-block-size transfer period 1-block-size transfer period

Other channel

EXDMA cycle

Bus

release Bus

release RepeatedRepeated

Figure 8.44 External Request/Cycle Steal Mode/Block Transfer Mode

(Content ion with Another Cha nnel/Dual Address Mode/Lo w Level Sens ing)

Section 8 EXDMA Controller

Rev. 3.00 Mar 17, 2006 page 393 of 926

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8.4.12 Ending DMA Transfer

The operation for ending DMA transfer depends on the tran sfer end conditions. When DMA

transfer ends, the EDA bit in EDMDR changes from 1 to 0, indicating that DMA transfer has

ended.

Transfer End by 1 →

→→

→ 0 Transition of EDTCR: When the value of EDTCR changes from 1 to 0,

DMA transfer ends on the corresponding channel and the EDA bit in EDMDR is cleared to 0. If

the TCEIE bit in EDMDR is set at th is time, a transfer end interrupt request is generated by the

transfer counter and the IRF bit in EDMDR is set to 1.

In block transfer mode, DMA transfer ends when the value of bits 15 to 0 in EDTCR changes

from 1 to 0.

DMA transfer does not end if the EDTCR value has been 0 since befo re the start of transfer.

Transfer End by Repeat Area Overflow Interrupt: If an address overflows the repeat area

when a repeat area specification has been made and repeat interrupts have been enabled (with the

SARIE or DARIE bit in EDACR), a repeat area overflow interrupt is requested. DMA transfer

ends, the EDA bit in EDMDR is clear ed to 0, and the IRF bit in EDMDR is set to 1.

In dual address mode, if a repeat area overflow interrupt is requested during a read cycle, the

following write cycle processing is still ex ecuted.

In block transfer mode, if a repeat area overflow interrupt is requested during transfer of a block,

transfer continues to the end of the block. Transfer end by means of a repeat area overflow

interrupt occurs between block-size transfers.

Transfer End by 0-Write to EDA Bit in EDMDR: When 0 is written to the EDA b it in EDMDR

by the CPU, etc., tran sf er ends after completion of the DMA cycle in which transfer is in progre ss

or a transfer request was accepted.

In block transfer mode, DMA transfer halts after completion of one-block-size transfer.

The EDA bit in EDMDR is no t clear ed to 0 until all transfer processin g has ended. Up to that

point, the value of the EDA b it will b e r ead as 1.

Transfer Abort by NMI Interr upt: DMA transfer is aborted when an NMI interrupt is

generated. The EDA b it is clear ed to 0 in all channels. In external reque st m ode, DMA tr ansfer is

performed for all transfer requests for which EDRAK has been output. In dual address mode,

processing is executed for the write cycle following the read cycle.

Section 8 EXDMA Controller

Rev. 3.00 Mar 17, 2006 page 394 of 926

REJ09B0283-0300

In block transfer mode, operation is aborted even in the middle of a block-size transfer. As the

transfer is ha lted midway through a block, the BEF bit in EDMDR is set to 1 to indicate that the

block transfer was not carried out normally.

When transfer is aborted, register values are retained, and as the address registers indicate the next

transfer addresses, transfer can be resum e d by setting the EDA bit to 1 in EDMDR. I f the BEF bit

is 1 in EDMDR, transfer can be resumed from midway through a block.

Hardware Standby Mode and Reset Input: The EXDMAC is initialized in har dware standby

mode and by a reset. DMA transfer is not guaranteed in these cases.

8.4.13 Relationship between EXDMAC and Other Bus Masters

The read and write operations in a DMA transfer cycle are indivisible, and a refresh cycle, external

bus release cycle, or internal bus mastership (CPU, DTC, or DMAC) external space access cycle

never occurs between the two.

When read and write cycles occur consecutively, as in burst transfer or block transfer, a refresh or

external bus release state may be inserted after the write cycle. As the internal bus masters are of

lower priority than the EXDMAC, external space accesses by internal bu s masters are not

executed until the EXDMAC re leases the bus.

The EXDMAC releases the bus in the following cases:

1. When DMA transfer is performed in cycle steal mode

2. When switching to a different channel

3. When transfer ends in burst transfer mode

4. When transfer of one block ends in block transfer mode

5. When burst transf er or block transfer is performed with the BGUP bit in EDMDR set to 1

(however, the bus is not released between read and write cycles)

Section 8 EXDMA Controller

Rev. 3.00 Mar 17, 2006 page 395 of 926

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8.5 Interrupt Sources

EXDMAC interrupt sources are a transfer end indicated by the transfer counter, and repeat area

overflow interrupts. Table 8.4 shows the interrupt sources and their priority order.

Table 8.4 Interrupt Source s and Priority Order

Interrupt Interrupt source Interrupt Priority

EXDMTEND0 Transfer end indicated by channel 0 transfer counter

Channel 0 source address repeat area overflow

Channel 0 destination address repeat area overflow

High

EXDMTEND1 Transfer end indicated by channel 1 transfer counter

Channel 1 source address repeat area overflow

Channel 1 destination address repeat area overflow

EXDMTEND2 Transfer end indicated by channel 2 transfer counter

Channel 2 source address repeat area overflow

Channel 2 destination address repeat area overflow

EXDMTEND3 Transfer end indicated by channel 3 transfer counter

Channel 3 source address repeat area overflow

Channel 3 destination address repeat area overflow Low

Interrupt sources can be enabled or disabled by means of the EDIE bit in EDMDR for the relevant

channel, and can be sent to the interrupt controller independently. The relative priority order of the

channels is de ter m ined by the interrupt controller (see table 8.4).

Figure 8.45 shows the transfer end interrupt logic. A transfer end interrupt is generated whenever

the EDIE bit is set to 1 while the IRF bit is set to 1 in EDMDR.

Transfer end interrupt

IRF bit

EDIE bit

Figure 8.45 Transfer End Interrupt Logic

Section 8 EXDMA Controller

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Interrupt sou r ce settings are made individually with the interrupt enable bits in the re gisters for the

relevant channels. The transfer counter’s transfer end interrupt is enabled or disabled by means of

the TCEIE bit in EDMDR, the source address register repeat area overflow interrupt by means of

the SARIE bit in EDACR, and the destination addr ess register repeat area overflow interrupt by

means of the DARIE bit in EDACR. When an interrupt source occurs while the corresponding

interrup t enable bit is set to 1, the I RF b it in EDMDR is set to 1. The IRF bit is set by all interrupt

sources indiscriminately.

The transfer end in terru pt can be cleared either by clearing the IRF bit to 0 in EDMDR within the

interrupt handling routine, or by re-setting the transfer counter and address registers and then

setting the EDA bit to 1 in EDMDR to perform transfer continuation processing. An example of

the procedure for clearing the transfer end interrupt and restarting transfer is shown in figure 8.46.

Section 8 EXDMA Controller

Rev. 3.00 Mar 17, 2006 page 397 of 926

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[1] Write set values to the registers (transfer counter, address registers, etc.).

[2] Write 1 to the EDA bit in EDMDR to restart EXDMA operation. When 1 is written to the

EDA bit, the IRF bit in EDMDR is automatically cleared to 0 and the interrupt source is

cleared.

[3] The interrupt handling routine is ended with an RTE instruction, etc.

[4] Clear the IRF bit to 0 in EDMDR by first reading 1 from it, then writing 0.

[5] After the interrupt handling routine is ended with an RTE instruction, etc., interrupt

masking is cleared.

[6] Write set values to the registers (transfer counter, address registers, etc.).

[7] Write 1 to the EDA bit in EDMDR to restart EXDMA operation.

End of transfer restart

processing

Write 1 to EDA bit

Change register settings

End of interrupt handling

routine

Clear IRF bit to 0

Transfer restart after end

of interrupt handling routine

Transfer end interrupt

exception handling routine

Transfer continuation

processing

Change register settings

Write 1 to EDA bit

End of interrupt handling

routine

(RTE instruction execution)

End of transfer restart

processing

[1] [4]

[5]

[6]

[7]

[2]

[3]

Figure 8.46 Example of Procedure for Restarting Transfer on Channel in which Transfer

End Interrupt Occurred

Section 8 EXDMA Controller

Rev. 3.00 Mar 17, 2006 page 398 of 926

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8.6 Usage Notes

8.6.1 EXDMAC Register Access during Operation

Except for clearing the EDA bit to 0 in EDMDR, settings should not be changed for a channel in

operation (including the transfer standby state). Transfer must be disabled before changing a

setting for an operational channel.

8.6.2 Module Stop State

When the MSTP14 bit is set to 1 in MSTPCRH, th e EXDMAC clock stops and the EXDMAC

enters the module stop state. However, 1 cannot be written to the MSTP14 bit when any of the

EXDMAC’s channels is enabled for transfer, or when an interrupt is being requested. Before

setting the MSTP14 bit, first clear the EDA bit in EDMDR to 0, then clear the IRF or EDIE bit in

EDMDR to 0.

When the EXDMAC clock stops, EXDMAC registers can no longer be accessed. The following

EXDMAC register settings remain valid in the module stop state, and so should be changed, if

necessary, before making the module stop transition.

• ETENDE = 1 in EDMDR (ETEND pin enable)

• EDRAKE = 1 in EDMDR (EDRAK pin enable)

• AMS = 1 in EDMDR (EDACK pin enable)

8.6.3 EDREQ

EDREQEDREQ

EDREQ Pin Falling Edge Activatio n

Falling edge sensing on the EDREQ pin is performed in synchronization with EXDMAC internal

operations, as indicated below.

[1] Activation request standby state: Waits for low level sensing on EDREQ pin, then goes to [2].

[2] Transfer standby state: Waits for EXDMAC data transfer to become possible, then goes to [3].

[3] Activation request disabled state: Waits for high level sensing on EDREQ pin, then goes to [1].

After EXDMAC transfer is enabled, the EXDMAC goes to state [1], so low level sensing is used

for the in itial activation after transfer is enab led.

Section 8 EXDMA Controller

Rev. 3.00 Mar 17, 2006 page 399 of 926

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8.6.4 Activation Source Acceptance

At the start of activatio n source acceptance, low level sensing is used for both falling edge sensing

and low level sensing on the EDREQ pin. Therefore, a request is accepted in the case of a low

level at the EDREQ pin that o ccurs bef ore ex ecution of the EDMDR write for settin g the transfer-

enabled state.

When the EXDMAC is activated, make sure, if necessary, that a low level does not remain at the

EDREQ pin from the previous end of transfer, etc.

8.6.5 Enabling Interrupt Requests when IRF = 1 in EDMDR

When transf er is started while the IRF bit is set to 1 in EDMDR, if the EDI E bit is set to 1 in

EDMDR together with the EDA bit in EDMDR, enabling interrupt requests, an inter r upt will b e

requested since EDIE = 1 and IRF = 1. To preven t the occurrence of an erroneous interrupt request

when transfer starts, ensure that the IRF bit is clear ed to 0 before the EDIE bit is set to 1 .

8.6.6 ETEND

ETENDETEND

ETEND Pin and CBR Refresh Cycle

If the last EXDMAC transfer cycle and a CBR refresh cycle occur simultaneously, note that

although the CBR refresh and the last transfer cycle may be executed consecutively, ETEND may

also go low in this case for the refresh cycle.

Section 8 EXDMA Controller

Rev. 3.00 Mar 17, 2006 page 400 of 926

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Section 9 Data Transfer Controller (DTC)

Rev. 3.00 Mar 17, 2006 page 401 of 926

REJ09B0283-0300

Section 9 Data Transfer Cont roller (DTC)

This LSI includ es a data transfer controller (DTC) . The DTC can be activated by an interrupt or

software, to transfer data.

Figure 9.1 shows a block diagram of th e DTC. The DTC’s register information is stored in the on-

chip RAM. When the DTC is used, the RAME bit in SYSCR must be set to 1. A 32-bit bus

connects the DTC to the on-chip RAM (1 kbyte), en abling 32-bit/1-state reading and wr iting of

the DTC register information.

9.1 Features

• Transfer possible over any number of channels

• Three transfer modes

Normal, repeat, and block tran sfer modes available

• One activation source can trigger a number of data transfers (chain transfer)

• Direct specification of 16-Mbyte address space possible

• Activation by software is possible

• Transfer can be set in byte or word units

• A CPU interrupt can be requested for the interrupt that activated the DTC

• Module stop mode can be set

DTCH804A_010020020400

Section 9 Data Transfer Controller (DTC)

Rev. 3.00 Mar 17, 2006 page 402 of 926

REJ09B0283-0300

Interrupt

request

Interrupt controller DTC

Internal address bus

DTC activation

request

Control logic

MRA MRB

CRA

CRB

DAR

SAR

CPU interrupt

request

On-chip

RAM

Internal data bus

Legend:

MRA, MRB

CRA, CRB

SAR

DAR

DTCERA to DTCERG

DTVECR

DTCERA

DTCERG

DTVECR

: DTC mode registers A and B

: DTC transfer count registers A and B

: DTC source address register

: DTC destination address register

: DTC enable registers A to G

: DTC vector register

Figure 9.1 Block Diagram of DTC

9.2 Register Descriptions

DTC has the following registers.

• DTC mode register A (MRA)

• DTC mode register B (MRB)

• DTC source address register (SAR)

• DTC destination address register (DAR)

• DTC transfer count register A (CRA)

• DTC transfer count register B (CRB)

These six registers cannot be directly accessed from the CPU. When activated, the DTC reads a set

of register info rmation that is stored in an on-chip RAM to the co rresponding DTC registers and

transfers data. After the data transfer, it writes a set of updated register information back to the

RAM.

• DTC enable registers A to G (DTCERA to DTCERG)

• DTC vector register (DTVECR)

Section 9 Data Transfer Controller (DTC)

Rev. 3.00 Mar 17, 2006 page 403 of 926

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9.2.1 DTC Mode Register A (MRA)

MRA selects the DTC operating mode.

Bit Bit Name Initial Value R/W Description

6SM1

SM0 Undefined

Undefined —

—Source Address Mode 1 and 0

These bits specify an SAR operation after a data

transfer.

0x: SAR is fixed

10: SAR is incremented after a transfer

(by +1 when Sz = 0; by +2 when Sz = 1)

11: SAR is decremented after a transfer

(by –1 w hen Sz = 0; by –2 wh en Sz = 1)

4DM1

DM0 Undefined

Undefined —

—Destination Address Mode 1 and 0

These bits specify a DAR operation after a data

transfer.

0x: DAR is fixed

10: DAR is incremented after a transfer

(by +1 when Sz = 0; by +2 when Sz = 1)

11: DAR is decremented after a transfer

(by –1 w hen Sz = 0; by –2 wh en Sz = 1)

2MD1

MD0 Undefined

Undefined —

—DTC Mode

These bits specify the DTC transfer mode.

00: Normal mode

01: Repeat mode

10: Block transfer mode

11: Setting prohibited

1 DTS Undefined — DTC Transfer Mode Select

Specifies whether the source side or the destination

side is set to be a repeat area or block area, in

repeat mode or block transfer mode.

0: Destination side is repeat area or block area

1: Source side is repeat area or block area

Section 9 Data Transfer Controller (DTC)

Rev. 3.00 Mar 17, 2006 page 404 of 926

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Bit Bit Name Initial Value R/W Description

0 Sz Undefined — DTC Data Transfer Size

Specifies the size of data to be transferred.

0: Byte-size transfer

1: Word-size transfer

Legend:

X: Don’t care

9.2.2 DTC Mode Register B (MRB)

MRB selects the DTC operating mode.

Bit Bit Name Initial Value R/W Description

7 CHNE Undefined — DTC Chain Transfer Enable

When this bit is set to 1, a chain transfer will be

performed. For de tails, refer to section 9.5.4, Chain

Transfer.

In data transfer with CHNE set to 1, determination of

the end of the specified number of transfers, clearing

of the activation source flag, and clearing of DTCER

is not performed.

6 DISEL Undefined — DTC Interrupt Select

When this bit is set to 1, a CPU interrupt request is

generated every time after a data transfer ends.

When this bit is set to 0, a CPU interrupt request is

generated at the time when the specified number of

data transfer ends.

5 CHNS Undefined — DTC Chain Transfer Selec t

Specifies the chain transfer condition.

0: Chain transfer every time

1: Chain transfer only when transfer counter = 0

— Undefined — Reserved

These bits have no effect on DTC operation, and

should always be written with 0.

Section 9 Data Transfer Controller (DTC)

Rev. 3.00 Mar 17, 2006 page 405 of 926

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9.2.3 DTC Source Address Register (SAR)

SAR is a 24-bit register that designates the source address of data to be transferred by the DTC.

For word-size transfer, specify an even source address.

9.2.4 DTC Destination Addres s Register (DAR)

DAR is a 24-bit register that designates the destination address of data to be transferred by the

DTC. For word-size transfer, specify an even destination address.

9.2.5 DTC Transfer Count Register A (CRA)

CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.

In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65,536). It is

decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.

In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits

(CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL

functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is

transferred, and the contents of CRAH are sent when the count reaches H'00.

9.2.6 DTC Transfer Count Register B (CRB)

CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in

block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1

every time data is transferred, and transfer ends when the count reaches H'0000. This register is

not available in normal and repeat modes.

9.2.7 DTC Enable Registers A to G (DTCERA to DTCERG)

DTCER which is comprised of seven registers, DTCERA to DTCERG, is a register that specifies

DTC activation interrupt sources. The correspondence between interrupt sources and DTCE bits is

shown in table 9.1. For DTCE bit setting, use bit manipulation instructions such as BSET and

BCLR fo r r eading and writing. If all inter rupts are masked, multip le activation sources can b e set

at one time (only at the initial setting) by writin g data after executing a dummy read on the

relevant register.

Section 9 Data Transfer Controller (DTC)

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Bit Bit Name Initial Value R/W Description

DTCE7

DTCE6

DTCE5

DTCE4

DTCE3

DTCE2

DTCE1

DTCE0

R/W

DTC Activation Enable

Setting this bit to 1 specifies a relevant interrupt

source to a DTC activation source.

[Clearing cond iti ons ]

• When the DISEL bit is 1 and the data transfer has

ended

• When the specified number of transfers have

ended

These bits are not cleared when the DISEL bit is 0

and the specified number of transfers have not

ended

9.2.8 DTC Vector Register (DTVECR)

DTVECR enables or disables DTC activation by software, and sets a vector number for the

software activation interrupt.

Bit Bit Name Initial Value R/W Description

7 SWDTE 0 R/W DTC Software Activation Enable

Setting this bit to 1 activates DTC. Only 1 can be

written to this bit.

[Clearing cond iti ons ]

• When the DISEL bit is 0 and the specified

number of transfers have not ended

• When 0 is written to the DISEL bit after a

software-activated data transfer end interrupt

(SWDTEND) request has been sent to the CPU.

When the DISEL bit is 1 and data transfer has ended

or when the specified num ber of transf ers hav e

ended, this bit will not be cleared.

DTVEC6

DTVEC5

DTVEC4

DTVEC3

DTVEC2

DTVEC1

DTVEC0

R/W

DTC Software Activation Vectors 6 to 0

These bits specify a vector number for DTC software

activation.

The vector address is expressed as H'0400 + (vector

number × 2). For ex ample, when DTVEC6 to

DTVEC0 = H'10, the vector address is H'0420. When

the bit SWDTE is 0, these bits can be written.

Section 9 Data Transfer Controller (DTC)

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9.3 Activation Sources

The DTC operates wh en activated by an interrupt or by a write to DTVECR b y software. An

interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER

bit. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the

activation source or corresponding DTCER bit is cleared. The activation source flag, in the case of

RXI0, for example, is the RDRF flag of SCI_0.

When an interrupt has been designated a DTC activation source, existing CPU mask level and

interrupt controller priorities have no effect. If there is more than one activation source at the same

time, the DTC operates in accordance with the default priorities.

Figure 9.2 shows a block diagram of activation source control. For details see section 5, Interrupt

Controller.

CPU

DTC

DTCER

Source flag cleared

On-chip

supporting

module

IRQ interrupt Interrupt

request

Clear

controller

Clear request

Interrupt controller

Selection circuit

Interrupt mask

Select

DTVECR

Figure 9.2 Block Diagram of DTC Activation Source Control

Section 9 Data Transfer Controller (DTC)

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9.4 Location of Register Information and DTC Vector Table

Locate the register informatio n in the on-chip RAM (ad dresses: H'FFBC00 to H'FFBFFF).

Locating the register information in address space is shown in figure 9.3. Locate the MRA, SAR,

MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register

information. In the case of chain transfer, register information should be located in consecutive

areas as shown in figure 9.3 and the register information start address should be located at the

corresponding vector address to the activation source. The DTC reads the start address of the

When the DTC is activated by software, the vector address is obtained from: H'0400 +

(DTVECR[6:0] × 2). For example, if DTVECR is H'10, the vector address is H'0420.

The configuration of the vector address is the same in both normal* and advanced modes, a 2-byte

unit being used in both cases. These two bytes specify the lower bits of the register information

start address.

Note: Not available in this LSI.

MRAStart address of

for second transfer

in case of chain

transfer

Chain transfer

Lower addresses

Four bytes

0123

SAR

MRB DAR

CRA CRB

MRA SAR

MRB DAR

CRA CRB

Figure 9.3 Correspondence between DTC Vector Address and Register Information

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Table 9.1 Interrupt Sources, DTC Vector Addresse s, and Corresponding DTCEs

Origin of

Activation

Source Activation

Source Vector

Number DTC

Vector Address DTCE*Priority

Software Write to DTVECR DTVECR H'0400 + (DTVECR

[6:0] × 2) —High

External pin IRQ0 16 H'0420 DTCEA7

IRQ1 17 H'0422 DTCEA6

IRQ2 18 H'0424 DTCEA5

IRQ3 19 H'0426 DTCEA4

IRQ4 20 H'0428 DTCEA3

IRQ5 21 H'042A DTCEA2

IRQ6 22 H'042C DTCEA1

IRQ7 23 H'042E DTCEA0

IRQ8 24 H'0430 DTCEB7

IRQ9 25 H'0432 DTCEB6

IRQ10 26 H'0434 DTCEB5

IRQ11 17 H'0436 DTCEB4

IRQ12 18 H'0438 DTCEB3

IRQ13 19 H'043A DTCEB2

IRQ14 30 H'043C DTCEB1

IRQ15 31 H'043E DTCEB0

A/D ADI 38 H'044C DTCEC6

TPU_0 TGI0A 40 H'0450 DTCEC5

TGI0B 41 H'0452 DTCEC4

TGI0C 42 H'0454 DTCEC3

TGI0D 43 H'0456 DTCEC2

TPU_1 TGI1A 48 H'0460 DTCEC1

TGI1B 49 H'0462 DTCEC0

TPU_2 TGI2A 52 H'0468 DTCED7

TGI2B 53 H'046A DTCED6

TPU_3 TGI3A 56 H'0470 DTCED5

TGI3B 57 H'0472 DTCED4

TGI3C 58 H'0474 DTCED3

TGI3D 59 H'0476 DTCED2 Low

Section 9 Data Transfer Controller (DTC)

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Origin of

Activation

Source Activation

Source Vector

Number DTC

Vector Address DTCE*Priority

TPU_4 TGI4A 64 H'0480 DTCED1 High

TGI4B 65 H'0482 DTCED0

TPU_5 TGI5A 68 H'0488 DTCEE7

TGI5B 69 H'048A DTCEE6

TMR_0 CMIA0 72 H'0490 DTCEE3

CMIB0 73 H'0492 DTCEE2

TMR_1 CMIA1 76 H'0498 DTCEE1

CMIB1 77 H'049A DTCEE0

DMAC DMTEND0A 80 H'04A0 DTCEF7

DMTEND0B 81 H'04A2 DTCEF6

DMTEND1A 82 H'04A4 DTCEF5

DMTEND1B 83 H'04A6 DTCEF4

SCI_0 RXI0 89 H'04B2 DTCEF3

TXI0 90 H'04B4 DTCEF2

SCI_1 RXI1 93 H'04BA DTCEF1

TXI1 94 H'04BC DTCEF0

SCI_2 RXI2 97 H'04C2 DTCEG7

TXI2 98 H'04C4 DTCEG6 Low

Note: *DTCE bits with no corresponding interrupt are reserved, and should be written with 0.

When clearing the software standby state or all-module-clocks-stop mode with an

interrupt, write 0 to the corresponding DTCE bit.

9.5 Operation

The DTC stores register information in the on-chip RAM. When activated, the DTC reads register

inform ation that is already stor ed in the on-chip RAM and transfers data on the basis o f that

chip RAM. Pre-storage of register information in the on-chip RAM makes it possible to transfer

data over any required number of channels. There are three transfer modes: normal mode, repeat

mode, and block transfer mode. Setting the CHNE bit to 1 makes it possible to perform a number

of transfers with a single activation (chain transfer). A setting can also be made to have chain

transfer performed only when the transfer counter value is 0. This enables DTC re-setting to be

performed by the DTC itself.

Section 9 Data Transfer Controller (DTC)

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The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the

transfer destination address. After each transfer, SAR and DAR are independently incremented,

decremented, or left fixed.

Figure 9.4 shows a flowchart of DTC operation, and table 9.2 summarizes the chain transfer

conditions (combinations fo r performing the second and third transfers are omitted).

Start

Read DTC vector

Next transfer

Read register information

Data transfer

Write register information

Clear activation flag

CHNE = 1?

End

Yes

Transfer counter = 0

or DISEL = 1?

Clear DTCER

Interrupt exception

handling

CHNS = 0?

DISEL = 1?

Transfer

counter = 0?

Figure 9.4 Flowchart of DTC Operation

Section 9 Data Transfer Controller (DTC)

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Table 9.2 Chain Tran sfer Conditions

1st Transfer 2nd Transfer

CHNE CHNS DISEL CR CHNE CHNS DISEL CR DTC Transfer

0 — 0Not 0————Ends at 1st transfer

0 — 00 ————Ends at 1st transfer

0—1— ————Interrupt request to CPU

10—— 0 — 0 Not 0 Ends at 2nd transfer

0 — 0 0 Ends at 2nd transfer

0 — 1 — Interrupt request to CPU

110Not 0————Ends at 1st transfer

11—00—0 Not 0 Ends at 2nd transfer

0 — 0 0 Ends at 2nd transfer

0 — 1 — Interrupt request to CPU

111Not 0————Ends at 1st transfer

Interrupt request to CPU

9.5.1 Normal Mode

In normal mode, one operation transfers one byte or one word of data. Table 9.3 lists the register

function in normal mode. From 1 to 65,536 transfers can be specified. Once th e specified number

of transfers has ended, a CPU interrupt can be requested.

Table 9.3 Register Function in Normal Mode

Name Abbreviation Function

DTC source address register SAR Designates source addres s

DTC destination address register DAR Designates destination address

DTC transfer count register A CRA Designates transfer count

DTC transfer count register B CRB Not used

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SAR DAR

Transfer

Figure 9.5 Memory Mapping in Normal Mode

9.5.2 Repeat Mode

In repeat mode, one operation transfers on e byte or one word of data. Table 9.4 lists the register

function in repeat mode. From 1 to 256 transfers can be specified. Once the specified number of

transfers ha s ended, the initial state of the transfer counter an d the addr ess register specified as the

repeat area is restored, and transfer is repeated. In repeat mode the transfer counter value does not

reach H'00, and therefore CPU interrupts canno t be requested when DISEL = 0.

Table 9.4 Register Function in Repeat Mode

Name Abbreviation Function

DTC source address register SAR Designates source address

DTC destination address register DAR Designates destination address

DTC transfer count register AH CRAH Holds number of transfers

DTC transfer count register AL CRAL Designates transfer count

DTC transfer count register B CRB Not used

Section 9 Data Transfer Controller (DTC)

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SAR

DAR

SAR

Repeat area

Transfer

Figure 9.6 Memory Mapping in Repeat Mode

9.5.3 Block Transfer Mode

In block transfer mode, one operation transfers one block of data. Either the transfer source or the

transfer destination is designated as a block area. Table 9.5 lists the register function in block

transfer mode.

The block size is 1 to 2 56. When the transfer of on e block ends, the initial state of the block size

counter and the address register specified as the block area is restored. The other address register

is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be sp ecified. Once

the specified number of transfers has ended, a CPU interrupt is requested.

Table 9.5 Register Function in Block Transfer Mode

Name Abbreviation Function

DTC source address register SAR Designates source address

DTC destination address register DAR Designates destination address

DTC transfer count regi ster AH CRAH Holds block size

DTC transfer count register AL CRAL Designates block size count

DTC transfer count register B CRB Designates transfer count

Section 9 Data Transfer Controller (DTC)

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First block

Transfer Block area

Nth block

DAR

SAR

DAR

Figure 9.7 Memory Mapping in Block Transfer Mode

9.5.4 Chain Transfer

Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in

response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data

transfers, can be set independently.

Figure 9.8 shows the operation of chain transfer. When activated, the DTC reads the register

information start address stored at the vector address, and then reads the first register information

at that start address. The CHNE bit in MRB is checked after the end of data transfer, if the value is

1, the next register information, which is located consecutively, is read and transfer is performed.

This operation is repeated until the end of d a ta tr ansfer of re g ister information with CHNE = 0. It

is also possible, by setting both the CHNE bit and CHNS bit to 1, to specify execution of chain

transfer only when the transfer counter value is 0.

In the case of transf er with CHNE set to 1, an interrupt r equest to the CPU is not generated at the

end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt

source flag for the activation source is not affected.

Section 9 Data Transfer Controller (DTC)

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DTC vector

address

CHNE=1

CHNE=0

start address

Source

Destination

Source

Destination

Figure 9.8 Operation of Chain Transfer

9.5.5 Interrupt Source s

An interrupt request is issued to the CPU when the DTC finishes the specified number of data

transfers, or a data transfer for which the DISEL b it was set to 1. In the case of interrupt activation,

the interru pt set as the activation sour ce is generated. These interrupts to the CPU are subject to

CPU mask level an d interrupt controller priority lev e l contr ol.

In the case of activation by software, a software activated data transfer end interrupt (SWDTEND)

is generated.

When the DISEL bit is 1 and one data transfer has ended, or the specified number of transfers has

ended, after data tr ansfer ends, the SWDTE bit is held at 1 and an SWDTEND interrupt is

generated. The interrupt handling routine should clear the SWDTE bit to 0.

When the DTC is activated by software, an SWDTEND interrupt is not generated during a data

transfer wait or dur in g data transfer even if the SWDTE bit is set to 1.

Section 9 Data Transfer Controller (DTC)

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9.5.6 Operation Timing

DTC activation

request

DTC

request

Address

Vector read

Read Write

Data transfer

Transfer

information write

Transfer

information read

Figure 9.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode)

DTC activation

request

DTC

request

Address

Vector read

Read Write Read Write

Data transfer

Transfer

information write

Transfer

information read

Figure 9.10 DTC Operation Timing (Example of Block Transfer Mode,

with Block Size of 2)

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DTC activation

request

DTC

request

Address

Vector read

Read Write Read Write

Data transfer Data transfer

Transfer

information

write

Transfer

information write

Transfer

information read Transfer

information

read

Figure 9.11 DTC Operation Timing (Example of Chain Transfer)

9.5.7 Number of DTC Execution States

Table 9.6 lists execution status for a single DTC data transfer, and table 9.7 shows the number of

states required for each execution status.

Table 9.6 DTC Execution Stat us

Mode Vector Read

Read/Write

JData Read

KData Write

Internal

Operations

Normal1 6 113

Repeat 1 6 1 1 3

Block transfer 1 6 N N 3

Legend:

N: Block size (initial setting of CRAH and CRAL)

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Table 9.7 Number of States Required for Each Execution Status

Object to be Accessed

On-

Chip

RAM

On-

Chip

ROM On-Chip I/O

Registers External Devices

Bus width 32168 168 8 1616

Access states 11222323

Execution Vector read SI— 1 ——46+2m23+m

status Register informatio n

read/write SJ

1———————

Byte data read SK112223+m23+m

Word data read SK114246+2m23+m

Byte data write SL112223+m23+m

Word data write SL114246+2m23+m

Internal operation SM11111111

The number of execution states is calculated from the formula below. No te that Σ means the sum

of all transfer s activated by one activation even t ( th e number in which the CHNE bit is set to 1,

plus 1).

Number of execution states = I · SI + Σ (J · SJ + K · SK + L · SL) + M · SM

For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,

and data is tran sferred from the on-chip ROM to an internal I/O register, the time required for the

DTC operation is 13 states. The time from activation to the end of the data write is 10 states.

Section 9 Data Transfer Controller (DTC)

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9.6 Procedures for Using DTC

9.6.1 Activation by Interrupt

The procedure for using the DTC with interrupt activation is as follows:

1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM.

2. Set the start address of the register information in the DTC vector address.

3. Set the corresponding bit in DTCER to 1.

4. Set the enab le b its for the interrupt sources to be used as the activation sour ces to 1. The DTC

is activated when an interrupt used as an activation source is generated.

5. After the end of one data transfer, or after the specified number of data transfers have ended,

the DTCE bit is cleared to 0 and a CPU interrupt is r equested. If the DTC is to contin u e

transferrin g data, set the DTCE bit to 1.

9.6.2 Activation by Software

The procedu r e for using the DTC with softwar e activation is as follows:

1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM.

2. Set the start address of the register information in the DTC vector address.

3. Check th at the SWDTE bit is 0.

4. Write 1 to SWDTE bit and the vector number to DTVECR.

5. Check th e vector number written to DTVECR.

6. After the end of one data transfer, if the DISEL bit is 0 and a CPU interrupt is not re quested,

the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE b it

to 1. When the DISEL bit is 1, or after the specified number of data transfers have ended, the

SWDTE bit is held at 1 and a CPU interru pt is requested.

Section 9 Data Transfer Controller (DTC)

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9.7 Examples of Use of the DTC

9.7.1 Normal Mode

An example is shown in which the DTC is used to receive 128 bytes of data via the SCI.

1. Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 =

1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have

any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the

SCI RDR address in SAR, the start addr ess of the RAM area where the d a ta will be received in

DAR, and 128 (H'0080) in CRA. CRB can be set to any value.

2. Set the start address of the register information at the DTC vector address.

3. Set the corresponding bit in DTCER to 1.

4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception

complete (RXI) interrupt. Since the generation of a receive error during the SCI reception

operation will disable subsequent reception, the CPU should be enabled to accept receive error

interrupts.

5. Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an

RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR

to RAM by the DTC. DAR is incremented and CRA is decremented. Th e RDRF flag is

automatically cleared to 0.

6. When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the

DTCE bit is cleared to 0 , and an RXI interrupt request is sent to the CPU. The interrupt

handling routine should perform wrap-up processing.

Section 9 Data Transfer Controller (DTC)

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9.7.2 Chain Transfer

An example of DTC chain transfer is shown in which pulse output is performed using the PPG.

Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle

updating. Repeat mode transfer to the PPG’s NDR is performed in the first half of the chain

transfer, and normal mode transfer to the TPU’s TGR in the second half. This is because clearing

of the activation source and interrupt generation at the end of the specified number of tran sfers are

restricted to the second half of the chain transfer (transfer when CHNE = 0).

1. Perform settings for transfer to the PPG’s NDR. Set MRA to so urce address in crementing

(SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), repeat mode (MD1 = 0,

MD0 = 1), and word size (Sz = 1). Set the source side as a repeat area (DTS = 1). Set MRB to

chain mode (CHNE = 1, DISEL = 0). Set the data table start address in SAR, the NDRH

address in DAR, and the data table size in CRAH and CRAL. CRB can be set to any value.

2. Perfor m settings for transfer to the TPU’s TGR. Set MRA to source address incrementing

(SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), normal mode (MD1 = MD0

= 0), and word size (Sz = 1). Set the data table start address in SAR, the TGRA address in

DAR, and the data table size in CRA. CRB can be set to any value.

3. Locate the TPU transfer register information consecutively after the NDR transfer register

information.

4. Set the start address of the NDR transfer register information to the DTC vector address.

5. Set the bit co rresponding to TGI A in DTCER to 1.

6. Set TGRA as an output compare register (output disabled) with TIOR, and enable the TGIA

interrupt with TIER.

7. Set the initial o utput value in PODR, and the next output value in NDR. Set bits in DDR and

NDER for which output is to be performed to 1. Using PCR, select the TPU compare match to

be used as the output trigger.

8. Set the CST bit in TSTR to 1, and start the TCNT count operation.

9. Each time a TGRA compare match occurs, the next output value is transferred to NDR and the

set value of the next output trigger period is transferred to TGRA. The activation source TGFA

flag is cleared.

10.When the specified number of transfers are completed (the TPU transfer CRA value is 0), the

TGFA flag is held at 1, the DTCE bit is cleared to 0, and a TGIA interrupt req uest is sent to the

CPU. Termination processing should be performed in the interrupt handling routine.

Section 9 Data Transfer Controller (DTC)

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9.7.3 Chain Transfer when Counter = 0

By executing a second data transfer, and performing re-setting of the first data transfer, only when

the counter value is 0, it is possible to perform 256 or more repeat transfers.

An example is shown in which a 128-kbyte input buffer is configured. The input buffer is assumed

to have been set to start at lower address H'0000. Figure 9.12 shows the chain transfer when the

counter value is 0.

1. For the first transfer, set the normal mode for input data. Set fixed transfer source address

(G/A, etc.), CRA = H'0000 (65,536 times), and CHNE = 1, CHNS = 1, and DISEL = 0.

2. Prepare the upper 8-bit addresses of the start addresses for each of the 65,536 transfer start

addresses for the first data transfer in a separate area (in ROM, etc.). For example, if the input

buffer comprises H'200000 to H'21FFFF, prepare H'21 and H'20.

3. For the second transfer, set repeat mode (with the source side as the repeat area) for re-setting

the transfer destination addr ess f or the first data transfer. Use th e upper 8 bits of DAR in the

first register information area as the transfer destination. Set CHNE = DISEL = 0. If the above

input buffer is specified as H'200000 to H'21FFFF, set the transfer counter to 2.

4. Execute the first data transfer 65,536 times by means of interrupts. When the transfer counter

for the first data transfer reaches 0, the second data transfer is started. Set the upper 8 bits of

the transfer source address for the first data transfer to H'21. The lower 16 bits of the transfer

destination address of the first data transfer and th e transfer counter are H'0000.

5. Next, execute the first data transfer the 65,536 times specified for the first data transfer by

means of interrupts. When the transfer counter for the first data transfer reaches 0, the second

data transfer is star ted. Set the upper 8 bits of the transfer source address for the first data

transfer to H'20. The lower 16 bits of the transfer destination address of the first data transfer

and the transfer counter are H'0000.

6. Steps 4 and 5 are repeated endlessly. As repeat mode is specified for the second data transfer,

an interrupt request is not sent to the CPU.

Section 9 Data Transfer Controller (DTC)

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First data

transfer register

information

Second data

transfer register

information

Chain transfer

(counter = 0) Upper 8 bits

of DAR

Input buffer

Input circuit

Figure 9.12 Chain Transfer when Counter = 0

Section 9 Data Transfer Controller (DTC)

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9.7.4 Software Activation

An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means

of software activation. The transfer source address is H'1000 and the destination address is

H'2000. The vector number is H'60, so the vector address is H'04C0.

1. Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination

address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz =

0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE =

0). Set the transfer source address (H'1000) in SAR, the destination address (H'2000) in DAR,

and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB.

2. Set the start address of the register information at the DTC vector address (H'04C0).

3. Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated

by software.

4. Write 1 to th e SWDTE bit and the vector number (H'60 ) to DTVECR. Th e wr ite data is H'E0.

5. Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this

indicates that the write failed. This is presumably because an interrupt occurred between steps

3 and 4 and led to a different software activation. To activate this transfer, go back to step 3.

6. If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred.

7. After the tr ansfer, an SWDTEND interrup t o c curs. The in terru pt handling routine should clear

the SWDTE bit to 0 and perform other wrap-up processing.

Section 9 Data Transfer Controller (DTC)

Rev. 3.00 Mar 17, 2006 page 426 of 926

REJ09B0283-0300

9.8 Usage Notes

9.8.1 Module Stop Mode Setting

DTC operation can be disabled or enabled using the m odule stop control register. The initial

setting is for DTC op e ration to be enabled. Register access is disab led by setting module sto p

mode. Module stop mode cannot be set while the DTC is activated. For details, refer to section 22,

Power-Down Modes.

9.8.2 On-Chip RAM

The MRA , MRB, SA R, DAR, CRA, an d CRB regi ste rs are all located in on-chip RAM. When the

DTC is used, the RAME bit in SYSCR must not be cleared to 0.

9.8.3 DTCE Bit Setting

For DTCE bit setting, use bit manipulation instructio ns such as BSET and BCLR. I f all interrupts

are disabled, multiple activation sources can be set at one time (only at the initial settin g) by

writing data after executing a dummy read on the relevant register.

• DMAC Transfer End Interrupt

When DTC transfer is activated by a DMAC transfer end interrupt, regardless of the transfer

counter and DISEL bit, the DMAC’s DTE bit is not subject to DTC control, and the write data

has priority. Consequently, an interrupt request may not be sent to the CPU when the DTC

transfer counter reaches 0.

• Chain Transfer

When chain transfer is used, clearing of the activation source or DTCER is performed when

the last of the chain of data transfers is executed. SCI and high-speed A/D converter

interrupt/activation sources, on the o ther hand, are cleared when the DTC reads o r writes to the

prescribed register.

Therefore, when the DTC is activated by an interrupt or activation so u r ce, if a read/write of the

relevant reg ister is not included in the last chained data transfer, the interrupt or activatio n

source will be r e tain ed.

Section 10 I/O Ports

Rev. 3.00 Mar 17, 2006 page 427 of 926

REJ09B0283-0300

Section 10 I/O Ports

Table 10.1 summarizes the po rt functions. The pins of each port also have other functions such as

input/output or external interrupt input pins of on-chip peripheral modules. Each I/O port includes

a data direction register (DDR) that contro ls input/output, a data register (DR) that stores output

data, and a port register (PORT) used to read the pin states. The input-only ports do not have a DR

or DDR register.

Ports A to E have a built-in pull-up MOS function and a input pull-up MOS control register (PCR)

to control the on/off state of input pull-up MOS.

Ports 3 and A include an open-drain contro l register (ODR) that controls the on/off state of the

output buffer PMOS.

Ports 1 to 3, 5 (P50 to P53), and 6 to 8 can drive a single TTL load and 30 pF capacitive load.

Ports A to H can drive a single TTL load and 50 pF capacitive load.

All the I/O ports can drive a Darlington transistor when outputting data.

Ports 1 and 2 are Schmitt-trigger ed inputs. Ports 5, 6, F ( PF1, PF2), and H (PH2 , PH3) are

Schmitt-triggered inputs when used as the IRQ input.

Section 10 I/O Ports

Rev. 3.00 Mar 17, 2006 page 428 of 926

REJ09B0283-0300

Table 10.1 Port Functions

Modes 3*1, 7

Port Description Modes 1

and 5 Modes 2

and 6 Mode 4 EXPE = 1 EXPE = 0

Input/

Output

Type

P17/PO15/TIOCB2/TCLKD/

EDRAK3 P17/PO15/TIOCB2/

TCLKD/EDRAK3 P17/PO15/TIOCB2/

TCLKD

P16/PO14/TIOCA2/EDRAK2 P16/PO14/TIOCA2/

EDRAK2 P16/PO14/TIOCA2

Port

1General I/O port

also functioning

as PPG outputs,

TPU I/O s, an d

EXDMAC outputs

P15/PO13/TIOCB1/TCLKC

P14/PO12/TIOCA1

P13/PO11/TIOCD0/TCLKB

P12/PO10/TIOCC0/TCLKA

P11/PO9/TIOCB0

P10/PO8/TIOCA0

Schmitt-

triggered

input

P27/PO7/TIOCB5/EDRAK1/

(IRQ15)P27/PO7/TIOCB5/

EDRAK1/(IRQ15)P27/PO7/TIOCB5/

(IRQ15)

P26/PO6/TIOCA5/EDRAK0/

(IRQ14)P26/PO6/TIOCA5/

EDRAK0/(IRQ14)P26/PO6/TIOCA5/

(IRQ14)

Port

2General I/O port

also functioning

as PPG outputs,

TPU I/O s,

interrupt i nputs,

and EXDMAC

outputs

P25/PO5/TIOCB4/(IRQ13)

P24/PO4/TIOCA4/(IRQ12)

P23/PO3/TIOCD3/(IRQ11)

P22/PO2/TIOCC3/(IRQ10)

P21/PO1/TIOCB3/(IRQ9)

P20/PO0/TIOCA3/(IRQ8)

Schmitt-

triggered

input

P35/SCK1/(OE)/CKE*2P35/SCK1/(OE)/

CKE*2P35/SCK1Port

3General I/O port

also functioning

as SCI I/O s P34/SCK0

P33/RxD1

P32/RxD0/IrRxD

P31/TxD1

P30/TxD0/IrTxD

Open-

drain

output

capability

Section 10 I/O Ports

Rev. 3.00 Mar 17, 2006 page 429 of 926

REJ09B0283-0300

Modes 3*1, 7

Port Description Modes 1

and 5 Modes 2

and 6 Mode 4 EXPE = 1 EXPE = 0

Input/

Output

Type

Port

4General I/O port

also functioning

as A/D converter

analog inputs and

D/A converter

analog outputs

P47/AN7/DA1

P46/AN6/DA0

P45/AN5

P44/AN4

P43/AN3

P42/AN2

P41/AN1

P40/AN0

Port

5General I/O port

also functioning

as interrupt i nputs,

A/D converter

analog inputs, and

D/A converter

analog outputs

P57/AN15/DA3/IRQ7

P56/AN14/DA2/IRQ6

P55/AN13/IRQ5

P54/AN12/IRQ4

General I/O port

also functioning

as interrupt i nputs,

A/D converter

analog inputs, and

SCI I/O s

P53/ADTRG/IRQ3

P52/SCK2/IRQ2

P51/RxD2/IRQ1

P50/TxD2/IRQ0

Schmitt-

triggered

input

when

used as

input

Port

6General I/O port

also functioning

as interrupt i nputs,

TMR I/O s, an d

DMAC I/Os

P65/TMO1/DACK1/IRQ13

P64/TMO0/DACK0/IRQ12

P63/TMCI1/TEND1/IRQ11

P62/TMCI0/TEND0/IRQ10

P61/TMRI1/DREQ1/IRQ9

P60/TMRI0/DREQ0/IRQ8

Schmitt-

triggered

input

when

used as

input

Port

7General I/O port

also functioning

as DMAC I/Os

and EXDMAC

I/Os

P75/EDACK1/(DACK1)

P74/EDACK0/(DACK0)

P73/ETEND1/(TEND1)

P72/ETEND0/(TEND0)

P71/EDREQ1/(DREQ1)

P70/EDREQ0/(DREQ0)

P75/EDACK1/

(DACK1)

P74/EDACK0/

(DACK0)

P73/ETEND1/

(TEND1)

P72/ETEND0/

(TEND0)

P71/EDREQ1/

(DREQ1)

P70/EDREQ0/

(DREQ0)

P75/(DACK1)

P74/(DACK0)

P73/(TEND1)

P72/(TEND0)

P71/(DREQ1)

P70/(DREQ0)

Section 10 I/O Ports

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Modes 3*1, 7

Port Description Modes 1

and 5 Modes 2

and 6 Mode 4 EXPE = 1 EXPE = 0

Input/

Output

Type

Port

8General I/O port

also functioning

as EXDM AC I/Os

and interrupt

inputs

P85/EDACK3/IRQ5

P84/EDACK2/IRQ4

P83/ETEND3/IRQ3

P82/ETEND2/IRQ2

P81/EDREQ3/IRQ1

P80/EDREQ2/IRQ0

P85/EDACK3/IRQ5

P84/EDACK2/IRQ4

P83/ETEND3/IRQ3

P82/ETEND2/IRQ2

P81/EDREQ3/IRQ1

P80/EDREQ2/IRQ0

P85/IRQ5

P84/IRQ4

P83/IRQ3

P82/IRQ2

P81/IRQ1

P80/IRQ0

Port

AGeneral I/O port

also functioning

as address

outputs

PA7/A23

PA6/A22

PA5/A21

A20

A19

A18

A17

A16

PA7/A23

PA6/A22

PA5/A21

PA4/A20

PA3/A19

PA2/A18

PA1/A17

PA0/A16

PA7/A23

PA6/A22

PA5/A21

PA4/A20

PA3/A19

PA2/A18

PA1/A17

PA0/A16

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

Built-in

input pull-

up MOS

Open-

drain

output

capability

Port

BGeneral I/O port

also functioning

as address

outputs

A15

A14

A13

A12

A11

A10

PB7/A15

PB6/A14

PB5/A13

PB4/A12

PB3/A11

PB2/A10

PB1/A9

PB0/A8

PB7/A15

PB6/A14

PB5/A13

PB4/A12

PB3/A11

PB2/A10

PB1/A9

PB0/A8

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

Built-in

input pull-

up MOS

Port

CGeneral I/O port

also functioning

as address

outputs

PC7/A7

PC6/A6

PC5/A5

PC4/A4

PC3/A3

PC2/A2

PC1/A1

PC0/A0

PC7/A7

PC6/A6

PC5/A5

PC4/A4

PC3/A3

PC2/A2

PC1/A1

PC0/A0

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

Built-in

input pull-

up MOS

Section 10 I/O Ports

Rev. 3.00 Mar 17, 2006 page 431 of 926

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Modes 3*1, 7

Port Description Modes 1

and 5 Modes 2

and 6 Mode 4 EXPE = 1 EXPE = 0

Input/

Output

Type

Port

DGeneral I/O port

also functioning

as data I/Os

D15

D14

D13

D12

D11

D10

D15

D14

D13

D12

D11

D10

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

Built-in

input pull-

up MOS

Port

EGeneral I/O port

also functioning

as data I/Os

PE7/D7

PE6/D6

PE5/D5

PE4/D4

PE3/D3

PE2/D2

PE1/D1

PE0/D0

PE7/D7

PE6/D6

PE5/D5

PE4/D4

PE3/D3

PE2/D2

PE1/D1

PE0/D0

PE7/D7

PE6/D6

PE5/D5

PE4/D4

PE3/D3

PE2/D2

PE1/D1

PE0/D0

PE7

PE6

PE5

PE4

PE3

PE2

PE1

PE0

Built-in

input pull-

up MOS

PF7/φ

PF6/AS

HWR

PF3/LWR

PF7/φ

PF6/AS

HWR

PF3/LWR

PF7/φ

PF6

PF5

PF4

PF3

PF2/LCAS/DQML*2/IRQ15 PF2/LCAS/

DQML*2/IRQ15 PF2/IRQ15

PF1/UCAS/DQMU*2/IRQ14 PF1/UCAS/

DQMU*2/IRQ14 PF1/IRQ14

Port

FGeneral I/O port

also functioning

as interrupt inputs

and bus control

I/Os

PF0/WAIT PF0/WAIT PF0

Only PF1

and PF2

are

Schmitt-

triggered

inputs

when

used as

the IRQ

input

Port

GGeneral I/O port

also functioning

as bus control

I/Os

PG6/BREQ

PG5/BACK

PG4/BREQO

PG3/CS3/RAS3/CAS*2

PG2/CS2/RAS2/RAS*2

PG1/CS1

PG0/CS0

PG6/BREQ

PG5/BACK

PG4/BREQO

PG3/CS3/RAS3/

CAS*2

PG2/CS2/RAS2/

RAS*2

PG1/CS1

PG0/CS0

PG6

PG5

PG4

PG3

PG2

PG1

PG0

Section 10 I/O Ports

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REJ09B0283-0300

Modes 3*1, 7

Port Description Modes 1

and 5 Modes 2

and 6 Mode 4 EXPE = 1 EXPE = 0

Input/

Output

Type

PH3/CS7/OE/CKE*2/(IRQ7)PH3/CS7/OE/

CKE*2/(IRQ7)PH3/(IRQ7)

PH2/CS6/(IRQ6)PH2/CS6/(IRQ6)PH2/(IRQ6)

PH1/CS5/RAS5/SDRAMφ*2PH1/CS5/RAS5/

SDRAMφ*2PH1/SDRAMφ*2

Port

HGeneral I/O port

also functioning

as interrupt inputs

and bus control

I/Os

PH0/CS4/RAS4/WE*2PH0/CS4/RAS4/

WE*2PH0

Only PH2

and PH3

are

Schmitt-

triggered

inputs

when

used as

the IRQ

input

Notes: 1. Mode 3 is not supported in H8S/2678 Group.

2. These pins are not supported in H8S/2678 Group.

10.1 Port 1

Port 1 is an 8-bit I/O port that also has other functions. The port 1 has the following registers.

• Port 1 data direction register (P1DDR)

• Port 1 data register (P1DR)

• Port 1 register (PORT1)

10.1.1 Port 1 Data Direction Register (P1DDR)

The individual bits of P1DDR specify input or output for the pins of port 1.

P1DDR cannot be read; if it is, an undefined value will be read.

Bit Bit Name Initial Value R/W Description

7 P17DDR 0 W

6 P16DDR 0 W

5 P15DDR 0 W

4 P14DDR 0 W

3 P13DDR 0 W

2 P12DDR 0 W

1 P11DDR 0 W

0 P10DDR 0 W

When a pin function is specified to a general

purpose I/O, setting this bit to 1 makes th e

corresponding port 1 pin an output pin, while

clearing this bit to 0 makes the pin an input pin.

Section 10 I/O Ports

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10.1.2 Port 1 Data Register (P1DR)

P1DR stores output data for the port 1 pins.

Bit Bit Name Initial Value R/W Description

7 P17DR 0 R/W

6 P16DR 0 R/W

5 P15DR 0 R/W

4 P14DR 0 R/W

3 P13DR 0 R/W

2 P12DR 0 R/W

1 P11DR 0 R/W

0 P10DR 0 R/W

Output data for a pin is stored when the pin function

is specified to a general purpose I/O.

10.1.3 Port 1 Register (PORT1)

PORT1 shows the pin states.

PORT1 cannot be modified.

Bit Bit Name Initial Value R/W Description

7 P17 Undefined*R

6 P16 Undefined*R

5 P15 Undefined*R

4 P14 Undefined*R

3 P13 Undefined*R

2 P12 Undefined*R

1 P11 Undefined*R

0 P10 Undefined*R

If a port 1 read is performed while P1DDR bits are

set to 1, the P1DR values are read. If a port 1 read

is performed while P1DDR b its are cleared to 0, the

pin states are read.

Note: *Determined by the states of pins P17 to P10.

Section 10 I/O Ports

Rev. 3.00 Mar 17, 2006 page 434 of 926

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10.1.4 Pin Functions

Port 1 pins also function as PPG outputs, TPU I/Os, and EXDMAC outputs. The correspondence

between the register specification and the pin functions is shown below.

• P17/PO15/TIOCB2/TCLKD/EDRAK3

The pin function is switched as shown below according to the combination of the TPU channel

2 settings (by bits MD3 to MD0 in TMDR2, bits IOB3 to IOB0 in TIOR2, and bits CCLR1

and CCLR0 in TCR2), bits TPSC2 to TPSC0 in TCR0 and TCR5, bit NDER15 in NDERH, bit

EDRAKE in EDMDR3, and bit P17DDR.

Modes 1, 2, 3*3 (EXPE = 1), 4, 5, 6, 7 (EXPE = 1)

EDRAKE 0 1

TPU channel 2

settings (1) in table

below (2) in table below —

P17DDR — 0 1 1 —

NDER15 — — 0 1 —

P17

input P17

output PO15

output EDRAK3

output

TIOCB2

output

TIOCB2 input*1

Pin function

TCLKD input*2

Modes 3*3 (EXPE = 0), 7 (EXPE = 0)

EDRAKE —

TPU channel 2

settings (1) in table

below (2) in table below

P17DDR — 0 1 1

NDER15 — — 0 1

P17 input P17 output PO15 outputTIOCB2 output

TIOCB2 input*1

Pin function

TCLKD input*2

Notes: 1. TIOCB2 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 = 1.

2. TCLKD input when the setting for either TCR0 or TCR5 is TPSC2 to TPSC0 = B'111.

TCLKD input when channels 2 and 4 are set to phase counting mode.

3. Only in H8S/2678R Group.

Section 10 I/O Ports

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TPU channel 2

settings (2) (1) (2) (2) (1) (2)

MD3 to MD0 B'0000, B'01xx B'0010 B'0011

IOB3 to IOB0 B'0000

B'0100

B'1xxx

B'0001 to B'0011

B'0101 to B'0111 B'xx00 B'xx00 Other than B'xx00

CCLR1, CCLR0 — — — — Other

than

B'10

Output function — Output compare

output ——PWM

mode 2

output

—

x: Don’t care

• P16/PO14/TIOCA2/EDRAK2

The pin function is switched as shown below according to the combination of the TPU channel

2 settings (by bits MD3 to MD0 in TMDR2, bits IOB3 to IOB0 in TIOR2, and bits CCLR1

and CCLR0 in TCR2), bit NDER14 in NDERH, bit EDRAKE in EDMDR2 and bit P1 6DDR.

Modes 1, 2, 3*3 (EXPE = 1), 4, 5, 6, 7 (EXPE = 1)

EDRAKE 0 1

TPU channel 2

settings (1) in table

below (2) in table below —

P16DDR — 0 1 1 —

NDER14 — — 0 1 —

TIOCA2

output P16

input P16

output PO14

output EDRAK2

output

Pin function

TIOCA input*1

Section 10 I/O Ports

Rev. 3.00 Mar 17, 2006 page 436 of 926

REJ09B0283-0300

Modes 3*3 (EXPE = 0), 7 (EXPE = 0)

EDRAKE —

TPU channel 2

settings (1) in table

below (2) in table below

P16DDR — 0 1 1

NDER14 — — 0 1

P16 input P16 output PO14 outputPin function TIOCA2 output

TIOCA2 input*1

Note: 1. TIOCA2 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 = 1.

TPU channel 2

settings (2) (1) (2) (1) (1) (2)

MD3 to MD0 B'0000, B'01xx B'001x B'0010 B'0011

IOA3 to IOA0 B'0000

B'0100

B'1xxx

B'0001 to B'0011

B'0101 to B'0111 B'xx00 Other than B'xx00

CCLR1, CCLR0 — — — — Oth er

than

B'10

Output function — Output compare

output —PWM

mode 1

output

PWM

mode 2

output

—

x: Don’t care

Notes: 2. TIOCB2 output disabled.

3. Only in H8S/2678R Group.

Section 10 I/O Ports

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• P15/PO13/TIOCB1/TCLKC

The pin function is switched as shown below according to the combination of the TPU channel

1 settings (by bits MD3 to MD0 in TMDR1, bits IOB3 to IOB0 in TIOR1, and bits CCLR1

and CCLR0 in TCR1), b its TPSC2 to TPSC0 in TCR0, TCR2, TCR4, and TCR5, bit NDER1 3

in NDERH, and bit P15DDR.

TPU channel 1

settings (1) in table

below (2) in table below

P15DDR — 0 1 1

NDER13 — — 0 1

P15 input P15 output PO13 outputTIOCB1 output

TIOCB1 input*1

Pin function

TCLKC input*2

Notes: 1. TIOCB1 input when MD3 to MD0 = B'0000 or B'01XX and IOB3 to IOB0 = B'10xx.

2. TCLKC input when the setting for either TCR0 or TCR2 is TPSC2 to TPSC0 = B'110, or

when the setting for either TCR4 or TCR5 is TPSC2 to TPSC0 = B'101.

TCLKC input when phase counting mode is set for channels 2 and 4.

TPU channel 1

settings (2) (1) (2) (2) (1) (2)

MD3 to MD0 B'0000, B'01xx B'0010 B'0011

IOB3 to IOB0 B'0000

B'0100

B'1xxx

B'0001 to B'0011

B'0101 to B'0111 B'xx00 B'xx00 Other than B'xx00

CCLR1, CCLR0 — — — — Oth er

than

B'10

Output function — Output compare

output ——PWM

mode 2

output

—

x: Don’t care

Section 10 I/O Ports

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• P14/PO12/TIOCA1

The pin function is switched as shown below according to the combination of the TPU channel

1 settings (by bits MD3 to MD0 in TMDR1, bits IOA3 to IOA0 in TIOR1, and bits CCLR1

and CCLR0 in TCR1), bit NDER12 in NDERH, and bit P14DDR.

TPU channel 1

settings (1) in table

below (2) in table below

P14DDR — 0 1 1

NDER12 — — 0 1

P14 input P14 output PO12 outputPin function TIOCA1 output

TIOCA1 input*1

Note: 1. TIOCA1 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 to IOA0 = B'10xx.

TPU channel 1

settings (2) (1) (2) (1) (1) (2)

MD3 to MD0 B'0000, B'01xx B'001x B'0010 B'0011

IOA3 to IOA0 B'0000

B'0100

B'1xxx

B'0001 to B'0011

B'0101 to B'0111 B'xx00 Other

than

B'xx00

Other than B'xx00

CCLR1, CCLR0 — — — — Oth er

than

B'01

Output function — Output compare

output —PWM

mode 1

output

PWM

mode 2

output

—

x: Don’t care

Note: 2. TIOCB1 output disabled .

Section 10 I/O Ports

Rev. 3.00 Mar 17, 2006 page 439 of 926

REJ09B0283-0300

• P13/PO11/TIOCD0/TCLKB

The pin function is switched as shown below according to the combination of the TPU channel

0 settings (by bits MD3 to MD0 in TMDR0, bits IOD3 to IOD0 in TIOR0L, and bits CCLR2

to CCLR0 in TC R0), bits TPSC2 to TPSC0 in TCR0 to TCR2, bit NDER11 in NDERH, and

bit P13DDR.

TPU channel 0

settings (1) in table

below (2) in table below

P13DDR — 0 1 1

NDER11 — — 0 1

P13 input P13 output PO11 outputTIOCD0 output

TIOCD0 input*1

Pin function

TCLKB input*2

Notes: 1. TIOCD0 input when MD3 to MD0 = B'0000 or B’01xx and IOD3 to IOD0 = B'10xx.

2. TCLKB input when the setting for any of TCR0 to TCR2 is TPSC2 to TPSC0 = B'101.

TCLKB input when phase counting mode is set for channels 1 and 5.

TPU channel 0

settings (2) (1) (2) (2) (1) (2)

MD3 to MD0 B'0000 B'0010 B'0011

IOD3 to IOD0 B'0000

B'0100

B'1xxx

B'0001 to B'0011

B'0101 to B'0111 — B'xx00 Other than B'xx00

CCLR2, CCLR0 — — — — Oth er

than

B'110

Output function — Output compare

output ——PWM

mode 2

output

—

x: Don’t care

Section 10 I/O Ports

Rev. 3.00 Mar 17, 2006 page 440 of 926

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• P12/PO10/TIOCC0/TCLKA

The pin function is switched as shown below according to the combination of the TPU channel

0 settings (by bits MD3 to MD0 in TMDR0, bits IOC3 to IOC0 in TIOR0L, and bits CCLR2

to CCLR0 in TC R0), bits TPSC2 to TPSC0 in TCR0 to TCR5, bit NDER10 in NDERH, and

bit P12DDR.

TPU channel 0

settings (1) in table

below (2) in table below

P12DDR — 0 1 1

NDER10 — — 0 1

P12 input P12 output PO10 outputTIOCC0 output

TIOCC0 input*1

Pin function

TCLKA input*2

Notes: 1. TIOCC0 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10xx.

2. TCLKA input when the setting for any of TCR0 to TCR5 is TPSC2 to TPSC0 = B'100.

TCLKA input when phase counting mode is set for channels 1 and 5.

TPU channel 0

settings (2) (1) (2) (1) (1) (2)

MD3 to MD0 B'0000 B'001x B'0010 B'0011

IOC3 to IOC0 B'0000

B'0100

B'1xxx

B'0001 to B'0011

B'0101 to B'0111 B'xx00 Other

than

B'xx00

Other than B'xx00

CCLR2, CCLR0 — — — — Oth er

than

B'101

Output function — Output compare

output —PWM

mode 1

output

PWM

mode 2

output

—

x: Don’t care

Note: 3. TIOCD0 output disabled.

Output disabled and settings (2) effective when BFA = 1 or BFB = 1 in TMDR0.

Section 10 I/O Ports

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REJ09B0283-0300

• P11/PO9/TIOCB0

The pin function is switched as shown below according to the combination of the TPU channel

0 settings (by bits MD3 to MD0 in TMDR0 and bits IOB3 to IOB0 in TIOR0H), b it NDER9 in

NDERH, and bit P11DDR.

TPU channel 0

settings (1) in table

below (2) in table below

P11DDR — 0 1 1

NDER9 — — 0 1

P11 input P11 output PO9 outputPin function TIOCB0 output

TIOCB0 input*

Note: *TIOCB0 input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10xx.

TPU channel 0

settings (2) (1) (2) (2) (1) (2)

MD3 to MD0 B'0000 B'0010 B'0011

IOB3 to IOB0 B'0000

B'0100

B'1xxx

B'0001 to B'0011

B'0101 to B'0111 — B'xx00 Other than B'xx00

CCLR2, CCLR0 — — — — Oth er

than

B'010

Output function — Output compare

output ——PWM

mode 2

output

—

x: Don’t care

Section 10 I/O Ports

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REJ09B0283-0300

• P10/PO8/TIOCA0

The pin function is switched as shown below according to the combination of the TPU channel

0 settings (by bits MD3 to MD0 in TMDR0, b its I OA3 to IOA0 in TIOR0H, and bits CCLR2

to CCLR0 in TC R0), bit NDER8 in NDERH, and bit P10DDR.

TPU channel 0

settings (1) in table

below (2) in table below

P10DDR — 0 1 1

NDER8 — — 0 1

P10 input P10 output PO8 outputPin function TIOCA0 output

TIOCA0 input*1

Note: 1. TIOCA0 input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10xx.

TPU channel 0

settings (2) (1) (2) (1) (1) (2)

MD3 to MD0 B'0000 B'001x B'0010 B'0011

IOA3 to IOA0 B'0000

B'0100

B'1xxx

B'0001 to B'0011

B'0101 to B'0111 B'xx00 Other

than

B'xx00

Other than B'xx00

CCLR2, CCLR0 — — — — Oth er

than

B'001

Output function — Output compare

output —PWM

mode 1

output

PWM

mode 2

output

—

x: Don’t care

Note: 2. TIOCB0 output disabled.

Section 10 I/O Ports

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REJ09B0283-0300

10.2 Port 2

Port 2 is an 8-bit I/O port that also has other functions. The port 2 has the following registers.

• Port 2 data direction register (P2DDR)

• Port 2 data register (P2DR)

• Port 2 register (PORT2)

10.2.1 Port 2 Data Direction Register (P2DDR)

The individual bits of P2DDR specify input or output for the pins of port 2.

P2DDR cannot be read; if it is, an undefined value will be read.

Bit Bit Name Initial Value R/W Description

7 P27DDR 0 W

6 P26DDR 0 W

5 P25DDR 0 W

4 P24DDR 0 W

3 P23DDR 0 W

2 P22DDR 0 W

1 P21DDR 0 W

0 P20DDR 0 W

When a pin function is specified to a general

purpose I/O, setting this bit to 1 makes th e

corresponding port 1 pin an output pin, while

clearing this bit to 0 makes the pin an input pin.

Section 10 I/O Ports

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REJ09B0283-0300

10.2.2 Port 2 Data Register (P2DR)

P2DR stores output data for the port 2 pins.

Bit Bit Name Initial Value R/W Description

7 P27DR 0 R/W

6 P26DR 0 R/W

5 P25DR 0 R/W

4 P24DR 0 R/W

3 P23DR 0 R/W

2 P22DR 0 R/W

1 P21DR 0 R/W

0 P20DR 0 R/W

Output data for a pin is stored when the pin function

is specified to a general purpose I/O.

10.2.3 Port 2 Register (PORT2)

PORT2 shows the pin states.

PORT2 cannot be modified.

Bit Bit Name Initial Value R/W Description

7 P27 Undefined*R

6 P26 Undefined*R

5 P25 Undefined*R

4 P24 Undefined*R

3 P23 Undefined*R

2 P22 Undefined*R

1 P21 Undefined*R

0 P20 Undefined*R

If a port 2 read is performed while P2DDR bits are

set to 1, the P2DR values are read. If a port 2 read

is performed while P2DDR b its are cleared to 0, the

pin states are read.

Note: *Determined by the states of pins P27 to P20.

Section 10 I/O Ports

Rev. 3.00 Mar 17, 2006 page 445 of 926

REJ09B0283-0300

10.2.4 Pin Functions

Port 2 pins also function as PPG outputs, TPU I/Os, interrupt inputs, and EXDMAC outputs. The

correspondence between the register specification and the pin functions is shown below.

• P27/PO7/TIOCB5/(IRQ15)/EDRAK1

The pin function is switched as shown below according to the combination of the TPU channel

5 settings (by bits MD3 to MD0 in TMDR5, bits IOB3 to IOB0 in TIOR5, and bits CCLR1

and CCLR0 in TCR5), bit NDER7 in NDERL, bit EDRAKE in EDMDR1, bit P27DDR, and

bit ITS1 5 in ITSR.

Modes 1, 2, 3*3 (EXPE = 1), 4, 5, 6, 7 (EXPE = 1)

EDRAKE 0 1

TPU channel 5

settings (1) in table

below (2) in table below —

P27DDR — 0 1 1 —

NDER7 — — 0 1 —

P27

input P27

output PO7

output EDRAK1

output

TIOCB5

output

TIOCB5 input*1

Pin function

IRQ15 interrupt input*2

Mode 3*3 (EXPE = 0), 7 (EXPE = 0)

EDRAKE —

TPU channel 5

settings (1) in table

below (2) in table below

P27DDR — 0 1 1

NDER7 — — 0 1

P27 input P27 output PO7 outputTIOCB5 output

TIOCB5 input*1

Pin function

IRQ15 interrupt input*2

Notes: 1. TIOCB5 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 = 1.

2. IRQ15 input when ITS15 = 1.

3. Only in H8S/2678R Group.

Section 10 I/O Ports

Rev. 3.00 Mar 17, 2006 page 446 of 926

REJ09B0283-0300

TPU channel 5

settings (2) (1) (2) (2) (1) (2)

MD3 to MD0 B'0000, B'01xx B'0010 B'0011

IOB3 to IOB0 B'0000

B'0100

B'1xxx

B'0001 to B'0011

B'0101 to B'0111 B'xx00 Other than B'xx00

CCLR1, CCLR0 — — — — Oth er

than

B'10

Output function — Output compare

output ——PWM

mode 2

output

—

x: Don’t care

• P26/PO6/TIOCA5/IRQ14/EDRAK0

The pin function is switched as shown below according to the combination of the TPU channel

5 settings (by bits MD3 to MD0 in TMDR5, bits IOA3 to IOA0 in TIOR5, and bits CCLR1

and CCLR0 in TCR5), bit NDER6 in NDERL, bit EDRAKE in EDMDR0 , b it P26DDR, and

bit ITS1 4 in ITSR.

Modes 1, 2, 3*4 (EXPE = 1), 4, 5, 6, 7 (EXPE = 1)

EDRAKE 0 1

TPU channel 5

settings (1) in table

below (2) in table below —

P26DDR — 0 1 1 —

NDER6 — — 0 1 —

P26

input P26

output PO6

output EDRAK0

output

TIOCA5

output

TIOCA input*1

Pin function

IRQ14 interrupt input*2

Section 10 I/O Ports

Rev. 3.00 Mar 17, 2006 page 447 of 926

REJ09B0283-0300

Modes 3*4 (EXPE = 0), 7 (EXPE = 0)

EDRAKE —

TPU channel 5

settings (1) in table

below (2) in table below

P26DDR — 0 1 1

NDER6 — — 0 1

P26 input P26 output PO6 outputTIOCA5 output

TIOCA5 input*1

Pin function

IRQ14 interrupt input*2

Notes: 1. TIOCA5 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 = 1.

2. IRQ14 input when ITS14 = 1.

TPU channel 5

settings (2) (1) (2) (2) (1) (2)

MD3 to MD0 B'0000, B'01xx B'001x B'0010 B'0011

IOA3 to IOA0 B'0000

B'0100

B'1xxx

B'0001 to B'0011

B'0101 to B'0111 B'xx00 Other

than

B'xx00

Other than B'xx00

CCLR1, CCLR0 — — — — Oth er

than

B'01

Output function — Output compare

output —PWM

mode 1

output

PWM

mode 2

output

—

x: Don’t care

Note: 3. TIOCB5 output disabled .

4. Only in H8S/2678R Group.

Section 10 I/O Ports

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REJ09B0283-0300

• P25/PO5/TIOCB4/IRQ13

The pin function is switched as shown below according to the combination of the TPU channel

4 settings (by bits MD3 to MD0 in TMDR4, bits IOB3 to IOB0 in TIOR4, and bits CCLR1

and CCLR0 in TCR4), bit NDER5 in NDERL, bit P25DDR, and bit ITS13 in ITSR.

TPU channel 4

settings (1) in table

below (2) in table below

P25DDR — 0 1 1

NDER5 — — 0 1

P25 input P25 output PO5 outputTIOCB4 output

TIOCB4 input*1

Pin function

IRQ13 interrupt input*2

Notes: 1. TIOCB4 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 to IOB0 = B'10xx.

2. IRQ13 input when ITS13 = 1.

TPU channel 5

settings (2) (1) (2) (2) (1) (2)

MD3 to MD0 B'0000, B'01xx B'0010 B'0011

IOB3 to IOB0 B'0000

B'0100

B'1xxx

B'0001 to B'0011

B'0101 to B'0111 — B'xx00 Other than B'xx00

CCLR1, CCLR0 — — — — Other

than

B'10

Output function — Output compare

output ——PWM

mode 2

output

—

x: Don’t care

Section 10 I/O Ports

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REJ09B0283-0300

• P24/PO4/TIOCA4/IRQ12

The pin function is switched as shown below according to the combination of the TPU channel

4 settings (by bits MD3 to MD0 in TMDR4 and bits IOA3 to IOA0 in TIOR4), bit NDER4 in

NDERL, bit P24DDR, and bit ITS12 in ITSR.

TPU channel 4

settings (1) in table

below (2) in table below

P24DDR — 0 1 1

NDER4 — — 0 1

P24 input P24 output PO4 outputTIOCA4 output

TIOCA4 input*1

Pin function

IRQ12 interrupt input*2

Notes: 1. TIOCA4 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 to IOA0 = B'10xx.

2. IRQ12 input when ITS12 = 1.

TPU channel 4

settings (2) (1) (2) (1) (1) (2)

MD3 to MD0 B'0000, B'01xx B'001x B'0010 B'0011

IOA3 to IOA0 B'0000

B'0100

B'1xxx

B'0001 to B'0011

B'0101 to B'0111 B'xx00 Other

than

B'xx00

Other than B'xx00

CCLR1, CCLR0 — — — — Oth er

than

B'01

Output function — Output compare

output —PWM

mode 1

output

PWM

mode 2

output

—

x: Don’t care

Note: 3. TIOCB4 output disabled .

Section 10 I/O Ports

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REJ09B0283-0300

• P23/PO3/TIOCD3/IRQ11

The pin function is switched as shown below according to the combination of the TPU channel

3 settings (by bits MD3 to MD0 in TMDR3, bits IOD3 to IOD0 in TIOR3L, and bits CCLR2

to CCLR0 in TC R3), bit NDER3 in NDERL, bit P23DDR, and bit ITS11 in ITSR.

TPU channel 3

settings (1) in table

below (2) in table below

P23DDR — 0 1 1

NDER3 — — 0 1

P23 input P23 output PO3 outputTIOCD3 output

TIOCD3 input*1

Pin function

IRQ11 interrupt input*2

Notes: 1. TIOCD3 input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10xx.

2. IRQ11 input when ITS11 = 1.

TPU channel 3

settings (2) (1) (2) (2) (1) (2)

MD3 to MD0 B'0000 B'0010 B'0011

IOD3 to IOD0 B'0000

B'0100

B'1xxx

B'0001 to B'0011

B'0101 to B'0111 — B'xx00 Other than B'xx00

CCLR2 to

CCLR0 — — — — Other

than

B'110

Output function — Output compare

output ——PWM

mode 2

output

—

x: Don’t care

Section 10 I/O Ports

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REJ09B0283-0300

• P22/PO2/TIOCC3/IRQ10

The pin function is switched as shown below according to the combination of the TPU channel

3 settings (by bits MD3 to MD0 in TMDR3, bits IOC3 to IOC0 in TIOR3L, and bits CCLR2

to CCLR0 in TC R3), bit NDER2 in NDERL, bit P22DDR, and bit ITS10 in ITSR.

TPU channel 3

settings (1) in table

below (2) in table below

P22DDR — 0 1 1

NDER2 — — 0 1

P22 input P22 output PO2 outputTIOCC3 output

TIOCC3 input*1

Pin function

IRQ10 interrupt input*2

Notes: 1. TIOCC3 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10xx.

2. IRQ10 input when ITS10 = 1.

TPU channel 3

settings (2) (1) (2) (1) (1) (2)

MD3 to MD0 B'0000 B'001x B'0010 B'0011

IOC3 to IOC0 B'0000

B'0100

B'1xxx

B'0001 to B'0011

B'0101 to B'0111 B'xx00 Other

than

B'xx00

Other than B'xx00

CCLR2 to

CCLR0 — — — — Other

than

B'101

Output function — Output compare

output —PWM

mode 1

output

PWM

mode 2

output

—

x: Don’t care

Note: 3. TIOCD3 output disabled.

Output disabled and settings (2) effective when BFA = 1 or BFB = 1 in TMDR3.

Section 10 I/O Ports

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REJ09B0283-0300

• P21/PO1/TIOCB3/IRQ9

The pin function is switched as shown below according to the combination of the TPU channel

3 settings (by bits MD3 to MD0 in TMDR3, bits IOB3 to IOB0 in TIOR3H, and bits CCLR2

to CCLR0 in TC R3), bit NDER1 in NDERL, bit P21DDR, and bit ITS9 in ITSR.

TPU channel 3

settings (1) in table

below (2) in table below

P21DDR — 0 1 1

NDER1 — — 0 1

P21 input P21 output PO1 outputTIOCB3 output

TIOCB3 input*1

Pin function

IRQ9 interrupt input*2

Notes: 1. TIOCB3 input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10xx.

2. IRQ9 input when ITS9 = 1.

TPU channel 3

settings (2) (1) (2) (2) (1) (2)

MD3 to MD0 B'0000 B'0010 B'0011

IOB3 to IOB0 B'0000

B'0100

B'1xxx

B'0001 to B'0011

B'0101 to B'0111 — B'xx00 Other than B'xx00

CCLR2 to

CCLR0 — — — — Other

than

B'010

Output function — Output compare

output ——PWM

mode 2

output

—

x: Don’t care

Section 10 I/O Ports

Rev. 3.00 Mar 17, 2006 page 453 of 926

REJ09B0283-0300

• P20/PO0/TIOCA3/IRQ8

The pin function is switched as shown below according to the combination of the TPU channel

3 settings (by bits MD3 to MD0 in TMDR3, b its I OA3 to IOA0 in TIOR3H, and bits CCLR2

to CCLR0 in TC R3), bit NDER0 in NDERL, bit P20DDR, and bit ITS8 in ITSR.

TPU channel 3

settings (1) in table

below (2) in table below

P20DDR — 0 1 1

NDER0 — — 0 1

P20 input P20 output PO0 outputTIOCA3 output

TIOCA3 input*1

Pin function

IRQ8 interrupt input*2

Notes: 1. TIOCA3 input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10xx.

2. IRQ8 input when ITS8 = 1.

TPU channel 3

settings (2) (1) (2) (1) (1) (2)

MD3 to MD0 B'0000 B'001x B'0010 B'0011

IOA3 to IOA0 B'0000

B'0100

B'1xxx

B'0001 to B'0011

B'0101 to B'0111 B'xx00 Other

than

B'xx00

Other than B'xx00

CCLR2 to

CCLR0 — — — — Other

than

B'001

Output function — Output compare

output —PWM

mode 1

output

PWM

mode 2

output

—

x: Don’t care

Note: 3. TIOCB3 output disabled .

Section 10 I/O Ports

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REJ09B0283-0300

10.3 Port 3

Port 3 is a 6-bit I/O port that also has other functions. The port 3 has the following registers.

• Port 3 data direction register (P3DDR)

• Port 3 data register (P3DR)

• Port 3 register (PORT3)

• Port 3 open drain control register (P3ODR)

• Port function control register 2(PFCR2)

10.3.1 Port 3 Data Direction Register (P3DDR)

The individual bits of P3DDR specify input or output for the pins of port 3.

P3DDR cannot be read; if it is, an undefined value will be read.

Bit Bit Name Initial Value R/W Description

7, 6 — All 0 — Reserved

These bits are always read as 0 and cannot be

modified.

5 P35DDR 0 W

4 P34DDR 0 W

3 P33DDR 0 W

2 P32DDR 0 W

1 P31DDR 0 W

0 P30DDR 0 W

When a pin function is specified to a general

purpose I/O, setting this bit to 1 makes th e

corresponding port 1 pin an output pin, while

clearing this bit to 0 makes the pin an input pin.

Section 10 I/O Ports

Rev. 3.00 Mar 17, 2006 page 455 of 926

REJ09B0283-0300

10.3.2 Port 3 Data Register (P3DR)

P3DR stores output data for the port 3 pins.

Bit Bit Name Initial Value R/W Description

7, 6 — All 0 — Reserved

These bits are always read as 0 and cannot be

modified.

5 P35DR 0 R/W

4 P34DR 0 R/W

3 P33DR 0 R/W

2 P32DR 0 R/W

1 P31DR 0 R/W

0 P30DR 0 R/W

Output data for a pin is stored when the pin function

is specified to a general purpose I/O.

10.3.3 Port 3 Register (PORT3)

PORT3 shows the pin states.

PORT3 cannot be modified.

Bit Bit Name Initial Value R/W Description

7, 6 — All 0 — Reserved

These bits are always read as 0 and cannot be

modified.

5 P35 Undefined*R

4 P34 Undefined*R

3 P33 Undefined*R

2 P32 Undefined*R

1 P31 Undefined*R

0 P30 Undefined*R

If a port 3 read is performed while P3DDR bits are

set to 1, the P3DR values are read. If a port 1 read

is performed while P3DDR b its are cleared to 0, the

pin states are read.

Note: *Determined by the states of pins P35 to P30.

Section 10 I/O Ports

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REJ09B0283-0300

10.3.4 Port 3 Open Drain Control Register (P3ODR)

P3ODR controls the output status for each port 3 pin.

Bit Bit Name Initial Value R/W Description

7, 6 — All 0 — Reserved

These bits are always read as 0 and cannot be

modified.

5 P35ODR 0 R/W

4 P34ODR 0 R/W

3 P33ODR 0 R/W

2 P32ODR 0 R/W

1 P31ODR 0 R/W

0 P30ODR 0 R/W

Setting a P3ODR bit to 1 makes the corresponding

port 3 pin an NMOS open-drain output pin, while

clearing the bit to 0 makes the pin a CMOS output

pin.

Section 10 I/O Ports

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REJ09B0283-0300

10.3.5 Port Function Control Register 2 (PFCR2)

P3ODR controls the I/O port.

Bit Bit Name Initial Value R/W Description

— All 0 — Reserved

These bits are always read as 0 and cannot be

modified.

3 ASOE 1 R/W AS Output Enable

Selects to enable or disable the AS output pin.

0: PF6 is designated as I/O port

1: PF6 is desi gnated as AS output pin

2LWROE 1 R/WLWR Output Enable

Selects to enable or disable the LWR output pin.

0: PF3 is designated as I/O port

1: PF3 is desi gnated as LWR output pin

1OES 1 R/WOE Output Select

Selects the OE output pin port when the OEE bit is

set to 1 in DRAMCR (enabling OE/CKE* output).

0: P35 is designated as OE output pin

1: PH3 is designated as OE/CKE* output pin

0 DMACS 0 R/W DMAC Control Pin Select

Selects the DMAC control I/O port.

0: PF65 to PF60 are designated as DMAC control

pins

1: PF75 to PF70 are designated as DMAC control

pins

Note: *Only in H8S/2678R Group.

Section 10 I/O Ports

Rev. 3.00 Mar 17, 2006 page 458 of 926

REJ09B0283-0300

10.3.6 Pin Functions

Port 3 pins also function as SCI I/Os and a bus control signal output. The correspondence between

the register specification and the pin functions is shown below.

• P35/SCK1/OE/CKE

The pin function is switched as shown below according to the combination of the C/A bit in

SMR of SCI_1, bits CKE0 and CKE1 in SCR, bits RMTS2 to RMTS0 in DRAMCR, bit OES

in PFCR2, and bit P35DDR.

Modes 1, 2, 3 (EXPE = 1), 4, 5, 6, 7 (EXPE = 1), H8S/2678R Group

OEE 0 1

OES — 1 0

Area

2 to 5 ——Normal

space

DRAM

space

Con-

tinuous

synch-

ronous

DRAM

space

CKE1 0101——

C/A0 1 — 0 1 ———

CKE0 0 1 —— 0 1 ————

P35DDR0 1 ——— 0 1 —————

function P35

input P35

output*SCK1

input P35

output*SCK1

input

output CKE

output

Modes 1, 2, 4, 5, 6, 7 (EXPE = 1), H8S/2678 Group

OEE 0 1

OES — 1 0

CKE1 0101—

C/A01—01——

CKE0 0 1 —— 0 1 ———

P35DDR0 1 ——— 0 1 ————

function P35

input P35

output*SCK1

input P35

output*SCK1

input

output

Note: *NMOS open-drain output when P35ODR = 1.

Section 10 I/O Ports

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REJ09B0283-0300

Modes 3*2 (EXPE = 0), 7 (EXPE = 0)

OEE —

OES —

CKE1 0 —

C/A01—

CKE0 0 1 — —

P35DDR 0 1 — — —

Pin function P35

input P35

output*1SCK1

input

Notes: 1. NMOS open-drain output when P35ODR = 1.

2. Only in H8S/2678R Group.

• P34/SCK0

The pin function is switched as shown below according to the combination of bit C/A in SMR

of SCI_0, bits CKE0 and CKE1 in SCR, and bit P34DDR.

CKE1 0 1

C/A01—

CKE0 0 1 — —

P34DDR 0 1 — — —

Pin function P34

input P34

output*SCK0

input

Note: *NMOS open-drain output when P34ODR = 1.

• P33/RxD1

The pin function is switched as shown below according to the combination of bit RE in SCR of

SCI_1 and bit P33DDR.

RE 0 1

P33DDR 0 1 —

Pin function P33 input P33 output*RxD1 input

Note: *NMOS open-drain output when P33ODR = 1.

Section 10 I/O Ports

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• P32/RxD0/IrRxD

The pin function is switched as shown below according to the combination of bit RE in SCR of

SCI_0 and bit P32DDR.

RE 0 1

P32DDR 0 1 —

Pin function P32 input P32 output*RxD0/IrRxD

input

Note: *NMOS open-drain output when P32ODR = 1.

• P31/TxD1

The pin function is switched as shown below according to the combination of bit TE in SCR of

SCI_1 and bit P31DDR.

TE 0 1

P31DDR 0 1 —

Pin function P31 input P31 output*TxD1 output*

Note: *NMOS open-drain output when P31ODR = 1.

• P30/TxD0/IrTxD

The pin function is switched as shown below according to the combination of bit TE in SCR of

SCI_0 and bit P30DDR.

TE 0 1

P30DDR 0 1 —

Pin function P30 input P30 output*RxD0/IrRxD

output*

Note: *NMOS open-drain output when P30ODR = 1.

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10.4 Port 4

Port 4 is an 8-bit input-only port. Port 4 has the following register.

• Port 4 register (PORT4)

10.4.1 Port 4 Register (PORT4)

PORT4 is an 8-bit read-only register that shows port 4 pin states.

PORT4 cannot be modified.

Bit Bit Name Initial Value R/W Description

7 P47 Undefined*R

6 P46 Undefined*R

5 P45 Undefined*R

4 P44 Undefined*R

3 P43 Undefined*R

2 P42 Undefined*R

1 P41 Undefined*R

0 P40 Undefined*R

The pin states are always read when a port 4 read is

performed.

Note: *Determined by the states of pins P47 to P40.

10.4.2 Pin Functions

Port 4 also functions as the A/D converter analog input and D/A converter analog output. The

correspondence between pins are as follows.

• P47/AN7/DA1

AN7 inputPin function

DA1 output

• P46/AN6/DA0

AN6 inputPin function

DA0 output

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• P45/AN5

Pin function AN5 input

• P44/AN4

Pin function AN4 input

• P43/AN3

Pin function AN3 input

• P42/AN2

Pin function AN2 input

• P41/AN1

Pin function AN1 input

• P40/AN0

Pin function AN0 input

10.5 Port 5

Port 5 comprises a 4-bit I/O port (P53 to P50) and a 4-bit input-only port (P57 to P54). The 4-bit

input-only port does not have the data direction register and data register. The port 5 has the

following registers.

• Port 5 data direction register (P5DDR)

• Port 5 data register (P5DR)

• Port 5 register (PORT5)

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10.5.1 Port 5 Data Direction Register (P5DDR)

The individual bits of P5DDR specify input or output for the pins of port 5.

P5DDR cannot be read; if it is, an undefined value will be read.

Bit Bit Name Initial Value R/W Description

— All 0 — Reserved

These bits are always read as 0 and cannot be

modified.

3 P53DDR 0 W

2 P52DDR 0 W

1 P51DDR 0 W

0 P50DDR 0 W

When a pin function is specified to a general

purpose I/O, setting this bit to 1 makes th e

corresponding port 1 pin an output pin, while

clearing this bit to 0 makes the pin an input pin.

10.5.2 Port 5 Data Register (P5DR)

P5DR stores output data for the port 5 pins.

Bit Bit Name Initial Value R/W Description

— All 0 — Reserved

These bits are always read as 0 and cannot be

modified.

3 P53DR 0 R/W

2 P52DR 0 R/W

1 P51DR 0 R/W

0 P50DR 0 R/W

Output data for a pin is stored when the pin function

is specified to a general purpose I/O.

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10.5.3 Port 5 Register (PORT5)

PORT5 shows the pin states.

PORT5 cannot be modified.

Bit Bit Name Initial Value R/W Description

7 P57 Undefined*R

6 P56 Undefined*R

5 P55 Undefined*R

4 P54 Undefined*R

When bits P57 to P54 are read, the pin states are

always read from bits 7 to 4.

3 P53 Undefined*R

2 P52 Undefined*R

1 P51 Undefined*R

0 P50 Undefined*R

If bits P53 to P50 are read while P5DDR bits are set

to 1, the P5DR values are read. If a port 5 read is

performed while P5DDR bits are cleared to 0, the

pin states are read.

Note: *Determined by the states of pins P57 to P50.

10.5.4 Pin Functions

Port 5 pins also function as SCI I/Os, A/D converter inputs, A/D converter analog inputs, D/A

converter analog outputs, and interrupt inputs. The correspondence between the register

specification and the pin functions is shown below.

• P57/AN15/DA3/IRQ7

The pin function is switched as shown below according to bit ITS7 in ITSR.

IRQ7 interrupt input pin*

AN15 input

Pin function

DA3 output

Note: *IRQ7 input when ITS7 = 0.

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• P56/AN14/DA2/IRQ6

The pin function is switched as shown below according to bit ITS6 in ITSR.

IRQ6 interrupt input pin*

AN14 input

Pin function

DA2 output

Note: *IRQ6 input when ITS6 = 0.

• P55/AN13/IRQ5

The pin function is switched as shown below according to bit ITS5 in ITSR.

IRQ5 interrupt input*

Pin function

AN13 input

Note: *IRQ5 input when ITS5 = 0.

• P54/AN12/IRQ4

The pin function is switched as shown below according to bit ITS4 in ITSR.

IRQ4 interrupt input*

Pin function

AN12 input

Note: *IRQ4 input when ITS4 = 0.

• P53/ADTRG/IRQ3

The pin function is switched as shown below according to the combination of bits TRGS1 and

TRGS0 in the A/D control register (ADCR), bit ITS3 in ITSR, and bit P5 3DDR.

P53DDR 0 1

P53 input P53 output

ADTRG input*1

Pin function

IRQ3 interrupt input*2

Notes: 1. ADTRG input when TRGS1 = TRGS0 = 0.

2. IRQ3 input when ITS3 = 0.

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• P52/SCK2/IRQ2

The pin function is switched as shown below according to the combination of bit C/A in SMR

of SCI_2, bits CKE0 and CKE1 in SCR, bit ITS2 in ITSR, and bit P52DDR.

CKE1 0 1

C/A01—

CKE0 0 1 — —

P52DDR 0 1 — — —

P52

input P52

output SCK2

input

Pin function

IRQ2 interrupt input*

Note: *IRQ2 input when ITS2 = 0.

• P51/RxD2/IRQ1

The pin function is switched as shown below according to the combination of bit RE in SCR of

SCI_2, bit ITS1 in ITSR, and bit P51DDR.

RE 0 1

P51DDR 0 1 —

P51 input P51 output RxD2 inputPin function

IRQ1 interrupt input*

Note: *IRQ1 input when ITS1 = 0.

• P50/TxD2/IRQ0

The pin function is switched as shown below according to the combination of bit TE in SCR of

SCI_2, bit ITS0 in ITSR, and bit P50DDR.

TE 0 1

P50DDR 0 1 —

P50 input P50 output TxD2 inputPin function

IRQ0 interrupt input*

Note: *IRQ0 input when ITS0 = 0.

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10.6 Port 6

Port 6 is a 6-bit I/O port that also has other functions. The port 6 has the following registers. For

details on the port function control register 2, refer to section 10.3.5, Port Function Control

• Port 6 data direction register (P6DDR)

• Port 6 data register (P6DR)

• Port 6 register (PORT6)

• Port function control register 2 (PFCR2)

10.6.1 Port 6 Data Direction Register (P6DDR)

The individual bits of P6DDR specify input or output for the pins of port 6.

P6DDR cannot be read; if it is, an undefined value will be read.

Bit Bit Name Initial Value R/W Description

7, 6 — All 0 — Reserved

These bits are always read as 0 and cannot be

modified.

5 P65DDR 0 W

4 P64DDR 0 W

3 P63DDR 0 W

2 P62DDR 0 W

1 P61DDR 0 W

0 P60DDR 0 W

When a pin function is specified to a general

purpose I/O, setting this bit to 1 makes th e

corresponding port 1 pin an output pin, while

clearing this bit to 0 makes the pin an input pin.

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10.6.2 Port 6 Data Register (P6DR)

P6DR stores output data for the port 6 pins.

Bit Bit Name Initial Value R/W Description

7, 6 — All 0 — Reserved

These bits are always read as 0 and cannot be

modified.

5 P65DR 0 R/W

4 P64DR 0 R/W

3 P63DR 0 R/W

2 P62DR 0 R/W

1 P61DR 0 R/W

0 P60DR 0 R/W

An output data for a pin is stored when the pi n

function is specified to a general purpose I/O.

10.6.3 Port 6 Register (PORT6)

PORT6 shows the pin states.

PORT6 cannot be modified.

Bit Bit Name Initial Value R/W Description

7, 6 — Undefined — Reserved

These bits are reserved, if read they will return an

undefined value.

5 P65 Undefined*R

4 P64 Undefined*R

3 P63 Undefined*R

2 P62 Undefined*R

1 P61 Undefined*R

0 P60 Undefined*R

If a port 6 read is performed while P6DDR bits are

set to 1, the P6DR values are read. If a port 6 read

is performed while P6DDR b its are cleared to 0, the

pin states are read.

Note: *Determined by the states of pins P65 to P60.

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10.6.4 Pin Functions

Port 6 pins also function as 8-bit timer I/Os, interrupt inputs, and DMAC I/Os. The

correspondence between the register specification and the pin functions is shown below.

• P65/TMO1/DACK1/IRQ13

The pin function is switched as shown below according to the combination of bit DMACS in

PFCR2, bit SAE1 in DMABCRH, bits OS3 to OS0 in TCSR_1 of the 8-bit timer, bit P65DDR,

and bit ITS13 in ITSR.

SAE1 0 1

DMACS — 1 0

OS3 to OS0 All 0 Not

all 0 All 0 Not

all 0 —

P65DDR 0 1 — 0 1 — —

P65

input P65

output TMO1

output P65

input P65

output TMO1

output DACK1

output

Pin function

IRQ13 interrupt input*

Note: *IRQ13 interrupt input when ITS13 = 0.

• P64/TMO0/DACK0/IRQ12

The pin function is switched as shown below according to the combination of bit DMACS in

PFCR2, bit SAE0 in DMABCRH, bits OS3 to OS0 in TCSR_0 of the 8-bit timer, bit P64DDR,

and bit ITS12 in ITSR.

SAE0 0 1

DMACS — 1 0

OS3 to OS0 All 0 Not

all 0 All 0 Not

all 0 —

P64DDR 0 1 — 0 1 — —

P64

input P64

output TMO0

output P64

input P64

output TMO0

output DACK0

output

Pin function

IRQ12 interrupt input*

Note: *IRQ12 interrupt input when ITS12 = 0.

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• P63/TMCI1/TEND1/IRQ11

The pin function is switched as shown below according to the combination of bit DMACS in

PFCR2, bit TEE1 in DMATCR of the DMAC, bit P63DDR, and bit ITS11 in ITSR.

TEE1 0 1

DMACS — 1 0

P63DDR 0 1 0 1 —

P63

input P63

output P63

input P63

output TEND1

output

IRQ11 interrupt input*1

Pin function

TMCI1 input*2

Notes: 1. IRQ11 interrupt input when ITS11 = 0.

2. When used as the external clock input pin for the TMR, its pin func tion should be

specified to the external clock input by the CKS2 to CKS0 bits in TCR_1.

• P62/TMCI0/TEND0/IRQ10

The pin function is switched as shown below according to the combination of bit DMACS in

PFCR2, bit TEE0 in DMATCR of the DMAC, bit P62DDR, and bit ITS10 in ITSR.

TEE0 0 1

DMACS — 1 0

P62DDR 0 1 0 1 —

P62

input P62

output P62

input P62

output TEND0

output

IRQ10 interrupt input*1

Pin function

TMCI0 input*2

Notes: 1. IRQ10 interrupt input when ITS10 = 0.

2. When used as the external clock input pin for the TMR, its pin func tion should be

specified to the external clock input by the CKS2 to CKS0 bits in TCR_0.

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• P61/TMRI1/DREQ1/IRQ9

The pin function is switched as shown below according to the combination of bit DMACS in

PFCR2, bit P6 1DDR, and bit I TS9 in ITSR.

P61DDR 0 1

P61 input P61 output

TMRI1 input*1

DREQ1 input*2

Pin function

IRQ9 interrupt input*3

Notes: 1. When used as the counter reset input pin for the TMR, both the CCLR1 and CCLR0 bits

in TCR_1 should be set to 1.

2. DREQ1 input when DMAKS = 0.

3. IRQ9 interrupt input when ITS9 = 0.

• P60/TMRI0/DREQ0/IRQ8

The pin function is switched as shown below according to the combination of bit DMACS in

PFCR2, bit P6 0DDR, and bit I TS8 in ITSR.

P60DDR 0 1

P60 input P60 output

TMRI0 input*1

DREQ0 input*2

Pin function

IRQ8 interrupt input*3

Notes: 1. When used as the counter reset input pin for the TMR, both the CCLR1 and CCLR0 bits

in TCR_0 should be set to 1.

2. DREQ0 input when DMAKS = 0.

3. IRQ8 interrupt input when ITS8 = 0.

Section 10 I/O Ports

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10.7 Port 7

Port 7 is a 6-bit I/O port that also has other functions. The port 7 has the following registers. For

details on the port function control register 2, refer to section 10.3.5, Port Function Control

• Port 7 data direction register (P7DDR)

• Port 7 data register (P7DR)

• Port 7 register (PORT7)

• Port function control register 2 (PFCR2)

10.7.1 Port 7 Data Direction Register (P7DDR)

The individual bits of P7DDR specify input or output for the pins of port 7.

P7DDR cannot be read; if it is, an undefined value will be read.

Bit Bit Name Initial Value R/W Description

7, 6 — All 0 — Reserved

These bits are always read as 0 and cannot be

modified.

5 P75DDR 0 W

4 P74DDR 0 W

3 P73DDR 0 W

2 P72DDR 0 W

1 P71DDR 0 W

0 P70DDR 0 W

When a pin function is specified to a general

purpose I/O, setting this bit to 1 makes th e

corresponding port 1 pin an output pin, while

clearing this bit to 0 makes the pin an input pin.

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10.7.2 Port 7 Data Register (P7DR)

P7DR stores output data for the port 7 pins.

Bit Bit Name Initial Value R/W Description

7, 6 — All 0 — Reserved

These bits are always read as 0 and cannot be

modified.

5 P75DR 0 R/W

4 P74DR 0 R/W

3 P73DR 0 R/W

2 P72DR 0 R/W

1 P71DR 0 R/W

0 P70DR 0 R/W

Output data for a pin is stored when the pin function

is specified to a general purpose I/O.

10.7.3 Port 7 Register (PORT7)

PORT7 shows the pin states.

PORT7 cannot be modified.

Bit Bit Name Initial Value R/W Description

7, 6 — Undefined — Reserved

These bits are reserved, if read they will return an

undefined value.

5 P75 Undefined*R

4 P74 Undefined*R

3 P73 Undefined*R

2 P72 Undefined*R

1 P71 Undefined*R

0 P70 Undefined*R

If a port 7 read is performed while P7DDR bits are

set to 1, the P7DR values are read. If a port 7 read

is performed while P7DDR b its are cleared to 0, the

pin states are read.

Note: *Determined by the states of pins P75 to P70.

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10.7.4 Pin Functions

Port 7 pins also function as DMAC I/Os and EXDMAC I/Os. The correspondence between the

• P75/DACK1/EDACK1

The pin function is switched as shown below according to the combination of bit DMACS in

PFCR2, bit SAE1 in DMABCRH, bit AMS in EDMDR_1, and bit P75DDR.

Modes 1, 2, 3* (EXPE = 1), 4, 5, 6, 7 (EXPE = 1)

AMS 0 1

SAE1 0 1 —

DMACS — 0 1 —

P75DDR 0101——

Pin function P75

input P75

output P75

input P75

output DACK1

output EDACK1

output

Modes 3* (EXPE = 0), 7 (EXPE = 0)

AMS —

SAE1 0 1

DMACS — 0 1

P75DDR 0101—

Pin function P75

input P75

output P75

input P75

output DACK1

output

Note: *Only in H8S/2678R Group.

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• P74/DACK0/EDACK0

The pin function is switched as shown below according to the combination of bit DMACS in

PFCR2, bit SAE0 in DMABCRH, bit AMS in EDMDR_0, and bit P74DDR.

Modes 1, 2, 3* (EXPE = 1), 4, 5, 6, 7 (EXPE = 1)

AMS 0 1

SAE0 0 1 —

DMACS — 0 1 —

P74DDR 0101——

Pin function P74

input P74

output P74

input P74

output DACK0

output EDACK0

output

Modes 3* (EXPE = 0), 7 (EXPE = 0)

AMS —

SAE0 0 1

DMACS — 0 1

P74DDR 0101—

Pin function P74

input P74

output P74

input P74

output DACK0

output

Note: *Only in H8S/2678R Group.

• P73/TEND1/ETEND1

The pin function is switched as shown below according to the combination of bit DMACS in

PFCR2, bit TEE1 in DMATCR of the DMAC, bit ETENDE in EDMDR_1 of the EXDMAC,

and bit P73DDR.

Modes 1, 2, 3* (EXPE = 1), 4, 5, 6, 7 (EXPE = 1)

ETENDE 0 1

TEE1 0 1 —

DMACS — 0 1 —

P73DDR 0101——

Pin function P73

input P73

output P73

input P73

output TEND1

output ETEND1

output

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Modes 3* (EXPE = 0), 7 (EXPE = 0)

ETENDE —

TEE1 0 1

DMACS — 0 1

P73DDR 0101—

Pin function P73

input P73

output P73

input P73

output TEND1

output

Note: *Only in H8S/2678R Group.

• P72/TEND0/ETEND0

The pin function is switched as shown below according to the combination of bit DMACS in

PFCR2, bit TEE0 in DMATCR of the DMAC, bit ETENDE in EDMDR_0 of the EXDMAC,

and bit P72DDR.

Modes 1, 2, 3* (EXPE = 1), 4, 5, 6, 7 (EXPE = 1)

ETENDE 0 1

TEE0 0 1 —

DMACS — 0 1 —

P72DDR 0 1 0 1 — —

Pin function P72

input P72

output P72

input P72

output TEND0

output ETEND0

output

Modes 3* (EXPE = 0), 7 (EXPE = 0)

ETENDE —

TEE0 0 1

DMACS — 0 1

P72DDR 0101—

Pin function P72

input P72

output P72

input P72

output TEND0

output

Note: *Only in H8S/2678R Group.

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• P71/DREQ1/EDREQ1

The pin function is switched as shown below according to the combination of bit P71DDR and

bit DMACS in PFCR2.

P71DDR 0 1

P71 input P71 output

DREQ1 input*

Pin function

EDREQ1 input

Note: *DREQ1 input when DMACS = 1.

• P70/DREQ0/EDREQ0

The pin function is switched as shown below according to the combination of bit P70DDR and

bit DMACS in PFCR2.

P70DDR 0 1

P70 input P70 output

DREQ0 input*

Pin function

EDREQ0 input

Note: *DREQ0 input when DMACS = 1.

Section 10 I/O Ports

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10.8 Port 8

Port 8 is a 6-bit I/O port that also has other functions. The port 8 has the following registers.

• Port 8 data direction register (P8DDR)

• Port 8 data register (P8DR)

• Port 8 register (PORT8)

10.8.1 Port 8 Data Direction Register (P8DDR)

The individual bits of P8DDR specify input or output for the pins of port 8.

P8DDR cannot be read; if it is, an undefined value will be read.

Bit Bit Name Initial Value R/W Description

7, 6 — All 0 — Reserved

These bits are always read as 0 and cannot be

modified.

5 P85DDR 0 W

4 P84DDR 0 W

3 P83DDR 0 W

2 P82DDR 0 W

1 P81DDR 0 W

0 P80DDR 0 W

When a pin function is specified to a general

purpose I/O, setting this bit to 1 makes th e

corresponding port 1 pin an output pin, while

clearing this bit to 0 makes the pin an input pin.

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10.8.2 Port 8 Data Register (P8DR)

P8DR stores output data for the port 8 pins.

Bit Bit Name Initial Value R/W Description

7, 6 — All 0 — Reserved

These bits are always read as 0 and cannot be

modified.

5 P85DR 0 R/W

4 P84DR 0 R/W

3 P83DR 0 R/W

2 P82DR 0 R/W

1 P81DR 0 R/W

0 P80DR 0 R/W

Output data for a pin is stored when the pin function

is specified to a general purpose I/O.

10.8.3 Port 8 Register (PORT8)

PORT8 shows the pin states.

PORT8 cannot be modified.

Bit Bit Name Initial Value R/W Description

7, 6 — Undefined — Reserved

These bits are reserved, if read they will return an

undefined value.

5 P85 Undefined*R

4 P84 Undefined*R

3 P83 Undefined*R

2 P82 Undefined*R

1 P81 Undefined*R

0 P80 Undefined*R

If a port 8 read is performed while P8DDR bits are

set to 1, the P8DR values are read. If a port 8 read

is performed while P8DDR b its are cleared to 0, the

pin states are read.

Note: *Determined by the states of pins P85 to P80.

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10.8.4 Pin Functions

Port 8 pins also function as interrupt inputs and EXDMAC I/Os. The correspondence between the

• P85/(IRQ5)/EDACK3

The pin function is switched as shown below according to the combination of bit AMS in

EDMDR_3 of the EXDMAC, bit P85DDR, and bit ITS5 in ITSR.

Modes 1, 2, 3 (EXPE = 1), 4, 5, 6, 7 (EXPE = 1)

AMS 0 1

P85DDR 0 1 —

P85 input P85 output EDACK3 outputPin function

IRQ5 interrupt input*

Modes 3, 7 (EXPE = 0)

AMS —

P85DDR 0 1

P85 input P85 outputPin function

IRQ5 interrupt input*

Note: *IRQ5 input when ITS5 = 1.

• P84/(IRQ4)/EDACK2

The pin function is switched as shown below according to the combination of bit AMS in

EDMDR_2 of the EXDMAC, bit P84DDR, and bit ITS4 in ITSR.

Modes 1, 2, 3*2 (EXPE = 1), 4, 5, 6, 7 (EXPE = 1)

AMS 0 1

P84DDR 0 1 —

P84 input P84 input/output EDACK2 outputPin function

IRQ4 interrupt input*1

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Modes 3*2 (EXPE = 0), 7 (EXPE = 0)

AMS —

P84DDR 0 1

P84 input P84 outputPin function

IRQ4 interrupt input*1

Notes: 1. IRQ4 input when ITS4 = 1.

2. Only in H8S/2678R Group.

• P83/(IRQ3)/ETEND3

The pin function is switched as shown below according to the combination of bit ETENDE in

EDMDR_3 of the EXDMAC, bit P83DDR, and bit ITS3 in ITSR.

Modes 1, 2, 3*2 (EXPE = 1), 4, 5, 6, 7 (EXPE = 1)

ETENDE 0 1

P83DDR 0 1 —

P83 input P83 output ETEND3 outputPin function

IRQ3 interrupt input*1

Modes 3*2 (EXPE = 0), 7 (EXPE = 0)

ETENDE —

P83DDR 0 1

P83 input P83 outputPin function

IRQ3 interrupt input*1

Notes: 1. IRQ3 input when ITS3 = 1.

2. Only in H8S/2678R Group.

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• P82/(IRQ2)/ETEND2

The pin function is switched as shown below according to the combination of bit ETENDE in

EDMDR_2 of the EXDMAC, bit P82DDR, and bit ITS2 in ITSR.

Modes 1, 2, 3*2 (EXPE = 1), 4, 5, 6, 7 (EXPE = 1)

ETENDE 0 1

P82DDR 0 1 —

P82 input P82 output ETEND2 outputPin function

IRQ2 interrupt input*1

Modes 3*2 (EXPE = 0), 7 (EXPE = 0)

ETENDE —

P82DDR 0 1

P82 input P82 outputPin function

IRQ2 interrupt input*1

Notes: 1. IRQ2 input when ITS2 = 1.

2. Only in H8S/2678R Group.

• P81/(IRQ1)/EDREQ3

The pin function is switched as shown below according to the combination of bit P81DDR and

bit ITS1 in ITSR.

P81DDR 0 1

P81 input P81 output

EDREQ3 input

Pin function

IRQ1 interrupt input*

Note: *IRQ1 input when ITS1 = 1.

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• P80/(IRQ0)/EDREQ2

The pin function is switched as shown below according to the combination of bit P80DDR and

bit ITS0 in ITSR.

P80DDR 0 1

P80 input P80 output

EDREQ2 input

Pin function

IRQ0 interrupt input*

Note: *IRQ0 input when ITS0 = 1.

10.9 Port A

Port A is an 8-bit I/O port that also has other functions. Th e port A has the following registers.

• Port A data direction register (PADDR)

• Port A data register (PADR)

• Port A register (PORTA)

• Port A pull-up MOS control register (PAPCR)

• Port A open-drain control register (PAODR)

• Port function control register 1 (PFCR1)

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10.9.1 Port A Data Direction Register (PADDR)

The individual bits of PADDR specify input or output for the pins of port A. PADDR cannot be

read; if it is, an undefined value will be read.

Bit Bit Name Initial Value R/W Description

7 PA7DDR 0 W

6 PA6DDR 0 W

5 PA5DDR 0 W

4 PA4DDR 0 W

3 PA3DDR 0 W

2 PA2DDR 0 W

1 PA1DDR 0 W

0 PA0DDR 0 W

• Modes 1, 2, 5, and 6

Pins PA4 to PA0 are address outputs regardless of

the PADDR settings.

For pins PA7 to PA5, when the corresponding bit of

A23E to A21E is set to 1, setting a PADDR bit to 1

makes the corresponding port A pin an address

output, while clearing the bit to 0 makes the pin an

input port. Clearing one of bits A23E to A21E to 0

makes the corresponding port A pin an I/O port, and

its function can be switched with PADDR.

• Mode 4

When the corresponding bit of A23E to A16E is set

to 1, setting a PADDR bit to 1 makes the

co rres ponding port A pin an address ou tput , while

clearing the bit to 0 makes the pin an input port.

Clearing one of bits A23E to A16E to 0 makes the

corresponding port A pin an I/O port, and its function

can be switched with PADDR.

• Modes 3* and 7 (when EXPE = 1)

When the corresponding bit of A23E to A16E is set

to 1, setting a PADDR bit to 1 makes the

co rres ponding port A pin an address ou tput , while

clearing the bit to 0 makes the pin an input port.

Clearing one of bits A23E to A16E to 0 makes the

corresponding port A pin an I/O port; setting the

corresponding PADDR bit to 1 makes the pin an

output port, while clearing the bit to 0 makes the pin

an input port.

• Modes 3* and 7 (when EXPE = 0)

Port A is an I/O port, and its pin functions can be

switched with PADDR.

Note: *Only in H8S/2678R Group.

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10.9.2 Port A Data Register (PADR)

PADR stores output data for the port A pins.

Bit Bit Name Initial Value R/W Description

7 PA7DR 0 R/W

6 PA6DR 0 R/W

5 PA5DR 0 R/W

4 PA4DR 0 R/W

3 PA3DR 0 R/W

2 PA2DR 0 R/W

1 PA1DR 0 R/W

0 PA0DR 0 R/W

Output data for a pin is stored when the pin function

is specified to a general purpose I/O.

10.9.3 Port A Register (PORTA)

PORTA shows port A pin states.

PORTA cannot be modified.

Bit Bit Name Initial Value R/W Description

7 PA7 Undefined*R

6 PA6 Undefined*R

5 PA5 Undefined*R

4 PA4 Undefined*R

3 PA3 Undefined*R

2 PA2 Undefined*R

1 PA1 Undefined*R

0 PA0 Undefined*R

If a port A read is performed while PADDR bits are

set to 1, the PADR values are read. If a port A read

is performed while PADDR bits are cleared to 0, the

pin states are read.

Note: *Determined by the states of pins PA7 to PA0.

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10.9.4 Port A Pull-Up MOS Control Register (PAPCR)

PAPCR controls the input pull-up MOS function. Bits 7 to 5 are valid in modes 1, 2, 5, and 6, and

all the bits are valid in modes 3*, 4, and 7.

Note: * Only in H8S/2678R Group.

Bit Bit Name Initial Value R/W Description

7 PA7PCR 0 R/W

6 PA6PCR 0 R/W

5 PA5PCR 0 R/W

4 PA4PCR 0 R/W

3 PA3PCR 0 R/W

2 PA2PCR 0 R/W

1 PA1PCR 0 R/W

0 PA0PCR 0 R/W

When a pin function is specif ied to an input port,

setting the corresponding bit to 1 turns on the input

pull-up MOS for that pin.

10.9.5 Port A Open Drain Control Register (PAODR)

PAODR specifies an output type of port A.

Bit Bit Name Initial Value R/W Description

7 PA7ODR 0 R/W

6 PA6ODR 0 R/W

5 PA5ODR 0 R/W

4 PA4ODR 0 R/W

3 PA3ODR 0 R/W

2 PA2ODR 0 R/W

1 PA1ODR 0 R/W

0 PA0ODR 0 R/W

Setting the corresponding bit to 1 specifies a pin

output type to NMOS open-drain output, while

clearing this bit to 0 specifies that to CMOS output.

10.9.6 Port Function Control Register 1 (PFCR1)

PFCR1 performs I/O port control. Bits 7 to 5 are valid in modes 1, 2, 5, and 6, and all the bits are

valid in m od e s 3 *, 4, and 7.

Note: * Only in H8S/2678R Group.

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Bit Bit Name Initial Value R/W Description

7 A23E 1 R/W Address 23 Enable

Enables or disables output for address output 23 (A23).

0: DR output when PA7DDR = 1

1: A23 output when PA7DDR = 1

6 A22E 1 R/W Address 22 Enable

Enables or disables output for address output 22 (A22).

0: DR output when PA6DDR = 1

1: A22 output when PA6DDR = 1

5 A21E 1 R/W Address 21 Enable

Enables or disables output for address output 21 (A21).

0: DR output when PA5DDR = 1

1: A21 output when PA5DDR = 1

4 A20E 1 R/W Address 20 Enable

Enables or disables output for address output 20 (A20).

0: DR output when PA4DDR = 1

1: A20 output when PA4DDR = 1

3 A19E 1 R/W Address 19 Enable

Enables or disables output for address output 19 (A19).

0: DR output when PA3DDR = 1

1: A19 output when PA3DDR = 1

2 A18E 1 R/W Address 18 Enable

Enables or disables output for address output 18 (A18).

0: DR output when PA2DDR = 1

1: A18 output when PA2DDR = 1

1 A17E 1 R/W Address 17 Enable

Enables or disables output for address output 17 (A17).

0: DR output when PA1DDR = 1

1: A17 output when PA1DDR = 1

0 A16E 1 R/W Address 16 Enable

Enables or disables output for address output 16 (A16).

0: DR output when PA0DDR = 1

1: A16 output when PA0DDR = 1

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10.9.7 Pin Functions

Port A pins also function as address outputs. The correspondence between the register

specification and the pin functions is shown below.

• PA7/A23, PA6/A22, PA5/A21

The pin function is switched as shown below according to the operating mode, bit EXPE, bits

A23E to A21E, and bit PADDR.

Operating

mode 1, 2, 4, 5, 6 3*, 7

EXPE — 0 1

AxxE 0 1 — 0 1

PADDR0101010101

function PA

input PA

output PA

input Address

output PA

input PA

output PA

input PA

output PA

input Address

output

Note: *Only in H8S/2678R Group.

• PA4/A20, PA3/A19, PA2/A18, PA1/A17, PA20/A16

The pin function is switched as shown below according to the operating mode, bit EXPE, bits

A23E to A21E, and bit PADDR.

Operating

mode 1, 2, 5,

643

*, 7

EXPE — — 0 1

AxxE — 0 1 — 0 1

PADDR—010 1 01010 1

function Address

output PA

input PA

output PA

input Address

output PA

input PA

output PA

input PA

output PA

input Address

output

Note: *Only in H8S/2678R Group.

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10.9.8 Port A Input Pull-Up MO S States

Port A has a bu ilt-in input pull-up MOS fun c tion that can be controlled by software. This input

pull-up MOS function can be used by pins PA7 to PA5 in modes 1, 2, 5, and 6, and by all pins in

modes 3*, 4, and 7. Input pull-up MOS can be specified as on or off on a bit-by-bit basis.

Table 10.2 summarizes the input pull-up MOS states.

Table 10. 2 Input Pull-Up MOS States (Port A)

Mode Reset Hardware

Standby Mode Software

Standby Mode In Other

Operations

3*, 4, 7 PA7 to PA0 On/Off On/Off

PA7 to PA5 On/Off On/Off1, 2, 5, 6

PA4 to PA0

Off Off

Legend:

Off: Input pull-up MOS is always off.

On/Off: On when PADDR = 0 and PAPCR = 1; otherwise off.

Note: *Only in H8S/2678R Group.

10.10 Port B

Port B is an 8-bit I/O port that also has other functions. The port B has the following registers.

• Port B data direction register (PBDDR)

• Port B data register (PBDR)

• Port B register (PORTB)

• Port B pull-up MOS control register (PBPCR)

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10.10.1 Port B Data Direction Register (PBDDR)

The individual bits of PBDDR sp ecify input or output for the pins of port B.

PBDDR cannot be read; if it is, an undefined value will be read.

Bit Bit Name Initial Value R/W Description

7 PB7DDR 0 W

6 PB6DDR 0 W

5 PB5DDR 0 W

4 PB4DDR 0 W

3 PB3DDR 0 W

2 PB2DDR 0 W

1 PB1DDR 0 W

0 PB0DDR 0 W

• Modes 1, 2, 5, and 6

Port B pins are address outputs regardless of the

PBDDR settings.

• Modes 3* (EXPE = 1), 4, and 7 (when EXPE =

Setting a PBDDR bit to 1 makes the corresponding

port B pin an address output, while clearing the bit

to 0 makes the pin an input port.

• Modes 3* (EXPE = 1) and 7 (when EXPE = 0)

Port B is an I/O port, and its pin functions can be

switched with PBDDR.

Note: *Only in H8S/2678R Group.

10.10.2 Port B Data Register (PBDR)

PBDR is stores output data for the port B pins.

Bit Bit Name Initial Value R/W Description

7 PB7DR 0 R/W

6 PB6DR 0 R/W

5 PB5DR 0 R/W

4 PB4DR 0 R/W

3 PB3DR 0 R/W

2 PB2DR 0 R/W

1 PB1DR 0 R/W

0 PB0DR 0 R/W

An output data for a pin is stored when the pi n

function is specified to a general purpose I/O.

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10.10.3 Port B Register (PORTB)

PORTB shows port B pin states.

PORTB cannot be modified.

Bit Bit Name Initial Value R/W Description

7 PB7 Undefined*R

6 PB6 Undefined*R

5 PB5 Undefined*R

4 PB4 Undefined*R

3 PB3 Undefined*R

2 PB2 Undefined*R

1 PB1 Undefined*R

0 PB0 Undefined*R

If a port B read is performed while PBDDR bits are

set to 1, the PBDR values are read. If a port B read

is performed while PBDDR bits are cleared to 0, the

pin states are read.

Note: *Determined by the states of pins PB7 to PB0.

10.10.4 Port B Pull-Up MOS Control Register (PBPCR)

PBPCR controls the on/off state of input pull-up MOS of port B. PBPCR is valid in modes 3, 4,

and 7.

Bit Bit Name Initial Value R/W Description

7 PB7PCR 0 R/W

6 PB6PCR 0 R/W

5 PB5PCR 0 R/W

4 PB4PCR 0 R/W

3 PB3PCR 0 R/W

2 PB2PCR 0 R/W

1 PB1PCR 0 R/W

0 PB0PCR 0 R/W

When a pin function is specif ied to an input port,

setting the corresponding bit to 1 turns on the input

pull-up MOS for that pin.

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10.10.5 Pin Functions

Port B pins also function as address outputs. The correspondence between the register

specification and the pin functions is shown below.

• PB7/A15, PB6/A14, PB5/A13, PB4/A12, PB3/A11, PB2/A10, PB1/A9, PB0/A8

The pin function is switched as shown below according to the operating mode, bit EXPE, and

bit PBDDR.

Operating

mode 1, 2, 5,

643

*, 7

EXPE — — 0 1

PBDDR — 0 1 0 1 0 1

Pin function Address

output PB

input Address

output PB

input PB

output PB

input Address

output

Note: *Only in H8S/2678R Group.

10.10.6 Po rt B Input Pull-Up MOS States

Port B has a built-in input pull-up MOS function that can be controlled by software. This input

pull-up MOS function can be used in modes 4 and 7. Input pull-up MOS can be specified as on or

off on a bit-by-bit basis.

In modes 3, 4, and 7, when a PBDDR bit is cleared to 0, setting the corresponding PBPCR bit to 1

turns on the input pull-up MOS for that pin.

Table 10.3 summarizes the input pull-up MOS states.

Table 10. 3 Input Pull-Up MOS Stat es (Port B)

Mode Reset Hardware

Standby Mode Software

Standby Mode In Other

Operations

1, 2, 5, 6 Off Off

3*, 4, 7

Off Off

On/Off On/Off

Legend:

Off: Input pull-up MOS is always off.

On/Off: On when PBDDR = 0 and PBPCR = 1; otherwise off.

Note: *Only in H8S/2678R Group.

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10.11 Port C

Port C is an 8-bit I/O port that also has other functions. The port C has the following registers.

• Port C data direction register (PCDDR)

• Port C data register (PCDR)

• Port C register (PORTC)

• Port C pull-up MOS control register (PCPCR)

10.11.1 Port C Data Direction Register (PCDDR)

The individual bits of PCDDR sp ecify input or output for the pins of port C.

PCDDR cannot be read; if it is, an undefined value will be read.

Bit Bit Name Initial Value R/W Description

7 PC7DDR 0 W

6 PC6DDR 0 W

5 PC5DDR 0 W

4 PC4DDR 0 W

3 PC3DDR 0 W

2 PC2DDR 0 W

1 PC1DDR 0 W

0 PC0DDR 0 W

• Modes 1, 2, 5, and 6

Port C pins are address outputs regardless of the

PCDDR settings.

• Modes 3* (EXPE = 1), 4, and 7 (when EXPE =

Setting a PCDDR bit to 1 makes the corre sponding

port C pin an address output, while clearing the bit

to 0 makes the pin an input port.

• Modes 3* (EXPE = 1) and 7 (when EXPE = 0)

Port C is an I/O port, and its pin functions can be

switched with PCDDR.

Note: *Only in H8S/2678R Group.

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10.11.2 Port C Data Register (PCDR)

PCDR stores output data for the port C pins.

Bit Bit Name Initial Value R/W Description

7 PC7DR 0 R/W

6 PC6DR 0 R/W

5 PC5DR 0 R/W

4 PC4DR 0 R/W

3 PC3DR 0 R/W

2 PC2DR 0 R/W

1 PC1DR 0 R/W

0 PC0DR 0 R/W

Output data for a pin is stored when the pin function

is specified to a general purpose I/O.

10.11.3 Port C Register (PORTC)

PORTC is shows port C pin states.

PORTC cannot be modified.

Bit Bit Name Initial Value R/W Description

7 PC7 Undefined*R

6 PC6 Undefined*R

5 PC5 Undefined*R

4 PC4 Undefined*R

3 PC3 Undefined*R

2 PC2 Undefined*R

1 PC1 Undefined*R

0 PC0 Undefined*R

If a port C read is performed while PCDDR bits are

set to 1, the PCDR values are read. If a port C read

is performed while PCDDR bits are cleared to 0, the

pin states are read.

Note: *Determined by the states of pins PC7 to PC0.

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10.11.4 Port C Pull-Up MOS Control Register (PCPCR)

PCPCR controls the on/off state of input pull-up MOS of port C. PCPCR is valid in modes 3*, 4,

and 7.

Bit Bit Name Initial Value R/W Description

7 PC7PCR 0 R/W

6 PC6PCR 0 R/W

5 PC5PCR 0 R/W

4 PC4PCR 0 R/W

3 PC3PCR 0 R/W

2 PC2PCR 0 R/W

1 PC1PCR 0 R/W

0 PC0PCR 0 R/W

When a pin function is specif ied to an input port,

setting the corresponding bit to 1 turns on the input

pull-up MOS for that pin.

Note: *Only in H8S/2678R Group.

10.11.5 Pin Functions

Port C pins also function as address outputs. The correspondence between the register

specification and the pin functions is shown below.

• PC7/A7, PC6/A6, PC5/A5, PC4/A4 , PC3/A3 , PC2/A2 , PC1/A1, PC0/A0

The pin function is switched as shown below according to the operating mode, bit EXPE, and

bit PCDDR.

Operating

mode 1, 2, 5,

643

*, 7

EXPE — — 0 1

PCDDR — 0 1 0 1 0 1

Pin function Address

output PC

input Address

output PC

input PC

output PC

input Address

output

Note: *Only in H8S/2678R Group.

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10.11.6 Port C Input Pull-Up MO S States

Port C has a built-in input pull-up MOS function that can be controlled by software. This input

pull-up MOS function can be used in modes 3*, 4, and 7. Input pull-up MOS can be specified as

on or off on a bit-by-bit basis.

In modes 3*, 4, and 7, when a PCDDR bit is cleared to 0, setting the corresponding PCPCR bit to

1 turns on the input pull-up MOS for that pin.

Table 10.4 summarizes the input pull-up MOS states.

Table 10. 4 Input Pull-Up MOS States (Port C)

Mode Reset Hardware

Standby Mode Software

Standby Mode In Other

Operations

1, 2, 5, 6 Off Off

3*, 4, 7

Off Off

On/Off On/Off

Legend:

Off: Input pull-up MOS is always off.

On/Off: On when PCDDR = 0 and PCPCR = 1; otherwise off.

Note: *Only in H8S/2678R Group.

10.12 Port D

Port D is an 8-bit I/O port that also has other functions. Th e port D has the following registers.

• Port D data direction register (PDDDR)

• Port D data register (PDDR)

• Port D register (PORTD)

• Port D pull-up MOS control register (PDPCR)

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10.12.1 Port D Data Direction Register (PDDDR)

The individual bits of PDDDR specify input or output for the pins of port D.

PDDDR cannot be read; if it is, an undefined value will be read.

Bit Bit Name Initial Value R/W Description

7 PD7DDR 0 W

6 PD6DDR 0 W

5 PD5DDR 0 W

4 PD4DDR 0 W

3 PD3DDR 0 W

2 PD2DDR 0 W

1 PD1DDR 0 W

0 PD0DDR 0 W

• Modes 1, 2, 3* (EXPE = 1), 4, 5, 6, and 7 (when

EXPE = 1)

Port D is automatically designated for data

input/output.

• Modes 3* (EXPE = 1) and 7 (when EXPE = 0)

Port D is an I/O port, and its pin functions can be

switched with PDDDR.

Note: *Only in H8S/2678R Group.

10.12.2 Port D Data Register (PDDR)

PDDR stores output data for the port D pins.

Bit Bit Name Initial Value R/W Description

7 PD7DR 0 R/W

6 PD6DR 0 R/W

5 PD5DR 0 R/W

4 PD4DR 0 R/W

3 PD3DR 0 R/W

2 PD2DR 0 R/W

1 PD1DR 0 R/W

0 PD0DR 0 R/W

Output data for a pin is stored when the pin function

is specified to a general purpose I/O.

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10.12.3 Port D Register (PORTD)

PORTD shows port D pin states.

PORTD cannot be modified.

Bit Bit Name Initial Value R/W Description

7 PD7 Undefined*R

6 PD6 Undefined*R

5 PD5 Undefined*R

4 PD4 Undefined*R

3 PD3 Undefined*R

2 PD2 Undefined*R

1 PD1 Undefined*R

0 PD0 Undefined*R

If a port D read is performed while PDDDR bits are

set to 1, the PDDR values are read. If a port D read

is performed while PDDDR bits are cleared to 0, the

pin states are read.

Note: *Determined by the states of pins PD7 to PD0.

10.12.4 Port D Pull-up Control Register (PDPCR)

PDPCR controls on/off states of the input pull-up MOS of port D. PDPCR is valid in modes 3*

and 7.

Bit Bit Name Initial Value R/W Description

7 PD7PCR 0 R/W

6 PD6PCR 0 R/W

5 PD5PCR 0 R/W

4 PD4PCR 0 R/W

3 PD3PCR 0 R/W

2 PD2PCR 0 R/W

1 PD1PCR 0 R/W

0 PD0PCR 0 R/W

When the pin is in its input state, the inp ut pull-u p

MOS of the input pin is on when the corresponding

bit is set to 1.

Note: *Only in H8S/2678R Group.

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10.12.5 Pin Functions

Port D pins also function as data I/Os. The correspondence between the register specification and

the pin functions is shown below.

• PD7/D15, PD6/D14, PD5/D13, PD4/D12, PD3/D11, PD2/D10, PD1/D9, PD0/D8

The pin function is switched as shown below according to the operating mode, bit EXPE, and

bit PDDDR.

Operating

mode 1, 2, 4, 5, 6 3*, 7

EXPE — 0 1

PDDDR — 0 1 —

Pin function Data I/O PD input PD output Data I/O

Note: *Only in H8S/2678R Group.

10.12.6 Port D Input Pull-Up MO S States

Port D has a bu ilt-in input pull-up MOS fun c tion that can be controlled by software. This input

pull-up MOS function can be used in modes 3* and 7. Input pull-up MOS can be specified as on

or off on a bit-by-bit basis.

In modes 3* and 7, when a PDDDR bit is cleared to 0, setting the corresponding PDPCR bit to 1

turns on the input pull-up MOS for that pin.

Note: * Only in H8S/2678R Group.

Table 10.5 summarizes the input pull-up MOS states.

Table 10. 5 Input Pull-Up MOS States (Port D)

Mode Reset Hardware

Standby Mode Software

Standby Mode In Other

Operations

1, 2, 4, 5, 6 Off Off

3*, 7

Off Off

On/Off On/Off

Legend:

OFF: Input pull-up MOS is always off.

On/Off: On when PDDDR = 0 and PDPCR = 1; otherwise off.

Note: *Only in H8S/2678R Group.

Section 10 I/O Ports

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10.13 Port E

Port E is an 8-bit I/O port that also has other functions. The port E has the following registers.

• Port E data direction register (PEDDR)

• Port E data register (PEDR)

• Port E register (PORTE)

• Port E pull-up MOS control register (PEPCR)

10.13.1 Port E Data Direction Register (PEDDR)

The individual bits of PEDDR specify input or output for the pins of port E.

PEDDR cannot be read; if it is, an undefined value will be read.

Bit Bit Name Initial Value R/W Description

7 PE7DDR 0 W

6 PE6DDR 0 W

5 PE5DDR 0 W

4 PE4DDR 0 W

3 PE3DDR 0 W

2 PE2DDR 0 W

1 PE1DDR 0 W

0 PE0DDR 0 W

• Modes 1, 2, 4, 5, and 6

When 8-bit bus mode is selecte d, port E functio ns

as an I/O port. The pin states can be changed with

PEDDR.

When 16-bit bus mode is selected, port E is

designated for data input/output.

For details on 8-bit and 16-bit bus modes, see

section 6, Bus Controller (BSC).

• Modes 3* and 7 (when EXPE = 1)

When 8-bit bus mode is selecte d, port E functio ns

as an I/O port. Setting a PEDDR bit to 1 makes the

corresponding port E pin an output port, while

clearing the bit to 0 makes the pin an input port.

When 16-bit bus mode is selected, port E is

designated for data input/output.

• Modes 3* and 7 (when EXPE = 0)

Port E is an I/O port, and its pin functions can be

switched with PEDDR.

Note: *Only in H8S/2678R Group.

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10.13.2 Port E Data Register (PEDR)

PEDR stores output data for the port E pins.

Bit Bit Name Initial Value R/W Description

7 PE7DR 0 R/W

6 PE6DR 0 R/W

5 PE5DR 0 R/W

4 PE4DR 0 R/W

3 PE3DR 0 R/W

2 PE2DR 0 R/W

1 PE1DR 0 R/W

0 PE0DR 0 R/W

Output data for a pin is stored when the pin function

is specified to a general purpose I/O.

10.13.3 Port E Register (PORTE)

PORTE shows port E pin states.

PORTE cannot be modified.

Bit Bit Name Initial Value R/W Description

7 PE7 Undefined*R

6 PE6 Undefined*R

5 PE5 Undefined*R

4 PE4 Undefined*R

3 PE3 Undefined*R

2 PE2 Undefined*R

1 PE1 Undefined*R

0 PE0 Undefined*R

If a port E read is performed while PEDDR bits are

set to 1, the PEDR values are read. If a port E read

is performed while PEDDR bits are cleared to 0, the

pin states are read.

Note: *Determined by the states of pins PE7 to PE0.

Section 10 I/O Ports

Rev. 3.00 Mar 17, 2006 page 502 of 926

REJ09B0283-0300

10.13.4 Port E Pull-up Control Register (PEPCR)

PEPCR controls on/off states of the input pull-up MOS of port E. PEPCR is valid in 8-bit bus

mode.

Bit Bit Name Initial Value R/W Description

7 PE7PCR 0 R/W

6 PE6PCR 0 R/W

5 PE5PCR 0 R/W

4 PE4PCR 0 R/W

3 PE3PCR 0 R/W

2 PE2PCR 0 R/W

1 PE1PCR 0 R/W

0 PE0PCR 0 R/W

When the pin is in its input state, the inp ut pull-u p

MOS of the input pin is on when the corresponding

bit is set to 1.

10.13.5 Pin Functions

Port E pins also function as data I/Os. The correspondence between the register specification and

the pin functions is shown below.

• PE7/D7, PE6/D6, PE 5/D5, PE4/D4, PE3/D3, PE2/D2, PE1/D1, PE0/D0

The pin function is switched as shown below accord ing to the operating mode, bus mode, bit

EXPE, and bit PEDDR.

Operating

mode 1, 2, 4, 5, 6 3*, 7

Bus mode All areas

8-bit space At least

one area

16-bit

space

— All areas

8-bit space At least

one area

16-bit

space

EXPE — — 0 1 1

PEDDR 01—0101—

Pin function PE

input PE

output Data I/O PE

input PE

output PE

input PE

output Data I/O

Note: *Only in H8S/2678R Group.

Section 10 I/O Ports

Rev. 3.00 Mar 17, 2006 page 503 of 926

REJ09B0283-0300

10.13.6 Po rt E Input Pull-Up MOS States

Port E has a built-in input pull-up MOS function that can be controlled by software. This input

pull-up MOS function can be used in 8-bit bus mode. Inpu t pull-up MOS can be specified as on or

off on a bit-by-bit basis. In 8-bit bus mode, when a PEDDR bit is cleared to 0, setting the

corresponding PEPCR bit to 1 turns on the input pull-up MOS for that pin.

Table 10.6 summarizes the input pull-up MOS states.

Table 10. 6 Input Pull-Up MOS Stat es (Port E)

Mode*Reset Hardware

Standby Mode Software

Standby Mode In Other

Operations

8-bit bus On/O ff On/Off1 to 7

16-bit bus

Off Off

Legend:

Off: Input pull-up MOS is always off.

On/Off: On when PEDDR = 0 and PEPCR = 1; otherwise off.

Note: *Mode 3 is available only in H8S/2678R Group.

10.14 Port F

Port F is an 8-bit I/O port that also has other functions. The port F has the following registers. For

details on the port function control register 2, refer to section 10.3.5, Port Function Control

• Port F data direction register (PFDDR)

• Port F data register (PFDR)

• Port F register (PORTF)

• Port Function Control Register 2 (PFCR2)

Section 10 I/O Ports

Rev. 3.00 Mar 17, 2006 page 504 of 926

REJ09B0283-0300

10.14.1 Port F Data Direction Register (PFDDR)

The individual bits of PFDDR specify input or output for the pins of port F.

PFDDR cannot be read; if it is, an undefined value will be read.

Bit Bit Name Initial Value R/W Description

7 PF7DDR 1/0*1W

6 PF6DDR 0 W

5 PF5DDR 0 W

4 PF4DDR 0 W

3 PF3DDR 0 W

2 PF2DDR 0 W

1 PF1DDR 0 W

0 PF0DDR 0 W

• Modes 1, 2, 4, 5, and 6

Pin PF7 functions as the φ output pin when the

corresponding PFDDR bit is set to 1, and as an

input port when the bit is cleared to 0.

Pin PF6 functions as the AS output pin when ASOE

is set to 1. When ASOE is cleared to 0, pin PF6 is

an I/O port and its function can be switched with

PF6DDR.

Pins PF5 and PF4 are automatically designated as

bus control outp uts (RD and HWR).

Pin PF3 functions as the LWR output pin when

LWROE is set to 1. When LWROE is cleared to 0,

pin PF3 is an I/O port and its function can be

switched with PF3DDR.

Pins PF2 and PF1 are designated as I/O ports and

their function can be switched with PFDDR.

Pins PF0 functions as bus control input/output pin

(LCAS, UCAS, and WAIT) when the appropriate bus

controller settings are made. Otherwise, these pins

are output ports when the corresponding PFDDR bit

is set to 1, and input ports when the bit is cleared to

• Modes 3*2 and 7 (when EXPE = 1)

Pin PF7 to PF3 func tion in the same way as in

modes 1, 2, 4, 5, and 6.

Pins PF2 to PF0 function as bus control input/output

pins (LCAS, UCAS, and WAIT) when the

appropriate PFCR2 settings are made. Otherwise,

these pins are I/O ports, and their functions can be

switched with PFDDR.

Section 10 I/O Ports

Rev. 3.00 Mar 17, 2006 page 505 of 926

REJ09B0283-0300

Bit Bit Name Initial Value R/W Description

• Modes 3*2 and 7 (when EXPE = 0)

Pin PF7 functions as the φ output pin when the

corresponding PFDDR bit is set to 1, and as an

input port when the bit is cleared to 0.

Pins PF6 to PF0 are I/O ports, and their functi ons

can be switched with PFDDR.

Notes: 1. PF7DDR is initialized to 1 in modes 1, 2, 4, 5, and 6, and to 0 in mode 7.

2. Only in H8S/2678R Group.

10.14.2 Port F Data Register (PFDR)

PFDR stores output data for the port F pins.

Bit Bit Name Initial Value R/W Description

7PF7DR 0 R/W

6PF6DR 0 R/W

5PF5DR 0 R/W

4PF4DR 0 R/W

3PF3DR 0 R/W

2PF2DR 0 R/W

1PF1DR 0 R/W

0PF0DR 0 R/W

Output data for a pin is stored when the pin function

is specified to a general purpose I/O.

Section 10 I/O Ports

Rev. 3.00 Mar 17, 2006 page 506 of 926

REJ09B0283-0300

10.14.3 Port F Register (PORTF)

PORTF shows port F pin states.

PORTF cannot be modified.

Bit Bit Name Initial Value R/W Description

7 PF7 Undefined*R

6 PF6 Undefined*R

5 PF5 Undefined*R

4 PF4 Undefined*R

3 PF3 Undefined*R

2 PF2 Undefined*R

1 PF1 Undefined*R

0 PF0 Undefined*R

If a port F read is performed while PFDDR bits are

set to 1, the PFDR values are read. If a port F read

is performed while PFDDR bi ts are cleared to 0, the

pin states are read.

Note: *Determined by the states of pins PF7 to PF0.

10.14.4 Pin Functions

Port F pins also function as external interrupt inputs, bus control signal I/Os, and system clock

outputs (φ). The correspondence between the register specification and the pin functions is shown

below.

• PF7/φ

The pin function is switched as shown below according to bit PF7DDR.

Operating

mode 1 to 7

PFDDR 0 1

Pin function PF7 input φ output

Section 10 I/O Ports

Rev. 3.00 Mar 17, 2006 page 507 of 926

REJ09B0283-0300

• PF6/AS

The pin function is switched as shown below according to the operating mode, bit EXPE, bit

PF6DDR, and bit ASOE.

Operating

mode 1, 2, 4, 5, 6 3*, 7

EXPE — 0 1

ASOE 1 0 — 1 0

PF6DDR—0101—01

Pin function AS

output PF6

input PF6

output PF6

input PF6

output AS

output PF6

input PF6

output

Note: *Only in H8S/2678R Group.

• PF5/RD

The pin function is switched as shown below according to the operating mode, bit EXPE, and

bit PF5DDR.

Operating

mode 1, 2, 4, 5, 6 3*, 7

EXPE — 0 1

PF5DDR — 0 1 —

Pin function RD output PF5 input PF5 output RD output

Note: *Only in H8S/2678R Group.

• PF4/HWR

The pin function is switched as shown below according to the operating mode, bit EXPE, and

bit PF4DDR.

Operating

mode 1, 2, 4, 5, 6 3*, 7

EXPE — 0 1

PF4DDR — 0 1 —

Pin function HWR output PF4 input PF4 output HWR output

Note: *Only in H8S/2678R Group.

Section 10 I/O Ports

Rev. 3.00 Mar 17, 2006 page 508 of 926

REJ09B0283-0300

• PF3/LWR

The pin function is switched as shown below according to the operating mode, bit EXPE, bit

PF3DDR, and bit LWROE.

Operating

mode 1, 2, 4, 5, 6 3*, 7

EXPE — 0 1

LWROD 1 0 — 1 0

PF3DDR—0101—01

Pin function LWR

output PF3

input PF3

output PF3

input PF3

output LWR

output PF3

input PF3

output

Note: *Only in H8S/2678R Group.

• PF2/LCAS/DQML*2/IRQ15

The pin function is switched as shown below accord ing to the combination of the operating

mode, bit EXPE, bits RMTS2 to RMTS0 in DRAMCR, bits AB W5 to ABW2 in AB WCR, and

bit PF2DDR.

Operating

mode 1, 2, 4, 5, 6 3*2, 7

EXPE — 0 1

Areas

2 to 5 Any

DRAM

space

area is

16-bit

bus

space

All DRAM

space areas

are 8-bit bus

sp ace, or areas

2 to 5 are all

normal space

—Any

DRAM

space

area is

16-bit

bus

space

All DRAM

space areas

are 8-bit bus

sp ace, or areas

2 to 5 are all

normal space

PF2DDR—0101—01

LCAS

output PF2

input PF2

output PF2

input PF2

output LCAS

output PF2

input PF2

output

Pin function

IRQ15 interrupt input*1

Notes: 1. IRQ15 interrupt input when bit ITS15 is cleared to 0 in ITSR.

2. Only in H8S/2678R Group.

Section 10 I/O Ports

Rev. 3.00 Mar 17, 2006 page 509 of 926

REJ09B0283-0300

• PF1/UCAS/DQMU*2/IRQ14

The pin function is switched as shown below accord ing to the combination of the operating

mode, bit EXPE, bits RMTS2 to RMTS0 in DRAMCR, and bit PF1DDR.

Operating

mode 1, 2, 4, 5, 3*2, 7

EXPE — 0 1

Areas

2 to 5 Any of

areas

2 to 5

DRAM

space

Areas 2 to 5

are all normal

space

— Any of

areas

2 to 5

DRAM

space

Areas 2 to 5

are all normal

space

PF1DDR—0101—01

UCAS

output PF1

input PF1

output PF1

input PF1

output UCAS

output PF1

input PF1

output

Pin function

IRQ14 interrupt*1

Notes: 1. IRQ14 interrupt input when bit ITS14 is cleared to 0 in ITSR.

2. Only in H8S/2678R Group.

• PF0/WAIT

The pin function is switched as shown below according to the operating mode, bit EXPE, bit

WAITE in BCR, an d bit PF0DDR.

Operating

mode 1, 2, 4, 5, 6 3*, 7

EXPE — 0 1

WAITE 0 1 — 0 1

PF0DDR01—0101—

Pin function PF0

input PF0

output WAIT

input PF0

output PF0

input PF0

output WAIT

input

Note: *Only in H8S/2678R Group.

Section 10 I/O Ports

Rev. 3.00 Mar 17, 2006 page 510 of 926

REJ09B0283-0300

10.15 Port G

Port G is a 7-bit I/O port that also has other functions. The port G has the following registers.

• Port G data direction register (PGDDR)

• Port G data register (PGDR)

• Port G register (PORTG)

• Port Function Control Register 0 (PFCR0)

10.15.1 Port G Data Direction Register (PGDDR)

The individual bits of PGDDR specify input or output for the pins of port G.

PGDDR cannot be read; if it is, an undefined value will be read.

Section 10 I/O Ports

Rev. 3.00 Mar 17, 2006 page 511 of 926

REJ09B0283-0300

Bit Bit Name Initial Value R/W Description

7— 0 — Reserved

If read, it returns an undefined value.

6 PG6DDR 0 W

5 PG5DDR 0 W

4 PG4DDR 0 W

3 PG3DDR 0 W

2 PG2DDR 0 W

1 PG1DDR 0 W

0 PG0DDR 1/0*1W

• Modes 1, 2, 4, 5, and 6

Pins PG6 to PG4 function as bus control

input/output pins (BREQO, BACK, and BREQ) when

the appropriate bus controller settings are made.

Otherwise, these pins are I/O ports, and their

functions can be switched with PGDDR.

When the CS output enable bits (CS3E to CS0E)

are set to 1, pins PG3 to PG0 function as CS output

pins when the corresponding PGDDR bit is set to 1,

and as input ports when the bit is cleared to 0.

When CS3E to CS0E are cleared to 0, pins PG3 to

PG0 are I/O ports, and their functions can be

switched with PGDDR.

• Modes 3*2, 7 (when EXPE = 1)

Pins PG6 to PG4 function as bus control

input/output pins (BREQO, BACK, and BREQ) when

the appropriate bus controller settings are made.

Otherwise, these pins are output ports when the

corresponding PGDDR bit is set to 1, and as input

ports when the bit is cleared to 0.

When the CS output enable bits (CS3E to CS0E)

are set to 1, pins PG3 to PG0 function as CS output

pins when the corresponding PGDDR bit is set to 1,

and as input ports when the bit is cleared to 0.

When CS3E to CS0E are cleared to 0, pins PG3 to

PG0 are I/O ports, and their functions can be

switched with PGDDR.

• Modes 3*2, 7 (when EXPE = 0)

Pins PG6 to PG0 are I/O ports, and their functions

can be switched with PGDDR.

Notes: 1. PG0DDR is initi alized to 1 in modes 1, 2, 5, and 6, and to 0 in modes 3, 4, and 7.

2. Only in H8S/2678R Group.

Section 10 I/O Ports

Rev. 3.00 Mar 17, 2006 page 512 of 926

REJ09B0283-0300

10.15.2 Port G Data Register (PGDR)

PGDR stores output data for the port G pins.

Bit Bit Name Initial Value R/W Description

7— 0 — Reserved

This bit is always read as 0, and cann ot be modif ied.

6PG6DR 0 R/W

5PG5DR 0 R/W

4PG4DR 0 R/W

3PG3DR 0 R/W

2PG2DR 0 R/W

1PG1DR 0 R/W

0PG0DR 0 R/W

An output data for a pin is stored when the pi n

function is specified to a general purpose I/O.

10.15.3 Port G Register (PORTG)

PORTG shows port G pin states.

PORTG cannot be modified.

Bit Bit Name Initial Value R/W Description

7 — Undefined — Reserved

If this bit is read, it will return an undefined value.

6 PG6 Undefined*R

5 PG5 Undefined*R

4 PG4 Undefined*R

3 PG3 Undefined*R

2 PG2 Undefined*R

1 PG1 Undefined*R

0 PG0 Undefined*R

If a port G read is performed while PGDDR bits are

set to 1, the PGDR values are read. If a port G read

is performed while PGDDR bits are cleared to 0, the

pin states are read.

Note: *Determined by the states of pins PG6 to PG0.

Section 10 I/O Ports

Rev. 3.00 Mar 17, 2006 page 513 of 926

REJ09B0283-0300

10.15.4 Port Function Control Register 0 (PFCR0)

PFCR0 performs I/O port control.

Bit Bit Name Initial Value R/W Description

7CS7E 0 R/W

6CS6E 0 R/W

5CS5E 0 R/W

4CS4E 0 R/W

3CS3E 0 R/W

2CS2E 0 R/W

1CS1E 0 R/W

0CS0E 0 R/W

CS7 to CS0 Enable

These bits enable or disable the corresponding CSn

output.

0: Pin is designated as I/O port

1: Pin is designated as CSn output pin (n = 7 to 0)

10.15.5 Pin Functions

Port G pins also function as bus control signal I/Os. The correspondence between the register

specification and the pin functions is shown below.

• PG6/BREQ

The pin function is switched as shown below according to the operating mode, bit EXPE, bit

BRLE, and bit PG6DDR.

Operating

mode 1, 2, 4, 5, 6 3*, 7

EXPE — 0 1

BRLE 0 1 — 0 1

PG6DDR 0 1 — 0 1 0 1 —

function PG6

input PG6

output BREQ

input PG6

output PG6

input PG6

output BREQ

input

Note: *Only in H8S/2678R Group.

Section 10 I/O Ports

Rev. 3.00 Mar 17, 2006 page 514 of 926

REJ09B0283-0300

• PG5/BACK

The pin function is switched as shown below according to the operating mode, bit EXPE, bit

BRLE, and bit PG5DDR.

Operating

mode 1, 2, 4, 5, 6 3*, 7

EXPE — 0 1

BRLE 0 1 — 0 1

PG5DDR 0 1 — 0 1 0 1 —

function PG5

input PG5

output BACK

output PG5

input PG5

output PG5

input PG5

output BACK

output

Note: *Only in H8S/2678R Group.

• PG4/BREQO

The pin function is switched as shown below according to the operating mode, bit EXPE, bit

BRLE, bit BREQO, and bit PG4DDR.

Operating

mode 1, 2, 4, 5, 6 3*, 7

EXPE — 0 1

BRLE 0 1 — 0 1

BREQO — 0 1 — — 0 1

PG4DDR0101 — 010101 —

function PG4

input PG4

output PG4

input PG4

output

BREQO

output PG4

input PG4

output PG4

input PG4

output PG4

input PG4

output

BREQO

output

Note: *Only in H8S/2678R Group.

Section 10 I/O Ports

Rev. 3.00 Mar 17, 2006 page 515 of 926

REJ09B0283-0300

• PG3/CS3/RAS3*/CAS*, PG2/CS2/RAS2*/RAS*

The pin function is switched as shown below according to the operating mode, bit EXPE, bit

PGnDDR, bit CSnE, and bits RMTS2 to RMTS0.

Operating

mode 1, 2, 4, 5, 6 3*, 7

EXPE — 0 1

CSnE 0 1 — 0 1

RMTS2 to

RMTS0 — Area n

normal space Area n

DRAM

space

Area 3

synchro-

nous

DRAM*

space

Area 2

synchro-

nous

DRAM*

space

— — Area n

normal space Area n

DRAM

space

Area 3

synchro-

nous

DRAM*

space

Area 2

synchro-

nous

DRAM*

space

PGnDDR0101 — — — 010101 — — —

Pin function PGn

input PGn

output PGn

input

CSn

output

RASn

output

CAS*

output

RAS*

output PGn

input PGn

output PGn

input PGn

output PGn

input

CSn

output

RASn

output

CAS*

output

RAS*

output

(n = 3 or 2)

Note: *Only in H8S/2678R Group.

• PG1/CS1, PG0/CS0

The pin function is switched as shown below according to the operating mode, bit EXPE, bit

PGnDDR, and bit CSnE.

Operating

mode 1, 2, 4, 5, 6 3*, 7

EXPE — 0 1

CSnE 0 1 — 0 1

PGnDDR 0101010101

Pin function PGn

input PGn

output PGn

input CSn

output PGn

input PGn

output PGn

input PGn

output PGn

input CSn

output

(n =1 or 0)

Note: *Only in H8S/2678R Group.

Section 10 I/O Ports

Rev. 3.00 Mar 17, 2006 page 516 of 926

REJ09B0283-0300

10.16 Port H

Port H is a 4-bit I/O port that also has other functions. The port H has the following registers. For

details on the port function control register 0, refer to section 10.15.4, Port Function Control

Port Function Control Register 2 (PFCR2).

• Port H data direction register (PHDDR)

• Port H data register (PHDR)

• Port H register (PORTH)

• Port Function Control Register 0 (PFCR0)

• Port Function Control Register 2 (PFCR2)

Section 10 I/O Ports

Rev. 3.00 Mar 17, 2006 page 517 of 926

REJ09B0283-0300

10.16.1 Port H Data Direction Register (PHDDR)

The individual bits of PHDDR specify input or output for the pins of port H.

PHDDR cannot be read; if it is, an undefined value will be read.

Bit Bit Name Initial Value R/W Description

— All 0 — Reserved

If these bits are read, they will return an undefined

value.

3 PH3DDR 0 W

2 PH2DDR 0 W

1 PH1DDR 0 W

0 PH0DDR 0 W

• Modes 1, 2, 3* (when EXPE = 1), 4, 5, 6, and 7

(when EXPE = 1)

When the OE output enable bit (OEE) and OE

output select bit (OES) are set to 1, pin PH3

functions as the OE output pin. Otherwise, when bit

CS7E is set to 1, pin PH3 functions as a CS output

pin when the corresponding PHDDR bi t is set to 1,

and as an input port when the bit is cleared to 0.

When bit CS7E is cleared to 0, pin PH3 is an I/O

port, and its function can be switched with PHDDR.

When the CS output enable bits (CS6E to CS4E)

are set to 1, pins PH2 to PH0 function as CS output

pins when the corresponding PHDDR bit is set to 1,

and as I/O ports when the bit is cleared to 0. When

CS6E to CS4E are cleared to 0, pins PH2 to PH0

are I/O ports, and their functions can be switched

with PHDDR.

• Mode 3* (EXPE = 0) and Mode 7 (when EXPE =

Pins PH3 to PH0 are I/O ports, and their functions

can be switched with PHDDR.

Note: *Only in H8S/2678R Group.

Section 10 I/O Ports

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REJ09B0283-0300

10.16.2 Port H Data Register (PHDR)

PHDR stores output data for the port H pins.

Bit Bit Name Initial Value R/W Description

— All 0 — Reserved

These bits are reserved; they are always read as 0

and cannot be modified.

3 PH3DR 0 R/W

2 PH2DR 0 R/W

1 PH1DR 0 R/W

0 PH0DR 0 R/W

Output data for a pin is stored when the pin function

is specified to a general purpose I/O.

10.16.3 Port H Register (PORTH)

PORTH shows port H pin states.

PORTH cannot be modified.

Bit Bit Name Initial Value R/W Description

— Undefined — Reserved

If these bits are read, they will return an undefined

value.

3 PH3 Undefined*R

2 PH2 Undefined*R

1 PH1 Undefined*R

0 PH0 Undefined*R

If a port H read is performed while PHDDR bits are

set to 1, the PHDR values are read. If a port H read

is performed while PHDDR bits are cleared to 0, the

pin states are read.

Note: *Determined by the states of pins PH3 to PH0.

Section 10 I/O Ports

Rev. 3.00 Mar 17, 2006 page 519 of 926

REJ09B0283-0300

10.16.4 Pin Functions

Port H pins also function as bus control signal I/Os and external interrupt inputs. The

correspondence between the register specification and the pin functions is shown below.

• PH3/CS7/OE/CKE*2/(IRQ7)

The pin function is switched as shown below according to the operating mode, bit EXPE, bit

OEE, bit OES, bit CS7E, an d bit PH3DDR.

Operating

mode 1, 2, 4, 5, 6 3*2, 7

EXPE — 0 1

CEE 0 1 — 0 1

CES — 0 1 — 0 1

Area

2 to 5 — — Normal

space

DRAM

space

syn-

chronous

DRAM

space*2

— — — Normal

space

DRAM

space

syn-

chronous

DRAM

space*2

CS7E0101———0101——

PH3DDR01010101— — 0101010101— —

PH3

input PH3

output PH3

input

CS7

output PH3

input PH3

output PH3

input

CS7

output

output CKE*2

output PH3

input PH3

output PH3

input PH3

output PH3

input

CS7

output PH3

input PH3

output PH3

input

CS7

output

output CKE*2

output

function

IRQ7 input*1

Notes: 1. IRQ7 interrupt input pin when bit ITS7 is set to 1 in ITSR

2. Only in H8S/2678R Group.

• PH2/CS6/(IRQ6)

The pin function is switched as shown below according to the operating mode, bit PH2DDR,

and bit CS6E.

Operating

mode 1, 2, 4, 5, 6 3*2, 7

EXPE — 0 1

CS6E 0 1 — 0 1

PH2DDR 0101010101

PH2

input PH2

output PH2

input CS6

output PH2

input PH2

output PH2

input PH2

output PH2

input CS6

output

Pin function

IRQ6 interrupt input*1

Notes: 1. IRQ6 interrupt input pin when bit ITS6 is set to 1 in ITSR.

2. Only in H8S/2678R Group.

Section 10 I/O Ports

Rev. 3.00 Mar 17, 2006 page 520 of 926

REJ09B0283-0300

• PH1/CS5/RAS5*/SDRAMφ*

The pin function is switched as shown below accord ing to the operating mode, DCTL pin, bit

EXPE, bit CS5E, bits RMTS2 to RMTS0, and bit PH1DDR.

Operating

mode 1, 2, 4, 5, 6 3*, 7 —

EXPE — 0 1 —

Area 5 Normal space DRAM space — Normal space DRAM space —

DCTL 0 1

CS5E 0101—0101—

PH1DDR 010101—01010101— —

Pin function PH1

input PH1

output PH1

input

CS5

output PH1

input PH1

output

RAS5*

output PH1

input PH1

output PH1

input PH1

output PH1

input

CS5

output PH1

input PH1

output

RAS5*

output SDRAM*

φ output

Note: *Only in H8S/2678R Group.

• PH0/CS4/RAS4*/WE*

The pin function is switched as shown below according to the operating mode, bit EXPE, bit

CS4E, bits RMTS2 to RMTS0, and bit PH0DDR.

Operating

mode 1, 2, 4, 5, 6 3*, 7

EXPE — 0 1

Area 4 — No rmal space DRAM

space Syn-

chronous

DRAM*

space

— — Normal space DRAM

space Syn-

chronous

DRAM*

space

SC4E 0 1 — 0 1

PH1DDR0101——010101——

Pin function PH0

input PH0

output PH0

input

CS4

output

RAS4*

output

WE*

output PH0

input PH0

output PH0

input PH0

output PH0

input

CS4

output

RAS4*

output

WE*

output

Note: *Only in H8S/2678R Group.

Section 11 16-Bit Ti mer Pulse Unit (TPU)

Rev. 3.00 Mar 17, 2006 page 521 of 926

REJ09B0283-0300

Section 11 16-Bit Timer Pulse Unit (TPU)

This LSI has an on-chip 16-bit timer pulse unit (TPU) that comprises six 16-bit timer channels.

The function list of the 16-bit timer unit and its block diagram are shown in table 11.1 and figure

11.1, respectively.

11.1 Features

• Maximum 16-pulse input/output

• Selection of 8 counter input clocks for each channel

• The following operations can be set for each channel:

Waveform output at compare match

Input capture function

Counter clear operation

Synchronous operations:

Multiple timer counters (TCNT) can be written to simultaneously

Simultaneous clearing by compare match and input capture possible

Maximum of 15-phase PWM output possible by combination with synchronous operation

• Buffer operation settable for channels 0 and 3

• Phase counting mode settable independently for each of channels 1, 2, 4, and 5

• Cascaded operation

• Fast access via internal 16-bit bus

• 26 interrupt sources

• Automatic tran sf er of r egister data

• Programmable pulse generator (PPG) output trigger can be generated

• A/D converter conversion start trigger can be generated

• Module stop mode can be set

TIMTPU0A_010020020400

Section 11 16-Bit Ti mer Pulse Unit (TPU)

Rev. 3.00 Mar 17, 2006 page 522 of 926

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Table 11.1 TPU Functions

Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5

Count clock φ/1

φ/4

φ/16

φ/64

TCLKA

TCLKB

TCLKC

TCLKD

φ/1

φ/4

φ/16

φ/64

φ/256

TCLKA

TCLKB

φ/1

φ/4

φ/16

φ/64

φ/1024

TCLKA

TCLKB

TCLKC

φ/1

φ/4

φ/16

φ/64

φ/256

φ/1024

φ/4096

TCLKA

φ/1

φ/4

φ/16

φ/64

φ/1024

TCLKA

TCLKC

φ/1

φ/4

φ/16

φ/64

φ/256

TCLKA

TCLKC

TCLKD

General registers

(TGR) TGRA_0

TGRB_0 TGRA_1

TGRB_1 TGRA_2

TGRB_2 TGRA_3

TGRB_3 TGRA_4

TGRB_4 TGRA_5

TGRB_5

General registers/

buffer registers TGRC_0

TGRD_0 ——TGRC_3

TGRD_3 ——

I/O pins TIOCA0

TIOCB0

TIOCC0

TIOCD0

TIOCA1

TIOCB1 TIOCA2

TIOCB2 TIOCA3

TIOCB3

TIOCC3

TIOCD3

TIOCA4

TIOCB4 TIOCA5

TIOCB5

Counter clear

function TGR

compare

match or

input

capture

TGR

compare

match or

input

capture

TGR

compare

match or

input

capture

TGR

compare

match or

input

capture

TGR

compare

match or

input

capture

TGR

compare

match or

input

capture

0 output

1 output

Compare

match

output Toggle

output

Input capture

function

Synchronous

operation

PWM mode

Phase counting

mode — —

Buffer operation —— ——

Section 11 16-Bit Ti mer Pulse Unit (TPU)

Rev. 3.00 Mar 17, 2006 page 523 of 926

REJ09B0283-0300

Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 C hannel 5

DTC

activation TGR

compare

match or

input capture

TGR

compare

match or

input capture

TGR

compare

match or

input capture

TGR

compare

match or

input capture

TGR

compare

match or

input capture

TGR

compare

match or

input capture

DMAC

activation TGRA_0

compare

match or

input capture

TGRA_1

compare

match or

input capture

TGRA_2

compare

match or

input capture

TGRA_3

compare

match or

input capture

TGRA_4

compare

match or

input capture

TGRA_5

compare

match or

input capture

A/D

converter

trigger

TGRA_0

compare

match or

input capture

TGRA_1

compare

match or

input capture

TGRA_2

compare

match or

input capture

TGRA_3

compare

match or

input capture

TGRA_4

compare

match or

input capture

TGRA_5

compare

match or

input capture

PPG

trigger TGRA_0/

TGRB_0

compare

match or

input capture

TGRA_1/

TGRB_1

compare

match or

input capture

TGRA_2/

TGRB_2

compare

match or

input capture

TGRA_3/

TGRB_3

compare

match or

input capture

——

Interrupt

sources 5 sources

• Compare

match or

input

capture 0A

Compare

match or

input

capture 0B

• Compare

match or

input

capture 0C

• Compare

match or

input

capture 0D

•Overflow

4 sources

• Compare

match or

input

capture 1A

• Compare

match or

input

capture 1B

•Overflow

• Underflow

4 sources

• Compare

match or

input

capture 2A

• Compare

match or

input

capture 2B

•Overflow

• Underflow

5 sources

• Compare

match or

input

capture 3A

• Compare

match or

input

capture 3B

• Compare

match or

input

capture 3C

• Compare

match or

input

capture 3D

•Overflow

4 sources

• Compare

match or

input

capture 4A

• Compare

match or

input

capture 4B

•Overflow

• Underflow

4 sources

• Compare

match or

input

capture 5A

• Compare

match or

input

capture 5B

•Overflow

• Underflow

Legend:

: Possible

— : Not possible

Section 11 16-Bit Ti mer Pulse Unit (TPU)

Rev. 3.00 Mar 17, 2006 page 524 of 926

REJ09B0283-0300

Channel 3

TMDR

TIORL

TSR

TCR

TIORH

TIER

TGRA

TCNT

TGRB

TGRC

TGRD

Channel 4

TMDR

TSR

TCR

TIOR

TIER

TGRA

TCNT

TGRB

Control logic TMDR

TSR

TCR

TIOR

TIER

TGRA

TCNT

TGRB

Control logic for channels 3 to 5

TMDR

TSR

TCR

TIOR

TIER

TGRA

TCNT

TGRB

TGRC

Channel 1

TMDR

TSR

TCR

TIOR

TIER

TGRA

TCNT

TGRB

Channel 0

TMDR

TSR

TCR

TIORH

TIER

Control logic for channels 0 to 2

TGRA

TCNT

TGRB

TGRD

TSYRTSTR

Input/output pins

TIOCA3

TIOCB3

TIOCC3

TIOCD3

TIOCA4

TIOCB4

TIOCA5

TIOCB5

Clock input

φ/1

φ/4

φ/16

φ/64

φ/256

φ/1024

φ/4096

TCLKA

TCLKB

TCLKC

TCLKD

Input/output pins

TIOCA0

TIOCB0

TIOCC0

TIOCD0

TIOCA1

TIOCB1

TIOCA2

TIOCB2

Interrupt request signals

Channel 3:

Channel 4:

Channel 5:

Interrupt request signals

Channel 0:

Channel 1:

Channel 2:

Internal data bus

A/D conversion start request signal

PPG output trigger signal

TIORL

Module data bus

TGI3A

TGI3B

TGI3C

TGI3D

TCI3V

TGI4A

TGI4B

TCI4V

TCI4U

TGI5A

TGI5B

TCI5V

TCI5U

TGI0A

TGI0B

TGI0C

TGI0D

TCI0V

TGI1A

TGI1B

TCI1V

TCI1U

TGI2A

TGI2B

TCI2V

TCI2U

Channel 3:

Channel 4:

Channel 5:

Internal clock:

External clock:

Channel 0:

Channel 1:

Channel 2:

Legend:

TSTR: Timer start register

TSYR: Timer synchronous register

TCR: Timer control register

TMDR: Timer mode register

TIOR (H, L): Timer I/O control registers (H, L)

TIER: Timer interrupt enable register

TSR: Timer status register

TGR (A, B, C, D): Timer general registers (A, B, C, D)

TCNT: Timer counter

Channel 2 Common Channel 5

Bus interface

Figure 11.1 Block Diagram of TPU

Section 11 16-Bit Ti mer Pulse Unit (TPU)

Rev. 3.00 Mar 17, 2006 page 525 of 926

REJ09B0283-0300

11.2 Input/Output Pins

Table 11.2 Pin Configuratio n

Channel Symbol I/O Function

All TCLKA Input External clock A input pin

(Channel 1 and 5 phase counting mode A phase input)

TCLKB Input External clo ck B input pin

(Channel 1 and 5 phase counting mode B phase input)

TCLKC Input External clock C inp ut pin

(Channel 2 and 4 phase counting mode A phase input)

TCLKD Input External clock D inp ut pin

(Channel 2 and 4 phase counting mode B phase input)

0 TIOCA0 I/O TGRA_0 input capture input/output compare output/PWM output pin

TIOCB0 I/O TGRB_0 input capture input/output compare output/PWM output pin

TIOCC0 I/O TGRC_0 input capture input/output compare output/PWM output pin

TIOCD0 I/O TGRD_0 input capture input/output compare output/PWM output pin

1 TIOCA1 I/O TGRA_1 input capture input/output compare output/PWM output pin

TIOCB1 I/O TGRB_1 input capture input/output compare output/PWM output pin

2 TIOCA2 I/O TGRA_2 input capture input/output compare output/PWM output pin

TIOCB2 I/O TGRB_2 input capture input/output compare output/PWM output pin

3 TIOCA3 I/O TGRA_3 input capture input/output compare output/PWM output pin

TIOCB3 I/O TGRB_3 input capture input/output compare output/PWM output pin

TIOCC3 I/O TGRC_3 input capture input/output compare output/PWM output pin

TIOCD3 I/O TGRD_3 input capture input/output compare output/PWM output pin

4 TIOCA4 I/O TGRA_4 input capture input/output compare output/PWM output pin

TIOCB4 I/O TGRB_4 input capture input/output compare output/PWM output pin

5 TIOCA5 I/O TGRA_5 input capture input/output compare output/PWM output pin

TIOCB5 I/O TGRB_5 input capture input/output compare output/PWM output pin

Section 11 16-Bit Ti mer Pulse Unit (TPU)

Rev. 3.00 Mar 17, 2006 page 526 of 926

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11.3 Register Descriptions

The TPU has the following registers in each channel.

• Timer control register_0 (TCR_0)

• Timer mode register_0 (TMDR _0)

• Timer I/O control register H_0 (TIORH_0)

• Timer I/O contro l register L_0 (TIORL_0)

• Timer interrupt en able register_0 (TIER_0)

• Timer status register_0 (TSR_0)

• Timer counter_0 (TCNT_0)

• Timer general register A_0 (TGRA_0)

• Timer general register B_0 (TGRB_0)

• Timer general register C_0 (TGRC_0)

• Timer general register D_0 (TGRD_0)

• Timer control register_1 (TCR_1)

• Timer mode register_1 (TMDR _1)

• Timer I/O control register _1 (TIOR_1)

• Timer interrupt en able register_1 (TIER_1)

• Timer status register_1 (TSR_1)

• Timer counter_1 (TCNT_1)

• Timer general register A_1 (TGRA_1)

• Timer general register B_1 (TGRB_1)

• Timer control register_2 (TCR_2)

• Timer mode register_2 (TMDR _2)

• Timer I/O control register_2 (TIOR_2)

• Timer interrupt en able register_2 (TIER_2)

• Timer status register_2 (TSR_2)

• Timer counter_2 (TCNT_2)

• Timer general register A_2 (TGRA_2)

• Timer general register B_2 (TGRB_2)

• Timer control register_3 (TCR_3)

• Timer mode register_3 (TMDR _3)

• Timer I/O control register H_3 (TIORH_3)

• Timer I/O contro l register L_3 (TIORL_3)

Section 11 16-Bit Ti mer Pulse Unit (TPU)

Rev. 3.00 Mar 17, 2006 page 527 of 926

REJ09B0283-0300

• Timer interrupt enable register_3 (TIER_3)

• Timer status register_3 (TSR_3)

• Timer counter_3 (TCNT_3)

• Timer general register A_3 (TGRA_3)

• Timer general register B_3 (TGRB_3)

• Timer general register C_3 (TGRC_3)

• Timer general register D_3 (TGRD_3)

• Timer control register_4 (TCR_4)

• Timer mode register_4 (TMDR _4)

• Timer I/O control register _4 (TIOR_4)

• Timer interrupt enable register_4 (TIER_4)

• Timer status register_4 (TSR_4)

• Timer counter_4 (TCNT_4)

• Timer general register A_4 (TGRA_4)

• Timer general register B_4 (TGRB_4)

• Timer control register_5 (TCR_5)

• Timer mode register_5 (TMDR _5)

• Timer I/O control register_5 (TIOR_5)

• Timer interrupt enable register_5 (TIER_5)

• Timer status register_5 (TSR_5)

• Timer counter_5 (TCNT_5)

• Timer general register A_5 (TGRA_5)

• Timer general register B_5 (TGRB_5)

Common Registers

• Timer sta rt registe r (TSTR)

• Timer synchronous register (TSYR)

Section 11 16-Bit Ti mer Pulse Unit (TPU)

Rev. 3.00 Mar 17, 2006 page 528 of 926

REJ09B0283-0300

11.3.1 Timer Control Register (TCR)

The TCR registers control the TCNT operation for each channel. The TPU has a total of six TCR

registers, one for each channel. TCR register settings should be made only when TCNT operation

is stopped.

Bit Bit Name Initial Value R/W Description

CCLR2

CCLR1

CCLR0

R/W

Counter Clear 2 to 0

These bits select the TCNT cou nter cl earing source.

See tables 11.3 and 11.4 for detail s.

3CKEG1

CKEG0 0

0R/W

R/W Clock Edge 1 and 0

These bits select the input cl ock edge. When the

input clock is counted using both edges, the input

clock period is halved (e.g. φ/4 both edges = φ/2

rising edge). If phase counting mode is used on

channels 1, 2, 4, and 5, this setting is ignored and

the phase counting mode setting has priority. Internal

clock edge selection is valid when the input clock is

φ/4 or slower. This setting is ignored if the input clock

is φ/1, or when overflow/underflow of another

channel is se lec ted.

00: Count at rising edge

01: Count at falling edge

1x: Count at both edges

Legend: x: Don’t care

TPSC2

TPSC1

TPSC0

R/W

Time Prescaler 2 to 0

These bits select the TCNT cou nter cl oc k. The cloc k

source can be sele cte d indep end entl y for each

channel. See tables 11.5 to 11.10 for details.

Section 11 16-Bit Ti mer Pulse Unit (TPU)

Rev. 3.00 Mar 17, 2006 page 529 of 926

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Table 11.3 CCLR2 to CCLR0 (Channels 0 and 3)

Channel Bit 7

CCLR2 Bit 6

CCLR1 Bit 5

CCLR0 Description

0, 3 0 0 0 TCNT cl earing disabled

1 TCNT cleared by TGRA compare match/input

capture

1 0 TCNT cleared by TGRB compare match/input

capture

1 TCNT cleared by counter clearin g for another

channel perf orm ing syn chr onous clearing/

synchronous operation*1

1 0 0 TCNT clearing dis abled

1 TCNT cleared by TGRC compare matc h/input

capture*2

1 0 TCNT cleared by TGRD compare match/input

capture*2

1 TCNT cleared by counter clearin g for another

channel perf orm ing syn chr onous clearing/

synchronous operation*1

Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.

2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the

buffer register setting has priority, and compare match/input capture does not occur.

Table 11.4 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5)

Channel Bit 7

Reserved*2Bit 6

CCLR1 Bit 5

CCLR0 Description

1, 2, 4, 5 0 0 0 TCNT clearing disabl ed

1 TCNT cleared by TGRA compare match/input

capture

1 0 TCNT cleared by TGRB compare match/input

capture

1 TCNT cleared by counter cle arin g for another

channel perf orm ing syn chr onous clearing/

synchronous operation*1

Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.

2. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be

modified.

Section 11 16-Bit Ti mer Pulse Unit (TPU)

Rev. 3.00 Mar 17, 2006 page 530 of 926

REJ09B0283-0300

Table 11.5 TPSC2 t o TPSC0 (Channel 0)

Channel Bit 2

TPSC2 Bit 1

TPSC1 Bit 0

TPSC0 Description

0 0 0 0 Intern al clo ck: co unts on φ/1

1 Internal clock: co unts on φ/4

1 0 Internal clock: counts on φ/16

1 Internal clock: co unts on φ/64

1 0 0 External clock: count s on TCLKA pin input

1 External clock: co unt s on TCLKB pin input

1 0 External clock: count s on TCLKC pin input

1 External clock: co unt s on TCLKD pin input

Table 11.6 TPSC2 t o TPSC0 (Channel 1)

Channel Bit 2

TPSC2 Bit 1

TPSC1 Bit 0

TPSC0 Description

1 0 0 0 Intern al clo ck: co unts on φ/1

1 Internal clock: co unts on φ/4

1 0 Internal clock: counts on φ/16

1 Internal clock: co unts on φ/64

1 0 0 External clock: count s on TCLKA pin input

1 External clock: co unt s on TCLKB pin input

1 0 Internal clock: counts on φ/256

1 Counts on TCNT2 ov erflow/underflow

Note: This setting is ignored when channel 1 is in phase counting mode.

Section 11 16-Bit Ti mer Pulse Unit (TPU)

Rev. 3.00 Mar 17, 2006 page 531 of 926

REJ09B0283-0300

Table 11.7 TPSC2 t o TPSC0 (Channel 2)

Channel Bit 2

TPSC2 Bit 1

TPSC1 Bit 0

TPSC0 Description

2 0 0 0 Intern al clo ck: co unts on φ/1

1 Internal clock: co unts on φ/4

1 0 Internal clock: counts on φ/16

1 Internal clock: co unts on φ/64

1 0 0 External clock: count s on TCLKA pin input

1 External clock: co unt s on TCLKB pin input

1 0 External clock: count s on TCLKC pin input

1 Internal clock: co unts on φ/1024

Note: This setting is ignored when channel 2 is in phase counting mode.

Table 11.8 TPSC2 t o TPSC0 (Channel 3)

Channel Bit 2

TPSC2 Bit 1

TPSC1 Bit 0

TPSC0 Description

3 0 0 0 Intern al clo ck: co unts on φ/1

1 Internal clock: co unts on φ/4

1 0 Internal clock: counts on φ/16

1 Internal clock: co unts on φ/64

1 0 0 External clock: count s on TCLKA pin input

1 Internal clock: co unts on φ/1024

1 0 Internal clock: counts on φ/256

1 Internal clock: co unts on φ/4096

Section 11 16-Bit Ti mer Pulse Unit (TPU)

Rev. 3.00 Mar 17, 2006 page 532 of 926

REJ09B0283-0300

Table 11.9 TPSC2 t o TPSC0 (Channel 4)

Channel Bit 2

TPSC2 Bit 1

TPSC1 Bit 0

TPSC0 Description

4 0 0 0 Intern al clo ck: co unts on φ/1

1 Internal clock: co unts on φ/4

1 0 Internal clock: counts on φ/16

1 Internal clock: co unts on φ/64

1 0 0 External clock: count s on TCLKA pin input

1 External clock: co unt s on TCLKC pin input

1 0 Internal clock: counts on φ/1024

1 Counts on TCNT5 ov erflow/underflow

Note: This setting is ignored when channel 4 is in phase counting mode.

Table 11. 10 TPSC2 to TPSC0 (Channel 5)

Channel Bit 2

TPSC2 Bit 1

TPSC1 Bit 0

TPSC0 Description

5 0 0 0 Intern al clo ck: co unts on φ/1

1 Internal clock: co unts on φ/4

1 0 Internal clock: counts on φ/16

1 Internal clock: co unts on φ/64

1 0 0 External clock: count s on TCLKA pin input

1 External clock: co unt s on TCLKC pin input

1 0 Internal clock: counts on φ/256

1 External clock: co unt s on TCLKD pin input

Note: This setting is ignored when channel 5 is in phase counting mode.

Section 11 16-Bit Ti mer Pulse Unit (TPU)

Rev. 3.00 Mar 17, 2006 page 533 of 926

REJ09B0283-0300

11.3.2 Timer Mode Register (TMDR)

TMDR registers are used to set the operating mode for each channel. The TPU has six TMDR

registers, one for each channel. TMDR register settings should be made only when TCNT

operation is stopped.

Bit Bit Name Initial Value R/W Description

7, 6 —All 1 —Reserved

These bits are always read as 1 and cannot be

modified.

5 BFB 0 R/W Buffer Operation B

Specifies whether TGRB is to operate in the normal

way, or TGRB and TGRD are to be used together for

buffer operation. When TGRD is used as a buffer

generated.

In channels 1, 2, 4, and 5, which have no TGRD, bit

5 is reserved. It is always read as 0 and cannot be

modified.

0: TGRB operates normally

1: TGRB and TGRD used together for buffer

operation

4 BFA 0 R/W Buffer Operation A

Specifies whether TGRA is to operate in the normal

way, or TGRA and TGRC are to be used together for

buffer operation. When TGRC is used as a buffer

generated.

In channels 1, 2, 4, and 5, which have no TGRC, bit

4 is reserved. It is always read as 0 and cannot be

modified.

0: TGRA operates normally

1: TGRA and TGRC used together for buffer

operation

MD3

MD2

MD1

MD0

R/W

Modes 3 to 0

These bits are used to set the timer operating mode.

MD3 is a reserved bit. In a write, it should always be

written with 0. See table 11.11 for details.

Section 11 16-Bit Ti mer Pulse Unit (TPU)

Rev. 3.00 Mar 17, 2006 page 534 of 926

REJ09B0283-0300

Table 11.11 MD3 to MD0

Bit 3

MD3*1Bit 2

MD2*2Bit 1

MD1 Bit 0

MD0 Description

0 0 0 0 Normal operation

1 Reserved

1 0 PWM mode 1

1 PWM mode 2

1 0 0 Phase counting mode 1

1 Phase counting mode 2

1 0 Phase counting mode 3

1 Phase counting mode 4

1xxx—

Legend: x: Don’t care

Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0.

2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always

be written to MD2.

11.3.3 Timer I/O Control Register (TIOR)

TIOR registers control the TGR registers. The TPU has eight TIOR registers, two each for

channels 0 and 3, and one each for channels 1, 2, 4, and 5. Care is required since TIOR is affected

by the TMDR setting.

The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is

cleared to 0). Note also th at, in PWM mo de 2, the output at the point at wh ich the counter is

cleared to 0 is specified.

When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register

operates as a buffer register.

Section 11 16-Bit Ti mer Pulse Unit (TPU)

Rev. 3.00 Mar 17, 2006 page 535 of 926

REJ09B0283-0300

TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5

Bit Bit Name Initial Value R/W Description

IOB3

IOB2

IOB1

IOB0

R/W

I/O Control B3 to B0

Specify the function of TGRB.

For details, see tables 11. 12, 11.14 , 11. 15, 11.1 6,

11.18, and 11.19.

IOA3

IOA2

IOA1

IOA0

R/W

I/O Control A3 to A0

Specify the function of TGRA.

For details, see tables 11. 20, 11.22 , 11. 23, 11.2 4,

11.26, and 11.27.

TIOR L_0, TIORL_3

Bit Bit Name Initial Value R/W Description

IOD3

IOD2

IOD1

IOD0

R/W

I/O Control D3 to D0

Specify the function of TGRD.

For details, see tables 11. 13, and 11.17 .

IOC3

IOC2

IOC1

IOC0

R/W

I/O Control C3 to C0

Specify the function of TGRC.

For details, see tables 11. 21, and 11.25

Section 11 16-Bit Ti mer Pulse Unit (TPU)

Rev. 3.00 Mar 17, 2006 page 536 of 926

REJ09B0283-0300

Table 11.12 TIORH_0

Description

Bit 7

IOB3 Bit 6

IOB2 Bit 5

IOB1 Bit 4

IOB0 TGRB_0

Function TIOCB0 Pin Function

0 0 0 0 Output disabled

Output

compare

0 output at compare match

1 0 Initial output is 0 output

1 output at compare match

1 Initial output is 0 output

Toggle output at compare match

1 0 0 Output disabled

1 Initial output is 1 output

0 output at compare match

1 0 Initial output is 1 output

1 output at compare match

1 Initial output is 1 output

Toggle output at compare match

1 0 0 0 Capture input source is TIOCB0 pin

Input capture at rising edge

1 Capture input source is TIOCB0 pin

Input capture at falling edge

Input

capture

Capture input source is TIOCB0 pin

Input capture at both edges

1 x x Capture input source is channel 1/count clock

Input capture at TCNT_1 count- up/ cou nt-dow n*

Legend: x: Don’t care

Note: *When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and φ/1 is used as the TCNT_1

count clock, this setting is invalid and input capture is not generated.

Section 11 16-Bit Ti mer Pulse Unit (TPU)

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Table 11.13 TIORL_0

Description

Bit 7

IOD3 Bit 6

IOD2 Bit 5

IOD1 Bit 4

IOD0 TGRD_0

Function TIOCD0 Pin Function

0 0 0 0 Output disabled

Output

compare

0 output at compare match

1 0 Initial output is 0 output

1 output at compare match

1 Initial output is 0 output

Toggle output at compare match

1 0 0 Output disabled

1 Initial output is 1 output

0 output at compare match

1 0 Initial output is 1 output

1 output at compare match

1 Initial output is 1 output

Toggle output at compare match

1 0 0 0 Capture input source is TIOCD0 pin

Input capture at rising edge

1 Capture input source is TIOCD0 pin

Input capture at falling edge

Input

capture

Capture input source is TIOCD0 pin

Input capture at both edges

1 x x Capture input source is channel 1/count clock

Input capture at TCNT_1 count-u p/ coun t-dow n*1

Legend: x: Don’t care

Notes: 1. When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and φ/1 is used as the TCNT_1

count clock, this setting is invalid and input capture is not generated.

2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this

setting is invali d and input cap ture/output compare is not generate d.

Section 11 16-Bit Ti mer Pulse Unit (TPU)

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Table 11.14 TIOR_1

Description

Bit 7

IOB3 Bit 6

IOB2 Bit 5

IOB1 Bit 4

IOB0 TGRB_1

Function TIOCB1 Pin Function

0 0 0 0 Output disabled

Output

compare

0 output at compare match

1 0 Initial output is 0 output

1 output at compare match

1 Initial output is 0 output

Toggle output at compare match

1 0 0 Output disabled

1 Initial output is 1 output

0 output at compare match

1 0 Initial output is 1 output

1 output at compare match

1 Initial output is 1 output

Toggle output at compare match

1 0 0 0 Capture input source is TIOCB1 pin

Input capture at rising edge

1 Capture input source is TIOCB1 pin

Input capture at falling edge

Input

capture

Capture input source is TIOCB1 pin

Input capture at both edges

1 x x TGRC_0 compare match/input capture

Input capture at generation of TGRC_0 compare

match/input ca pture

Legend: x: Don’t care

Section 11 16-Bit Ti mer Pulse Unit (TPU)

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Table 11.15 TIOR_2

Description

Bit 7

IOB3 Bit 6

IOB2 Bit 5

IOB1 Bit 4

IOB0 TGRB_2

Function TIOCB2 Pin Function

0 0 0 0 Output disabled

Output

compare

0 output at compare match

1 0 Initial output is 0 output

1 output at compare match

1 Initial output is 0 output

Toggle output at compare match

1 0 0 Output disabled

1 Initial output is 1 output

0 output at compare match

1 0 Initial output is 1 output

1 output at compare match

1 Initial output is 1 output

Toggle output at compare match

1 x 0 0 Capture input source is TIOCB2 pin

Input capture at rising edge

1 Capture input source is TIOCB2 pin

Input capture at falling edge

Input

capture

Capture input source is TIOCB2 pin

Input capture at both edges

Legend: x: Don’t care

Section 11 16-Bit Ti mer Pulse Unit (TPU)

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Table 11.16 TIORH_3

Description

Bit 7

IOB3 Bit 6

IOB2 Bit 5

IOB1 Bit 4

IOB0 TGRB_3

Function TIOCB3 Pin Function

0 0 0 0 Output disabled

Output

compare

0 output at compare match

1 0 Initial output is 0 output

1 output at compare match

1 Initial output is 0 output

Toggle output at compare match

1 0 0 Output disabled

1 Initial output is 1 output

0 output at compare match

1 0 Initial output is 1 output

1 output at compare match

1 Initial output is 1 output

Toggle output at compare match

1 0 0 0 Capture input source is TIOCB3 pin

Input capture at rising edge

1 Capture input source is TIOCB3 pin

Input capture at falling edge

Input

capture

Capture input source is TIOCB3 pin

Input capture at both edges

1 x x Capture input source is channel 4/count clock

Input capture at TCNT_4 count-u p/ coun t-dow n*

Legend: x: Don’t care

Note: *When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and φ/1 is used as the TCNT_4

count clock, this setting is invalid and input capture is not generated.

Section 11 16-Bit Ti mer Pulse Unit (TPU)

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Table 11.17 TIORL_3

Description

Bit 7

IOD3 Bit 6

IOD2 Bit 5

IOD1 Bit 4

IOD0 TGRD_3

Function TIOCD3 Pin Function

0 0 0 0 Output disabled

Output

compare

0 output at compare match

1 0 Initial output is 0 output

1 output at compare match

1 Initial output is 0 output

Toggle output at compare match

1 0 0 Output disabled

1 Initial output is 1 output

0 output at compare match

1 0 Initial output is 1 output

1 output at compare match

1 Initial output is 1 output

Toggle output at compare match

1 0 0 0 Capture input source is TIOCD3 pin

Input capture at rising edge

1 Capture input source is TIOCD3 pin

Input capture at falling edge

Input

capture

Capture input source is TIOCD3 pin

Input capture at both edges

1 x x Capture input source is channel 4/count clock

Input capture at TCNT_4 count-u p/ coun t-dow n*1

Legend: x: Don’t care

Notes: 1. When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and φ/1 is used as the TCNT_4

count clock, this setting is invalid and input capture is not generated.

2. When the BFB bit in TMDR_3 is set to 1 and TGRD_3 is used as a buffer register, this

setting is invali d and input cap ture/output compare is not generate d.

Section 11 16-Bit Ti mer Pulse Unit (TPU)

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Table 11.18 TIOR_4

Description

Bit 7

IOB3 Bit 6

IOB2 Bit 5

IOB1 Bit 4

IOB0 TGRB_4

Function TIOCB4 Pin Function

0 0 0 0 Output disabled

Output

compare

0 output at compare match

1 0 Initial output is 0 output

1 output at compare match

1 Initial output is 0 output

Toggle output at compare match

1 0 0 Output disabled

1 Initial output is 1 output

0 output at compare match

1 0 Initial output is 1 output

1 output at compare match

1 Initial output is 1 output

Toggle output at compare match

1 0 0 0 Capture input source is TIOCB4 pin

Input capture at rising edge

1 Capture input source is TIOCB4 pin

Input capture at falling edge

Input

capture

Capture input source is TIOCB4 pin

Input capture at both edges

1 x x Capture input source is TGRC_3 compare

match/input ca pture

Input capture at generation of TGRC_3 compare

match/input ca pture

Legend: x: Don’t care

Section 11 16-Bit Ti mer Pulse Unit (TPU)

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Table 11.19 TIOR_5

Description

Bit 7

IOB3 Bit 6

IOB2 Bit 5

IOB1 Bit 4

IOB0 TGRB_5

Function TIOCB5 Pin Function

0 0 0 0 Output disabled

Output

compare

0 output at compare match

1 0 Initial output is 0 output

1 output at compare match

1 Initial output is 0 output

Toggle output at compare match

1 0 0 Output disabled

1 Initial output is 1 output

0 output at compare match

1 0 Initial output is 1 output

1 output at compare match

1 Initial output is 1 output

Toggle output at compare match

1 x 0 0 Capture input source is TIOCB5 pin

Input capture at rising edge

1 Capture input source is TIOCB5 pin

Input capture at falling edge

Input

capture

Capture input source is TIOCB5 pin

Input capture at both edges

Legend: x: Don’t care

Section 11 16-Bit Ti mer Pulse Unit (TPU)

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Table 11.20 TIORH_0

Description

Bit 3

IOA3 Bit 2

IOA2 Bit 1

IOA1 Bit 0

IOA0 TGRA_0

Function TIOCA0 Pin Function

0 0 0 0 Output disabled

Output

compare

0 output at compare match

1 0 Initial output is 0 output

1 output at compare match

1 Initial output is 0 output

Toggle output at compare match

1 0 0 Output disabled

1 Initial output is 1 output

0 output at compare match

1 0 Initial output is 1 output

1 output at compare match

1 Initial output is 1 output

Toggle output at compare match

1 0 0 0 Capture input source is TIOCA0 pin

Input capture at rising edge

1 Capture input source is TIOCA0 pin

Input capture at falling edge

Input

capture

Capture input source is TIOCA0 pin

Input capture at both edges

1 x x Capture input source is channel 1/count clock

Input capture at TCNT_1 count-u p/ coun t-dow n

Legend: x: Don’t care

Section 11 16-Bit Ti mer Pulse Unit (TPU)

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Table 11.21 TIORL_0

Description

Bit 3

IOC3 Bit 2

IOC2 Bit 1

IOC1 Bit 0

IOC0 TGRC_0

Function TIOCC0 Pin Function

0 0 0 0 Output disabled

Output

compare

0 output at compare match

1 0 Initial output is 0 output

1 output at compare match

1 Initial output is 0 output

Toggle output at compare match

1 0 0 Output disabled

1 Initial output is 1 output

0 output at compare match

1 0 Initial output is 1 output

1 output at compare match

1 Initial output is 1 output

Toggle output at compare match

1 0 0 0 Capture input source is TIOCC0 pin

Input capture at rising edge

1 Capture input source is TIOCC0 pin

Input capture at falling edge

Input

capture

Capture input source is TIOCC0 pin

Input capture at both edges

1 x x Capture input source is channel 1/count clock

Input capture at TCNT_1 count-u p/ coun t-dow n

Legend: x: Don’t care

Note: *When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this

setting is invali d and input cap ture/output compare is not generate d.

Section 11 16-Bit Ti mer Pulse Unit (TPU)

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Table 11.22 TIOR_1

Description

Bit 3

IOA3 Bit 2

IOA2 Bit 1

IOA1 Bit 0

IOA0 TGRA_1

Function TIOCA1 Pin Function

0 0 0 0 Output disabled

Output

compare

0 output at compare match

1 0 Initial output is 0 output

1 output at compare match

1 Initial output is 0 output

Toggle output at compare match

1 0 0 Output disabled

1 Initial output is 1 output

0 output at compare match

1 0 Initial output is 1 output

1 output at compare match

1 Initial output is 1 output

Toggle output at compare match

1 0 0 0 Capture input source is TIOCA1 pin

Input capture at rising edge

1 Capture input source is TIOCA1 pin

Input capture at falling edge

Input

capture

Capture input source is TIOCA1 pin

Input capture at both edges

1 x x Capture input source is TGRA_0 compare

match/input ca pture

Input capture at generation of channel

0/TGRA_0 compare match/input capture

Legend: x: Don’t care

Section 11 16-Bit Ti mer Pulse Unit (TPU)

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Table 11.23 TIOR_2

Description

Bit 3

IOA3 Bit 2

IOA2 Bit 1

IOA1 Bit 0

IOA0 TGRA_2

Function TIOCA2 Pin Function

0 0 0 0 Output disabled

Output

compare

0 output at compare match

1 0 Initial output is 0 output

1 output at compare match

1 Initial output is 0 output

Toggle output at compare match

1 0 0 Output disabled

1 Initial output is 1 output

0 output at compare match

1 0 Initial output is 1 output

1 output at compare match

1 Initial output is 1 output

Toggle output at compare match

1 x 0 0 Capture input source is TIOCA2 pin

Input capture at rising edge

1 Capture input source is TIOCA2 pin

Input capture at falling edge

Input

capture

Capture input source is TIOCA2 pin

Input capture at both edges

Legend: x: Don’t care

Section 11 16-Bit Ti mer Pulse Unit (TPU)

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Table 11.24 TIORH_3

Description

Bit 3

IOA3 Bit 2

IOA2 Bit 1

IOA1 Bit 0

IOA0 TGRA_3

Function TIOCA3 Pin Function

0 0 0 0 Output disabled

Output

compare

0 output at compare match

1 0 Initial output is 0 output

1 output at compare match

1 Initial output is 0 output

Toggle output at compare match

1 0 0 Output disabled

1 Initial output is 1 output

0 output at compare match

1 0 Initial output is 1 output

1 output at compare match

1 Initial output is 1 output

Toggle output at compare match

1 0 0 0 Capture input source is TIOCA3 pin

Input capture at rising edge

1 Capture input source is TIOCA3 pin

Input capture at falling edge

Input

capture

Capture input source is TIOCA3 pin

Input capture at both edges

1 x x Capture input source is channel 4/count clock

Input capture at TCNT_4 count-u p/ coun t-dow n

Legend: x: Don’t care

Section 11 16-Bit Ti mer Pulse Unit (TPU)

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Table 11.25 TIORL_3

Description

Bit 3

IOC3 Bit 2

IOC2 Bit 1

IOC1 Bit 0

IOC0 TGRC_3

Function TIOCC3 Pin Function

0 0 0 0 Output disabled

Output

compare

0 output at compare match

1 0 Initial output is 0 output

1 output at compare match

1 Initial output is 0 output

Toggle output at compare match

1 0 0 Output disabled

1 Initial output is 1 output

0 output at compare match

1 0 Initial output is 1 output

1 output at compare match

1 Initial output is 1 output

Toggle output at compare match

1 0 0 0 Capture input source is TIOCC3 pin

Input capture at rising edge

1 Capture input source is TIOCC3 pin

Input capture at falling edge

Input

capture

Capture input source is TIOCC3 pin

Input capture at both edges

1 x x Capture input source is channel 4/count clock

Input capture at TCNT_4 count-u p/ coun t-dow n

Legend: x: Don’t care

Note: *When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this

setting is invali d and input cap ture/output compare is not generate d.

Section 11 16-Bit Ti mer Pulse Unit (TPU)

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Table 11.26 TIOR_4

Description

Bit 3

IOA3 Bit 2

IOA2 Bit 1

IOA1 Bit 0

IOA0 TGRA_4

Function TIOCA4 Pin Function

0 0 0 0 Output disabled

Output

compare

0 output at compare match

1 0 Initial output is 0 output

1 output at compare match

1 Initial output is 0 output

Toggle output at compare match

1 0 0 Output disabled

1 Initial output is 1 output

0 output at compare match

1 0 Initial output is 1 output

1 output at compare match

1 Initial output is 1 output

Toggle output at compare match

1 0 0 0 Capture input source is TIOCA4 pin

Input capture at rising edge

1 Capture input source is TIOCA4 pin

Input capture at falling edge

Input

capture

Capture input source is TIOCA4 pin

Input capture at both edges

1 x x Capture input source is TGRA_3 compare

match/input ca pture

Input capture at generation of TGRA_3 compare

match/input ca pture

Legend: x: Don’t care

Section 11 16-Bit Ti mer Pulse Unit (TPU)

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Table 11.27 TIOR_5

Description

Bit 3

IOA3 Bit 2

IOA2 Bit 1

IOA1 Bit 0

IOA0 TGRA_5

Function TIOCA5 Pin Function

0 0 0 0 Output disabled

Output

compare

0 output at compare match

1 0 Initial output is 0 output

1 output at compare match

1 Initial output is 0 output

Toggle output at compare match

1 0 0 Output disabled

1 Initial output is 1 output

0 output at compare match

1 0 Initial output is 1 output

1 output at compare match

1 Initial output is 1 output

Toggle output at compare match

1 x 0 0 Input cap ture sour ce is TIO C A5 pin

Input capture at rising edge

1 Input capture source is TIOCA5 pin

Input capture at falling edge

Input

capture

Input capture sour ce is TIO CA5 pin

Input capture at both edges

Legend: x: Don’t care

Section 11 16-Bit Ti mer Pulse Unit (TPU)

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11.3.4 Timer Interrupt Enable Register (TIER)

TIER registers control enab ling or disabling of interrupt requests for each channel. The TPU has

six TIER registers, one for each ch annel.

Bit Bit Name Initial value R/W Description

7 TTGE 0 R/W A/D Conversion Start Request Enable

Enables or disables generation of A/D conversion

start requests by TGRA input capture/compare

match.

0: A/D conversion start request gen erati on dis abl ed

1: A/D conversion start request gen erati on enab led

6 — 1 — Reserved

This bit is always read as 1 and cann ot be modif ied.

5 TCIEU 0 R/W Underflow Interrupt Enable

Enables or disables interrupt requests (TCIU) by the

TCFU flag when the TCFU flag in TSR is set to 1 in

channels 1, 2, 4, and 5.

In channels 0 and 3, bit 5 is reserved. It is always

read as 0 and cannot be modified.

0: Interrupt requests (TCIU) by TCFU disabled

1: Interrupt requests (TCIU) by TCFU enabled

4 TCIEV 0 R/W Overflow Interrupt Enable

Enables or disables interrupt requests (TCIV) by the

TCFV flag when the TCFV flag in TSR is set to 1.

0: Interrupt requests (TCIV) by TCFV disabled

1: Interrupt requests (TCIV) by TCFV enabled

3 TGIED 0 R/W TGR Interrupt Enable D

Enables or disables interrupt requests (TGID) by th e

TGFD bit when the TGFD bit in TSR is set to 1 in

channels 0 and 3.

In channels 1, 2, 4, and 5, bit 3 is reserved. It is

always read as 0 and cannot be modified.

0: Interrupt requests (TGID) by TGFD bit disabled

1: Interrupt requests (TGID) by TGFD bit enabled

Section 11 16-Bit Ti mer Pulse Unit (TPU)

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Bit Bit Name Initial value R/W Description

2 TGIEC 0 R/W TGR Interrupt Enable C

Enables or disables interrupt requests (TGIC) by th e

TGFC bit when the TGFC bit in TSR is set to 1 in

channels 0 and 3.

In channels 1, 2, 4, and 5, bit 2 is reserved. It is

always read as 0 and cannot be modified.

0: Interrupt requests (TGIC) by TGFC bit disabled

1: Interrupt requests (TGIC) by TGFC bit enabled

1 TGIEB 0 R/W TGR Interrupt Enable B

Enables or disables interrupt requests (TGIB) by the

TGFB bit when the TGFB bit in TSR is set to 1.

0: Interrupt requests (TGIB) by TGFB bit disabled

1: Interrupt requests (TGIB) by TGFB bit enabled

0 TGIEA 0 R/W TGR Interrupt Enable A

Enables or disables interrupt requests (TGIA) by the

TGFA bit when the TGFA bit in TSR is set to 1.

0: Interrupt requests (TGIA) by TGFA bit disabled

1: Interrupt requests (TGIA) by TGFA bit enabled

Section 11 16-Bit Ti mer Pulse Unit (TPU)

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11.3.5 Timer Status Register (TSR)

TSR registers indicate the status of each channel. The TPU has six TSR registers, one for each

channel.

Bit Bit Name Initial value R/W Description

7 TCFD 1 R Count Direction Flag

Status flag that shows the direction in which TCNT

counts in channels 1, 2, 4, and 5.

In channels 0 and 3, bit 7 is reserved. It is always

read as 1 and cannot be modified.

0: TCNT counts down

1: TCNT counts up

6 — 1 — Reserved

This bit is always read as 1 and cann ot be modif ied.

5 TCFU 0 R/(W)*Underflow Flag

Status flag that indicates that TCNT underflow has

occurred when channels 1, 2, 4, and 5 are set to

phase counting mode.

In channels 0 and 3, bit 5 is reserved. It is always

read as 0 and cannot be modified.

[Setting condition]

When the TCNT value underflows (changes from

H'0000 to H'FFFF)

[Clearing cond iti on]

When 0 is written to TCFU after reading TCFU = 1

4 TCFV 0 R/(W)*Overflow Flag

Status flag that indicates that TCNT overflow has

occurred.

[Setting condition]

When the TCNT value overflows (changes from

H'FFFF to H'0000)

[Clearing cond iti on]

When 0 is written to TCFV after reading TCFV = 1

Section 11 16-Bit Ti mer Pulse Unit (TPU)

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Bit Bit Name Initial value R/W Description

3TGFD 0 R/(W)

*Input Capture/Output Compare Flag D

Status flag that indicates the occurrence of TGRD

input capture or compare match in channels 0 and

In channels 1, 2, 4, and 5, bit 3 is reserved. It is

always read as 0 and cannot be modified.

[Setting conditions]

• When TCNT = TGRD while TGRD is functioning

as output compare register

• When TCNT value is transferred to TGRD by

input capture signal while TGRD is functioning

as input capture register

[Clearing cond iti ons ]

• When DTC is activated by TGID interrupt while

DISEL bit of MRB in DTC is 0

• When 0 is written to TGFD after reading TGFD =

2TGFC 0 R/(W)

*Input Capture/Output Compare Flag C

Status flag that indicates the occurrence of TGRC

input capture or compare match in channels 0 and

In channels 1, 2, 4, and 5, bit 2 is reserved. It is

always read as 0 and cannot be modified.

[Setting conditions]

• When TCNT = TGRC while TGRC is functioning

as output compare register

• When TCNT value is transferred to TGRC by

input capture signal while TGRC is functioning

as input capture register

[Clearing cond iti ons ]

• When DTC is activated by TGIC interrupt while

DISEL bit of MRB in DTC is 0

• When 0 is written to TGFC after reading TGFC =

Section 11 16-Bit Ti mer Pulse Unit (TPU)

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Bit Bit Name Initial value R/W Description

1TGFB 0 R/(W)

*Input Capture/Output Compare Flag B

Status flag that indicates the occurrence of TGRB

input capture or compare match.

[Setting conditions]

• When TCNT = TGRB while TGRB is functioning

as output compare register

• When TCNT value is transferred to TGRB by

input capture signal while TGRB is functioning

as input capture register

[Clearing cond iti ons ]

• When DTC is activat ed by TGIB interr upt wh ile

DISEL bit of MRB in DTC is 0

• When 0 is written to TGFB after reading TGFB =

0TGFA 0 R/(W)

*Input Capture/Output Compare Flag A

Status flag that indicates the occurrence of TGRA

input capture or compare match.

[Setting conditions]

• When TCNT = TGRA while TGRA is functioning

as output compare register

• When TCNT value is transferred to TGRA by

input capture signal while TGRA is functioning

as input capture register

[Clearing cond iti ons ]

• When DTC is activat ed by TGIA interr upt wh ile

DISEL bit of MRB in DTC is 0

• When 0 is written to TGFA after reading TGFA =

Note: *Only 0 can be written, for flag clearing.

Section 11 16-Bit Ti mer Pulse Unit (TPU)

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11.3.6 Timer Counter (TCNT)

The TCNT registers are 16-bit readable/writable counters. The TPU has six TCNT counters, one

for each channel.

The TCNT counters are initialized to H'0000 by a reset, or in hardware standby mode.

The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit

unit.

11.3.7 Timer General Register (TGR)

The TGR registers are 16-bit readable/writable registers with a dual function as output compare

and input capture registers. The TPU has 16 TGR registers, four each for channels 0 and 3 and two

each for channels 1, 2, 4, and 5. TGRC and TGRD for channels 0 and 3 can also be designated for

operation as buffer registers. The TGR registers cannot be accessed in 8-bit units; they must

always be accessed as a 16-bit unit. TGR buffer register combinations are TGRA–TGRC and

TGRB–TGRD.

11.3.8 Timer Start Register (TSTR)

TSTR selects operation/stoppage for channels 0 to 5. When setting the operating mode in TMDR

or setting the count clock in TCR, first stop the TCNT counter.

Bit Bit Name Initial value R/W Description

7, 6 —All 0 —Reserved

These bits should always be written with 0.

CST5

CST4

CST3

CST2

CST1

CST0

R/W

Counter Start 5 to 0

These bits select operation or stoppage for TCNT.

If 0 is written to the CST bit during operation with the

TIOC pin designated for output, the counter stops but

the TIOC pin output compare output level is retained.

If TIOR is written to when the CST bit is cleared to 0,

the pin output level will be changed to the set initial

output value.

0: TCNT_5 to TCNT_0 count operation is stopped

1: TCNT_5 to TCNT_0 performs count operation

Section 11 16-Bit Ti mer Pulse Unit (TPU)

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11.3.9 Timer Synchronous Register (TSYR)

TSYR selects independent op eration or synchronous operation for the TCNT counters of channels

0 to 5. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1.

Bit Bit Name Initial value R/W Description

7, 6 —All 0 R/W Reserved

These bits should always be written with 0.

SYNC5

SYNC4

SYNC3

SYNC2

SYNC1

SYNC0

R/W

Timer Synchronization 5 to 0

These bits select whether operation is independent

of or synchronized with other channels.

When synchronous operation is selected,

synchronous presetting of multiple channels, and

synchronous clearing through counter clearing on

another channel are possible.

To set synchronous operation, the SYNC bits for at

least two channels must be set to 1. To set

synchronous clearing, in addition to the SYNC bit,

the TCNT clearing source must also be set by means

of bits CCLR2 to CCLR0 in TCR.

0: TCNT_5 to TCNT_0 operates independently

(TCNT presetting /clearing is unrelated to

other channels)

1: TCNT_5 to TCNT_0 performs synchronous

operation (TCNT synchronous presetting/

synchronous clearing is possible)

Section 11 16-Bit Ti mer Pulse Unit (TPU)

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11.4 Operation

11.4.1 Basic Functions

Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of

free-running operation, periodic counting, and external event counting.

Each TGR can be used as an input capture register or output compare register.

Counter Operation: When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for

the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic

counter, and so on.

1. Example of count operation setting procedure

Figure 11.2 shows an example of the count operation setting procedure.

Select counter clock

Operation selection

Select counter clearing source

Periodic counter

Set period

Start count

[1]

[2]

[4]

[3]

[5]

Free-running counter

Start count

<Free-running counter>

[5]

[1]

[2]

[3]

[4]

[5]

Select output compare register

Select the counter

clock with bits

TPSC2 to TPSC0 in

TCR. At the same

time, select the

input clock edge

with bits CKEG1

and CKEG0 in TCR.

For periodic counter

operation, select the

TGR to be used as

the TCNT clearing

source with bits

CCLR2 to CCLR0 in

TCR.

Designate the TGR

selected in [2] as an

output compare

TIOR.

Set the periodic

counter cycle in the

TGR selected in [2].

Set the CST bit in

TSTR to 1 to start

the counter

operation.

Figure 11.2 Example of Counter Operation Setting Procedure

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2. Free-running count operation and periodic count operation

Immediately after a reset, the TPU’s TCNT counters are all designated as free-running

counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up-

count operation as a free-running counter. When TCNT overflows (changes from H'FFFF to

H'0000), the TCFV bit in TSR is set to 1. If the valu e of the corresponding TCIEV bit in TIER

is 1 at this poin t, th e TPU r e quests an interrupt. After overflow, TCNT starts counting up again

from H'0000.

Figure 11.3 illustrates free-r unning counter operatio n.

TCNT value

H'FFFF

H'0000

CST bit

TCFV

Time

Figure 11.3 Free-Running Counter Operatio n

When compare match is selected as the TCNT clearing source, the TCNT counter for the

relevant channel performs periodic count operation. The TGR register for setting the period is

designated as an output compare register, and counter clearing by compare match is selected

by means of bits CCLR2 to CCLR0 in TCR. After the settings have been made, TCNT starts

count-up operation as a periodic counter when the corresponding bit in TSTR is set to 1. When

the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared

to H'0000.

If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an

interrupt. After a compare match, TCNT starts counting up again from H'0000.

Figure 11.4 illustrates periodic counter operation.

Section 11 16-Bit Ti mer Pulse Unit (TPU)

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TCNT value

TGR

H'0000

CST bit

TGF

Time

Counter cleared by TGR

compare match

Flag cleared by software or

DTC activation

Figure 11.4 Periodic Counter Operation

Wavefo rm Output by Compa re Match: The TPU can perform 0, 1, or toggle output from the

corresponding output pin using a compare match.

1. Example of setting procedure for waveform output by compare match

Figure 11.5 shows an example of the setting procedure for waveform output by a compare

match.

Select waveform output mode

Output selection

Set output timing

Start count

[1]

[2]

[3]

[1] Select initial value 0 output or 1 output, and

compare match output value 0 output, 1 output,

or toggle output, by means of TIOR. The set

initial value is output at the TIOC pin until the

first compare match occurs.

[2] Set the timing for compare match generation in

TGR.

[3] Set the CST bit in TSTR to 1 to start the count

operation.

Figure 11.5 Example of Setting Procedure for Waveform Output by Compare Match

Section 11 16-Bit Ti mer Pulse Unit (TPU)

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2. Examples of waveform output operation

Figure 11.6 shows an example of 0 output/1 output.

In this example, TCNT has been designated as a free-running counter, and settings have been

made so that 1 is output by comp are match A, and 0 is output by compare match B. When the

set level and the pin level match, the pin level does not change.

TCNT value

H'FFFF

H'0000

TIOCA

TIOCB

Time

TGRA

TGRB

No change No change

1 output

0 output

Figure 11.6 Example of 0 Output/1 Output Operation

Figure 11.7 shows an ex ample of toggle output.

In this example TCNT has been designated as a periodic counter (with counter clearing

performed by compare match B), and settings have been made so that output is toggled by both

compare match A and compare match B.

TCNT value

H'FFFF

H'0000

TIOCB

TIOCA

Time

TGRB

TGRA

Toggle output

Counter cleared by TGRB compare match

Figure 11.7 Example of Toggle Output Operation

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Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC

pin input edge.

Rising edge, falling edge, or both edges can be selected as the detection edge. For channels 0, 1, 3,

and 4, it is also possible to specify another channel’s counter input clock or compare match signal

as the input capture source.

Note: When another channel’s counter input clock is used as the input capture input for channels

0 and 3, φ/1 should not be selected as the counter input clock used for inpu t capture input.

Input capture will not be generated if φ/1 is selected.

1. Example of setting procedure for input capture operation

Figure 11.8 shows an example of the setting procedure for input capture operation.

Select input capture input

Input selection

Start count

[1]

[2]

[1] Designate TGR as an input capture register by

means of TIOR, and select the input capture

source and input signal edge (rising edge, falling

edge, or both edges).

[2] Set the CST bit in TSTR to 1 to start the count

operation.

Figure 11.8 Example o f Set ting Procedure fo r Input Capt ure O pera tion

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2. Example of input capture operation

Figure 11.9 shows an example of input capture operation.

In this example both rising and falling edges have been selected as the TIOCA pin input

capture input edge, falling edge has been selected as the TIOCB pin input capture input edge,

and counter clearing by TGRB input capture has been design ated for TCNT.

TCNT value

H'0180

H'0000

TIOCA

TGRA

Time

H'0010

H'0005

Counter cleared by TIOCB

input (falling edge)

H'0160

H'0005 H'0160 H'0010

TGRB H'0180

TIOCB

Figure 11.9 Example o f Input Capture Operation

11.4.2 Synchronous Operation

In synchronous operation, the values in multiple TCNT counters can be rewritten simultaneously

(synchronous presetting). Also, multiple of TCNT counters can be cleared simultaneously

(synchronous clearing) by making the appropriate setting in TCR.

Synchronous op eration enables TGR to be incremented with respect to a single time base.

Channels 0 to 5 can all be designated for synchronous operation.

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Example of Synchronous Operation Setting Procedure: Figure 11.10 shows an example of the

synchronous operation setting procedure.

Synchronous operation

selection

Set TCNT

Synchronous presetting

[1]

[2]

Synchronous clearing

Select counter

clearing source

[3]

Start count [5]

Set synchronous

counter clearing

[4]

Start count [5]

Clearing

source generation

channel?

Yes

[1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation.

[2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the

same value is simultaneously written to the other TCNT counters.

[3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc.

[4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source.

[5] Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation.

Set synchronous

operation

Figure 11.10 Example of Synchronous Operation Setting Procedure

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Example of Synchronous Operation: Figure 11.11 shows an example of synchronous operation.

In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to

2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and

synchronous clearing has been set for the channel 1 and 2 counter clearing source.

Three-phase PWM waveforms are output from pins TIOCA0, TIOCA1, and TIOCA2. At this

time, synchronous presetting, and synchronous clearing by TGRB_0 compare match, is performed

for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM cycle.

For details on PWM modes, see section 11.4.5, PWM Modes.

TCNT0 to TCNT2 values

H'0000

TIOCA_0

TIOCA_1

TGRB_0

Synchronous clearing by TGRB_0 compare match

TGRA_2

TGRA_1

TGRB_2

TGRA_0

TGRB_1

TIOCA_2

Time

Figure 11.11 Example of Synchronous Operation

11.4.3 Buffer Operation

Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer

registers.

Buffer operation differs depending on whether TGR has been designated as an input capture

Table 11.28 shows the register combinations used in buffer operation.

Section 11 16-Bit Ti mer Pulse Unit (TPU)

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Table 11.28 Register Combinations in Buffer Operation

Channel Timer General Register Buffer Register

0 TGRA_0 TGRC_0

TGRB_0 TGRD_0

3 TGRA_3 TGRC_3

TGRB_3 TGRD_3

• When TGR is an output compare register

When a compare match occurs, the value in the buffer register for the corresponding channel is

transferred to the timer general r egister.

This operation is illustrated in figure 11.12.

Buffer register Timer general

Compare match signal

Figure 11.12 Compare Match Buffer Operation

• When TGR is an input capture register

When input capture occurs, the value in TCNT is transferred to TGR and the value previously

held in the timer general register is tran sf er red to the buffer register.

This operation is illustrated in figure 11.13.

Buffer register Timer general

Input capture

signal

Figure 11.13 Input Capture Buffer Operation

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Example of Buffer Operation Setting Procedure: Figure 11.14 shows an example of the buffer

operation setting procedure.

Select TGR function

Buffer operation

Set buffer operation

Start count

[1]

[2]

[3]

[1] Designate TGR as an input capture register or

output compare register by means of TIOR.

[2] Designate TGR for buffer operation with bits

BFA and BFB in TMDR.

[3] Set the CST bit in TSTR to 1 to start the count

operation.

Figure 11.14 Example of Buffer Operation Setting Procedure

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Examples of Buffer Operation:

1. When TGR is an output compare register

Figure 11.15 shows an operation example in which PWM mode 1 has been designated for

channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used

in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0

output at compare match B.

As buffer operation has been set, when compare match A occurs the output changes and the

value in buff er reg ister TGRC is simultaneou sly transferred to timer general register TGRA.

This operation is repeated each time compare match A occurs.

For details on PWM modes, see section 11.4.5, PWM Modes.

TCNT value

TGRB_0

H'0000

TGRC_0

TGRA_0

H'0200 H'0520

TIOCA

H'0200

H'0450 H'0520

H'0450

TGRA_0 H'0450H'0200

Transfer

Time

Figure 11.15 Example of Buffer Operation (1)

2. When TGR is an input capture register

Figure 11.16 shows an operation example in which TGRA has been designated as an input

capture register, and buffer operation has been designated for TGRA and TGRC.

Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling

edges have been selected as the TIOCA pin input capture input edge.

As buffer operation has been set, when the TCNT value is stored in TGRA upon occurrence of

input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC.

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TCNT value

H'09FB

H'0000

TGRC

Time

H'0532

TIOCA

TGRA H'0F07H'0532

H'0F07

H'0532

H'0F07

H'09FB

Figure 11.16 Example of Buffer Operation (2)

11.4.4 Cascaded Operation

In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit

counter.

This function works by counting the channel 1 (channel 4) counter clock at overflow/underflow of

TCNT_2 (TCNT_5) as set in bits TPSC2 to TPSC0 in TCR.

Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.

Table 11.29 shows the register combinations used in cascaded operation.

Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid

and the counter operates independently in phase coun ting mode.

Table 11.29 Cascaded Combinations

Combination Upper 16 Bits Lower 16 Bits

Channels 1 and 2 TCNT_1 TCNT_2

Channels 4 and 5 TCNT_4 TCNT_5

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Example of Cascaded Operation Setting Procedure: Figure 11.17 shows an example of the

setting procedure for cascaded operation.

Cascaded operation

Set cascading

Start count

Set bits TPSC2 to TPSC0 in the channel 1

(channel 4) TCR to B'1111 to select TCNT_2

(TCNT_5) overflow/underflow counting.

Set the CST bit in TSTR for the upper and lower

channel to 1 to start the count operation.

[1]

[2]

[1]

[2]

Figure 11.17 Cascaded Operation Setting Procedure

Examples of Cascaded Operation: Figure 11.18 illustrates the operation when counting upon

TCNT_2 overflow/underflow has been set for TCNT_1, TGRA_1 and TGRA_2 have been

designated as input capture registers, and the TIOC pin rising edge has been selected.

When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of

the 32-bit data ar e tr ansfer r e d to TGRA_1, and the lower 16 bits to TGRA_2.

TCNT_2

clock

TCNT_2 H'FFFF H'0000 H'0001

TIOCA1,

TIOCA2

TGRA_1 H'03A2

TGRA_2 H'0000

TCNT_1

clock

TCNT_1 H'03A1 H'03A2

Figure 11.18 Example of Cascaded Operation (1)

Section 11 16-Bit Ti mer Pulse Unit (TPU)

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Figure 11 .19 illustrates the operatio n when counting upon TCNT_2 overflow/underf low has been

set for TCNT_1, and phase counting mode has been designated for channel 2.

TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.

TCLKC

TCNT_2 FFFD

TCNT_1 0001

TCLKD

FFFE FFFF 0000 0001 0002 0001 0000 FFFF

0000 0000

Figure 11.19 Example of Cascaded Operation (2)

11.4.5 PWM Modes

In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be

selected as the output level in response to compare match of each TGR.

Settings of TGR registers can output a PWM waveform in the range of 0% to 100% duty cycle.

Designating TGR compare match as the counter clearing source enables the cycle to be set in that

also possible.

There are two PWM modes, as described below.

• PWM mode 1

PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and

TGRC with TGRD. The outputs specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR

are output from the TIOCA and TIOCC pins at compare matches A and C, respectively. The

outputs specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TI OR are output at compare

matches B and D, r e spectively. The initial output value is the value set in TGRA or TGRC. If

the set values of paired TGRs are identical, the output value does not change when a comp are

match occurs.

In PWM mode 1, a maximum 8-phase PWM output is possible.

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• PWM mode 2

PWM output is generated using one TGR as the cycle register and the others as duty cycle

registers. The output specified in TIOR is performed by means of compare matches. Upon

counter clearing by a synchronization register compare match, the output value of each pin is

the initial value set in TIOR. If the set values of the cycle and duty cycle registers are id entical,

the output value does not change when a compare match occurs.

In PWM mode 2, a maximum 15-phase PWM output is po ssible by combined use with

synchronous operation.

The correspondence between PWM output pins and registers is shown in table 11.30.

Table 11. 30 PWM Output Registers and Out put Pins

Output Pins

Channel Registers PWM Mode 1 PWM Mode 2

0 TGRA_0 TIOCA0 TIOCA0

TGRB_0 TIOCB0

TGRC_0 TIOCC0 TIOCC0

TGRD_0 TIOCD0

1 TGRA_1 TIOCA1 TIOCA1

TGRB_1 TIOCB1

2 TGRA_2 TIOCA2 TIOCA2

TGRB_2 TIOCB2

3 TGRA_3 TIOCA3 TIOCA3

TGRB_3 TIOCB3

TGRC_3 TIOCC3 TIOCC3

TGRD_3 TIOCD3

4 TGRA_4 TIOCA4 TIOCA4

TGRB_4 TIOCB4

5 TGRA_5 TIOCA5 TIOCA5

TGRB_5 TIOCB5

Note: In PWM mode 2, PWM output is not possible for the TGR register in which the cycle is set.

Section 11 16-Bit Ti mer Pulse Unit (TPU)

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Example of P WM Mode Setting Procedure: Figure 11.20 shows an example of the PWM mode

setting procedure.

Select counter clock

PWM mode

Select counter clearing source

Select waveform output level

[1]

[2]

[3]

Set TGR [4]

Set PWM mode [5]

Start count [6]

[1] Select the counter clock with bits TPSC2 to

TPSC0 in TCR. At the same time, select the

input clock edge with bits CKEG1 and CKEG0 in

TCR.

[2] Use bits CCLR2 to CCLR0 in TCR to select the

TGR to be used as the TCNT clearing source.

[3] Use TIOR to designate the TGR as an output

compare register, and select the initial value and

output value.

[4] Set the cycle in the TGR selected in [2], and

set the duty in the other TGRs.

[5] Select the PWM mode with bits MD3 to MD0 in

TMDR.

[6] Set the CST bit in TSTR to 1 to start the count

operation.

Figure 11.20 Example of PWM Mode Setting Procedure

Examples of PWM Mode Operation: Figure 11.21 shows an example of PWM mode 1

operation.

In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA

initial output value and outpu t value, and 1 is set as the TGRB output value.

In this case, the value set in TGRA is used as the cycle, and the values set in TGRB registers as

the duty cycle.

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TCNT value

TGRA

H'0000

TIOCA

Time

TGRB

Counter cleared by

TGRA compare match

Figure 11.21 Example of PWM Mode Operation (1)

Figure 11.22 shows an example of PWM mode 2 operation.

In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare

match is set as the TCNT clearin g source, and 0 is set f or the initial output value and 1 for the

output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), to output a 5-phase

PWM waveform.

In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs as

the duty cycle.

TCNT value

TGRB_1

H'0000

TIOCA0

Counter cleared by

TGRB_1 compare match

Time

TGRA_1

TGRD_0

TGRC_0

TGRB_0

TGRA_0

TIOCB0

TIOCC0

TIOCD0

TIOCA1

Figure 11.22 Example of PWM Mode Operation (2)

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Figure 11.23 shows exam ples of PWM waveform output with 0% duty cycle and 100% duty cycle

in PWM mode.

TCNT value

TGRA

H'0000

TIOCA

Time

TGRB

0% duty

TGRB rewritten

TGRB

rewritten

TGRB rewritten

TCNT value

TGRA

H'0000

TIOCA

Time

TGRB

100% duty

TGRB rewritten

Output does not change when cycle register and duty register

compare matches occur simultaneously

TCNT value

TGRA

H'0000

TIOCA

Time

TGRB

100% duty

TGRB rewritten

Output does not change when cycle register and duty

0% duty

Figure 11.23 Example of PWM Mode Operation (3)

Section 11 16-Bit Ti mer Pulse Unit (TPU)

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11.4.6 Phase Counting Mode

In phase counting mode, the phase difference between two external clock inputs is detected and

TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5.

When phase counting mode is set, an external clock is selected as the counter input clock an d

TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits

CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of

TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be

used.

This can be used for two-phase encoder pulse input.

When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow

occurs while TCNT is counting down, th e TCFU flag is set.

The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of

whether TCNT is counting up or down.

Table 11.31 shows the correspondence between external clock pins and channels.

Table 11. 31 Clock Input Pins in Phase Counting Mode

External Clock Pins

Channels A-Phase B-Phase

When channel 1 or 5 is set to phase counting mode TCLKA TCLKB

When channel 2 or 4 is set to phase counting mode TCLKC TCLKD

Example of Phase Counting Mode Setting Procedure: Figure 11.24 shows an example of the

phase counting mode setting procedure.

Phase counting mode

Select phase counting mode

Start count

Select phase counting mode with bits MD3 to

MD0 in TMDR.

Set the CST bit in TSTR to 1 to start the count

operation.

[1]

[2]

[1]

[2]

Figure 11.24 Example of Phase Counting Mode Setting Procedure

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Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or

down according to the phase difference between two external clocks. There are four modes,

according to the count conditions.

1. Phase counting mode 1

Figure 11.25 shows an example of phase counting mode 1 operation, and table 11.32

summarizes th e TCNT up/down-count co nditions.

TCNT value

Time

Down-count

Up-count

TCLKA (channels 1 and 5)

TCLKC (channels 2 and 4)

TCLKB (channels 1 and 5)

TCLKD (channels 2 and 4)

Figure 11.25 Example of Phase Counting Mode 1 Operation

Table 11.32 Up/Down-Count Cond it ions in Phase Counting Mode 1

TCLKA (Channels 1 and 5)

TCLKC (Channels 2 and 4) TCLKB (Channels 1 and 5)

TCLKD (Channels 2 and 4) Operation

High level Up-count

Low level

High level

High level Down-count

Low level

High level

Low level

Legend:

: Rising edge

: Falling edge

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2. Phase counting mode 2

Figure 11.26 shows an example of phase counting mode 2 operation, and table 11.33

summarizes th e TCNT up/down-count co nditions.

Time

Down-countUp-count

TCNT value

TCLKA (channels 1 and 5)

TCLKC (channels 2 and 4)

TCLKB (channels 1 and 5)

TCLKD (channels 2 and 4)

Figure 11.26 Example of Phase Counting Mode 2 Operation

Table 11.33 Up/Down-Count Cond it ions in Phase Counting Mode 2

TCLKA (Channels 1 and 5)

TCLKC (Channels 2 and 4) TCLKB (Channels 1 and 5)

TCLKD (Channels 2 and 4) Operation

High level

Low level

Don’t care

High level Up-count

High level

Low level

High level

Don’t care

Low level Down-count

Legend:

: Rising edge

: Falling edge

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3. Phase counting mode 3

Figure 11.27 shows an example of phase counting mode 3 operation, and table 11.34

summarizes th e TCNT up/down-count co nditions.

Time

Up-count Down-count

TCNT value

TCLKA (channels 1 and 5)

TCLKC (channels 2 and 4)

TCLKB (channels 1 and 5)

TCLKD (channels 2 and 4)

Figure 11.27 Example of Phase Counting Mode 3 Operation

Table 11.34 Up/Down-Count Cond it ions in Phase Counting Mode 3

TCLKA (Channels 1 and 5)

TCLKC (Channels 2 and 4) TCLKB (Channels 1 and 5)

TCLKD (Channels 2 and 4) Operation

High level

Low level

Don’t care

High level Up-count

High level Down-count

Low level

High level

Low level

Don’t care

Legend:

: Rising edge

: Falling edge

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4. Phase counting mode 4

Figure 11.28 shows an example of phase counting mode 4 operation, and table 11.35

summarizes th e TCNT up/down-count co nditions.

Time

Up-count Down-count

TCNT value

TCLKA (channels 1 and 5)

TCLKC (channels 2 and 4)

TCLKB (channels 1 and 5)

TCLKD (channels 2 and 4)

Figure 11.28 Example of Phase Counting Mode 4 Operation

Table 11.35 Up/Down-Count Cond it ions in Phase Counting Mode 4

TCLKA (Channels 1 and 5)

TCLKC (Channels 2 and 4) TCLKB (Channels 1 and 5)

TCLKD (Channels 2 and 4) Operation

High level Up-count

Low level

Low level Don’t care

High level

High level Down-count

Low level

High level Don’t care

Low level

Legend:

: Rising edge

: Falling edge

Section 11 16-Bit Ti mer Pulse Unit (TPU)

Rev. 3.00 Mar 17, 2006 page 582 of 926

REJ09B0283-0300

Phase Counting Mode Application Example: Figure 11.29 shows an example in which phase

counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo

motor 2-phase encoder pulses in order to detect the position or speed.

Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input

to TCLKA and TCLKB.

Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and

TGRC_0 are used for the compare match function, and are set with the speed control cycle and

position control cycle. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating

in buffer mode. The channel 1 counter input clock is designated as the TGRB_0 input capture

source, and detectio n of the pulse width of 2-phase encoder 4-multiplication pulses is pe r f ormed.

TGRA_1 and TGRB_1 for channel 1 are designated for input capture, channel 0 TGRA_0 and

TGRC_0 compare matches are selected as the input capture source, and th e up/down-counter

values for the control cycles are stored.

This procedure en ables accurate p osition/speed detection to be achiev ed.

TCNT_1

TCNT_0

Channel 1

TGRA_1

(speed cycle capture)

TGRA_0

(speed control cycle)

TGRB_1

(position cycle capture)

TGRC_0

(position control cycle)

TGRB_0 (pulse width capture)

TGRD_0 (buffer operation)

Channel 0

TCLKA

TCLKB

Edge

detection

circuit

Figure 11.29 Phase Counting Mode Application Example

Section 11 16-Bit Ti mer Pulse Unit (TPU)

Rev. 3.00 Mar 17, 2006 page 583 of 926

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11.5 Interrupt Sources

There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT

overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disable

bit, allowing generation of interrupt request signals to be enabled or disabled individually.

When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the

correspo ndin g enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The

interrupt request is cleared by clearing the status flag to 0.

Relative channel priorities can be changed by th e interrupt controller, but the priority order within

a channel is fixed. For details, see section 5, Interrupt Controller.

Table 11.36 lists th e TPU interrupt sources.

Section 11 16-Bit Ti mer Pulse Unit (TPU)

Rev. 3.00 Mar 17, 2006 page 584 of 926

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Table 11.36 TPU Interrupts

Channel Name Interrupt Source Interrupt

Flag DTC

Activation DMAC

Activation

0 TGI0A TGRA_0 input capture/compare match TGFA_0 Possible Possible

TGI0B TGRB_0 input capture/compare match TGFB_0 Possible Not possible

TGI0C TGRC_0 input capture/c ompare matc h TGFC_0 Possible Not possible

TGI0D TGRD_0 input capture/c ompare matc h TGFD_0 Possible Not possible

TGI0V TCNT_0 overflow TCFV_0 Not possible Not possible

1 TGI1A TGRA_1 input capture/compare match TGFA_1 Possible Possible

TGI1B TGRB_1 input capture/compare match TGFB_1 Possible Not possible

TCI1V TCNT_1 overflow TCFV _1 Not poss i bl e Not possibl e

TCI1U TCNT_1 underflow TCFU_1 Not possible Not possibl e

2 TGI2A TGRA_2 input capture/compare match TGFA_2 Possible Possible

TGI2B TGRB_2 input capture/compare match TGFB_2 Possible Not possible

TCI2V TCNT_2 overflow TCFV _2 Not poss i bl e Not possibl e

TCI2U TCNT_2 underflow TCFU_2 Not possible Not possibl e

3 TGI3A TGRA_3 input capture/compare match TGFA_3 Possible Possible

TGI3B TGRB_3 input capture/compare match TGFB_3 Possible Not possible

TGI3C TGRC_3 input capture/c ompare matc h TGFC_3 Possible Not possible

TGI3D TGRD_3 input capture/c ompare matc h TGFD_3 Possible Not possible

TCI3V TCNT_3 overflow TCFV _3 Not poss i bl e Not possibl e

4 TGI4A TGRA_4 input capture/compare match TGFA_4 Possible Possible

TGI4B TGRB_4 input capture/compare match TGFB_4 Possible Not possible

TCI4V TCNT_4 overflow TCFV _4 Not poss i bl e Not possibl e

TCI4U TCNT_4 underflow TCFU_4 Not possible Not possibl e

5 TGI5A TGRA_5 input capture/compare match TGFA_5 Possible Possible

TGI5B TGRB_5 input capture/compare match TGFB_5 Possible Not possible

TCI5V TCNT_5 overflow TCFV _5 Not poss i bl e Not possibl e

TCI5U TCNT_5 underflow TCFU_5 Not possible Not possibl e

Note: This tab le shows the initia l st ate imm ediate ly after a reset. The rela tiv e chann el priorities

can be changed by the interrupt controller.

Section 11 16-Bit Ti mer Pulse Unit (TPU)

Rev. 3.00 Mar 17, 2006 page 585 of 926

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Input Capture/Compa re Match Interrupt: An inter r upt is requested if the TGI E bit in TI ER is

set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare

match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The

TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each

for channels 1, 2, 4, and 5.

Overflow Interrupt: An interrupt is requ ested if the TCIEV bit in TIER is set to 1 when the

TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt

request is cleared by clearing the TCFV flag to 0. The TPU has six overflow interrupts, one for

each channel.

Underflow Interrupt: An interrupt is r equested if the TCIEU bit in TIER is set to 1 when the

TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt

request is cleared by clearing the TCFU flag to 0. The TPU has four underflow interrupts, one

each for channels 1, 2, 4, and 5.

11.6 DTC Activation

The DTC can be activated by the TGR input capture/compare match interrupt for a channel. For

details, see section 9, Data Tr ansfer Controller (DTC).

A total of 16 TPU input capture/compare match interrup ts can be used as DTC activation sources,

four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5.

11.7 DMAC Activation

The DMAC can be activated by the TGRA input capture/compare match interrupt for a channel.

For details, see section 7, DMA Controller (DMAC).

In the TPU, a total of six TGRA input capture/compare match interrupts can be used as DMAC

activation sources, one for each channel.

11.8 A/D Converter Activation

The A/D converter can be activated by the TGRA input capture/compare match for a channel.

If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a

TGRA input capture/compare match on a particular channel, a request to start A/D conversion is

sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D

converter side at this time, A/D conversion is started.

Section 11 16-Bit Ti mer Pulse Unit (TPU)

Rev. 3.00 Mar 17, 2006 page 586 of 926

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In the TPU, a total of six TGRA input capture/compare match interrupts can be used as A/D

converter conversion start sources, one for each channel.

11.9 Operation Timing

11.9 .1 Input/Output Ti ming

TCNT Count Timing: Figure 11.30 shows TCNT count timing in internal clock operation, and

figure 11.31 shows TCNT count timing in external clock operation.

TCNT

input clock

Internal clock

N – 1 N N + 1 N + 2

Falling edge Rising edge

Figure 11.30 Count Timing in Internal Clock Operation

TCNT

input clock

External clock

N – 1 N N + 1 N + 2

Falling edge Rising edge Falling edge

Figure 11.31 Count Timing in External Clock Operation

Section 11 16-Bit Ti mer Pulse Unit (TPU)

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Output Compa re Output Timing : A co mpare match sig nal is generated in the final state in

which TCNT and TGR match (the point at which the count value matched by TCNT is updated).

When a comp are match signal is generated, the output value set in TI OR is output at the output

compare output pin. After a match between TCNT and TGR, the compare match signal is not

generated until the (TIOC pin) TCNT input clock is generated.

Figure 11.32 shows ou tput compare output timing.

TGR

TCNT

input clock

N N + 1

Compare

match signal

TIOC pin

Figure 11.32 Output Compa re Output Timing

Input Capture S ignal Timing: Figure 11.33 shows input capture signal timing.

TCNT

Input capture

input

N N + 1 N + 2

NN + 2

TGR

Input capture

signal

Figure 11. 33 Input Capture Input Signal Timing

Section 11 16-Bit Ti mer Pulse Unit (TPU)

Rev. 3.00 Mar 17, 2006 page 588 of 926

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Timing for Counter Clearing by Compare Match/Input Capture: Figure 11.34 shows the

timing when counter clearing by compare match occurrence is specified, and figure 11.35 shows

the timing when counter clearing by input capture occurrence is specified.

TCNT

Counter

clear signal

Compare

match signal

TGR N

N H'0000

Figure 11.34 Counter Clear Timing (Compare Match)

TCNT

Counter clear

signal

Input capture

signal

TGR

N H'0000

Figure 11.35 Counter Clear Timing (Input Capture)

Section 11 16-Bit Ti mer Pulse Unit (TPU)

Rev. 3.00 Mar 17, 2006 page 589 of 926

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Buffer Operation Timing: Figures 11.36 and 11.37 show the timings in buffer operation.

TGRA,

TGRB

Compare

match signal

TCNT

TGRC,

TGRD

n n + 1

Figure 11.36 Buffer Operation Timing (Compare Match)

TGRA,

TGRB

TCNT

Input capture

signal

TGRC,

TGRD

n N + 1

N N + 1

Figure 11.37 Buffer Operation Timing (Input Capture)

Section 11 16-Bit Ti mer Pulse Unit (TPU)

Rev. 3.00 Mar 17, 2006 page 590 of 926

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11.9.2 Interrupt Signal Timing

TGF Flag Setting Timing in Case of Compare Match: Figure 11.38 shows the timing for

setting of the TGF flag in TSR by comp are match occurrence, and the TGI interrupt request signal

timing.

TGR

TCNT

TCNT input

clock

N N + 1

Compare

match signal

TGF flag

TGI interrupt

Figure 11.38 TGI Interrupt Timing (Compare Match)

Section 11 16-Bit Ti mer Pulse Unit (TPU)

Rev. 3.00 Mar 17, 2006 page 591 of 926

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TGF Flag Setting Timing in Case of Input Capture: Figure 11.3 9 shows the timing for settin g

of the TGF flag in TSR by input capture occurrence, and the TGI interrupt request signal timing.

TGR

TCNT

Input capture

signal

TGF flag

TGI interrupt

Figure 11. 39 TGI Interrupt Timing (Input Capture)

Section 11 16-Bit Ti mer Pulse Unit (TPU)

Rev. 3.00 Mar 17, 2006 page 592 of 926

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TCFV Flag/TCFU Flag Setting Timing: Figure 11.40 shows the timing for setting of the TCFV

flag in TSR by ov erflow occurrence, and the TCIV interrupt request signal timing.

Figure 11.41 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and

the TCIU interr upt request sign a l timing.

Overflow

signal

TCNT

(overflow)

TCNT input

clock

H'FFFF H'0000

TCFV flag

TCIV interrupt

Figure 11.40 TCIV Interrupt Setting Timing

Underflow

signal

TCNT

(underflow)

TCNT

input clock

H'0000 H'FFFF

TCFU flag

TCIU interrupt

Figure 11.41 TCIU Interrupt Setting Timing

Section 11 16-Bit Ti mer Pulse Unit (TPU)

Rev. 3.00 Mar 17, 2006 page 593 of 926

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Status Fla g Clearing Timing: After a status flag is read as 1 b y the CPU, it is cleared by writing

0 to it. When the DTC or DMAC is activated, the flag is cleared automatically. Figure 11.42

shows the timing for status flag clearing by the CPU, and figure 11.43 shows the timing for status

flag clearing by the DTC or DMAC.

Status flag

Write signal

Address TSR address

Interrupt

request

signal

TSR write cycle

T1 T2

Figure 11.42 Timing for Status Flag Clearing by CPU

Interrupt

request

signal

Status flag

Address Source address

DTC/DMAC

read cycle

T1 T2

Destination

address

T1 T2

DTC/DMAC

write cycle

Figure 11.43 Timing for Stat us Fla g Clearing by DTC/DMAC Activatio n

Section 11 16-Bit Ti mer Pulse Unit (TPU)

Rev. 3.00 Mar 17, 2006 page 594 of 926

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11.10 Usage Notes

11.10.1 Module Stop Mode Setting

TPU operation can be disabled or enabled using the module stop control register. The initial

setting is for TPU operation to be halted. Register access is enabled by clearing module stop

mode. For details, refer to section 22, Power-Down Modes.

11.10.2 Input Clo c k Restrictions

The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at

least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a

narrower pulse width.

In phase counting mode, the phase difference and overlap between the two input clocks must be at

least 1.5 states, and the pulse width must be at least 2.5 states. Figure 11.44 shows the input clock

conditions in phase counting mode.

Overlap

Phase

diffe-

rence

Phase

diffe-

rence

Overlap

TCLKA

(TCLKC)

TCLKB

(TCLKD)

Pulse width Pulse width

Notes: Phase difference and overlap

Pulse width : 1.5 states or more

: 2.5 states or more

Figure 11.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode

Section 11 16-Bit Ti mer Pulse Unit (TPU)

Rev. 3.00 Mar 17, 2006 page 595 of 926

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11.10.3 Cautio n on Cycle Setting

When counter clearing by compare match is set, TCNT is cleared in the final state in which it

matches the TGR value (the point at which the count value matched by TCNT is updated).

Consequently, the actual counter frequency is given by the following formula:

f = (N + 1)

Where f: Counter frequency

φ: Operating frequency

N: TGR set value

11.10.4 Contention between TCNT Write and Clear Operations

If the counter clearing signal is generated in the T2 state of a TCNT write cycle, TCNT clearing

takes precedence and the TCNT write is not performed. Figure 11.45 shows the timing in this

case.

Counter clearing

signal

Write signal

Address

TCNT address

TCNT

TCNT write cycle

T1 T2

N H'0000

Figure 11.45 Contention between TCNT Write and Clear Operations

Section 11 16-Bit Ti mer Pulse Unit (TPU)

Rev. 3.00 Mar 17, 2006 page 596 of 926

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11.10.5 Contention between TCNT Write and Increme nt Operations

If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence

and TCNT is not in cremented. Figure 11 . 46 sh ows the timing in this case.

TCNT input

clock

Write signal

Address

TCNT address

TCNT

TCNT write cycle

T1 T2

N M

TCNT write data

Figure 11.46 Contention between TCNT Write and Increment Operations

Section 11 16-Bit Ti mer Pulse Unit (TPU)

Rev. 3.00 Mar 17, 2006 page 597 of 926

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11.10.6 Contention between TGR Write and Compare Match

If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence

and the compare match signal is disabled. A compare match also does not occur when the same

value as before is wr itten.

Figure 11.47 shows the timing in this case.

Compare

match signal

Write signal

Address

TGR address

TCNT

TGR write cycle

T1 T2

N M

TGR write data

TGR

N N + 1

Prohibited

Figure 11.47 Contention between TGR Write and Compare Match

Section 11 16-Bit Ti mer Pulse Unit (TPU)

Rev. 3.00 Mar 17, 2006 page 598 of 926

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11.10.7 Contention between Buffer Register Write and Compare Match

If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the

buffer ope r a tion will be the data prior to the wr ite.

Figure 11.48 shows the timing in this case.

Compare

match signal

Write signal

Address

Buffer register

address

Buffer

TGR write cycle

T1 T2

TGR

N M

Buffer register write data

Figure 11.48 Contention between Buffer Register Write and Compare Match

Section 11 16-Bit Ti mer Pulse Unit (TPU)

Rev. 3.00 Mar 17, 2006 page 599 of 926

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11.10.8 Content io n bet ween TGR Read and Inp ut Capture

If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read

will be the data after input capture transfer.

Figure 11.49 shows the timing in this case.

Input capture

signal

Read signal

Address

TGR address

TGR

TGR read cycle

T1 T2

Internal

data bus

X M

Figure 11.49 Contention betw een TG R Read and Input Capture

Section 11 16-Bit Ti mer Pulse Unit (TPU)

Rev. 3.00 Mar 17, 2006 page 600 of 926

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11.10.9 Content ion between TGR Write and Input Capt ure

If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture

operation takes preceden ce and the write to TGR is not performed.

Figure 11.50 shows the timing in this case.

Input capture

signal

Write signal

Address

TCNT

TGR write cycle

T1 T2

TGR

TGR address

Figure 11.50 Contention between TGR Write and Input Capture

Section 11 16-Bit Ti mer Pulse Unit (TPU)

Rev. 3.00 Mar 17, 2006 page 601 of 926

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11.10.10 Contention between Buffer Register Write and Input Ca pt ure

If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer

operation takes preceden ce and the write to the buffer register is not performed.

Figure 11.51 shows the timing in this case.

Input capture

signal

Write signal

Address

TCNT

Buffer register write cycle

T1 T2

TGR

Buffer

Buffer register

address

Figure 11.51 Contention between Buff er Register Write and Input Ca pt ure

Section 11 16-Bit Ti mer Pulse Unit (TPU)

Rev. 3.00 Mar 17, 2006 page 602 of 926

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11.10.11 Contention between Overflow/Underflow and Counter Clearing

If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is

not set and TCNT clearing takes precedence.

Figure 11.52 shows the operation timing when a TGR compare match is specified as the clearing

source, an d H'FFFF is set in TGR.

Counter

clearing signal

TCNT input

clock

TCNT

TGF

Prohibited

TCFV

H'FFFF H'0000

Figure 11.52 Contention between Overflow and Counter Clearing

Section 11 16-Bit Ti mer Pulse Unit (TPU)

Rev. 3.00 Mar 17, 2006 page 603 of 926

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11.10.12 Contentio n between TCNT Write and Overflow/Underflow

If there is an up-count or down-count in the T2 state of a TCNT write cycle, when

overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is

not set.

Figure 11.53 shows the operation timing when there is contention between TCNT write and

overflow.

Write signal

Address

TCNT address

TCNT

TCNT write cycle

T1 T2

H'FFFF M

TCNT write data

TCFV flag Prohibited

Figure 11.53 Contention between TCNT Write and Overflow

11.10.13 Multiplexing of I/O Pins

In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin

with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input

pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not

be performe d from a m ultiplexed pin.

11.10.1 4 Interrupts a nd Module Stop Mode

If module stop mode is entered when an inter rupt has been requested, it will not be possible to

clear the CPU interrupt source or the DMAC or DTC activation source. Interrupts should therefore

be disabled before entering module stop mode.

Section 11 16-Bit Ti mer Pulse Unit (TPU)

Rev. 3.00 Mar 17, 2006 page 604 of 926

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Section 12 Programmable Pu lse Generator (PPG)

Rev. 3.00 Mar 17, 2006 page 605 of 926

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Section 12 Programmable Pulse Generator (PPG)

The programmable pulse generator (PPG) provides pulse outputs by using the 16-bit timer pulse

unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (groups 3 to 0) that

can operate both simultaneously and independently. The block diagram of PPG is shown in figure

12.1

12.1 Features

• 16-bit output data

• Four output groups

• Selectable output trigger signals

• Non-overlap mode

• Can operate to gether with the data transfer contr oller (DTC) and the DMA contro ller (DMAC)

• Settable inverted output

• Module stop mode can be set

PPG0001A_000020020400

Section 12 Programmable Pu lse Generator (PPG)

Rev. 3.00 Mar 17, 2006 page 606 of 926

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Compare match signals

PO15

PO14

PO13

PO12

PO11

PO10

PO9

PO8

PO7

PO6

PO5

PO4

PO3

PO2

PO1

PO0

Legend:

PMR

PCR

NDERH

NDERL

NDRH

NDRL

PODRH

PODRL

: PPG output mode register

: PPG output control register

: Next data enable register H

: Next data enable register L

: Next data register H

: Next data register L

: Output data register H

: Output data register L

Internal

data bus

Pulse output

pins, group 3

Pulse output

pins, group 2

Pulse output

pins, group 1

Pulse output

pins, group 0

PODRH

PODRL

NDRH

NDRL

Control logic

NDERH

PMR

NDERL

PCR

Figure 12.1 Block Diagram of PPG

Section 12 Programmable Pu lse Generator (PPG)

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12.2 Input/Output Pins

Table 12.1 shows the PPG pin configuration.

Table 12.1 Pin Configuratio n

Pin Name I/O Function

PO15 Output

PO14 Output

PO13 Output

PO12 Output

Group 3 puls e output

PO11 Output

PO10 Output

PO9 Output

PO8 Output

Group 2 puls e output

PO7 Output

PO6 Output

PO5 Output

PO4 Output

Group 1 puls e output

PO3 Output

PO2 Output

PO1 Output

PO0 Output

Group 0 puls e output

12.3 Register Descriptions

The PPG has the following registers.

• Next data enable register H (NDERH)

• Next data enable register L (NDERL)

• Output data register H (PODRH)

• Output data register L (PODRL)

• Next data register H (NDRH)

• Next data register L (NDRL)

• PPG output control register (PCR)

• PPG output mode register (PMR)

Section 12 Programmable Pu lse Generator (PPG)

Rev. 3.00 Mar 17, 2006 page 608 of 926

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12.3.1 Next Data Enable Registers H, L (NDERH, NDERL)

NDERH, NDERL enable or disable pulse output on a bit-by-bit basis. For outputting pulse by the

PPG, set the corresponding DDR to 1.

NDERH

Bit Bit Name Initial Value R/W Description

NDER15

NDER14

NDER13

NDER12

NDER11

NDER10

NDER9

NDER8

R/W

Next Data Enable 15 to 8

When a bit is set to 1, the value in the

corresponding NDRH bit is transferred to the

PODRH bit by the selected output trigger. Values

are not transferred from NDRH to PODRH for

cleared bit s.

NDERL

Bit Bit Name Initial Value R/W Description

NDER7

NDER6

NDER5

NDER4

NDER3

NDER2

NDER1

NDER0

R/W

Next Data Enable 7 to 0

When a bit is set to 1, the value in the

corresponding NDRL bit is transferred to the

PODRL bit by the selected output trigger. Values

are not transferred from NDRL to PODRL for

cleared bit s.

Section 12 Programmable Pu lse Generator (PPG)

Rev. 3.00 Mar 17, 2006 page 609 of 926

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12.3.2 Output Data Registers H, L (PODRH, PODRL)

PODRH and PODRL store output data for use in pulse output. A bit that has been set for pulse

output by NDER is read-only and cannot be modified.

PODRH

Bit Bit Name Initial Value R/W Description

POD15

POD14

POD13

POD12

POD11

POD10

POD9

POD8

R/W

Output Data Register 15 to 8

For bits which have been set to pulse ou tput by

NDERH, the output trigger transfers NDRH values

to this register during PPG operation. While

NDERH is set to 1, the CPU cannot write to this

value of the pulse can be set.

PODRL

Bit Bit Name Initial Value R/W Description

POD7

POD6

POD5

POD4

POD3

POD2

POD1

POD0

R/W

Output Data Register 7 to 0

For bits which have been set to pulse ou tput by

NDERL, the output trigger transfers NDRL values

to this register during PPG operation. While

NDERL is set to 1, the CPU cannot write to this

value of the pulse can be set.

Section 12 Programmable Pu lse Generator (PPG)

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12.3.3 Next Data Registers H, L (NDRH, NDRL)

NDRH, NDRL store the next data for pulse output. The NDR addresses differ depending on

whether pulse output groups have the same output trigger or different output triggers.

NDRH

If pulse output groups 2 and 3 have the same output trigger, all eight bits are mapped to the same

address and can be accessed at one time, as shown below.

Bit Bit Name Initial Value R/W Description

NDR15

NDR14

NDR13

NDR12

NDR11

NDR10

NDR9

NDR8

R/W

Next Data Register 15 to 8

The register contents are transferred to the

corresponding PODRH bits by the output trigger

specified with PCR.

If pulse output groups 2 and 3 have different output triggers, upper 4 bits and lower 4 bits are

mapped to the different addresses as shown below.

Bit Bit Name Initial Value R/W Description

NDR15

NDR14

NDR13

NDR12

R/W

Next Data Register 15 to 12

The register contents are transferred to the

corresponding PODRH bits by the output trigger

specified with PCR.

— All 1 — Reserved

These bits are always read as 1 and cannot be

modified.

Section 12 Programmable Pu lse Generator (PPG)

Rev. 3.00 Mar 17, 2006 page 611 of 926

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Bit Bit Name Initial Value R/W Description

— All 1 — Reserved

These bits are always read as 1 and cannot be

modified.

NDR11

NDR10

NDR9

NDR8

R/W

Next Data Register 11 to 8

The register contents are transferred to the

corresponding PODRH bits by the output trigger

specified with PCR.

NDRL

If pulse output groups 0 and 1 have the same output trigger, all eight bits are mapped to the same

address and can be accessed at one time, as shown below.

Bit Bit Name Initial Value R/W Description

NDR7

NDR6

NDR5

NDR4

NDR3

NDR2

NDR1

NDR0

R/W

Next Data Register 7 to 0

The register contents are transferred to the

corresponding PODRL bits by the output trigger

specified with PCR.

If pulse output groups 0 and 1 have different output triggers, upper 4 bits and lower 4 bits are

mapped to the different addresses as shown below.

Bit Bit Name Initial Value R/W Description

NDR7

NDR6

NDR5

NDR4

R/W

Next Data Register 7 to 4

The register contents are transferred to the

corresponding PODRL bits by the output trigger

specified with PCR.

— All 1 — Reserved

These bits are always read as 1 and cannot be

modified.

Section 12 Programmable Pu lse Generator (PPG)

Rev. 3.00 Mar 17, 2006 page 612 of 926

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Bit Bit Name Initial Value R/W Description

— All 1 — Reserved

These bits are always read as 1 and cannot be

modified.

NDR3

NDR2

NDR1

NDR0

R/W

Next Data Register 3 to 0

The register contents are transferred to the

corresponding PODRL bits by the output trigger

specified with PCR.

12.3.4 PPG Output Control Register (PCR)

PCR selects output trigger signals on a group-by-group basis. For details on output trigger

selection, refer to section 12.3.5, PPG Output Mode Register (PMR).

Bit Bit Name Initial Value R/W Description

6G3CMS1

G3CMS0 1

1R/W

R/W Group 3 Compare Match Select 1 and 0

Select output trigger of pulse output group 3.

00: Compare match in TPU channel 0

01: Compare match in TPU channel 1

10: Compare match in TPU channel 2

11: Compare match in TPU channel 3

4G2CMS1

G2CMS0 1

1R/W

R/W Group 2 Compare Match Select 1 and 0

Select output trigger of pulse output group 2.

00: Compare match in TPU channel 0

01: Compare match in TPU channel 1

10: Compare match in TPU channel 2

11: Compare match in TPU channel 3

2G1CMS1

G1CMS0 1

1R/W

R/W Group 1 Compare Match Select 1 and 0

Select output trigger of pulse output group 1.

00: Compare match in TPU channel 0

01: Compare match in TPU channel 1

10: Compare match in TPU channel 2

11: Compare match in TPU channel 3

Section 12 Programmable Pu lse Generator (PPG)

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Bit Bit Name Initial Value R/W Description

0G0CMS1

G0CMS0 1

1R/W

R/W Group 0 Compare Match Select 1 and 0

Select output trigger of pulse output group 0.

00: Compare match in TPU channel 0

01: Compare match in TPU channel 1

10: Compare match in TPU channel 2

11: Compare match in TPU channel 3

12.3.5 PPG Output Mode Register (PMR)

PMR selects the pulse output mode of the PPG for each group. If inverted output is selected, a

low-level pulse is output when PODRH is 1 and a high-level pu lse is output when PODRH is 0. If

non-overlapping operation is selected, PPG updates its output values at compare match A or B of

the TPU that becom es the output trigger. For details, re f er to section 12.4.4, Non-Overlapping

Pulse Outpu t.

Bit Bit Name Initial Value R/W Description

7 G3INV 1 R/W Group 3 Inversion

Selects direct output or inverted output for pulse

output group 3.

0: Inverted output

1: Direct output

6 G2INV 1 R/W Group 2 Inversion

Selects direct output or inverted output for pulse

output group 2.

0: Inverted output

1: Direct output

5 G1INV 1 R/W Group 1 Inversion

Selects direct output or inverted output for pulse

output group 1.

0: Inverted output

1: Direct output

Section 12 Programmable Pu lse Generator (PPG)

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Bit Bit Name Initial Value R/W Description

4 G0INV 1 R/W Group 0 Inversion

Selects direct output or inverted output for pulse

output group 0.

0: Inverted output

1: Direct output

3 G3NOV 0 R/W Group 3 Non-Overlap

Selects norma l or non-overlapping operation for

pulse output group 3.

0: Normal operation (output values updated at

compare match A in the selected TPU channel)

1: Non-overlapping operation (output values

updated at compare match A or B in the selected

TPU channel)

2 G2NOV 0 R/W Group 2 Non-Overlap

Selects norma l or non-overlapping operation for

pulse output group 2.

0: Normal operation (output values updated at

compare match A in the selected TPU channel)

1: Non-overlapping operation (output values

updated at compare match A or B in the selected

TPU channel)

1 G1NOV 0 R/W Group 1 Non-Overlap

Selects norma l or non-overlapping operation for

pulse output group 1.

0: Normal operation (output values updated at

compare match A in the selected TPU channel)

1: Non-overlapping operation (output values

updated at compare match A or B in the selected

TPU channel)

0 G0NOV 0 R/W Group 0 Non-Overlap

Selects norma l or non-overlapping operation for

pulse output group 0.

0: Normal operation (output values updated at

compare match A in the selected TPU channel)

1: Non-overlapping operation (output values

updated at compare match A or B in the selected

TPU channel)

Section 12 Programmable Pu lse Generator (PPG)

Rev. 3.00 Mar 17, 2006 page 615 of 926

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12.4 Operation

Figure 12.2 shows an overview diagram of the PPG. PPG pulse output is enabled when the

correspo nding bits in P1DDR, P2DDR, and NDER are set to 1. An initial output value is

determined by its corresponding PODR initial setting. When the compare match event specified

by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output

values. Sequential output of data of up to 16 bits is possible by writing new output data to NDR

before the next compare match.

Output trigger signal

Pulse output pin Internal data bus

Normal output/inverted output

PODRQD

NDER

NDRQD

DDR

Figure 12.2 Overview Diagram of PPG

Section 12 Programmable Pu lse Generator (PPG)

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12.4 .1 Output Timing

If pulse output is enabled, NDR contents are transferred to PODR and output when the specified

compare match event occurs. Figure 12.3 shows the timing of th ese operations for the case of

normal output in groups 2 and 3, triggered by compare match A.

TCNT N N + 1

TGRA N

Compare match

A signal

NDRH

PODRH

PO8 to PO15

Figure 12.3 Timing of Transfer and Output of NDR Contents (Example)

Section 12 Programmable Pu lse Generator (PPG)

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12.4.2 Sample Setup Procedure for Normal Pulse Output

Figure 12.4 shows a sample procedure for setting up normal pulse output.

Select TGR functions [1]

Set TGRA value

Set counting operation

Select interrupt request

Set initial output data

Enable pulse output

Select output trigger

Set next pulse

output data

Start counter

Set next pulse

output data

Normal PPG output

Yes

TPU setup

Port and

PPG setup

TPU setup

[2]

[3]

[4]

[5]

[6]

[7]

[8]

[9]

[10]

Compare match?

[1] Set TIOR to make TGRA an output

compare register (with output

disabled)

[2] Set the PPG output trigger period

[3] Select the counter clock source with

bits TPSC2 to TPSC0 in TCR.

Select the counter clear source with

bits CCLR2 to CCLR0.

[4] Enable the TGIA interrupt in TIER.

The DTC or DMAC can also be set

up to transfer data to NDR.

[5] Set the initial output values in

PODR.

[6] Set the DDR and NDER bits for the

pins to be used for pulse output to 1.

[7] Select the TPU compare match

event to be used as the output

trigger in PCR.

[8] Set the next pulse output values in

NDR.

[9] Set the CST bit in TSTR to 1 to start

the TCNT counter.

[10] At each TGIA interrupt, set the next

output values in NDR.

Figure 12.4 Setup Procedure for Normal Pulse Output (Example)

Section 12 Programmable Pu lse Generator (PPG)

Rev. 3.00 Mar 17, 2006 page 618 of 926

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12.4.3 Example of Normal Pulse Output (Example of Five-Phase Pulse Output)

Figure 12.5 shows an example in which pulse output is used for cyclic five-phase pulse output.

TCNT value TCNT

TGRA

H'0000

NDRH

00 80 C0 40 60 20 30 10 18 08 88

PODRH

PO15

PO14

PO13

PO12

PO11

Time

Compare match

C080 40 60 20 30 10 18 08 88 80 C0 40

Figure 12.5 Normal Pulse Output Example (Five-Phase Pulse Output)

1. Set up TGRA in TPU which is used as the output trigger to be an output compare register. Set

a cycle in TGRA so the co unter will b e clear ed by compare match A. Set the TGIEA bit in

TIER to 1 to enable the compare match/input capture A (TGIA) interrupt.

2. Write H'F8 in P1DDR and NDERH, and set the G3CMS1, G3 CMS0 , G2 CMS1 , and G2CMS0

bits in PCR to select compare m a tch in the TPU channel set up in the previous step to be the

output trigger. Write output data H'80 in NDRH.

3. The timer counter in the TPU channel starts. When compare match A occurs, the NDRH

contents are transferred to PODRH and output. The TGIA interrupt handling routine writes the

next output data (H'C0) in NDRH.

4. Five-phase pulse output (one or two phases active at a time) can be obtained subsequently by

writing H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88, ... at successive TGIA interrupts.

Section 12 Programmable Pu lse Generator (PPG)

Rev. 3.00 Mar 17, 2006 page 619 of 926

REJ09B0283-0300

If the DTC or DMAC is set f or activation by the TGIA interrupt, pulse output can be obtain ed

without imposing a load on the CPU.

12.4.4 Non-Overlapping Pulse Output

During non-overlapping operation, transfer from NDR to PODR is performed as follows:

• NDR bits are always transferred to PODR bits at compare match A.

• At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred

if their valu e is 1.

Figure 12.6 illustrates the non-overlapping pulse output operation.

Compare match A

Compare match B

Pulse

output

Internal data bus

Normal output/inverted output

PODRQD

NDER

NDRQD

DDR

Figure 12.6 Non-Overlapping Pulse Out put

Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before

compare match A.

The NDR contents should not be altered during the interval from compare match B to compare

match A (the non-overlap margin).

This can be accomplished by having the TGIA interrupt handling routine write the next data in

NDR, or by having the TGIA interrupt activate the DTC or DMAC. Note, however, that the next

data must be wr itten before the next compare match B occurs.

Figure 12.7 shows the timing of this operation.

Section 12 Programmable Pu lse Generator (PPG)

Rev. 3.00 Mar 17, 2006 page 620 of 926

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0/1 output0 output 0/1 output0 output

Do not write

to NDR here

Write to NDR

here

Compare match A

Compare match B

NDR

PODR

Do not write

to NDR here

Write to NDR

here

Write to NDR Write to NDR

Figure 12.7 Non-Overlapping Operation and NDR Write Timing

Section 12 Programmable Pu lse Generator (PPG)

Rev. 3.00 Mar 17, 2006 page 621 of 926

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12.4.5 Sample Setup Pr ocedure for Non-O verlapping Pulse Output

Figure 12.8 shows a sample procedure for setting up non-overlapping pulse output.

Select TGR functions [1]

Set TGR values

Set counting operation

Select interrupt request

Set initial output data

Enable pulse output

Select output trigger

Set next pulse

output data

Start counter

Set next pulse

output data

Compare match A? No

Yes

TPU setup

PPG setup

TPU setup

Non-overlapping

pulse output

Set non-overlapping groups

[2]

[3]

[4]

[5]

[6]

[7]

[8]

[9]

[10]

[11]

[1] Set TIOR to make TGRA and

TGRB an output compare registers

(with output disabled)

[2] Set the pulse output trigger period

in TGRB and the non-overlap

period in TGRA.

[3] Select the counter clock source

with bits TPSC2 to TPSC0 in TCR.

Select the counter clear source

with bits CCLR2 to CCLR0.

[4] Enable the TGIA interrupt in TIER.

The DTC or DMAC can also be set

up to transfer data to NDR.

[5] Set the initial output values in

PODR.

[6] Set the DDR and NDER bits for the

pins to be used for pulse output to

[7] Select the TPU compare match

event to be used as the pulse

output trigger in PCR.

[8] In PMR, select the groups that will

operate in non-overlap mode.

[9] Set the next pulse output values in

NDR.

[10] Set the CST bit in TSTR to 1 to

start the TCNT counter.

[11] At each TGIA interrupt, set the next

output values in NDR.

Figure 12.8 Setup Pro cedure f or Non-Overla pping Pulse Output (Example)

Section 12 Programmable Pu lse Generator (PPG)

Rev. 3.00 Mar 17, 2006 page 622 of 926

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12.4.6 Example of No n-Overlapping Pulse Output (Example of Four-Phase

Complement ary Non-O verlapping Out put )

Figure 12.9 shows an example in which pulse output is used for four-phase complementary non-

overlapping pulse output.

TCNT value

TCNT

TGRB

TGRA

H'0000

NDRH 95 65 59 56 95 65

00 95 05 65 41 59 50 56 14 95 05 65

PODRH

PO15

PO14

PO13

PO12

PO11

PO10

PO9

PO8

Time

Non-overlap margin

Figure 12.9 Non-Overlapping Pulse Output Example (Four-Phase Complementary)

Section 12 Programmable Pu lse Generator (PPG)

Rev. 3.00 Mar 17, 2006 page 623 of 926

REJ09B0283-0300

1. Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are

output compare registers. Set the trigger period in TGRB and the non-overlap margin in

TGRA, and set the counter to be cleared by compare match B. Set the TGIEA bit in TIER to 1

to enable the TGIA interrupt.

2. Write H'FF in P1DDR and NDERH, and set the G3 CMS1 , G3CMS0, G2CMS1, and G2 CMS0

bits in PCR to select compare m a tch in the TPU channel set up in the previous step to be the

output trigger. Set the G3NOV and G2NOV bits in PMR to 1 to select non-overlapping output.

Write output data H'95 in NDRH.

3. The timer counter in the TPU channel starts. When a compare match with TGRB occurs,

outputs change from 1 to 0. When a compare match with TGRA occurs, outputs change from 0

to 1 (the change from 0 to 1 is delayed by the value set in TGRA). The TGIA interrupt

handling routine writes the next output data (H'65) in NDRH.

4. Four-phase complementary non-overlapping pulse output can be obtained subsequently by

writing H'59, H'56, H'95, ... at successive TGIA interrupts.

If the DTC or DMAC is set f or activation by the TGIA interrupt, pulse output can be obtain ed

without imposing a load on the CPU.

Section 12 Programmable Pu lse Generator (PPG)

Rev. 3.00 Mar 17, 2006 page 624 of 926

REJ09B0283-0300

12.4.7 Inverted Pulse Output

If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the

inverse of the PODR contents can be output.

Figure 12.10 shows the outputs when G3INV and G2INV are cleared to 0, in addition to the

settings of figure 12.9.

TCNT value

TCNT

TGRB

TGRA

H'0000

NDRH 95 65 59 56 95 65

00 95 05 65 41 59 50 56 14 95 05 65

PODRL

PO15

PO14

PO13

PO12

PO11

PO10

PO9

PO8

Time

Figure 12.10 Inverted Pulse Output (Example)

Section 12 Programmable Pu lse Generator (PPG)

Rev. 3.00 Mar 17, 2006 page 625 of 926

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12.4.8 Pulse Output Trig gered by Input Capture

Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA

function s as an input capture register in the TPU channel selected b y PCR, pulse outp u t will be

triggered by the input capture signal.

Figure 12.11 shows the timing of this output.

TIOC pin

Input capture

signal

NDR

PODR

MNPO

Figure 12.11 Pulse Output Trigg ered by Input Capture (Example)

12.5 Usage Notes

12.5.1 Module Stop Mode Setting

PPG operation can be disabled or enabled using the module sto p control register. The initial va lu e

is for PPG operation to be halted. Register access is enabled by clearing module stop mode. For

details, refer to section 22, Power-Down Modes.

12.5.2 Operation of Pulse Output Pins

Pins PO0 to PO15 are also used for other peripheral functions such as the TPU. When output by

another peripheral function is enabled, the corresponding pins cannot be used for pulse output.

Note, however, that data transfer from NDR bits to PODR bits takes place, regardless of the usage

of the pins.

Pin functions should be changed only under conditio ns in which the output trigger even t will not

occur.

Section 12 Programmable Pu lse Generator (PPG)

Rev. 3.00 Mar 17, 2006 page 626 of 926

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Section 13 8-Bit Timers (TMR)

Rev. 3.00 Mar 17, 2006 page 627 of 926

REJ09B0283-0300

Section 13 8-Bit Timers (TMR)

This LSI has an on-chip 8-bit timer module with two channels operating on the basis of an 8-bit

counter. The 8-bit timer module can be used to count external events and be used as a

multifunction timer in a variety of applications, such as generation of counter reset, interrupt

requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two

registers.

13.1 Features

• Selection of four clock sources

The counters can be driven by one of three internal clock signals (φ/8, φ/64, or φ/8192) or an

external clock input

• Selection of three ways to clear the counters

The counters can be cleared on compare match A or B, or by an external reset signal

• Timer output control by a combination of two compare match signals

The timer output signal in each channel is controlled by a combination of two independent

compare ma tch signals, enabling the timer to generate output waveforms with an arbitr ar y duty

cycle or PWM output

• Provision for cascading of two channels (TMR_0 and TMR_1)

Operation as a 16-bit timer is possible, using TMR_0 for the upper 8 bits and TMR_1 for the

lower 8 bits (16-bit count mode)

TMR_1 can be used to count TMR_0 compare matches (compare match count mode)

• Three independent interrupts

Compare match A and B and overflow interrupts can be requested independently

• A/D converter conversion start trigger can be generated

TIMH260A_000020020400

Section 13 8-Bit Timers (TMR)

Rev. 3.00 Mar 17, 2006 page 628 of 926

REJ09B0283-0300

Figure 13.1 shows a block diagram of the 8-bit timer module (TMR_0 and TMR_1).

External clock source Internal clock sources

TMR_0

φ/8

φ/64

φ/8192

TMR_1

φ/8

φ/64

φ/8192

Clock 1

Clock 0

Compare match A1

Compare match A0

Clear 1

CMIA0

CMIB0

OVI0

CMIA1

CMIB1

OVI1

Interrupt signals

TCORA_0 : Time constant register A_0

TCORB_0 : Time constant register B_0

TCNT_0 : Timer counter_0

TCSR_0 : Timer control/status register_0

TCR_0 : Timer control register_0

TCORA_1 : Time constant register A_1

TCORB_1 : Time constant register B_1

TCNT_1 : Timer counter_1

TCSR_1 : Timer control/status register_1

TCR_1 : Timer control register_1

TMO0

TMRI0

Internal bus

TCORA_0

Comparator A_0

Comparator B_0

TCORB_0

TCSR_0

TCR_0

TCORA_1

Comparator A_1

TCNT_1

Comparator B_1

TCORB_1

TCSR_1

TCR_1

TMCI0

TMCI1

TCNT_0

Overflow 1

Overflow 0

Compare match B1

Compare match B0

TMO1

TMRI1

A/D

conversion

start request

signal

Clock select

Control logic

Clear 0

Legend:

Figure 13.1 Block Diagram of 8-Bit Timer Module

Section 13 8-Bit Timers (TMR)

Rev. 3.00 Mar 17, 2006 page 629 of 926

REJ09B0283-0300

13.2 Input/Output Pins

Table 13.1 shows the pin configuration of the 8-bit timer.

Table 13.1 Pin Configuratio n

Channel Name Symbol I/O Function

0 Timer output pin TMO0 Output Outputs at compare match

Timer clock input pin TMCI0 Input Inputs external clock for coun ter

Timer reset input pin TMRI0 Input Inputs external reset to counter

1 Timer output pin TMO1 Output Outputs at compare match

Timer clock input pin TMCI1 Input Inputs external clock for coun ter

Timer reset input pin TMRI1 Input Inputs external reset to counter

13.3 Register Descriptions

The 8-bit timer module has the following registers. For details on the module stop control register,

refer to section 22.1.2 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL).

• Timer counter_0 (TCNT_0)

• Time constant register A_0 (TCORA_0)

• Time constant register B_0 (TCORB_0)

• Timer control register_0 (TCR_0)

• Timer control/status register_0 (TCSR_0)

• Timer counter_1 (TCNT_1)

• Time constant register A_1 (TCORA_1)

• Time constant register B_1 (TCORB_1)

• Timer control register_1 (TCR_1)

• Timer control/status register_1 (TCSR_1)

Section 13 8-Bit Timers (TMR)

Rev. 3.00 Mar 17, 2006 page 630 of 926

REJ09B0283-0300

13.3.1 Timer Counter (TCNT)

TCNT is 8-bit up-counter. TCNT_0 and TCNT_1 comprise a single 16-bit register so they can be

accessed together by a word transfer instruction. Bits CKS2 to CKS0 in TCR are used to select a

clock. TCNT can be cleared by an external reset input or by a compare match signal A or B.

Which signal is to be used for clearing is selected by bits CCLR1 and CCLR0 in TCR. When

TCNT overflo ws f rom H'FF to H'00, OVF in TCSR is set to 1. TCNT is initialized to H'00.

13.3.2 Time Con stant Reg ister A (TCORA)

TCORA is 8-bit readable/writable register. TCORA_0 and TCORA_1 comprise a single 16-bit

The value in TCORA is continually compared with the value in TCNT. When a match is detected,

the corresp ond ing CMFA f lag in TCSR is set to 1. Note, however, that compar ison is disabled

during the T2 state of a TCORA write cycle.

The timer output from the TMO pin can be fr eely controlled by this compare match signal

(compare match A) and the settings of bits OS1 and OS0 in TCSR.

TCORA is initialized to H'FF.

13.3.3 Time Con stant Reg ister B (TCORB)

TCORB is 8-bit readable/writable register. TCORB_0 and TCORB_1 comprise a single 16-bit

TCORB is continually compared with the value in TCNT. When a match is detected, the

corresponding CMFB flag in TCSR is set to 1. Note, however, th at comparison is disabled during

the T2 state of a TCOBR write cycle.

The timer output from the TMO pin can be fr eely controlled by this compare match signal

(compare match B) and the settings of bits OS3 and OS2 in TCSR.

TCORB is initialized to H'FF.

Section 13 8-Bit Timers (TMR)

Rev. 3.00 Mar 17, 2006 page 631 of 926

REJ09B0283-0300

13.3.4 Timer Control Register (TCR)

TCR selects the clock source and the time at which TCNT is cleared, and controls interrupts.

Bit Bit Name Initial Value R/W Description

7 CMIEB 0 R/W Compare Match Interrupt Enable B

Selects whether CMFB interrupt requests

(CMIB) are enabled or disabled when the

CMFB flag in TCSR is set to 1.

0: CMFB interrupt requests (CMIB) are disabled

1: CMFB interrupt requests (CMIB) are enabled

6 CMIEA 0 R/W Compare Match Interrupt Enable A

Selects whether CMFA interrupt requests

(CMIA) are enabled or disabled when the

CMFA flag in TCSR is set to 1.

0: CMFA interrupt requests (CMIA) are disabled

1: CMFA interrupt requests (CMIA) are enabled

5 OVIE 0 R/W Timer Overflow Interrupt Enable

Selects whether OVF interrupt requests (OVI)

are enabled or disabled when the OVF flag in

TCSR is set to 1.

0: OVF interrupt requests (OVI) are disabled

1: OVF interrupt requests (OVI) are enabled

3CCLR1

CCLR0 0

0R/W

R/W Counter Clear 1 and 0

These bits select the method by which TCNT is

cleared

00: Clearing is disabled

01: Clear by compare match A

10: Clear by compare match B

11: Clear by rising edge of external reset input

CKS2

CKS1

CKS0

R/W

Clock Select 2 to 0

These bits select the clock input to TCNT and

count condition. See table 13.2.

Section 13 8-Bit Timers (TMR)

Rev. 3.00 Mar 17, 2006 page 632 of 926

REJ09B0283-0300

Table 13.2 Clock Input to TCNT and Count Condition

TCR

Channel Bit 2

CKS2 Bit 1

CKS1 Bit 0

CKS0 Description

TMR_0 0 0 0 Clock input disabled

1 Internal clock, counted at falling edge of φ/8

1 0 Internal clock, counted at falling edge of φ/64

1 Internal clock, counted at falling edge of φ/8192

1 0 0 Count at TCNT_1 overflow signal*

TMR_1 0 0 0 Clock input disabled

1 Internal clock, counted at falling edge of φ/8

1 0 Internal clock, counted at falling edge of φ/64

1 Internal clock, counted at falling edge of φ/8192

1 0 0 Count at TCNT_0 compare match A*

All 1 0 1 External clock, counted at rising edge

1 0 External clock, counted at falling edge

1 1 External clock, counted at both rising and falling edges

Note: *If the count input of TMR_0 is the TCNT_1 overflow sign al and that of TMR _1 is the

TCNT_0 compare mat ch sig nal, no incr em enti ng clock is generated. Do not use this

setting.

Section 13 8-Bit Timers (TMR)

Rev. 3.00 Mar 17, 2006 page 633 of 926

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13.3.5 Timer Control/Status Register (TCSR)

TCSR displays status flags, and controls compare match output.

TCSR_0

Bit Bit Name Initial Value R/W Description

7CMFB 0 R/(W)

*Compare Match Flag B

[Setting condition]

Set when TCNT matches TCORB

[Clearing cond iti ons ]

• Cleared by reading CMFB when CMFB = 1,

then writing 0 to CMFB

• When DTC is activat ed by CMIB interru pt

while DISEL bit of MRB in DTC is 0

6CMFA 0 R/(W)

*Compare Match Flag A

[Setting condition]

Set when TCNT matches TCORA

[Clearing cond iti ons ]

• Cleared by reading CMFA when CMFA = 1,

then writing 0 to CMFA

• When DTC is activat ed by CMIA interru pt

while DISEL bit of MRB in DTC is 0

5OVF 0 R/(W)

*Timer Overflow Flag

[Setting condition]

Set when TCNT overflows from H'FF to H'00

[Clearing cond iti on]

Cleared by reading OVF when OVF = 1, then

writing 0 to OVF

4 ADTE 0 R/W A/D Tri gger Enable

Selects enablin g or disabl ing of A/D con vert er

start requests by compare match A.

0: A/D converter start requests by compare

match A are disabled

1: A/D converter start requests by compare

match A are enabled

Section 13 8-Bit Timers (TMR)

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Bit Bit Name Initial Value R/W Description

2OS3

OS2 0

0R/W

R/W Output Select 3 and 2

These bits select a method of TMO pin output

when compare match B of TCORB and TCNT

occurs.

00: No change when compare match B occurs

01: 0 is output when compare match B occurs

10: 1 is output when compare match B occurs

11: Output is inverted when compare match B

occurs (toggle output)

0OS1

OS0 0

0R/W

R/W Output Select 1 and 0

These bits select a method of TMO pin output

when compare match A of TCORA and TCNT

occurs.

00: No change when compare match A occurs

01: 0 is output when compare match A occurs

10: 1 is output when compare match A occurs

11: Output is inverted when compare match A

occurs (toggle output)

Note: *Only 0 can be written to bits 7 to 5, to clear these flags.

Section 13 8-Bit Timers (TMR)

Rev. 3.00 Mar 17, 2006 page 635 of 926

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TCSR_1

Bit Bit Name Initial Value R/W Description

7CMFB 0 R/(W)

*Compare Match Flag B

[Setting condition]

Set when TCNT matches TCORB

[Clearing cond iti ons ]

• Cleared by reading CMFB when CMFB = 1,

then writing 0 to CMFB

• When DTC is activat ed by CMIB interru pt

while DISEL bit of MRB in DTC is 0

6CMFA 0 R/(W)

*Compare Match Flag A

[Setting condition]

Set when TCNT matches TCORA

[Clearing cond iti ons ]

• Cleared by reading CMFA when CMFA = 1,

then writing 0 to CMFA

• When DTC is activat ed by CMIA interru pt

while DISEL bit of MRB in DTC is 0

5OVF 0 R/(W)

*Timer Overflow Flag

[Setting condition]

Set when TCNT overflows from H'FF to H'00

[Clearing cond iti on]

Cleared by reading OVF when OVF = 1, then

writing 0 to OVF

4— 1 R Reserved

This bit is always read as 1 and cann ot be

modified.

Section 13 8-Bit Timers (TMR)

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Bit Bit Name Initial Value R/W Description

2OS3

OS2 0

0R/W

R/W Output Select 3 and 2

These bits select a method of TMO pin output

when compare match B of TCORB and TCNT

occurs.

00: No change when compare match B occurs

01: 0 is output when compare match B occurs

10: 1 is output when compare match B occurs

11: Output is inverted when compare match B

occurs (toggle output)

0OS1

OS0 0

0R/W

R/W Output Select 1 and 0

These bits select a method of TMO pin output

when compare match A of TCORA and TCNT

occurs.

00: No change when compare match A occurs

01: 0 is output when compare match A occurs

10: 1 is output when compare match A occurs

11: Output is inverted when compare match A

occurs (toggle output)

Note: *Only 0 can be written to bits 7 to 5, to clear these flags.

13.4 Operation

13.4.1 Pulse Output

Figure 13.2 shows an example that the 8-bit timer is used to generate a pulse output with a

selected duty cycle. The control bits are set as follows:

[1] In TCR, bit CCLR1 is cleared to 0 and bit CCLR0 is set to 1 so that the timer counter is

cleared at a TCORA compare match.

[2] In TCSR, bits OS3 to OS0 are set to B'0110, causing the output to change to 1 at a TCORA

compare match and to 0 at a TCORB compare match.

With these settings, the 8-bit timer provides output o f pulses at a rate determined by TCORA with

a pulse width d etermined by TCORB. No software intervention is required.

Section 13 8-Bit Timers (TMR)

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TCNT

H'FF Counter clear

TCORA

TCORB

H'00

TMO

Figure 13.2 Example of Pulse Output

13.5 Operation Timing

13.5.1 TCNT Incrementation Timing

Figure 13.3 shows the count timing for internal clock input. Figure 13.4 shows the count timing

for external clock signal. Note that the external clock pulse width must be at least 1.5 states for

incrementation at a single edge, and at least 2.5 states for incrementation at both edges. The

counter will not increment correctly if the pulse width is less than these values.

Internal clock

Clock input

to TCNT

TCNT N–1 N N+1

Figure 13.3 Count Timing for Internal Clock Input

Section 13 8-Bit Timers (TMR)

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External clock

input pin

Clock input

to TCNT

TCNT N–1 N N+1

Figure 13.4 Count Timing for External Clock Input

13.5.2 Timing of CMFA and CMFB Setting when Compare-Match Occurs

The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the

TCOR and TCNT values match. The compare match signal is generated at the last state in which

the match is true , just before the timer counter is updated . Therefore, when TCOR and TCNT

match, the compare match signal is not generated until the next incrementation clock input. Figure

13.5 shows this timing.

TCNT N N+1

TCOR N

Compare match

signal

CMF

Figure 13.5 Timing of CMF Setting

Section 13 8-Bit Timers (TMR)

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13.5.3 Timing of Timer Output when Compare-Match Occurs

When compare match A or B occurs, the timer output changes as specified by bits OS3 to OS0 in

TCSR.

Figure 13.6 shows the timing when the output is set to toggle at compare match A.

Compare match A

signal

Timer output pin

Figure 13.6 Timing of Timer Output

13.5.4 Timing of Compare Match Clear

TCNT is cleared when compare match A or B occurs, depending on the setting of the CCLR1 and

CCLR0 bits in TCR. Figure 13.7 shows the timing of this operation.

N H'00

Compare match

signal

TCNT

Figure 13.7 Timing of Compare Match Clear

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13.5.5 Timing of TCNT External Reset

TCNT is cleared at the rising edge of an external reset input, depending on the settings of the

CCLR1 and CCLR0 bits in TCR. The clear pulse width must be at least 1.5 states. Figure 13.8

shows the timing of this operation.

Clear signal

External reset

input pin

TCNT N H'00N–1

Figure 13.8 Timing of Clearance by External Reset

13.5.6 Timing of Overflow Flag (O VF) Setting

The OVF in TCSR is set to 1 when TCNT overflows (changes from H'FF to H'00). Figure 13.9

shows the timing of this operation.

OVF

Overflow signal

TCNT H'FF H'00

Figure 13.9 Timing of OVF Setting

Section 13 8-Bit Timers (TMR)

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13.6 Operation with Cascaded Connection

If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two

channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit counter

mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1

(compare match count mode). In this case, the timer operates as below.

13.6.1 16-Bit Counter Mode

When bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer

with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits.

[1] Setting of compare match flags

• The CMF flag in TCSR_0 is set to 1 when a 16-bit compare match event occurs.

• The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare match event occurs.

[2] Counter clear specification

• If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare match, the

16-bit counters (TCNT_0 and TCNT_1 together) are cleared when a 16-bit compare match

event occurs. The 16-bit counters (TCNT0 and TCNT1 together) are cleared even if counter

clear by the TMRI0 pin has also been set.

• The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot be

cleared independently.

[3] Pin output

• Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR_0 is in accordance with the

16-bit compare match conditions.

• Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR_1 is in accordance with the

lower 8-bit comp are match conditions.

13.6 .2 Compare Match Count Mode

When bits CKS2 to CKS0 in TCR_1 are B'100, TCNT_1 counts compare match A’s for channel

Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag,

generation of interrupts, output from the TMO pin, and counter clear are in accordan ce with the

settings for each channel.

Section 13 8-Bit Timers (TMR)

Rev. 3.00 Mar 17, 2006 page 642 of 926

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13.7 Interrupts

13.7.1 Interrupt Sources and DTC Activa tion

There are three 8-bit timer in ter rup t so urces: CMIA, CMIB, and OVI. Their r elative priorities are

shown in table 13.3. Each interrupt source is set as enabled or disabled by the corresponding

interrupt enable bit in TCR or TCSR, and independent interrupt requests are sent for each to the

interrup t controller. It is also possible to activate the DTC by m e ans o f CMI A and CMIB

interrupts.

Table 13.3 8-Bit Timer Interrupt Sources

Name Interrupt Source Interrupt Flag DTC Activation Priority

CMIA0 TCORA_0 compare match CMFA Possible High

CMIB0 TCORB_0 compare match CMFB Possible

OVI0 TCNT_0 overflow OVF Not possible Low

CMIA1 TCORA_1 compare match CMFA Possible High

CMIB1 TCORB_1 compare match CMFB Possible

OVI1 TCNT_1 overflow OVF Not possible Low

13.7.2 A/D Converter Activation

The A/D converter can be activated on ly by TMR_0 compare match A.

If the ADTE bit in TCSR0 is set to 1 when the CMFA flag is set to 1 by the occurr ence of TMR_0

compare match A, a request to start A/D conversion is sent to the A/D converter. If the 8-bit timer

conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is

started.

Section 13 8-Bit Timers (TMR)

Rev. 3.00 Mar 17, 2006 page 643 of 926

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13.8 Usage Notes

13.8.1 Contention between TCNT Write and Clea r

If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear

takes prior ity, so that the counter is cleared and th e wr ite is not performed.

Figure 13.10 shows this operation.

Address TCNT address

Internal write signal

Counter clear signal

TCNT N H'00

TCNT write cycle by CPU

Figure 13.10 Contention between TCNT Write and Clear

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13.8.2 Contention between TCNT Write and Increment

If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write

takes priority and the counter is not incremented.

Figure 13.11 shows this operation.

Address TCNT address

Internal write signal

TCNT input clock

TCNT NM

TCNT write cycle by CPU

Counter write data

Figure 13.11 Contention between TCNT Write and Increment

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13.8.3 Contention between TCOR Wr it e and Compare Mat c h

During the T2 state of a TCOR write cycle, the TCOR write has priority and the compare match

signal is inhibited even if a compare match event occurs as shown in figure 13.12.

Address TCOR address

Internal write signal

TCNT

TCOR NM

T1T2

TCOR write cycle by CPU

TCOR write data

N N+1

Compare match signal

Prohibited

Figure 13.12 Contention between TCOR Write and Compare Match

Section 13 8-Bit Timers (TMR)

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13.8.4 Contention between Compare Matches A and B

If compare match events A and B occur at the same time, the 8-bit timer operates in accordan ce

with the prio rities for the output statuses set for compare match A and compare match B, as shown

in table 13.4.

Table 13.4 Timer Output Priorities

Output Setting Priority

Toggle output High

1 output

0 output

No change Low

13.8.5 Switching of Internal Clocks and TCNT Operation

TCNT may increment erroneously when the internal clock is switched over. Table 13.5 shows the

relationship between the timin g at which the internal clock is switched ( by writing to the CKS1

and CKS0 bits) and the TCNT op eration.

When the TCNT clock is generated from an internal clock, the falling edge of the internal clock

pulse is detected. If clock switching causes a change from high to low level, as shown in case 3 in

table 13.5, a TCNT clock pulse is generated on the assumption that the switchover is a falling

edge. This increments TCNT.

The erroneous incrementation can also happen when switching between internal and external

clocks.

Section 13 8-Bit Timers (TMR)

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Table 13.5 Switching of Internal Clock and TCNT Operation

No.

Timing of Switchover

by Means of CKS1

and CKS0 Bits TCNT Clock Operation

1 Switching from

low to low*1

Clock before

switchover

Clock after

switchover

TCNT clock

TCNT

CKS bit write

NN + 1

2 Switching from

low to high*2

Clock before

switchover

Clock after

switchover

TCNT clock

TCNT

CKS bit write

N N + 1 N + 2

3 Switching from

high to low*3

Clock before

swichover

Clock after

swichover

TCNT clock

TCNT

CKS bit write

N N + 1 N + 2

Section 13 8-Bit Timers (TMR)

Rev. 3.00 Mar 17, 2006 page 648 of 926

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No.

Timing of Switchover

by Means of CKS1

and CKS0 Bits TCNT Clock Operation

4 Switching from high

to high

Clock before

switchover

Clock after

switchover

TCNT clock

TCNT

CKS bit write

N N + 1 N + 2

Notes: 1. Includes switching from low to stop, and from stop to low.

2. Includes switching from stop to high.

3. Includes switching from high to stop.

4. Generated on the assumption that the switchover is a falling edge; TCNT is

incremented.

13.8.6 Mode Setting with Cascaded Connection

If 16-bit counter mode and compare match count mode are specified at the same time, input clocks

for TCNT_0 and TCNT_1 are not generated, and the counter stops. Do not specify 16-bit counter

and compare match count modes simultaneously.

13.8 .7 Interrupts i n Module Stop Mode

If module stop mode is entered when an inter rupt has been requested, it will not be possible to

clear the CPU interrupt source or the DTC and DMAC activation source. Interrupts should

therefore be disabled before entering module stop mode.

Section 14 Watchdog Timer

Rev. 3.00 Mar 17, 2006 page 649 of 926

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Section 14 Watchdog Timer

The watchdog timer ( WDT) is an 8-bit timer that outputs an overflow signal (WDTOVF) if a

system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow.

At the same time, the WDT can also generate an internal reset signal.

When this watchdog function is not needed, the WDT can be used as an in terval timer. In interval

timer operation, an interval timer interrupt is generated each time the counter overflows.

The block diagram of the WDT is shown in figure 14.1.

14.1 Features

• Selectable from eight counter input clocks

• Switchable between watchdog timer mode and interval timer mode

In watchdog timer mode

• If the counter overflows, the WDT outputs WDTOVF. It is possible to select whether or not

the entire chip is r e set at the same time.

In interval tim er mo d e

• If the counter overflows, the WDT g e n e r ates an interval timer interrupt ( WOVI) .

WDT0101A_010020020400

Section 14 Watchdog Timer

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Overflow

Interrupt

control

WOVI

(interrupt request

signal)

Internal reset signal*

WDTOVF Reset

control

RSTCSR TCNT TSCR

φ/2

φ/64

φ/128

φ/512

φ/2048

φ/8192

φ/32768

φ/131072

Clock Clock

select

Internal clock

sources

Bus

interface

Module bus

TCSR

TCNT

RSTCSR

Note: * An internal reset signal can be generated by the register setting.

: Timer control/status register

: Timer counter

: Reset control/status register

WDT

Legend:

Internal bus

Figure 14.1 Block Diagram of WDT

14.2 Input/Output Pin

Table 14.1 shows the WDT pin configuration.

Table 14.1 Pin configuration

Name Symbol I/O Function

Watchdog timer overf low WDTOVF Output Outputs counter overflow si gnal in watchdog

time r mode

14.3 Register Descriptions

The WDT has the follo win g three registers. To prevent accidental overwriting, TCSR, TCNT, and

RSTCSR have to be written to in a method different from normal registers. For details, refer to

section 14.6.1, Notes on Register Access.

• Timer counter (TCNT)

• Timer con trol/status register ( TCSR)

• Reset contro l/status register (RSTCSR)

Section 14 Watchdog Timer

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14.3.1 Timer Counter (TCNT)

TCNT is an 8-bit read able/writable up-counter. TCNT is initialized to H'00 when the TME bit in

TCSR is cleared to 0.

14.3.2 Timer Control/Status Register (TCSR)

TCSR selects the clock source to be input to TCNT, and the timer mode.

Bit Bit Name Initial Value R/W Description

7OVF 0 R/(W)

*Overflow Flag

Indicates that TCNT has overflowed in interval

timer mode. Only a write of 0 is permitted, to clear

the flag.

[Setting condition]

When TCNT overflows in interval timer mode

(changes from H’FF to H’00)

When internal reset request generation is selected

in watchdog timer mode, OVF is cleared

automatica lly by the internal reset.

[Clearing cond iti on]

Cleared by reading TCSR when OVF = 1, then

writing 0 to OVF

6WT/IT 0 R/W Timer Mode Select

Selects whether the WDT is used as a watchdog

timer or interval timer.

0: Interval timer mode

When TCNT overflows, an interval timer

interrupt (WOVI) is requested.

1: Watchdog timer mode

When TCNT overflows, the WDTOVF signal is

output.

5 TME 0 R/W Timer Enable

When this bit is set to 1, TCNT starts counting.

When this bit is cleared, TCNT stops counting and

is initialized to H'00.

Section 14 Watchdog Timer

Rev. 3.00 Mar 17, 2006 page 652 of 926

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Bit Bit Name Initial Value R/W Description

4, 3 — All 1 — Reserved

These bits are always read as 1 and cannot be

modified.

CKS2

CKS1

CKS0

R/W

Clock Select 2 to 0

Selects the clock source to be input to TCNT. The

overflow frequency for φ = 20 MHz is enclosed in

parentheses.

000: Clock φ/2 (frequency: 25.6 µs)

001: Clock φ/64 (frequency: 819.2 µs)

010: Clock φ/128 (frequency: 1.6 ms)

011: Clock φ/512 (frequency: 6.6 ms)

100: Clock φ/2048 (frequency: 26.2 ms)

101: Clock φ/8192 (frequency: 104.9 ms)

110: Clock φ/32768 (frequency: 419.4 ms)

111: Clock φ/131072 (frequency: 1.68 s)

Note: *Only a write of 0 is permitted, to clear the flag.

Section 14 Watchdog Timer

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14.3.3 Reset Control/Status Register (RSTCSR)

RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects

the type of inter nal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin,

but not by the WDT internal reset signal caused by overflows.

Bit Bit Name Initial Value R/W Description

7WOVF 0 R/(W)

*Watchdog Time r Overflow Flag

This bit is set when TCNT overflow s in wat chdo g

timer mode. This bit cannot be set in interval timer

mode, and only 0 can be written.

[Setting condition]

Set when TCNT overflows (changed from H'FF to

H'00) in watchdog timer mode

[Clearing cond iti on]

Cleared by reading RSTCSR when WOVF = 1,

and then writing 0 to WOVF

6 RSTE 0 R/W Reset Enable

Specifies whether or not a reset signal is

generated in the chip if TCNT overflows during

watchdog timer operation.

0: Reset signal is not generated even if TCNT

overflows

(Though this LSI is not reset, TCNT and TCSR

in WDT are reset)

1: Reset signal is generated if TCNT overflows

5— 0 R/WReserved

Can be read and written, but does not affect

operation.

— All 1 — Reserved

These bits are always read as 1 and cannot be

modified.

Note: *Only a write of 0 is permitted, to clear the flag.

Section 14 Watchdog Timer

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14.4 Operation

14.4.1 Watchdog Timer Mode

To use the WDT as a watchdog timer mode, set the WT/IT and TME bits in TCSR to 1.

If TCNT overflows without being rewritten because of a system crash or other error, the

WDTOVF signal is output.

This ensures that TCNT does not overflow while the sy stem is operating normally. Software must

prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before

overflow occurs. This WDTOVF signal can be used to reset the chip internally in watchdog timer

mode.

If TCNT over f lows when 1 is set in the RSTE bit in RSTCSR, a signal that re sets this LSI

internally is g e n e r a ted at the sam e tim e as the WDTOVF signal. If a reset caused by a signal input

to the RES pin occurs at the same time as a reset caused by a WDT overflow, the RES pin reset

has priority and the WOVF bit in RSTCSR is cleared to 0.

The WDTOVF signal is output for 132 states when RSTE = 1, and for 130 states when RSTE = 0.

The internal r e set signal is output f or 5 18 states.

When TCNT overflows in watchdog timer mode, the WOVF bit in RSTCSR is set to 1. If TCNT

overflo w s when 1 is set in the RSTE bit in RSTCSR, an internal r e set signal is gener a ted to the

entire chip.

Section 14 Watchdog Timer

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TCNT count

H'00 Time

H'FF

WT/IT=1

TME=1 H'00 written

to TCNT WT/IT=1

TME=1 H'00 written

to TCNT

132 states

518 states

WDTOVF signal

Internal reset signal*

WT/IT

TME

Notes: 1. If TCNT overflows when the RSTE bit is set to 1, an internal reset signal is generated.

2. 130 states when the RSTE bit is cleared to 0.

Overflow

WDTOVF and

internal reset are

generated

WOVF=1

: Timer mode select bit

: Timer enable bit

Legend:

Figure 14.2 Operation in Watchdog Timer Mode

14.4.2 Interval Timer Mode

To use the WDT as an interval timer, set the WT/IT bit to 0 and TME bit in TCSR to 1.

When the WDT is used as an interval timer, an interv al tim er interrupt ( WOVI) is generated each

time the TCNT overflows. Therefore, an interrupt can be gener ated at inter vals.

When the TCNT overflows in in terval tim er mode, an interval timer interrupt ( WOVI) is r e q uested

at the same time the OVF bit in the TCSR is set to 1.

Section 14 Watchdog Timer

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TCNT count

H'00 Time

H'FF

WT/IT=0

TME=1 WOVI

Overflow Overflow Overflow Overflow

Legend:

WOVI: Interval timer interrupt request generation

WOVI WOVI WOVI

Figure 14.3 Operation in Interval Timer Mode

14.5 Interrupt Source

During interval timer mode operation, an overflow gener ates an interval timer interrupt (WOVI) .

The interval timer interrupt is requested wh enever the OVF flag is set to 1 in TCSR. OVF mu st be

cleared to 0 in the interrupt handling routine.

Table 14.2 WDT Interrupt Source

Name Interrupt Source Interrupt Flag DTC Activation

WOVI TCNT overflow OVF Impossible

14.6 Usage Notes

14.6.1 Notes on Register Access

The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being

more difficult to wr ite to. The procedures for writing to and r eadin g these registers are given

below.

Section 14 Watchdog Timer

Rev. 3.00 Mar 17, 2006 page 657 of 926

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Writing to TCNT, TCSR, and RSTCSR

TCNT and TCSR must be written to by a word transfer instruction. They cannot be written to by a

byte transfer instruction.

TCNT and TCSR both h a ve the same write address. Ther efore, satisfy the relative cond ition

shown in f igure 14.4 to write to TCNT or TCSR. The transfer instruction writes the lower byte

data to TCNT or TCSR according to the satisfied condition.

To write to RSTCSR, execute a word transfer instruction for address H'FFBE. A byte transfer

instruction cannot perform writing to RSTCSR.

The method of writing 0 to the WOVF bit differs from th at of writing to the RSTE bit. To write 0

to the WOVF bit, satisfy the lower con dition shown in figu r e 14.4.

If satisfied, the tr ansfer instru ction clear s the WOVF bit to 0, but h a s no effect on the RSTE bit.

To write to the RSTE b it, satisf y the above condition sh own in figure 14.4. If satisfied, the transfer

instruction writes the value in bit 6 of th e lower byte into the RSTE bit, bu t has no effect on the

WOVF bit.

TCNT write or

Writing to RSTE bit in RSTCSR

TCSR write

Address: H'FFBC (TCNT)

H'FFBE (RSTCSR) 15 8 7 0

H'5A Write data

Address: H'FFBC (TCSR) 15 8 7 0

H'A5 Write data

Writing 0 to WOVF bit in RSTCSR

Address: H'FFBE (RSTCSR) 15 8 7 0

H'A5 H'00

Figure 14.4 Writing to TCNT, TCSR, and RSTCSR

Reading TCNT, TCSR, and RSTCSR

These registers are read in the same way as other registers. The read addresses are H'FFBC for

TCSR, H'FFBD for TCNT, and H'FFBF for RSTCSR.

Section 14 Watchdog Timer

Rev. 3.00 Mar 17, 2006 page 658 of 926

REJ09B0283-0300

14.6.2 Contention between Timer Counter (TCNT) Write and Increment

If a timer counter clock pulse is generated during the next cycle after the T2 state of a TCNT write

cycle, the write takes priority and the timer coun ter is not in cremented. Figure 14.5 sh ows this

operation.

Address

Internal write signal

TCNT input clock

TCNT NM

T1T2Next cycle

TCNT write cycle

Counter write data

Figure 14.5 Contention between TCNT Write and Increment

14.6.3 Changing Value of CKS2 to CKS0

If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, error s could occur in

the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0 ) before

changing the value of bits CKS2 to CKS0.

14.6.4 Switching betw een Watchdo g Timer Mode a nd Interval Timer Mode

If the mode is switche d from watchdog timer to interval timer, while the WDT is op er a ting, errors

could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME

bit to 0) before switching the mode.

Section 14 Watchdog Timer

Rev. 3.00 Mar 17, 2006 page 659 of 926

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14.6.5 Internal Reset in Watchdog Timer Mode

This LSI is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during

watchdog timer mode operation, but TCNT and TCSR of the WDT are reset.

TCNT, TCSR, and RSTCR cannot be written to while the WDTOVF signal is low. Also note that

a read of the WOVF flag is not recognized during this period. To clear the WOVF flag, therefore,

read TCSR after the WDTOVF signal goes high, then write 0 to the WOVF flag.

14.6.6 System Reset by WDTOVF

WDTOVFWDTOVF

WDTOVF Signal

If the WDTOVF output signal is input to the RES pin, the chip will not be initialized correctly.

Make sure that the WDTOVF signal is not input logically to the RES pin.

To reset the entire system by means of the WDTOVF signal, use the circuit shown in figure 14.6.

Reset input

Reset signal to entire system

This LSI

RES

WDTOVF

Figure 14.6 Circuit for System Reset by WDTOVF

WDTOVFWDTOVF

WDTOVF Signal (Example)

Section 14 Watchdog Timer

Rev. 3.00 Mar 17, 2006 page 660 of 926

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Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 661 of 926

REJ09B0283-0300

Section 15 Serial Communication Interface (SCI, IrDA)

This LSI has three independent serial communication interface (SCI) channels. The SCI can

handle both asynchronous and clocked synchronous serial communication. Serial data

communication can be carried out with standard asynchronous communication ch ips such as a

Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication

Interface Adapter (ACIA). A function is also provided for serial communication between

processors (multiprocessor communication function) in asynchronous mode. The SCI also

supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as

an asynchronous serial communication interface extension function. One of the three SCI channels

(SCI_0) can generate an IrDA communication waveform conforming to IrDA specification

version 1.0.

Figure 15.1 shows a block diagram of the SCI.

15.1 Features

• Choice of asynchronous or clocked synchronous serial communication mode

• Full-duplex communication capab ility

The transmitter and receiver are mutually independent, enablin g transmission and reception to

be executed simultan eously. Double-buffering is used in both the transmitter and the receiver,

enabling continuous transmission and continuous reception of serial data.

• On-chip baud rate generator allows any bit rate to be selected

External clock can be selected as a transfer clock source (except for in Smart Card interface

mode).

• Choice of LSB-first or MSB- first transfer (except in the case of asynchronous mode 7-bit data)

• Four interrupt sources

Four interrupt sources — transmit-end, transmit-data-empty, receive-data-full, and receive

error — that can issue requests. The transmit-data-empty interrupt and receive data full

interrupts can activate the data transfer con troller ( DTC) or DMA controller (DMAC).

• Module stop mode can be set

Asynchronous mode

• Data length: 7 or 8 bits

• Stop bit length: 1 or 2 bits

• Parity: Even, odd, or none

• Receive error detection: Parity, overrun, and framing errors

SCI0020A_000020020400

Section 15 Seri al Communication Interface (SCI, IrDA)

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• Break detection: Break can be detected by reading the RxD pin level directly in case of a

framing error

• Average transfer rate generator (only for H8S/2678R Group): The following transfer rate can

be selected (SCI_2 only)

115.152 or 460.606 kbps at 10.667-MHz operation

115.196, 460.784 or 720 kbps at 16-MHz operation

720 kbps at 32-MHz operation

Clocked Synchronous mode

• Data length: 8 bits

• Receive error detection: Overrun errors detected

Smart Card Interface

• Automatic transmission of error signal (parity error) in receive mode

• Error signal detection and automatic d ata retransmission in transmit mode

• Direct convention and inverse convention both supported

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 663 of 926

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RxD

TxD

SCK

Clock

External clock

φ/4

φ/16

φ/64

TEI

TXI

RXI

ERI

SCMR

SSR

SCR

SMR

SEMR*

Transmission/

reception control

Baud rate

generator

BRR

Module data bus

RDR

TSRRSR

Parity generation

Parity check

TDR

Bus interface

Internal

data bus

Average transfer

rate generator*

(SCI_2)

10.667-MHz operation

• 115.152 kbps

• 460.606 kbps

16-MHz operation

• 115.196 kbps

• 460.784 kbps

• 720 kbps

32-MHz operation

• 720 kbps

Legend:

RSR : Receive shift register

RDR : Receive data register

TSR : Transmit shift register

TDR : Transmit data register

SMR : Serial mode register

SCR : Serial control register

SSR : Serial status register

SCMR : Smart card mode register

BRR : Bit rate register

SEMR : Serial extension mode register (only in SCI_2)

Note: * Only in H8S/2678R Group.

Figure 15.1 Block Diagram of SCI

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 664 of 926

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15.2 Input/Output Pins

Table 15.1 shows the pin configuration of the serial communication interface.

Table 15.1 Pin Configuratio n

Channel Pin Name*I/O Function

SCK0 I/O Channel 0 clock input/output

RxD0/IrRxD Input Channel 0 receive data input (normal/IrDA)

TxD0/IrTxD Output Channel 0 transmit data output (normal/IrDA)

SCK1 I/O Channel 1 clock input/output

RxD1 Input Channel 1 receive data input

TxD1 Output Channel 1 transmit data output

SCK2 I/O Channel 2 clock input/output

RxD2 Input Channel 2 receive data input

TxD2 Output Channel 2 transmit data output

Note: *Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the

channel designation.

15.3 Register Descriptions

The SCI has the following registers. The serial mode register (SMR), serial status register (SSR),

and serial control register (SCR) are described separately for normal serial communication

interface mode and Smart Card interface mode because their bit functions partially differ.

• Receive shift register_0 (RSR_0)

• Transmit shift register_0 (TSR_0)

• Receive data register_0 (RDR_0)

• Transmit data register_0 (TDR_0)

• Serial mode register_0 (SMR_0)

• Serial control register_0 (SCR_0)

• Serial status register_0 (SSR_0)

• Smart card mode register_0 (SCMR_0)

• Bit rate register_0 (BRR_0)

• IrDA control regist er_0 (IrC R _0)

• Receive shift register_1 (RSR_1)

• Transmit shift register_1 (TSR_1)

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 665 of 926

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• Receive data register_1 (RDR_1)

• Transmit data register_1 (TDR_1)

• Serial mode register_1 (SMR_1)

• Serial control register_1 (SCR_1)

• Serial status register_1 (SSR_1)

• Smart card mode register_1 (SCMR_1)

• Bit rate register_1 (BRR_1)

• Receive shift register_2 (RSR_2)

• Transmit shift register_2 (TSR_2)

• Receive data register_2 (RDR_2)

• Transmit data register_2 (TDR_2)

• Serial mode register_2 (SMR_2)

• Serial control register_2 (SCR_2)

• Serial status register_2 (SSR_2)

• Smart card mode register_2 (SCMR_2)

• Bit rate register_2 (BRR_2)

• Serial extension mode register (SEMR)*

Note: * Only in H8S/2678R Group.

15.3.1 Receive Shift Register (RSR)

RSR is a shift register used to receive serial data that is input to the RxD pin and convert it into

parallel data. When one byte of data has been received, it is transferred to RDR automatically.

RSR cannot be directly accessed by the CPU.

15.3.2 Receive Data Register (RDR)

RDR is an 8-bit register that stores receive data. When the SCI has received one byte of serial

data, it transfers the received serial data from RSR to RDR where it is stored. After this, RSR is

receive-enabled. Since RSR and RDR function as a double buffer in this way, enables continuous

receive operations to be performed. After confirming that the RDRF bit in SSR is set to 1, read

RDR for only once. RDR cannot be written to by the CPU.

Section 15 Seri al Communication Interface (SCI, IrDA)

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15.3.3 Transmit Data Register (TDR)

TDR is an 8-bit r e gister that stores tr ansmit data. When the SCI detects that TSR is empty, it

transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered

structures of TDR and TSR enable continuous serial transmission. If the next transmit data has

already been written to TDR during serial transmission , the SCI transfers the written data to TSR

to continue transmission. Although TDR can be read or written to by the CPU at all times, to

achieve reliable ser ial tr ansmission, write transmit data to TDR f or only once after confirming that

the TDRE bit in SSR is set to 1.

15.3.4 Transmit Shift Register (TSR)

TSR is a shift register that transmits serial d ata. To perform serial data transmissio n, the SCI first

transfers tran smit data from TDR to TSR, th en sends the data to the Tx D pin star ting. TSR cannot

be directly accessed by the CPU.

15.3.5 Serial Mode Register (SMR)

SMR is used to set the SCI’s serial transfer format and select the on-chip baud rate generato r clock

source.

Some bit functions of SMR differ in normal serial communication interface mode and Smart Card

interface mode.

Section 15 Seri al Communication Interface (SCI, IrDA)

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Normal Serial Communication Interface Mode (When SMIF in SCMR is 0)

Bit Bit Name Initial Value R/W Description

7C/A0 R/W Communication Mode

0: Asynchronous mode

1: Clocked synchronous mode

6 CHR 0 R/W Character Length (enabled only in asynchronous

mode)

0: Selects 8 bits as the data length.

1: Selects 7 bits as the data length. LSB-first is

fixed and the MSB (bit 7) of TDR is not

transmitted in transm i ssi on.

In clocked synchronous mode, a fixed data length

of 8 bits is used.

5 PE 0 R/W Parity Enable (enabled only in asynchronous

mode)

When this bit is set to 1, the parity bit is added to

transmit data before transmission, and the parity

bit is checked in reception. For a multiprocessor

format, parity bit addition and checking are not

performed regardless of the PE bit setting.

4O/E0 R/W Parity Mode (enabled only when the PE bit is 1 in

asynchronous mode)

0: Selects even parity.

1: Selects odd parity.

3 STOP 0 R/W Stop Bit Length (enabled only in asynchronous

mode)

Selects the stop bit length in transm i ss ion.

0: 1 stop bit

1: 2 stop bits

In reception, only the first stop bit is checked

regardless of the STOP bit setting. If the second

stop bit is 0, it is treated as the start bit of the next

transmit charact er.

Section 15 Seri al Communication Interface (SCI, IrDA)

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Bit Bit Name Initial Value R/W Description

2 MP 0 R/W Multiprocessor Mode (enabled only in

asynchronous mode)

When this bit is set to 1, the multiprocessor

communication function is enabled. The PE bit

and O/E bit settings are invalid in multiprocessor

mode.

0CKS1

CKS0 0

0R/W

R/W Clock Select 1 and 0:

These bits select the clock source for the on-chip

baud rate generator.

00: φ clock (n = 0)

01: φ/4 clock (n = 1)

10: φ/16 clock (n = 2)

11: φ/64 clock (n = 3)

For the relation between the bit rate register

setting and the baud rate, see section 15.3.9, Bit

Rate Register (BRR). n is the decimal display of

the value of n in BRR (see section 15.3.9, Bit Rate

Smart Card Interf ace Mode (When SMIF in SCMR is 1)

Bit Bit Name Initial Value R/W Description

7 GM 0 R/W GSM Mode

When this bit is set to 1, the SCI operates in GSM

mode. In GSM mode, the timing of the TEND

setting is advanced by 11.0 etu (Elementary Time

Unit: the time for transfer of one bit), and clock

output control mode addition is performed. For

details, refer to section 15.7.8, Clock Output

Control.

6 BLK 0 R/W When this bit is set to 1, the SCI operates in block

transfer mode. For details on block transfer mode,

refer to section 15.7.3, Block Transfer Mode.

5 PE 0 R/W Parity Enable (enabled only in asynchronous

mode)

When this bit is set to 1, the parity bit is added to

transmit data before transmission, and the parity

bit is checked in reception. In Smart Card

interface mode, this bit must be set to 1.

Section 15 Seri al Communication Interface (SCI, IrDA)

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Bit Bit Name Initial Value R/W Description

4O/E0 R/W Parity Mode (enabled only when the PE bit is 1 in

asynchronous mode)

0: Selects even parity

1: Selects odd parity

For details on setting this bit in Smart Card

interface mode, refer to section 15.7.2, Data

Format (Except for Block Transfer Mode).

2BCP1

BCP0 0

0R/W

R/W Basic Clock Pulse 1 and 0

These bits select the number of basic clock

periods in a 1-bit transfer interval on the Smart

Card interface.

00: 32 clock (S = 32)

01: 64 clock (S = 64)

10: 372 clock (S = 372)

11: 256 clock (S = 256)

For details, refer to section 15.7.4, Receive Data

Sampling Timing and Reception Margin. S stands

for the value of S in BRR (see section 15.3.9, Bit

Rate Register (BRR)).

0CKS1

CKS0 0

0R/W

R/W Clock Select 1 and 0

These bits select the clock source for the on-chip

baud rate generator.

00: φ clock (n = 0)

01: φ/4 clock (n = 1)

10: φ/16 clock (n = 2)

11: φ/64 clock (n = 3)

For the relation between the bit rate register

setting and the baud rate, see section 15.3.9, Bit

Rate Register (BRR). n is the decimal display of

the value of n in BRR (see section 15.3.9, Bit Rate

Section 15 Seri al Communication Interface (SCI, IrDA)

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15.3.6 Serial Control Register (SCR)

SCR performs enabling or disabling of SCI transfer operations and interrupt requests, and

selection of the transfer/receive clock source. For details on interrupt requests, refer to section

15.9, Interrupts Sources. Some bit functions of SCR differ in normal serial communication

interface mode and Smart Card interface mode.

Normal Serial Communication Interface Mode (When SMIF in SCMR is 0)

Bit Bit Name Initial Value R/W Description

7 TIE 0 R/W Transmit Interr upt Enab le

When this bit is set to 1, TXI interrupt request is

enabled.

6 RIE 0 R/W Receive Interrupt Enable

When this bit is set to 1, RXI and ERI interrupt

requests are enabled.

5TE 0 R/WTransmit Enable

When this bit s set to 1, transmission is enabled.

4 RE 0 R/W Receive Enable:

When this bit is set to 1, reception is enabled.

3 MPIE 0 R/W Multiprocessor Interrupt Enable (enabled only

when the MP bit in SMR is 1 in asynchronous

mode)

When this bit is set to 1, receiv e data in which the

multiprocessor bit is 0 is skipped, and setting of

the RDRF, FER, and ORER status flags in SSR is

prohibited. On receiving data in which the

multiproce ssor bit is 1, this bit is automatic all y

cleared and normal reception is resumed. For

details, refer to section 15.5, Multiprocessor

Communication Function.

2 TEIE 0 R/W Transmit End Interrupt Enable

When this bit is set to 1, TEI interrupt request is

enabled.

Section 15 Seri al Communication Interface (SCI, IrDA)

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Bit Bit Name Initial Value R/W Description

0CKE1

CKE0 0

0R/W

R/W Clock Enable 1 and 0

Selects the clock source and SCK pin functi on.

Asynchronous mode

00: On-chip baud rate generator

SCK pin functions as I/O port

01: On-chip baud rate generator

(Outputs a clock of the same frequency as the

bit rate from the SCK pin.)

1X: External clo ck

(Inputs a clock with a frequency 16 times the

bit rate from the SCK pin.)

Clocked sy nchr ono us mode

0X: Internal clock (SCK pin fun ction s as clock

output)

1X: Externa l clo ck (SCK pin fun ctio ns as clo ck

input)

X: Don’t care

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 672 of 926

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Smart Card Interf ace Mode (When SMIF in SCMR is 1)

Bit Bit Name Initial Value R/W Description

7 TIE 0 R/W Transmit Interr upt Enab le

When this bit is set to 1, TXI interrupt request is

enabled.

6 RIE 0 R/W Receive Interrupt Enable

When this bit is set to 1, RXI and ERI interrupt

requests are enabled.

5 TE 0 R/W Transmit Enable

When this bit is set to 1, transmission is enabled.

4 RE 0 R/W Receive Enable

When this bit is set to 1, reception is enabled.

3 MPIE 0 R/W Multiprocessor Interrupt Enable (enabled only

when the MP bit in SMR is 1 in asynchronous

mode)

Write 0 to this bit in Smart Card interface mode.

2 TEIE 0 R/W Transmit End Interrupt Enable

Write 0 to this bit in Smart Card interface mode.

0CKE1

CKE0 0

0R/W Clock Enable 1 and 0

Enables or disables clock output from the SCK

pin. The clock outp ut can be dynamically switched

in GSM mode. For details, refer to section 15.7.8,

Clock Output Control.

When the GM bit in SMR is 0:

00: Output disabled (SCK pin can be used as an

I/O port pin)

01: Clock output

1X: Reserved

When the GM bit in SMR is 1:

00: Output fixed low

01: Clock output

10: Output fixed high

11: Clock output

X: Don’t care

Section 15 Seri al Communication Interface (SCI, IrDA)

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15.3.7 Serial Status Register (SSR)

SSR is a register containing status flags of the SCI and multiprocessor b its for transfer. 1 cannot

be written to flag s TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Som e bit

functions of SSR differ in normal serial communication interface mode and Smart Card interface

mode.

Normal Serial Communication Interface Mode (When SMIF in SCMR is 0)

Bit Bit Name Initial Value R/W Description

7 TDRE 1 R/(W)*Transmit Data Register Empty

Indicates whether TDR contains transmit data.

[Setting conditions]

• When the TE bit in SCR is 0

• When data is transferred from TDR to TSR

[Clearing cond iti ons ]

• When 0 is written to TDRE after reading TDRE

= 1

• When the DMAC or DTC is activated by a TXI

interrupt request and transfers data to TDR

6 RDRF 0 R/(W)*Re ceive Data Register Full

Indicates that the received data is stored in RDR.

[Setting condition]

When serial reception ends normally and receive

data is transferred from RSR to RDR

[Clearing cond iti ons ]

• When 0 is written to RDRF after reading

RDRF = 1

• When the DMAC or DTC is activated by an

RXI interrupt and transferred data from RDR

The RDRF flag is not affected and retains their

previous values when the RE bit in SCR is cleared

to 0.

Section 15 Seri al Communication Interface (SCI, IrDA)

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Bit Bit Name Initial Value R/W Description

5 ORER 0 R/(W)*Overrun Error

[Setting condition]

When the next serial reception is completed while

RDRF = 1

[Clearing cond iti on]

When 0 is written to ORER after reading ORER =

4FER 0 R/(W)

*Framing Error

[Setting condition]

When the stop bit is 0

[Clearing cond iti on]

When 0 is written to FER after reading FER = 1

In 2-stop-bit mode, only the first stop bit is

checked.

3 PER 0 R/(W)*Parity Error

[Setting condition]

When a parity error is detected dur ing rec epti on

[Clearing cond iti on]

When 0 is written to PER after reading PER = 1

2 TEND 1 R Transmit End

[Setting conditions]

• When the TE bit in SCR is 0

• When TDRE = 1 at transmission of the last bit

of a 1-byte serial transmit character

[Clearing cond iti ons ]

• When 0 is written to TDRE after reading TDRE

= 1

• When the DMAC or DTC is activated by a TXI

interrupt and writes data to TDR

Section 15 Seri al Communication Interface (SCI, IrDA)

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Bit Bit Name Initial Value R/W Description

1 MPB 0 R Multiprocessor Bit

MPB stores the multiprocessor bit in the receive

data. When the RE bit in SCR is cleared to 0 its

previous state is retained.

0 MPBT 0 R/W Multiprocessor Bit Transfer

MPBT sets the multiprocessor bit to be added to

the transmit data.

Note: *Only 0 can be written, to clear the flag.

Smart Card Interf ace Mode (When SMIF in SCMR is 1)

Bit Bit Name Initial Value R/W Description

7 TDRE 1 R/(W)*Transmit Data Register Empty

Indicates whether TDR contains transmit data.

[Setting conditions]

• When the TE bit in SCR is 0

• When data is transferred from TDR to TSR

[Clearing cond iti ons ]

• When 0 is written to TDRE after reading TDRE

= 1

• When the DMAC or DTC is activated by a TXI

interrupt request and transfers data to TDR

6 RDRF 0 R/(W)*Re ceive Data Register Full

Indicates that the received data is stored in RDR.

[Setting condition]

When serial reception ends normally and receive

data is transferred from RSR to RDR

[Clearing cond iti ons ]

• When 0 is written to RDRF after reading

RDRF = 1

• When the DMAC or DTC is activated by an

RXI interrupt and transferred data from RDR

The RDRF flag is not affected and retains their

previous values when the RE bit in SCR is cleared

to 0.

Section 15 Seri al Communication Interface (SCI, IrDA)

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Bit Bit Name Initial Value R/W Description

5 ORER 0 R/(W)*Overrun Error

[Setting condition]

When the next serial reception is completed while

RDRF = 1

[Clearing cond iti on]

When 0 is written to ORER after reading ORER =

4ERS 0 R/(W)

*Error Signal Status

[Setting condition]

When the low level of the error signal is sampled

[Clearing cond iti on]

When 0 is written to ERS after reading ERS = 1

3 PER 0 R/(W)*Parity Error

[Setting condition]

When a parity error is detected dur ing rec epti on

[Clearing cond iti on]

When 0 is written to PER after reading PER = 1

Section 15 Seri al Communication Interface (SCI, IrDA)

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Bit Bit Name Initial Value R/W Description

2 TEND 1 R Transmit End

This bit is set to 1 when no error signal has been

sent back from the receiving end and the next

transmit data is ready to be transferred to TDR.

[Setting conditions]

• When the TE bit in SCR is 0 and the ERS bit

is also 0

• If the ERS bit is 0 and the TDRE bit is 1 after

the specified interval after transmission of 1-

byte data

Timing to set this bit differs according to the

GM = 0, BLK = 0: 2.5 etu after transmission

GM = 0, BLK = 1: 1.5 etu after transmission

GM = 1, BLK = 0: 1.0 etu after transmission

GM = 1, BLK = 1: 1.0 etu after transmission

[Clearing cond iti ons ]

• When 0 is written to TEND after read ing TEND

= 1

• When the DMAC or DTC is activated by a TXI

interrupt and writes data to TDR

1 MPB 0 R Multiprocessor Bit

This bit is not used in Smart Card interfac e mode.

0 MPBT 0 R/W Multiprocessor Bit Transfer

Write 0 to this bit in Smart Card interface mode.

Note: *Only 0 can be written, to clear the flag.

Section 15 Seri al Communication Interface (SCI, IrDA)

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15.3.8 Sma rt Ca rd Mode Register (SCMR)

SCMR selects Smart Card interface mode and its format.

Bit Bit Name Initial Value R/W Description

— All 1 — Reserved

These bits are always read as 1.

3 SDIR 0 R/W Smart Card Data Transfer Direction

Selects the serial/parallel conversi on format .

0: LSB-first in transfer

1: MSB-first in transfer

The bit setting is valid only when the transfer data

format is 8 bits. For 7-bit data, LSB-first is fixed.

2 SINV 0 R/W Smart Card Data Invert

Specifies inversion of the data logic level. The

SINV bit does not affect the logic level of the

parity bit. To invert the parity bit, invert the O/E bit

in SMR.

0: TDR contents are transmitted as they are.

Receive data is stored as it is in RDR.

1: TDR contents are inverted before being

transmitted. Receive data is stored in inverted

form in RDR.

1— 1 — Reserved

This bit is always read as 1.

0 SMIF 0 R/W Smart Card Interface Mode Select

This bit is set to 1 to make the SCI operate in

Smart Card interface mode.

0: Normal asynchronous mode or clocked

synchronous mode

1: Smart card interface mode

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 679 of 926

REJ09B0283-0300

15.3.9 Bit Rate Regist er (BRR)

BRR is an 8-bit register that adjusts the bit ra te. As the SCI perform s b aud r a te gen erator control

independently for each ch annel, different bit rates can be set for each channel. Table 15.2 shows

the rela tionships between the N setting in BRR and bit rate B for nor mal asyn c hronous mode,

clocked syn chronou s mode, and Smart Card in terface mode. The initial value o f BRR i s H'FF, and

it can be read or written to by the CPU at all times.

Table 15.2 Relationships between N Sett ing in BRR and Bit Rate B

Mode Bit Rate Error

Asynchronous

Mode

B =

64 × 2

–

× (N + 1)

φ × 10

B × 64 × 2

–

× (N + 1)

φ × 10

Error (%) =

{}

– 1 × 100

Clocked

Synchronous

Mode

B =

Smart Card

Interface Mode

B =

Error (%) =

B × S × 2

× (N + 1)

φ × 10

{}

– 1 × 100

8 × 2

–

× (N + 1)

φ × 10

S × 2

× (N + 1)

φ × 10

Note: B: Bit rate (bit/s)

N: BRR setting for baud rate generator (0 ≤ N ≤ 255)

φ: Operating frequency (MHz)

n and S: Determined by the SMR settings shown in the foll owing tables.

SMR Setting SMR Setting

CKS1 CKS0 n BCP1 BCP0 S

000 0032

011 0164

102 10372

113 11256

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 680 of 926

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Table 15.3 shows sample N settings in BRR in normal asynchronous mode. Table 15.4 shows the

maximum bit rate for each frequency in normal asynchronous mode. Table 15.6 shows sample N

settings in BRR in c l ocked synchronous mode. Table 15.8 sh ows sample N settings in BRR in

Smart Card interface mode. In Smart Card interface mode, S (the number of basic clock periods in

a 1-bit transfer interval) can be selected. For details, refer to section 15.7.4, Receive Data

Sampling Timing and Reception Margin. Tables 15.5 and 15.7 show the maximum bit rates with

external clock input.

Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1)

Operating Frequency φ

φφ

φ (MHz)

2 2.097152 2.4576 3

Bit Rate

(bit/s) n N Error

(%) nN Error

(%)

110 1 141 0.03 1 148 –0.04 1 174 –0.26 1 212 0.03

150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16

300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16

600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16

1200 0 51 0.16 0 54 –0.70 0 63 0.00 0 77 0.16

2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16

4800 0 12 0.16 0 13 –2.48 0 15 0.00 0 19 –2.34

9600 —— — 06 –2.48 0 7 0.00 0 9 –2.34

19200 —— — —— — 0 3 0.00 0 4 –2.34

31250 0 1 0.00 —— — —— — 0 2 0.00

38400 —— — —— — 0 1 0.00 —— —

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 681 of 926

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Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2)

Operating Frequency φ

φφ

φ (MHz)

3.6864 4 4.9152 5

Bit Rate

(bit/s) n N Error

(%) n N Error

(%)

110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 –0.25

150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16

300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16

600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16

1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16

2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16

4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 –1.36

9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73

19200 0 5 0.00 —— — 0 7 0.00 0 7 1.73

31250 —— — 0 3 0.00 0 4 –1.70 0 4 0.00

38400 0 2 0.00 —— — 0 3 0.00 0 3 1.73

Operating Frequency φ

φφ

φ (MHz)

6 6.144 7.3728 8

Bit Rate

(bit/s) n N Error

(%) nN Error

(%)

110 2 106 –0.44 2 108 0.08 2 130 –0.07 2 141 0.03

150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16

300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16

600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16

1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16

2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16

4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16

9600 0 19 –2.34 0 19 0.00 0 23 0.00 0 25 0.16

19200 0 9 –2.34 0 9 0.00 0 11 0.00 0 12 0.16

31250 0 5 0.00 0 5 2.40 —— — 0 7 0.00

38400 0 4 –2.34 0 4 0.00 0 5 0.00 —— —

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 682 of 926

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Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (3)

Operating Frequency φ

φφ

φ (MHz)

9.8304 10 12 12.288

Bit Rate

(bit/s) n N Error

(%) n N Error

(%)

110 2 174 –0.26 2 177 –0.25 2 212 0.03 2 217 0.08

150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00

300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00

600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00

1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00

2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00

4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00

9600 0 31 0.00 0 32 –1.36 0 38 0.16 0 39 0.00

19200 0 15 0.00 0 15 1.73 0 19 –2.34 0 19 0.00

31250 0 9 –1.70 0 9 0.00 0 11 0.00 0 11 2.40

38400 0 7 0.00 0 7 1.73 0 9 –2.34 0 9 0.00

Operating Frequency φ

φφ

φ (MHz)

14 14.7456 16 17.2032

Bit Rate

(bit/s) n N Error

(%) nN Error

(%)

110 2 248 –0.17 3 64 0.70 3 70 0.03 3 75 0.48

150 2 181 0.16 2 191 0.00 2 207 0.16 2 223 0.00

300 2 90 0.16 2 95 0.00 2 103 0.16 2 111 0.00

600 1 181 0.16 1 191 0.00 1 207 0.16 1 223 0.00

1200 1 90 0.16 1 95 0.00 1 103 0.16 1 111 0.00

2400 0 181 0.16 0 191 0.00 0 207 0.16 0 223 0.00

4800 0 90 0.16 0 95 0.00 0 103 0.16 0 111 0.00

9600 0 45 –0.93 0 47 0.00 0 51 0.16 0 55 0.00

19200 0 22 –0.93 0 23 0.00 0 25 0.16 0 27 0.00

31250 0 13 0.00 0 14 –1.70 0 15 0.00 0 16 1.20

38400 —— — 0110.00 0120.16 0130.00

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 683 of 926

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Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (4)

Operating Frequency φ

φφ

φ (MHz)

18 19.6608 20 25

Bit Rate

(bit/s) n N Error

(%) n N Error

(%)

110 3 79 –0.12 3 86 0.31 3 88 –0.25 3 110 –0.02

150 2 233 0.16 2 255 0.00 3 64 0.16 3 80 –0.47

300 2 116 0.16 2 127 0.00 2 129 0.16 2 162 0.15

600 1 233 0.16 1 255 0.00 2 64 0.16 2 80 –0.47

1200 1 116 0.16 1 127 0.00 1 129 0.16 1 162 0.15

2400 0 233 0.16 0 255 0.00 1 64 0.16 1 80 –0.47

4800 0 116 0.16 0 127 0.00 0 129 0.16 0 162 0.15

9600 0 58 –0.69 0 63 0.00 0 64 0.16 0 80 –0.47

19200 0 28 1.02 0 31 0.00 0 32 –1.36 0 40 –0.76

31250 0 17 0.00 0 19 –1.70 0 19 0.00 0 24 0.00

38400 0 14 –2.34 0 15 0.00 0 15 1.73 0 19 1.73

Operating Frequency φ

φφ

φ (MHz)

30 33

Bit Rate

(bit/s) n N Error

(%) nN Error

(%)

110 3 132 0.13 3 145 0.33

150 3 97 –0.35 3 106 0.39

300 2 194 0.16 2 214 –0.07

600 2 97 –0.35 2 106 0.39

1200 1 194 0.16 1 214 –0.07

2400 1 97 –0.35 1 106 0.39

4800 0 194 0.16 0 214 –0.07

9600 0 97 –0.35 0 106 0.39

19200 0 48 –0.35 0 53 –0.54

31250 0 29 0 0 32 0

38400 0 23 1.73 0 26 –0.54

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 684 of 926

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Table 15.4 Maximum Bit Rat e for Each Frequency (Asynchronous Mode)

φφ

φ (MHz) Maximum Bit

Rate (bit/s) nN φ

φφ

φ (MHz) Maximum Bit

Rate (bit/s) nN

2 62500 0 0 10 312500 0 0

2.097152 65536 0 0 12 375000 0 0

2.4576 76800 0 0 12.288 384000 0 0

3 93750 0 0 14 437500 0 0

3.6864 115200 0 0 14.7456 460800 0 0

4 125000 0 0 16 500000 0 0

4.9152 153600 0 0 17.2032 537600 0 0

5 156250 0 0 18 562500 0 0

6 187500 0 0 19.6608 614400 0 0

6.144 192000 0 0 20 625000 0 0

7.3728 230400 0 0 25 781250 0 0

8 250000 0 0 30 937500 0 0

9.8304 307200 0 0 33 1031250 0 0

Table 15.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode)

φφ

φ (MHz) External Input

Clock (MHz) Maximum Bit

Rate (bit/s) φ

φφ

φ (MHz) External Input

Clock (MHz) Maximum Bit

Rate (bit/s)

2 0.5000 31250 10 2.5000 156250

2.097152 0.5243 32768 12 3.0000 187500

2.4576 0.6144 38400 12.288 3.0720 192000

3 0.7500 46875 14 3.5000 218750

3.6864 0.9216 57600 14.7456 3.6864 230400

4 1.0000 62500 16 4.0000 250000

4.9152 1.2288 76800 17.2032 4.3008 268800

5 1.2500 78125 18 4.5000 281250

6 1.5000 93750 19.6608 4.9152 307200

6.144 1.5360 96000 20 5.0000 312500

7.3728 1.8432 115200 25 6.2500 390625

8 2.0000 125000 30 7.5000 468750

9.8304 2.4576 153600 33 8.2500 515625

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 685 of 926

REJ09B0283-0300

Table 15.6 BRR Setting s f or Various Bit Ra tes (Clocked Synchronous Mode)

Operating Frequency φ

φφ

φ (MHz)

24810162025

Bit

Rate

(bit/s)nNnN nNnNn Nn Nn N

110 3 70 ——

250 2 124 2 249 3 124 ——3 249

500 1 249 2 124 2 249 ——3 124 ——

1 k 1 124 1 249 2 124 ——2 249 ——397

2.5 k 0 199 1 99 1 199 1 249 2 99 2 124 2 155

5 k 0 99 0 199 1 99 1 124 1 199 1 249 2 77

10 k 0 49 0 99 0 199 0 249 1 99 1 124 1 155

25 k 0 19 0 39 0 79 0 99 0 159 0 199 0 249

50 k 0 9 0 19 0 39 0 49 0 79 0 99 0 124

100 k 0 4 0 9 0 19 0 24 0 39 0 49 0 62

250 k 0 1 0 3 0 709015019024

500 k 0 0*01 03040709——

1 M 0 0*01 0 3 0 4——

2.5 M 0 0*01——

5 M 0 0*——

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 686 of 926

REJ09B0283-0300

Operating Frequency φ

φφ

(MHz)

30 33

Bit

Rate

(bit/s) n N n N

110

250

500 3 233

1 k 3 116 3 128

2.5 k 2 187 2 205

5 k 2 93 2 102

10 k 1 187 1 205

25 k 1 74 1 82

50 k 0 149 0 164

100 k 0 74 0 82

250 k 0 29 0 32

500 k 0 14 ——

1 M —— ——

2.5 M 0 2 ——

5 M —— ——

Legend:

Blank: Cannot be set.

—: Can be set, but there will be a degree of error.

*: Continuous transfer is not possible.

Table 15.7 Maximum Bit Rat e with External Clo c k Input (Clocked Synchronou s Mode)

φφ

φ (MHz) External Input

Clock (MHz) Maximum Bit

Rate (bit/s) φ

φφ

φ (MHz) External Input

Clock (MHz) Maximum Bit

Rate (bit/s)

2 0.3333 333333.3 16 2.6667 2666666.7

4 0.6667 666666.7 18 3.0000 3000000.0

6 1.0000 1000000.0 20 3.3333 3333333.3

8 1.3333 1333333.3 25 4.1667 4166666.7

10 1.6667 1666666.7 30 5.0000 5000000.0

12 2.0000 2000000.0 33 5.5000 5500000.0

14 2.3333 2333333.3

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 687 of 926

REJ09B0283-0300

Table 15.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode)

(when n = 0 and S = 372)

Operating Frequency φ

φφ

φ (MHz)

7.1424 10.00 10.7136 13.00

Bit Rate

(bit/s) nNError

(%) n N Error

(%)

9600 1 1 0.00 0 1 30 0 1 25 0 1 8.99

Operating Frequency φ

φφ

φ (MHz)

14.2848 16.00 18.00 20.00

Bit Rate

(bit/s) nNError

(%) n N Error

(%)

9600 0 1 0.00 0 1 12.01 0 2 15.99 0 2 6.60

Operating Frequency φ

φφ

φ (MHz)

25.00 30.00 33.00

Bit Rate

(bit/s) nNError

(%) n N Error

(%)

9600 0 3 12.49 0 3 5.01 0 4 7.59

Table 15.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)

(when S = 372)

φφ

φ (MHz) Maximum Bit

Rate (bit/s) n N φ

φφ

φ (MHz) Maximum Bit

Rate (bit/s) n N

7.1424 9600 0 0 18.00 24194 0 0

10.00 13441 0 0 20.00 26882 0 0

10.7136 14400 0 0 25.00 33602 0 0

13.00 17473 0 0 30.00 40323 0 0

14.2848 19200 0 0 33.00 44355 0 0

16.00 21505 0 0

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 688 of 926

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15.3.10 IrDA Control Register (IrCR)

IrCR selects the function of SCI_0.

Bit Bit Name Initial Value R/W Description

7 IrE 0 R/W IrDA Enable

Specifies normal SCI mode or IrDA mode for

SCI_0 input/output.

0: Pins TxD0/IrTx D and RxD0/IrRxD function as

TxD0 and RxD0

1: Pins TxD0/IrTx D and RxD0/IrRxD function as

IrTxD and IrRxD

IrCKS2

IrCKS1

IrCKS0

R/W

IrDA Clock Select 2 to 0

Specifies the high pulse width in IrTxD output

pulse encoding when the IrDA function is enabled.

000: Pulse width = B × 3/16 (3/16 of bit rate)

001: Pulse width = φ/2

010: Pulse width = φ/4

011: Pulse width = φ/8

100: Pulse width = φ/16

101: Pulse width = φ/32

110: Pulse width = φ/64

111: Pulse width = φ/128

—All 0 —Reserved

These bits are always read as 0 and cannot be

modified.

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 689 of 926

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15.3.11 Serial Extension Mode Register (SEMR)

SEMR selects the clock source in asynchronous mode. The basic clock can be automatically set by

selecting the average transfer rate. SEMR is supported only in SCI_2 of the H8S/2678R Group.

Bit Bit Name Initial Value R/W Description

—Undefined —Reserved

If these bits are read, an undefined value will be

returned and cannot be modified.

3 AB C S 0 R/W Asynchronou s basic clock selection ( va lid onl y in

asynchronous mode)

Selects the basic clock for 1-bit period in

asynchronous mode.

0: Operates on a basic clock with a frequency of

16 times the transfer rate.

1: Operates on a basic clock with a frequency of

8 times the transfer rate.

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 690 of 926

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Bit Bit Name Initial Value R/W Description

ACS2

ACS1

ACS0

R/W

Asynchronous clock source selection (valid when

CKS1 = 1 in asynchronous mode)

Selects the clock source for the average transfer

rate.

The basic clock can be automatically set by

selecting the average transfer rate in spite of the

value of ABCS.

000: External clo ck inp ut

001: Selects 115. 152 kbp s wh ich is the aver age

transfer rate dedicated for φ = 10.667 MHz.

(Operates on a basic clock with a frequency

of 16 times the transfer rate.)

010: Selects 460. 606 kbp s wh ich is the aver age

transfer rate dedicated for φ = 10.667 MHz.

(Operates on a basic clock with a frequency

of 8 times the transfer rate.)

011: Selects 720 kbp s which is the aver age

transfer rate dedicated for φ = 32 MHz.

(Operates on a basic clock with a frequency

of 16 times the transfer rate.)

100: Reserved

101: Selects 115. 196 kbp s wh ich is the aver age

transfer rate dedicated for φ = 16 MHz

(Operates on a basic clock with a frequency

of 16 times the transfer rate.)

110: Selects 460. 784 kbp s wh ich is the aver age

transfer rate dedicated for φ = 16 MHz

(Operates on a basic clock with a frequency

of 16 times the transfer rate.)

111: Selects 720 kbp s which is the aver age

transfer rate dedicated for φ = 16 MHz

(Operates on a basic clock with a frequency

of 8 times the transfer rate.)

Note that the average transfer rate does not

correspond to the frequen cy other tha n 10. 667,

16, or 32 MHz.

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 691 of 926

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15.4 Operation in Asynchronous Mode

Figure 15.2 shows the general format for asynchronous serial communication. One frame consists

of a start bit (lo w level), followed by transfer data, a par ity bit, and finally stop bits (high level). In

asynchronous serial communication, the transmission line is usually held in the mark state (high

level). The SCI monitors the transmission line, and when it goes to the space state (low level),

recognizes a start bit and starts serial communication. In asynchronous serial communication, the

commun ication line is usually held in the mark state (high level). The SCI m onitors the

communication line, and when it goes to the space state (low level), recognizes a start bit and

starts serial communication. Inside the SCI, the transmitter and receiver are independent units,

enabling full-duplex communication. Both the transmitter and the receiver also have a double-

buffered structure, so that data can be read or written during transmission o r reception, enabling

continuous data transfer.

LSB

Start

bit

MSB

Idle state

(mark state)

Stop bit(s)

Transmit/receive data

D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1

1 1

Serial

data Parity

bit

1 bit 1 or

2 bits

7 or 8 bits 1 bit,

or none

One unit of transfer data (character or frame)

Figure 15.2 Data Format in Asynchronous Communication

(Example with 8-Bit Data, Parity, Two Stop Bits)

15.4.1 Data Transfer Format

Table 15.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12

transfer formats can be selected accordin g to the SMR setting. For details o n the multiprocessor

bit, refer to section 15.5, Multiprocessor Comm unication Functio n.

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 692 of 926

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Table 15.10 Serial Transfer Formats (Asynchronous Mode)

—

S8-bit data

STOP

S7-bit data

STOP

S8-bit data

STOP STOP

S8-bit data P

STOP

S7-bit data

STOP

S8-bit data

MPB STOP

S8-bit data

MPB STOP STOP

S7-bit data

STOPMPB

S7-bit data

STOPMPB STOP

S7-bit data

STOPSTOP

CHR

STOP

SMR Settings

123456789101112

Serial Transfer Format and Frame Length

STOP

S8-bit data P

STOP

S7-bit data

STOP

Legend:

S : Start bit

STOP : Stop bit

P: Parity bit

MPB : Multi processor bit

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 693 of 926

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15.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode

In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate.

In reception, the SCI samples the falling edge of the start bit using the basic clo ck, and performs

internal synchronization. Receive data is latched at the middle of each bit by sampling the data at

the rising edge of the 8th pulse of the basic clock as shown in figure 15.3. Thus the reception

margin in asynchronous mode is given by formula (1) below.

M = (0.5 – ) – (L – 0.5) F – (1 + F) × 100 [%]

2N D – 0.5

{}

... Formula (1)

Where M: Reception Margin

N: Ratio of bit rate to clock (N = 16)

D: Clock duty cycle (D = 0.5 to 1.0)

L: Frame length (L = 9 to 12)

F: Absolute value of clock rate deviation

Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin is given by formula

below.

M = {0.5 – 1/(2 × 16)} × 100 [%] = 46.875%

However, this is only the computed value, and a margin of 20% to 30% should be allowed in

system design.

Internal base

clock

16 clocks

8 clocks

Receive data

(RxD)

Synchronization

sampling timing

Start bit D0 D1

Data sampling

timing

15 0 7 15 007

Figure 15.3 Receive Data Sampling Timing in Asynchronous Mode

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 694 of 926

REJ09B0283-0300

15.4.3 Clock

Either an internal clock generated by the on-chip baud rate generator or an external clock input at

the SCK pin can be selected as the SCI’s serial clock, according to the setting o f the C/A bit in

SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input at the SCK pin, the

clock frequency should be 16 times the bit rate used.

When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The

frequen cy of the clock output in this case is equ al to the bit rate, and the phase is such th at the

rising edge of th e clo ck is in th e middle of the transmit data, as sh o w n in f igure 15.4.

1 frame

SCK

TxD D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1

Figure 15.4 Relation between Output Clock and Transfer Data Phase

(Asynchrono us Mo de)

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 695 of 926

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15.4.4 SCI Initialization (Asynchronous Mode)

Before transmitting an d receivin g data, you should first clear the TE and RE bits in SCR to 0, th en

initialize the SCI as sho wn in figure 15.5. When the operating mode , transf er format, etc., is

changed, the TE and RE bits must be cleared to 0 before making the change. When the TE bit is

cleared to 0, the TDRE flag is set to 1. Note that clearing th e RE bit to 0 does not initialize the

contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. When the external

clock is used in asynchronous mode, the clo ck must be supplied even during initializatio n.

Wait

Start of initialization

Set data transfer format in

SMR and SCMR

[1]

Set CKE1 and CKE0 bits in SCR

(TE, RE bits 0)

Yes

Set value in BRR

Clear TE and RE bits in SCR to 0

[2]

[3]

Set TE and RE bits in

SCR to 1, and set RIE, TIE, TEIE,

and MPIE bits [4]

1-bit interval elapsed?

[1] Set the clock selection in SCR.

Be sure to clear bits RIE, TIE,

TEIE, and MPIE, and bits TE and

RE, to 0.

When the clock is selected in

asynchronous mode, it is output

immediately after SCR settings are

made.

[2] Set the data transfer format in SMR

and SCMR.

[3] Write a value corresponding to the

bit rate to BRR. (Not necessary if

an external clock is used.)

[4] Wait at least one bit interval, then

set the TE bit or RE bit in SCR to 1.

Also set the RIE, TIE, TEIE, and

MPIE bits.

Setting the TE and RE bits enables

the TxD and RxD pins to be used.

Figure 15.5 Sample SCI Initialization Flowchart

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 696 of 926

REJ09B0283-0300

15.4.5 Data Transmission (Asynchronous Mode)

Figure 15.6 shows an ex ample of the operation for transmission in asynchronous mode. In

transmission, the SCI operates as described below.

1. The SCI monitors the TDRE flag in SSR, and if is cleared to 0, recognizes that data has been

written to TDR, and transfers the data from TDR to TSR.

2. After tran sferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts

transmission . If the TIE bit is set to 1 at this time, a transmit d a ta empty interrupt request (TXI)

is generated. Because the TXI interrupt routine writes the next transmit data to TDR before

transmission of the current transmit data has finished, continuous transmission can be enabled.

3. Data is sent fro m the TxD pin in the follo wing order: start bit, transm it data, parity bit or

multiprocessor bit (m ay b e omitted depending on the for mat), and stop bit.

4. The SCI checks the TDRE flag at the timing for sending the stop bit.

5. If the TDRE f lag is 0, the data is transferred from TDR to TSR, the stop bit is sen t, and then

serial transmission of the next frame is started.

6. If the TDRE f lag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the “mark

state” is entered in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI

interrupt request is generated.

Figure 15.7 shows a sample flowchart for transmission in asynchronous mode.

TDRE

TEND

1 frame

D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 1

1 1

DataStart

bit Parity

bit Stop

bit Start

bit Data Parity

bit Stop

bit

TXI interrupt

request generated Data written to TDR and

TDRE flag cleared to 0 in

TXI interrupt handling routine TEI interrupt

request generated

Idle state

(mark state)

TXI interrupt

request generated

Figure 15.6 Example of Operation in Transmission in Asynchronous Mode

(Example with 8-Bit Data, Parity, One Stop Bit)

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 697 of 926

REJ09B0283-0300

<End>

[1]

Yes

Initialization

Start of transmission

Read TDRE flag in SSR [2]

Write transmit data to TDR

and clear TDRE flag in SSR to 0

Yes

Read TEND flag in SSR

[3]

Yes

[4]

Clear DR to 0 and

set DDR to 1

Clear TE bit in SCR to 0

TDRE = 1?

All data transmitted?

TEND = 1?

Break output?

[1] SCI initialization:

The TxD pin is automatically

designated as the transmit data

output pin.

After the TE bit is set to 1, a frame

of 1s is output, and transmission is

enabled.

[2] SCI status check and transmit data

write:

Read SSR and check that the

TDRE flag is set to 1, then write

transmit data to TDR and clear the

TDRE flag to 0.

[3] Serial transmission continuation

procedure:

To continue serial transmission,

read 1 from the TDRE flag to

confirm that writing is possible,

then write data to TDR, and then

clear the TDRE flag to 0. Checking

and clearing of the TDRE flag is

automatic when the DMAC or DTC

is activated by a transmit-data-

empty interrupt (TXI) request, and

data is written to TDR.

[4] Break output at the end of serial

transmission:

To output a break in serial

transmission, set DDR for the port

corresponding to the TxD pin to 1,

clear DR to 0, then clear the TE bit

in SCR to 0.

Figure 15.7 Sample Serial Transmission Flowchart

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 698 of 926

REJ09B0283-0300

15.4.6 Serial Data Reception (Asynchronous Mode)

Figure 15.8 shows an example of the operation for reception in asynchronous mode. In serial

reception, the SCI operates as described below.

1. The SCI monitors the commu n ication lin e, and if a start bit is detected, performs inter nal

synchronization, receives receive data in RSR, and checks the parity bit and stop bit.

2. If an overrun error (when reception of the next data is completed while the RDRF flag is still

set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time,

an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag

remains to be set to 1.

3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to

RDR. If the RIE b it in SCR is set to 1 at th is time, an ERI interr upt request is generated.

4. If a framing error (when the stop bit is 0) is detected, the FER bit in SSR is set to 1 and receive

data is transfer red to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt

request is generated.

5. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is

transferre d to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrup t request is

generated. Because the RXI interrupt routine reads the receive data transferred to RDR before

reception of the next receive data has finished, continuous reception can be enabled.

RDRF

FER

1 frame

D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 0

1 1

DataStart

bit Parity

bit Stop

bit Start

bit Data Parity

bit Stop

bit

RXI interrupt

request

generated ERI interrupt request

generated by framing

error

Idle state

(mark state)

RDR data read and RDRF

flag cleared to 0 in RXI

interrupt handling routine

Figure 15.8 Example of SCI Operation in Reception

(Example with 8-Bit Data, Parity, One Stop Bit)

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 699 of 926

REJ09B0283-0300

Table 15.11 shows the states of the SSR status flags and receive data handling when a receive

error is detected. If a receive error is detected, the RDRF flag retains its state before receiving

data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the

ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 15.9 shows a sample

flowchart for serial data reception.

Table 15.11 SSR Status Flags and Receive Data Handling

SSR Status Flag

RDRF*ORER FER PER Receive Data Receive Error Type

1 1 0 0 Lost Overrun error

0 0 1 0 Transferred to RDR Framing error

0 0 0 1 Transferred to RDR Parity error

1 1 1 0 Lost Overrun error + framing error

1 1 0 1 Lost Overrun error + parity error

0 0 1 1 Transferred to RDR Framing error + parity error

1 1 1 1 Lost Overrun error + framing error +

parity error

Note: *The RDRF flag retains its state before data reception.

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 700 of 926

REJ09B0283-0300

Yes

<End>

[1]

Initialization

Start of reception

[2]

Yes

Read RDRF flag in SSR [4]

[5]

Clear RE bit in SCR to 0

Read ORER, PER, and

FER flags in SSR

Error handling

(Continued on next page)

[3]

Read receive data in RDR, and

clear RDRF flag in SSR to 0

Yes

PER ∨ FER ∨ ORER = 1?

RDRF = 1?

All data received?

SCI initialization:

The RxD pin is automatically

designated as the receive data

input pin.

Receive error handling and

break detection:

If a receive error occurs, read the

ORER, PER, and FER flags in

SSR to identify the error. After

performing the appropriate error

processing, ensure that the

ORER, PER, and FER flags are

all cleared to 0. Reception cannot

be resumed if any of these flags

are set to 1. In the case of a

framing error, a break can be

detected by reading the value of

the input port corresponding to

the RxD pin.

SCI status check and receive

data read :

Read SSR and check that RDRF

= 1, then read the receive data in

RDR and clear the RDRF flag to

0. Transition of the RDRF flag

from 0 to 1 can also be identified

by an RXI interrupt.

Serial reception continuation

procedure:

To continue serial reception,

before the stop bit for the current

frame is received, read the

RDRF flag, read RDR, and clear

the RDRF flag to 0. The RDRF

flag is cleared automatically

when the DMAC or DTC is

activated by an RXI interrupt and

the RDR value is read.

[1]

[2] [3]

[4]

[5]

Figure 15.9 Sample Serial Reception Data Flowchart (1)

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 701 of 926

REJ09B0283-0300

<End>

[3]

Error handling

Parity error handling

Yes

Clear ORER, PER, and

FER flags in SSR to 0

Yes

Framing error handling

Yes

Overrun error handling

ORER = 1?

FER = 1?

Break?

PER = 1?

Clear RE bit in SCR to 0

Figure 15.9 Sample Serial Reception Data Flowchart (2)

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 702 of 926

REJ09B0283-0300

15.5 Multiprocessor Communication Function

Use of the mu ltiprocessor communication function enables data transfer to be perfor m e d among a

number of processors sharing communication lines by means of asynchronous serial

communication using the multip rocessor format, in which a multiprocessor bit is added to the

transfer data. When multipro cessor communication is carried out, each receiving station is

addressed by a unique ID code. The serial communication cycle consists of two component cycles:

an ID transmission cycle which specifies the receiving station, and a data transmission cycle to the

specified receiving statio n. The multiprocessor bit is used to differentiate between the ID

transmission cycle and the data transmission cycle. If the multiprocessor bit is 1 , the cycle is an ID

transmission cycle, and if the multip rocessor bit is 0, th e cycle is a da ta tr ansmission cycle. Figure

15.10 sho ws an example of inter-processor communication using the multiprocessor format. The

transmitting station first sends commun ication data with a 1 multiprocessor bit added to th e ID

code of the receiving station. It then sends transmit data as data with a 0 multiprocessor b it added.

When data with a 1 multip rocessor bit is received, the receiving statio n compares that data with its

own ID. The station whose ID matches then receives the data sent next. Stations whose ID does

not match continue to skip data until data with a 1 multipro cesso r bit is again received.

The SCI uses the MPIE bit in SCR to implement this function. When the MPI E bit is set to 1,

transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags,

RDRF, FER, and ORER to 1 are inhibited until data with a 1 multiprocessor bit is receiv ed. On

reception of receive character with a 1 multip rocesso r b it, the MPBR bit in SSR is set to 1 and the

MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to

1 at this time, an RXI interrupt is gener a ted.

When the multiprocessor format is selected, the p arity bit setting is inv alid. All other bit setting s

are the same as those in nor m al asynchronous mode. The clock used for multip rocesso r

communication is the same as that in normal asynchronous mode.

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 703 of 926

REJ09B0283-0300

Transmitting

station

Receiving

station A

(ID = 01)

Receiving

station B

(ID = 02)

Receiving

station C

(ID = 03)

Receiving

station D

(ID = 04)

Serial communication line

Serial

data

ID transmission cycle =

receiving station

specification

Data transmission cycle =

data transmission to

receiving station specified by ID

(MPB= 1) (MPB= 0)

H'01 H'AA

Legend:

MPB: Multiprocessor bit

Figure 15.10 Example of Communication Using Multiprocessor Format

(Transmission of Data H'AA to Receiving Statio n A)

15.5.1 Multiprocessor Serial Data Transmission

Figure 15.11 shows a sample flowchart for multipr ocessor serial data tr ansmission. For an ID

transmission cycle, set the MPBT bit in SSR to 1 befo r e transmission. For a data transmissio n

cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same

as those in asynchronous mode.

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 704 of 926

REJ09B0283-0300

<End>

[1]

Yes

Initialization

Start of transmission

Read TDRE flag in SSR [2]

Write transmit data to TDR and

set MPBT bit in SSR

Yes

Read TEND flag in SSR

[3]

Yes

[4]

Clear DR to 0 and set DDR to 1

Clear TE bit in SCR to 0

TDRE = 1?

All data transmitted?

TEND = 1?

Break output?

Clear TDRE flag to 0

SCI initialization:

The TxD pin is automatically

designated as the transmit data

output pin.

After the TE bit is set to 1,

a frame of 1s is output, and

transmission is enabled.

SCI status check and transmit

data write:

Read SSR and check that the

TDRE flag is set to 1, then write

transmit data to TDR. Set the

MPBT bit in SSR to 0 or 1.

Finally, clear the TDRE flag to 0.

Serial transmission continuation

procedure:

To continue serial transmission,

be sure to read 1 from the TDRE

flag to confirm that writing is

possible, then write data to TDR,

and then clear the TDRE flag to

0. Checking and clearing of the

TDRE flag is automatic when the

DMAC or DTC is activated by a

transmit-data-empty interrupt

(TXI) request, and data is written

to TDR.

Break output at the end of serial

transmission:

To output a break in serial

transmission, set the port DDR to

1, clear DR to 0, then clear the

TE bit in SCR to 0.

[1]

[2]

[3]

[4]

Figure 15.11 Sample Multiprocessor Serial Transmission Flowchart

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 705 of 926

REJ09B0283-0300

15.5.2 Multiprocessor Serial Data Reception

Figure 15.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in

SCR is set to 1, d a ta is skipped until data with a 1 multiprocessor bit is received. On receiving data

with a 1 multiprocessor b it, the receive data is transferred to RDR. An RXI interrupt request is

generated at this time. All other SCI operations are the same as in asynchronous mode. Figure

15.12 sho ws an example of SCI opera tion for multiprocessor format reception.

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 706 of 926

REJ09B0283-0300

MPIE

RDR

value

0D0 D1 D7 1 1 0 D0 D1 D7 0 1

1 1

Data (ID1)Start

bit MPB Stop

bit Start

bit Data (Data1) MPB Stop

bit

RXI interrupt

request

(multiprocessor

interrupt)

generated

MPIE = 0

Idle state

(mark state)

RDRF

RDR data read

and RDRF flag

cleared to 0 in

RXI interrupt

handling routine

If not this station’s ID,

MPIE bit is set to 1

again

RXI interrupt request is

not generated, and RDR

retains its state

ID1

(a) Data does not match station’s ID

MPIE

RDR

value

0D0 D1 D7 1 1 0 D0 D1 D7 0 1

1 1

Data (ID2)Start

bit

MPB Stop

bit Start

bit Data (Data2) MPB Stop

bit

RXI interrupt

request

(multiprocessor

interrupt)

generated

MPIE = 0

Idle state

(mark state)

RDRF

RDR data read and

RDRF flag cleared

to 0 in RXI interrupt

handling routine

Matches this station’s ID,

so reception continues, and

data is received in RXI

interrupt handling routine

MPIE bit set to 1

again

ID2

(b) Data matches station’s ID

Data2ID1

Figure 15.12 Example of SCI Operation in Reception

(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 707 of 926

REJ09B0283-0300

Yes

<End>

[1]

Initialization

Start of reception

Yes

[4]

Clear RE bit in SCR to 0

Error handling

(Continued on

next page)

[5]

Yes

FER ∨ ORER = 1?

RDRF = 1?

All data received?

Set MPIE bit in SCR to 1 [2]

Read ORER and FER flags in SSR

Read RDRF flag in SSR [3]

Read receive data in RDR

Yes

This station's ID?

Read ORER and FER flags in SSR

Yes

Read RDRF flag in SSR

Yes

FER ∨ ORER = 1?

Read receive data in RDR

RDRF = 1?

SCI initialization:

The RxD pin is automatically

designated as the receive data

input pin.

ID reception cycle:

Set the MPIE bit in SCR to 1.

SCI status check, ID reception

and comparison:

Read SSR and check that the

RDRF flag is set to 1, then read

the receive data in RDR and

compare it with this station’s ID.

If the data is not this station’s ID,

set the MPIE bit to 1 again, and

clear the RDRF flag to 0.

If the data is this station’s ID,

clear the RDRF flag to 0.

SCI status check and data

reception:

Read SSR and check that the

RDRF flag is set to 1, then read

the data in RDR.

Receive error handling and break

detection:

If a receive error occurs, read the

ORER and FER flags in SSR to

identify the error. After

performing the appropriate error

handling, ensure that the ORER

and FER flags are both cleared

to 0.

Reception cannot be resumed if

either of these flags is set to 1.

In the case of a framing error, a

break can be detected by reading

the RxD pin value.

[1]

[2]

[3]

[4]

[5]

Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (1)

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 708 of 926

REJ09B0283-0300

<End>

Error handling

Yes

Clear ORER, PER, and

FER flags in SSR to 0

Yes

Framing error handling

Overrun error handling

ORER = 1?

FER = 1?

Break?

Clear RE bit in SCR to 0

[5]

Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (2)

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 709 of 926

REJ09B0283-0300

15.6 Operation in Clocked Synchronous Mode

Figure 15.14 shows the general format for clocked synchronous communication. In clocked

synchro nou s mode, data is transmitted or received in synchronization with clock pulses. One

character of communication data consists of 8-bit data. In clocked synchronous serial

commun ication, data on the transmission lin e is output from one f a lling edge of the serial clock to

the next. In clocked synchronous mode, the SCI receives data in synchronization with the rising

edge of the serial clock. After 8-bit data is output, the transmission line ho lds the MSB state. In

clocked sy nchronous mode, no parity or multiprocesso r bit is added. Inside the SCI , the

transmitter and receiver are independent units, enabling full-duplex communication by use of a

common clock. Both the transmitter and the receiver also hav e a double-buffered structure, so that

data can be read or written dur in g transmission or r eception , enabling continuous data transfer.

Don’t

care

Don’t

care

One unit of transfer data (character or frame)

Bit 0

Serial

data

Serial

clock

Bit 1 Bit 3 Bit 4 Bit 5

LSB MSB

Bit 2 Bit 6 Bit 7

Note: * High except in continuous transfer

Figure 15.14 Data Format in Clocked Synchronous Communication (For LSB-First)

15.6.1 Clock

Either an internal clock generated by the on-chip baud rate generator or an external

synchronization clock input at the SCK pin can be selected, according to the setting of CKE1 and

CKE0 bits in SC R. When the SCI is op e r a ted on an internal clock, the serial clock is output from

the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no

transfer is performed the clock is fixed high.

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 710 of 926

REJ09B0283-0300

15.6.2 SCI Initia lization (Clo cked Synchronous Mode)

Before transmitting an d receivin g data, you should first clear the TE and RE bits in SCR to 0, th en

initialize the SCI as descr ib e d in a sample flowchart in figure 15.15. When the oper ating mode,

transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the

change. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to

0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR.

Wait

Start of initialization

Set data transfer format in

SMR and SCMR

Yes

Set value in BRR

Clear TE and RE bits in SCR to 0

[2]

[3]

Set TE and RE bits in SCR to 1, and

set RIE, TIE, TEIE, and MPIE bits

Note: In simultaneous transmit and receive operations, the TE and RE bits should

both be cleared to 0 or set to 1 simultaneously.

[4]

1-bit interval elapsed?

Set CKE1 and CKE0 bits in SCR

(TE, RE bits 0) [1]

[1] Set the clock selection in SCR. Be sure

to clear bits RIE, TIE, TEIE, and MPIE,

TE and RE, to 0.

[2] Set the data transfer format in SMR

and SCMR.

[3] Write a value corresponding to the bit

rate to BRR. (Not necessary if an

external clock is used.)

[4] Wait at least one bit interval, then set

the TE and RE bits in SCR to 1.

Also set the RIE, TIE, TEIE, and MPIE

bits.

Setting the TE and RE bits enable the

TxD and RxD pins to be used.

Figure 15.15 Sa mple SCI Initialization Flowchart

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 711 of 926

REJ09B0283-0300

15.6.3 Serial Data Transmission (Clocked Synchronous Mode)

Figure 15.16 shows an example of SCI operation for transmission in clocked synchronous mode.

In serial transmission, the SCI operates as described below.

1. The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to

TDR, and transf ers the data from TDR to TSR.

2. After tran sferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts

transmission . If the TIE bit in SCR is set to 1 at this time, a TXI inter r upt request is generated.

Because the TXI interrupt routine writes the next transmit data to TDR before transmission of

the current transmit data has finished, continuous transmission can be enabled.

3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock

mode has been specified and synchronized with the input clock when use of an external clock

has been specified.

4. The SCI checks the TDRE flag at the timing for sending the MSB.

5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission

of the next frame is started.

6. If the TDRE f lag is set to 1, the TEND flag in SSR is set to 1, and the TxD pin maintain s the

output state o f the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI in terrupt request

is generated. The SCK pin is fixed high.

Figure 15.17 shows a sample flowchart for serial data transmission. Even if the TDRE flag is

cleared to 0, transmission will n o t start while a receive error flag (ORER, FER, or PER) is set to 1.

Make sure to clear the receive error flags to 0 before starting transmission. Note that clearing the

RE bit to 0 does not clear the receive error flags.

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 712 of 926

REJ09B0283-0300

Transfer direction

Bit 0

Serial data

Serial clock

1 frame

TDRE

TEND

Bit 1 Bit 7 Bit 0 Bit 1 Bit 7Bit 6

Data written to TDR

and TDRE flag

cleared to 0 in TXI

interrupt handling routine

TEI interrupt

request generated

TXI interrupt

request generated

TXI interrupt

request generated

Figure 15.16 Sample SCI Transmission Operation in Clocked Synchronous Mode

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 713 of 926

REJ09B0283-0300

<End>

[1]

Yes

Initialization

Start of transmission

Read TDRE flag in SSR [2]

Write transmit data to TDR and

clear TDRE flag in SSR to 0

Yes

Read TEND flag in SSR

[3]

Clear TE bit in SCR to 0

TDRE = 1?

All data transmitted?

TEND = 1?

[1] SCI initialization:

The TxD pin is automatically

designated as the transmit data output

pin.

[2] SCI status check and transmit data

write:

Read SSR and check that the TDRE

flag is set to 1, then write transmit data

to TDR and clear the TDRE flag to 0.

[3] Serial transmission continuation

procedure:

To continue serial transmission, be

sure to read 1 from the TDRE flag to

confirm that writing is possible, then

write data to TDR, and then clear the

TDRE flag to 0.

Checking and clearing of the TDRE

flag is automatic when the DMAC or

DTC is activated by a transmit-data-

empty interrupt (TXI) request and data

is written to TDR.

Figure 15.17 Sample Serial Transmission Flowchart

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 714 of 926

REJ09B0283-0300

15.6.4 Serial Data Reception (Clocked Synchronous Mode)

Figure 15.18 shows an example of SCI operation for reception in clocked synchronous mode. In

serial reception, the SCI operates as described below.

1. The SCI performs internal initialization in synchronization with a synchronization clock input

or output, starts receiving data, and stores the received data in RSR.

2. If an overrun error (when reception of the next data is completed while the RDRF flag is still

set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at th is tim e,

an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag

remains to be set to 1.

3. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is

transferre d to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrup t request is

generated. Because the RXI interrupt routine reads the receive data transferred to RDR before

reception of the next receive data has finished, continuous reception can be enabled.

Bit 7

Serial

data

Serial

clock

1 frame

RDRF

ORER

Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7

RXI interrupt request

generated RDR data read and

RDRF flag cleared to 0

in RXI interrupt handling

routine

RXI interrupt request

generated ERI interrupt request

generated by overrun

error

Figure 15.18 Example of SCI Operation in Reception

Transfer cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER,

FER, PER, and RDRF bits to 0 before resuming reception. Figure 15.19 shows a sample flowchart

for serial data reception.

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 715 of 926

REJ09B0283-0300

Yes

<End>

[1]

Initialization

Start of reception

[2]

Yes

Read RDRF flag in SSR [4]

[5]

Clear RE bit in SCR to 0

Error processing

(Continued below)

[3]

Read receive data in RDR, and

clear RDRF flag in SSR to 0

Yes

ORER = 1?

RDRF = 1?

All data received?

Read ORER flag in SSR

[1]

[2] [3]

[4]

[5]

SCI initialization:

The RxD pin is automatically

designated as the receive data

input pin.

Receive error handling:

If a receive error occurs, read the

ORER flag in SSR, and after

performing the appropriate error

handling, clear the ORER flag to

0. Transfer cannot be resumed if

the ORER flag is set to 1.

SCI status check and receive

data read:

Read SSR and check that the

RDRF flag is set to 1, then read

the receive data in RDR and

clear the RDRF flag to 0.

Transition of the RDRF flag from

0 to 1 can also be identified by

an RXI interrupt.

Serial reception continuation

procedure:

To continue serial reception,

before the MSB (bit 7) of the

current frame is received, finish

reading the RDRF flag, reading

RDR, and clearing the RDRF flag

to 0. The RDRF flag is cleared

automatically when the DMAC or

DTC is activated by a receive-

data-full interrupt (RXI) request

and the RDR value is read.

<End>

Error handling

Overrun error handling

[3]

Clear ORER flag in SSR to 0

Figure 15.19 Sample Serial Reception Flowchart

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 716 of 926

REJ09B0283-0300

15.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous

Mode)

Figure 15.20 shows a sample flowchart for simultaneous serial transmit and receive operations.

The following procedure should be used for simultaneous serial data transmit and receive

operatio ns after the SCI is initialized. To switch from transmit mode to simu ltaneous transmit and

receive mode, after checking that the SCI has finished transmission and the TDRE and TEND

flags are set to 1, clear TE to 0. Then simultaneously set TE and RE to 1 with a single instruction.

To switch from receive mode to simultaneous transmit and receive mode, after checking that the

SCI has finished reception, clear RE to 0. Then after checking that the RDRF and receive error

flags (ORER, FER, and PER) are cleared to 0, simultaneously set TE and RE to 1 with a single

instruction.

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 717 of 926

REJ09B0283-0300

Yes

<End>

[1]

Initialization

Start of transmission/reception

[5]

Error handling

[3]

Read receive data in RDR, and

clear RDRF flag in SSR to 0

Yes

ORER = 1?

All data received?

[2]

Read TDRE flag in SSR

Yes

TDRE = 1?

Write transmit data to TDR and

clear TDRE flag in SSR to 0

Yes

RDRF = 1?

Read ORER flag in SSR

[4]

Read RDRF flag in SSR

Clear TE and RE bits in SCR to 0

Note: When switching from transmit or receive operation to simultaneous

transmit and receive operations, first clear the TE and RE bits to 0,

then set both these bits to 1 simultaneously.

[1]

[2]

[3]

[4]

[5]

SCI initialization:

The TxD pin is designated as the

transmit data output pin, and the

RxD pin is designated as the

receive data input pin, enabling

simultaneous transmit and receive

operations.

SCI status check and transmit data

write:

Read SSR and check that the

TDRE flag is set to 1, then write

transmit data to TDR and clear the

TDRE flag to 0.

Transition of the TDRE flag from 0 to

1 can also be identified by a TXI

interrupt.

Receive error handling:

If a receive error occurs, read the

ORER flag in SSR, and after

performing the appropriate error

handling, clear the ORER flag to 0.

Transmission/reception cannot be

resumed if the ORER flag is set to 1.

SCI status check and receive data

read:

Read SSR and check that the

RDRF flag is set to 1, then read the

receive data in RDR and clear the

RDRF flag to 0. Transition of the

RDRF flag from 0 to 1 can also be

identified by an RXI interrupt.

Serial transmission/reception

continuation procedure:

To continue serial transmission/

reception, before the MSB (bit 7) of

the current frame is received, finish

reading the RDRF flag, reading

RDR, and clearing the RDRF flag to

0. Also, before the MSB (bit 7) of

the current frame is transmitted,

read 1 from the TDRE flag to

confirm that writing is possible.

Then write data to TDR and clear

the TDRE flag to 0.

Checking and clearing of the TDRE

flag is automatic when the DMAC or

DTC is activated by a transmit-data-

empty interrupt (TXI) request and

data is written to TDR. Also, the

RDRF flag is cleared automatically

when the DMAC or DTC is activated

by a receive-data-full interrupt (RXI)

request and the RDR value is read.

Figure 15.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 718 of 926

REJ09B0283-0300

15.7 Operation in Smart Card Interface Mode

The SCI supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification

Card) as a serial communication interface extension function. Switching between the normal serial

communication interface and the Smart Card interface is carried out by means of a register setting.

15.7.1 Pin Connection Example

Figure 15.21 shows an example of connection with the Smart Card. In communication with an IC

card, since both transmission and reception are carried out on a single data transmission line, the

TxD pin and RxD pin should be connected with the LSI pin. The data transmission line should be

pulled up to th e VCC power supply with a resistor. If an IC card is not connected, and the TE and

RE bits are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be

carried out. Wh en the clock generated on the SCI is used by an IC card, the SCK pin output is

input to the CLK pin of th e IC card. This LSI port output is used as the reset signal.

TxD

RxD

This LSI

I/O

Connected equipment

IC card

Data line

CLK

RST

SCK

Rx (port) Clock line

Reset line

Figure 15.21 Schematic Diagram of Smart Card Interface Pin Connections

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 719 of 926

REJ09B0283-0300

15.7.2 Data Format (Except for Block Transfer Mo de)

Figure 15.22 shows the transfer data format in Smart Card interface mode.

• One frame consists of 8-bit data plus a parity bit in asynchronous mode.

• In transmissio n, a guard time of at least 2 etu (Eleme ntary Time Unit: the time for transfer of

one bit) is left between the end of the parity bit and th e start of the next frame.

• If a parity error is detected during reception, a low error signal level is output for one etu

period, 10.5 etu after the start bit.

• If an error sig nal is sampled dur ing tr ansmission, th e same data is retransmitted automatically

after the elapse of 2 etu or longer.

Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp

When there is no parity error

Transmitting station output

Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp

When a parity error occurs

Transmitting station output

Receiving station

output

: Start bit

: Data bits

: Parity bit

: Error signal

Legend:

D0 to D7

Figure 15.22 Normal Smart Card Interface Data Format

Data transfer with the types of IC cards (direct convention and inverse convention) are performed

as described in the following.

AZZAZZ ZZAA(Z) (Z) State

D0 D1 D2 D3 D4 D5 D6 D7 Dp

Figure 15.23 Direct Convention (SDIR = SINV = O/E

E = 0)

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 720 of 926

REJ09B0283-0300

As in the above sample start character, with the direct convention type, the logic 1 level

corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order.

The start character data above is H'3B. For the direct convention type, clear the SDIR and SINV

bits in SCMR to 0 . According to the Smart Card r egulatio ns, clear the O/E bit in SMR to 0 to

select even parity mode.

AZZAAA ZAAA(Z) (Z) State

D7 D6 D5 D4 D3 D2 D1 D0 Dp

Figure 15.24 Inverse Convention (SDIR = SINV = O/E

E = 1)

With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to

state Z, and transfer is performed in MSB-first order. The start character data above is H'3F. For

the inverse convention type, set the SDIR and SINV bits in SCMR to 1. Accor ding to the Smart

Card regulations, even parity mode is the logic 0 level of the parity bit, and corresponds to state Z.

In this LSI, th e SI NV bit inverts only data bits D7 to D0. Therefore, set the O/E bit in SMR to 1 to

invert the parity bit for both transmission and reception.

15.7.3 Block Transfer Mode

Operation in block transfer mode is the same as that in normal Smart Card interface, except for the

followin g points.

• In reception, though the parity check is performed, no error signal is ou tput even if an error is

detected. However, the PER bit in SSR is set to 1 and must be cleared before receiving the

parity bit of the next frame.

• In transmissio n, a guard time of at least 1 etu is left between the end of the parity bit and the

start of the next frame.

• In transmission, because retransmission is not performed, the TEND flag is set to 1, 11.5 etu

after tr a nsmission sta rt.

• As with the normal Smart Card interface, the ERS flag indicates the error signal status, but

since error signal tran sfer is not performed, this flag is always cleared to 0.

15.7.4 Receive Data Sampling Timing and Reception Margin

Only the internal clock g enerated by the on- chip b aud rate generator is used as transmit/receive

clock in Smart Card interface. In Smart Card interface mode, the SCI operates on a basic clock

with a frequency of 32, 64, 372, or 256 times the bit rate (fixed at 16 times in normal

asynchronous mode) as determined by bits BCP1 and BCP0. In reception, the SCI samples the

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 721 of 926

REJ09B0283-0300

falling edge of the start bit using the basic clock, and performs intern al synchronization. As shown

in figure 15.25, by sampling receive data at the rising-edge of the 16th, 32nd, 186th, or 128th

pulse of the basic clock, data can be latched at the middle of the bit. The reception margin is given

by the following formula.

M = (0.5 – ) – (L – 0.5) F – (1 + F) × 100 [%]



D – 0.5



Where M: Reception margin (%)

N: Ratio of bit rate to clock (N = 32, 64, 372, and 256)

D: Clock duty cycle (D = 0 to 1.0)

L: Frame length (L = 10)

F: Absolute value of clock frequency deviation

Assuming values of F = 0, D = 0.5 and N = 372 in the above formula, the reception margin

formula is as follows.

M = (0.5 – 1/2 × 372) × 100%

= 49.866%

Internal

basic clock

372 clocks

186 clocks

Receive data

(RxD)

Synchronization

sampling timing

D0 D1

Data sampling

timing

185 371 0

371

185 0

Start bit

Figure 15.25 Receive Data Sampling Timing in Smart Card Mode

(Using Clock of 372 Times the Bit Rate)

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 722 of 926

REJ09B0283-0300

15.7.5 Initialization

Before transmitting an d receivin g data, in itialize the SCI as described be lo w. Initializatio n is also

necessary when switching from transmit mode to receive mode, or vice versa.

1. Clear the TE an d RE bits in SCR to 0.

2. Clear the error flag s ERS, PER, and ORER in SSR to 0.

3. Set the GM, BLK, O/E, BCP1, BCP0, CKS1, and CKS0 bits in SMR. Set the PE bit to 1.

4. Set the SMIF, SDIR, and SINV bits in SCMR.

When the SMIF bit is set to 1, the TxD and RxD pins are both switched from ports to SCI pins,

and are placed in the high-impedance state.

5. Set the value corresponding to the bit rate in BRR.

6. Set the CKE0 and CKE1 bits in SCR. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0.

If the CKE0 b it is set to 1, the clock is ou tput from the SCK pin.

7. Wait at least on e bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE

bit and RE bit at the same time, except for self-diagnosis.

To switch from receive mode to transmit mode, after checking that the SCI has finished reception,

initialize the SCI, and clear RE to 0 and set TE to 1. Whether SCI has finished reception can be

checked with the RDRF, PER, or ORER flag. To switch from transmit mode to receive mode,

after checking th at th e SCI has finished transmission, initialize th e SCI , and clear TE to 0 and set

RE to 1. Whether SCI has finished transmission can be checked with the TEND flag.

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 723 of 926

REJ09B0283-0300

15.7.6 Data Transmission (Except for Block Transfer Mode)

As data transmission in Smart Card interface mode involves error signal sampling and

retransmission processing, the operations are different from those in normal serial communication

interface mode (except for block transfer mode). Figure 15.26 illustrates the retransfer operation

when the SCI is in transmit mo de.

1. If an error signal is sampled from the receiving end after tran smission of one frame is

completed, the ERS bit in SSR is set to 1 . I f the RIE bit in SCR is se t at this time, an ERI

interrupt request is generated. The ERS bit in SSR should be cleared to 0 before the next parity

bit is sampled.

2. The TEND bit in SSR is not set for a frame for which an error signal is received. Data is

retransferred from TDR to TSR, and r etransmitted automatically.

3. If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set.

Transmission of one frame, including a retransfer, is judged to have been completed, and the

TEND bit in SSR is se t to 1. If the TIE bit in SCR is set at this time, a TXI inter r upt request is

genera ted. Writing tr ansm it data to TDR transf er s the next transmit data.

Figure 15.28 shows a flowchart for transmission. The sequence of transmit operations can be

performed automatically by specifying the DTC or DMAC to be activated with a TXI interrupt

source. In a transmit operation, the TDRE flag is also set to 1 at the same time as the TEND flag in

SSR, and a TXI inter r upt will b e generated if the TIE bit in SCR has been set to 1 . If th e TXI

request is designated beforehand as a DTC or DMAC activation source, the DTC or DMAC will

be activated by the TXI requ est, and tr ansfer of the transmit data will be car r ied ou t. The TDRE

and TEND flags are automatically cleared to 0 when data transfer is performed by the DTC or

DMAC. In the even t of an error, the SCI retransmits the same data automatically. Dur ing this

period, the TEND flag remains cleared to 0 and the DTC or DMAC is not activated. Therefore, the

SCI and DTC or DMAC will automatically transmit the specified number of bytes in the event of

an error, including retransmission. However, the ERS flag is not cleared automatically when an

error occurs, and so the RIE bit should be set to 1 beforehand so that an ERI request will be

generated in the ev ent of an error, and the ERS flag will be cleared.

When performing transfer using the DTC or DMAC, it is essential to set and enable th e DTC or

DMAC before carrying out SCI setting. For details on the DTC or DMAC setting procedures,

refer to section 9, Data Transfer Controller (DTC) or section 7, DMA Controller (DMAC).

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 724 of 926

REJ09B0283-0300

D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) Ds D0 D1 D2 D3 D4Ds

Transfer

frame n+1

Retransferred framenth transfer frame

TDRE

TEND

[6]

FER/ERS

Transfer to TSR from TDR Transfer to TSR from TDR Transfer to TSR

from TDR

[7] [9]

[8]

Figure 15.26 Retransfer Operation in SCI Transmit Mode

The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag

generation timing is shown in figure 15.27.

Ds D0 D1 D2 D3 D4 D5 D6 D7 DpI/O data

12.5etu

TXI

(TEND interrupt)

11.0etu

Guard

time

When GM = 0

When GM = 1

: Start bit

: Data bits

: Parity bit

: Error signal

Legend:

D0 to D7

Figure 15.27 TEND Flag Generation Timing in Transmission Operation

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 725 of 926

REJ09B0283-0300

Initialization

Yes

Clear TE bit to 0

Start transmission

Start

Yes

End

Write data to TDR,

and clear TDRE flag

in SSR to 0

Error processing

TEND = 1?

All data transmitted ?

TEND = 1?

ERS = 0?

Figure 15.28 Example of Transmission Processing Flow

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 726 of 926

REJ09B0283-0300

15.7.7 Serial Data Reception (Except for Block Transfer Mode)

Data reception in Smart Card interface mode uses the same operation procedure as for normal

serial communication in terface mode. Figure 15.29 illustrates the retransfer operation when the

SCI is in receive mode.

1. If an error is found when the received parity bit is checked, the PER bit in SSR is

automatically set to 1. If the RIE bit in SCR is set at this time, an ERI interrupt request is

generated. The PER bit in SSR should be cleared to 0 before the next parity bit is sampled.

2. The RDRF bit in SSR is not set fo r a f rame in which an error has occurred.

3. If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1.

The receive operation is judged to have been completed normally, and the RDRF flag in SSR

is automatically set to 1. If the RI E bit in SCR is set at this time, an RXI interrup t r equ e st is

generated.

Figure 15.30 shows a flowchart for reception. The sequence of receive operations can be

performed automatically by specifying the DTC or DMAC to be activated with an RXI interrupt

source. In a receive operation, an RXI interrupt request is generated when the RDRF flag in SSR

is set to 1. If the RXI request is designated beforehand as a DTC or DMAC activation source, the

DTC or DMAC will be activated by the RXI request, and tran sfer of the receive data will be

carried out. The RDRF flag is cleared to 0 automatically when data transfer is performed by the

DTC or DMAC. If an error occurs in receive mode and the ORER or PER flag is set to 1, a

transfer err or in ter rup t ( E RI) request will be generated, and so the error flag must be clear ed to 0.

In the event of an error, the DTC or DMAC is not activated and receive data is skipped. Therefore,

receive data is transferred for only the specified number of bytes in the event of an error. Even

when a parity error occurs in receive mode and the PER flag is set to 1, the data that has been

received is transferred to RDR and can be read from there.

Note: For details on receive operations in block transfer mode, refer to section 15.4, Operation in

Asynchronous Mode.

D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE)Ds D0 D1 D2 D3 D4Ds

Transfer

frame n+1

Retransferred framenth transfer frame

RDRF

[1]

PER

[2]

[3]

[4]

Figure 15.29 Retransfer Operation in SCI Receive Mode

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 727 of 926

REJ09B0283-0300

Initialization

Read RDR and clear

RDRF flag in SSR to 0

Clear RE bit to 0

Start reception

Start

Error processing

Yes

ORER = 0 and

PER = 0

RDRF = 1?

All data received?

Yes

Figure 15.30 Example of Reception Processing Flow

15.7.8 Clock Output Control

When the GM bit in SMR is set to 1, the clo ck output level can be fixed with bits CKE1 and

CKE0 in SCR. At this time, the minimum clock pulse width can be made the specified width.

Figure 15.31 shows the timing for fixing the clock output level. In this example, GM is set to 1,

CKE1 is cleared to 0, and th e CKE0 bit is controlled.

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 728 of 926

REJ09B0283-0300

Specified pulse width

SCK

CKE0

Specified pulse width

Figure 15.31 Timing for Fixing Clock Output Level

When turning on the power or switching between Smart Card interface mode and software standby

mode, the following procedures should be followed in order to maintain the clock duty cycle.

Powering On: To secure the clock duty cycle from power-on, the following switching procedure

should be followed.

1. The initial state is port input and high impedance. Use a pull-up resistor or pull-down

resistor to f ix the potential.

2. Fix the SCK pin to the specified output leve l with the CKE1 bit in SCR.

3. Set SMR and SCMR, and switch to smart card mode operation.

4. Set the CKE0 bit in SCR to 1 to star t clock output.

When changing fro m smart card interfa ce mode to software standby mode:

1. Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin

to the value for the fixed output state in software standby mode.

2. Write 0 to the TE bit and RE bit in the serial control register (SCR) to halt tran smit/receiv e

operation. At the same time, set the CKE1 bit to the value for the fixed outpu t state in

software standby mode.

3. Write 0 to the CKE0 bit in SCR to halt the clock.

4. Wait for one serial clock period.

During this interval, clock output is f ix ed at the specified level, with the duty cy cle

preserved.

5. Make the transition to the software standby state.

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 729 of 926

REJ09B0283-0300

When returning t o smart card interf ace mode from software standby mo de:

1. Exit the software standby state.

2. Write 1 to the CKE0 bit in SCR and output the clock. Signal generation is started with the

normal duty cycle.

[1] [2] [3] [4] [5] [7]

Software

standby

Normal operation Normal operation

[6]

Figure 15.32 Clock Halt and Restart Procedure

15.8 IrDA Operation

When the Ir DA f unc tion is enabled with bit IrE in IrCR, the SCI_0 TxD0 and RxD0 signals are

subjected to waveform encoding/decoding conforming to IrDA specification version 1.0 (IrTxD

and IrRxD pins). By connecting these pins to an infrared transceiver/receiver, it is possible to

implement infrared transmission/reception conforming to the IrDA specification version 1.0

system.

In the IrDA specification version 1.0 system, communication is started at a transfer rate of 9600

bps, and subsequently the transfer rate can be varied as necessary. As the IrDA interface in this

LSI does not include a function for varying the transfer rate automatically, th e tr ansfer rate setting

must be changed by software.

Figure 15.33 shows a block diagram of the IrDA function.

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 730 of 926

REJ09B0283-0300

IrDA

Pulse encoder

Pulse decoder

TxD0/IrTxD

RxD0/IrRxD

SCI0

TxD

RxD

IrCR

Figure 15.33 Block Diagram of IrDA

Transm ission: In transmission, the output signal (UART frame) from the SCI is converted to an

IR frame by the IrDA interface (see figure 15.34).

When the serial data is 0, a high pulse of 3/16 the bit rate (interval equivalent to the width of one

bit) is output (initial value). The high-level pulse can b e v aried according to the setting of bits

IrCKS2 to IrCKS0 in IrCR.

In the specification, the high pulse width is fixed at a minimum of 1.41 µs, and a maximum of

(3/16 + 2.5%) × bit rate or (3/16 × bit rate) + 1.08 µs. When system clock φ is 20 MHz, 1.6 µs can

be set for a high pulse width with a minimum value of 1.41 µs.

When the serial data is 1, no pulse is output.

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 731 of 926

REJ09B0283-0300

UART frame Data

IR frame Data

0000 011 111

Start

bit

Transmit Receive

Stop

bit

Start

bit Stop

bit

Bit

cycle Pulse width

1.6 µs to 3/16 bit cycle

Figure 15.34 IrDA Transmit/Receive Operations

Reception: In reception, IR frame data is converted to a UART frame by the IrDA interface, and

input to the SCI.

When a high pulse is detected, 0 data is output, and if there is no pulse during a one-bit interval, 1

data is outpu t. Note that a pulse shorter than th e minimum pulse width of 1.41 µs will be identif ied

as a 0 signal.

High Pulse Width Selection: Table 15.12 shows possible settings for bits IrCKS2 to IrCKS0

(minimum pulse width), and operating frequencies of this LSI and bit rates, for making the pulse

width shorter than 3/16 times th e bit rate in transmissio n.

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 732 of 926

REJ09B0283-0300

Table 15.12 Settings of Bits IrCKS2 to IrCKS0

Bit Rate (bps) (Above) /Bit Period ×

××

× 3/16 (µs) (Below)

2400 9600 19200 38400 57600 115200

Operating

Frequency

φφ

φ (MHz) 78.13 19.53 9.77 4.88 3.26 1.63

2 010 010 010 010 010 —

2.097152 010 010 010 010 010 —

2.4576 010 010 010 010 010 —

3 011 011 011 011 011 —

3.6864 011 011 011 011 011 011

4.9152 011 011 011 011 011 011

5 011 011 011 011 011 011

6 100 100 100 100 100 100

6.144 100 100 100 100 100 100

7.3728 100 100 100 100 100 100

8 100 100 100 100 100 100

9.8304 100 100 100 100 100 100

10 100 100 100 100 100 100

12 101 101 101 101 101 101

12.288 101 101 101 101 101 101

14 101 101 101 101 101 101

14.7456 101 101 101 101 101 101

16 101 101 101 101 101 101

16.9344 101 101 101 101 101 101

17.2032 101 101 101 101 101 101

18 101 101 101 101 101 101

19.6608 101 101 101 101 101 101

20 101 101 101 101 101 101

25 110 110 110 110 110 110

Legend:

—: A bit rate setting cannot be made on the SCI side.

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 733 of 926

REJ09B0283-0300

15.9 Interrupt Sources

15.9.1 Interrupts in Normal Serial Communication Interface Mode

Table 15.13 shows the interrupt sources in normal serial communication interface mode. A

different interrupt vector is assigned to each interrupt source, and individual interrupt sources can

be enabled or disabled using the enable bits in SCR.

When the TDRE flag in SSR is set to 1, a TXI inter rupt request is generated. When the TEND flag

in SSR is set to 1, a TEI interrupt request is generated. A TXI interrup t can activate the DTC or

DMAC to perform data transfer. Th e TDRE flag is cleared to 0 automatically when data transfer is

performed by the DTC or DMAC.

When the RDRF flag in SSR is set to 1, an RXI interru pt request is gener a ted. Wh en the ORER,

PER, or FER flag in SSR is set to 1, an ERI interrupt request is ge nerated. An RXI interr upt

request can activate the DTC or DMAC to perform data transfer. The RDRF flag is cleared to 0

automatically wh en data transfer is perform ed b y the DTC o r DMAC.

A TEI interrupt is gene r ated when the TEND flag is set to 1 while the TEIE b it is set to 1. If a TEI

interrupt and a TXI interrupt are generated simultaneously, the TXI interrupt h as priority for

acceptance. However, note that if the TDRE and TEND flags are cleared simultaneously by the

TXI interrup t rou tine, the SCI cannot branch to th e TEI inter rupt rou tine later.

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 734 of 926

REJ09B0283-0300

Table 15.13 SCI I nterrupt Sources

Channel Name Interrupt Source Interrupt Flag DTC

Activation DMAC

Activation Priority

ERI0 Receive Error ORER, FER, PER Not poss i bl e Not possible Hi gh

RXI0 Rec eive Data Full RDRF Possible P ossible

TXI0 Transmit Data Empty TDRE Possible Possible

TEI0 Transmiss i on End TEND Not possible Not possi bl e

ERI1 Receive Error ORER, FER, PER Not poss i bl e Not possible

RXI1 Rec eive Data Full RDRF Possible P ossible

TXI1 Transmit Data Empty TDRE Possible Possible

TEI1 Transmiss i on End TEND Not possible Not possi bl e

ERI2 Receive Error ORER, FER, PER Not poss i bl e Not possible

RXI2 Rece i ve Data Full RDRF Possible Not possi bl e

TXI2 Transm it Dat a Empty TDRE Possible Not possible

TEI2 Transmiss i on End TEND Not possible Not possi bl e Low

15.9.2 Interrupts in Smart Card Interface Mode

Table 15.14 shows the interrupt sources in Smart Card interface mode. The transmit end interrupt

(TEI) request cannot be used in this mode.

Table 15.14 SCI I nterrupt Sources

Channel Name Interrupt Source Interrupt Flag DTC

Activation DMAC

Activation Priority

ERI0 Recei ve Error, detection ORER, PER, ERS Not possible Not possible High

RXI0 Rec eive Data Full RDRF Possibl e Possible

TXI0 Trans m it Data Empty TEND P ossible Possible

ERI1 Recei ve Error, detection ORER, PER, ERS Not possible Not possible

RXI1 Rec eive Data Full RDRF Possibl e Possible

TXI1 Trans m it Data Empty TEND P ossible Possible

ERI2 Recei ve Error, detection ORER, PER, ERS Not possible Not possible

RXI2 Rece i ve Data Full RDRF Possi b l e Not possi bl e

TXI2 Trans m it Data Empty TEND P ossible Not possible Low

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 735 of 926

REJ09B0283-0300

In Smart Card interface mode, as in normal serial communication interface mode, transfer can be

carried out using the DTC or DMAC. In transmit o perations, the TDRE flag is also set to 1 at the

same time as the TEND flag in SSR, and a TXI interrup t is g enerated. If the TXI request is

designated beforehand as a DTC or DMAC activ ation source, the DTC or DMAC will be activated

by the TXI request, and transfer of the transmit data will be carr ied out. The TDRE and TEND

flags are automatically cleared to 0 wh en data transfer is performed by the DTC or DMAC. In the

event of an error, the SCI retransmits the same data automatically . During this period, the TEND

flag remains cleared to 0 and the DTC or DMAC is not activated. Therefore, th e SCI and DTC or

DMAC will autom atically transmit the sp ecif ied number of bytes in the event of an error,

including retransmission. However, the ERS flag is not cleared automatically when an error

occurs, and so the RIE bit should be set to 1 beforehand so th at an ERI r equest will be generated in

the event of an error, and the ERS flag will be clear ed .

When performing transfer using the DTC or DMAC, it is essential to set and enable th e DTC or

DMAC before carrying out SCI setting. For details on the DTC or DMAC setting procedures,

refer to section 9, Data Transfer Controller (DTC) or section 7, DMA Controller (DMAC).

In receive operations, an RXI interrupt request is generated when the RDRF flag in SSR is set to

1. If the RXI request is designated beforehand as a DTC or DMAC activation source, the DTC or

DMAC will be activated b y the RXI request, and transfer of the receive data will be carried out.

The RDRF flag is cleared to 0 automatically when data transfer is performed by the DTC or

DMAC. If an error occurs, an error flag is set but the RDRF flag is not. Consequently, the DTC or

DMAC is not activated, but instead, an ERI interrupt request is sent to the CPU. Therefore, the

error flag should be cleared.

15.10 Usage Notes

15.10.1 Module Stop Mode Setting

SCI operatio n can be disabled or enabled u sin g the m odule stop control register. Th e initial setting

is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For

details, refer to section 22, Power-Down Modes.

15.10.2 Break Detection and Processing

When framing error detection is performed, a break can be detected by reading the RxD pin value

directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the

PER flag may also be set. Note that, since the SCI continues the receive operation after receiving a

break, even if the FER flag is cleared to 0, it will be set to 1 again.

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 736 of 926

REJ09B0283-0300

15.10.3 Mark St ate and Break Sending

When TE is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are

determined by DR and DDR. This can be used to set the TxD pin to mark state or send a break

during serial da ta tr ansmission. To m a intain the communication line at ma r k state until TE is set to

1, set both PCR and PDR to 1. Since TE is cleared to 0 at this point, the TxD pin becomes an I/O

port, and 1 is output from the TxD pin. To send a break during serial transmission, first set PCR to

1 and clear PDR to 0, an d then clear TE to 0. When TE is cleared to 0, the transmitter is initialized

regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from

the TxD pin.

15.10.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)

Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if

the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting

transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared

to 0.

15.10.5 Relation between Writes to TDR and the TDRE Flag

The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from

TDR to TSR. When the SCI transfers data f r om TDR to TSR, the TDRE flag is set to 1.

Data can be written to TDR r e g ardless of the state of the TDRE flag. Ho wev e r, if n ew data is

written to TDR when the TDRE flag is cleared to 0, the data sto r ed in TDR will be lost since it has

not yet been tran sf erred to TSR. It is therefore essential to check that the TDRE flag is set to 1

before wr iting transmit data to TDR.

15.10.6 Restrictions on Use of DMAC or DTC

• When an external clock source is used as the serial clock, the transmit clock should not be

input until at least 5 φ clock cycles after TDR is updated by the DMAC or DTC. Misoperation

may occur if the transmit clock is input within 4 φ clocks after TDR is updated. (Figure 15.35)

• When RDR is read by the DMAC or DTC, b e sure to set the activation sour ce to the relevant

SCI receive-data-full interrupt (RXI).

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 737 of 926

REJ09B0283-0300

LSB

Serial data

SCK

D1 D3 D4 D5D2 D6 D7

Note: When operating on an external clock, set t > 4 clocks.

TDRE

Figure 15.35 Example of Synchronous Transmission Using DTC

15.10.7 Operation in Case of Mode Transition

• Transmission

Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module

stop mode or so ftware standby mode transition. TSR, TDR, and SSR are reset. The output pin

states in module stop mode or software standby mode depend on the port settings, and become

high-level output after the relevant mode is cleared. If a transition is made during transmission,

the data being transmitted will be undefined.

When transmitting without changing the transmit mode after the relevant mode is cleared,

transmission can be started by setting TE to 1 again, and performing the fo llo wing sequence:

SSR read → TDR write → TDRE clearance. To transmit with a different transmit mode after

clearing the relevant mode, the procedure must be started again from initialization.

Figure 15.36 shows a sample flowchart for mode transition during transmission. Port pin states

during mode transition are shown in figures 15.37 and 15.38.

Operation should also be stopped (by clearing TE, TIE, and TEIE to 0) before making a

transition from transmission by DTC transfer to module stop mode or software standby mode

transition. To perform transmission with the DTC after th e r elevan t m ode is cleared, setting TE

and TIE to 1 will set the TXI flag and start DTC transmission.

• Reception

Receive operation should be stopped (by clearing RE to 0) before making a module stop mode

or software standby mode transition. RSR, RDR, and SSR are reset. If a transition is made

during reception, th e data being received will be invalid.

To continue receiving without changing the reception mode after the relevant mode is cleared,

set RE to 1 before starting reception. To receive with a different receive mode, the procedure

must be started again from initialization.

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 738 of 926

REJ09B0283-0300

Figure 15.39 shows a sample flowchart for mode transition during reception.

Read TEND flag in SSR

TE = 0

Transition to software

standby mode

Exit from software

standby mode

Change

operating mode? No

All data

transmitted?

TEND = 1

Yes

[1]

[3]

[2]

TE = 1Initialization

[1] Data being transmitted is interrupted.

After exiting software standby mode,

normal CPU transmission is possible

by setting TE to 1, reading SSR,

writing TDR, and clearing TDRE to 0,

but note that if the DTC has been

activated, the remaining data in

DTCRAM will be transmitted when

TE and TIE are set to 1.

[2] If TIE and TEIE are set to 1, clear

them to 0 in the same way.

[3] Includes module stop mode.

Figure 15.36 Sample Flowchart for Mode Transition during Transmission

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 739 of 926

REJ09B0283-0300

SCK output pin

TE bit

TxD output pin Port input/output High outputPort input/output High output Start Stop

Start of transmission End of

transmission

Port input/output

SCI TxD output Port SCI TxD

output

Port

Transition

to software

standby

Exit from

software

standby

Figure 15.37 Port Pin States during Mode Transition

(Internal Clock, Asynchronous Transmission)

Port input/output

Last TxD bit held

High output*

Port input/output Marking output

Port input/output

SCI TxD output PortPort

Note: * Initialized by software standby.

SCK output pin

TE bit

TxD output pin

SCI TxD

output

Start of transmission End of

transmission

Transition

to software

standby

Exit from

software

standby

Figure 15.38 Port Pin States during Mode Transition

(Internal Clock, Synchronous Transmission)

Section 15 Seri al Communication Interface (SCI, IrDA)

Rev. 3.00 Mar 17, 2006 page 740 of 926

REJ09B0283-0300

RE = 0

Transition to software

standby mode

Read receive data in RDR

Read RDRF flag in SSR

Exit from software

standby mode

Change

operating mode? No

RDRF = 1

Yes

No [1]

[2]

RE = 1Initialization

[1] Receive data being received

becomes invalid.

[2] Includes module stop mode.

Figure 15.39 Sample Flowchart for Mode Transition during Reception

Section 16 A/D Converter

Rev. 3.00 Mar 17, 2006 page 741 of 926

REJ09B0283-0300

Section 16 A/D Converter

This LSI includ e s a successive approxim ation type 10-bit A/D conver ter that allows up to twelve

analog input channels to be selected. The block diagram of A/D converter is shown in figure 16.1.

16.1 Features

• 10-b it resolution

• Twelve input channels

• Conversion time: 6.7 µs per channel (at 20-MHz operation)

• Two kinds of operating modes

 Single mode: Single-channel A/D conversion

 Scan mode: Continuous A/D conversion on 1 to 4 channels, or 1 to 8 channels (H8S/2678R

Group)

• Four data registers (H8S/2678 Group) or eight data registers (H8S/2678R Group)

 Conversion results are held in a 16-bit data register for each channel

• Sample and hold fun c tion

• Three kinds of conversion start

 Conversion can be started by software, 16-bit timer pulse unit (TPU), conversion start

trigger by 8 -bit tim er ( T MR), or external trigger signal.

• Interrupt request

 A/D conversion end interrupt (ADI) requ est can be generated

• Module stop mode can be set

ADCMS01A_010020020400

Section 16 A/D Converter

Rev. 3.00 Mar 17, 2006 page 742 of 926

REJ09B0283-0300

Module data bus

Control circuit

Internal data bus

10-bit D/A

Comparator

–

Sample-and-

hold circuit

ADI interrupt

signal

Bus interface

AVCC

Vref

AVSS

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

AN12

AN13

AN14

AN15

ADTRG Conversion start

trigger from 8-bit

timer or TPU

Successive approximations

Multiplexer

Legend:

ADCR: A/D control register

ADCSR: A/D control/status register

ADDRA: A/D data register A

ADDRB: A/D data register B

ADDRC: A/D data register C

Note:

Only in H8S/2678R Group.

ADDRD: A/D data register D

ADDRE: A/D data register E

ADDRF: A/D data register F

ADDRG: A/D data register G

ADDRH: A/D data register H

****

Figure 16.1 Block Diagram of A/D Converter

Section 16 A/D Converter

Rev. 3.00 Mar 17, 2006 page 743 of 926

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16.2 Input/Output Pins

Table 16.1 shows the pin configuration of th e A/D converter.

The twelve analog input pins are divided into two channel sets: channel set 0 (AN0 to AN7) and

channel set 1 (AN12 to AN15).

In the H8S/2678 Group, each channel set is divided in to four channels × two groups: group 0 in

channel set 0 (AN0 to AN3), group 1 in channel set 0 (AN4 to AN7), and group1 in channel set 1

(AN12 to AN15).

The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. The

Vref pin is the A/D conversion reference voltage pin.

Table 16.1 A/D Converter Pins

Pin Name Symbol I/O Function

Analog power supply pin AVCC Input Analog block power supply

Analog ground pin AVSS Input Analog block ground

Reference voltage pin Vref Input A/D conversion reference voltage

Analog input pin 0 AN0 Input Channel set 0 analog inputs

Analog input pin 1 AN1 Input

Analog input pin 2 AN2 Input

Analog input pin 3 AN3 Input

Analog input pin 4 AN4 Input

Analog input pin 5 AN5 Input

Analog input pin 6 AN6 Input

Analog input pin 7 AN7 Input

Analog input pin 12 AN12 Input Channel set 1 analog inputs

Analog input pi n 13 AN13 Input

Analog input pi n 14 AN14 Input

Analog input pi n 15 AN15 Input

A/D external trigger input

pin ADTRG Input External trigger input for starting A/D

conversion

Section 16 A/D Converter

Rev. 3.00 Mar 17, 2006 page 744 of 926

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16.3 Register Descriptions

The A/D converter has the following registers.

• A/D data register A (ADDRA)

• A/D data register B (ADDRB)

• A/D data register C (ADDRC)

• A/D data register D (ADDRD)

• A/D data register E (ADDRE)

• A/D data register F (ADDRF)

• A/D data register G (ADDRG)

• A/D data register H (ADDRH)

• A/D control/status register (ADCSR)

• A/D control register (ADCR)

16.3.1 A/D Data Registers A to H (ADDRA to ADDRH)

There are four 16-bit read-only ADDR registers, ADDRA to ADDRD (H8S/2678 Group) and

eight 16-bit read-only ADDR registers, ADDRA to ADDRH (H8S/2678R Group), used to store

the results of A/D conversion. The ADDR registers, which store a conversion result for each

channel, are shown in table 16.2.

The converted 10-bit data is stored to bits 15 to 6. The lower 6-bit data is always read as 0. ADDR

must not be accessed in 8-bit units and must be accessed in 16-bit units.

In the H8S/2678 Group, the data bus between the CPU and the A/D converter is 8-bit width. The

upper byte can be read directly from the CPU, but the lower byte should be read via a temporary

is read. When reading the ADDR, read the only upper byte, or read in word unit.

In the H8S/2678R Group, the data bus between the CPU and the A/D converter is 16-bit width.

The data can be read directly from the CPU.

Section 16 A/D Converter

Rev. 3.00 Mar 17, 2006 page 745 of 926

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Table 16.2 Analo g Input Channels a nd Corresponding ADDR Registers

• H8S/2678 Group

Analog Input Channel

Channel Set 0 (CH3 = 1) Channel Set 1 (CH3 = 0)

Group 0

(CH2 = 0) Group 1

(CH2 = 1) Group 0

(CH2 = 0) Group 1

(CH2 = 1)

A/D Data Register

which stores

conversion result

AN0 AN4 Setting prohibited AN12 ADDRA

AN1 AN5 Setting prohibited AN13 ADDRB

AN2 AN6 Setting prohibited AN14 ADDRC

AN3 AN7 Setting prohibited AN15 ADDRD

• H8S/2678R Group

Analog Input Channel

Channel Set 0 (CH3 = 0) Channel Set 1 (CH3 = 1) A/D Data Register which stores

conversion result

AN0 Nothing ADDRA

AN1 Nothing ADDRB

AN2 Nothing ADDRC

AN3 Nothing ADDRD

AN4 AN12 ADDRE

AN5 AN13 ADDRF

AN6 AN14 ADDRG

AN7 AN15 ADDRH

Section 16 A/D Converter

Rev. 3.00 Mar 17, 2006 page 746 of 926

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16.3.2 A/D Control/Status Register (ADCSR)

ADCSR controls A/D conversion op erations.

• H8S/2678 Group

Bit Bit Name Initial Value R/W Description

7ADF 0 R/(W)

*A/D End Flag

A status flag that indi cates the end of A/D

conversion.

[Setting conditions]

• When A/D conversion ends in single mode

• When A/D conversion ends on all specified

channels in scan mode

[Clearing cond iti ons ]

• When 0 is written after reading ADF = 1

• When the DTC or DMAC is activated by an

ADI interrupt and ADDR is read

6 ADIE 0 R/W A/D Interrupt Enable

A/D conversion end interrupt (ADI) request

enabled when 1 is set

5 ADST 0 R/W A/D Start

Clearing this bit to 0 stops A/D conversion, and

the A/D converter enters wait state. When this bit

is set to 1 by software, TPU (trigger), TMR

(trigger), or the ADTRG pin, A/D conversion

starts. This bit remains set to 1 during A/D

conversion . In single mo de, cle ared to 0

automatically when conversion on the specified

channel ends. In scan mode, conversion

continue s seq uent ial ly on the spec ifi ed channels

until this bit is cleared to 0 by a reset, or a

transition to hardware standby mode or software.

4 SCAN 0 R/W Scan Mode

Selects single mode or scan mode as the A/D

conversion operating mode.

0: Single mo de

1: Scan mode

Section 16 A/D Converter

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Bit Bit Name Initial Value R/W Description

3 CKS 0 R/W Clock Select

Used together with the CKS1 bit in ADCR to set

the A/D conversion time.

When CKS1 = 0

0: 530 states (max)

1: 68 states (max)

When CKS = 1

0: 266 states (max)

1: 134 states (max)

CH2

CH1

CH0

R/W

Channel Select 2 to 0

These bits are used together with the SCAN bit in

ADCSR and the CH3 bit in ADCR to select the

analog input channels.

When SCAN = 0, When SCAN = 1,

CH3 = 0 CH3 = 0

0XXX: Setting prohibited 0XXX: Setting

prohibited

100: AN12 100: AN12

101: AN13 101: AN12 and AN13

110: AN14 110: AN12 to AN14

111: AN15 111: AN12 to AN15

When SCAN = 0, When SCAN = 1,

CH3 = 1 CH3 = 1

000: AN0 000: AN0

001: AN1 001: AN0 and AN1

010: AN2 010: AN0 to AN2

011: AN3 011: AN0 to AN3

100: AN4 100: AN4

101: AN5 101: AN4 and AN5

110: AN6 110: AN4 to AN6

111: AN7 111: AN4 to AN7

Legend: X: Don’t care.

Note: *Only 0 can be written in bit 7, to clear the flag.

Section 16 A/D Converter

Rev. 3.00 Mar 17, 2006 page 748 of 926

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• H8S/2678R Group

Bit Bit Name Initial Value R/W Description

7ADF 0 R/(W)

*A/D End Flag

A status flag that indi cates the end of A/D

conversion.

[Setting conditions]

• When A/D conversion ends in single mode

• When A/D conversion ends on all specified

channels in scan mode

[Clearing cond iti ons ]

• When 0 is written after reading ADF = 1

• When the DTC or DMAC is activated by an

ADI interrupt and ADDR is read

6 ADIE 0 R/W A/D Interrupt Enable

A/D conversion end interrupt (ADI) request

enabled when 1 is set

5 ADST 0 R/W A/D Start

Clearing this bit to 0 stops A/D conversion, and

the A/D converter enters wait state.

Setting this bit to 1 starts an A/D conversion. In

single mode, cleared to 0 automatically when

conversion on the specified channel ends. In scan

mode, conversi on cont inues sequentially on the

specified channels until this bit is cleared to 0 by

software, a reset, or a transition to software

standby mode, hardware standby mode or module

stop mode.

4— 0 — Reserved

This bit is always read as 0 and cann ot be

modified.

Section 16 A/D Converter

Rev. 3.00 Mar 17, 2006 page 749 of 926

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Bit Bit Name Initial Value R/W Description

CH3

CH2

CH1

CH0

R/W

Channel select 3 to 0

Selects analog inpu t togeth er with bits SCANE

and SCANS in ADCR.

When SCANE = 0 and SCANS = X

0000: AN0 1000: Setting prohibited

0001: AN1 1001: Setting prohibited

0010: AN2 1010: Setting prohibited

0011: AN3 1011: Setting prohibited

0100: AN4 1100: AN12

0101: AN5 1101: AN13

0110: AN6 1110: AN14

0111: AN7 1111: AN15

When SCANE = 1 and SCANS = 0

0000: AN0 1000: Setting prohibited

0001: AN0 and AN1 1001: Setting prohibited

0010: AN0 to AN2 1010: Setting prohibited

0011: AN0 to AN3 1011: Setting prohibited

0100: AN4 1100: AN12

0101: AN4 and AN5 1101: AN12 and AN13

0110: AN4 to AN6 1110: AN12 to AN14

0111: AN4 to AN7 1111: AN12 to AN15

When SCANE = 1 and SCANS = 1

0000: AN0 1000: Setting prohibited

0001: AN0 and AN1 1001: Setting prohibited

0010: AN0 to AN2 1010: Setting prohibited

0011: AN0 to AN3 1011: Setting prohibited

0100: AN0 to AN4 1100: Setting prohibited

0101: AN0 to AN5 1101: Setting prohibited

0110: AN0 to AN6 1110: Setting prohibited

0111: AN0 to AN7 1111: Setting prohibited

Legend: X: Don’t care.

Note: *Only 0 can be written in bit 7, to clear the flag.

Section 16 A/D Converter

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16.3.3 A/D Co ntrol Register (ADCR)

ADCR enables A/D conversion start by an external trigger input.

• H8S/2678 Group

Bit Bit Name Initial Value R/W Description

6TRGS1

TRGS0 0

0R/W

R/W Timer Trigger Select 1 and 0

These bits select enabling or disabling of the start

of A/D conversion by a trigger signal.

00: A/D conversion start by external trigger is

disabled

01: A/D conversion start by external trigger (TPU)

is enabled

10: A/D conversion start by external trigger (TMR)

is enabled

11: A/D conversion start by external trigger pin

(ADTRG) is enabled

5, 4 — All 1 — Reserved

These bits are always read as 1 and cannot be

modified.

3 CKS1 1 R/W Cloc k Select 1

Used together with the CKS bit in ADCSR to set

the A/D conversion time. See the description of the

CKS bit for details.

2 CH3 1 R/W Channel Select 3

Used together with bits CH2 to CH0 in ADCSR to

select the analog input channel(s). See the

description of bits CH2 to CH0 for details.

1, 0 — All 1 — Reserved

These bits are always read as 1 and cannot be

modified.

Section 16 A/D Converter

Rev. 3.00 Mar 17, 2006 page 751 of 926

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• H8S/2678R Group

Bit Bit Name Initial Value R/W Description

6TRGS1

TRGS0 0

0R/W

R/W Timer Trigger Select 1 and 0

These bits select enabling or disabling of the start

of A/D conversion by a trigger signal.

00: A/D conversion start by external trigger is

disabled

01: A/D conversion start by external trigger (TPU)

is enabled

10: A/D conversion start by external trigger (TMR)

is enabled

11: A/D conversion start by external trigger pin

(ADTRG) is enabled

4SCANE

SCANS 0

0R/W

R/W Scan Mode

Selects single mode or scan mode as the A/D

conversion operating mode.

0x: Single mode

10: Scan mode. A/D conversion is performed

continuously for channels 1 to 4

11: Scan mode. A/D conversion is performed

continuously for channels 1 to 8.

2CKS1

CKS0 0

0R/W

R/W Clock Select 1 to 0

Sets the A/D conversion time.

Only set bits CKS1 and CKS0 while conversion is

stopped (ADST = 0).

00: A/D conversion time = 530 states (max)

01: A/D conversion time = 266 states (max)

10: A/D conversion time = 134 states (max)

11: A/D conversion time = 68 states (max)

1, 0 — All 0 — Reserved

These bits are always read as 0 and cannot be

modified.

Legend: X: Don’t care.

Section 16 A/D Converter

Rev. 3.00 Mar 17, 2006 page 752 of 926

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16.4 Operation

The A/D converter operates by successive approximation with 10-bit resolution. It has two

operating modes: single mode and scan mode. When changing the operating mode or analog input

channel, to prev ent incorrect operation, first clear the bit ADST to 0 in ADCSR to halt A/D

conversion. The ADST bit can be set at the same time as the operating mode or analog input

channel is changed.

16.4.1 Single Mode

In single mode, A/D conversion is to be performed only once on the specified single channel.

Operations are as follows.

1. A/D conversion is started when the ADST bit in ADCSR is set to 1, according to the software

or external trigger input.

2. When A/D conversion is completed, the result is transferred to the corresponding A/D data

3. On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at

this time, an ADI in ter rupt request is genera ted .

4. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when

conversion ends. When the ADST bit is cleared to 0 during A/D conversion, A/D conversion

stops and the A/D converter enters wait state.

16.4.2 Scan Mode

In scan mode, A/D conversion is to be performed sequentially on the specified channels:

maximum four channels or maximum eight channels (H8S/2678R Group). Operations are as

follows.

1. When the ADST bit in ADCSR is set to 1 by a software, TPU or external trigger input, A/D

conversion starts on the first channel in the group.

In the H8S/2678 Group, the A/D conversion starts on AN0 when CH3 and CH2 =10, AN4

when CH3 and CH2 = 11, or AN12 when CH3 and CH2 = 01.

In the H8S/2678R Group, the consecutive A/D conversion on maximum four channels

(SCANE and SCANS = 10) or on maximum eight channels (SCANE and SCANS = 11) can be

selected. When the consecutive A/D conversion is performed on the four channels, the A/D

conversion starts on AN0 when CH3 and CH2 =00, AN4 when CH3 and CH2 = 01, or AN12

when CH3 and CH2 = 11. When the consecutive A/D conversion is performed on the eight

channels, the A/D conversion starts on AN0 when SH3 and SH2 =00.

Section 16 A/D Converter

Rev. 3.00 Mar 17, 2006 page 753 of 926

REJ09B0283-0300

2. When A/D conversion for each channel is completed, the result is sequentially transferred to

the corresponding A/D data register to each channel.

3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1.

If the ADIE bit is set to 1 at this time, an ADI interrupt is requested. Conv e r sio n of the first

channel in the group starts again.

4. The ADST bit is not cleared automatically, and steps [2] to [3] are repeated as long as the

ADST bit remains set to 1. When th e ADST b it is cleared to 0, A/D conversion stops and the

A/D converter enters wait state. If the ADST bit is later set to 1, A/D conversion starts again

from the first channel in the group.

16.4.3 Input Sampling and A/D Conversion Time

The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog

input when A/D conversion start delay time (tD) passes after the ADST bit is set to 1, then starts

conversion. Figure 16.2 shows the A/D conversion timing. Table 16.3 indicates the A/D

conversion time.

As indicated in figure 16.2, the A/D conversion time (tCONV) includes tD and the input sampling time

(tSPL). The length of tD varies depending on the timing of the write access to ADCSR. The total

conversion time therefore varies within the ranges indicated in tables 16 .3.

In scan mode, the values given in tables 16.3 apply to the first conversion time. The values given

in tables 16.4 apply to the second and subsequent conversions. The conversion time must be

within the ranges indicated in the descriptions, A/D Conversion Characteristics in section 24,

Electrical Characteristics. Therefore the CKS and CKS1 bits (H8S/2678 Group) or CKS1 and

CKS0 bits (H8S/2678R Group) must be set to satisfy this condition.

Section 16 A/D Converter

Rev. 3.00 Mar 17, 2006 page 754 of 926

REJ09B0283-0300

(1)

(2)

SPL

CONV

Address

Write signal

Input sampling

timing

ADF

Legend:

(1) : ADCSR write cycle

(2) : ADCSR address

: A/D conversion start delay time

SPL

: Input sampling time

CONV

: A/D conversion time

Figure 16.2 A/D Conversion Timing

Table 16.3 A/D Conversion Time (Single Mode)

• H8S/2678 Group

CKS1 = 0 CKS1 = 1

CKS = 0 CKS = 1 CKS = 0 CKS = 1

Item Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max

A/D conversion

start delay time tD18 —33 4 —510—17 6 — 9

Input sampling

time tSPL —127 ——15 ——63 ——31 —

A/D conversion

time tCONV 515 —530 67 —68 259 —266 131 —134

Note: Values in the table are the number of states.

Section 16 A/D Converter

Rev. 3.00 Mar 17, 2006 page 755 of 926

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• H8S/2678R Group

CKS1 = 0 CKS1 = 1

CKS0 = 0 CKS0 = 1 CKS0 = 0 CKS0 = 1

Item Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max

A/D conversion

start delay time tD18 —33 10 —17 6 —94— 5

Input sampling

time tSPL —127 ——63 ——31 ——15 —

A/D conversion

time tCONV 515 —530 259 —266 131 —134 67 —68

Note: Values in the table are the number of states.

Table 16.4 A/D Conversion Time (Scan Mode)

• H8S/2678 Group

CKS1 CKS Conversion Time (State)

0 512 (Fixed)

1 64 (Fixed)

0 256 (Fixed)1

1 128 (Fixed)

• H8S/2678R Group

CKS1 CKS0 Conversion Time (State)

0 512 (Fixed)

1 256 (Fixed)

0 128 (Fixed)1

1 64 (Fixed)

Section 16 A/D Converter

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16.4.4 External Trig ger Input Timing

A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to 11 in

ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets

the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan

modes, are the same as when the bit ADST has been set to 1 by software. Figure 16.3 shows the

timing.

ADTRG

Internal trigger signal

ADST A/D conversion

Figure 16.3 External Trigger Input Timing

16.5 Interrupt Source

The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion.

Setting the ADIE b it to 1 enables an ADI interru pt requests while the b it ADF in ADCSR is set to

1 after A/D conversion is completed. The DTC or DMAC can be activated by an ADI interrupt.

Having the converted data read by the DTC or DMAC in response to an ADI interrupt enables

continuous conversion to be achieved without imposing a load on software.

Table 16.5 A/D Converter Interrupt Source

Name Interrupt Source Inte rrupt Flag DTC Activation DMAC Activation

ADI End of conversion ADF Possible Possible

Section 16 A/D Converter

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16.6 A/D Conversion Accuracy Definitions

This LSI’s A/D conversion accuracy definitions are given below.

• Resolution

The number of A/D converter digital output codes

• Quantization error

The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 16.4).

• Offset error

The deviation of the analog input voltage value from the ideal A/D conversion characteristic

when the digital output changes from the minimum voltage value B'0000000000 (H'000) to

B'0000000001 (H'001) (see figure 16.5).

• Full-scale error

The deviation of the analog input voltage value from the ideal A/D conversion characteristic

when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see

figure 16.5).

• Nonlinearity er ror

The error with respect to the ideal A/D conversion characteristic between the zero voltage and

the full-scale voltage. Does not include the offset error, full-scale error, or quantization error

(see figure 16.5).

• Absolute pr ecision

The deviation between the digital value and the analog input value. Includes the offset error,

full-scale error, quantization error, and nonlinearity error.

Section 16 A/D Converter

Rev. 3.00 Mar 17, 2006 page 758 of 926

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111

110

101

100

011

010

001

000 1

1024 2

1024 1022

1024 1023

1024 FS

Quantization error

Digital output

Ideal A/D conversion

characteristic

Analog

input voltage

Figure 16.4 A/D Conversion Accuracy Definitions

Digital output

Ideal A/D conversion

characteristic

Nonlinearity

error

Analog

input voltage

Offset error

Actual A/D conversion

characteristic

Full-scale error

Figure 16.5 A/D Conversion Accuracy Definitions

Section 16 A/D Converter

Rev. 3.00 Mar 17, 2006 page 759 of 926

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16.7 Usage Notes

16.7.1 Module Stop Mode Setting

Operation of the A/D converter can be disabled or en abled using the module stop control register.

The initial setting is fo r operation of the A/D converter to be halted. Register access is enabled by

clearing module stop mode. For details, refer to section 22, Power-Down Modes.

16.7.2 Permissible Signal Source Impedance

This LSI’s analog input is designed so that conversion precision is guaranteed for an input signal

for which the signal source impedance is 10 kΩ or less. This specification is provided to enable

the A/D converter’s sample-and-hold circuit input capacitance to be charged within the sampling

time; if the sensor output impedance exceeds 10 kΩ, charging may be insufficient and it may not

be possible to guarantee the A/D conversion accuracy. However, if a large capacitance is provided

externally for conv e r sion in single mode, the input load will essentially comprise only the internal

input resistance of 10 kΩ, and the signal source impedance is ignored. However, since a low-pass

filter effect is ob tained in this case, it may not be possible to follow an analog signal with a large

differential coefficient (e.g., 5 mV/µs or greater) (see figure 16.6). When converting a high-speed

analog signal or conversion in scan mode, a low-impedance buffer should be inserted.

Equivalent circuit of A/D converter

This LSI

20 pF

Cin =

15 pF

10 kΩ

Up to 10 kΩ

Low-pass

filter

C to 0.1 µF

Sensor output

impedance

Sensor input

Figure 16.6 Example o f Analog Input Circuit

Section 16 A/D Converter

Rev. 3.00 Mar 17, 2006 page 760 of 926

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16.7.3 Influences on Absolute Precision

Adding capacitance results in coupling with GND, and therefore noise in GND may adversely

affect absolute precision. Be sure to make the connection to an electrically stable GND such as

AVss.

Care is also required to in sure that filter circuits d o not communicate with digital signals on th e

mounting board, so acting as antennas.

16.7.4 Setting Range of Analog P ower Supply and Other P ins

If conditions sho wn below are not met, the reliability of th e device m ay be adver sely affected.

• Analog input voltage range

The voltage applied to analog input pin ANn during A/D conversion should be in the range

AVss ≤ VAn ≤ Vref.

• Relation between AVcc, AVss and Vcc, Vss

As the relationship between AVcc, AVss and Vcc, Vss, set AVcc ≥ Vcc and AVss = Vss. If

the A/D converter is not used, the AVcc and AVss pins must not be left open.

• Vref setting range

The reference voltage at the Vref pin should be set in the range Vref ≤ AVcc.

16.7.5 Notes on Board Design

In board design, digital circuitry and analog circuitry should be as mutually isolated as possible,

and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close

proximity should be avoided as far as possible. Failure to do so may result in incorrect operation

of the analog circuitry due to inductance, adversely affecting A/D conversion values.

Also, digital circu itry must be isolated from the analog input sign als ( AN0 to AN7 and AN12 to

AN15), analog reference power supply (Vref), and analog power supply (AVcc) by the analog

ground (AVss). Also, the analog ground (AVss) should be connected at one point to a stable

digital ground (Vss) on the board.

Section 16 A/D Converter

Rev. 3.00 Mar 17, 2006 page 761 of 926

REJ09B0283-0300

16.7.6 Notes on Noise Countermeasures

A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive

surge at the analog input pins (AN0 to AN7 and AN12 to AN15) should be connected between

AVcc and AVss as shown in figure 16.7. Also, the bypass capacitors connected to AVcc and the

filter capacitor connected to AN0 to AN7 and AN12 to AN15 must be conn ected to AVss.

If a filter capacitor is connected, the input currents at the analog input pins (AN0 to AN7 and

AN12 to AN15) are averaged, and so an error may arise. Also, when A/D conversion is performed

frequently, as in scan mode, if the current charged and discharged by the capacitance of the

sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance

(Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required

when deciding the circuit constants.

*1*1

Vref

AN0 to AN7, AN12 to AN15

Notes: Values are reference values.

2. Rin: Input impedance

Rin*2100Ω

0.1 µF

0.01 µF10 µF

Figure 16.7 Example o f Analog Input Pr otection Circuit

Section 16 A/D Converter

Rev. 3.00 Mar 17, 2006 page 762 of 926

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Table 16.6 Analog Pin Specificat ions

Item Min Max Unit

Analog input capacitance —20 pF

Permissible signal source impedance —10 kΩ

20 pF

To A/D

converter

AN0 to AN7,

AN12 to AN15

10 kΩ

Note: Values are reference values.

Figure 16.8 Analog Input Pin Equiva lent Circuit

Section 17 D/A Converter

Rev. 3.00 Mar 17, 2006 page 763 of 926

REJ09B0283-0300

Section 17 D/A Converter

17.1 Features

D/A converter features are listed below.

• 8-bit re solution

• Four output channels

• Maximum conversion time of 10 µs (with 20-pF load)

• Output voltage of 0 V to Vref

• D/A output hold function in software standby mode

• Setting the module stop mode

DAC0001A_000020020400

Section 17 D/A Converter

Rev. 3.00 Mar 17, 2006 page 764 of 926

REJ09B0283-0300

Module data bus Internal data bus

Vref

DA3

DA2

DA1

DA0

8-bit

D/A

Control circuit

DADR0

DADR1

DADR2

DADR3

DACR01

DACR23

Bus interface

Legend:

DADR0: D/A data register 0

DADR1: D/A data register 1

DADR2: D/A data register 2

DADR3: D/A data register 3

DACR01: D/A control register 01

DACR23: D/A control register 23

Figure 17.1 Block Diagram of D/A Converter

Section 17 D/A Converter

Rev. 3.00 Mar 17, 2006 page 765 of 926

REJ09B0283-0300

17.2 Input/Output Pins

Table 17.1 shows the pin configuration of th e D/A converter.

Table 17.1 Pin Configuratio n

Pin Name Symbol I/O Function

Analog power pin AVCC Input Analog power

Analog ground pin AVSS Input Analog ground

Reference volt age pin Vref Input Reference voltage of D/A convert er

Analog output pin 0 DA0 Output Channel 0 analog output

Analog output pin 1 DA1 Output Channel 1 analog output

Analog output pin 2 DA2 Output Channel 2 analog output

Analog output pin 3 DA3 Output Channel 3 analog output

17.3 Register Descriptions

The D/A converter has the following registers.

• D/A data register 0 (DADR0)

• D/A data register 1 (DADR1)

• D/A data register 2 (DADR2)

• D/A data register 3 (DADR3)

• D/A control register 01 (DACR01)

• D/A control register 23 (DACR23)

17.3.1 D/A Data Reg isters 0 to 3 (DADR0 to DADR3)

DADR0 to DADR3 are 8-bit readable/writable registers that store data for conversion.

Whenever output is enabled , the values in DADR are converted and output to the analog output

pins.

Section 17 D/A Converter

Rev. 3.00 Mar 17, 2006 page 766 of 926

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17.3.2 D /A Co ntrol Registers 01 and 23 (DACR01, DACR23)

DACR01 and DACR23 control the operation of the D/A converter.

DACR01

Bit Bit Name Initial Value R/W Description

7 DAOE1 0 R/W D/A Output Enable 1

Controls D/A conversion and analog output.

0: Analog output (DA1) is disabled

1: Channel 1 D/A conversion is enabled; analog

output (DA1) is enabled

6 DAOE0 0 R/W D/A Output Enable 0

Controls D/A conversion and analog output.

0: Analog output (DA0) is disabled

1: Channel 0 D/A conversion is enabled; analog

output (DA0) is enabled

5 DAE 0 R/W D/A Enable

Used together with the DAOE0 and DAOE1 bits to

control D/A conversion. When the DAE bit is

cleared to 0, channel 0 and 1 D/A conversions are

controll ed inde pend ent ly. When the DAE bit is set

to 1, channel 0 and 1 D/A conversions are

controlled together.

Output of conversion results is always controlled

independently by the DAOE0 and DAOE1 bits. For

details, see table 17.2.

— All 1 — Reserved

These bits are always read as 1 and cannot be

modified.

Section 17 D/A Converter

Rev. 3.00 Mar 17, 2006 page 767 of 926

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Table 17.2 Control of D/A Conversion

Bit 5

DAE Bit 7

DAOE1 Bit 6

DAOE0 Description

0 0 0 D/A conversion disabled

1 Channel 0 D/A conversion enabled, channel1 D/A conversion

disabled

1 0 Channel 1 D/A conversion enabled, channel0 D/A conversion

disabled

1 Channel 0 and 1 D/A conversions enabled

1 0 0 D/A conversion disabled

1 Channel 0 and 1 D/A conversions enabled

Section 17 D/A Converter

Rev. 3.00 Mar 17, 2006 page 768 of 926

REJ09B0283-0300

DACR23

Bit Bit Name Initial Value R/W Description

7 DAOE3 0 R/W D/A Output Enable 3

Controls D/A conversion and analog output.

0: Analog output (DA3) is disabled

1: Channel 3 D/A conversion is enabled; analog

output (DA3) is enabled

6 DAOE2 0 R/W D/A Output Enable 2

Controls D/A conversion and analog output.

0: Analog output (DA2) is disabled

1: Channel 2 D/A conversion is enabled; analog

output (DA2) is enabled

5 DAE 0 R/W D/A Enable

Used together with the DAOE2 and DAOE3 bits to

control D/A conversion. When the DAE bit is

cleared to 0, channel 2 and 3 D/A conversions are

controll ed inde pend ent ly. When the DAE bit is set

to 1, channel 2 and 3 D/A conversions are

controlled together.

Output of conversion results is always controlled

independently by the DAOE2 and DAOE3 bits. For

details, see table 17.3.

— All 1 — Reserved

These bits are always read as 1 and cannot be

modified.

Section 17 D/A Converter

Rev. 3.00 Mar 17, 2006 page 769 of 926

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Table 17.3 Control of D/A Conversion

Bit 5

DAE Bit 7

DAOE3 Bit 6

DAOE2 Description

0 0 0 D/A conversion disabled

1 Channel 2 D/A conversion enabled, channel3 D/A conversion

disabled

1 0 Channel 3 D/A conversion enabled, channel2 D/A conversion

disabled

1 Channel 2 and 3 D/A conversions enabled

1 0 0 D/A conversion disabled

1 Channel 2 and 3 D/A conversions enabled

17.4 Operation

The D/A converter includes D/A conversion circuits for four channels, each of which can operate

independently.

When DAOE bit in DACR01 or DACR23 is set to 1, D/A conversion is enabled and the

conversion result is output.

The operation example concerns D/A conversion on channel 0. Figu re 17.2 shows the timing of

this oper a tion.

[1] Write the conversion data to DADR0.

[2] Set the DAOE0 bit in DACR01 to 1. D/A conversion is started. The conversion result is output

from the analog output pin DA0 after the conversion time tDCONV has elapsed. The conversion

result is continued to output until DADR0 is written to again or the DAOE0 bit is cleared to 0.

The output value is expressed by the following formula:

256

DADR contents × Vre

[3] If DADR0 is written to again, the conversion is immediately started. The conversion result is

output after the conversion time tDCONV has elapsed.

[4] If the DAOE0 bit is cleared to 0, analog output is disabled.

Section 17 D/A Converter

Rev. 3.00 Mar 17, 2006 page 770 of 926

REJ09B0283-0300

Conversion data 1

Conversion

result 1

High-impedance state

DCONV

DADR0

write cycle

DA0

DAOE0

DADR0

Address

DACR01

write cycle

Conversion data 2

Conversion

result 2

DCONV

Legend:

DCONV

: D/A conversion time

DADR0

write cycle DACR01

write cycle

Figure 17.2 Example of D/A Converter Operation

17.5 Usage Notes

17.5.1 Setting for Module Sto p Mode

It is possible to enable/disable the D/A converter operation using the module stop control register,

the D/A converter does not operate by the initial value of the register. The register can be accessed

by releasing the module stop mode. For details, see section 22, Power-Down Modes.

17.5.2 D/A Output Hold Function in Sof t ware Standby Mo de

If D/A conversion is enabled and this LSI enters software standby mode, D/A output is held and

analog power supply current remains at the same level during D/A conversion. When the analog

power supply current is required to go low in software standby mode, bits DAOE0 to DAOE3 and

DAE should be cleared to 0, and D/A output should be disabled.

Section 18 RAM

Rev. 3.00 Mar 17, 2006 page 771 of 926

REJ09B0283-0300

Section 18 RAM

This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit

data bus, enabling one-state access by the CPU to both byte data and word data.

The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control

System Control Register (SYSCR).

Product Type Name ROM Type RAM

Capacitance RAM Address

HD64F2676 Flash memory version 8 kbytes H'FFA000 to H'FFBFFF

HD6432676 Masked ROM version 8 kbytes H'FFA000 to H'FFBFFF

HD6432675 8 kbytes H'FFA000 to H'FFBFFF

HD6432673 8 kbytes H'FFA000 to H'FFBFFF

H8S/2678

Group

HD6412670 ROMless version 8 kbytes H'FFA000 to H'FFBFFF

H8S/2678R

Group HD6412674R ROMless version 32 kbytes H'FF4000 to H'FFBFFF

Section 18 RAM

Rev. 3.00 Mar 17, 2006 page 772 of 926

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Section 19 Fl ash Memory (F-ZTAT Version)

Rev. 3.00 Mar 17, 2006 page 773 of 926

REJ09B0283-0300

Section 19 Flash Memory (F-ZTAT Version)

The features of the flash memory included in the flash memory version are summarized below.

The block diagram of the flash memory is shown in figure 19.1.

19.1 Features

• Size

Product Classification ROM Size ROM Address

H8S/2678 Group HD64F2676 256 kbytes H'000000 to H'03F FFF

(Modes 3, 4, 7, 10, and 11)

H'100000 to H'13FFFF

(Modes 5, 6, 13, and 14)

• Programming/erase methods

The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units.

The flash memory of 384 kbytes is configured as follows: 64 kbytes × 5 blocks, 32 kbytes × 1

block, and 4 kbytes × 8 blocks. The 256-kbyte flash memory is configured as follows: 64

kbytes × 3 blocks, 32 kbytes × 1 block, and 4 kbytes × 8 blocks. To erase the entire flash

memory, each block must be erased in turn.

• Reprogram ming capability

The flash memory can be reprogrammed up to 100 times.

• Two on-board programming modes

Boot mode

User program mode

On-board programming/erasing can be done in boot mode in which the on-chip boot program

is started for erase or programming of the entire flash memory. In normal user program mode,

individual blocks can be erased or programmed.

• Programmer mode

Flash memory can be programmed/erased in programmer mode, using a PROM programmer,

as well as in on-board programming mode.

• Automatic bit r ate adjustment

With data transf er in boot mode, the bit rate of this LSI can b e autom a tically adjusted to match

the transfer bit rate of the host.

• Flash memory emulation by RAM

Part of the RAM area can be overlapped onto flash memory, to emulate flash memory updates

in real time.

ROMF251A_000020020400

Section 19 Fl ash Memory (F-ZTAT Version)

Rev. 3.00 Mar 17, 2006 page 774 of 926

REJ09B0283-0300

• Programming/erasing protection

There are three protect modes, hardware, software, and error protect, which allow protected

status to be designated for flash memory program/erase operations.

Module bus

Bus interface/controller

Flash memory

Operating

mode

EBR1

Internal address bus

Internal data bus (16 bits)

FWE pin*

Mode pins

EBR2

SYSCR

FLMCR2

FLMCR1

RAMER

Legend:

FLMCR1: Flash memory control register 1

FLMCR2: Flash memory control register 2

EBR1: Erase block register 1

EBR2: Erase block register 2

RAMER: RAM emulation register

SYSCR: System control register

Note: * Only in H8S/2678 Group.

Figure 19.1 Block Diagram of Flash Memory

19.2 Mode Transitions

When the mode pins and the FWE pin* are set in the reset state and a reset-start is executed, this

LSI enters an operating mode as shown in figure 19.2. In user mode, flash memory can be read but

not programmed or erased.

The boot, user program and programmer modes are provided as modes to write and erase the flash

memory.

Section 19 Fl ash Memory (F-ZTAT Version)

Rev. 3.00 Mar 17, 2006 page 775 of 926

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The differences between boot mode and user program mode are shown in table 19.1. Figure 19.3

shows boot mode. Figure 19.4 shows user program mode.

Note: * Only in th e H8S/2678 Group.

Boot mode

On-board programming mode

User

program mode

User mode

(on-chip ROM

enabled)

Reset state

Programmer

mode

RES = 0

FWE = 1, MD2 = 1,

SWE = 1*1

SWE = 1*2

FWE = 0, MD2 = 1,

SWE = 0*1

SWE = 0*2

Notes: Only make a transition between user mode and user program mode when the CPU is

not accessing the flash memory.

1. Only in H8S/2678 Group.

2. Only in H8S/2678R Group.

RES = 0

MD2 = 1, FWE = 0*

MD2 = 1*

MD1 = 1, MD2 = 0, FWE = 1*1

MD0 = 1, MD1 = 1, MD2 = 0*2

MD0 = 0, MD1 = 0,

MD2 = 0, P50 = 0,

P51 = 0, P52 = 1

Figure 19.2 Flash Memory State Transitions

Table 19.1 Differences between Boot Mode and User Program Mode

Boot Mode User Program Mode

Total erase Yes Yes

Block erase No Yes

Programming contr ol program *Program/program-verify Erase/erase-verify/program/

program-verify emulation

Note: *To be provided by the user, in accordance with the recommended algorithm.

Section 19 Fl ash Memory (F-ZTAT Version)

Rev. 3.00 Mar 17, 2006 page 776 of 926

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Flash memory

This LSI

RAM

Host

Programming control

program

SCI

Application program

(old version)

New application

program

Flash memory

This LSI

RAM

Host

SCI

Application program

(old version)

Boot program area

New application

program

Flash memory

This LSI

RAM

Host

SCI

Flash memory

prewrite-erase

Boot program

New application

program

Flash memory

This LSI

Program execution state

RAM

Host

SCI

New application

program

Boot program

Programming control

program

1. Initial state

The old program version or data remains written

in the flash memory. The user should prepare the

programming control program and new

application program beforehand in the host.

2. Programming control program transfer

When boot mode is entered, the boot program in

the chip (originally incorporated in the chip) is

started and the programming control program in

the host is transferred to RAM via SCI

communication. The boot program required for

flash memory erasing is automatically transferred

to the RAM boot program area.

3. Flash memory initialization

The erase program in the boot program area (in

RAM) is executed, and the flash memory is

initialized (to H'FF). In boot mode, entire flash

memory erasure is performed, without regard to

blocks.

4. Writing new application program

The programming control program transferred

from the host to RAM is executed, and the new

application program in the host is written into the

flash memory.

Programming control

program

Boot programBoot program

Boot program area Boot program area

Programming control

program

Figure 19.3 Boot Mode

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Flash memory

This LSI

RAM

Host

Programming/

erase control program

SCI

Boot program

New application

program

Flash memory

This LSI

RAM

Host

SCI

New application

program

Flash memory

This LSI

RAM

Host

SCI

Flash memory

erase

Boot program

New application

program

Flash memory

This LSI

Program execution state

RAM

Host

SCI

Boot program

FWE assessment

program

Application program

(old version)

New application

program

1. Initial state

(1) The FWE assessment program that confirms

that user program mode is entered, and (2) the

program that will transfer the programming/ erase

control program to on-chip RAM should be

written into the flash memory by the user

beforehand. (3) The programming/erase control

program should be prepared in the host or in the

flash memory.

2. Programming/erase control program transfer

When user program mode is entered, user

software confirms this fact, executes the transfer

program in the flash memory, and transfers the

programming/erase control program to RAM.

3. Flash memory initialization

The programming/erase program in RAM is

executed, and the flash memory is initialized (to

H'FF). Erasing can be performed in block units,

but not in byte units.

4. Writing new application program

Next, the new application program in the host is

written into the erased flash memory blocks. Do

not write to unerased blocks.

Programming/

erase control program

Programming/

erase control program

Programming/

erase control program

Transfer program

Application program

(old version)

Transfer program

FWE assessment

program

FWE assessment

program

Transfer program

FWE assessment

program

Transfer program

Note: The FWE assessment program is not available in the H8S/2678R Group.

Figure 19.4 User Program Mode

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19.3 Block Configuration

Figure 19.5 shows the block configuration of 384-kbyte flash memory and figure 19.6 shows that

of 256-kbyte flash memory. The thick lines indicate erasing units, the narrow lines indicate

programming units, and the values are addresses. The 384-kbyte flash memory is divided into 64

kbytes (5 blocks), 32 kbytes (1 block), and 4 kbytes (8 blocks). The 256-kbyte flash memory is

divided into 64 kbytes (3 blocks), 32 kbytes (1 block), and 4 kbytes (8 blocks). Erasing is

performed in th ese divided units. Programming is performed in 128-byte units starting from an

address whose lower eight bits are H'00 or H'80.

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EB0

Erase unit

4 kbytes

EB1

Erase unit

4 kbytes

EB2

Erase unit

4 kbytes

EB3

Erase unit

4 kbytes

EB4

Erase unit

4 kbytes

EB7

Erase unit

4 kbytes

EB8

Erase unit

32 kbytes

EB9

Erase unit

64 kbytes

EB10

Erase unit

64 kbytes

EB11

Erase unit

64 kbytes

H'000000 H'000001 H'000002 H'00007F

H'000FFF

H'00107F

H'00207F

H'00307F

H'00407F

H'00707F

H'007FFF

H'001FFF

H'002FFF

H'003FFF

H'03FFFF

H'00807F

H'00FFFF

H'01007F

H'01FFFF

H'02007F

H'02FFFF

H'03007F

H'001000 H'001001 H'001002

H'002000 H'002001 H'002002

H'003000 H'003001 H'003002

H'004000 H'004001 H'004002

H'007000 H'007001 H'007002

H'008000 H'008001 H'008002

H'010000 H'010001 H'010002

H'020000 H'020001 H'020002

H'030000 H'030001 H'030002

Programming unit: 128 bytes

EB12

Erase unit

64 kbytes

EB13

Erase unit

64 kbytes

H'05FFFF

H'04007F

H'04FFFF

H'05007F

H'040000 H'040001 H'040002

H'050000 H'050001 H'050002

Programming unit: 128 bytes

Note: Addresses H'100000 to H'15FFFF are allocated in modes 5 and 6.

Figure 19.5 384-kbyte Flash Memory Block Configuration (Modes 3, 4, and 7)

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EB0

Erase unit

4 kbytes

EB1

Erase unit

4 kbytes

EB2

Erase unit

4 kbytes

EB3

Erase unit

4 kbytes

EB4

Erase unit

4 kbytes

EB7

Erase unit

4 kbytes

EB8

Erase unit

32 kbytes

EB9

Erase unit

64 kbytes

EB10

Erase unit

64 kbytes

EB11

Erase unit

64 kbytes

H'000000 H'000001 H'000002 H'00007F

H'000FFF

H'00107F

H'00207F

H'00307F

H'00407F

H'00707F

H'007FFF

H'001FFF

H'002FFF

H'003FFF

H'03FFFF

H'00807F

H'00FFFF

H'01007F

H'01FFFF

H'02007F

H'02FFFF

H'03007F

H'001000 H'001001 H'001002

H'002000 H'002001 H'002002

H'003000 H'003001 H'003002

H'004000 H'004001 H'004002

H'007000 H'007001 H'007002

H'008000 H'008001 H'008002

H'010000 H'010001 H'010002

H'020000 H'020001 H'020002

H'030000 H'030001 H'030002

Programming unit: 128 bytes

Note: Addresses H'100000 to H'13FFFF are allocated in modes 5, 6, 13, and 14.

Figure 19.6 256-kbyte Flash Memory Block Configuration (Modes 4, 7, 10, and 11)

Section 19 Fl ash Memory (F-ZTAT Version)

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19.4 Input/Output Pins

Table 19.2 shows the pin configuration of the flash memory.

Table 19.2 Pin Configuratio n

Pin Name I/O Function

RES Input Reset

FWE*Input Flash program/erase protection by hardware

MD2 Input Sets this LSI’s operating mode

MD1 Input Sets this LSI’s operating mode

MD0 Input Sets this LSI’s operating mode

P52 Input Sets operating mode in programmer mode

P51 Input Sets operating mode in programmer mode

P50 Input Sets operating mode in programmer mode

TxD1 Output Serial transmit data output

RxD1 Input Serial receive data input

Note: *Only in H8S/2678 Group.

19.5 Register Descriptions

The flash memory has the following registers. For details on the system control register, refer to

section 3.2.2, System Control Register (SYSCR).

• Flash memory control register 1 (FLMCR1)

• Flash memory control register 2 (FLMCR2)

• Erase block register 1 (EBR1)

• Erase block register 2 (EBR2)

• RAM emulation register (RAMER)

19.5.1 Flash Memory Control Register 1 (FLMCR1)

FLMCR1 is a register that makes the flash memory transit to program mode, program-verify

mode, erase mode, or erase-verify mode. For details on register setting, refer to section 19.8, Flash

Memory Programming/Erasing.

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Bit Bit Name Initial Value R/W Description

7 FWE 0/1 R Flash Write Enable

Reflects the input level at the FWE pin. It is set to 1

when a high level is input to the FWE pin, and

cleared to 0 when a low level is input. When this bit

is cleared to 0, the flash memory transits to the

hardware protection state.

Note: In the H8S/2678R Group, this bit is

reserved. This bit is always read as 0 in

modes 1 and 2. This bit is always read as 1

in modes 3 to 7. The initial value should not

be changed.

6 SWE 0 R/W Software Write Enable

When this bit is set to 1, flash memory

programming/erasing is enabled. When this bit is

cleared to 0, other FLMCR1 register bits and all

EBR1 and EBR2 bits cannot be set.

5 ESU 0 R/W Erase Setup

When this bit is set to 1 while FWE = 1* and SWE

= 1, the flash memory transits to the erase setup

state. When it is cleared to 0, the erase setup state

is cancelled.

4 PSU 0 R/W Program Setup

When this bit is set to 1 while FWE = 1* and SW E

= 1, the flash memory transits to the program setup

state. When it is cleared to 0, the program setup

state is cancelled.

3 EV 0 R/W Erase-Verify

When this bit is set to 1 while FWE = 1* and SW E

= 1, the flash memory transits to erase-verify

mode. When it is cleared to 0, erase-verify mode is

cancelled.

2 PV 0 R/W Program-Verify

When this bit is set to 1 while FWE = 1* and SW E

= 1, the flash memory transits to program-verify

mode. When it is cleared to 0, program-verify

mode is cancelled.

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Bit Bit Name Initial Value R/W Description

1E 0 R/WErase

When this bit is set to 1 while FWE = 1*, SWE = 1,

and ESU = 1, the flash memory transits to erase

mode. When it is cleared to 0, erase mode is

cancelled.

0 P 0 R/W Program

When this bit is set to 1 while FWE = 1*, SWE = 1,

and PSU = 1, the flash memory transits to program

mode. When it is cleared to 0, program mode is

cancelled.

Note: *Only in H8S/2678 Group.

19.5.2 Flash Memory Control Register 2 (FLMCR2)

FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a

read-only register, and should not be written to. When the on-chip flash memory is disabled, the

contents of FLMCR2 are always read as H'00.

Bit Bit Name Initial Value R/W Description

7 FLER 0 R Indicates that an error has occurred during an

operation on flash memory (programming or

erasing). When FLER is set to 1, flash memory

goes to the error-protection state.

See 19.9.3 Error Protection, for details.

— All 0 R Reserved

These bits always read as 0.

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19.5.3 Erase Block Register 1 (EBR1)

EBR1 specifies the flash memory er ase ar ea block. EBR1 is initialized to H'00 when the SWE bit

in FLMCR1 is 0. Set only one bit in EBR1 and EBR2 together (do not set more than one bit at the

same time). Setting more than one bit will au tomatically clear all EBR1 an d EBR2 bits to 0. For

details, see table 19.3, Erase Blocks.

Bit Bit Name Initial Value R/W Description

7 EB7 0 R/W When this bit is set to 1, 4 kbytes of EB7 are to be

erased.

6 EB6 0 R/W When this bit is set to 1, 4 kbytes of EB6 are to be

erased.

5 EB5 0 R/W When this bit is set to 1, 4 kbytes of EB5 are to be

erased.

4 EB4 0 R/W When this bit is set to 1, 4 kbytes of EB4 are to be

erased.

3 EB3 0 R/W When this bit is set to 1, 4 kbytes of EB3 is to be

erased.

2 EB2 0 R/W When this bit is set to 1, 4 kbytes of EB2 is to be

erased.

1 EB1 0 R/W When this bit is set to 1, 4 kbytes of EB1 is to be

erased.

0 EB0 0 R/W When this bit is set to 1, 4 kbytes of EB0 is to be

erased.

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19.5.4 Erase Block Register 2 (EBR2)

EBR2 specifies the flash memory er ase ar ea block. EBR2 is initialized to H'00 when the SWE bit

in FLMCR1 is 0. Set only one bit in EBR2 and EBR1 together (do not set more than one bit at the

same time). Setting more than one bit will au tomatically clear all EBR1 an d EBR2 bits to 0. For

details, see table 19.3, Erase Blocks.

Bit Bit Name Initial Value R/W Description

7, 6 — All 0 R/W Reserved

The initial value shou ld not be changed.

5 EB13 0 R/W When this bit is set to 1, 64 kbytes of EB13 are to

be erased.

Note: In the H8S/2678 Group, this bit is reserved.

The initial value shou ld not be chan ged.

4 EB12 0 R/W When this bit is set to 1, 64 kbytes of EB12 are to

be erased.

Note: In the H8S/2678 Group, this bit is reserved.

The initial value shou ld not be chan ged.

3 EB11 0 R/W When this bit is set to 1, 64 kbytes of EB11 are to

be erased.

2 EB10 0 R/W When this bit is set to 1, 64 kbytes of EB10 are to

be erased.

1 EB9 0 R/W When this bit is set to 1, 64 kbytes of EB9 are to be

erased.

0 EB8 0 R/W When this bit is set to 1, 32 kbytes of EB8 are to be

erased.

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Table 19.3 Erase Blocks

Address

Block (Size) H8S/ 2678R Group: Modes 3, 4, and 7

H8S/2678 Group: Modes 4, 7, 10, and 11 H8S/2678R Group: Modes 5 and 6

H8S/2678 Group: Modes 5, 6, 13, and 14

EB0 (4 kbytes) H'000000 to H'000FFF H'100000 to H'100FFF

EB1 (4 kbytes) H'001000 to H'001FFF H'101000 to H'101FFF

EB2 (4 kbytes) H'002000 to H'002FFF H'102000 to H'102FFF

EB3 (4 kbytes) H'003000 to H'003FFF H'103000 to H'103FFF

EB4 (4 kbytes) H'004000 to H'004FFF H'104000 to H'104FFF

EB5 (4 kbytes) H'005000 to H'005FFF H'105000 to H'105FFF

EB6 (4 kbytes) H'006000 to H'006FFF H'106000 to H'106FFF

EB7 (4 kbytes) H'007000 to H'007FFF H'107000 to H'107FFF

EB8 (32 kbytes) H'008000 to H'00FFFF H'108000 to H'10FFFF

EB9 (64 kbytes) H'010000 to H'01FFFF H'110000 to H'11FFFF

EB10 (64 kbytes) H'020000 to H'02FFFF H' 120000 t o H'12FFFF

EB11 (64 kbytes) H'030000 to H'03FFFF H' 130000 t o H'13FFFF

EB12 (64 kbytes) H'040000 to H'04FFFF H' 140000 t o H'14FFFF

EB13 (64 kbytes) H'050000 to H'05FFFF H' 150000 t o H'15FFFF

Note: The erase blocks of the 384-kbyte flash memory are EB0 to EB13.

The erase blocks of the 256-kbyte flash memory are EB0 to EB11.

19.5.5 RAM Emulation Register (RAMER)

RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating

real-time flash memory programming. RAMER settings should be made in user mode or user

program mode. To ensure correct operation of the emulation function, the ROM for which RAM

emulation is performed should not be accessed immediately after this register has been modified.

Normal execution of an access immediately after register modification is not guaranteed.

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Bit Bit Name Initial Value R/W Description

7, 5 — All 0 R Reserved

These bits always read as 0.

4— 0 R/WReserved

The initial value shou ld not be chan ged.

3 RAMS 0 R/W RAM Select

Specifies selection or non-selection of flash

memory emulation in RAM. When RAMS = 1, the

flash memory is overlapped with part of RAM, and

all flash memory block are in the program/erase-

protect state. When this bit is cleared to 0, the

RAM emulation function is invalid.

RAM2

RAM1

RAM0

R/W

Flash Memory Area Selection

When the RAMS bit is set to 1, selects one of the

following flash memory areas to overlap the RAM

area. The areas correspond with 4-kbyte erase

blocks.

H8S/2678R Group: Modes 3, 4, and 7

H8S/2678 Group: Modes 4, 7, 10, and 11

000: H'000000 to H'000FFF (EB0)

001: H'001000 to H'001FFF (EB1)

010: H'002000 to H'002FFF (EB2)

011: H'003000 to H'003FFF (EB3)

100: H'004000 to H'004FFF (EB4)

101: H'005000 to H'005FFF (EB5)

110: H'006000 to H'006FFF (EB6)

111: H'007000 to H'007FFF (EB7)

H8S/2678R Group: Modes 5 and 6

H8S/2678 Group: Modes 5, 6, 13, and 14

000: H'100000 to H'100FFF (EB0)

001: H'101000 to H'101FFF (EB1)

010: H'102000 to H'102FFF (EB2)

011: H'103000 to H'103FFF (EB3)

100: H'104000 to H'104FFF (EB4)

101: H'105000 to H'105FFF (EB5)

110: H'106000 to H'106FFF (EB6)

111: H'107000 to H'107FFF (EB7)

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19.6 On-Board Programming Modes

In an on-board programming mode, programming, erasing, and verification for the on-chip flash

memory can be performed. There are two on-board programming modes: boot mode and user

program mode. Table 19.4 shows how to select boot mode. User program mode can be selected by

setting the control bits by software. For a diagram that shows mode transitions of flash memory,

see figure 19.2.

Table 19.4 Setting On-Board Programming Modes

• H8S/2678 Group

Mode Setting FWE MD2 MD1 MD0

Boot mode Expanded mode with on-chip

ROM enabled 1010

Single-chip activation expanded

mode with on-chip ROM enabled 1011

User program mode Expanded mode with on-chip ROM

enabled 1100

External ROM activation expanded

mode with on-chip ROM enabled*11101

External ROM activation expanded

mode with on-chip ROM enabled*21110

Single-chip activation expanded

mode with on-chip ROM enabled 1111

Notes: 1. The initial setting for the external bus width is 16 bits.

2. The initial setting for the external bus width is 8 bits

• H8S/2678R Group

Mode Setting MD2 MD1 MD0

Boot mode Single-chip activation expanded

mode with on-chip ROM enabled 011

Section 19 Fl ash Memory (F-ZTAT Version)

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19.6.1 Boot Mode

When this LSI enters boot mode, the embedded boot program is started. The boot program

transfers the programming control pro gram from the externally connected host to the on-chip

RAM via the SCI_1. When the flash memory is all erased, the programming control program is

executed.

Table 19.5 shows the boot mode operations between reset end and branching to the prog ramming

control program.

1. When the boot program is initiated, the SCI_1 should be set to asynchronous mode, the chip

measures the lo w- level period of async hro nous SCI communication data (H'00) transmitted

continuously f rom the host. The chip then calculates the bit rate of transmission f r om the host,

and adjusts the SCI_1 bit r ate to match that of the host. The transfer form at is 8-bit data, 1 stop

bit, and no parity. The reset should end with the RxD pin high. The RxD and TxD pins should

be pulled up on the board if necessary. After the reset ends, it takes approximately 100 states

before th e chip is r eady to measure the low-level period.

2. After matching the bit rates, the ch ip tran sm its one H'00 byte to the host to indicate the end of

bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has

been received normally, and transmit one H'55 byte to the chip. If reception could not be

performed normally, initiate boot mode again by a reset. Depending on the host’s transfer bit

rate and system clock frequency of this LSI, there will be a discrepancy between the bit rates

of the host and the chip. To operate the SCI properly, set the host’s transfer bit rate and system

clock frequen cy of this LSI within the ranges listed in tab le 1 9.6.

3. When boot mode is used, the flash memory programming control program must be prepared in

the host beforehand. Prepare a programming control program in accordance with the

description in section 19.8, Flash Memory Programming/Erasing.

4. Before branching to the programming control program, the chip terminates transfer op erations

by the SCI_1 (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value

remains set in BRR. Therefore, the programming contr ol program can still use it for tr ansfer of

program data or verify data with the host. The TxD pin is high. The contents of the CPU

general registers are undefined immediately after branching to the programming control

program. These r egisters m ust be initialized at the beginning of the programming control

program, since the stack pointer (SP), in par ticular, is used implicitly in su broutine calls, etc.

5. In boot mode, if flash memory contains data (all data is not 1), all blocks of flash memory are

erased. Boot mode is used for the initial progr amming in the on-board state or for a for cible

Section 19 Fl ash Memory (F-ZTAT Version)

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return when a program that is to be initiated in user program mode was accidentally erased and

could not be executed in user program mode.

Notes: 1. In boot mode, a part of the on-chip RAM area (H'FF8000 to H'FF87FF) is used by the

boot program. Addresses H'FF8800 to H'FFBFFF is the area to which the

programming control program is transferred from the host. The boot program area

cannot be used until the execution state in boot mode switches to the programming

control program.

2. Boot mode can be cleared by a reset. Release the reset by setting the MD pins, after

waiting at least 20 states since driving the reset pin low. Boot mode is also cleared

when the WDT overflow reset occurs.

3. Do not change the MD pin input levels in boot mode.

4. All interrupts are disabled during programming or erasing of the flash memory.

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Table 19.5 Boot Mode Operation

Communication Contents

Processing Contents

Host Operation LSI Operation

Processing Contents

Continuously transmits data H'00

at specified bit rate.

Branches to boot program at reset-start.

Boot program initiation

H'00, H'00 . . . H'00

H'00

H'55

Transmits data H'55 when data H'00

is received error-free.

H'AA reception

H'XX

Transmits number of bytes (N) of

programming control program to be

transferred as 2-byte data

(low-order byte following high-order

byte)

Transmits 1-byte of programming

control program (repeated for N times)

H'AA reception.

Upper bytes, lower bytes

Echoback

H'AA

Branches to programming control program

transferred to on-chip RAM and starts

execution.

Checks flash memory data, erases all flash

memory blocks in case of written data

existing, and transmits data H'AA to host.

(If erase could not be done, transmits data

H'FF to host and aborts operation.)

H'FF

Boot program

erase error

H'AA

Item

Boot mode initiation

• Measures low-level period of receive data H'00.

• Calculates bit rate and sets BRR in SCI_1.

• Transmits data H'00 to host as adjustment end

indication.

Transmits data H'AA to host when data H'55 is

received.

Bit rate adjustment

Echobacks the 2-byte data

received to host.

Echobacks received data to host and also

transfers it to RAM.

(repeated for N times)

Transfer of number of bytes of

programming control program

Flash memory erase

Section 19 Fl ash Memory (F-ZTAT Version)

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Table 19.6 Syste m Clock Frequencies f or which Auto matic Adjustment of LSI Bit Rate Is

Possible

Host Bit Rate System Clock Frequency Range of LSI

19,200 bps 8 to 25 MHz

9,600 bps 8 to 25 MHz

19.6.2 User Program Mode

On-board programming/erasing of an individual flash memory block can also be performed in user

program mode by branching to a user program/erase program. The user must set branching

conditions and provide on-board means of supplying programming data. The flash memory must

contain the program/erase program or a prog ram which provides the program/erase program from

external memory. Because the flash memory itself cannot be read during programming/erasing,

transfer the program/erase program to on-chip RAM, as like in boot mode. Figure 19.7 shows a

sample procedure for programming/erasing in user program mode. Prepare a program/erase

program in accordance with the description in section 19.8, Flash Memory Programming/Erasing.

Section 19 Fl ash Memory (F-ZTAT Version)

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Yes

Program/erase?

Transfer user program/erase control

program to RAM

Reset-start

Branch to user program/erase control

program in RAM

Execute user program/erase control

program (flash memory programming)

Branch to flash memory application

program

Branch to flash memory application

program

FWE = high*

Clear FWE*

Note: * Not available in H8S/2678R Group.

Figure 19.7 Programming/Erasing Flowchart Example in User Program Mode

19.7 Flash Memory Emulation in RAM

Making a setting in the RAM emulation register (RAMER) enables RAM to be overlapped onto

the part of flash memory area so that data to be programmed to flash memory can be emulated in

the on-chip RAM in real time. Emulation can be performed in user mode or user program mode.

Figure 19.8 shows an example of emulation of real-time flash memory programming.

1. Set RAMER to overlap RAM onto the area for which real-time programming is required.

2. Emulation is performed using the overlapping RAM.

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3. After the program data has been confirmed, th e RAMS bit is cleared, thus releasing RAM

overlap.

4. The data written in the overlapping RAM is written into the flash memory sp ace (EB0).

Start of emulation program

Set RAMER

Write tuning data to overlap

RAM

Execute application program

Tuning OK?

Clear RAMER

Write to flash memory

emulation block

End of emulation program

Yes

Figure 19.8 Flowchart for Flash Memory Emulation in RAM

Example in which flash memory block is overlapped is shown in figure 19.9.

1. The RAM area to be overlapped is fixed at a 4-kbyte area in the range of H'FFA000 to

H'FFAFFF.

2. The flash memory area to overlap is selected by RAMER from a 4-kbyte area among one of

the EB0 to EB7 blocks.

3. The overlapped RAM area can be accessed from both the flash memory addresses and RAM

addresses.

Notes: 1. When the RAMS bit in RAMER is set to 1, prog ram/erase protection is enab led for all

flash memory blocks (emulation protection). In this state, setting the P or E bit in

FLMCR1 to 1 does not cause a transition to program mode or erase mode.

2. A RAM area cannot be erased by ex ecution of software in accordance with the erase

algorithm.

Section 19 Fl ash Memory (F-ZTAT Version)

Rev. 3.00 Mar 17, 2006 page 795 of 926

REJ09B0283-0300

3. Block area EB0 contains the vector table. When performing RAM emulation, the

vector table is needed in the overlap RAM.

H'00000

H'01000

H'02000

H'03000

H'04000

H'05000

H'06000

H'07000

H'08000

H'5FFFF

Flash memory

EB8 to EB13

This area can be accessed

from both the RAM area

and flash memory area

EB0

EB1

EB2

EB3

EB4

EB5

EB6

EB7

H'FFA000

H'FFAFFF

H'FFBFFF

On-chip RAM

384-kbyte flash memory

Figure 19.9 Example of RAM Overlap Operation

19.8 Flash Memory Programming/Erasing

A software method, using the CPU, is employed to program and erase flash memory in the on -

board programming modes. Depending on the FLMCR1 and FLMCR2 setting, the flash memory

operates in one of the following four modes: program mode, erase mode, program-verify mode,

and erase-verify mode. The programming control program in boot mode and the user

program/erase program in user mode use these operating modes in combination to perform

programming/erasing. Flash memory programming and erasing should be performed in

accordance with the descriptions in section 19.8.1, Program/Program-Verify, and section 19.8.2,

Erase/Erase-Verify, respectively.

Section 19 Fl ash Memory (F-ZTAT Version)

Rev. 3.00 Mar 17, 2006 page 796 of 926

REJ09B0283-0300

19.8.1 Program/Program-Verify

When programming data or programs to the flash memory, the program/program-verify flowchart

shown in figure 19.10 should be followed. Performing programming operations according to this

flowchart will enable data or programs to be programmed to the flash memory without subjecting

the chip to vo ltage stress or sacrif icing program da ta reliability.

1. Programming must be done to an empty address. Do not reprogram an address to which

programming has already been performed.

2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be

performed ev en if program m in g fewer than 128 bytes. In this case, H'FF data mu st be written

to the extra addresses.

3. Prepare the following data storage areas in RAM: a 128-byte programming data area, a 128-

byte reprogramming data area, and a 128-byte additional-programming data area. Perform

reprogramming data computation and additional programming data computation according to

figure 19.10.

4. Consecutively transfer 128 bytes of data in byte units from the programming data area,

reprogramming data area, or additional-programming data area to the flash memory. The

program address and 128-byte data are latched in the flash memory. The lower 8 bits of the

start address in the flash memory destination area must be H'00 or H'80.

5. The time during which the P bit is set to 1 is the programming time. Figure 19.10 shows the

allowable programming times.

6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.

Set a value greater than (y + z2 + α + β) µs as the WDT overflow period.

7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 2 bits

are B'00. Verify data can be read in words from the address to which a dummy write was

performed.

8. The maxim um n umber of repetitions of the program/progr am-ver ify sequence to the same bit

(N) must not be exceeded.

Section 19 Fl ash Memory (F-ZTAT Version)

Rev. 3.00 Mar 17, 2006 page 797 of 926

REJ09B0283-0300

Start

End of programming

End sub

Set SWE bit in FLMCR1

Wait (x) ms

n = 1

m = 0

Sub-routine-call

See note 7 for pulse width

Note 7: Write Pulse Width

Start of programming

Write pulse application

Set PSU bit in FLMCR1

Enable WDT

Set P bit in FLMCR1

Wait (y) µs

Clear P bit in FLMCR1

Wait (z1) ms or (z2) ms or (z3) ms

Clear PSU bit in FLMCR1

Wait (α) ms

Disable WDT

Wait (β) ms

Write pulse application subroutine

NG NG

Wait (γ) ms

Wait (ε) ms

*6*6

*5 *6

Set PV bit in FLMCR1

H'FF dummy write to verify address

Read verify data

Additional program data computation

Transfer additional program data to

additional program data area

Write data = verify

data?

Reprogram data computation

Clear PV bit in FLMCR1

Clear SWE bit in FLMCR1

m = 1

128-byte

data verification

completed?

m = 0?

6 ≥ n ?

Increment address

Programming failure

Clear SWE bit in FLMCR1

n ≥ (N)?

Write 128-byte data in RAM reprogram

data area consecutively to flash memory

Write pulse application

(z1) µs or (z2) µs

Perform programming in the erased state.

Do not perform additional programming

on previously programmed addresses.

RAM

Program data storage

area (128 bytes)

Reprogram data storage

area (128 bytes)

Additional program data

storage area (128 bytes)

Store 128-byte program data in program

data area and reprogram data area

Number of Writes (n)

998

999

1000

Write Time (z) ms

Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address

written to must be H'00 or H'80. A 128-byte data transfer must be performed even

if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra

addresses.

2. Verify data is read in 16-bit (W) units.

3. The reprogram data is given by the operation of the following tables (comparison

between stored data in the program data area and verify data). Programming is

executed for the bits of reprogram data 0 in the next reprogram loop. Even bits for

which programming has been completed will be subjected to additional

programming if they fail the subsequent verify operation.

4. A 128-byte areas for storing program data, reprogram data, and additional

program data must be provided in the RAM. The contents of the reprogram and

additional program data are modified as programming proceeds.

5. A write pulse of (z1) or (z2) µs should be applied according to the progress of the

programming operation. See note 7 for the pulse widths. When writing of

additional-programming data is executed, a (z3) µs write pulse should be applied.

Reprogram data X' means reprogram data when the write pulse is applied.

6. For the values of x, y, z1, z2, z3, α, β, γ, ε, η, θ, and N, see section 24.6, Flash

Memory Characteristics.

Comments

Programming completed

Programming incomplete; reprogram

Still in erased state; no action

Program Data Operation Chart

Transfer reprogram data to reprogram

data area

n ← n + 1

Note: Use a z3 µs write pulse for additional programming.

Sequentially write 128-byte data in

additional program data area in RAM to

flash memory

Write pulse application

(z3) µs

(additional programming)

Wait (θ) ms

Wait (η) ms

Wait (θ) ms

Original Data

(D) Verify Data

(V) Reprogram Data

(X) 0

Comments

Additional programming executed

Additional programming not executed

Additional Program Data Operation Chart

Reprogram Data

(X') Verify Data

(V) Additional Program

Data (Y)

Figure 19.10 Program/Program-Verify Flowchart

Section 19 Fl ash Memory (F-ZTAT Version)

Rev. 3.00 Mar 17, 2006 page 798 of 926

REJ09B0283-0300

19.8.2 Erase/Erase-Verify

When erasing flash memory, the erase/erase-verify flowchart shown in figure 19.11 should be

followed.

1. Prewriting (setting erase block data to all 0s) is not necessary.

2. Erasing is performed in block units. Make on ly a single-bit specification in the erase block

registers (EBR1 and EBR2). To erase multiple blocks, each block must be erased in turn.

3. The time during which the E bit is set to 1 is the flash memory erase time.

4. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.

Set a value greater than (y + z + α + β) ms as the WDT overflow period.

5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two

bits are B'00. Verify data can be read in longwords from the address to which a dummy write

was performed.

6. If the read data is unerased, set erase mode again, and repeat the erase/erase-verify sequence as

before. The maximum num b er of repetitions of the erase/erase-verify sequence (N) must not be

exceeded.

19.8.3 Interrupt Handling when Programming/Erasing Flash Memory

All interrupts, including NMI input, are disabled when flash memory is being programmed or

erased, and while the boot program is executing in boot mode. There are three reasons for this:

1. Interrupt during programming or erasing might cause a violation of the programming or

erasing algorithm, with the result that normal operation could not be assured.

2. If the interrupt exception handling is started when the vector address has not been programmed

yet or the flash memory is being programmed or erased, the vector would not be read correctly,

possibly resulting in CPU runaway.

3. If an interrupt occurred during boot program execution, it would not be possible to execute the

normal boot mode sequence.

Section 19 Fl ash Memory (F-ZTAT Version)

Rev. 3.00 Mar 17, 2006 page 799 of 926

REJ09B0283-0300

End of erasing

Start

Set SWE bit in FLMCR1

Set ESU bit in FLMCR1

Set E bit in FLMCR1

Wait (x) µs

Wait (y) µs

n = 1

Set EBR1, EBR2

Enable WDT

Wait (z) ms *

Wait (α) µs*

Wait (β) µs*

Wait (γ) µs

Set block start address to verify address

Wait (ε) µs*

Wait (η) µs

Start of erase

Clear E bit in FLMCR1

Clear ESU bit in FLMCR1

Set EV bit in FLMCR1

H'FF dummy write to verify address

Read verify data

Clear EV bit in FLMCR1

Wait (η) µs

Clear EV bit in FLMCR1

Clear SWE bit in FLMCR1

Disable WDT

Halt erase

Verify data = all 1?

Last address of block?

End of

erasing of all erase

blocks?

Erase failure

Clear SWE bit in FLMCR1

n ≥ N?

NG NG

OK OK

n ← n + 1

Increment

address

Notes: 1. Prewriting (setting erase block data to all 0) is not necessary.

2. The values of x, y, z, α, β, γ, ε, η, θ, and N are shown in section 24.6, Flash Memory Characteristics.

3. Verify data is read in 16-bit (W) units.

4. Set only one bit in EBR1or EBR2. More than one bit cannot be set.

5. Erasing is performed in block units. To erase a number of blocks, the individual blocks must be erased sequentially.

Wait (θ) µs Wait (θ) µs

Figure 19.11 Erase/Erase-Verify Flowchart

Section 19 Fl ash Memory (F-ZTAT Version)

Rev. 3.00 Mar 17, 2006 page 800 of 926

REJ09B0283-0300

19.9 Program/Erase Protection

There are three kinds of flash memory program/erase protection: hardware protection, software

protection, and error protection.

19.9.1 Hardware Protection

Hardware protection refers to a state in which programming/erasing of flash memory is forcibly

disabled or aborted because o f a transition to reset (including an overflow reset by the WDT) or

standby mode. Flash memory control register 1 (FLMCR1), flash memory control register 2

(FLMCR2), erase b lo c k register 1 (EBR1) , and erase block register 2 ( E BR2) are initialized. In a

reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation

stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the

RES pulse width specified in the AC Characteristics section.

19.9.2 Software Protection

Software protection can be implemented against programming/erasing of all flash memory blocks

by clearing the SWE bit in FLMCR1 (this operation must be executed in the on-chip RAM or

external mem ory ) . When software protection is in effect, setting the P or E bit in FLMCR1 does

not cause a transition to program mode or erase mode. By setting the erase block register 1

(EBR1) and erase block register 2 (EBR2), erase protection can be set for individual blocks. When

EBR1 and EBR2 are set to H'00, erase protection is set for all blocks.

19.9.3 Error Protection

In error protection, an error is detected when the CPU’s runaway occurs during flash memory

programming/erasing, or operation is not performed in accordance with the program/erase

algorithm, and the program/erase operation is forcibly aborted. Aborting the program/erase

operation prevents damage to the flash memo ry due to overprogramming or overerasing.

When the following errors are detected during programming/erasing of flash memory, the FLER

bit in FLMCR2 is set to 1, and the error protection state is enter ed.

• When flash memory is read during programming/erasing (including a vector read or instruction

fetch)

• When an exception handling (excluding a reset) is started during programming/erasing

• When a SLEEP instruction is executed during programming/erasing

• When the CPU releases the bus mastership during programming/erasing

Section 19 Fl ash Memory (F-ZTAT Version)

Rev. 3.00 Mar 17, 2006 page 801 of 926

REJ09B0283-0300

The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase

mode is forcibly aborted at the point at which the error occurred. Program mode or erase mode

cannot be re-entered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a

transition can be made to verify mode. The error protection state can be canceled by a power-on

reset or in hardware standby mode.

19.10 Programmer Mode

In programmer mode, a PROM programmer can perform programming/erasing via a socket

adapter, just like for a discrete flash memory. Use a PROM programmer which supports the

Renesas 512-kbyte flash memory on-chip MCU device type (FZTAT512V3A). A 12-MHz input

clock is needed.

19.11 Power-Down States for Flash Memory

In user mode, th e flash m emory will operate in either of th e follo wing states:

• Normal operating mode

The flash memory can be read.

• Standby mode

All flash memo r y circuits are halted.

Table 19.7 shows the correspondence between the operating modes of this LSI and the flash

memory. When the flash memory returns to normal operation from a standby state, a power supply

circuit stabilization period is needed. When the flash memory returns to its normal operating state,

bits STS3 to STS0 in SBYCR must be set to provide a wait time of at least 100 µs, even when the

external clock is being used.

Table 19.7 Flash Memory Operating States

Operating Mode Flash Memory Operating State

Active mode Normal operating state

Sleep mode Normal operating state

Standby mode Standby state

Section 19 Fl ash Memory (F-ZTAT Version)

Rev. 3.00 Mar 17, 2006 page 802 of 926

REJ09B0283-0300

19.12 Usage Notes

Precautions concerning the use of on-board programming mode, the RAM emulation function, and

programmer mode are summarized below.

1. Use the specified voltages and timing for programming and erasing.

Applied voltages in excess of the rating can permanently damage the device. Use a PROM

programmer that supports the Renesas Technology microcomputer device type with 512-kbyte

on-chip flash memory (FZTAT512V3A).

Do not select the HN27C4096 setting for the PROM programmer, and only use the specified

socket adapter.

2. Reset the flash memory before turning on/off the power.

When applying or disconnecting Vcc power, fix the RES pin low and place the flash memory

in the hardware protection state. The power-on and power-off timing requirements should also

be satisfied in the event of a power failure and subsequent recovery.

3. Powering on and off.

Do not apply a high lev el to the FWE pin until VCC has stabilized. Also, drive the FWE pin low

before turning off VCC.

When applying or disconnecting VCC power, fix the FWE pin low and place the flash memory

in the hardware protection state.

The power-on and power-off timing requirements should also be satisfied in the event of a

power failure and subsequent recovery . The power-on and power-off timing in the H8S/2678

Group is shown in figure 19.12.

4. FWE application/disconnection.

FWE application should be carried out when this LSI operation is in a stable condition. If this

LSI operation is not stable, fix the FWE pin low and set the protection state.

The following points must be observed concerning FWE application and disconnection to prevent

unintentional programming or erasing of flash memory:

• Apply FWE when the VCC voltage has stabilized within its r ated voltage r ange .

• In boot mode, apply and disconnect FWE during a reset.

• In user program mode, FWE can be switched between high and low level regardless of the

reset state. FWE input can also be switched during execution of a program in flash memory.

• Do not apply FWE if program runaway has occurred.

• Disconnect FWE only when the SWE, ESU, PSU, EV, PV, and E bits in FLMCR1 are cleared.

Section 19 Fl ash Memory (F-ZTAT Version)

Rev. 3.00 Mar 17, 2006 page 803 of 926

REJ09B0283-0300

5. Do not apply a constant high level to the FWE pin.

Apply a high level to the FWE pin only when programming or erasing flash memory. Also,

while a high lev el is applied to the FWE pin, the watchdog timer should be activated to prevent

overprogramming or overerasing due to program runaway, etc.

6. Use the recommended algorithm when programming and erasing flash memory.

The recommended algorithm enables programming and erasing to be carried out without

subjecting the device to voltage stress o r sacrificing prog r am data reliability. When setting the

P or E bit in FLMCR1, the watchdog timer should be set beforehand as a precaution against

program runaway, etc.

7. Do not set or clear the SWE bit during execution of a program in flash memory.

Wait for at least 100 µs after clearing the SWE bit before executing a program or reading data

in flash memory.

When the SWE bit is set, data in flash mem ory can be rewritten. When the SWE bit is set to 1,

data in flash memory can be read only in program-verify/erase-verify mode. Access flash

memory only for verify operatio ns (verificat io n duri ng pro gramming/erasing). Also, do not

clear the SWE bit during programming, erasing, or verifying. Similarly, when using the RAM

emulation function, the SWE bit must be cleared before executing a program or reading data in

flash memory.

However, the RAM area overlapping flash memory space can be read and written to regardless

of whether the SWE bit is set or cleared.

8. Do not use interrupts while flash memory is being programmed or erased.

All interrupt requests, including NMI, should be disabled during programming/erasing the

flash memory to give priority to program/erase operations.

9. Do not p erfo rm additional programming. Erase th e memo ry b efor e reprogr amming.

In on-board programming, perform only one programming operation on a 128-byte

programming unit block. In programmer mode, too, perform only one programming operation

on a 128-byte programming unit block. Programming should be carried out with the entire

programming unit block erased.

10. Before program m ing, ch eck that the chip is correctly mounted in the PROM programmer.

Overcurrent damage to the device can result if the index marks on the PROM programmer

socket, socket adapter, and chip are not correctly aligned.

11.Do not touch the socket adapter or chip during programming.

Touching either of these can cause contact faults and write errors.

12.Apply the reset signal after the SWE, bit is cleared during its operation.

The reset signal is applied at least 100 µs after the SWE bit has been cleared.

Section 19 Fl ash Memory (F-ZTAT Version)

Rev. 3.00 Mar 17, 2006 page 804 of 926

REJ09B0283-0300

Period during which flash memory access is prohibited

(x: Wait time after setting SWE bit)*

Period during which flash memory can be programmed

(Execution of program in flash memory prohibited, and data reads other than verify operations prohibited)

VCC

FWE

OSC1

Min 0 µs

MDS

MD2 to MD0*

RES

SWE bit SWE set SWE cleared

Programming/

erasing

possible

Wait time: x Wait time: 100 µs

Notes: 1. Except when switching modes, the level of the mode pins (MD2 to MD0) must be fixed until

power-off by pulling the pins up or down.

2. See section 24.6, Flash Memory Characteristics.

3. Mode programming setup time t

MDS

(min) = 200 ns

SWE set SWE cleared

VCC

FWE

OSC1

Min 0 µs

MD2 to MD0*

RES

SWE bit

(2) User Program Mode

(1) Boot Mode

Programming/

erasing

possible

Wait time: x Wait time: 100 µs

MDS

Figure 19.12 Power-On/Off Timing (H8S/2678 Group)

Section 19 Fl ash Memory (F-ZTAT Version)

Rev. 3.00 Mar 17, 2006 page 805 of 926

REJ09B0283-0300

OSC1

Min 0 µs

MDS

MD2 to MD0*

RES

SWE bit

SWE set

(1) Boot Mode

(2) User Program Mode

SWE cleared

Programming/

erasing

possible

Wait time: x Wait time: 100 µs

Period during which flash memory access is prohibited

(x: Wait time after setting SWE bit)*

Period during which flash memory can be programmed

(Execution of program in flash memory prohibited, and data reads other than verify operations prohibited)

Notes: 1. Except when switching modes, the level of the mode pins (MD2 to MD0) must be fixed until

power-off by pulling the pins up or down.

2. See section 24.6, Flash Memory Characteristics.

3. Mode programming setup time t

MDS

(min) = 200 ns

SWE set SWE cleared

OSC1

MD2 to MD0*

RES

SWE bit

Programming/

erasing

possible

Wait time: x

MDS

Wait time: 100 µs

Min 0 µs

Figure 19.13 Power-On/Off Timing (H8S/2678R Group)

Section 19 Fl ash Memory (F-ZTAT Version)

Rev. 3.00 Mar 17, 2006 page 806 of 926

REJ09B0283-0300

Period during which flash memory access is prohibited

(x: Wait time after setting SWE bit)

Period during which flash memory can be programmed

(Execution of program in flash memory prohibited, and data reads other than verify operations prohibited)

FWE

OSC1

Min 0 µs

MDS

RESW

MD2 to MD0

RES

SWE bit

Mode

change

Mode

change

Boot

mode User

mode User program mode

(1) H8S/2678 Group

(2) H8S/2678R Group

SWE

set SWE

cleared

Programming/erasing

possible

Wait time: x Programming/erasing

possible

Wait time: x Programming/erasing

possible

Wait time: x Programming/erasing

possible

Wait time: x

User

mode User program

mode

Notes: 1. When entering boot mode or making a transition from boot mode to another mode, mode switching must be

carried out by means of RES input. The state of ports with multiplexed address functions and bus control output

pins (AS, RD, HWR, LWR) will change during this switchover interval (the interval during which the RES pin

input is low), and therefore these pins should not be used as output signals during this time.

2. When making a transition from boot mode to another mode, a mode programming setup time t

MDS

(min) of 200

ns is necessary with respect to RES clearance timing.

3. See section 24.6, Flash Memory Characteristics.

4. Wait time: 100 µs

OSC1

MDS

Wait time: x

Programming/erasing

possible

Wait time: x

Programming/erasing

possible

Wait time: x

Programming/erasing

possible

Wait time: x

Programming/erasing

possible

RESW

MD2 to MD0

RES

SWE bit

Boot

mode

Mode

change

Mode

change

User

program

mode

User

program

mode

User

program

mode

User modeUser

mode

User

mode

SWE

set SWE

cleared

Figure 19.14 Mode Transition Timing

(Example: Boot Mode →

→→

→ User Mode ↔

↔↔

↔ User Program Mode)

Section 19 Fl ash Memory (F-ZTAT Version)

Rev. 3.00 Mar 17, 2006 page 807 of 926

REJ09B0283-0300

19.13 Note on Switching from F-ZTAT Version to Masked ROM Version

Care is required if application software developed on the F-ZTAT version is used when the F-

ZTAT version is switched to the masked ROM version product.

If an address in which a register for the F-ZTAT version is present is read (see section 23.1,

masked ROM version, an undefined value will be returned.

If application software developed on the F-ZTAT version is used in the masked ROM version

product, the state of the FWE pin cannot be judged. The program must be modified so that the part

of reprogramming (erasing/programming) the flash memory and the part of the RAM emulation

are not started.

Also, the mode pin of boot mode must not be set in the masked ROM version.

Note: T his note is applied to all products in the F-ZTAT v ersion and in the masked ROM

version of same Group with the different ROM size.

Section 19 Fl ash Memory (F-ZTAT Version)

Rev. 3.00 Mar 17, 2006 page 808 of 926

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Section 20 Masked ROM

Rev. 3.00 Mar 17, 2006 page 809 of 926

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Section 20 Masked ROM

This Group microcomputer has 64, 128, or 256 kbytes of on-chip masked ROM. The on-chip

ROM is connected to the CPU, data transfer contr oller (DTC), and DMA controller (DMAC) with

a 16-bit data bus. The on-chip ROM can be accessed by the CPU, DTC, and DMAC in 8 or 16-bit

units. The data in the on-chip ROM can always be accessed in one state.

H'000000

H'000002

H'03FFFE

H'000001

H'000003

H'03FFFF

Internal data bus (upper 8 bits)

Modes 4 and 7 Modes 5 and 6

Internal data bus (lower 8 bits)

H'100000

H'100002

H'13FFFE

H'100001

H'100003

H'13FFFF

Internal data bus (upper 8 bits)

Internal data bus (lower 8 bits)

Figure 20.1 Block Diagram of 256-kbyte Masked ROM (HD6432676)

H'000000

H'000002

H'01FFFE

H'000001

H'000003

H'01FFFF

Internal data bus (upper 8 bits)

Modes 4 and 7 Modes 5 and 6

Internal data bus (lower 8 bits)

H'100000

H'100002

H'11FFFE

H'100001

H'100003

H'11FFFF

Internal data bus (upper 8 bits)

Internal data bus (lower 8 bits)

Figure 20.2 Block Diagram of 128-kbyte Masked ROM (HD6432675)

Section 20 Masked ROM

Rev. 3.00 Mar 17, 2006 page 810 of 926

REJ09B0283-0300

H'000000

H'000002

H'00FFFE

H'000001

H'000003

H'00FFFF

Internal data bus (upper 8 bits)

Modes 4 and 7 Modes 5 and 6

Internal data bus (lower 8 bits)

H'100000

H'100002

H'10FFFE

H'100001

H'100003

H'10FFFF

Internal data bus (upper 8 bits)

Internal data bus (lower 8 bits)

Figure 20.3 Block Diagram of 64-kbyte Masked ROM (HD6432673)

The operating mode enables or disables the on-chip ROM. The operating mode is selected by the

mode setting pins, such as the FWE and MD2 to MD0 pins as shown in table 3.1. Select modes 4

to 7 when the on-chip ROM is used, and mode 1 or 2 when the on-chip ROM is not used. The on-

chip ROM is allocated in area 0.

Section 21 Clock Pulse Generator

Rev. 3.00 Mar 17, 2006 page 811 of 926

REJ09B0283-0300

Section 21 Clock Pulse Generator

This LSI has an on-chip clock pulse generator (CPG) that generates the system clock (φ) and

internal clock s.

The clock pulse gener a tor consists of an oscillator circuit, PLL circuit, and divider.

Figure 21.1 shows a block diagram of the clock pulse generator.

EXTAL PLL circuit

(×1, 2, 4)

Oscillator Divider

System clock

to φ pin Internal cloc

to peripheral

modules

SCK2 to SCK0

SCKCR

STC0, STC1

PLLCR

XTAL

Legend:

PLLCR: PLL system control register

SCKCR: System clock control register

Figure 21.1 Block Diagram of Clock Pulse Generator

The frequency can be changed by means of the PLL circuit. Frequency changes are made by

software by means of settings in the PLL control register (PLLCR) and the system clock control

21.1 Register Descriptions

The clock pulse generator has the following registers.

• System clock control register (SCKCR)

• PLL control register (PLLCR)

CPG0400A_010020020400

Section 21 Clock Pulse Generator

Rev. 3.00 Mar 17, 2006 page 812 of 926

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21.1.1 System Clock Control Register (SCKCR)

SCKCR controls φ clock output and selects operation when the frequency multiplication factor

used by the PLL circuit is changed, and the division ratio used by the divider.

Bit Bit Name Initial Value R/W Description

7 PSTOP 0 R/W φ Clock Output Disable

Controls φ output.

Normal Operation

0: φ output

1: Fixed high

Sleep Mode

0: φ output

1: Fixed high

Software Standby Mode

0: Fixed high

1: Fixed high

Hardware Standby Mode

0: High impedance

1: High impedance

All module clo ck sto p mode

0: φ output

1: Fixed high

6— 0 R/WReserved

This bit can be read from or written to. However, The

write value should always be 0.

5, 4 — All 0 R/W Reserved

These bits are always read as 0. However, the write

value should always be 0.

3 STCS 0 R/W Frequency Multiplication Factor Switching Mode Select

Selects the operation when the PLL circuit frequency

multiplica tio n factor is changed.

0: Specified mu ltiplication factor is valid after transition

to software standby mode

1: Specified multiplication factor is valid immediately

after STC1 and STC0 bits are rewritten

Section 21 Clock Pulse Generator

Rev. 3.00 Mar 17, 2006 page 813 of 926

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Bit Bit Name Initial Value R/W Description

SCK2

SCK1

SCK0

R/W

System Clock Select 2 to 0

Select the division ratio.

000: 1/1

001: 1/2

010: 1/4

011: 1/8

100: 1/16

101: 1/32

11X: Setting prohibited

Legend: X: Don’t care

21.1.2 PLL Control Register (PLLCR)

PLLCR sets the fr equency multiplication factor used by the PLL circuit.

Bit Bit Name Initial Value R/W Description

— All 0 — Reserved

These bits are always read as 0 and cannot be

modified.

3— 0 R/WReserved

This bit can be read from or written to. However,

the write value should always be 0.

2— 0 R/WReserved

This bit is always read as 0 and cann ot be

modified.

0STC1

STC0 0

0R/W

R/W Frequency Multiplication Factor

The STC bits specify the frequency multiplication

factor used by the PLL circuit.

00: × 1

01: × 2

10: × 4

11: Setting prohibited

Section 21 Clock Pulse Generator

Rev. 3.00 Mar 17, 2006 page 814 of 926

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21.2 Oscillator

Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock.

21.2.1 Connecting a Crystal Resonator

A crystal resonator can be connected as shown in the example in figure 21.2. Select the damping

resistance Rd according to table 20.1. An AT-cut parallel-resonance type should be used.

Figure 21.3 shows the equivalent circuit of the crystal resonator. Use a crystal resonator that has

the characteristics shown in table 21.2. When a crystal resonator is used, the range of its

frequencies is from 8 to 25 MHz.

EXTAL

XTAL RdCL2

CL1

CL1 = CL2 = 10 to 22 pF

Figure 21.2 Connection of Crystal Resonator (Example)

Table 21.1 Damping Resistance Value

Frequency (MHz) 8 12 16 20 25

Rd (Ω) 2000000

XTAL

AT-cut parallel-resonance type

EXTAL

Figure 21.3 Crystal Resonator Equivalent Circuit

Section 21 Clock Pulse Generator

Rev. 3.00 Mar 17, 2006 page 815 of 926

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Table 21.2 Crystal Resonator Characteristics

Frequency (MHz) 8 12 16 20 25

RS max (Ω) 8060504040

C0 max (pF) 77777

21.2.2 External Clock Input

An external clock signal can be input as shown in the examples in figure 21.4. If the XTAL pin is

left open, make sure that parasitic capacitance is no more than 10 pF. When the counter clock is

input to the XTAL pin, make sure that the external clock is held high in standby mode.

Table 21.3 shows the inpu t conditions for the external clock. When an external clock is used, the

range of its frequencies is from 8 to 25 MHz.

EXTAL

XTAL

External clock input

Open

(a) XTAL pin left open

EXTAL

XTAL

External clock input

(b) Counter clock input at XTAL pin

Figure 21.4 External Clock Input (Ex amples)

Section 21 Clock Pulse Generator

Rev. 3.00 Mar 17, 2006 page 816 of 926

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Table 21.3 External Clock Input Conditions

VCC = 3.0 V to 3.6 V

Item Symbol Min Max Unit Test Conditions

External clo ck input

low pulse width tEXL 15 —ns Figure 21.5

External clo ck input

high pulse width tEXH 15 —ns

External clock rise time tEXr —5ns

External clock fall time tEXf —5ns

Clock low pulse width tCL 0.4 0.6 tcyc

Clock high pulse width tCH 0.4 0.6 tcyc

EXH

EXL

EXr

EXf

× 0.5

EXTAL

Figure 21. 5 External Clock Input Timing

21.3 PLL Circuit

The PLL circuit has the function of multiplying the frequency of the clock from the oscillator by a

factor of 1, 2, or 4. The m ultiplication factor is set with the STC1 and the STC0 bits in PLLCR.

The phase of the rising edge of the internal clock is controlled so as to match that of the rising

edge of the EXTAL pin.

When the multip licatio n factor of the PLL circuit is changed, the operation varies according to th e

setting of the STCS bit in SCKCR.

When STCS = 0, the setting becomes valid after a transition to software standby mode. The

transition time count is performed in accordance with the setting of bits STS3 to STS0 in SBYCR.

For details on SBYCR, refer to section 22.1.1, Standby Control Register (SBYCR).

1. The initial PLL circ uit multiplication f actor is 1 .

Section 21 Clock Pulse Generator

Rev. 3.00 Mar 17, 2006 page 817 of 926

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2. A value is set in bits STS3 to STS0 to give the specified transition time.

3. The targ et value is set in bits STC1 and STC0, and a transition is m a de to software standby

mode.

4. The clock pulse generator stops and the value set in STC1 and STC0 becomes valid.

5. Software standby mode is cleared, and a transition time is secured in accordance with the

setting in STS3 to STS0.

6. After th e set tr ansition time h as elapsed, this LSI r esumes operation using the target

multiplication factor.

When STCS = 1, th is LSI operates usin g the new multiplicatio n factor immediately after b its

STC1 and STC0 ar e rewritten.

21.4 Frequeny Divider

The frequency divider divides the PLL output clock to generate a 1/2, 1/4, 1/8, 1/16 , or 1/32 clock.

21.5 Usage Notes

21.5.1 Notes on Clock Pulse Generator

1. The following points should be noted since the frequency of φ changes according to the setting

of SCKCR and PLLCR.

Select the clock division ratio that is within the operation guaranteed range of clock cycle time

tcyc shown in the AC timing of Electrical Characteristics. In other words, the range of φ must

be specified from 8 MHz (min) to 33 MHz (max); outside of this range must be prevented.

2. All the on-chip peripheral modules operate on the φ. Therefore, note that the time processing

of modules such as a timer and SCI differ before and after changing the clock division ratio. In

addition, wait time for clearing software standby mode differs by changing the clock division

ratio. See the description, Setting Oscillation Stabilization Time after Clearing So f twar e

Standby Mode, in section 22.2.3, Software Standby Mode, for details.

3. Note that the frequency of φ will be changed when setting SCKCR or PLLCR while executing

the external bus cycle with the write-data-buffer function or the EXDMAC.

21.5.2 Notes on Reso nator

Since various characteristics related to the resonator are closely linked to the user’s board design,

thorough evalua tio n is necessary on the user’s part, u sing the oscillator connection examples

shown in this section as a guide. As the parameters for the oscillation circuit will depe nd on the

floating capacitance of the resonator and the user board, the parameters should be determined in

Section 21 Clock Pulse Generator

Rev. 3.00 Mar 17, 2006 page 818 of 926

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consultation with the resonator manufacturer. The design must ensu re that a voltage exceeding the

maximum rating is not applied to the oscillator pin.

21.5.3 Notes on Board Design

When using the crystal resonator, place the crystal resonator and its load capacitors as close as

possible to the XTAL and EXTAL pins. Other signal lines should be routed away from the

oscillation circuit to prevent induction from interfering with cor r ect oscillation . See f ig ure 21.6.

Signal A Signal B

This LSI

XTAL

EXTAL

Avoid

Figure 21.6 Note on Board Design for Oscillation Circuit

Figure 21.7 shows the extern al circuitry recommended for the PLL circuit. Separate PLLVcc and

PLLVss from the other Vcc and Vss lines at the board power supply source, and be sure to insert

bypass capacitors CPB and CB close to the pins.

PLLV

Rp: 200Ω

CPB: 0.1 µF*

CB: 0.1 µF*

Note: * CB and CPB are laminated ceramic capacitors.

Figure 21.7 Recommended External Circuitry for PLL Circuit

Section 22 Power-Down Modes

Rev. 3.00 Mar 17, 2006 page 819 of 926

REJ09B0283-0300

Section 22 Power-Down Modes

In addition to the normal program execution state, this LSI ha s power -down modes in which

operation of the CPU and oscillator is halted and power dissipation is reduced. Low-po w er

operation can be achieved by individually controlling the CPU, on-chip peripheral modules, and

so on.

This LSI’s operating modes are high-speed mode and six power down modes:

• Clock division mode

• Sleep mode

• Module stop mode

• All module clock stop mode

• Software standby mode

• Hardware standby mode

Sleep mode is a CPU state, clock division mode is a CPU and bus master state, and module stop

mode is an on-chip peripheral function (including bus masters other than the CPU) state. A

combination of these modes can be set.

After a reset, this LSI is in high-sp eed mode.

Table 22.1 shows the internal states of this LSI in each mode. Figure 21.1 shows the mode

transition diagram.

LPWS261A_010020020400

Section 22 Power-Down Modes

Rev. 3.00 Mar 17, 2006 page 820 of 926

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Table 22.1 Opera ting Modes

Operating Stat e

High

Speed

Mode

Clock

Division

Mode Sleep

Mode Module

Stop Mode

All Module

Clock Stop

Mode

Software

Standby

Mode

Hardware

Standby

Mode

Clock pulse generator Functions Functions Functions Functions Functions Halted Halted

Instruction

execution Halted Halted HaltedCPU

Functions Functions

Retained

Functions Halted

Retained Undefined

NMIExternal

interrupts IRQ0 to 15

Functions Functions Functions Functions Functions Functions Halted

Peripheral

functions WDT Functions Functions Functions Functions Functions Halted

(Retained) Halted

(Reset)

TMR Functions Functions Functions Halted

(Retained) Functions/

Halted

(Retained)*

Halted

(Retained) Halted

(Reset)

EXDMAC Functions Functions Functions Halted

(Retained) Halted

(Reset)

DMAC Functions Functions Functions Halted

(Retained) Halted

(Reset)

DTC Functions Functions Functions Halted

(Retained) Halted

(Reset)

TPU Functions Functions Functions Halted

(Retained) Halted

(Reset)

PPG Functions Functions Functions Halted

(Retained) Halted

(Reset)

D/A Functions Functions Functions Halted

(Retained) Halted

(Reset)

A/D Functions Functions Functions Halted

(Retained) Halted

(Reset) Halted

(Reset)

SCI Functions Functions Functions Halted

(Reset) Halted

(Reset)

RAM Functions Functions Functions Functions Functions Retained Retained

I/O Functions Functions Functions Functions Retained Retained High

impedance

Notes: “Halted (Retained)” in the table means that internal register values are retained and internal

operations are suspended.

“Halted (Reset)” in the table means that internal register values and internal states are

initialized.

In module stop mode, only modules for which a stop setting has been made are halted

(reset or retained).

*The active or halted state can be selected by means of the MSTP0 bit in MSTPCR.

Section 22 Power-Down Modes

Rev. 3.00 Mar 17, 2006 page 821 of 926

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Program-halted stateProgram execution state

High-speel mode

(Internal clock is PLL

circuit output clock)

Reset state

STBY pin = low

STBY pin = high

RES pin = low

SSBY = 0

MSTPCR =

H'FFFF (H'FFFE),

SSBY = 0

SSBY = 1

SCK2 to

SCK0 ≠ 0

RES pin = high

SCK2 to

SCK0 = 0

SLEEP

instruction

Interrupt*

: Transition after exception handling : Power- down mode

SLEEP

instruction

Any interrupt

SLEEP

instruction

External

interrupt*

Notes: When a transition is made between modes by means of an interrupt, the transition cannot

be made on interrupt source generation alone. Ensure that interrupt handling is performed

after accepting the interrupt request.

From any state, a transition to hardware standby mode occurs when STBY is driven low.

From any state except hardware standby mode, a transition to the reset state occurs when

RES is driven low.

1. NMI, IRQ0 to IRQ15, 8-bit timer interrupts, watchdog timer interrupts.

(8-bit timer interrupts are valid when MSTP0 = 0.)

2. NMI, IRQ0 to IRQ15

(IRQ0 to IRQ15 are valid when the corresponding bit in SSIER is 1.)

Hardware

standby mode

Sleep mode

All

module-clocks-stop

mode

Software

standby mode

Clock division

mode

Figure 22.1 Mo de Transitions

Section 22 Power-Down Modes

Rev. 3.00 Mar 17, 2006 page 822 of 926

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22.1 Register Descriptions

The registers relating to the power-down mode are shown below. For details on the system clock

control register (SCKCR), refer to section 21.1.1, System Clock Control Register (SCKCR).

• System clock control register (SCKCR)

• Standby control register (SBYCR)

• Module stop control register H (MSTPCRH)

• Module stop control register L (MSTPCRL)

22.1.1 Standby Control Register (SBYCR)

SBYCR performs software standby mode control.

Bit Bit Name Initial Value R/W Description

7 SSBY 0 R/W Software Standby

This bit specifies the transition mode after

executing the SLEEP instruction

0: Shifts to sleep mode after the SLEEP instruction

is exec uted

1: Shifts to software standby mode after the

SLEEP instruction is executed

This bit does not change when clearing the

software standby mode by using external interrupts

and shifting to normal operation. This bit should be

written 0 when clearing.

6OPE 1 R/W

Output Port Enable

Specifies whether the output of the address bus

and bus control sig nal s (CS0 to CS7, AS, RD,

HWR, LWR, UCAS, LCAS) is retained or set to the

high-impedance state in software standby mode.

0: In software standby mode, address bus and bus

control signals are high-impedance

1: In software standby mode, address bus and bus

control sig nal s retain outp ut state

Section 22 Power-Down Modes

Rev. 3.00 Mar 17, 2006 page 823 of 926

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Bit Bit Name Initial Value R/W Description

5, 4 —All 0 —Reserved

These bits are always read as 0. The initial value

should not be changed.

STS3

STS2

STS1

STS0

R/W

Standby Timer Select 3 to 0

These bits select the time the MCU waits for the

clock to stabilize when software standby mode is

cleared by an external interrupt. With crystal

oscillation, refer to table 22.2 and make a selection

according to the operating frequency so that the

standby time is at least the os cillation stabilization

time. With an external clock, a PLL circuit

stabilization time is necessary. Refer to table 22.2

to set the wait time. When DRAM is used and self-

refreshing in the softw are stand by state is

selected, no te that the DRAM’s tRAS (self-refresh

RAS pulse width) specification must be satisfied.

With the F-ZTAT version, a flash memory

stabilization time must be provided.

0000: Setting prohibited

0001: Setting prohibited

0010: Setting prohibited

0011: Setting prohibited

0100: Setting prohibited

0101: Standby time = 64 states

0110: Standby tim e = 512 states

0111: Standby time = 1024 states

1000: Standby time = 2048 states

1001: Standby time = 4096 states

1010: Standby time = 16384 states

1011: Standby time = 32768 states

1100: Standby time = 65536 states

1101: Standby time = 131072 states

1110: Standby time = 262144 states

1111: Standby time = 524288 states

Section 22 Power-Down Modes

Rev. 3.00 Mar 17, 2006 page 824 of 926

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22.1.2 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL)

MSTPCR performs module stop mode control.

Setting a bit to 1, the corresponding module enters module stop mode, while clearing the bit to 0

clears the module stop mode.

MSTPCRH

Bit Bit Name Initial Value R/W Module

15 ACSE 0 R/W All-Module-Clocks-Stop Mode Enable

Enables or disables all-module-clocks-stop mode,

in which, when the CPU ex ecutes a SLEEP

instruction after module stop mode has been set

for all the on-chip peripheral functions controlled by

MSTPCR or the on-chip peripheral functions

except the TMR.

0: All-module-clocks-stop mode disabled

1: All-module-clocks-stop mode enabled

14 MSTP14 0 R/W EXDMA controller (EXDMAC)

13 MSTP13 0 R/W DMA controller (DMAC)

12 MSTP12 0 R/W Data transfer controller (DTC)

11 MSTP11 1 R/W 16-bit timer-pulse unit (TPU)

10 MSTP10 1 R/W Programm able pul se gener ator (PPG)

9 MSTP9 1 R/W D/A converter (channels 0 and 1)

8 MSTP8 1 R/W D/A converter (channels 2 and 3)

Section 22 Power-Down Modes

Rev. 3.00 Mar 17, 2006 page 825 of 926

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MSTPCRL

Bit Bit Name Initial Value R/W Module

7 MSTP7 1 R/W —

6 MSTP6 1 R/W A/D converter

5 MSTP5 1 R/W —

4 MSTP4 1 R/W —

3 MSTP3 1 R/W Serial comm uni cat ion inter f ace 2 (SCI_2)

2 MSTP2 1 R/W Serial comm uni cat ion inter f ace 1 (SCI_1)

1 MSTP1 1 R/W Serial comm uni cat ion inter f ace 0 (SCI_0)

0 MSTP0 1 R/W 8-bit timer (TMR)

22.2 Operation

22.2.1 Clock Division Mo de

When bits SCK2 to SCK0 in SCKC R ar e set to a value from 001 to 101, a transition is made to

clock division mode at the end of the bus cycle. In clock division mode, the CPU, bus masters, and

on-chip periph eral functions all operate on the operating clock (1/2, 1/4, 1/8, 1/16, or 1/32)

specified by bits SCK2 to SCK0.

Clock division mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to

high-speed mode at the end of the bus cycle, and clock division mode is cleared.

If a SLEEP instruction is executed while the SSBY bit in SBYCR is cleared to 0, the chip enters

sleep mode. When sleep mode is cleared by an interrupt, clock division mode is restored.

If a SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, the chip enters

software standby mode. When software standby mode is cleared by an external interrupt, clock

division mode is restored.

When the RES pin is driven low, the reset state is entered and clock division mode is cleared. The

same applies to a reset caused by watchdog timer overflow.

When the STBY pin is driven low, a transition is made to hardware standby mode.

Section 22 Power-Down Modes

Rev. 3.00 Mar 17, 2006 page 826 of 926

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22.2.2 Sleep Mode

Transition to Sleep Mode: When the SLEEP instruction is executed when the SSBY bit is 0 in

SBYCR, the CPU enters the sleep mode. In sleep mode, CPU operation stops but the contents of

the CPU’s internal registers are retained. Other peripheral functions do not stop.

Exiting Sleep Mode: Sleep mode is exited by an y inter r upt, or signals at the RES, or STBY pins.

• Exiting Sleep Mode by Interrupts

When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep

mode is not ex ited if the interrupt is disabled, or interrupts other than NMI are masked by the

CPU.

• Exiting Sleep Mode by RES Pin

Setting the RES pin level low selects the reset state. After the stipulated reset input duration,

driving the RES pin high starts the CPU performing reset exception processing.

• Exiting Sleep Mode by STBY Pin

When the STBY pin level is driven low, a transition is made to hardware standby mode.

22.2.3 Softw are Standby Mo de

Transition to Software Standby Mode: If a SLEEP instruction is executed when the SSBY bit in

SBYCR is set to 1, software standby mode is entered. In this mode, the CPU, on-chip peripheral

functions, and oscillator all stop. Ho wever, the contents of the CPU’s internal r e gisters, RAM

data, and the states of on-chip peripheral functions other than the SCI and A/D converter, and I/O

ports, are retained. Whether the address bus and bus control signals are placed in the high-

impedance state or retain the output state can be specified by the OPE bit in SBYCR.

In this mo de the oscillator stops, and therefore power dissipation is significantly reduced.

Clearing Software Standby Mode: Software standby mode is cleared by an extern al interrupt

(NMI pin, or pins IRQ0 to IRQ15), or by means of the RES pin or STBY pin. Setting the SSI bit

in SSIER to 1 enables IRQ0 to IRQ15 to be used as software standby mode clearing so urces.

• Clearing with an I nterrupt

When an NMI or IRQ0 to IRQ15 interrupt request signal is input, clock oscillation starts, and

after the elapse of the time set in bits STS2 to STS0 in SBYCR, stable clocks ar e su pplied to

the entire LSI, software standby mode is cleared, and interrupt exception handling is started.

When clearing software standby mode with an IRQ0 to IRQ15 interrupt, set the corresponding

enable bit to 1 and ensure that no interrupt with a high er pr iority than interrupts IRQ0 to

Section 22 Power-Down Modes

Rev. 3.00 Mar 17, 2006 page 827 of 926

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IRQ15 is generated. Software standby mode cannot be cleared if the interrupt has been masked

on the CPU side or has been designated as a DTC activation source.

• Clearing with the RES Pin

When the RES pin is dr iven low, clock oscillation is started. At the same time as clock

oscillation starts, clocks are supplied to the entire LSI. Note that the RES pin must be held low

until clock oscillation stabilizes. When the RES pin goes high, the CPU begins reset exception

handling.

• Clearing with the STBY Pin

When the STBY pin is driven low, a transition is made to hardware standby mode.

Setting Oscillat ion Stabilizatio n Time after Clearing Software Sta ndby Mode: Bits STS3 to

STS0 in SBYCR should be set as described below.

• Using a Crystal Oscillator

Set bits STS3 to STS0 so that the standby time is more than the oscillation stabilization time.

Table 22.2 shows the standby times for operating frequencies and settings of bits STS3 to

STS0.

• Using an External Clock

A PLL circuit stabilization time is necessary. Refe r to table 22.2 to set the wait tim e.

Section 22 Power-Down Modes

Rev. 3.00 Mar 17, 2006 page 828 of 926

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Table 22.2 Oscilla tion Stabilization Time Settings

φφ

φ* [MH z]

STS3 STS2 STS1 STS0 Standby

Time 33 25 20 13 10 8 Unit

0000Reserved——————µs

1 Reserved ——————

1 0 Reserved ——————

1 Reserved ——————

1 0 0 Reserved ——————

1 64 1.9 2.6 3.2 4.9 6.4 8.0

1 0 512 15.5 20.5 25.6 39.4 51.2 64.0

1 1024 31.0 41.0 51.2 78.8 102.4 128.0

1 0 0 0 2048 62.1 81.9 102.4 157.5 204.8 256.0

1 4096 0.12 0.16 0.20 0.32 0.41 0.51 ms

1 0 16384 0.50 0.66 0.82 1.26 1.64 2.05

1 32765 0.99 1.31 1.64 2.52 3.28 4.10

1 0 0 65536 1.99 2.62 3.28 5.04 6.55 8.19

1 131072 3.97 5.24 6.55 10.08 13.11 16.38

1 0 262144 7.94 10.49 13.11 20.16 26.21 32.77

1 524288 15.89 20.97 26.21 40.33 52.43 65.54

: Recommended time setting

Note: *φ is the frequency divider output.

Software Standby Mode Applica tion Example: Figure 22.2 shows an ex ample in which a

transition is made to software standby mode at the falling edge on the NMI pin, and software

standby mode is cleared at the rising edge on the NMI pin.

In this example, an NMI interrupt is accepted with the NMIEG bit in INTCR cleared to 0 (falling

edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set

to 1, and a SLEEP instruction is executed, causing a transition to software standby mode.

Software standby mode is then cleared at the rising edge on the NMI pin.

Section 22 Power-Down Modes

Rev. 3.00 Mar 17, 2006 page 829 of 926

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Oscillator

NMI

NMIEG

SSBY

NMI exception

handling

NMIEG=1

SSBY=1

SLEEP instruction

Software standby mode

(power-down mode) Oscillation

stabilization

time tOSC2

NMI exception

handling

Figure 22.2 Software Standby Mode Application Exa mple

22.2.4 Hardware Standby Mo de

Transition to H ardware Standby Mode: When the STBY pin is dr iven low, a transition is m a de

to hardware standby mode from any mode.

In hardware standby mode, all functions enter the reset state and stop operation, resulting in a

significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip

RAM data is retained. I /O ports are set to the high -impedance state.

In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before

driving the STBY pin low. Do not change the state of th e mode pins (MD2 to MD0) while this

LSI is in hardware standby mode.

Clearing Hardware Standby Mode: Hardware standby mode is cleared by means of the STBY

pin and the RES pin. When the STBY pin is driven high while the RES pin is low, the reset state is

set and clock oscillation is started. En sure that the RES pin is held low until the clock oscillator

stabilizes (for details on the oscillatio n stabilization time, r efer to table 22.2). When the RES pin is

Section 22 Power-Down Modes

Rev. 3.00 Mar 17, 2006 page 830 of 926

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subsequently driven high, a transition is made to the program execution state via the reset

exception handling state.

Hardware Standby Mode Tim ing: Figure 22.3 shows an example of hardware standby mode

timing.

When the STBY pin is dr iven low after the RES pin has been driven low, a transition is made to

hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high, waiting

for the oscillation stabilization time, then ch angin g the RES pin from low to high.

Oscillator

RES

STBY

Oscillation

stabilization

time

Reset

exception

handling

Figure 22.3 Hardware Standby Mode Timing

22.2.5 Module Stop Mode

Module stop mode can be set for individual on-chip peripheral modules.

When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of

the bus cycle and a transition is made to module stop mode. The CPU continues operating

independently.

When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module

starts operating at the end of the bus cycle. In module stop mode, the internal states of modules

other than the SCI are retained.

After reset clearance, all modules other than the EXDMAC, DMAC, and DTC are in module stop

mode.

The module registers which are set in module stop mode cannot be read or written to.

Section 22 Power-Down Modes

Rev. 3.00 Mar 17, 2006 page 831 of 926

REJ09B0283-0300

22.2.6 All-Module-Clocks-Stop Mode

When the ACSE bit in MSTPCRH is set to 1 and module stop mode is set for all the on-chip

peripheral functions controlled by MSTPCR (MSTPCR = H'FFFF), or for all the on-chip

peripheral functions except the 8-b it timer (MSTPCR = H'FFFE), executin g a SLEEP instruction

while the SSBY bit in SBYCR is cleared to 0 will cause all the on- chip peripheral functions

(except the 8-b it timer and watchdog timer), th e bus controller, and the I/O ports to stop operating,

and a transition to be made to all-module-clocks-stop mode, at the end of the bus cycle.

Operation or halting of the 8-bit timer can be selected by means of the MSTP0 bit.

All-module-clocks-stop mode is cleared by an external interrupt (NMI, IRQ0 to IRQ15 pins), RES

pin input, or an internal interrupt (8-bit timer, watchdog timer), and the CPU returns to the normal

program execution state via the exception handling state. All-module-clocks-stop mode is not

cleared if interrupts are disabled, if interrupts other than NMI are masked by the CPU, or if the

relevant interrupt is designated as a DTC activation source.

When the STBY pin is driven low, a transition is made to hardware standby mode.

22.3 φ

φφ

φ Clock Output Control

Output of the φ clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the

correspo nding port. When the PSTOP bit is set to 1, the φ clock stops at the end of the bus cycle,

and φ output goes high. φ clock output is enabled when the PSTOP bit is cleared to 0. When DDR

for the corresponding port is cleared to 0, φ clock output is disabled and input port mode is set.

Table 22.3 shows the state of the φ pin in each processing state.

Table 22.3 φ

φφ

φ Pin State in Ea ch P r ocessing State

DDR PSTOP Normal

operating state Sleep mode Software

standby mode Hardware

standby mode All-module-

clocks-stop mode

0 X High im pedance High impedance High i m pedance High impedanc e High impedance

10 φ output φ output Fixed high High impedanc e φ output

1 1 Fix ed high Fix ed high Fixed high High i m pedance Fixed high

Section 22 Power-Down Modes

Rev. 3.00 Mar 17, 2006 page 832 of 926

REJ09B0283-0300

22.4 Usage Notes

22.4.1 I/O Port Status

In software standby mode, I/O port states are retained. Therefore, there is no reduction in current

dissipation for the output current when a high-level signal is output.

22.4.2 Current Dissipation during Oscillation Sta biliza t ion Standby Period

Current dissipation increases during the oscillation stabilization standby period.

22.4.3 EXDMAC/DMAC/DTC Module Stop

Depending on the operating status of the EXDMAC, DMAC, or DTC, the MSTP14 to MSTP12

bits may not be set to 1. Setting of the EXDMAC, DMAC, or DTC module stop mode should be

carried out only when the respective module is not activated.

For details, ref er to section 8, EXDMA Contr oller, section 7, DMA Con tr oller (DMAC), and

section 9, Data Transfer Controller (DTC).

22.4.4 On-Chip Peripheral Module Interrupts

Relevant interrupt operations cannot be performed in module stop mode. Consequently, if module

stop mod e is entered when an interrupt ha s been requested, it will not b e possible to clear the CPU

interrupt source or the EXDMAC, DMAC, or DTC activation source.

Interrupts should therefore be disabled before entering module stop mode.

22.4.5 Writing to MSTPCR

MSTPCR should only be written to by the CPU.

Section 23 Li st of Registers

Rev. 3.00 Mar 17, 2006 page 833 of 926

REJ09B0283-0300

Section 23 List of Regi sters

This section gives information on the on -chip I/O registers and is configured as described below.

1. Register Addresses (by functional module, in order of the corresponding section numbers)

• Descriptions by functional module, in order of the corresponding section numbers

Entries that consist of  lines are fo r separation of the functiona l m odules.

• Access to reserved addresses which are not described in th is list is prohibited.

• When registers consist of 16 or 32 bits, the addresses of the MSBs are given, on the

presumption of a big-endi an system.

2. Register Bits

• Bit configurations of the registers are described in the same order as the Register Addresses

(by functional module, in order of the corresponding section numbers).

• Reserved bits are indicated by  in the bit name.

• No entry in the bit-name column indicates that the whole register is allocated as a counter or

for holding data.

• When registers consist of 16 or 32 bits, bits are described from the MSB side.

The order in which bytes are described is on the presumption of a big-endian system.

3. Register States in Each Operating Mode

• Register states are described in the same order as the Register Addresses (by functional

module, in order of the corresponding section numbers).

• For the initial state of each bit, refer to the description of the register in the corresponding

section.

• The register states described are for the basic operating modes. If there is a specific reset for an

on-chip module, refer to the section on that on-chip module.

23.1 Register Addresses

(by functional module, in order of the corresponding section

numbers)

Entries under Access size indicates numbers of bits.

Note: Access to undefined or reserved addresses is prohibited. Since operation or continued

operation is not guaranteed when these registers are accessed, do not attempt such access.

Section 23 Li st of Registers

Rev. 3.00 Mar 17, 2006 page 834 of 926

REJ09B0283-0300

tion Bit No. Address Module Data

Width Access

States

DTC mode register A MRA 8 H'BC00 t o DTC 16/32 2

DTC source address register SAR 24 H' B FFF DTC 16/32 2

DTC mode register B MRB 8 DTC 16/ 32 2

DTC destination address regi st er DAR 24 DTC 16/32 2

DTC transfer count register A CRA 16 DTC 16/ 32 2

DTC transfer count register B CRB 18 DTC 16/ 32 2

Serial expansi on mode regist er*1SEMR 8 H'FDA8 SCI_2 8 2

EXDMA source address regist er_0 EDSAR_0 32 H'FDC0 EXDMAC_0 16 2

EXDMA destination address register_0 EDDA R_0 32 H'FDC4 E XDMAC_0 16 2

EXDMA transfer count register_0 EDTCR_0 32 H'FDC8 EXDMAC_0 16 2

EXDMA mode control register_0 EDMDR_0 16 H'FDCC EXDMAC_0 16 2

EXDMA address control regis ter_0 E DACR_0 16 H'FDCE EXDMA C_0 16 2

EXDMA source address regist er_1 EDSAR_1 32 H'FDD0 EXDMAC_1 16 2

EXDMA destination address register_1 EDDA R_1 32 H'FDD4 E XDMAC_1 16 2

EXDMA transfer count register_1 EDTCR_1 32 H'FDD8 EXDMAC_1 16 2

EXDMA mode control register_1 EDMDR_1 16 H'FDDC EXDMAC_1 16 2

EXDMA address control regis ter_1 E DACR_1 16 H'FDDE EXDMA C_1 16 2

EXDMA source address regist er_2 EDSAR_2 32 H'FDE0 EX DMAC_2 16 2

EXDMA destination address register_2 EDDA R_2 32 H'FDE4 EX DMAC_2 16 2

EXDMA transfer count register_2 EDTCR_2 32 H'FDE8 EXDMAC_2 16 2

EXDMA mode control register_2 EDMDR_2 16 H'FDEC EXDMAC_2 16 2

EXDMA address control regis ter_2 E DACR_2 16 H'FDEE E XDMAC_2 16 2

EXDMA source address register_3 EDSAR_3 32 H'FDF0 EXDMAC_3 16 2

EXDMA destinati on address regi ster_3 EDDAR_3 32 H'FDF4 E X DMAC_3 16 2

EXDMA transfer count register 3 EDTCR_3 32 H'FDF8 EXDMAC_3 16 2

EXDMA mode control register 3 EDMDR_3 16 H'FDFC EXDMAC_3 16 2

EXDMA address control register 3 EDACR_3 16 H'FDFE EXDMAC_3 1 6 2

Interrupt pri ority regi ster A IPRA 16 H'FE0 0 INT 16 2

Interrupt pri ority regi ster B IPRB 16 H'FE0 2 INT 16 2

Interrupt pri ority regi ster C IPRC 16 H'F E04 INT 16 2

Interrupt pri ority regi ster D IPRD 16 H'F E06 INT 16 2

Interrupt pri ority regi ster E IPRE 16 H'FE0 8 INT 16 2

Interrupt pri ority regi ster F IPRF 16 H'FE0A INT 16 2

Section 23 Li st of Registers

Rev. 3.00 Mar 17, 2006 page 835 of 926

REJ09B0283-0300

tion Bit No. Address Module Data

Width Access

States

Interrupt pri ority regi ster G IPRG 16 H'FE0C INT 16 2

Interrupt pri ority regi ster H IPRH 16 H'F E0E INT 16 2

Interrupt pri ority regi ster I IPRI 16 H'FE 10 INT 16 2

Interrupt pri ority regi ster J IPRJ 16 H'FE12 INT 16 2

Interrupt pri ority regi ster K IPRK 16 H'FE1 4 INT 16 2

IRQ pin select register ITS R 16 H'FE16 INT 16 2

Software standby release IRQ enable

IRQ sense control register H I S CRH 16 H'FE1A I NT 16 2

IRQ sense control register L ISCRL 16 H'FE1C INT 16 2

IrDA control register_0 IrCR_0 8 H'FE1E IrDA_0 8 2

Port 1 data direction register P1DDR 8 H'FE20 PORT 8 2

Port 2 data direction register P2DDR 8 H'FE21 PORT 8 2

Port 3 data direction register P3DDR 8 H'FE22 PORT 8 2

Port 5 data direction register P5DDR 8 H'FE24 PORT 8 2

Port 6 data direction register P6DDR 8 H'FE25 PORT 8 2

Port 7 data direction register P7DDR 8 H'FE26 PORT 8 2

Port 8 data direction register P8DDR 8 H'FE27 PORT 8 2

Port A data directi on regis t er PADDR 8 H'F E29 PORT 8 2

Port B data directi on regis t er PBDDR 8 H'F E2A PORT 8 2

Port C data directi on regist er P CDDR 8 H'FE2B PORT 8 2

Port D data directi on regist er P DDDR 8 H'FE2C P ORT 8 2

Port E data directi on regis t er PEDDR 8 H'F E2D PORT 8 2

Port F data direction regis t er P F DDR 8 H'FE 2E PORT 8 2

Port G data direction register PGDDR 8 H'FE2F PORT 8 2

Port function control register 0 PFCR0 8 H'FE32 PORT 8 2

Port function control register 1 PFCR1 8 H'FE33 PORT 8 2

Port function control register 2 PFCR2 8 H'FE34 PORT 8 2

Port A pull-up MOS control register P APCR 8 H'FE36 PORT 8 2

Port B pull-up MOS control register P BPCR 8 H'FE37 PORT 8 2

Port C pull-up MOS control register PCPCR 8 H'FE38 PORT 8 2

Port D pull-up MOS control register PDPCR 8 H'FE39 PORT 8 2

Port E pull-up MOS control register P EPCR 8 H'FE3A PORT 8 2

Section 23 Li st of Registers

Rev. 3.00 Mar 17, 2006 page 836 of 926

REJ09B0283-0300

tion Bit No. Address Module Data

Width Access

States

Port 3 open drain control regist er P3ODR 8 H'FE3C PORT 8 2

Port A open drain control register PAO DR 8 H'FE 3D PORT 8 2

Timer control register_3 TCR_3 8 H'FE80 TPU_3 16 2

Timer mode register_3 TMDR_3 8 H'FE81 TPU_3 16 2

Timer I/O control regis t er H_3 TI O RH_3 8 H'FE82 TPU_3 16 2

Timer I/O control register L_3 TIORL_3 8 H'FE83 TPU_3 16 2

Timer interrupt enable regist er_3 TIER_3 8 H'FE84 TPU_3 16 2

Timer status register_3 TSR_3 8 H'FE85 TPU_3 16 2

Timer counter_3 TCNT_3 16 H'FE86 TPU_3 16 2

Timer general register A_3 TGRA_3 16 H'F E 88 TPU_3 16 2

Timer general register B_3 TGRB_3 16 H'F E 8A TPU_3 16 2

Timer general register C_3 T GRC_3 16 H'FE8C TPU_3 16 2

Timer general register D_3 T GRD_3 16 H'FE8E TPU_3 16 2

Timer control register_4 TCR_4 8 H'FE90 TPU_4 16 2

Timer mode register_4 TMDR_4 8 H'FE91 TPU_4 16 2

Timer I/O control register_4 TIOR_4 8 H'FE92 TPU_4 16 2

Timer interrupt enable regist er_4 TIER_4 8 H'FE94 TPU_4 16 2

Timer status register_4 TSR_4 8 H'FE95 TPU_4 16 2

Timer counter_4 TCNT_4 16 H'FE96 TPU_4 16 2

Timer general register A_4 TGRA_4 16 H'F E 98 TPU_4 16 2

Timer general register B_4 TGRB_4 16 H'F E 9A TPU_4 16 2

Timer control register_5 TCR_5 8 H'FEA0 TPU_5 16 2

Timer mode register_5 TMDR_5 8 H'FEA1 TPU_5 16 2

Timer I/O control register_5 TI OR_5 8 H'FEA2 TPU_5 16 2

Timer interrupt enable register_5 TIER_5 8 H'FEA4 TPU_5 16 2

Timer status register_5 TSR_5 8 H'FEA5 TPU_5 16 2

Timer counter_5 TCNT_5 16 H'FEA6 TPU_5 16 2

Timer general register A_5 TGRA _5 16 H'FEA8 TPU_5 16 2

Timer general register B_5 TGRB_5 16 H'F E AA TP U_5 16 2

Bus width cont rol register AB WCR 8 H'FEC0 BSC 16 2

Access st ate control register AS T CR 8 H'FEC1 BSC 16 2

Wait control register AH WTCRAH 8 H'FEC2 BSC 16 2

Wait control register AL WTCRA L 8 H'FEC3 BS C 16 2

Section 23 Li st of Registers

Rev. 3.00 Mar 17, 2006 page 837 of 926

REJ09B0283-0300

tion Bit No. Address Module Data

Width Access

States

Wait control register BH WTCRBH 8 H'FEC4 BSC 16 2

Wait control register BL WTCRB L 8 H'FEC5 BS C 16 2

Read strobe timing control register RDNCR 8 H'FEC6 BSC 16 2

Chip select assertion period control

registers H CSACRH 8 H'FEC8 BSC 16 2

Chip select assertion period control

Burst ROM interfac e control regi ster H BROMCRH 8 H'FECA BSC 16 2

Burst ROM interfac e control regi ster L BROMCRL 8 H'FE CB BS C 16 2

Bus control register BCR 16 H'FECC BSC 16 2

RAM emulati on register *3RAMER 8 H'FECE FLASH 16 2

DRAM control regist er L DRAMCR 16 H'F E D0 BS C 16 2

DRAM access cont rol register DRACCR 8/16*2H'FED2 BSC 16 2

Refresh control register REFCR 16 H'FED4 BSC 16 2

Refresh timer counter RTCNT 8 H'FED6 BSC 16 2

Refresh time constant regist er RTCOR 8 H'FED7 BSC 16 2

Memory address regis t er 0AH MAR0A H 16 H'FEE0 DMAC 16 2

Memory address regis t er 0AL M AR_0AL 16 H'FEE2 DMAC 16 2

I/O address regist er 0A IOAR_0A 16 H'FEE4 DMAC 16 2

Transfer count register 0A ETCR_0A 16 H'FEE6 DMAC 16 2

Memory address regis t er 0BH MAR_0B H 16 H'FEE8 DMAC 16 2

Memory address register 0BL MAR_0BL 16 H'F E EA DMAC 1 6 2

I/O address regist er 0B IOAR_0B 16 H'FEEC DMAC 16 2

Transfer count register 0B ETCR_0B 16 H'FEEE DMAC 16 2

Memory address register 1AH M AR_1AH 16 H'FEF0 DMAC 16 2

Memory address register 1AL MAR_1AL 16 H'F E F 2 DMAC 16 2

I/O address regist er 1A IOAR_1A 16 H'FEF4 DMAC 16 2

Transfer count register 1A ETCR_1A 16 H'FEF6 DMAC 16 2

Memory address register 1BH M AR_1BH 16 H'FEF8 DMAC 16 2

Memory address register 1BL MAR_1BL 16 H'F E FA DMAC 16 2

I/O address regist er 1B IOAR_1B 16 H'FEFC DMAC 16 2

Transfer count register 1B ETCR_1B 16 H'FEFE DMAC 16 2

DMA write enable regist er DMA WER 8 H'FF20 DMAC 8 2

Section 23 Li st of Registers

Rev. 3.00 Mar 17, 2006 page 838 of 926

REJ09B0283-0300

tion Bit No. Address Module Data

Width Access

States

DMA terminal control register DMATCR 8 H'FF21 DMAC 8 2

DMA control register 0A DMACR_0A 8 H'FF22 DMAC 16 2

DMA control register 0B DMACR_0B 8 H'FF23 DMAC 16 2

DMA control register 1A DMACR_1A 8 H'FF24 DMAC 16 2

DMA control register 1B DMACR_1B 8 H'FF25 DMAC 16 2

DMA band control register H DMABCRH 8 H'FF26 DMA C 16 2

DMA band control register L DMAB CRL 8 H'FF27 DMAC 16 2

DTC enable register A DTCERA 8 H'FF28 DTC 16 2

DTC enable register B DTCERB 8 H'FF29 DTC 16 2

DTC enable register C DTCERC 8 H'FF2A DTC 16 2

DTC enable register D DTCERD 8 H'FF2B DTC 16 2

DTC enable register E DTCERE 8 H'FF2C DTC 16 2

DTC enable register F DTCE RF 8 H'FF2D DTC 16 2

DTC enable register G DTCERG 8 H'FF2E DTC 16 2

DTC vector register DTVECR 8 H'FF30 DTC 16 2

Interrupt control register INTCR 8 H'FF31 INT 16 2

IRQ enable register IER 16 H'FF32 INT 16 2

IRQ status register ISR 16 H'FF34 INT 16 2

Standby control register SBYCR 8 H'FF3A SYSTEM 8 2

System clock control register SCKCR 8 H'FF3B SYSTEM 8 2

System control register SYSCR 8 H'FF3D SYSTEM 8 2

Mode control register MDCR 8 H'FF3E SYSTEM 8 2

Module stop control register H MSTPCRH 8 H'FF40 SYSTEM 8 2

Module stop control register L MSTPCRL 8 H'FF41 SYSTEM 8 2

PLL control register PLLCR 8 H'FF45 SYSTEM 8 2

PPG output control register PCR 8 H'FF46 PPG 8 2

PPG output mode register PMR 8 H'FF47 PPG 8 2

Next data enable regist er H NDERH 8 H'FF48 PPG 8 2

Next data enable regist er L NDERL 8 H'FF49 PPG 8 2

Output data register H PODRH 8 H'FF4A PPG 8 2

Output data register L P ODRL 8 H'FF4B PPG 8 2

Next data register H*4NDRH 8 H'FF4C PPG 8 2

Next data register L*4NDRL 8 H'FF4D PPG 8 2

Section 23 Li st of Registers

Rev. 3.00 Mar 17, 2006 page 839 of 926

REJ09B0283-0300

tion Bit No. Address Module Data

Width Access

States

Next data register H*4NDRH 8 H'FF4E PPG 8 2

Next data register L*4NDRL 8 H'FF4F PPG 8 2

Port 1 register P ORT1 8 H'FF50 PORT 8 2

Port 2 register P ORT2 8 H'FF51 PORT 8 2

Port 3 register P ORT3 8 H'FF52 PORT 8 2

Port 4 register P ORT4 8 H'FF53 PORT 8 2

Port 5 register P ORT5 8 H'FF54 PORT 8 2

Port 6 register P ORT6 8 H'FF55 PORT 8 2

Port 7 register P ORT7 8 H'FF56 PORT 8 2

Port 8 register P ORT8 8 H'FF57 PORT 8 2

Port A register PO R TA 8 H'FF59 PORT 8 2

Port B register PO R TB 8 H'FF5A PORT 8 2

Port C register PORTC 8 H'FF5B PORT 8 2

Port D register PORTD 8 H'FF5C PORT 8 2

Port E register PO R TE 8 H'FF5D PORT 8 2

Port F register PORTF 8 H'FF5E PORT 8 2

Port G register PORTG 8 H'FF5F PORT 8 2

Port 1 data register P1DR 8 H'FF60 PORT 8 2

Port 2 data register P2DR 8 H'FF61 PORT 8 2

Port 3 data register P3DR 8 H'FF62 PORT 8 2

Port 5 data register P5DR 8 H'FF64 PORT 8 2

Port 6 data register P6DR 8 H'FF65 PORT 8 2

Port 7 data register P7DR 8 H'FF66 PORT 8 2

Port 8 data register P8DR 8 H'FF67 PORT 8 2

Port A data register PADR 8 H' FF69 PORT 8 2

Port B data register PBDR 8 H' FF6A PORT 8 2

Port C data register PCDR 8 H' FF6B PORT 8 2

Port D data register PDDR 8 H' FF6C PORT 8 2

Port E data register PEDR 8 H' FF6D PORT 8 2

Port F data register PFDR 8 H'FF6E PORT 8 2

Port G data register PGDR 8 H'FF6F PORT 8 2

Port H register PORTH 8 H'FF70 PORT 8 2

Port H data register PHDR 8 H' FF72 PORT 8 2

Section 23 Li st of Registers

Rev. 3.00 Mar 17, 2006 page 840 of 926

REJ09B0283-0300

tion Bit No. Address Module Data

Width Access

States

Port H data directi on regist er P HDDR 8 H'FF74 PORT 8 2

Serial mode register_0 SMR_0 8 H'FF78 SCI_0 8 2

Bit rate regist er_0 BRR_0 8 H'FF79 SCI_0 8 2

Serial control register_0 SCR_0 8 H'FF7A SCI_0 8 2

Transmit data register_0 TDR_0 8 H'FF7B SCI_0 8 2

Serial status register_0 SSR_0 8 H'FF7C SCI_0 8 2

Receive data register_0 RDR_0 8 H'FF7D SCI_0 8 2

Smart card mode register_0 SCMR_0 8 H'FF7E SCI_0 8 2

Serial mode register_1 SMR_1 8 H'FF80 SCI_1 8 2

Bit rate regist er_1 BRR_1 8 H'FF81 SCI_1 8 2

Serial control register_1 SCR_1 8 H'FF82 SCI_1 8 2

Transmit data register_1 TDR_1 8 H'FF83 SCI _1 8 2

Serial status register_1 SSR_1 8 H'FF84 SCI_1 8 2

Receive data register_1 RDR_1 8 H'FF85 SCI_1 8 2

Smart card mode register_1 SCMR_1 8 H'FF86 SCI _1 8 2

Serial mode register_2 SMR_2 8 H'FF88 SCI_2 8 2

Bit rate regist er_2 BRR_2 8 H'FF89 SCI_2 8 2

Serial control register_2 SCR_2 8 H'FF8A SCI_2 8 2

Transmit data register_2 TDR_2 8 H'FF8B SCI_2 8 2

Serial status register_2 SSR_2 8 H'FF8C SCI_2 8 2

Receive data register_2 RDR_2 8 H'FF8D SCI_2 8 2

Smart card mode register_2 SCMR_2 8 H'FF8E SCI_2 8 2

A/D data register A

(H8S/2678R Group) ADDRA 16 H'FF90 A/D 16 2

A/D data register AH

(H8S/2678 Group) ADDRAH 8 H'FF90 A/D 8 2

A/D data register AL

(H8S/2678 Group) ADDRAL 8 H'FF91 A/D 8 2

A/D data register B

(H8S/2678R Group) ADDRB 16 H'FF92 A/D 16 2

A/D data register BH

(H8S/2678 Group) ADDRBH 8 H'FF92 A/D 8 2

A/D data register BL

(H8S/2678 Group) ADDRBL 8 H'FF93 A/D 8 2

Section 23 Li st of Registers

Rev. 3.00 Mar 17, 2006 page 841 of 926

REJ09B0283-0300

tion Bit No. Address Module Data

Width Access

States

A/D data register C

(H8S/2678R Group) ADDRC 16 H'FF94 A/D 16 2

A/D data register CH

(H8S/2678 Group) ADDRCH 8 H'FF94 A/D 8 2

A/D data register CL

(H8S/2678 Group) ADDRCL 8 H'FF95 A/D 8 2

A/D data register D

(H8S/2678R Group) ADDRD 16 H'FF96 A/D 16 2

A/D data register DH

(H8S/2678 Group) ADDRDH 8 H'FF96 A/D 8 2

A/D data register DL

(H8S/2678 Group) ADDRDL 8 H'FF97 A/D 8 2

A/D control/status register

(H8S/2678 Group) ADCSR 8 H'FF98 A/D 8 2

A/D data register E

(H8S/2678R Group) ADDRE 16 H'FF98 A/D 16 2

A/D control register

(H8S/2678 Group) ADCR 8 H'FF99 A/D 8 2

A/D data register F

(H8S/2678R Group) ADDRF 16 H'FF9A A/D 16 2

A/D data register G

(H8S/2678R Group) ADDRG 16 H'FF9C A/D 16 2

A/D data register H

(H8S/2678R Group) ADDRH 16 H'FF9E A/D 16 2

A/D control/status register

(H8S/2678R Group) ADCSR 8 H'FFA0 A/D 16 2

A/D control register

(H8S/2678R Group) ADCR 8 H'FFA1 A/D 16 2

D/A data register 0 DADR0 8 H'FFA4 D/A 8 2

D/A data register 1 DADR1 8 H'FFA5 D/A 8 2

D/A control regist er 01 DACR01 8 H'FFA6 D/A 8 2

D/A data register 2 DADR2 8 H'FFA8 D/A 8 2

D/A data register 3 DADR3 8 H'FFA9 D/A 8 2

D/A control regist er 23 DACR23 8 H'FFAA D/A 8 2

Timer control register 0 TCR_0 8 H'FFB0 TMR_0 16 2

Timer control register 1 TCR_1 8 H'FFB1 TMR_1 16 2

Section 23 Li st of Registers

Rev. 3.00 Mar 17, 2006 page 842 of 926

REJ09B0283-0300

tion Bit No. Address Module Data

Width Access

States

Timer control/stat us register 0 T CSR_0 8 H'FFB2 TMR_0 16 2

Timer control/stat us register 1 T CSR_1 8 H'FFB3 TMR_1 16 2

Time constant register A0 TCORA_0 8 H' FFB 4 TMR_0 16 2

Time constant register A1 TCORA_1 8 H' FFB 5 TMR_1 16 2

Time constant register B0 TCORB_0 8 H' FFB 6 TMR_0 16 2

Time constant register B1 TCORB_1 8 H' FFB 7 TMR_1 16 2

Timer counter 0 TCNT_0 8 H'FFB8 TMR_0 16 2

Timer counter 1 TCNT_1 8 H'FFB9 TMR_1 16 2

Timer control/status register TCSR 8 H'FFBC*4

(Write) WDT 16 2

H'FFBC

(Read)

Timer counter TCNT 8 H'FFBC*4

(Write) WDT 16 2

H'FFBD

(Read)

Reset control/status register RSTCSR 8 H'FFBE*4

(Write) WDT 16 2

H'FFBF

(Read)

Timer start register TSTR 8 H'FFC0 TPU 16 2

Timer synchronous register TSYR 8 H'FFC1 TPU 16 2

Flash memory control register 1*3FLMCR1 8 H'FFC8 FLASH 8 2

Flash memory control register 2*3FLMCR2 8 H'FFC9 FLASH 8 2

Erase block register 1*3EBR1 8 H'FFCA FLASH 8 2

Erase block register 2*3EBR2 8 H'FFCB FLASH 8 2

Timer control register_0 TCR_0 8 H'FFD0 TPU_0 16 2

Timer mode register_0 TMDR_0 8 H'FFD1 TPU_0 16 2

Timer I/O control register H_0 TIORH_0 8 H'FFD2 TPU_0 16 2

Timer I/O control register L_0 TIORL_0 8 H'FFD3 TPU_0 16 2

Timer interrupt enable regist er_0 TIER_0 8 H'FFD4 TPU_0 16 2

Timer status register_0 TSR_0 8 H'FFD5 TPU_0 16 2

Timer counter_0 TCNT_0 16 H'FFD6 TPU_0 16 2

Timer general register A_0 TGRA _0 16 H'FFD8 TPU_0 16 2

Section 23 Li st of Registers

Rev. 3.00 Mar 17, 2006 page 843 of 926

REJ09B0283-0300

tion Bit No. Address Module Data

Width Access

States

Timer general register B_0 TGRB _0 16 H'FFDA TPU_0 16 2

Timer general register C_0 TGRC_0 16 H'FFDC TPU_0 16 2

Timer general register D_0 TGRD_0 16 H'FFDE TPU_0 16 2

Timer control register_1 TCR_1 8 H'FFE0 TPU_1 16 2

Timer mode register_1 TMDR_1 8 H'FFE1 TPU_1 16 2

Timer I/O control register_1 TIOR_1 8 H'FFE2 TPU_1 16 2

Timer interrupt enable register_1 TIER_1 8 H'FFE4 TPU_1 16 2

Timer status register_1 TSR_1 8 H'FFE5 TPU_1 16 2

Timer counter_1 TCNT_1 16 H'FFE6 TPU_1 16 2

Timer general register A_1 TGRA _1 16 H'FFE8 TPU_1 16 2

Timer general register B_1 TGRB _1 16 H'FFEA TPU_1 16 2

Timer control register_2 TCR_2 8 H'FFF0 TPU_2 16 2

Timer mode register_2 TMDR_2 8 H'FFF1 TPU_2 16 2

Timer I/O control register_2 TIOR_2 8 H'FFF2 TPU_2 16 2

Timer interrupt enable register_2 TIER_2 8 H'FFF4 TP U_2 16 2

Timer status rgister_ 2 TSR_2 8 H'FFF5 TPU_2 16 2

Timer counter_2 TCNT_2 16 H'FFF6 TPU_2 16 2

Timer general register A_2 TGRA_2 16 H'FFF8 TPU_2 16 2

Timer general register B_2 TGRB_2 16 H'FFFA TPU_2 16 2

Notes: 1. Not available in the H8S/2678 Group.

2. In the H8S/2678 Group: 8 bits, in the H8S/2678R Group: 16 bits.

3. Register of the flash memory version. Not available in the masked ROM version and

ROM-less version.

4. If the pulse output group 2 and pulse output group 3 output triggers are the same

according to the PCR s e tting, the NDRH address will be H'FF4C, and if different, the

address of NDRH for group 2 will be H'FF4E, and that for group 3 will be H'FF4C.

Similarly, if the pulse output group 0 and pulse output group 1 output triggers are the

same according to the PCR setting, the NDRL address will be H'FF4D, and if different,

the address of NDRL for group 0 will be H'FF4F, and that for group 1 will be H'FF4D.

5. For writing, refer to section 14.6.1, Notes on Register Access.

Section 23 Li st of Registers

Rev. 3.00 Mar 17, 2006 page 844 of 926

REJ09B0283-0300

23.2 Register Bits

Each line covers eight bits, and 16-bit and 32-bit registers are shown as 2 or 4 lines, respectively.

Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

MRA AM1 SM0 DM1 DM0 MD1 MD0 DTS Sz DTC*9

SAR ————————

————————

MRB CHNE DISEL CHNS — — — — —

DAR ————————

————————

CRA ————————

————————

CRB ————————

————————

SEMR*8— — — — ABCS ACS2 ACS1 ACS0 SCI_2

Smart card

interface 2

EDSAR_0————————EXDMAC_0

EDDAR_0————————

EDTCR_0————————

EDA BEF EDRAKE ETENDE EDREQS AMS MDS1 MDS0EDMDR_0

EDIE IRF TCEIE SDIR DTSIZE BGUP — —

SAT1 SAT0 SARIE SARA4 SARA3 SARA2 SARA1 SARA0EDACR_0

DAT1 DAT0 DARIE DARA4 DARA3 DARA2 DARA1 DARA0

EDSAR_1————————

EDDAR_1————————

EDTCR_1————————

EDA BEF EDRAKE ETENDE EDREQS AMS MDS1 MDS0EDMDR_1

EDIE IRF TCEIE SDIR DTSIZE BGUP — —

SAT1 SAT0 SARIE SARA4 SARA3 SARA2 SARA1 SARA0EDACR_1

DAT1 DAT0 DARIE DARA4 DARA3 DARA2 DARA1 DARA0

EXDMAC_1

Section 23 Li st of Registers

Rev. 3.00 Mar 17, 2006 page 845 of 926

REJ09B0283-0300

Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

EDSAR_2————————

EDDAR_2————————

EDTCR_2————————

EDA BEF EDRAKE ETENDE EDREQS AMS MDS1 MDS0EDMDR_2

EDIE IRF TCEIE SDIR DTSIZE BGUP — —

SAT1 SAT0 SARIE SARA4 SARA3 SARA2 SARA1 SARA0EDACR_2

DAT1 DAT0 DARIE DARA4 DARA3 DARA2 DARA1 DARA0

EXDMAC_2

EDSAR_3————————

EDDAR_3————————

EDTCR_3————————

EDA BEF EDRAKE ETENDE EDREQS AMS MDS1 MDS0EDMDR_3

EDIE IRF TCEIE SDIR DTSIZE BGUP — —

SAT1 SAT0 SARIE SARA4 SARA3 SARA2 SARA1 SARA0EDACR_3

DAT1 DAT0 DARIE DARA4 DARA3 DARA2 DARA1 DARA0

EXDMAC_3

— IPRA14 IPRA13 IPRA12 — IPRA10 IPRA9 IPRA8 INTIPRA

— IPRA6 IPRA5 IPRA4 — IPRA2 IPRA1 IPRA0

— IPRB14 IPRB13 IPRB12 — IPRB10 IPRB9 IPRB8IPRB

— IPRB6 IPRB5 IPRB4 — IPRB2 IPRB1 IPRB0

— IPRC14 IPRC13 IPRC12 — IPRC10 IPRC9 IPRC8IPRC

— IPRC6 IPRC5 IPRC4 — IPRC2 IPRC1 IPRC0

— IPRD14 IPRD13 IPRD12 — IPRD10 IPRD9 IPRD8IPRD

— IPRD6 IPRD5 IPRD4 — IPRD2 IPRD1 IPRD0

— IPRE14 IPRE13 IPRE12 — IPRE10 IPRE9 IPRE8IPRE

— IPRE6 IPRE5 IPRE4 — IPRE2 IPRE1 IPRE0

— IPRF14 IPRF13 IPRF12 — IPRF10 IPRF9 IPRF8IPRF

— IPRF6 IPRF5 IPRF4 — IPRF2 IPRF1 IPRF0

— IPRG14 IPRG13 IPRG12 — IPRG10 IPRG9 IPRG8IPRG

— IPRG6 IPRG5 IPRG4 — IPRG2 IPRG1 IPRG0

— IPRH14 IPRH13 IPRH12 — IPRH10 IPRH9 IPRH8IPRH

— IPRH6 IPRH5 IPRH4 — IPRH2 IPRH1 IPRH0

— IPRI14 IPRI13 IPRI12 — IPRI10 IPRI9 IPRI8IPRI

— IPRI6 IPRI5 IPRI4 — IPRI2 IPRI1 IPRI0

— IPRJ14 IPRJ13 IPRJ12 — IPRJ10 IPRJ9 IPRJ8IPRJ

— IPRJ6 IPRJ5 IPRJ4 — IPRJ2 IPRJ1 IPRJ0

IPRK — IPRK14 IPRK13 IPRK12 — IPRK10 IPRK9 IPRK8

— IPRK6 IPRK5 IPRK4 — IPRK2 IPRK1 IPRK0

Section 23 Li st of Registers

Rev. 3.00 Mar 17, 2006 page 846 of 926

REJ09B0283-0300

Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

ITS15 ITS14 ITS13 ITS12 ITS11 ITS10 ITS9 ITS8 INT

ITSR

ITS7 ITS6 ITS5 ITS4 ITS3 ITS2 ITS1 ITS0

SSI15 SSI14 SSI13 SSI12 SSI11 SSI10 SSI9 SSI8SSIER

SSI7 SSI6 SSI5 SSI4 SSI3 SSI2 SSI1 SSI0

IRQ15SCB IRQ15SCA IRQ14SCB IRQ14SCA IRQ13SCB IRQ13SCA IRQ12SCB IRQ12SCAISCRH

IRQ11SCB IRQ11SCA IRQ10SCB IRQ10SCA IRQ9SCB IRQ9SCA IRQ8SCB IRQ8SCA

IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCAISCRL

IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA

IrCR_0 IrE IrCKS2 IrCKS1 IrCKS0 — — — — IrDA_0

P1DDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR

P2DDR P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR

P3DDR — — P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR

P5DDR — — — — P53DDR P52DDR P51DDR P50DDR

P6DDR — — P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR

P7DDR — — P75DDR P74DDR P73DDR P72DDR P71DDR P70DDR

P8DDR — — P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR

PADDR PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR

PBDDR PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR

PCDDR PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR

PDDDR PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR

PEDDR PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR

PFDDR PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR

PGDDR — PG6DDR PG5DDR PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR

PFCR0 CS7E CS6E CS5E CS4E CS3E CS2E CS1E CS0E

PFCR1 A23E A22E A21E A20E A19E A18E A17E A16E

PFCR2 — — — — ASOE LWROE OES DMACS

PAPCR PA7PCR PA6PCR PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR

PBPCR PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR

PCPCR PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR

PDPCR PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR

PEPCR PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR

P3ODR — — P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR

PAODR PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR

PORT

Section 23 Li st of Registers

Rev. 3.00 Mar 17, 2006 page 847 of 926

REJ09B0283-0300

Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

TCR_3 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_3

TMDR_3 — — BFB BFA MD3 MD2 MD1 MD0

TIORH_3 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0

TIORL_3 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0

TIER_3 TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA

TSR_3 — — — TCFV TGFD TGFC TGFB TGFA

TCNT_3 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8TGRA_3

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8TGRB_3

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8TGRC_3

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8TGRD_3

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

TCR_4 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0

TMDR_4 — — — — MD3 MD2 MD1 MD0

TIOR_4 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0

TIER_4 TTGE — TCIEU TCIEV — — TGIEB TGIEA

TSR_4 TCFD — TCFU TCFV — — TGFB TGFA

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8TCNT_4

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8TGRA_4

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8TGRB_4

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

TPU_4

TCR_5 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_5

TMDR_5 — — — — MD3 MD2 MD1 MD0

TIOR_5 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0

TIER_5 TTGE — TCIEU TCIEV — — TGIEB TGIEA

TSR_5 TCFD — TCFU TCFV — — TGFB TGFA

TCNT_5 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Section 23 Li st of Registers

Rev. 3.00 Mar 17, 2006 page 848 of 926

REJ09B0283-0300

Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

TGRA_5 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TPU_5

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8TGRB_5

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

ABWCR ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 BSC

ASTCR AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0

WTCRAH — W72 W71 W70 — W62 W61 W60

WTCRAL — W52 W51 W50 — W42 W41 W40

WTCRBH — W32 W31 W30 — W22 W21 W20

WTCRBL — W12 W11 W10 — W02 W01 W00

RDNCR RDN7 RDN6 RDN5 RDN4 RDN3 RDN2 RDN1 RDN0

CSACRH CSXH7 CSXH6 CSXH5 CSXH4 CSXH3 CSXH2 CSXH1 CSXH0

CSACRL CSXT7 CSXT6 CSXT5 CSXT4 CSXT3 CSXT2 CSXT1 CSXT0

BROMCRH BSRM0 BSTS02 BSTS01 BSTS00 — — BSWD01 BSWD00

BROMCRL BSRM1 BSTS12 BSTS11 BSTS10 — — BSWD11 BSWD10

BRLE BREQ0E — IDLC ICIS1 ICIS0 WDBE WAITEBCR

—————ICIS2*8——

RAMER*7— — — — RAMS RAM2 RAM1 RAM0 FLASH

0EE RAST — CAST — RMTS2 RMTS1 RMTS0DRAMCR

BE RCDM DDS EDDS — MXC2 MXC1 MXC0

DRACCR*1DRMI — TPC1 TPC0 SDWCD*8— RCD1 RCD0

————CKSPE*8—RDXC1*8RDXC0*8

CMF CMIE RCW1 RCW0 — RTCK2 RTCK1 RTCK0REFCR

RFSHE CBRM RLW1 RLW0 SLFRF TPCS2 TPCS1 TPCS0

RTCNT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

RTCOR Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

BSC

————————DMACMAR_0AH

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8MAR_0AL

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8IOAR_0A

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8ETCR_0A

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

MAR_0BH————————

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Section 23 Li st of Registers

Rev. 3.00 Mar 17, 2006 page 849 of 926

REJ09B0283-0300

Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 DMAC

MAR_0BL

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

IOAR_0B Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8ETCR_0B

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

————————MAR_1AH

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8MAR_1AL

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8IOAR_1A

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8ETCR_1A

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

————————MAR_1BH

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8MAR_1BL

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8IOAR_1B

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8ETCR_1B

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

DMAWER — — — — WE1B WE1A WE0B WE0A

DMATCR — — TEE1 TEE0 — — — —

DMACR_0A*11 DTSZ DTID RPE DTDIR DTF3 DTF2 DTF1 DTF0

DMACR_0A*12 DTSZ SAID SAIDE BLKDIR BLKE — — —

DMACR_0B*11 DTSZ DTID RPE DTDIR DTF3 DTF2 DTF1 DTF0

DMACR_0B*12 — DAID DAIDE — DTF3 DTF2 DTF1 DTF0

DMACR_1A*11 DTSZ DTID RPE DTDIR DTF3 DTF2 DTF1 DTF0

DMACR_1A*12 DTSZ SAID SAIDE BLKDIR BLKE — — —

DMACR_1B*11 DTSZ DTID RPE DTDIR DTF3 DTF2 DTF1 DTF0

DMACR_1B*12 — DAID DAIDE — DTF3 DTF2 DTF1 DTF0

DMABCRH*11 FAE1 FAE0 SAE1 SAE0 DTA1B DTA1A DTA0B DTA0A

DMABCRH*12 FAE1 FAE0 — — DTA1 — DTA0 —

DMABCRL*11 DTE1B DTE1A DTE0B DTE0A DTIE1B DTIE1A DTIE0B DTIE0A

DMABCRL*12 DTME1 DTE1 DTME0 DTE0 DTIE1B DTIE1A DTIE0B DTIE0A

Section 23 Li st of Registers

Rev. 3.00 Mar 17, 2006 page 850 of 926

REJ09B0283-0300

Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

DTCERA DTCEA7 DTCEA6 DTCEA5 DTCEA4 DTCEA3 DTCEA2 DTCEA1 DTCEA0

DTCERB DTCEB7 DTCEB6 DTCEB5 DTCEB4 DTCEB3 DTCEB2 DTCEB1 DTCEB0

DTCERC — DTCEC6 DTCEC5 DTCEC4 DTCEC3 DTCEC2 DTCEC1 DTCEC0

DTCERD DTCED7 DTCED6 DTCED5 DTCED4 DTCED3 DTCED2 DTCED1 DTCED0

DTCERE DTCEE7 DTCEE6 DTCEE5 DTCEE4 DTCEE3 DTCEE2 DTCEE1 DTCEE0

DTCERF DTCEF7 DTCEF6 DTCEF5 DTCEF4 DTCEF3 DTCEF2 DTCEF1 DTCEF0

DTCERG DTCEG7 DTCEG6 — — — — — —

DTVECR SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0

DTC*10

INTCR — — INTM1 INTM0 NMIEG — — —

IRQ15E IRQ14E IRQ13E IRQ12E IRQ11E IRQ10E IRQ9E IRQ8EIER

IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E

IRQ15F IRQ14F IRQ13F IRQ12F IRQ11F IRQ10F IRQ9F IRQ8FISR

IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F

INT

SBYCR SSBY OPE — — STS3 STS2 STS1 STS0

SCKCR PSTOP — — — STCS SCK2 SCK1 SCK0

SYSCR — — MACS — FLSHE — EXPE RAME

MDCR — — — — — MDS2 MDS1 MDS0

MSTPCRH ACSE MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8

MSTPCRL MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0

PLLCR——————STC1STC0

SYSTEM

PCR G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0

PMR G3INV G2INV G1INV G0INV G3NOV G2NOV G1NOV G0NOV

NDERH NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8

NDERL NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0

PODRH POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8

PODRL POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0

NDRH NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8

NDRL NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0

NDRH — — — — NDR11 NDR10 NDR9 NDR8

NDRL — — — — NDR3 NDR2 NDR1 NDR0

PPG

PORT1 P17 P16 P15 P14 P13 P12 P11 P10 PORT

PORT2 P27 P26 P25 P24 P23 P22 P21 P20

PORT3 — — P35 P34 P33 P32 P31 P30

PORT4 P47 P46 P45 P44 P43 P42 P41 P40

PORT5 P57 P56 P55 P54 P53 P52 P51 P50

Section 23 Li st of Registers

Rev. 3.00 Mar 17, 2006 page 851 of 926

REJ09B0283-0300

Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

PORT6 — — P65 P64 P63 P62 P61 P60 PORT

PORT7 — — P75 P74 P73 P72 P71 P70

PORT8 — — P85 P84 P83 P82 P81 P80

PORTA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0

PORTB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0

PORTC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

PORTD PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

PORTE PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0

PORTF PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0

PORTG — PG6 PG5 PG4 PG3 PG2 PG1 PG0

P1DR P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR

P2DR P27DR P26DR P25DR P24DR P23DR P22DR P21DR P20DR

P3DR — — P35DR P34DR P33DR P32DR P31DR P30DR

P5DR — — — — P53DR P52DR P51DR P50DR

P6DR — — P65DR P64DR P63DR P62DR P61DR P60DR

P7DR — — P75DR P74DR P73DR P72DR P71DR P70DR

P8DR — — P85DR P84DR P83DR P82DR P81RD P80DR

PADR PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR

PBDR PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR

PCDR PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR

PDDR PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR

PEDR PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR

PFDR PF7DR PF6DR PF5DR PF4DR PF3DR PF2DR PF1DR PF0DR

PGDR — PG6DR PG5DR PG4DR PG3DR PG2DR PG1DR PG0DR

PORTH — — — — PH3 PH2 PH1 PH0

PHDR — — — — PH3DR PH2DR PH1DR PH0DR

PHDDR — — — — PH3DDR PH2DDR PH1DDR PH0DDR

SMR_0 C/A/

GM*2CHR/

BLK*3PE O/ESTOP/

BCP1*4MP/

BCP0*5CKS1 CKS0

BRR_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SCI_0,

Smart card

interface 0

SCR_0 TIE RIE TE RE MPIE TEIE CKE1 CKE0

TDR_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SSR_0 TDRE RDRF ORER FER/

ERS*6PER TEND MPB MPBT

RDR_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SCMR_0————SDIRSINV—SMIF

Section 23 Li st of Registers

Rev. 3.00 Mar 17, 2006 page 852 of 926

REJ09B0283-0300

Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

SMR_1 C/A/

GM*2CHR/

BLK*3PE O/ESTOP/

BCP1*4MP/

BCP0*5CKS1 CKS0

BRR_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SCR_1 TIE RIE TE RE MPIE TEIE CKE1 CKE0

TDR_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SSR_1 TDRE RDRF ORER FER/

ERS*6PER TEND MPB MPBT

RDR_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SCMR_1————SDIRSINV—SMIF

SCI_1,

Smart card

interface 1

SMR_2 C/A/

GM*2CHR/

BLK*3PE O/ESTOP/

BCP1*4MP/

BCP0*5CKS1 CKS0

BRR_2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SCR_2 TIE RIE TE RE MPIE TEIE CKE1 CKE0

TDR_2

SSR_2 TDRE RDRF ORER FER/

ERS*6PER TEND MPB MPBT

RDR_2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SCMR_2————SDIRSINV—SMIF

SCI_2,

Smart card

interface 2

ADDRA AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 A/D

AD1AD0——————

ADDRB AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2

AD1AD0——————

ADDRC AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2

AD1AD0——————

ADDRD AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2

AD1AD0——————

ADDRE*8AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2

AD1AD0——————

ADDRF*8AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2

AD1AD0——————

ADDRG*8AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2

AD1AD0——————

ADDRH*8AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2

AD1AD0——————

ADCSR ADF ADIE ADST SCAN*9/

—*8CKS*9/

CH3*8CH2 CH1 CH0

ADCR TRGS1 TRGS0 —*9/

SCANE*8—*9/

SCANS*8CKS1 CH3*9/

CKS0*8——

Section 23 Li st of Registers

Rev. 3.00 Mar 17, 2006 page 853 of 926

REJ09B0283-0300

Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

DADR0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

DADR1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

DACR01 DAOE1 DAOE0 DAE — — — — —

DADR2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

DADR3 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

DACR23 DAOE3 DAOE2 DAE — — — — —

D/A

TCR_0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0

TCR_1 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0

TCSR_0 CMFB CMFA OVF ADTE OS3 OS2 OS1 OS0

TCSR_1 CMFB CMFA OVF — OS3 OS2 OS1 OS0

TCORA_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

TCORA_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

TCORB_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

TCORB_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

TCNT_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

TCNT_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

TMR_0

TMR_1

TCSR OVF WT/IT TME — — CKS2 CKS1 CKS0

TCNT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

RSTCSRWOVFRSTE——————

WDT

TSTR — — CST5 CST4 CST3 CST2 CST1 CST0

TSYR — — SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0

TPU

FLMCR1*7FWE SWE ESU PSU EV PV E P FLASH

FLMCR2*7FLER———————

EBR1*7EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0

EBR2*7— — EB13 EB12 EB11 EB10 EB9 EB8

TCR_0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_0

TMDR_0 — — BFB BFA MD3 MD2 MD1 MD0

TIORH_0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0

TIORL_0 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0

TIER_0 TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA

TSR_0 — — — TCFV TGFD TGFC TGFB TGFA

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8TCNT_0

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

TGRA_0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Section 23 Li st of Registers

Rev. 3.00 Mar 17, 2006 page 854 of 926

REJ09B0283-0300

Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TPU_0

TGRB_0

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8TGRC_0

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8TGRD_0

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

TCR_1 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0

TMDR_1 — — — — MD3 MD2 MD1 MD0

TIOR_1 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0

TIER_1 TTGE — TCIEU TCIEV — — TGIEB TGIEA

TSR_1 TCFD — TCFU TCFV — — TGFB TGFA

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8TCNT_1

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8TGRA_1

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8TGRB_1

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

TPU_1

TCR_2 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_2

TMDR_2 — — — — MD3 MD2 MD1 MD0

TIOR_2 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0

TIER_2 TTGE — TCIEU TCIEV — — TGIEB TGIEA

TSR_2 TCFD — TCFU TCFV — — TGFB TGFA

TCNT_2 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8TGRA_2

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8TGRB_2

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Notes: 1. In the H8S/2678 Group: 8 bits, in the H8S/2678R Group: 16 bits.

2. Functions as C/A for SCI use, and as GM for smart card interface use.

3. Functions as CHR for SCI use, and as BLK for smart card interface use.

4. Functions as STOP for SCI use, and as BCP1 for smart card interface use.

5. Functions as MP for SCI use, and as BCP0 for smart card interface use.

6. Functions as FER for SCI use, and as ERS for smart card interface use.

7. Register of the flash memory version. Not available in the masked ROM version and

ROM-less version.

8. Not available in the H8S/2678 Group.

9. Not available in the H8S/2678R Group.

Section 23 Li st of Registers

Rev. 3.00 Mar 17, 2006 page 855 of 926

REJ09B0283-0300

10.Loaded in on-chip RAM. The bus width is 32 bits when the DTC accesses this area as

11.For short address mode

12.For full address mode

Section 23 Li st of Registers

Rev. 3.00 Mar 17, 2006 page 856 of 926

REJ09B0283-0300

23.3 Register States in Each Operating Mode

Abbreviation Reset High-

Speed Clock

Division Sleep Module

Stop All Module

Clock Stop Software

Standby Hardware

Standby Module

MRA Initialized — — — — — — Initialized DTC

SAR Initialized — — — — — — Initialized

MRB Initialized — — — — — — Initialized

DAR Initialized — — — — — — Initialized

CRA Initialized — — — — — — Initialized

CRB Initialized — — — — — — Initialized

SEMR*1Initialized — — — Initialized Initialized Initialized Initialized SCI2

EDSAR_0 Initialized — — — — — — Initialized EXDMA_C

EDDAR_0 Initialized — — — — — — Initialized

EDTCR_0 Initialized — — — — — — Initialized

EDMDR_0 Initialized — — — — — — Initialized

EDACR_0 Initialized — — — — — — Initialized

EDSAR_1 Initialized — — — — — — Initialized EXDMA_1

EDDAR_1 Initialized — — — — — — Initialized

EDTCR_1 Initialized — — — — — — Initialized

EDMDR_1 Initialized — — — — — — Initialized

EDACR_1 Initialized — — — — — — Initialized

EDSAR_2 Initialized — — — — — — Initialized

EDDAR_2 Initialized — — — — — — Initialized

EDTCR_2 Initialized — — — — — — Initialized

EDMDR_2 Initialized — — — — — — Initialized

EDACR_2 Initialized — — — — — — Initialized

EXDMA_2

EDSAR_3 Initialized — — — — — — Initialized EXDMA_3

EDDAR_3 Initialized — — — — — — Initialized

EDTCR_3 Initialized — — — — — — Initialized

EDMDR_3 Initialized — — — — — — Initialized

EDACR_3 Initialized — — — — — — Initialized

IPRA Initialized — — — — — — Initialized INT

IPRB Initialized — — — — — — Initialized

IPRC Initialized — — — — — — Initialized

IPRD Initialized — — — — — — Initialized

IPRE Initialized — — — — — — Initialized

IPRF Initialized — — — — — — Initialized

Section 23 Li st of Registers

Rev. 3.00 Mar 17, 2006 page 857 of 926

REJ09B0283-0300

Abbreviation Reset High-

Speed Clock

Division Sleep Module

Stop All Module

Clock Stop Software

Standby Hardware

Standby Module

IPRG Initialized — — — — — — Initialized INT

IPRH Initialized — — — — — — Initialized

IPRI Initialized — — — — — — Initialized

IPRJ Initialized — — — — — — Initialized

IPRK Initialized — — — — — — Initialized

ITSR Initialized — — — — — — Initialized

SSIER Initialized — — — — — — Initialized

ISCRH Initialized — — — — — — Initialized

ISCRL Initialized — — — — — — Initialized

IrCR_0 Initialized — — — — — — Initialized IrDA_0

P1DDR — — — — — — — Initialized PORT

P2DDR— ————— —Initialized

P3DDR— ————— —Initialized

P5DDR— ————— —Initialized

P6DDR— ————— —Initialized

P7DDR— ————— —Initialized

P8DDR— ————— —Initialized

PADDR— ————— —Initialized

PBDDR— ————— —Initialized

PCDDR — — — — — — — Initialized

PDDDR — — — — — — — Initialized

PEDDR— ————— —Initialized

PFDDR— ————— —Initialized

PGDDR— ————— —Initialized

PFCR0— ————— —Initialized

PFCR1— ————— —Initialized

PFCR2— ————— —Initialized

PAPCR — — — — — — — Initialized

PBPCR — — — — — — — Initialized

PCPCR — — — — — — — Initialized

PDPCR — — — — — — — Initialized

PEPCR — — — — — — — Initialized

P3ODR — — — — — — — Initialized

PAODR— ————— —Initialized

Section 23 Li st of Registers

Rev. 3.00 Mar 17, 2006 page 858 of 926

REJ09B0283-0300

Abbreviation Reset High-

Speed Clock

Division Sleep Module

Stop All Module

Clock Stop Software

Standby Hardware

Standby Module

TCR_3 Initialized — — — — — — Initialized TPU_3

TMDR_3 Initialized — — — — — — Initialized

TIORH_3 Initialized — — — — — — Initialized

TIORL_3 Initialized — — — — — — Initialized

TIER_3 Initialized — — — — — — Initialized

TSR_3 Initialized — — — — — — Initialized

TCNT_3 Initialized — — — — — — Initialized

TGRA_3 Initialized — — — — — — Initialized

TGRB_3 Initialized — — — — — — Initialized

TGRC_3 Initialized — — — — — — Initialized

TGRD_3 Initialized — — — — — — Initialized

TCR_4 Initialized — — — — — — Initialized TPU_4

TMDR_4 Initialized — — — — — — Initialized

TIOR_4 Initialized — — — — — — Initialized

TIER_4 Initialized — — — — — — Initialized

TSR_4 Initialized — — — — — — Initialized

TCNT_4 Initialized — — — — — — Initialized

TGRA_4 Initialized — — — — — — Initialized

TGRB_4 Initialized — — — — — — Initialized

TCR_5 Initialized — — — — — — Initialized TPU_5

TMDR_5 Initialized — — — — — — Initialized

TIOR_5 Initialized — — — — — — Initialized

TIER_5 Initialized — — — — — — Initialized

TSR_5 Initialized — — — — — — Initialized

TCNT_5 Initialized — — — — — — Initialized

TGRA_5 Initialized — — — — — — Initialized

TGRB_5 Initialized — — — — — — Initialized

ABWCR Initialized — — — — — — Initialized BSC

ASTCR Initialized — — — — — — Initialized

WTCRAH Initialized — — — — — — Initialized

WTCRAL Initialized — — — — — — Initialized

WTCRBH Initialized — — — — — — Initialized

WTCRBL Initialized — — — — — — Initialized

RDNCR Initialized — — — — — — Initialized

CSACRH Initialized — — — — — — Initialized

Section 23 Li st of Registers

Rev. 3.00 Mar 17, 2006 page 859 of 926

REJ09B0283-0300

Abbreviation Reset High-

Speed Clock

Division Sleep Module

Stop All Module

Clock Stop Software

Standby Hardware

Standby Module

CSACRL Initialized — — — — — — Initialized BSC

BROMCRH Initialized — — — — — — Initialized

BROMCRL Initialized — — — — — — Initialized

BCR Initialized — — — — — — Initialized

RAMER*2Initialized — — — — — — Initialized FLASH

DRAMCR Initialized — — — — — — Initialized BSC

DRACCR Initialized — — — — — — Initialized

REFCR Initialized — — — — — — Initialized

RTCNT Initialized — — — — — — Initialized

RTCOR Initialized — — — — — — Initialized

MAR_0AH Initialized — — — — — — Initialized

MAR_0AL Initialized — — — — — — Initialized

IOAR_0A Initialized — — — — — — Initialized

ETCR_0A Initialized — — — — — — Initialized

MAR_0BH Initialized — — — — — — Initialized

MAR_0BL Initialized — — — — — — Initialized

IOAR_0B Initialized — — — — — — Initialized

ETCR_0B Initialized — — — — — — Initialized

MAR_1AH Initialized — — — — — — Initialized

MAR_1AL Initialized — — — — — — Initialized

IOAR_1A Initialized — — — — — — Initialized

ETCR_1A Initialized — — — — — — Initialized DMAC

MAR_1BH Initialized — — — — — — Initialized

MAR_1BL Initialized — — — — — — Initialized

IOAR_1B Initialized — — — — — — Initialized

ETCR_1B Initialized — — — — — — Initialized

DMAWER Initialized — — — — — — Initialized

DMATCR Initialized — — — — — — Initialized

DMACR_0A Initialized — — — — — — Initialized

DMACR_0B Initialized — — — — — — Initialized

DMACR_1A Initialized — — — — — — Initialized

DMACR_1B Initialized — — — — — — Initialized

DMABCRH Initialized — — — — — — Initialized

DMABCRL Initialized — — — — — — Initialized

Section 23 Li st of Registers

Rev. 3.00 Mar 17, 2006 page 860 of 926

REJ09B0283-0300

Abbreviation Reset High-

Speed Clock

Division Sleep Module

Stop All Module

Clock Stop Software

Standby Hardware

Standby Module

DTCERA Initialized — — — — — — Initialized DTC

DTCERB Initialized — — — — — — Initialized

DTCERC Initialized — — — — — — Initialized

DTCERD Initialized — — — — — — Initialized

DTCERE Initialized — — — — — — Initialized

DTCERF Initialized — — — — — — Initialized

DTCERG Initialized — — — — — — Initialized

DTVECR Initialized — — — — — — Initialized

INTCR Initialized — — — — — — Initialized INT

IER Initialized — — — — — — Initialized

ISR Initialized — — — — — — Initialized

SBYCR Initialized — — — — — — Initialized SYSTEM

SCKCR Initialized — — — — — — Initialized

SYSCR Initialized — — — — — — Initialized

MDCR Initialized — — — — — — Initialized

MSTPCRH Initialized — — — — — — Initialized

MSTPCRL Initialized — — — — — — Initialized

PLLCR Initialized — — — — — — Initialized

PCR Initialized — — — — — — Initialized PPG

PMR Initialized — — — — — — Initialized

NDERH Initialized — — — — — — Initialized

NDERL Initialized — — — — — — Initialized

PODRH Initialized — — — — — — Initialized

PODRL Initialized — — — — — — Initialized

NDRH Initialized — — — — — — Initialized

NDRL Initialized — — — — — — Initialized

NDRH Initialized — — — — — — Initialized

NDRL Initialized — — — — — — Initialized

PORT1 — — — — — — — — PORT

PORT2 — — — — — — — —

PORT3 — — — — — — — —

PORT4 — — — — — — — —

PORT5 — — — — — — — —

PORT6 — — — — — — — —

Section 23 Li st of Registers

Rev. 3.00 Mar 17, 2006 page 861 of 926

REJ09B0283-0300

Abbreviation Reset High-

Speed Clock

Division Sleep Module

Stop All Module

Clock Stop Software

Standby Hardware

Standby Module

PORT7 — — — — — — — — PORT

PORT8 — — — — — — — —

PORTA — — — — — — — —

PORTB — — — — — — — —

PORTC — — — — — — — —

PORTD — — — — — — — —

PORTE — — — — — — — —

PORTF — — — — — — — —

PORTG — — — — — — — —

P1DR Initialized — — — — — Initialized —

P2DR Initialized — — — — — Initialized —

P3DR Initialized — — — — — Initialized —

P5DR Initialized — — — — — Initialized —

P6DR Initialized — — — — — Initialized —

P7DR Initialized — — — — — Initialized —

P8DR Initialized — — — — — Initialized —

PADR Initialized — — — — — Initialized —

PBDR Initialized — — — — — Initialized —

PCDR Initialized — — — — — Initialized —

PDDR Initialized — — — — — Initialized —

PEDR Initialized — — — — — Initialized —

PFDR Initialized — — — — — Initialized —

PGDR Initialized — — — — — Initialized —

PORTH Initialized — — — — — — —

PHDR Initialized — — — — — Initialized —

PHDDR Initialized — — — — — Initialized —

SMR_0 Initialized — — — Initialized Initialized Initialized Initialized SCI_0

BRR_0 Initialized — — — Initialized Initialized Initialized Initialized

SCR_0 Initialized — — — Initialized Initialized Initialized Initialized

TDR_0 Initialized — — — Initialized Initialized Initialized Initialized

SSR_0 Initialized — — — Initialized Initialized Initialized Initialized

RDR_0 Initialized — — — Initialized Initialized Initialized Initialized

SCMR_0 Initialized — — — Initialized Initialized Initialized Initialized

Section 23 Li st of Registers

Rev. 3.00 Mar 17, 2006 page 862 of 926

REJ09B0283-0300

Abbreviation Reset High-

Speed Clock

Division Sleep Module

Stop All Module

Clock Stop Software

Standby Hardware

Standby Module

SMR_1 Initialized — — — Initialized Initialized Initialized Initialized SCI_1

BRR_1 Initialized — — — Initialized Initialized Initialized Initialized

SCR_1 Initialized — — — Initialized Initialized Initialized Initialized

TDR_1 Initialized — — — Initialized Initialized Initialized Initialized

SSR_1 Initialized — — — Initialized Initialized Initialized Initialized

RDR_1 Initialized — — — Initialized Initialized Initialized Initialized

SCMR_1 Initialized — — — Initialized Initialized Initialized Initialized

SMR_2 Initialized — — — Initialized Initialized Initialized Initialized SCI_2

BRR_2 Initialized — — — Initialized Initialized Initialized Initialized

SCR_2 Initialized — — — Initialized Initialized Initialized Initialized

TDR_2 Initialized — — — Initialized Initialized Initialized Initialized

SSR_2 Initialized — — — Initialized Initialized Initialized Initialized

RDR_2 Initialized — — — Initialized Initialized Initialized Initialized

SCMR_2 Initialized — — — Initialized Initialized Initialized Initialized

ADDRA Initialized — — — Initialized Initialized Initialized Initialized A/D

ADDRB Initialized — — — Initialized Initialized Initialized Initialized

ADDRC Initialized — — — Initialized Initialized Initialized Initialized

ADDRD Initialized — — — Initialized Initialized Initialized Initialized

ADDRE*1Initialized — — — Initialized Initialized Initialized Initialized

ADDRF*1Initialized — — — Initialized Initialized Initialized Initialized

ADDRG*1Initialized — — — Initialized Initialized Initialized Initialized

ADDRH*1Initialized — — — Initialized Initialized Initialized Initialized

ADCSR Initialized — — — Initialized Initialized Initialized Initialized

ADCR Initialized — — — Initialized Initialized Initialized Initialized

DADR0 Initialized — — — — — — Initialized D/A

DADR1 Initialized — — — — — — Initialized

DACR01 Initialized — — — — — — Initialized

DADR2 Initialized — — — — — — Initialized

DADR3 Initialized — — — — — — Initialized

DACR23 Initialized — — — — — — Initialized

TCR_0 Initialized — — — — — — Initialized

TCR_1 Initialized — — — — — — Initialized

TMR_0

TMR_1

TCSR_0 Initialized — — — — — — Initialized

TCSR_1 Initialized — — — — — — Initialized

Section 23 Li st of Registers

Rev. 3.00 Mar 17, 2006 page 863 of 926

REJ09B0283-0300

Abbreviation Reset High-

Speed Clock

Division Sleep Module

Stop All Module

Clock Stop Software

Standby Hardware

Standby Module

TCORA_0 Initialized — — — — — — Initialized

TCORA_1 Initialized — — — — — — Initialized

TMR_0

TMR_1

TCORB_0 Initialized — — — — — — Initialized

TCORB_1 Initialized — — — — — — Initialized

TCNT_0 Initialized — — — — — — Initialized

TCNT_1 Initialized — — — — — — Initialized

TCSR Initialized — — — — — — Initialized

TCNT Initialized — — — — — — Initialized

RSTCSR Initialized — — — — — — —

WDT

TSTR Initialized — — — — — — Initialized

TSYR Initialized — — — — — — Initialized

TPU

FLMCR1*2Initialized — — — — — — Initialized

FLMCR2*2Initialized — — — — — — Initialized

EBR1*2Initialized — — — — — — Initialized

EBR2*2Initialized — — — — — — Initialized

FLASH

TCR_0 Initialized — — — — — — Initialized

TMDR_0 Initialized — — — — — — Initialized

TIORH_0 Initialized — — — — — — Initialized

TIORL_0 Initialized — — — — — — Initialized

TIER_0 Initialized — — — — — — Initialized

TSR_0 Initialized — — — — — — Initialized

TCNT_0 Initialized — — — — — — Initialized

TGRA_0 Initialized — — — — — — Initialized

TGRB_0 Initialized — — — — — — Initialized

TGRC_0 Initialized — — — — — — Initialized

TGRD_0 Initialized — — — — — — Initialized

TPU_0

TCR_1 Initialized — — — — — — Initialized TPU_1

TMDR_1 Initialized — — — — — — Initialized

TIOR_1 Initialized — — — — — — Initialized

TIER_1 Initialized — — — — — — Initialized

TSR_1 Initialized — — — — — — Initialized

TCNT_1 Initialized — — — — — — Initialized

TGRA_1 Initialized — — — — — — Initialized

TGRB_1 Initialized — — — — — — Initialized

Section 23 Li st of Registers

Rev. 3.00 Mar 17, 2006 page 864 of 926

REJ09B0283-0300

Abbreviation Reset High-

Speed Clock

Division Sleep Module

Stop All Module

Clock Stop Software

Standby Hardware

Standby Module

TCR_2 Initialized — — — — — — Initialized TPU_2

TMDR_2 Initialized — — — — — — Initialized

TIOR_2 Initialized — — — — — — Initialized

TIER_2 Initialized — — — — — — Initialized

TSR_2 Initialized — — — — — — Initialized

TCNT_2 Initialized — — — — — — Initialized

TGRA_2 Initialized — — — — — — Initialized

TGRB_2 Initialized — — — — — — Initialized

Notes: 1. Not available in the H8S/2678 Group.

2. Register of the flash memory version. Not available in the masked ROM version and

ROM-less version.

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 865 of 926

REJ09B0283-0300

Section 24 Electrical Characteristics

24.1 Absolute Maximum Ratings

Table 24.1 lists the ab solute maximum ratings.

Table 24.1 Absolute Maximum Ratings

Item Symbol Value Unit

Power supply voltage VCC

PLLVCC

–0.3 to + 4.6*V

Input voltage (except port 4, P54 to P57) Vin –0.3 to VCC + 0.3 V

Input voltage (port 4, P54 to P57) Vin –0.3 to AVCC + 0.3 V

Reference power supp ly vo ltag e Vref –0.3 to AVCC + 0.3 V

Analog power supply voltage AVCC –0.3 to + 4.6*V

Analog input voltage VAN –0.3 to AVCC + 0.3 V

Operating temperature Topr Regular specifications:

–20 to + 75*°C

Wide-range specifications:

–40 to + 85 °C

Storage temperature Tstg –55 to + 125*°C

Caution: Permanent damage to the LSI may result if absolute maximum ratings are exceeded.

Note: *F-ZTAT version:

Ranges of power supply voltage and analog power supply voltage:

–0.3 to 4.0 V

Ranges of operating temperature when flash memory is programmed/erased:

Regular specifications: 0 to +75°C

Wide-range specifications: 0 to +85°C

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 866 of 926

REJ09B0283-0300

24.2 DC Characteristics

Table 24.2 DC Characteristics

Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC,

VSS = AVSS = 0 V*1, Ta = –20°C to +75°C (regular specifications),

Ta = –40°C to +85°C (wide-range specifications)

Item Symbol Min Typ Max Unit Test

Conditions

Schmitt

trigger input

voltage

VT–VCC × 0.2 — — VPorts 1, 2,

P50 to P53*2,

ports 6*2, 8*2,

PF1*2, PF2*2,

PH2*2, PH3*2VT+——V

CC × 0.7 V

VT+ – VT–VCC × 0.07 — — V

P54 to P57*2VT–AVCC × 0.2 — — V

VT+——AV

CC × 0.7 V

VT+ – VT–AVCC × 0.07 — — V

Input high

voltage STBY,

MD2 to MD0,

DCTL*4

VIH VCC × 0.9 — VCC + 0.3 V

RES, NMI VCC × 0.9 — VCC + 0.3 V

EXTAL VCC × 0.7 — VCC + 0.3 V

Port 3,

P50 to P53*3,

ports 6 to 8*3,

ports A to H*3

VCC × 0.7 — VCC + 0.3 V

Port 4,

P54 to P57*3AVCC × 0.7 — AVCC + 0.3 V

Input low

voltage RES, STBY,

MD2 to MD0,

DCTL*4

VIL –0.3 — VCC × 0.1 V

NMI, EXTAL –0.3 — VCC × 0.2 V

Ports 3 to 8,

ports A to H*3–0.3 — VCC × 0.2 V

All output pins VOH VCC – 0.5 — — V IOH = –200 µAOutput high

voltage VCC – 1.0 — — V IOH = –1 mA

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 867 of 926

REJ09B0283-0300

Item Symbol Min Typ Max Unit Test

Conditions

Output low

voltage All output pins VOL ——0.4VI

OL = 1.6 mA

RES |Iin| — — 10.0 µAInput

leakage

current STBY, NMI,

MD2 to MD0,

DCTL*4

——1.0 µA

Vin = 0.5 to

VCC – 0.5 V

Port 4,

P54 to P57 ——1.0 µAV

in = 0.5 to

AVCC – 0.5 V

Notes: 1. If the A/D and D/A converters are not used , do not leave the AVCC, Vref, and AVSS pins

open. Connect the AVCC and Vref pins to VCC, and the AVSS pin to VSS.

2. When used as IRQ0 to IRQ15.

3. When used as other than IRQ0 to IRQ15.

4. Not supported in the H8S/2678 Group.

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 868 of 926

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Table 24.3 DC Characteristics

Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC,

VSS = AVSS = 0 V*1, Ta = –20°C to +75°C (regular specifications),

Ta = –40°C to +85°C (wide-range specifications)

Item Symbol Min Typ Max Unit Test

Conditions

Three-state

leakage

current

(off state)

Ports 1 to 3,

P50 to P53,

ports 6 to 8,

ports A to H

| ITSI | — — 1.0 µAV

in = 0.5 to

VCC – 0.5 V

Input pull-up

MOS current Ports A to E –Ip10 — 300 µAV

CC = 2.7 to

3.6 V

Vin = 0 V

RES Cin — — 30 pF Vin = 0 VInput

capacitance NMI — — 30 pF f = 1 MHz

All input pins

except RES

and NMI

— — 15 pF Ta = 25°C

Current

consamption

Normal operation ICC*4—80

(3.3 V) 150 mA f = 33 MHz

Sleep mode — 70

(3.3 V) 125 mA f = 33 MHz

Standby mode*3—0.0110µAT

a ≤ 50°C

——80µA 50°C < Ta

All module clocks

stopped*5—50

(3.3 V) 125 µA

During A/D and

D/A conversion AICC —0.2

(3.0 V) 2.0 mAAnalog

power

supply

current Idle — 0.01 5.0 µA

During A/D and

D/A conversion AICC —1.4

(3.0 V) 4.0 mAReference

power

supply

current Idle — 0.01 5.0 µA

RAM standby voltage VRAM 2.0 — — V

Notes: 1. If the A/D and D/A converters are not used , do not leave the AVCC, Vref, and AVSS pins

open. Connect the AVCC and Vref pins to VCC, and the AVSS pin to VSS.

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 869 of 926

REJ09B0283-0300

2. Current dissipation values are for VIHmin = VCC – 0.5 V and VILmax = 0.5 V with all output

pins unloaded and all input pull-up MOSs in the off state.

3. The values are for VRAM ≤ VCC < 3.0 V, VIHmin = VCC × 0.9, and VILmax = 0.3 V.

4. ICC depends on VCC and f as follows:

ICCmax = 1.0 (mA) + 1.2 (mA/(MHz × V)) × VCC × f (normal operation)

ICCmax = 1.0 (mA) + 1.0 (mA/(MHz × V)) × VCC × f (sleep mode)

5. The values are for reference.

Table 24.4 Permissible Output C urrents

Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC,

VSS = AVSS = 0 V*, Ta = –20°C to +75°C (regular specifications),

Ta = –40°C to +85°C (wide-range specifications)

Item Symbol Min Typ Max Unit

Permissible output low

current (per pin) All output pins IOL ——2.0mA

Permissible output low

current (total) Total of all output

pins ΣIOL ——80mA

Permissible output high

current (per pin) All output pins –IOH ——2.0mA

Permissible output high

current (total) Total of all output

pins Σ–IOH ——40mA

Caution: To protect the LSI’s reliability, do not exceed the output cu rrent values in table 24.3.

Note: *If the A/D and D/A converters are not used, do not leave the AVCC, Vref, and AVSS pi ns

open. Connect the AVCC and Vref pins to VCC, and the AVSS pin to VSS.

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 870 of 926

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24.3 AC Characteristics

LSI output pin

CRH

3 V

C = 50 pF: ports A to H

C = 30 pF: ports 1 to 3,

P50 to P53,

ports 6 to 8

RL = 2.4 kΩ

RH = 12 kΩ

Input/output timing

measurement level:

1.5 V (VCC = 2.7 V to 3.6 V)

Figure 24.1 Output Load Circuit

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 871 of 926

REJ09B0283-0300

Clock Timing

Table 24.5 Clock Timing

Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V,

φ = 8 MHz to 33 MHz, Ta = –20°C to +75°C (regular specifications),

Ta = –40°C to +85°C (wide-range specifications)

Item Symbol Min Max Unit Test Conditions

Clock cycle time tcyc 30.3 500 ns Figure 24.2

Clock pulse high width tCH 10 —ns Figure 24.2

Clock pulse low width tCL 10 —ns

Clock rise time tCr —5ns

Clock fall time tCf —5ns

Reset oscil lati on stab ili zation time

(crystal) tOSC1 10 —ms Figure 24.4 (1)

Software standb y osci llat ion

stabilization time (crystal) tOSC2 10 —ms Figure 24.4 (2)

External clo ck outp ut delay

stabilization time tDEXT 500 —µs Figure 24.4 (1)

Clock phase difference*tcdif 1/4 × tcyc – 31/4 × tcyc + 3 n s Figure 24.3

Clock pulse high width (SDRAMφ)*tSDCH 10 —ns Figure 24.3

Clock p ulse low width (SDRAMφ)*tSDCL 10 —ns Figure 24.3

Clock rise time (SDRAMφ)*tsdcr —5 ns Figure 24.3

Clock fall time (SDRAMφ)*tsdcf —5 ns Figure 24.3

Note: *Not supported in the H8S/2678 Group.

tcyc

tCH tCf

tCL tCr

Figure 24.2 System Clock Timing

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 872 of 926

REJ09B0283-0300

cyc

SDRAMφ

cdif

sdcf

sdcr

SDCH

SDCL

Figure 24.3 SDRAMφ

φφ

φ Timing*

Note: Not supported in the H8S/2678 Group.

EXTAL

STBY

RES

DEXT

OSC1

DEXT

OSC1

Figure 24.4 (1) Oscillation Stabilizatio n Timing

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 873 of 926

REJ09B0283-0300

Oscillator

Software standby mode

(power-down mode) Oscillation

stabilization time

OSC2

NMI

NMI exception

handling

NMIEG = 1

SSBY = 1

NMI exception handling

SLEEP

instruction

NMIEG

SSBY

Figure 24.4 (2) Oscillation Stabilizatio n Timing

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 874 of 926

REJ09B0283-0300

Control Signal Timing

Table 24.6 Control Signal Timing

Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V,

φ = 8 MHz to 33 MHz, Ta = –20°C to +75°C (regular specifications),

Ta = –40°C to +85°C (wide-range specifications)

Item Symbol Min Max Unit Test Conditions

RES setup time tRESS 200 —ns Figure 24.5

RES pulse width tRESW 20 — tcyc

NMI setup time tNMIS 150 —ns Figure 24.6

NMI hold time tNMIH 10 —

NMI pulse width (in recovery from

software standby mode) tNMIW 200 —

IRQ setup time tIRQS 150 —ns

IRQ hold time tIRQH 10 —

IRQ pulse width (in recovery from

software standby mode) tIRQW 200 —

RES

tRESS tRESS

tRESW

Figure 24.5 Reset Input Timing

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 875 of 926

REJ09B0283-0300

NMI

IRQi

(i = 0 to 15)*

IRQ

(edge input)

IRQ

(level input)

Note: * Necessary for SSIER setting to clear software standby mode.

NMIS

NMIH

IRQS

IRQH

NMIW

IRQW

Figure 24. 6 Interrupt Input Timi ng

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 876 of 926

REJ09B0283-0300

Bus Timing

Table 24.7 Bus Timing

Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V,

φ = 8 MHz to 33 MHz, Ta = –20°C to +75°C (regular specifications),

Ta = –40°C to +85°C (wide-range specifications)

Item Symbol Min M ax Unit Test Conditions

Address delay tim e tAD —20 ns

Address setup time 1 tAS1 0.5 × tcyc – 13 —ns Figures 24.7 to

24.21

Address setup time 2 tAS2 1.0 × tcyc – 13 —ns

Address setup time 3 tAS3 1.5 × tcyc – 13 —ns

Address setup time 4 tAS4 2.0 × tcyc – 13 —ns

Address hold time 1 t AH1 0.5 × tcyc – 8 —ns

Address hold time 2 t AH2 1.0 × tcyc – 8 —ns

Address hold time 3 t AH3 1.5 × tcyc – 8 —ns

CS delay time 1 tCSD1 —15 ns

CS delay time 2 tCSD2 —15 ns

CS delay time 3 tCSD3 —20 ns

AS delay time tASD —15 ns

RD delay time 1 tRSD1 —15 ns

RD delay time 2 tRSD2 —15 ns

Read data setup time 1 tRDS1 15 —ns

Read data setup time 2 tRDS2 15 —ns

Read data hold time 1 tRDH1 0 — ns

Read data hold time 2 tRDH2 0 — ns

Read data access time 1 tAC1 —1.0 × tcyc – 20 ns

Read data access time 2 tAC2 —1.5 × tcyc – 20 ns

Read data access time 3 tAC3 —2.0 × tcyc – 20 ns

Read data access time 4 tAC4 —2.5 × tcyc – 20 ns

Read data access time 5 tAC5 —1.0 × tcyc – 20 ns

Read data access time 6 tAC6 —2.0 × tcyc – 20 ns

Read data access time 7 tAC7 —4.0 × tcyc – 20 ns

Read data access time 8 tAC8 —3.0 × tcyc – 20 ns

Address read dat a access time 1 tAA1 —1.0 × tcyc – 20 ns

Address read dat a access time 2 tAA2 —1.5 × tcyc – 20 ns

Address read dat a access time 3 tAA3 —2.0 × tcyc – 20 ns

Address read dat a access time 4 tAA4 —2.5 × tcyc – 20 ns

Address read dat a access time 5 tAA5 —3.0 × tcyc – 20 ns

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 877 of 926

REJ09B0283-0300

Table 24.8 Bus Timing

Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V,

φ = 8 MHz to 33 MHz, Ta = –20°C to +75°C (regular specifications),

Ta = –40°C to +85°C (wide-range specifications)

Item Symbol Min M ax Unit Test Conditions

WR delay time 1 tWRD1 —15 ns

WR delay time 2 tWRD2 —15 ns Figures 24.7 to

24.21

WR pulse width 1 tWSW1 1.0 × tcyc – 13 —ns

WR pulse width 2 tWSW2 1.5 × tcyc – 13 —ns

Write data delay time tWDD —20 ns

Write data setup time 1 tWDS1 0.5 × tcyc – 13 —ns

Write data setup time 2 tWDS2 1.0 × tcyc – 13 —ns

Write data setup time 3 tWDS3 1.5 × tcyc – 13 —ns

Write data hold time 1 t WDH1 0.5 × tcyc – 8 —ns

Write data hold time 2 t WDH2 1.0 × tcyc – 8 —ns

Write data hold time 3 t WDH3 1.5 × tcyc – 8 —ns

Write command setup time 1 tWCS1 0.5 × tcyc – 10 —ns

Write command setup time 2 tWCS2 1.0 × tcyc – 10 —ns

Write command hold time 1 tWCH1 0.5 × tcyc – 10 —ns

Write command hold time 2 tWCH2 1.0 × tcyc – 10 —ns

Read command setup time 1 tRCS1 1.5 × tcyc – 10 —ns

Read command setup time 2 tRCS2 2.0 × tcyc – 10 —ns

Read command hold time tRCH 0.5 × tcyc – 10 —ns

CAS delay time 1 tCASD1 —15 ns

CAS delay time 2 tCASD2 —15 ns

CAS setup time 1 tCSR1 0.5 × tcyc – 10 —ns

CAS setup time 2 tCSR2 1.5 × tcyc – 10 —ns

CAS pulse width 1 tCASW1 1.0 × tcyc – 20 —ns

CAS pulse width 2 tCASW2 1.5 × tcyc – 20 —ns

CAS precharge time 1 tCPW1 1.0 × tcyc – 20 —ns

CAS precharge time 2 tCPW2 1.5 × tcyc – 20 —ns

OE delay time 1 tOED1 —15 ns

OE delay time 2 tOED2 —15 ns

Precharge time 1 t PCH1 1.0 × tcyc – 20 —ns

Precharge time 2 t PCH2 1.5 × tcyc – 20 —ns

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 878 of 926

REJ09B0283-0300

Item Symbol Min M ax Unit Test Conditions

Self-ref resh prec harge time 1 tRPS1 2.5 × tcyc – 20 —ns

Self-ref resh prec harge time 2 tRPS2 3.0 × tcyc – 20 —ns Figures 24.22,

24.23

WAIT setup time tWTS 25 —ns Figure 24. 15

WAIT hold time t WTH 5 — ns

BREQ setup time tBREQS 30 —ns Fi gure 24. 24

BACK delay time tBACD —15 ns

Bus floating time tBZD —40 ns

BREQO delay time tBRQOD —25 ns Figure 24.25

Address delay tim e 2*tAD2 —16.5 ns F i gure 24. 26

CS delay time 4*tCSD4 —16.5 ns Figure 24. 26

DQM delay time*tDQMD —16.5 ns Figure 24.26

CKE delay time*tCKED —16.5 ns Fi gure 24.27

Read data setup time 3*tRDS3 15 —ns Fi gure 24.26

Read data hold time 3*tRDH3 0 — ns Figure 24.26

Write data delay time 2*tWDD2 —31.5 ns Figure 24. 26

Write data hold time 4*tWDH3 2 — ns Figure 24.26

Note: *Not supported in the H8S/2678 Group.

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 879 of 926

REJ09B0283-0300

T1 T2

A23 to A0

CS7 to CS0

D15 to D0

HWR, LWR

D15 to D0

Read

(RDNn = 1)

Read

(RDNn = 0)

Write

CSD1

AS1

RSD1

AC5

AA2

RSD1

WRD2

WSW1

WDH1

WDD

WRD2

AH1

AC2

RDS2

AA3

RSD2

RDS1

RDH1

AH1

ASD

DACK0, DACK1

EDACK0 to EDACK3

DACD1

DACD2

EDACD1

EDACD2

RDH2

Figure 24.7 Basic Bus Timing: Two-State Access

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 880 of 926

REJ09B0283-0300

A23 to A0

CS7 to CS0

D15 to D0

HWR, LWR

D15 to D0

T2 T3

Read

(RDNn = 1)

Read

(RDNn = 0)

Write

AS1

AH1

RSD1

RDS1

RDH1

RSD2

RDS2

RDH2

ASD

RSD1

AC6

AC4

AA5

AS2

WSW2

WDS1

WRD1

WRD2

AH1

AA4

AS1

CSD1

DACK0, DACK1

EDACK0 to EDACK3

DACD1

DACD2

EDACD1

EDACD2

WDH1

WDD

Figure 24.8 Basic Bus Timing: Three-State Access

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 881 of 926

REJ09B0283-0300

A23 to A0

CS7 to CS0

D15 to D0

HWR, LWR

D15 to D0

WAIT

WTS

WTH

WTS

WTH

T2 Tw T3

Read

(RDNn = 1)

Read

(RDNn = 0)

Write

Figure 24.9 Basic Bus Timing: Three-State Access, One Wait

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 882 of 926

REJ09B0283-0300

CSD1

AS1

ASD

AS3

RSD1

AC5

RDS1

RDH1

AH2

AH3

WDH3

WSW1

WDS2

WDD

AS3

WRD2

RSD2

RSD1

AC2

RDS2

RDH2

AS3

RSD1

AH3

AH1

ASD

A23 to A0

CS7 to CS0

D15 to D0

HWR, LWR

D15 to D0

T1 T2 Tt

Read

(RDNn = 1)

Read

(RDNn = 0)

Write

DACK0, DACK1

EDACK0 to EDACK3

DACD1

DACD2

EDACD1

EDACD2

Figure 24.10 Basic Bus Timing: Two-State Access

(CS

CSCS

CS Assertion Period Extended)

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 883 of 926

REJ09B0283-0300

CSD1

AS1

ASD

AS3

RSD1

ASD

AH1

AH3

AH2

AH3

WDH3

WSW2

WDS3

AS4

AS3

RSD1

WRD2

WRD1

AC4

RDH2

RSD2

AC6

RDH1

T1 T2 T3 Tt

A23 to A0

CS7 to CS0

D15 to D0

HWR, LWR

Read

(RDNn = 1)

Read

(RDNn = 0)

Write

DACK0, DACK1

EDACK0 to EDACK3

DACD1

DACD2

EDACD1

EDACD2

RDS2

WDD

RDS1

Figure 24.11 Basic Bus Timing: Three-State Access

(CS

CSCS

CS Assertion Period Extended)

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 884 of 926

REJ09B0283-0300

A23 to A6,

A5 to A1

CS7 to CS0

D15 to D0

HWR, LWR

T2 T1

RSD2

AA1

RDS2

RDH2

Read

Figure 24.12 Burst ROM Access Timing: One-State Burst Access

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 885 of 926

REJ09B0283-0300

A23 to A6,

A5 to A1

CS7 to CS0

D15 to D0

HWR, LWR

T2 T3 T1

tAD

tAS1

tASD

tAA3

tRSD2

tRDS2 tRDH2

tASD

tAH1

Read

Figure 24.13 Burst ROM Access Timing: Two-State Burst Access

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 886 of 926

REJ09B0283-0300

AS3

AH1

CSD2

PCH2

AS2

AC1

OED1

AA3

AC4

WCS1

WCH1

WRD2

WDD

WDS1

WDH2

RDS2

RDH2

AH2

CSD3

CASD1

CASW1

A23 to A0

RAS5 to RAS2

UCAS

LCAS

OE, RD

HWR

D15 to D0

OE, RD

HWR

D15 to D0

Tr Tc1 Tc2

Read

Write

DACK0, DACK1

EDACK0 to EDACK3

DACD1

DACD2

EDACD1

EDACD2

Notes: DACK and EDACK timing: when DDS = 0 and EDDS = 0

RAS timing: when RAST = 0

WRD2

Figure 24.14 DRAM Access Timing: Two-State Access

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 887 of 926

REJ09B0283-0300

Tp Tr Tc1 Tcw Tcwp Tc2

A23 to A0

RAS5 to RAS2

UCAS, LCAS

OE, RD

HWR

D15 to D0

UCAS, LCAS

OE, RD

HWR

WTS

WTH

WTS

WTH

D15 to D0

WAIT

Read

Write

Tcw : Wait cycle inserted by programmable wait function

Tcwp: Wait cycle inserted by pin wait function

DACK0, DACK1

EDACK0 to EDACK3

DACK and EDACK timing: when DDS = 0 and EDDS = 0

RAS timing: when RAST = 0

Notes:

Figure 24.15 DRAM Access Timing: Two-State Access, One Wait

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 888 of 926

REJ09B0283-0300

A23 to A0

RAS5 to RAS2

UCAS

LCAS

OE, RD

HWR

D15 to D0

OE, RD

HWR

D15 to D0

Tr Tc1

CPW1

AC3

RCH

RCS1

Tc2 Tc1 Tc2

Read

Write

DACK and EDACK timing: when DDS = 1 and EDDS = 1

RAS timing: when RAST = 0

Notes:

DACK0, DACK1

EDACK0 to EDACK3

DACD1

DACD2

EDACD1

EDACD2

Figure 24.16 DRAM Access Timing: Two-State Burst Access

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 889 of 926

REJ09B0283-0300

AS2

AH2

CSD2

PCH1

AS3

CSD3

CASD1

AH3

CASD2

CASW2

AC2

AA5

AC7

WRD2

WDD

WDS2

WDH3

WCS2

WCH2

RDH2

OED2

OED1

A23 to A0

RAS5 to RAS2

UCAS

LCAS

OE, RD

HWR

D15 to D0

OE, RD

HWR

D15 to D0

Tr Tc1 Tc2 Tc3

Write

Read

DACK and EDACK timing: when DDS = 0 and EDDS = 0

RAS timing: when RAST = 1

Notes:

DACK0, DACK1

EDACK0 to EDACK3

DACD1

DACD2

EDACD1

EDACD2

WRD2

RDS2

Figure 24.17 DRAM Access Timing: Three-State Access (RAST = 1)

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 890 of 926

REJ09B0283-0300

Tp Tr Tc1 Tcw Tcwp Tc2 Tc3

A23 to A0

RAS5 to RAS2

UCAS, LCAS

OE, RD

HWR

D15 to D0

UCAS, LCAS

HWR

WTS

WTH

WTS

WTH

D15 to D0

WAIT

Read

Write

Tcw : Wait cycle inserted by programmable wait function

Tcwp: Wait cycle inserted by pin wait function

DACK0, DACK1

EDACK0, EDACK1

DACK and EDACK timing: when DDS = 0 and EDDS = 0

RAS timing: when RAST = 0

Notes:

Figure 24.18 DRAM Access Timing: Three-State Access, One Wait

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 891 of 926

REJ09B0283-0300

Tp Tr Tc1 Tc2 Tc3 Tc1 Tc2 Tc3

A23 to A0

RAS5 to RAS0

UCAS

LCAS

OE, RD

HWR

D15 to D0

OE, RD

HWR

tRCH

tRCS2

tAC8

tCPW2

D15 to D0

Read

Write

DACK and EDACK timing: when DDS = 1 and EDDS = 1

RAS timing: when RAST = 1

Notes:

DACK0, DACK1

EDACK0 to EDACK3

Figure 24.19 DRAM Access Timing: Three-State Burst Access

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 892 of 926

REJ09B0283-0300

TRp

RAS5 to RAS2

UCAS, LCAS

TRr

tCSD2

tCSR1

tCASD1

tCSD1

TRc1 TRc2

Figure 24.20 CAS-Before-RAS Refresh Timing

TRp

RAS5 to RAS2

UCAS, LCAS

TRrw

CSD2

CSR2

CASD1

CSD1

CASD1

TRr TRc1 TRcw TRc2

Figure 24.21 CAS-Before-RAS Refresh Timing (with Wait Cycle Insertion)

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 893 of 926

REJ09B0283-0300

TRp

RAS5 to RAS2

UCAS, LCAS

TRr

tCSD2

tCASD1

tCSD2

tCASD1

tRPS2

TRc TRc Tpsr Tp Tr

DRAM accessSelf-refresh

Figure 24.22 Self-Refresh Timing

(Return fro m Software St andby Mode: RAST = 0 )

TRp

RAS5 to RAS2

UCAS, LCAS

TRr

CSD2

CASD1

CSD2

CASD1

RPS1

TRc TRc Tpsr Tp Tr

DRAM accessSelf-refresh

Figure 24.23 Self-Refresh Timing

(Return fro m Software St andby Mode: RAST = 1 )

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 894 of 926

REJ09B0283-0300

BREQ

BREQS

BACD

BZD

BACD

BZD

BACK

A23 to A0

CS7 to CS0

(RAS5 to RAS2)

D15 to D0

AS, RD

HWR, LWR

UCAS, LCAS, OE

Figure 24.24 External Bus Release Timing

BACK

tBRQOD tBRQOD

BREQO

Figure 24.25 External Bus Request Output Timing

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 895 of 926

REJ09B0283-0300

AD2

SDRAMφ

Address bus

Data bus

RAS

CAS

CKE

Precharge-sel

DQMU,

DQML

Data bus

DQMU,

DQML

Tr Tc1 Tw Tc2

Write

Read

CSD4

DQMD

RDS3

RDH3

CSD4

DQMD

CSD4

DQMD

WDD

WDH4

CSD4

High

Figure 24.26 Synchronous DRAM Basic Access Timing (CAS Latency 2)

Note: Not supported in the H8S/2678 Group.

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 896 of 926

REJ09B0283-0300

SDRAMφ

Address bus

Precharge-sel

RAS

CAS

CKE

Rr2

tCKED

Software standby

Figure 24.27 Synchro no us DRAM Self-Refresh Timing

Note: Not supported in the H8S/2678 Group.

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 897 of 926

REJ09B0283-0300

SDRAMφ

DACK or EDACK

Address bus

Data bus

Precharge-sel

RAS

CAS

CKE

DQMU,

DQML

Ttp

CKED

Figure 24.28 Read Data: Two-State Expansion (CAS Latency 2)

Note: Not supported in the H8S/2678 Group.

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 898 of 926

REJ09B0283-0300

DMAC and EXDMAC Timing

Table 24. 9 DMAC and EXDMAC Timing

Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V,

φ = 8 MHz to 33 MHz, Ta = –20°C to +75°C (regular specifications),

Ta = –40°C to +85°C (wide-range specifications)

Item Symbol Min Max Unit Test Conditions

DREQ setup time tDRQS 25 —ns Figure 24.32

DREQ hold time tDRQH 10 —

TEND delay time tTED —18 ns Figure 24.31

DACK delay time 1 t DACD1 —18

DACK delay time 2 t DACD2 —18

Figures 24.29, 24.30

EDREQ setup time tEDRQS 25 —ns Figure 24.32

EDREQ hold time tEDRQH 10 —

ETEND delay time tETED —18 ns Figure 24.31

EDACK delay time 1 tEDACD1 —18

EDACK delay time 2 tEDACD2 —18

Figures 24.29, 24.30

EDRAK delay time tEDRKD —18 ns Figure 24.33

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 899 of 926

REJ09B0283-0300

A23 to A0

CS7 to CS0

tDACD1 tDACD2

tEDACD1 tEDACD2

(read)

D15 to D0

(read)

HWR, LWR

(write)

D15 to D0

(write)

DACK0, DACK1

EDACK0 to EDACK3

Figure 24. 29 DMAC and EXDMAC Single Address Transfer Timing:

Two-State Access

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 900 of 926

REJ09B0283-0300

tDACD1

tEDACD1

tDACD2

tEDACD2

A23 to A0

CS7 to CS0

(read)

D15 to D0

(read)

HWR, LWR

(write)

D15 to D0

(write)

DACK0, DACK1

EDACK0 to EDACK3

T2 T3

Figure 24. 30 DMAC and EXDMAC Single Address Transfer Timing:

Three-State Access

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 901 of 926

REJ09B0283-0300

TED

ETED

TED

ETED

TEND0, TEND1

ETEND0 to ETEND3

T2 or T3

Figure 24.31 DMAC and EXDMAC TEND

TENDTEND

TEND/ETEND

ETENDETEND

ETEND Output Timing

DREQ0, DREQ1

DRQS

EDRQS

DRQH

DERQH

EDREQ0 to EDREQ3

Figure 24.32 DMAC and EXDMAC DREQ

DREQDREQ

DREQ/EDREQ

EDREQEDREQ

EDREQ Input Timing

EDRAK0 to EDRAK3

tEDRKD tEDRKD

Figure 24.33 EXDMAC EDRAK

EDRAKEDRAK

EDRAK Output Timing

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 902 of 926

REJ09B0283-0300

Timing o f On-Chip Peripheral Modules

Table 24.10 Timing of On- Chip Peripheral Modules

Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V,

φ = 8 MHz to 33 MHz, Ta = –20°C to +75°C (regular specifications),

Ta = –40°C to +85°C (wide-range specifications)

Item Symbol Min Max Unit Test Conditions

I/O ports Output data delay time tPWD —40 ns Figure 24.34

Input data setup time tPRS 25 —ns

Input data hold time tPRH 25 —ns

PPG P ulse output delay time tPOD —40 ns Figure 24. 35

TPU T i m er out put delay time tTOCD —40 ns Figure 24.36

Timer input setup time tTICS 25 —ns

Timer clock input setup time tTCKS 25 —ns Fi gure 24.37

Single-edge

specification tTCKWH 1.5 — tcyc

Timer clock

pulse width Both-edge

specification tTCKWL 2.5 — tcyc

8-bit timer Tim er output delay time tTMOD —40 ns Figure 24.38

Timer reset input setup time tTMRS 25 —ns Figure 24. 40

Timer clock input setup time tTMCS 25 —ns Fi gure 24. 39

Single-edge

specification tTMCWH 1.5 — tcyc

Timer clock

pulse width Both-edge

specification tTMCWL 2.5 — tcyc

WDT Overflow output delay time t WOVD —40 ns Figure 24.41

SCI Asynchronous 4 —Figure 24.42

Input clock

cycle Synchronous tScyc 6 — tcyc

Input clock pulse wi dth tSCKW 0.4 0.6 tScyc

Input clock rise time tSCKr —1.5 tcyc

Input clock fall time tSCKf —1.5

Transmit data delay time tTXD —40 ns Figure 24. 43

Receive data set up time

(synchronous) tRXS 40 —ns

Receive data hold time

(synchronous) tRXH 40 —ns

A/D

converter Trigger input setup time tTRGS 30 —ns Figure 24.44

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 903 of 926

REJ09B0283-0300

tPRS tPRH

tPWD

Ports 1 to 8, A to H

(read)

Ports 1 to 3, 6 to 9,

P53 to P50,

ports A to H

(write)

Figure 24. 34 I/O Port Input/Out put Timing

PO15 to PO0

POD

Figure 24.35 PPG Output Timing

Output compare

output*

Input capture

input*

TOCD

TICS

Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3

Figure 24 . 36 TPU Input/Out put Timing

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 904 of 926

REJ09B0283-0300

TCLKA to TCLKD

TCKWL

TCKWH

TCKS

Figure 24 . 37 TPU Clock Input Timing

TMO0, TMO1

tTMOD

Figure 24.38 8-Bit Timer Output Timing

TMCI0, TMCI1

TMCWL

TMCWH

TMCS

Figure 24 . 39 8-Bit Timer Clock Input Timing

TMRI0, TMRI1

tTMRS

Figure 24 . 40 8-Bit Timer Reset I nput Timing

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 905 of 926

REJ09B0283-0300

WDTOVF

WOVD

Figure 24.41 WDT Output Timing

SCK0 to SCK2

SCKW

SCKr

SCKf

Scyc

Figure 24. 42 SCK Clock Input Timing

SCK0 to SCK2 t

TXD

RXS

RXH

TxD0 to TxD2

(transmit data)

RxD0 to RxD2

(receive data)

Figure 24 .43 SCI Input/Output Timing: Synchronous Mode

ADTRG

TRGS

Figure 24.44 A/D Converter Ext ernal Trigger Input Timing

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 906 of 926

REJ09B0283-0300

24.4 A/D Conversion Characteristics

Table 24.11 A/D Conversion Characteristics

Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V,

φ = 8 MHz to 33 MHz, Ta = –20°C to +75°C (regular specifications),

Ta = –40°C to +85°C (wide-range specifications)

Item Min Typ Max Unit

Resolution 10 10 10 Bit

Conversion time ——8.1 µs

Analog input capacitance ——20 pF

Permissible signal source impedance ——5kΩ

Nonlineari ty error ——±7.5 LSB

Offset error ——±7.5 LSB

Full-sca le error ——±7.5 LSB

Quantization error —±0.5 —LSB

Absolute ac curacy ——±8.0 LSB

24.5 D/A Conversion Characteristics

Table 24.12 D/A Conversion Characteristics

Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V,

φ = 8 MHz to 33 MHz, Ta = –20°C to +75°C (regular specifications),

Ta = –40°C to +85°C (wide-range specifications)

Item Min Typ Max Unit Test Conditions

Resolution 888Bit

Conversion time ——10 µs 20 pF capacitive load

Absolute ac curacy —±2.0 ±3.0 LSB 2 MΩ resistive load

——±2.0 LSB 4 MΩ resistive load

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 907 of 926

REJ09B0283-0300

24.6 Flash Memory Characteristics

Table 24.13 Flash Memory Characteristics

Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC,

VSS = AVSS = 0 V, Ta = 0°C to 75°C (program/erase operating temperature range:

regular specifications), Ta = 0°C to 85°C (program/erase operating temperature

range: wide-range specifications)

Item Symbol Min Typ Max Unit Test

Conditions

Programming time*1 *2 *4tP—10 200 ms/

128 bytes

Erase time*1 *3 *6tE—50 1000 ms/

128 bytes

Reprogramming count NWEC 100*710,000*8—Times

Data retention time*9tDRP 10 ——Years

Programming Wait tim e after SWE bit setting*1x1——µs

Wait time after PSU bit setting*1y50——µs

Wait time after P bit setting*1 *4zz1—— 30 µs1 ≤ n ≤ 6

z2 —— 200 µs7 ≤ n ≤ 1000

z3 —— 10 µs Additional

program-

ming wait

Wait time after P bit clearing*1α5——µs

Wait time after PSU bit clearing*1β5——µs

Wait time after PV bit setting*1γ4——µs

Wait time after H'FF dummy write*1ε2——µs

Wait time after PV bit clearing*1η2——µs

Wait time after SWE bit clearing*1θ100 ——µs

Maximum number of writes*1 *4N—— 1000*5Times

Erasing Wait time after SWE bit setting*1x1——µs

Wait time after ESU bit setting*1y 100 ——µs

Wait time after E bit setting*1 *6z—— 10 µsErase time

wait

Wait time after E bit clearing*1α10 ——µs

Wait time after ESU bit clearing*1β10 ——µs

Wait time after EV bit setting*1γ20 ——µs

Wait time after H'FF dummy write*1ε2——µs

Wait time after EV bit clearing*1η4——µs

Wait time after SWE bit clearing*1θ100 ——µs

Maximum number of erases*1 *6N—— 100 Times

Section 24 Electrical Characteristics

Rev. 3.00 Mar 17, 2006 page 908 of 926

REJ09B0283-0300

Notes: 1. Follow the program/erase algorithms when making the time settings.

2. Programming time per 128 bytes. (Indicates the total time during which the P bit is set

in flash memory control register 1 (FLMCR1). Does not include the program-verify

time.)

3. Time to erase one block. (Indicates the time during which the E bit is set in FLMCR1.

Does not include the erase-verify time.)

4. Maximum programming time

tP (max) = ∑ wait time after P bit setting (z)

i=1

5. The maximum number of writes (N) should be set as shown below according to the

actual set value of (z) so as not to exceed the maximum programming time (tP(max)).

The wait time after P bit setting (z) should be changed as follows accord ing to the

number of writes (n).

Number of writes (n)

1 ≤ n ≤ 6 z = 30 µs

7 ≤ n ≤ 1000 z = 200 µs

(Additional programming)

Number of writes (n)

1 ≤ n ≤ 6 z = 10 µs

6. For the maximum erase time (tE(max)), the following relationshi p applies between the

wait time after E bit setting (z) and the maximum number of erases (N):

tE(max) = Wait time after E bit setting (z) × maximum number of erases (N)

7. Minimum number of times for which all characteristics are guaranteed after rewriting

(Guarantee range is 1 to minimum value).

8. Reference value for 25°C (as a guideline, rewriting should normally function up to this

value).

9. Data retention characteristic when rewriting is performed within the specification range,

including the minimum value.

24.7 Usage Note

The F-ZTAT and masked ROM versions both satisfy the electrical characteristics shown in this

manual, but actual electrical characteristic values, operating margins, noise margins, and other

properties may vary due to differences in manufacturing process, on-chip ROM, layout patterns,

and so on.

When system ev aluation testing is car ried out using the F-ZTAT version, the same evaluation

testing should also be conducted for the masked ROM version when changing over to that version.

Appendix

Rev. 3.00 Mar 17, 2006 page 909 of 926

REJ09B0283-0300

Appendix

A. I/O Port States in Each Pin State

Port Name

MCU

Operating

Mode*1Reset

Hardware

Standby

Mode Software

Standby Mode Bus Rel ease

State

Program

Execution

State Sleep

Mode

Port 1 1 to 7 T T Keep Keep I/O port

Port 2 1 to 7 T T Keep Keep I/O port

P34 to P30 1 t o 7 T T Keep Keep I/O port

P35/OE/

CKE 1 to 7 T T [OPE = 0, OE

(CKE)*2 output]

[OPE = 1,

OE (CKE)*2

output]

[Other than the

above]

Keep

[OE (CKE)*2

output]

[Other than the

above]

Keep

[OE (CKE)*2

output]

OE (CKE)*2

[Other than the

above]

I/O port

P47/DA1 1 to 7 T T [DAOE1 = 1]

Keep

[DAOE1 = 0]

Keep Input port

P46/DA0 1 to 7 T T [DAOE0 = 1]

Keep

[DAOE0 = 0]

Keep Input port

P45 to P40 1 t o 7 T T T T I nput port

P57/DA3 1 to 7 T T [DAOE3 = 1]

Keep

[DAOE3 = 0]

Keep Input port

P56/DA2 1 to 7 T T [DAOE2 = 1]

Keep

[DAOE2 = 0]

Keep Input port

Appendix

Rev. 3.00 Mar 17, 2006 page 910 of 926

REJ09B0283-0300

Port Name

MCU

Operating

Mode*1Reset

Hardware

Standby

Mode Software

Standby Mode Bus Rel ease

State

Program

Execution

State Sleep

Mode

P55, P54 1 t o 7 T T T T Input port

P53 to P50 1 t o 7 T T Keep Keep I/O port

Port 6 1 to 7 T T Keep Keep I/O port

Port 7 1 to 7 T T Keep Keep I/O port

Port 8 1 to 7 T T Keep Keep I/O port

PA7/A23

PA6/A22

PA5/A21

1 to 7 T T [OPE = 0,

address output]

[OPE = 1,

address output]

Keep

[Other than the

above]

Keep

[Address output]

[Other than the

above]

Keep

[Address output]

A23 to A21

[Other than the

above]

I/O port

PA4/A20

PA3/A19

PA2/A18

PA1/A17

PA0/A16

1, 2, 5, 6 L T [OPE = 0]

[OPE = 1]

Keep

T Address output

A20 to A16

3, 4, 7 T T [OPE = 0,

address output]

[OPE = 1,

address output]

Keep

[Other than the

above]

Keep

[Address output]

[Other than the

above]

Keep

[Address output]

A20 to A16

[Other than the

above]

I/O port

Port B 1, 2, 5, 6 L T [OPE = 0]

[OPE = 1]

Keep

T Address output

A15 to A8

Appendix

Rev. 3.00 Mar 17, 2006 page 911 of 926

REJ09B0283-0300

Port Name

MCU

Operating

Mode*1Reset

Hardware

Standby

Mode Software

Standby Mode Bus Rel ease

State

Program

Execution

State Sleep

Mode

Port B 3, 4 T T [OPE = 0,

address output]

[OPE = 1,

address output]

Keep

[Other than the

above]

Keep

[Address output]

[Other than the

above]

Keep

[Address output]

A15 to A8

[Other than the

above]

I/O port

3, 7 T T [OPE = 0,

address output]

[OPE = 1,

address output]

Keep

[Other than the

above]

Keep

[Address output]

[Other than the

above]

Keep

[Address output]

A15 to A8

[Other than the

above]

I/O port

Port C 1, 2, 5, 6 L T [OPE = 0]

[OPE = 1]

Keep

T Address output

A7 to A0

4TT

[OPE = 0,

address output]

[OPE = 1,

address output]

Keep

[Other than the

above]

Keep

[Address output]

[Other than the

above]

Keep

[Address output]

A7 to A0

[Other than the

above]

I/O port

Appendix

Rev. 3.00 Mar 17, 2006 page 912 of 926

REJ09B0283-0300

Port Name

MCU

Operating

Mode*1Reset

Hardware

Standby

Mode Software

Standby Mode Bus Rel ease

State

Program

Execution

State Sleep

Mode

Port C 3, 7 T T [OPE = 0,

address output]

[OPE = 1,

address output]

Keep

[Other than the

above]

Keep

[Address output]

[Other than the

above]

Keep

[Address output]

A7 to A0

[Other than the

above]

I/O port

Port D 1, 2, 4 to 6 T T T T D15 toD8

3, 7 T T [Data bus]

[Other than the

above]

Keep

[Data bus]

[Other than the

above]

Keep

[Data bus]

D15 to D8

[Other than the

above]

I/O port

Port E 1, 2, 4

to 6 8-bit

bus T T Keep Keep I /O port

16-bit

bus TTTTD7 to D0

3, 7 8-bit

bus T T Keep Keep I /O port

16-bit

bus T T [Data bus]

[Other than the

above]

Keep

[Data bus]

[Other than the

above]

Keep

[Data bus]

D7 to D0

[Other than the

above]

I/O port

PF7/φ1, 2, 4 to 6 Clock

output T

3, 7 T

[Clock output]

[Other than the

above]

Keep

[Clock output]

Clock output

[Other than the

above]

Keep

[Clock output]

Clock output

[Other than the

above]

Input port

Appendix

Rev. 3.00 Mar 17, 2006 page 913 of 926

REJ09B0283-0300

Port Name

MCU

Operating

Mode*1Reset

Hardware

Standby

Mode Software

Standby Mode Bus Rel ease

State

Program

Execution

State Sleep

Mode

1, 2, 4 to 6 H

PF6/AS

3, 7 T

T[OPE = 0,

AS output]

[OPE = 1,

AS output]

[Other than the

above]

Keep

[AS output]

[Other than the

above]

Keep

[AS output]

[Other than the

above]

I/O port

1, 2, 4 to 6 H [OPE = 0]

[OPE = 1]

TRD, HWRPF5/RD

PF4/HWR

3, 7 T

[OPE = 0, RD,

HWR output]

[OPE = 1, RD,

HWR output]

[Other than the

above]

Keep

[RD, HWR

output]

[Other than the

above]

Keep

[RD, HWR

output]

RD, HWR

[Other than the

above]

I/O port

1, 2, 4 to 6 HPF3/LWR

3, 7 T

T[OPE = 0,

LWR output]

[OPE = 1,

LWR output]

[Other than the

above]

Keep

[LWR output]

[Other than the

above]

Keep

[LWR output]

LWR

[Other than the

above]

I/O port

Appendix

Rev. 3.00 Mar 17, 2006 page 914 of 926

REJ09B0283-0300

Port Name

MCU

Operating

Mode*1Reset

Hardware

Standby

Mode Software

Standby Mode Bus Rel ease

State

Program

Execution

State Sleep

Mode

PF2/LCAS/

DQML*21 to 7 T T [OPE = 0,

LCAS (DQML)

output]

[OPE = 1,

LCAS (DQML)

output]

[Other than the

above]

Keep

[LCAS (DQML)

output]

[Other than the

above]

Keep

[LCAS (DQML)

output]

LCAS (DQML)

[Other than the

above]

I/O port

PF1/UCAS/

(DQMU)*21 to 7 T T [OPE = 0,

UCAS (DQMU)

output]

[OPE = 1,

UCAS (DQMU)

output]

[Other than the

above]

Keep

[UCAS (DQMU)

output]

[Other than the

above]

Keep

[UCAS (DQMU)

output]

UCAS

[Other than the

above]

I/O port

PF0/WAIT 1 to 7 T T [WAIT i nput]

[Other than the

above]

Keep

[WAIT input]

[Other than the

above]

Keep

[WAIT input]

WAIT

[Other than the

above]

I/O port

PG6/BREQ 1 to 7 T T [BREQ input]

[Other than the

above]

Keep

[BREQ input]

BREQ

[BREQ input]

BREQ

[Other than the

above]

I/O port

Appendix

Rev. 3.00 Mar 17, 2006 page 915 of 926

REJ09B0283-0300

Port Name

MCU

Operating

Mode*1Reset

Hardware

Standby

Mode Software

Standby Mode Bus Rel ease

State

Program

Execution

State Sleep

Mode

PG5/BACK 1 to 7 T T [BACK output]

[Other than the

above]

Keep

BACK [BACK output]

BACK

[Other than the

above]

I/O port

PG4/

BREQO 1 to 7 T T [BREQO output]

[Other than the

above]

Keep

[BREQO output]

BREQO

[Other than the

above]

Keep

[BREQO output]

BREQO

[Other than the

above]

I/O port

PG3/CS3

PG2/CS2

PG1/CS1

1 to 7 T T [OPE = 0,

CS output]

[OPE = 1,

CS output]

[Other than the

above]

Keep

[CS output]

[Other than the

above]

Keep

[CS output]

[Other than the

above]

I/O port

1, 2, 5, 6 H

3, 4, 7 T

PG0/CS0 T[OPE = 0,

CS output]

[OPE = 1,

CS output]

[Other than the

above]

Keep

[CS output]

[Other than the

above]

Keep

[CS output]

[Other than the

above]

I/O port

Appendix

Rev. 3.00 Mar 17, 2006 page 916 of 926

REJ09B0283-0300

Port Name

MCU

Operating

Mode*1Reset

Hardware

Standby

Mode Software

Standby Mode Bus Rel ease

State

Program

Execution

State Sleep

Mode

PH3/OE/

CKE/CS7 1 to 7 T T [OPE = 0,

OE output]

[OPE = 1,

OE output]

[OPE = 0,

CS output]

[OPE = 1,

CS output]

[Other than the

above]

Keep

[OE output]

[CS output]

[Other than the

above]

Keep

[OE output]

[CS output]

[Other than the

above]

I/O port

PH2/CS6 1 to 7 T T [OPE = 0,

CS output]

[OPE = 1,

CS output]

[Other than the

above]

Keep

[CS output]

[Other than the

above]

Keep

[CS output]

[Other than the

above]

I/O port

PH1/CS5/

SDRAMφ*21 to 7 [ DCTL =

Clock

output

[DCTL =

[DCTL = 1]

[DCTL = 0]

[DCTL = 1]

[DCTL = 0,

OPE = 0,

CS output]

[DCTL = 0,

OPE = 1,

CS output]

[Other than the

above]

Keep

[DCTL = 1]

Clock output

[DCTL = 0,

CS output]

[Other than the

above]

Keep

[DCTL = 1]

Clock output

[DCTL = 0,

CS output]

[Other than the

above]

I/O port

Appendix

Rev. 3.00 Mar 17, 2006 page 917 of 926

REJ09B0283-0300

Port Name

MCU

Operating

Mode*1Reset

Hardware

Standby

Mode Software

Standby Mode Bus Rel ease

State

Program

Execution

State Sleep

Mode

PH0/CS4 1 to 7 T T [OPE = 0,

CS output]

[OPE = 1,

CS output]

[Other than the

above]

Keep

[CS output]

[Other than the

above]

Keep

[CS output]

[Other than the

above]

I/O port

Legend:

L: Low level

H: High level

Keep: Input port becomes high- impedance, output port retains state

T: High impedance

DDR: Data direction register

OPE: Output port enable

Notes: 1. Mode 3 is not supported in the H8S/2678 Group.

2. Not available in the H8S/2678 Group.

Appendix

Rev. 3.00 Mar 17, 2006 page 918 of 926

REJ09B0283-0300

B. Product Lineup

Product Type Name Model Marking Package (Code)

H8S/2676 Flash memory

version HD64F2676 HD64F2676 144-pin QFP (FP-144G)

Masked ROM

version HD6432676 HD64F2676(***) 144-pi n QFP (FP-144G)

H8S/2675 Masked ROM

version HD6432675 HD6432675(***) 144-pin QFP (FP-144G)

H8S/2674R ROM-less

version HD6412674R HD6412674 144-pin LQFP (FP-144H)

H8S/2673 Masked ROM

version HD6432673 HD6432673(***) 144-pin QFP (FP-144G)

H8S/2670 ROM-less

version HD6412670 HD6412670 144-pin QFP (FP-144G)

Legend:

(***): ROM code

Appendix

Rev. 3.00 Mar 17, 2006 page 919 of 926

REJ09B0283-0300

C. Package Dimensions

For package dimensions, dimensions described in Renesas Semiconductor Packages have priority.

NOTE)

1. DIMENSIONS"*1"AND"*2"

DO NOT INCLUDE MOLD FLASH

2. DIMENSION"*3"DOES NOT

INCLUDE TRIM OFFSET.

MaxNomMin

Dimension in Millimeters

Symbol

Reference

1.25

21.7 22.0 22.3

0.08

0.60.50.4

0.15

0.20

1.45

22.322.021.7

1.70

0.200.120.04

0.270.220.17

0.220.170.12

0.5

8°0°

0.10

1.0

1.25

Index mark

*3p

108

109

144

136

xMy

Detail F

Terminal cross section

P-LQFP144-20x20-0.50 1.4g

MASS[Typ.]

FP-144H/FP-144HVPLQP0144KC-A

RENESAS CodeJEITA Package Code Previous Code

Figure C.1 Package Dimensions (FP-144H)

Appendix

Rev. 3.00 Mar 17, 2006 page 920 of 926

REJ09B0283-0300

NOTE)

1. DIMENSIONS"*1"AND"*2"

DO NOT INCLUDE MOLD FLASH

2. DIMENSION"*3"DOES NOT

INCLUDE TRIM OFFSET.

MaxNomMin

Dimension in Millimeters

Symbol

Reference

1.25

21.8 22.0 22.2

0.10

0.60.50.4

0.15

0.20

2.70

22.222.021.8

3.05

0.250.100.00

0.270.220.17

0.220.170.12

0.5

8°0°

0.10

1.0

1.25

*3p

144

109

108 73

xMy

Detail F

Terminal cross section

P-QFP144-20x20-0.50 2.4g

MASS[Typ.]

FP-144G/FP-144GVPRQP0144KA-A

RENESAS CodeJEITA Package Code Previous Code

Figure C.2 Package Dimensions (FP-144G)

Index

Rev. 3.00 Mar 17, 2006 page 921 of 926

REJ09B0283-0300

Index

16-Bit Timer Pulse Unit.......................... 521

Buffer Operation................................. 566

Cascaded Operation ............................ 570

Free-running count operation.............. 560

Input Capture Function ....................... 563

periodic count operation ..................... 560

Phase Counting Mode......................... 577

PWM Modes....................................... 572

Synchronous Operation....................... 564

toggle output ....................................... 562

Waveform Output by Compare Match 561

8-Bit Timers............................................ 627

16-Bit Counter Mode .......................... 641

Compare Match Count Mode.............. 641

Operation with Cascaded Connection. 641

Pulse Output........................................ 636

TCNT Incrementation Timing ............ 637

Toggle output...................................... 646

A/D Converter ........................................ 741

Conversion Time................................. 753

DTC Activation................................... 585

External Trigger.................................. 756

Scan Mode .......................................... 752

Single Mode........................................ 752

Address Space........................................... 28

Addressing Modes .................................... 48

Absolute Address.................................. 50

Immediate ............................................. 51

Memory Indirect ................................... 51

Program-Counter Relative .................... 51

Bcc ......................................................37, 45

Bus Controller.........................................121

Auto Refreshing ..................................218

Basic Bus Interface .............................158

Basic Operation Timing ..............160, 202

Basic Timing .......................................229

Burst ROM Interface...........................229

Bus Arbitration....................................255

Bus Release .........................................250

Chip Select (CS) Assertion Period

Extension States ..............................155

Data Size and Data Alignment ............158

DRAM Interface..................................173

Idle Cycle ............................................232

Read Strobe (RD) Timing ...................170

Self-Refreshing ...................................220

Synchronous DRAM Interface............198

Valid Strobes.......................................160

Wait Control........................................169

Write Data Buffer Function.................249

Clock Pulse Generator.............................811

PLL Circuit .........................................816

Condition Field .........................................47

Condition-Code Register (CCR) ...............32

CPU Operating Modes ..............................24

Advanced Mode ....................................26

Normal Mode .................................. 24, 25

D/A Converter.........................................763

data direction register..............................427

data register.............................................427

Data Transfer Controller .........................401

Activation by Software ...............416, 420

Block Transfer Mode ..........................414

Chain Transfer............................. 415, 422

Chain Transfer when Counter = 0.......423

DTC Vector Table...............................408

Index

Rev. 3.00 Mar 17, 2006 page 922 of 926

REJ09B0283-0300

Normal Mode.............................. 412, 421

Repeat Mode....................................... 413

Software Activation ............................ 425

vector number for the software activation

........................................................ 406

DMA Controller...................................... 259

Activation by Auto-Request ............... 288

Activation by External Request .......... 287

Block Transfer Mode.................. 304, 313

Burst Mode ......................................... 312

Idle Mode............................................ 292

Interrupt Sources................................. 329

Multi-Channel Operation.................... 325

Normal Mode...................................... 301

Repeat Mode....................................... 295

Sequential Mode ................................. 290

Single Address Mode.................. 298, 318

Transfer Modes................................... 288

Write Data Buffer Function ........ 324, 331

Effective Address Extension..................... 47

Exception Handling ............................ 75, 76

Interrupts............................................... 80

Reset exception handling ...................... 77

Stack Status after Exception Handling.. 82

Traces ................................................... 80

Trap Instruction .................................... 81

Exception Vector Table ............................ 75

EXDMA Controller ................................ 335

Auto Request Mode ............................ 355

Block Transfer Mode.......................... 358

Burst Mode ......................................... 356

Cycle Steal Mode................................ 355

Dual Address Mode ............................ 351

External Request Mode....................... 355

Normal Transfer Mode ....................... 357

Single Address Mode.......................... 352

Extended Register (EXR) ......................... 31

Flash Memory .........................................773

Boot Mode ..........................................789

Erase Block ......................................... 784

Erase/Erase-Verify.............................. 798

Error Protection................................... 800

Hardware Protection ........................... 800

Program/Program-Verify ....................796

Programmer Mode ..............................801

Programming is performed in 128-byte

units.................................................778

Software Protection............................. 800

General Registers......................................30

input pull-up MOS ..................................427

Instruction Set ........................................... 37

Arithmetic operations...................... 37, 40

Bit Manipulation Instructions ...............43

Block Data Transfer Instructions .......... 47

Branch Instructions ...............................45

Data Transfer Instructions..................... 39

Logic Operations Instructions............... 42

Shift Instructions...................................42

System Control Instructions.................. 46

Interrupt Control Modes..........................107

Interrupt Controller ...................................85

Interrupt Exception Handling Vector Table

............................................................102

Interrupt Mask Bit..................................... 32

interrupt mask level................................... 31

interrupt priority register (IPR) ................. 85

Interrupts

ADI .....................................................756

CMIA .................................................. 642

CMIB ..................................................642

EXDMTEND ...................................... 395

NMI..................................................... 118

NMI Interrupt...................................... 101

OVI .....................................................642

SWDTEND ......................................... 416

Index

Rev. 3.00 Mar 17, 2006 page 923 of 926

REJ09B0283-0300

TCI1U................................................. 584

TCI1V................................................. 584

TCI2U................................................. 584

TCI2V................................................. 584

TCI3V................................................. 584

TCI4U................................................. 584

TCI4V................................................. 584

TCI5U................................................. 584

TCI5V................................................. 584

TGI0A................................................. 584

TGI0B................................................. 584

TGI0C................................................. 584

TGI0D................................................. 584

TGI0V................................................. 584

TGI1A................................................. 584

TGI1B................................................. 584

TGI2A................................................. 584

TGI2B................................................. 584

TGI3A................................................. 584

TGI3B................................................. 584

TGI3C................................................. 584

TGI3D................................................. 584

TGI4A................................................. 584

TGI4B................................................. 584

TGI5A................................................. 584

TGI5B................................................. 584

WOVI ................................................. 656

List of Registers...................................... 833

........................................................ 856

MCU Operating Modes ............................ 57

Multiply-Accumulate Register (MAC)..... 33

On-Board Programming.......................... 788

open-drain control register...................... 427

Operation Field ......................................... 47

port register .............................................427

Program Counter (PC) ..............................31

Programmable Pulse Generator...............605

Non-Overlapping Pulse Output...........619

output trigger.......................................612

RAM .......................................................771

Registers

ABWCR...................... 126, 836, 848, 858

ADCR ......................... 750, 841, 852, 862

ADCSR ....................... 746, 841, 852, 862

ADDR ................. 744, 840, 841, 852, 862

ASTCR........................ 126, 836, 848, 858

BCR............................. 136, 837, 848, 859

BROMCR.................... 135, 837, 848, 859

BRR............. 679, 840, 851, 852, 861, 862

CRA ............................ 405, 834, 844, 856

CRB............................. 405, 834, 844, 856

CSACR................ 133, 837, 848, 858, 859

DACR .........................766, 841, 853, 862

DADR ......................... 765, 841, 853, 862

DAR ............................ 405, 834, 844, 856

DMABCR ................... 272, 838, 849, 859

DMACR...................... 265, 838, 849, 859

DMATCR.................... 285, 838, 849, 859

DMAWER .................. 283, 837, 849, 859

DRACCR .................... 144, 837, 848, 859

DRAMCR ................... 138, 837, 848, 859

DTCER ....................... 405, 838, 850, 860

DTVECR..................... 406, 838, 850, 860

EBR1........................... 784, 842, 853, 863

EBR2........................... 785, 842, 853, 863

EDACR ............... 346, 834, 844, 845, 856

EDDAR............... 339, 834, 844, 845, 856

EDMDR ...................... 834, 844, 845, 856

EDSAR................ 338, 834, 844, 845, 856

EDTCR ............... 339, 834, 844, 845, 856

ETCR .......................... 264, 837, 849, 859

FLMCR1 ..................... 781, 842, 853, 863

Index

Rev. 3.00 Mar 17, 2006 page 924 of 926

REJ09B0283-0300

FLMCR2..................... 783, 842, 853, 863

IER................................ 91, 838, 850, 860

INTCR .......................... 88, 838, 850, 860

IOAR .......................... 263, 837, 849, 859

IPR.................88, 834, 835, 845, 856, 857

IrCR ............................ 688, 835, 846, 857

ISCR ............................. 92, 835, 846, 857

ISR................................ 98, 838, 850, 860

ITSR ............................. 98, 835, 846, 857

MAR ................... 263, 837, 848, 849, 859

MDCR .......................... 59, 838, 850, 860

MRA ........................... 403, 834, 844, 856

MRB ........................... 404, 834, 844, 856

MSTPCR .................... 824, 838, 850, 860

NDER ......................... 608, 838, 850, 860

NDR.................... 610, 838, 839, 850, 860

P1DDR........................ 432, 835, 846, 857

P1DR .......................... 433, 839, 851, 861

P2DDR........................ 443, 835, 846, 857

P2DR .......................... 444, 839, 851, 861

P3DDR........................ 454, 835, 846, 857

P3DR .......................... 455, 839, 851, 861

P3ODR........................ 456, 836, 846, 857

P5DDR........................ 463, 835, 846, 857

P5DR .......................... 463, 839, 851, 861

P6DDR........................ 467, 835, 846, 857

P6DR .......................... 468, 839, 851, 861

P7DDR........................ 472, 835, 846, 857

P7DR .......................... 473, 839, 851, 861

P8DDR........................ 478, 835, 846, 857

P8DR .......................... 479, 839, 851, 861

PADDR....................... 484, 835, 846, 857

PADR.......................... 485, 839, 851, 861

PAODR....................... 486, 836, 846, 857

PAPCR........................ 486, 835, 846, 857

PBDDR....................... 490, 835, 846, 857

PBDR.......................... 490, 839, 851, 861

PBPCR........................ 491, 835, 846, 857

PCDDR....................... 493, 835, 846, 857

PCDR.......................... 494, 839, 851, 861

PCPCR ........................ 495, 835, 846, 857

PCR............................. 612, 838, 850, 860

PDDDR....................... 497, 835, 846, 857

PDDR.......................... 497, 839, 851, 861

PDPCR........................ 498, 835, 846, 857

PEDDR ....................... 500, 835, 846, 857

PEDR .......................... 501, 839, 851, 861

PEPCR ........................ 502, 835, 846, 857

PFCR0......................... 513, 835, 846, 857

PFCR1......................... 486, 835, 846, 857

PFCR2......................... 457, 835, 846, 857

PFDDR........................ 504, 835, 846, 857

PFDR .......................... 505, 839, 851, 861

PGDDR....................... 510, 835, 846, 857

PGDR.......................... 512, 839, 851, 861

PHDDR....................... 517, 840, 851, 861

PHDR.......................... 518, 839, 851, 861

PLLCR ........................ 813, 838, 850, 860

PMR ............................ 613, 838, 850, 860

PODR.......................... 609, 838, 850, 860

PORT1 ........................ 433, 839, 850, 860

PORT2 ........................ 444, 839, 850, 860

PORT3 ........................ 455, 839, 850, 860

PORT4 ........................ 461, 839, 850, 860

PORT5 ........................ 464, 839, 850, 860

PORT6 ........................ 468, 839, 851, 860

PORT7 ........................ 473, 839, 851, 861

PORT8 ........................ 479, 839, 851, 861

PORTA ....................... 485, 839, 851, 861

PORTB........................ 491, 839, 851, 861

PORTC........................ 494, 839, 851, 861

PORTD ....................... 498, 839, 851, 861

PORTE........................ 501, 839, 851, 861

PORTF ........................ 506, 839, 851, 861

PORTG ....................... 512, 839, 851, 861

PORTH ....................... 518, 839, 851, 861

RAMER ...................... 786, 837, 848, 859

RDNCR....................... 132, 837, 848, 858

RDR ............ 665, 840, 851, 852, 861, 862

REFCR........................ 149, 837, 848, 859

Index

Rev. 3.00 Mar 17, 2006 page 925 of 926

REJ09B0283-0300

RSTCSR ..................... 653, 842, 853, 863

RTCNT ....................... 152, 837, 848, 859

RTCOR....................... 152, 837, 848, 859

SAR............................. 405, 834, 844, 856

SBYCR ....................... 822, 838, 850, 860

SCKCR ....................... 812, 838, 850, 860

SCMR ......... 678, 840, 851, 852, 861, 862

SCR............. 670, 840, 851, 852, 861, 862

SEMR ......................... 689, 834, 844, 856

SMR............ 666, 840, 851, 852, 861, 862

SSIER ......................... 100, 835, 846, 857

SSR ............. 673, 840, 851, 852, 861, 862

SYSCR.......................... 59, 838, 850, 860

TCNT......... 557, 630, 651, 836, 843, 847,

853, 854, 858, 863

TCORA....................... 630, 842, 853, 863

TCORB....................... 630, 842, 853, 863

TCR ........... 528, 631, 836, 842, 843, 847,

853, 854, 858, 862, 863

TCSR .......... 633, 651, 842, 853, 862, 863

TDR ............ 666, 840, 851, 852, 861, 862

TGR ........... 557, 836, 843, 847, 853, 854,

858, 863

TIER .......... 552, 836, 842, 843, 847, 853,

854, 858, 863

TIOR.......... 534, 836, 842, 843, 847, 853,

854, 858, 863

TMDR........ 533, 836, 842, 843, 847, 853,

854, 858, 863

TSR ............ 554, 666, 836, 842, 843, 847,

853, 854, 858, 863

TSTR........................... 557, 842, 853, 863

TSYR .......................... 558, 842, 853, 863

WTCR ................. 127, 836, 837, 848, 858

Reset..........................................................77

RRRDACR..............................................766

RRRDADR .............................................765

RRRMDCR...............................................59

RRRSYSCR..............................................59

Serial Communication Interface..............661

Asynchronous Mode ...........................691

Bit Rate ...............................................679

Break...................................................735

framing error .......................................698

Mark State...........................................736

Operation in Clocked Synchronous Mode

........................................................709

overrun error .......................................698

parity error...........................................698

stack pointer (SP) ......................................30

Trace Bit....................................................31

TRAPA instruction ...................................51

Watchdog Timer .....................................649

Interval Timer Mode ...........................655

Watchdog Timer Mode .......................654

Index

Rev. 3.00 Mar 17, 2006 page 926 of 926

REJ09B0283-0300

Renesas 16-Bit Single-Chip Microcomputer

Hardware Manual

H8S/2678 Group, H8S/2678R Group, H8S/2676 F-ZTAT™

Publication Date: 1st Edition, September 2001

Rev.3.00, March 17, 2006

Published by: Sales Strategic Planning Div.

Renesas Technology Corp.

Edited by: Customer Su ppor t Dep ar tme nt

Global Strategic Communication Div.

Renesas Soluti ons Corp.

Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan

http://www.renesas.com

Refer to "http://www.renesas.com/en/network" for the latest and detailed information.

Renesas Technology America, Inc.

450 Holger Way, San Jose, CA 95134-1368, U.S.A

Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501

Renesas Technology Europe Limited

Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.

Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900

Renesas Technology (Shanghai) Co., Ltd.

Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120

Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898

Renesas Technology Hong Kong Ltd.

7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong

Tel: <852> 2265-6688, Fax: <852> 2730-6071

Renesas Technology Taiwan Co., Ltd.

10th Floor, No.99, Fushing North Road, Taipei, Taiwan

Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999

Renesas Technology Singapore Pte. Ltd.

1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632

Tel: <65> 6213-0200, Fax: <65> 6278-8001

Renesas Technology Korea Co., Ltd.

Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea

Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145

Renesas Technology Malaysia Sdn. Bhd

Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia

Tel: <603> 7955-9390, Fax: <603> 7955-9510

RENESAS SALES OFFICES

Colophon 6.0

1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan

H8S/2678 Group, H8S/2678R Group,

H8S/2676 F-ZTATTM

REJ09B0283-0300

Hardware Manual