1
FN6287.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2006. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc.
All other trademarks mentioned are the property of their respective owners.
ISL55020
Wideband, Low Distortion, Differential
Amplifier
The ISL55020 is fully differential wideband amplifier
designed to drive differential ADCs. This device features a
high drive capability of 100mA, low operating quiescent
current of 21mA and operates with both single and dual
supplies over a range of 4.5V (±2.25V) to +12V (±6V). Key
features include high impedance, full differential inputs and
full differential or DC referenced complementary single-
ended outputs A wide bandwidth unity gain common mode
(VCM) amplifier input is included to provide DC offset
correction or common mode signal injection to the
differential output.
The ISL55020 is available in the thermally-enhanced 16 Ld
QFN package and is specified for operation over the full
-40°C to +85°C temperature range. The ISL55020 has an
EN pin to disable the outputs.
Features
• Fully differential current feedback amplifier
• High impedance differential inputs
• Differential output drives up to 100mA from a +12V supply
• Separate unity-gain common mode input (VCM)
• 300MHz bandwidth
• 1200V/µs Slewrate
• -73.3dBc typical driver output distortion at 10VPP; 1MHz
• -64.6dBc typical driver output distortion at 10VPP; 4MHz
• Low quiescent supply current of 21mA
• Pb-free plus anneal available (RoHS compliant)
Applications
• High Linearity ADC preamplifier
• Differential driver
• Wireless communication receiver
• Differential active filter
Pinout
ISL55020
(16 LD QFN)
TOP VIEW
Ordering Information
PART NUMBER
(Note)
PART
MARKING
TAPE &
REEL
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL55020IRZ 55020IRZ - 16 Ld QFN MDP0046
ISL55020IRZ-T13 55020IRZ 13” 16 Ld QFN MDP0046
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1
2
3
4
12
11
10
9
5678
16 15 14 13
NC
FB+
IN+
GND
VCM
NC
V-
EN
OUT+
NC
V+
OUT-
NC
FB-
IN-
NC
+1
+
-
+
-
Data Sheet December 18, 2006
NOT RECOMMENDED FOR NEW DESIGNS
NO RECOMMENDED REPLACEMENT
contact our Technical Support Center at
1-888-INTERSIL or www.intersil.com/tsc
2FN6287.0
December 18, 2006
Absolute Maximum Ratings (TA = +25°C) Thermal Information
V+ Voltage to Ground or V- . . . . . . . . . . . . . . . . . . . -0.3V to +13.2V
V- Voltage to Ground or V+ . . . . . . . . . . . . . . . . . . . +0.3V to -13.2V
IN+, IN-, FB+, FB-, VCM, EN Voltage . . . . . . . V- -0.3V to V+ +0.3V
Current into any Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8mA
Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
ESD Tolerance
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200V
Thermal Resistance JA (°C/W)
16 Ld QFN Package . . . . . . . . . . . . . . . . . . . . . . . . 40
Ambient Operating Temperature Range . . . . . . . . . . -40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . . . . . . -60°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operationa l sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications VS = 12V, RF = 750, RG = 1.5k, RL = 1k connected to mid supply, TA = +25°C, unless otherwise specified.
PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT
DC PERFORMANCE
VOS Common Mode Offset Voltage -38 15 38 mV
VOS VOS Mismatch -7 0.7 7 mV
INPUT CHARACTERISTICS
IB+, IB- Non-Inverting Input Bias Current -7 7 µA
FB+, FB- Inverting Input Bias Current -125 25 125 µA
IB-I
B- Mismatch -75 0 75 µA
eNInput Noise Voltage fo = 1kHz 9.8 nV
Hz
fo = 10kHz 6.9 nVHz
iNInput Noise Current fo = 1kHz 6.6 pA/
Hz
fo = 10kHz 2.7 pA/
Hz
CMIR Common Mode Input Range IN+, IN- 2 10 V
VCM
IB VCM VCM Input Bias Current VCM = 5V to 6V -7 7 µA
VOS VCM ((VOUT+) + (VOUT -))/2 VCM, IN +, IN- = 0V, RL = 1k -150 150 mV
VCM Av Close Loop Gain VCM = 1V, VCM = 5V to 6V 0.87 0.95 1.03 V/V
CMIR Common Mode Input Range VCM 2.3 9.7 V
OUTPUT CHARACTERISTICS
VOUT Loaded Output Swing (differential) VS = ±6V, RL = 1kdifferential load ±4.8 ±5.0 V
VS = 4.5V, RL = 1kdifferential load ±1.05 V
IOUT Output Current RL = 0differential load ±150 mA
RL = 50differential load ±1.45 mA
SUPPLY
VSSupply Voltage Single supply 4.5 12 V
IS+ ENABLE Positive Supply Current All outputs at 0V, EN = 0V 14 21 28 mA
IS- ENABLE Negative Supply All outputs at 0V, EN = 0V -28 -21 -14 mA
IS+ DISABLE Positive Supply Current All outputs at 0V, EN = 5V 0.5 1.4 2.5 mA
IS- DISABLE Negative Supply All outputs at 0V, EN = 5V -2.5 -1.6 0.5 mA
Ts Thermal Shutdown Temperature IC Junction Temperature 185 °C
Ts-hys Thermal Shutdown Hysteresis IC Junction Shutdown Hysteresis 15 °C
ISL55020
3FN6287.0
December 18, 2006
LOGIC
VINH, EN ENABLE High Level 2 V
VINL, EN ENABLE Low Level 0.8 V
IINH, EN Input Current, High ENABLE = 5V 180 250 320 µA
IINL, EN Input Current, Low ENABLE = 0V -5 +5 µA
tEN ON Enable time, off to on ENABLE = 5V to 0V 12 nS
tEN OFF Disable time, on to off ENABLE = 0V to 5V 250 nS
RIN IN+, IN- Input resistance disables state V+ = 12V, Vin = 2V to 10V, ENABLE = 5V 1 M
V+ = 4.5V,Vin = 2V to 4V, ENABLE = 5V 1 M
AC PERFORMANCE
BW -3dB Bandwidth, single-ended output to
GND (Figure 3)
AVS = +2.5, RF = 750, RG = 374,
RL=100
300 MHz
AVS = 5, RF = 750, RG = 169
RL=100
200 MHz
THD, HD2, HD3 THD, A = 2; Differential f = 1MHz, VO = 1VP-P
, RL = 1k -63.8 dBc
f = 1MHz, VO = 10VP-P
, RL = 1k-73.3 dBc
f = 4MHz, VO = 1VP-P
, RL = 1k -57.4 dBc
f = 4MHz, VO = 10VP-P
, RL = 1k-62.4 dBc
HD2, AV = 2; Differential f = 1MHz, VO = 1VP-P
, RL = 1k -82.3 dBc
f = 1MHz, VO = 10VP-P
, RL = 1k77.6 dBc
f = 4MHz, VO = 1VP-P
, RL = 1k -62.3 dBc
f = 4MHz, VO = 10VP-P
, RL = 1k-64.6 dBc
HD3, AV = 2; Differential f = 1MHz, VO = 1VP-P
, RL = 1k -68.5 dBc
f = 1MHz, VO = 10VP-P
, RL = 1k-83.5 dBc
f = 4MHz, VO = 1VP-P
, RL = 1k -60.3 dBc
f = 4MHz, VO = 10VP-P
, RL = 1k-67.7 dBc
SR Slew Rate, Single-ended VOUT from -3V to +3V, RL = 1k600 1200 V/µs
Electrical Specifications VS = 12V, RF = 750, RG = 1.5k, RL = 1k connected to mid supply, TA = +25°C, unless otherwise specified.
(Continued)
PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT
ISL55020
4FN6287.0
December 18, 2006
Typical Performance Curves
FIGURE 1. SINGLE-ENDED GAIN vs FREQUENCY vs RLFIGURE 2. SINGLE-ENDED GAIN vs FREQUENCY vs CL
FIGURE 3. CLOSED LOOP GAIN vs FREQUENCY FIGURE 4. SINGLE-ENDED GAIN vs FREQUENCY vs VS
FIGURE 5. SINGLE-ENDED GAIN vs FREQUENCY vs RF/RG FIGURE 6. VCM GAIN vs FREQUENCY vs RL
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
100k 1M 10M 100M 1G
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
RIN = 200
RF = 750
RG = 374
VOUT = 100mVP-P
AVS = 2.5
RL = 1000
RL = 500
RL = 250
RL = 50
RL = 100
-16
-14
-12
-10
-8
-6
-4
-2
0
2
4
6
8
10
12
14
16
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
RIN = 200
RF = 750
RG = 374
VOUT = 100mVP-P
AVS = 2.5
RL = 100
CL = 2.3pFCL = 24.3pF
CL = 14.4pF
CL = 9.1pF
CL = 2.3pF
100k 1M 10M 100M 1G
0
5
10
15
20
25
30
35
40
FREQUENCY (Hz)
GAIN (dB)
RIN = 200
VOUT = 100mVP-P
RL = 100
AVS = 50, RF = 750, RG = 15.4
AVS = 5, RF = 750, RG = 169
AVS = 2.5, RF = 750, RG = 374
100k 1M 10M 100M 1G
-5
-4
-3
-2
-1
0
1
2
3
4
5
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
RIN = 200
RF = 750
RG = 374
VOUT = 100mVP-P
AVS = 2.5
RL = 100 to GND
VS = ±2.25
VS = ±3
VS = ±6
100k 1M 10M 100M 1G
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
AVS = 2.5
VOUT = 100mVP-P
RL= 100
-10
-8
-6
-4
-2
0
2
4
6
8
10
12
RF = 187, RG = 93.1
RF = 374, RG = 187
RF = 750, RG = 374
RF = 1500, RG = 750
100k 1M 10M 100M 1G
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
FREQUENCY (Hz)
RL = 100
RL = 250
RL = 500
RL = 1000
NORMALIZED GAIN (dB)
AVS = 2.5
RIN = 200
RF = 750
VOUT = 100mVP-P
AVCM = 1
RG = 374
INPUT = VCM
RL = 50
100k 1M 10M 100M 1G
ISL55020
5FN6287.0
December 18, 2006
FIGURE 7. VCM GAIN vs FREQUENCY vs CL FIGURE 8. PSRR+ vs FREQUENCY vs VS (DUAL SUPPLIES)
FIGURE 9. PSRR- vs FREQUENCY vs VSFIGURE 10. PSRR+ vs FREQUENCY vs VS (SINGLE SUPPLY)
FIGURE 11. INPUT OFF ISOLATION GAIN vs FREQUENCY
SINGLE-ENDED
FIGURE 12. VCM OFF ISOLATION vs FREQUENCY - SINGLE-
ENDED
Typical Performance Curves (Continued)
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
AVS = 2.5
RIN = 200
RF = 750
VOUT = 100mVP-P
AVCM = 1
RG = 374
INPUT = VCM
RL = 100
CL = 24.3pF
CL = 14.4pF
CL = 9.1pF
CL = 2.3pF
100k 1M 10M 100M 1G
-60
-50
-40
-30
-20
-10
0
10
FREQUENCY (Hz)
PSRR+ (dB)
AVS = 2.5
RIN = 200
RF = 750
VPSRR = 1VP-P
RG = 374
RL = 100
VS = ±6V
VS = ±2.25V
VS = ±3V
100k 1M 10M 100M 1G
-70
-60
-50
-40
-30
-20
-10
0
10
PSRR- (dB)
FREQUENCY (Hz)
AVS = 2.5
RIN = 200
RF = 750
VPSRR = 1VP-P
RG = 374
RL = 100
VS = ±6V
VS = ±2.25V
VPSRR = 500mVP-P
V
S
= ±3V
VS = ±2.25V
100k 1M 10M 100M 1G
-50
-40
-30
-20
-10
0
10
20
FREQUENCY (Hz)
PSRR+ (dB)
AVS = 2.5
RIN = 200
RF = 750
VPSRR = 1VP-P
RG = 374
RL = 100
V
S
= +4.5V
100k 1M 10M 100M 1G
VCM = 2.25V
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
FREQUENCY (Hz)
OFF ISOLATION (dB)
AVS = 2.5
RIN = 200
RF = 1500
VIN = 1VP-P
RG = 374
RL = 100
100k 1M 10M 100M 1G
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
FREQUENCY (Hz)
RIN = 200
RF = 1500
VIN = 1VP-P
RG = 374
RL = 100
AVS = 2.5
AVCM = 1
VCM OFF ISOLATION (dB)
100k 1M 10M 100M 1G
ISL55020
6FN6287.0
December 18, 2006
FIGURE 13. SMALL SIGNAL STEP RESPONSE FIGURE 14. LARGE SIGNAL STEP RESPONSE
FIGURE 15. SMALL SIGNAL STEP RESPONSE - VCM TO
VOUT
FIGURE 16. LARGE SIGNAL STEP RESPONSE - VCM TO
VOUT
FIGURE 17. ENABLE TO OUTPUT DELAY
Typical Performance Curves (Continued)
-0.02
0
0.02
0.04
0.06
0.08
0.10
0.12
0 5 10 15 20 25 30 35 40 45 50
TIME (ns)
VOUT (V)
AVS = 2.5
RL = 100 TO GND
VS = ±6V
-6
-4
-2
0
2
4
6
0 50 100 150 200 250 300 350 400
TIME (ns)
VOUT (V)
AVS = 2.5
RL = 100 TO GND
VS = ±6V
-0.02
0
0.02
0.04
0.06
0.08
0.10
0.12
0 5 10 15 20 25 30 35 40 45 50
TIME (ns)
VOUT (V)
AVS = 2.5
RL = 100 TO GND
VS = ±6V
-4
-3
-2
-1
0
1
2
3
0 50 100 150 200 250 300 350 400
TIME (ns)
VOUT (V)
AVS = 2.5
RL = 100 TO GND
VS = ±6V
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
0 100 200 300 400 500 600 700 800
TIME (ns)
VOUT (V)
-1
0
1
2
3
4
5
6
V-ENABLE (V)
AVS = 2.5
RL = 100 TO GND
VS = ±6V
V-ENABLE (V)
VOUT (V)
ISL55020
7FN6287.0
December 18, 2006
Pin Descriptions
PIN NUMBER PIN NAME
EQUIVALENT
CIRCUIT PIN FUNCTION
1, 6, 9, 12, 15 NC No connect; grounded for best AC performance
2 FB+ Circuit1 Feedback from non-inverting output
3 IN+ Circuit 1 Non-inverting input
4 GND Circuit 4 Ground
5 VCM Circuit 1 Reference input, sets common-mode output voltage with AV = 1. Must be st to
V+/2 for single supply applications
7 V- Circuit 4 Negative supply. Must be connected to GND for single supply operation
8EN
Circuit 2 Enable pin with internal pull-down; Logic “1” selects the disabled state; Logic “0”
selects the enabled state
10 IN- Circuit 1 Inverting input
11 FB- Circuit 1 Feedback from inverting output
13 OUT- Circuit 3 Inverting output
14 V+ Circuit 4 Positive supply
16 OUT+ Circuit 3 Non-inverting output
Thermal Pad Circuit 5 Pack thermal pad electrically connected to IC substrate - must be connected to
most negative voltage applied to the IC
IN+, IN-
V+
V-
EN
V+
V-
GND
V+
V-
OUT
CIRCUIT 3
CIRCUIT 1
CIRCUIT 2
FB+,FB-
VCM
V-
V+
CAPACITIVELY
COUPLED
ESD CLAMP
GND
CIRCUIT 4.
V-
THERMAL HEAT SINK PAD
~1M
SUBSTRATE
CIRCUIT 5
ISL55020
8FN6287.0
December 18, 2006
Description of Operation and Application
Information
Product Descr iption
The ISL55020 is a full differential Current Feedback
Amplifier (CFA) featuring wide bandwidth and low power.
The device contains a pair of high impedance differential
inputs and a pair of differential outputs. It can be used in any
combination of single/differential ended input/output
configurations. A wide bandwidth unity gain, common mode
amplifier with a 100MHz -3dB bandwidth (Figure 6) is
included to provide DC offset correction or common mode
signal injection to the differential output. The ISL55020 is
internally compensated for single-ended closed loop gain
(AVS), differential closed gain (AVD) of 2, or greater.
Connected in differential gain of 5 (single ended gain of ±2.5
and driving a 200 differential load, the ISL55020 has a -
3dB bandwidth of 300MHz. Driving a 200 differential load
at gain of 10, the bandwidth is about 200MHz (Figure 3). The
ISL55020 is available with a power down feature (EN) to
reduce the power while the amplifier is disabled.
Input, Output, and Supply Voltage Range
The ISL55020 is designed to operate with dual supplies over
a range of +/-2.25V to +/-6V and can also operate with a
single supply over the range of 4.5V to 12V. For single
supply operation, the V- and GND pins must be connected
together as close to the device as possible. The amplifiers
have an input common mode voltage range from -4.3V to
3.4V when operated from ±5V supplies. The differential
mode input range (DMIR) between the two inputs is from -
2.3V to +2.3V. The input voltage range at the VCM pin is
from -3.3V to 3.7V. If the input common mode or differential
mode signal is outside the above-specified ranges, the
output signal will be distorted.
The output of the ISL55020 can swing from -3.8V to +3.8V at
100 differential load at ±5V supply. As the load resistance
becomes lower, the output swing is reduced.
Single-ended, Differential and Common Mode Gain
Settings
The ISL55020 can be used as a single/differential ended to
differential/single converter. The voltage applied at VCM pin
sets the output common mode voltage and the common
mode gain is fixed at gain is one (AVCM = 1).
The output differential voltage is given by the following:
Where:
RF1 = RF2 = RF
The differential output gain (AVD) is defined by the feedback
resistors according to the following
The single ended output voltage (VOS) contains a common
mode component (VCM) and a differential mode component
equal to one-half the differential output (VOD/2)., and is
given by the following:
and the single-ended gain becomes:
FIGURE 18. BASIC APPLICATION CIRCUIT
VOUT+
FB+
RG
RF2
IN+
IN-
FB-
VIN+
VIN-
RF1
VOUT -
VCM
RIN-
RIN+
RL+
RL-
+1
OUT+
OUT-
RT-
RT-VCM
RT+
V+ V-
VCM
GND-
EN
V+ V-
GND-
EN
RS+
RS+
VOD = (VIN+ - VIN-) x (1 + 2RF/RG)(EQ. 1)
AVD = 1 + 2RF/RG(EQ. 2)
VOS = VOD/2 + VCM = VCM +(VIN+ - VIN-) x (0.5 + RF/RG)(EQ. 3)
AVS = 0.5+ RF/RG(EQ. 4)
ISL55020
9FN6287.0
December 18, 2006
Feedback Resistor, Gain Bandwidth Product and
Stability Considerations (See Figure 18 - Basic
Application Schematic)
For gains greater than 1, the feedback resistor forms a pole
with the parasitic capacitance at the inverting input. As this
pole becomes lower in frequency, the amplifier's phase
margin is reduced. Excessive parasitic capacitance at the
input will cause excessive ringing in the time domain and
peaking in the frequency domain. High feedback resistor
values have the same effect, and therefore should be kept
as low as possible. Figure 5 shows the gain-peaking effect of
using higher feedback resistor values. Feedback resistor RF
has some maximum value that should not be exceeded for
optimum performance.
Unlike voltage feedback (VFA) amplifier topologies that
exhibit constant gain-bandwidth product, CFA amplifiers
maintain high bandwidth at gains high greater than 1.
Figure 3 illustrates the nearly constant bandwidth from a
single-ended gain (AVS) of 2.5 to 5, and only a slight
reduction out to a AVS of 50. For the gains other than 1,
optimum response is obtained with RF between 500 to
1k.
The high impedance inputs IN+ and IN- are sensitive
parasitic capacitance and inductance. To ensure input
stability, a small value resistor (200 recommended) should
be placed as close to the device IN+ and IN- pins as
possible.
Driving Capacitive Loads and Cables
Excessive output capacitance also contributes to gain
peaking (Figure 2) and high overshoot in pulse applications.
For PC board layouts requiring long traces at the output, a
small series resistor (Figure 17 - RS+, RS- usually between
5 to 50should be inserted as close to the device output
pin as possible to each to minimize peaking,. The resultant
gain error should be compensated with an appropriate
adjustment of RG
.
When used as a cable driver, double termination is always
recommended for reflection-free performance. For those
applications, a back-termination series resistor (RS) at the
amplifier's output will isolate the amplifier from the cable and
allow extensive capacitive drive. However, other applications
may have high capacitive loads without a back-termination
resistor. Again, a small series resistor at the output can help
to reduce peaking.
Disable/Power-Down
The ISL55020 can be disabled with it’s outputs in a high
impedance state. The turn off time is about 250nS and the
turn on time is about 12nS (Figure 17). When disabled, the
amplifier's supply current is reduced to 1.4mA for IS+ and -
1.6mA for IS- typically. The amplifier's power down can be
controlled by standard ground-referenced CMOS signal
levels at the EN pin. V.
Output Drive Capability
The ISL55020 has no internal current-limiting circuitry. If the
output is shorted, it is possible to exceed the Absolute
Maximum Rating for output current or power dissipation,
potentially resulting in the destruction of the device.internal
short circuit protection.
Power Dissipation
With the high output drive capability of the ISL55020, It is
possible to exceed the +150°C absolute maximum junction
temperature under certain load current conditions.
Therefore, it is important to calculate the maximum junction
temperature for the application to determine if the load
conditions or package types need to be modified for the
amplifier to remain in the safe operating area.
A thermal shutdown circuit is included that implements a
thermal shutdown if the junction temperature exceeds
~+185°C. The thermal shutdown includes thermal hysteresis
of ~+15°C. The thermal shutdown feature is designed to
protect the device during accidental overload conditions and
continuous operation at junction temperatures greater than
+150°C should never be allowed.
The maximum power dissipation allowed in a package is
determined according to:
Where:
TJMAX = Maximum junction temperature
TAMAX = Maximum ambient temperature
JA = Thermal resistance of the package
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the load, or:
Where:
VS = Total supply voltage
ISMAX = Maximum quiescent supply current per channel
VO = Maximum differential output voltage of the
application
RLD = Differential load resistance
ILOAD = Load current
By setting the two PDMAX equations equal to each other, we
can solve the output current and RLD to avoid the device
overheat.
PDMAX
TJMAX TAMAX
–
JA
---------------------------------------------
=
PD VSISMAX VS
VO
RLD
------------
+=
ISL55020
10 FN6287.0
December 18, 2006
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
For additional products, see www.intersil.com/en/products.html
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, a good printed circuit
board layout is necessary for optimum performance. Lead
lengths should be as sort as possible. The power supply pin
must be well bypassed to reduce the risk of oscillation. For
normal single supply operation, where the V- pin is
connected to the ground plane, a single 4.7µF tantalum
capacitor in parallel with a 0.1µF ceramic capacitor from V+
to GND will suffice. This same capacitor combination should
be placed at each supply pin to ground if split supplies are to
be used. In this case, the V- pin becomes the negative
supply rail.
For good AC performance, parasitic capacitance should be
kept to minimum. Use of wire wound resistors should be
avoided because of their additional series inductance. Use
of sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance that can result in
compromised performance. Minimizing parasitic capacitance
at the amplifier's inverting input pin is very important. The
feedback resistor should be placed very close to the
inverting input pin. Strip line design techniques are
recommended for the signal traces.
ISL55020
11 FN6287.0
December 18, 2006
ISL55020
QFN (Quad Flat No-Lead) Package Family
PIN #1
I.D. MARK
2
1
3
(N-2)
(N-1)
N
(N/2)
2X
0.075
TOP VIEW
(N/2)
NE
2
3
1
PIN #1 I.D.
(N-2)
(N-1)
N
b
L
N LEADS
BOTTOM VIEW
DETAIL X
PLANE
SEATING
N LEADS
C
SEE DETAIL "X"
A1
(L)
N LEADS
& EXPOSED PAD
0.10
SIDE VIEW
0.10 BA
MC
C
B
A
E
2X
0.075 C
D
3
5
7
(E2)
(D2)
e
0.08 C
C
(c)
A
2
C
MDP0046
QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY
(COMPLIANT TO JEDEC MO-220)
SYMBOL QFN44 QFN38 QFN32 TOLERANCE NOTES
A 0.90 0.90 0.90 0.90 ±0.10 -
A1 0.02 0.02 0.02 0.02 +0.03/-0.02 -
b 0.25 0.25 0.23 0.22 ±0.02 -
c 0.20 0.20 0.20 0.20 Reference -
D 7.00 5.00 8.00 5.00 Basic -
D2 5.10 3.80 5.80 3.60/2.48 Reference 8
E 7.00 7.00 8.00 6.00 Basic -
E2 5.10 5.80 5.80 4.60/3.40 Reference 8
e 0.50 0.50 0.80 0.50 Basic -
L 0.55 0.40 0.53 0.50 ±0.05 -
N 44 38 32 32 Reference 4
ND 11 7 8 7 Reference 6
NE 11 12 8 9 Reference 5
SYMBOL QFN28 QFN24 QFN20 QFN16
TOLER-
ANCE NOTES
A 0.90 0.90 0.90 0.90 0.90 ±0.10 -
A1 0.02 0.02 0.02 0.02 0.02 +0.03/
-0.02
-
b 0.25 0.25 0.30 0.25 0.33 ±0.02 -
c 0.20 0.20 0.20 0.20 0.20 Reference -
D 4.00 4.00 5.00 4.00 4.00 Basic -
D2 2.65 2.80 3.70 2.70 2.40 Reference -
E 5.00 5.00 5.00 4.00 4.00 Basic -
E2 3.65 3.80 3.70 2.70 2.40 Reference -
e 0.50 0.50 0.65 0.50 0.65 Basic -
L 0.40 0.40 0.40 0.40 0.60 ±0.05 -
N 28 24 20 20 16 Reference 4
ND 6 5 5 5 4 Reference 6
NE 8 7 5 5 4 Reference 5
Rev 10 12/04
NOTES:
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Tiebar view shown is a non-functional feature.
3. Bottom-side pin #1 I.D. is a diepad chamfer as shown.
4. N is the total number of terminals on the device.
5. NE is the number of terminals on the “E” side of the package
(or Y-direction).
6. ND is the number of terminals on the “D” side of the package
(or X-direction). ND = (N/2)-NE.
7. Inward end of terminal may be square or circular in shape with radius
(b/2) as shown.
8. If two values are listed, multiple exposed pad options are available.
Refer to device-specific datasheet.
1
FN6287.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2006. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc.
All other trademarks mentioned are the property of their respective owners.
ISL55020
Wideband, Low Distortion, Differential
Amplifier
The ISL55020 is fully differential wideband amplifier
designed to drive differential ADCs. This device features a
high drive capability of 100mA, low operating quiescent
current of 21mA and operates with both single and dual
supplies over a range of 4.5V (±2.25V) to +12V (±6V). Key
features include high impedance, full differential inputs and
full differential or DC referenced complementary single-
ended outputs A wide bandwidth unity gain common mode
(VCM) amplifier input is included to provide DC offset
correction or common mode signal injection to the
differential output.
The ISL55020 is available in the thermally-enhanced 16 Ld
QFN package and is specified for operation over the full
-40°C to +85°C temperature range. The ISL55020 has an
EN pin to disable the outputs.
Features
• Fully differential current feedback amplifier
• High impedance differential inputs
• Differential output drives up to 100mA from a +12V supply
• Separate unity-gain common mode input (VCM)
• 300MHz bandwidth
• 1200V/µs Slewrate
• -73.3dBc typical driver output distortion at 10VPP; 1MHz
• -64.6dBc typical driver output distortion at 10VPP; 4MHz
• Low quiescent supply current of 21mA
• Pb-free plus anneal available (RoHS compliant)
Applications
• High Linearity ADC preamplifier
• Differential driver
• Wireless communication receiver
• Differential active filter
Pinout
ISL55020
(16 LD QFN)
TOP VIEW
Ordering Information
PART NUMBER
(Note)
PART
MARKING
TAPE &
REEL
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL55020IRZ 55020IRZ - 16 Ld QFN MDP0046
ISL55020IRZ-T13 55020IRZ 13” 16 Ld QFN MDP0046
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1
2
3
4
12
11
10
9
5678
16 15 14 13
NC
FB+
IN+
GND
VCM
NC
V-
EN
OUT+
NC
V+
OUT-
NC
FB-
IN-
NC
+1
+
-
+
-
Data Sheet December 18, 2006
NOT RECOMMENDED FOR NEW DESIGNS
NO RECOMMENDED REPLACEMENT
contact our Technical Support Center at
1-888-INTERSIL or www.intersil.com/tsc
2FN6287.0
December 18, 2006
Absolute Maximum Ratings (TA = +25°C) Thermal Information
V+ Voltage to Ground or V- . . . . . . . . . . . . . . . . . . . -0.3V to +13.2V
V- Voltage to Ground or V+ . . . . . . . . . . . . . . . . . . . +0.3V to -13.2V
IN+, IN-, FB+, FB-, VCM, EN Voltage . . . . . . . V- -0.3V to V+ +0.3V
Current into any Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8mA
Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
ESD Tolerance
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200V
Thermal Resistance JA (°C/W)
16 Ld QFN Package . . . . . . . . . . . . . . . . . . . . . . . . 40
Ambient Operating Temperature Range . . . . . . . . . . -40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . . . . . . -60°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operationa l sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications VS = 12V, RF = 750, RG = 1.5k, RL = 1k connected to mid supply, TA = +25°C, unless otherwise specified.
PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT
DC PERFORMANCE
VOS Common Mode Offset Voltage -38 15 38 mV
VOS VOS Mismatch -7 0.7 7 mV
INPUT CHARACTERISTICS
IB+, IB- Non-Inverting Input Bias Current -7 7 µA
FB+, FB- Inverting Input Bias Current -125 25 125 µA
IB-I
B- Mismatch -75 0 75 µA
eNInput Noise Voltage fo = 1kHz 9.8 nV
Hz
fo = 10kHz 6.9 nVHz
iNInput Noise Current fo = 1kHz 6.6 pA/
Hz
fo = 10kHz 2.7 pA/
Hz
CMIR Common Mode Input Range IN+, IN- 2 10 V
VCM
IB VCM VCM Input Bias Current VCM = 5V to 6V -7 7 µA
VOS VCM ((VOUT+) + (VOUT -))/2 VCM, IN +, IN- = 0V, RL = 1k -150 150 mV
VCM Av Close Loop Gain VCM = 1V, VCM = 5V to 6V 0.87 0.95 1.03 V/V
CMIR Common Mode Input Range VCM 2.3 9.7 V
OUTPUT CHARACTERISTICS
VOUT Loaded Output Swing (differential) VS = ±6V, RL = 1kdifferential load ±4.8 ±5.0 V
VS = 4.5V, RL = 1kdifferential load ±1.05 V
IOUT Output Current RL = 0differential load ±150 mA
RL = 50differential load ±1.45 mA
SUPPLY
VSSupply Voltage Single supply 4.5 12 V
IS+ ENABLE Positive Supply Current All outputs at 0V, EN = 0V 14 21 28 mA
IS- ENABLE Negative Supply All outputs at 0V, EN = 0V -28 -21 -14 mA
IS+ DISABLE Positive Supply Current All outputs at 0V, EN = 5V 0.5 1.4 2.5 mA
IS- DISABLE Negative Supply All outputs at 0V, EN = 5V -2.5 -1.6 0.5 mA
Ts Thermal Shutdown Temperature IC Junction Temperature 185 °C
Ts-hys Thermal Shutdown Hysteresis IC Junction Shutdown Hysteresis 15 °C
ISL55020
3FN6287.0
December 18, 2006
LOGIC
VINH, EN ENABLE High Level 2 V
VINL, EN ENABLE Low Level 0.8 V
IINH, EN Input Current, High ENABLE = 5V 180 250 320 µA
IINL, EN Input Current, Low ENABLE = 0V -5 +5 µA
tEN ON Enable time, off to on ENABLE = 5V to 0V 12 nS
tEN OFF Disable time, on to off ENABLE = 0V to 5V 250 nS
RIN IN+, IN- Input resistance disables state V+ = 12V, Vin = 2V to 10V, ENABLE = 5V 1 M
V+ = 4.5V,Vin = 2V to 4V, ENABLE = 5V 1 M
AC PERFORMANCE
BW -3dB Bandwidth, single-ended output to
GND (Figure 3)
AVS = +2.5, RF = 750, RG = 374,
RL=100
300 MHz
AVS = 5, RF = 750, RG = 169
RL=100
200 MHz
THD, HD2, HD3 THD, A = 2; Differential f = 1MHz, VO = 1VP-P
, RL = 1k -63.8 dBc
f = 1MHz, VO = 10VP-P
, RL = 1k-73.3 dBc
f = 4MHz, VO = 1VP-P
, RL = 1k -57.4 dBc
f = 4MHz, VO = 10VP-P
, RL = 1k-62.4 dBc
HD2, AV = 2; Differential f = 1MHz, VO = 1VP-P
, RL = 1k -82.3 dBc
f = 1MHz, VO = 10VP-P
, RL = 1k77.6 dBc
f = 4MHz, VO = 1VP-P
, RL = 1k -62.3 dBc
f = 4MHz, VO = 10VP-P
, RL = 1k-64.6 dBc
HD3, AV = 2; Differential f = 1MHz, VO = 1VP-P
, RL = 1k -68.5 dBc
f = 1MHz, VO = 10VP-P
, RL = 1k-83.5 dBc
f = 4MHz, VO = 1VP-P
, RL = 1k -60.3 dBc
f = 4MHz, VO = 10VP-P
, RL = 1k-67.7 dBc
SR Slew Rate, Single-ended VOUT from -3V to +3V, RL = 1k600 1200 V/µs
Electrical Specifications VS = 12V, RF = 750, RG = 1.5k, RL = 1k connected to mid supply, TA = +25°C, unless otherwise specified.
(Continued)
PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT
ISL55020
4FN6287.0
December 18, 2006
Typical Performance Curves
FIGURE 1. SINGLE-ENDED GAIN vs FREQUENCY vs RLFIGURE 2. SINGLE-ENDED GAIN vs FREQUENCY vs CL
FIGURE 3. CLOSED LOOP GAIN vs FREQUENCY FIGURE 4. SINGLE-ENDED GAIN vs FREQUENCY vs VS
FIGURE 5. SINGLE-ENDED GAIN vs FREQUENCY vs RF/RG FIGURE 6. VCM GAIN vs FREQUENCY vs RL
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
100k 1M 10M 100M 1G
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
RIN = 200
RF = 750
RG = 374
VOUT = 100mVP-P
AVS = 2.5
RL = 1000
RL = 500
RL = 250
RL = 50
RL = 100
-16
-14
-12
-10
-8
-6
-4
-2
0
2
4
6
8
10
12
14
16
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
RIN = 200
RF = 750
RG = 374
VOUT = 100mVP-P
AVS = 2.5
RL = 100
CL = 2.3pFCL = 24.3pF
CL = 14.4pF
CL = 9.1pF
CL = 2.3pF
100k 1M 10M 100M 1G
0
5
10
15
20
25
30
35
40
FREQUENCY (Hz)
GAIN (dB)
RIN = 200
VOUT = 100mVP-P
RL = 100
AVS = 50, RF = 750, RG = 15.4
AVS = 5, RF = 750, RG = 169
AVS = 2.5, RF = 750, RG = 374
100k 1M 10M 100M 1G
-5
-4
-3
-2
-1
0
1
2
3
4
5
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
RIN = 200
RF = 750
RG = 374
VOUT = 100mVP-P
AVS = 2.5
RL = 100 to GND
VS = ±2.25
VS = ±3
VS = ±6
100k 1M 10M 100M 1G
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
AVS = 2.5
VOUT = 100mVP-P
RL= 100
-10
-8
-6
-4
-2
0
2
4
6
8
10
12
RF = 187, RG = 93.1
RF = 374, RG = 187
RF = 750, RG = 374
RF = 1500, RG = 750
100k 1M 10M 100M 1G
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
FREQUENCY (Hz)
RL = 100
RL = 250
RL = 500
RL = 1000
NORMALIZED GAIN (dB)
AVS = 2.5
RIN = 200
RF = 750
VOUT = 100mVP-P
AVCM = 1
RG = 374
INPUT = VCM
RL = 50
100k 1M 10M 100M 1G
ISL55020
5FN6287.0
December 18, 2006
FIGURE 7. VCM GAIN vs FREQUENCY vs CL FIGURE 8. PSRR+ vs FREQUENCY vs VS (DUAL SUPPLIES)
FIGURE 9. PSRR- vs FREQUENCY vs VSFIGURE 10. PSRR+ vs FREQUENCY vs VS (SINGLE SUPPLY)
FIGURE 11. INPUT OFF ISOLATION GAIN vs FREQUENCY
SINGLE-ENDED
FIGURE 12. VCM OFF ISOLATION vs FREQUENCY - SINGLE-
ENDED
Typical Performance Curves (Continued)
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
AVS = 2.5
RIN = 200
RF = 750
VOUT = 100mVP-P
AVCM = 1
RG = 374
INPUT = VCM
RL = 100
CL = 24.3pF
CL = 14.4pF
CL = 9.1pF
CL = 2.3pF
100k 1M 10M 100M 1G
-60
-50
-40
-30
-20
-10
0
10
FREQUENCY (Hz)
PSRR+ (dB)
AVS = 2.5
RIN = 200
RF = 750
VPSRR = 1VP-P
RG = 374
RL = 100
VS = ±6V
VS = ±2.25V
VS = ±3V
100k 1M 10M 100M 1G
-70
-60
-50
-40
-30
-20
-10
0
10
PSRR- (dB)
FREQUENCY (Hz)
AVS = 2.5
RIN = 200
RF = 750
VPSRR = 1VP-P
RG = 374
RL = 100
VS = ±6V
VS = ±2.25V
VPSRR = 500mVP-P
V
S
= ±3V
VS = ±2.25V
100k 1M 10M 100M 1G
-50
-40
-30
-20
-10
0
10
20
FREQUENCY (Hz)
PSRR+ (dB)
AVS = 2.5
RIN = 200
RF = 750
VPSRR = 1VP-P
RG = 374
RL = 100
V
S
= +4.5V
100k 1M 10M 100M 1G
VCM = 2.25V
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
FREQUENCY (Hz)
OFF ISOLATION (dB)
AVS = 2.5
RIN = 200
RF = 1500
VIN = 1VP-P
RG = 374
RL = 100
100k 1M 10M 100M 1G
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
FREQUENCY (Hz)
RIN = 200
RF = 1500
VIN = 1VP-P
RG = 374
RL = 100
AVS = 2.5
AVCM = 1
VCM OFF ISOLATION (dB)
100k 1M 10M 100M 1G
ISL55020
6FN6287.0
December 18, 2006
FIGURE 13. SMALL SIGNAL STEP RESPONSE FIGURE 14. LARGE SIGNAL STEP RESPONSE
FIGURE 15. SMALL SIGNAL STEP RESPONSE - VCM TO
VOUT
FIGURE 16. LARGE SIGNAL STEP RESPONSE - VCM TO
VOUT
FIGURE 17. ENABLE TO OUTPUT DELAY
Typical Performance Curves (Continued)
-0.02
0
0.02
0.04
0.06
0.08
0.10
0.12
0 5 10 15 20 25 30 35 40 45 50
TIME (ns)
VOUT (V)
AVS = 2.5
RL = 100 TO GND
VS = ±6V
-6
-4
-2
0
2
4
6
0 50 100 150 200 250 300 350 400
TIME (ns)
VOUT (V)
AVS = 2.5
RL = 100 TO GND
VS = ±6V
-0.02
0
0.02
0.04
0.06
0.08
0.10
0.12
0 5 10 15 20 25 30 35 40 45 50
TIME (ns)
VOUT (V)
AVS = 2.5
RL = 100 TO GND
VS = ±6V
-4
-3
-2
-1
0
1
2
3
0 50 100 150 200 250 300 350 400
TIME (ns)
VOUT (V)
AVS = 2.5
RL = 100 TO GND
VS = ±6V
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
0 100 200 300 400 500 600 700 800
TIME (ns)
VOUT (V)
-1
0
1
2
3
4
5
6
V-ENABLE (V)
AVS = 2.5
RL = 100 TO GND
VS = ±6V
V-ENABLE (V)
VOUT (V)
ISL55020
7FN6287.0
December 18, 2006
Pin Descriptions
PIN NUMBER PIN NAME
EQUIVALENT
CIRCUIT PIN FUNCTION
1, 6, 9, 12, 15 NC No connect; grounded for best AC performance
2 FB+ Circuit1 Feedback from non-inverting output
3 IN+ Circuit 1 Non-inverting input
4 GND Circuit 4 Ground
5 VCM Circuit 1 Reference input, sets common-mode output voltage with AV = 1. Must be st to
V+/2 for single supply applications
7 V- Circuit 4 Negative supply. Must be connected to GND for single supply operation
8EN
Circuit 2 Enable pin with internal pull-down; Logic “1” selects the disabled state; Logic “0”
selects the enabled state
10 IN- Circuit 1 Inverting input
11 FB- Circuit 1 Feedback from inverting output
13 OUT- Circuit 3 Inverting output
14 V+ Circuit 4 Positive supply
16 OUT+ Circuit 3 Non-inverting output
Thermal Pad Circuit 5 Pack thermal pad electrically connected to IC substrate - must be connected to
most negative voltage applied to the IC
IN+, IN-
V+
V-
EN
V+
V-
GND
V+
V-
OUT
CIRCUIT 3
CIRCUIT 1
CIRCUIT 2
FB+,FB-
VCM
V-
V+
CAPACITIVELY
COUPLED
ESD CLAMP
GND
CIRCUIT 4.
V-
THERMAL HEAT SINK PAD
~1M
SUBSTRATE
CIRCUIT 5
ISL55020
8FN6287.0
December 18, 2006
Description of Operation and Application
Information
Product Descr iption
The ISL55020 is a full differential Current Feedback
Amplifier (CFA) featuring wide bandwidth and low power.
The device contains a pair of high impedance differential
inputs and a pair of differential outputs. It can be used in any
combination of single/differential ended input/output
configurations. A wide bandwidth unity gain, common mode
amplifier with a 100MHz -3dB bandwidth (Figure 6) is
included to provide DC offset correction or common mode
signal injection to the differential output. The ISL55020 is
internally compensated for single-ended closed loop gain
(AVS), differential closed gain (AVD) of 2, or greater.
Connected in differential gain of 5 (single ended gain of ±2.5
and driving a 200 differential load, the ISL55020 has a -
3dB bandwidth of 300MHz. Driving a 200 differential load
at gain of 10, the bandwidth is about 200MHz (Figure 3). The
ISL55020 is available with a power down feature (EN) to
reduce the power while the amplifier is disabled.
Input, Output, and Supply Voltage Range
The ISL55020 is designed to operate with dual supplies over
a range of +/-2.25V to +/-6V and can also operate with a
single supply over the range of 4.5V to 12V. For single
supply operation, the V- and GND pins must be connected
together as close to the device as possible. The amplifiers
have an input common mode voltage range from -4.3V to
3.4V when operated from ±5V supplies. The differential
mode input range (DMIR) between the two inputs is from -
2.3V to +2.3V. The input voltage range at the VCM pin is
from -3.3V to 3.7V. If the input common mode or differential
mode signal is outside the above-specified ranges, the
output signal will be distorted.
The output of the ISL55020 can swing from -3.8V to +3.8V at
100 differential load at ±5V supply. As the load resistance
becomes lower, the output swing is reduced.
Single-ended, Differential and Common Mode Gain
Settings
The ISL55020 can be used as a single/differential ended to
differential/single converter. The voltage applied at VCM pin
sets the output common mode voltage and the common
mode gain is fixed at gain is one (AVCM = 1).
The output differential voltage is given by the following:
Where:
RF1 = RF2 = RF
The differential output gain (AVD) is defined by the feedback
resistors according to the following
The single ended output voltage (VOS) contains a common
mode component (VCM) and a differential mode component
equal to one-half the differential output (VOD/2)., and is
given by the following:
and the single-ended gain becomes:
FIGURE 18. BASIC APPLICATION CIRCUIT
VOUT+
FB+
RG
RF2
IN+
IN-
FB-
VIN+
VIN-
RF1
VOUT -
VCM
RIN-
RIN+
RL+
RL-
+1
OUT+
OUT-
RT-
RT-VCM
RT+
V+ V-
VCM
GND-
EN
V+ V-
GND-
EN
RS+
RS+
VOD = (VIN+ - VIN-) x (1 + 2RF/RG)(EQ. 1)
AVD = 1 + 2RF/RG(EQ. 2)
VOS = VOD/2 + VCM = VCM +(VIN+ - VIN-) x (0.5 + RF/RG)(EQ. 3)
AVS = 0.5+ RF/RG(EQ. 4)
ISL55020
9FN6287.0
December 18, 2006
Feedback Resistor, Gain Bandwidth Product and
Stability Considerations (See Figure 18 - Basic
Application Schematic)
For gains greater than 1, the feedback resistor forms a pole
with the parasitic capacitance at the inverting input. As this
pole becomes lower in frequency, the amplifier's phase
margin is reduced. Excessive parasitic capacitance at the
input will cause excessive ringing in the time domain and
peaking in the frequency domain. High feedback resistor
values have the same effect, and therefore should be kept
as low as possible. Figure 5 shows the gain-peaking effect of
using higher feedback resistor values. Feedback resistor RF
has some maximum value that should not be exceeded for
optimum performance.
Unlike voltage feedback (VFA) amplifier topologies that
exhibit constant gain-bandwidth product, CFA amplifiers
maintain high bandwidth at gains high greater than 1.
Figure 3 illustrates the nearly constant bandwidth from a
single-ended gain (AVS) of 2.5 to 5, and only a slight
reduction out to a AVS of 50. For the gains other than 1,
optimum response is obtained with RF between 500 to
1k.
The high impedance inputs IN+ and IN- are sensitive
parasitic capacitance and inductance. To ensure input
stability, a small value resistor (200 recommended) should
be placed as close to the device IN+ and IN- pins as
possible.
Driving Capacitive Loads and Cables
Excessive output capacitance also contributes to gain
peaking (Figure 2) and high overshoot in pulse applications.
For PC board layouts requiring long traces at the output, a
small series resistor (Figure 17 - RS+, RS- usually between
5 to 50should be inserted as close to the device output
pin as possible to each to minimize peaking,. The resultant
gain error should be compensated with an appropriate
adjustment of RG
.
When used as a cable driver, double termination is always
recommended for reflection-free performance. For those
applications, a back-termination series resistor (RS) at the
amplifier's output will isolate the amplifier from the cable and
allow extensive capacitive drive. However, other applications
may have high capacitive loads without a back-termination
resistor. Again, a small series resistor at the output can help
to reduce peaking.
Disable/Power-Down
The ISL55020 can be disabled with it’s outputs in a high
impedance state. The turn off time is about 250nS and the
turn on time is about 12nS (Figure 17). When disabled, the
amplifier's supply current is reduced to 1.4mA for IS+ and -
1.6mA for IS- typically. The amplifier's power down can be
controlled by standard ground-referenced CMOS signal
levels at the EN pin. V.
Output Drive Capability
The ISL55020 has no internal current-limiting circuitry. If the
output is shorted, it is possible to exceed the Absolute
Maximum Rating for output current or power dissipation,
potentially resulting in the destruction of the device.internal
short circuit protection.
Power Dissipation
With the high output drive capability of the ISL55020, It is
possible to exceed the +150°C absolute maximum junction
temperature under certain load current conditions.
Therefore, it is important to calculate the maximum junction
temperature for the application to determine if the load
conditions or package types need to be modified for the
amplifier to remain in the safe operating area.
A thermal shutdown circuit is included that implements a
thermal shutdown if the junction temperature exceeds
~+185°C. The thermal shutdown includes thermal hysteresis
of ~+15°C. The thermal shutdown feature is designed to
protect the device during accidental overload conditions and
continuous operation at junction temperatures greater than
+150°C should never be allowed.
The maximum power dissipation allowed in a package is
determined according to:
Where:
TJMAX = Maximum junction temperature
TAMAX = Maximum ambient temperature
JA = Thermal resistance of the package
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the load, or:
Where:
VS = Total supply voltage
ISMAX = Maximum quiescent supply current per channel
VO = Maximum differential output voltage of the
application
RLD = Differential load resistance
ILOAD = Load current
By setting the two PDMAX equations equal to each other, we
can solve the output current and RLD to avoid the device
overheat.
PDMAX
TJMAX TAMAX
–
JA
---------------------------------------------
=
PD VSISMAX VS
VO
RLD
------------
+=
ISL55020
10 FN6287.0
December 18, 2006
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
For additional products, see www.intersil.com/en/products.html
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, a good printed circuit
board layout is necessary for optimum performance. Lead
lengths should be as sort as possible. The power supply pin
must be well bypassed to reduce the risk of oscillation. For
normal single supply operation, where the V- pin is
connected to the ground plane, a single 4.7µF tantalum
capacitor in parallel with a 0.1µF ceramic capacitor from V+
to GND will suffice. This same capacitor combination should
be placed at each supply pin to ground if split supplies are to
be used. In this case, the V- pin becomes the negative
supply rail.
For good AC performance, parasitic capacitance should be
kept to minimum. Use of wire wound resistors should be
avoided because of their additional series inductance. Use
of sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance that can result in
compromised performance. Minimizing parasitic capacitance
at the amplifier's inverting input pin is very important. The
feedback resistor should be placed very close to the
inverting input pin. Strip line design techniques are
recommended for the signal traces.
ISL55020
11 FN6287.0
December 18, 2006
ISL55020
QFN (Quad Flat No-Lead) Package Family
PIN #1
I.D. MARK
2
1
3
(N-2)
(N-1)
N
(N/2)
2X
0.075
TOP VIEW
(N/2)
NE
2
3
1
PIN #1 I.D.
(N-2)
(N-1)
N
b
L
N LEADS
BOTTOM VIEW
DETAIL X
PLANE
SEATING
N LEADS
C
SEE DETAIL "X"
A1
(L)
N LEADS
& EXPOSED PAD
0.10
SIDE VIEW
0.10 BA
MC
C
B
A
E
2X
0.075 C
D
3
5
7
(E2)
(D2)
e
0.08 C
C
(c)
A
2
C
MDP0046
QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY
(COMPLIANT TO JEDEC MO-220)
SYMBOL QFN44 QFN38 QFN32 TOLERANCE NOTES
A 0.90 0.90 0.90 0.90 ±0.10 -
A1 0.02 0.02 0.02 0.02 +0.03/-0.02 -
b 0.25 0.25 0.23 0.22 ±0.02 -
c 0.20 0.20 0.20 0.20 Reference -
D 7.00 5.00 8.00 5.00 Basic -
D2 5.10 3.80 5.80 3.60/2.48 Reference 8
E 7.00 7.00 8.00 6.00 Basic -
E2 5.10 5.80 5.80 4.60/3.40 Reference 8
e 0.50 0.50 0.80 0.50 Basic -
L 0.55 0.40 0.53 0.50 ±0.05 -
N 44 38 32 32 Reference 4
ND 11 7 8 7 Reference 6
NE 11 12 8 9 Reference 5
SYMBOL QFN28 QFN24 QFN20 QFN16
TOLER-
ANCE NOTES
A 0.90 0.90 0.90 0.90 0.90 ±0.10 -
A1 0.02 0.02 0.02 0.02 0.02 +0.03/
-0.02
-
b 0.25 0.25 0.30 0.25 0.33 ±0.02 -
c 0.20 0.20 0.20 0.20 0.20 Reference -
D 4.00 4.00 5.00 4.00 4.00 Basic -
D2 2.65 2.80 3.70 2.70 2.40 Reference -
E 5.00 5.00 5.00 4.00 4.00 Basic -
E2 3.65 3.80 3.70 2.70 2.40 Reference -
e 0.50 0.50 0.65 0.50 0.65 Basic -
L 0.40 0.40 0.40 0.40 0.60 ±0.05 -
N 28 24 20 20 16 Reference 4
ND 6 5 5 5 4 Reference 6
NE 8 7 5 5 4 Reference 5
Rev 10 12/04
NOTES:
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Tiebar view shown is a non-functional feature.
3. Bottom-side pin #1 I.D. is a diepad chamfer as shown.
4. N is the total number of terminals on the device.
5. NE is the number of terminals on the “E” side of the package
(or Y-direction).
6. ND is the number of terminals on the “D” side of the package
(or X-direction). ND = (N/2)-NE.
7. Inward end of terminal may be square or circular in shape with radius
(b/2) as shown.
8. If two values are listed, multiple exposed pad options are available.
Refer to device-specific datasheet.
