MIC2590A-3BTQ - Micrel, Inc.

March 2002 1 MIC2590A

MIC2590A Micrel

MIC2590A

Dual-Slot PCI Hot-Plug Controller

Preliminary Information

General Description

The MIC2590A is a power controller supporting power distri-

bution requirements for Peripheral Component Interconnect

(PCI) Hot-Plug compliant systems incorporating the Intelli-

gent Platform Management Interface (IPMI). The MIC2590A

provides complete power control support for two PCI slots

including the 3.3VAUX defined by the PCI 2.2 specification.

Support for +5V, +3.3V, +12V and –12V supplies is provided

including programmable constant-current inrush limiting,

voltage supervision, programmable current-limit, fault report-

ing and circuit breaker functions which provide fault isolation.

The MIC2590A also incorporates a SMBus interface in which

complete status and control of power within each slot is

provided. Data such as voltage and current from each supply

of each slot can be obtained for IPMI sensor records in

addition to power status of each slot.

Features

• Supports two independent PCI 2.2 slots

• SMBus interface for slot power control and status

• +5V, +3.3V, +12V, –12V, +3.3VAUX supplies supported

per PCI specification 2.2

• Programmable inrush current-limiting

• Active current regulation controls inrush current

• Electronic circuit breaker

• Dual level fault detection for quick fault response without

nuisance tripping

• Thermal isolation between circuitry for slot A

and slot B

Applications

• PCI hot-plug power distribution

Micrel, Inc. • 1849 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 944-0970 • http://www.micrel.com

Ordering Information

5V & 3V Fast-trip +12V & –12V Fast-trip

Part Number Threshold Threshold Operating Temp. Range Package

MIC2590A-2BTQ 100mV 1.5A/0.4A 0°C to +70°C 48-Pin TQFP

MIC2590A-3BTQ 150mV* 1.5A/0.4A 0°C to +70°C 48-Pin TQFP

MIC2590A-4BTQ 200mV* 1.5A/0.4A 0°C to +70°C 48-Pin TQFP

MIC2590A-5BTQ Disabled* 1.5A/0.4A 0°C to +70°C 48-Pin TQFP

*Contact factory for availability.

MIC2590A Micrel

MIC2590A 2 March 2002

Typical Application

VAUXA

5VINA

12VIN1 12VIN2 12MVIN1 12MVIN2

5VSENA

5VGATEA

5VOUTA

VSTBY1

VSTBY2

12SLEWA

12SLEWB

CFILTERA

3.3VAUXA

PCI Bus

5V, 5A

3VINA

3VSENA

3VGATEA

3VOUTA

12VOUTA

12MVOUTA

5VINB

3.3V, 7.6A

12V, 0.5A

–12V, 0.1A

5VSENB

5VGATEB

5VOUTB

3VINB

3VSENB

3VGATEB

3VOUTB

12VOUTB

12MVOUTB

VAUXB

5V, 5A

3.3V, 7.6A

12V, 0.5A

–12V, 0.1A

3.3VAUXB

SENSE

GATE

5VGATEA

3VGATEA

5VGATEB

3VGATEB

GATE

SENSE

GATE

SENSE

PCI Bus

4.7µF4.7µF

MIC2590

IREF

CFILTERB

GND

ONA/ONB

AUXENA/AUXENB

/FAULTA, /FAULTB

/INT

SCL

SDA

PCI

Connector

SDA

SCL

/INT

SDA

SCL

/INT

Management

Controller

Bus Switch

/OE

Hot-Plug

Controller

ONA/ONB

AUXENA/AUXENB

/FAULTA, /FAULTB

SMBus I/O

20k

Power

Supply

+12V

–12V

+5.0V

+3.3V

VSTBY

1A Schotty Diode

(Clamp)

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MIC2590A Micrel

Pin Configuration

12VMIN

3VOUTA

VAUXA

3VGATEA

3VSENSEA

12VMIN

12MVOUTA

12MVOUTB

14 1516 1718 19 20

/FAULTA

CFILTERA

12VSLEWA

GPIA

12VIN

5VINA

5VSENSEA

5VGATEA

5VOUTA

12VOUTA

VSTBY

3VINA

3VSENSEB

3VGATEB

VAUXB

3VOUTB

21 22 23 24

/FAULTB

CFILTERB

12VSLEWB

IREF

12VIN

5VINB

5VSENSEB

5VGATEB

5VOUTB

12VOUTB

VSTBY

3VINB

48 47 4645 4443 42 41 40 39 38 37

ONA

AUXENA

GND

SCL

SDA

ONB

AUXENB

/INT

GPIB

48-Pin TQFP (BTQ)

MIC2590A Micrel

MIC2590A 4 March 2002

Pin Description

Pin Number Pin Name Pin Function

6, 31 5VINA, 5VINB 5V Supply Power and Sense Inputs [A/B]: Two pins are provided for Kelvin

connection (one for each slot). Pin 6 is the Kelvin-sense connection to the

supply side of the sense resistor for 5V Slot A. Pin 31 is the Kelvin-sense

connection to the supply side of the sense resistor for 5V Slot B. These two

pins must ultimately connect to each other within 10cm. An undervoltage

lockout circuit (UVLO) prevents the switches from turning on while this input is

less than its lockout threshold.

12, 25 3VINA, 3VINB 3.3V Supply Power and Sense Inputs [A/B]: Two pins are provided for

Kelvin connection (one for each slot). Pin 12 is the Kelvin-sense connection to

the supply side of the sense resistor for 3V Slot A. Pin 25 is the Kelvin-sense

connection to the supply side of the sense resistor for 3V Slot B. These two

pins must ultimately connect to each other within 10cm. An undervoltage

lockout circuit (UVLO) prevents the switches from turning on while this input is

less than its lockout threshold.

5, 32 12VIN – 2 pins +12V Supply Input: An undervoltage lockout circuit prevents the switches from

turning on while this input is less than its lockout threshold. Both pins must be

tied together at the chip.

17,18 12VMIN – 2 pins –12V Supply Input: An undervoltage lockout circuit prevents the switches from

turning on while this input is less than its lockout threshold. Both pins must be

tied together at the chip.

10, 27 12VOUTA, 12VOUTB 12V output [A/B]

19, 20 12MVOUTA, 12MVOUTB –12V output [A/B]

3, 34 12VSLEWA, 12VSLEWB 12V Slew Rate Control [A/B]: Connect capacitors between these pins and

ground to set output slew rates of the +12V and -12V supplies.

45, 42 AUXENA, AUXENB AUX Enable Inputs [A/B]: Rising-edge sensitive enable inputs for VAUXA

and VAUXB outputs. Taking AUXENA/AUXENB low after a fault resets the

respective slot’s Aux Output Fault Latch. Tie these pins to ground if using

SMBus-mode power control.

16, 21 3VOUTA, 3VOUTB 3.3V Power-Good Sense Inputs: Connect to 3.3V[A/B] outputs. Used to

monitor the 3.3V output voltages for Power-Good status.

9, 28 5VOUTA, 5VOUTB 5V Power-Good Sense Inputs: Connect to 5V[A/B] outputs. Used to monitor

the 5V output voltages for Power-Good status.

33 IREF A resistor connected between this pin and ground sets the ADC current

measurement gain. This resistor must be 20kΩ ±1%.

7, 30 5VSENSEA, 5VSENSEB 5V Circuit Breaker Sense Input [A/B]: The current-limit thresholds are set by

connecting sense resistors between these pins and 5VIN[A/B]. When the

current-limit threshold of IR = 50mV is reached, the 5VGATE[A/B] pin is

modulated to maintain a constant voltage across the sense resistor and

therefore a constant current into the load. If the 50mV threshold is exceeded

for tFLT, the circuit breaker is tripped and the GATE pin for the affected slot is

immediately pulled low.

13, 24 3VSENSEA, 3VSENSEB 3V Circuit Breaker Sense Input [A/B]: The current-limit thresholds are set by

connecting sense resistors between these pins and 3VIN[A/B]. When the

current-limit threshold of IR = 50mV is reached, the 3VGATE[A/B] pin is

modulated to maintain a constant voltage across the sense resistor and

therefore a constant current into the load. If the 50mV threshold is exceeded

for tFLT, the circuit breaker is tripped and the GATE pin for the affected slot is

immediately pulled low.

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Pin Description

Pin Number Pin Name Pin Function

8, 29 5VGATEA, 5VGATEB 5V Gate Drive Outputs [A/B]: Each connects to the gate of an external N-

Channel MOSFET. During power-up the CGATE and the gate of the

MOSFETs are charged by a 20µA current source. This controls the value of

dv/dt seen at the source of the MOSFETs, and hence the current flowing into

the load capacitance.

During current-limit events, the voltage at this pin is adjusted to maintain

constant current through the switch for a period of tFLT. Whenever an

overcurrent, thermal shutdown or input undervoltage fault condition occurs

the GATE pin for the affected slot is immediately brought low.

During power-down these pins are discharged by an internal current source.

14, 23 3VGATEA, 3VGATEB 3V Gate Drive Outputs [A/B]: Each connects to the gate of an external N-

Channel MOSFET. During power-up the CGATE and the gate of the

MOSFETs are charged by a 20µA current source. This controls the value of

dv/dt seen at the source of the MOSFETs, and hence the current flowing into

the load capacitance.

During current-limit events, the voltage at this pin is adjusted to maintain

constant current through the switch for a period of tFLT. Whenever an

overcurrent, thermal shutdown or input undervoltage fault condition occurs

the GATE pin for the affected slot is immediately brought low.

During power-down these pins are discharged by an internal current source.

11, 26 VSTBY – 2 pins 3.3V Standby input voltage required to support PCI 2.2 VAUX input: SMBus,

internal registers and A/D converter run off of VSTBY to ensure chip access

during standby modes. A UVLO circuit prevents turn-on of this supply until

VSTBY rises above its UVLO threshold. Both pins must be tied together at

the chip.

15, 22 VAUXA, VAUXB VAUX[A/B] output voltages to PCI card slots: These outputs connect the

VAUX pin of the PCI 2.2 Connectors to VSTBY via internal 400mΩ

MOSFETs which are current-limited and protected against short-circuit

faults.

44, 43 ONA, ONB Enable input for MAIN outputs: Rising-edge sensitive. Used to enable or

disable MAIN (5V, 3.3V, +12V, –12V) outputs. Taking ONA/ONB low after a

fault resets the respective slot’s Main Output Fault Latch. Tie these pins to

ground if using SMBus-mode power control.

1, 36 /FAULTA, /FAULTB Open Drain, Active-Low: Asserted whenever the circuit breaker trips due to

a fault condition.

/FAULT[A/B] is reset by bringing the faulted slot’s ON pin low if /FAULT was

asserted in response to a fault condition on one of the slot’s MAIN outputs

(+12V, +5V, +3.3V, or –12V).

/FAULT[A/B] is reset by bringing the faulted slot’s AUXEN pin low if /FAULT

was asserted in response to a fault condition on the slot’s VAUX output.

If a fault condition occurred on both the MAIN and AUX outputs of the same

slot, then both ON and AUXEN must be brought low to de-assert the /FAULT

output.

2, 35 CFILTERA, CFILTERB Filter Capacitor [A/B]: Capacitors connected between these pins and ground

set the duration of tFLT. tFLT is the amount of time for which a slot remains in

current-limit before its circuit breaker is tripped.

37 /INT Interrupt Output: Open Drain, Active-low. Asserted whenever a power fault

is detected. Cleared by writing a logic 1 to the respective active bit into the

Status Register.

MIC2590A Micrel

MIC2590A 6 March 2002

Pin Description

Pin Number Pin Name Pin Function

48 SDA SMBus Data: Bidirectional SMBus data line.

47 SCL SMBus Clock: Input.

39, 40, 41 A2, A1, A0 SMBus Address Select pins: Connect to ground or leave open in order to

program device SMBus base address. There is an internal pull-up to VSTBY

on each of these inputs.

4, 38 GPIA, GPIB General Purpose Inputs: The state of these inputs are available by reading

the Common Status Register.

46 GND Ground.

March 2002 7 MIC2590A

MIC2590A Micrel

Absolute Maximum Ratings (Note 1)

Supply Voltage

(12VIN).....................................................................+14V

(12MVIN)..................................................................–14V

(5VIN).........................................................................+7V

(3VIN), (VSTBY) ..........................................................+7V

Any Logic Output Voltage ............ –0.5 (min.)/+5.5V (max.)

Any Logic Input Voltage ............... –0.5 (min.)/+5.5V (max.)

Output Current FAULT[A/B]#, (/INT, SDA).................10mA

Lead Temperature

IR Reflow, Peak Temperature.....................235 +5/–0°C

Storage Temperature (TS) .......................–65°C to +150°C

ESD Rating, Note 3 ...................................................1.5kV

Operating Ratings (Note 2)

Supply Voltage

(12VIN)............................................... +11.65V to +12.6V

(12MVIN).............................................. –11.0V to –13.2V

(5VIN)................................................... +4.85V to +5.25V

(3VIN)....................................................... +3.1V to +3.6V

(VSTBY) .................................................. +3.15V to +3.6V

Ambient Temperature (TA)............................. 0°C to +70°C

Junction Temperature (TJ) ........................................ 125°C

Package Thermal Resistance

TQFP (θJA) .......................................................56.5°C/W

Electrical Characteristics

12VIN = 12V; 12MVIN = –12V; 5VIN = 5V; 3VIN = 3.3V; VSTBY = 3.3V; TA = 0°C to 70°C; unless noted.

Power Control and Logic Sections

Symbol Parameter Condition Min Typ Max Units

ICC12 Supply Current 0.6 2.0 mA

ICC5 1.2 2.0 mA

ICC33 0.5 0.7 mA

ICC12M –1.0 –2.0 mA

ICCVSBY 2.5 5.0 mA

VUVLO Under-Voltage Lockout 12VIN increasing 8 9 10 V

3VIN increasing 2.2 2.5 2.75 V

5VIN increasing 3.7 4.0 4.3 V

12MVIN decreasing –10 –9–8V

VSTBY increasing 2.8 2.9 3.0 V

VHYSUV Under-Voltage Lockout Hysteresis - 180 mV

12VIN, 12MVIN, 5VIN, 3VIN

VHYSSTBY Under-voltage Lockout Hysteresis - 50 mV

VSTBY

VUVTH Power Good Under-Voltage Thresholds

VUVTH(12V) 12VOUT[A/B] 12VOUT[A/B] decreasing 10.2 10.5 10.8 V

VUVTH(12MV) 12MVOUT[A/B] 12MVOUT[A/B] increasing –10.8 –10.6 –10.2 V

VUVTH(3V) 3VOUT[A/B] 3VOUT[A/B] decreasing 2.7 2.8 2.9 V

VUVTH(5V) 5VOUT[A/B] 5VOUT[A/B] decreasing 4.4 4.5 4.7 V

VUVTH(VAUX) VAUX[A/B] VAUX[A/B] decreasing 2.7 2.8 2.9 V

VHYSPG Power-Good Detect Hysteresis 30 mV

VGATE 5VGATE/3VGATE Voltage 12VIN-1.5 12VIN V

GATE(SOURCE)

5VGATE/3VGATE Output Source start sycle 15 25 35 µA

Current

IGATE(SINK) 5VGATE/3VGATE Output Sink any fault condition, VGATE = 5V 70 mA

Fault Current

VFILTER CFILTER Threshold Voltage 1.20 1.25 1.30 V

IFILTER CFILTER[A/B] Charge Current V[5/3]VIN – V[5/3]VSENSE > VTHILIMIT 1.80 2.5 5.0 µA

ISLEW 12VSLEW[A/B] Charge Current During Turn-On Only 13 22 35 µA

VTHILIMIT Current Limit Threshold Voltages

5V[A/B] Supplies V5VIN – V5VSENSE 35 50 65 mV

3.3V[A/B] Supplies V3VIN – V3VSENSE 35 50 65 mV

VTHFAST 5VOUT[A/B] and 3VOUT[A/B] MIC2590A-2 90 113 135 mV

Fast-Trip Thresholds MIC2590A-3 150 mV

MIC2590A-4 200 mV

MIC2590A-5 Disabled

MIC2590A Micrel

MIC2590A 8 March 2002

Symbol Parameter Condition Min Typ Max Units

VIL LOW-Level Input Voltage 0.8 V

(SCL, SDA, ON[A/B], A[0-2],GPI[A/B])

VOL Output LOW Voltage IOL = 3mA 0.4 V

/FAULT[A/B], /INT, SDA

VIH HIGH-Level Input Voltage 2.1 V

SCL, SDA, ON[A/B], A[0-2],

AUXEN[A/B], GPI[A/B])

RPULL-UP Internal Pullups from A[0-2] to VSTBY 40 kΩ

IIL Input Leakage Current ±5µA

SCL, ON[A/B], AUXEN[A/B], GP[A/B])

ILKG(OFF) Off-State Leakage Current ±5µA

SDA, /FAULT[A/B], /INT

TOV Overtemperature Shutdown & Reset TJ Increasing, each slot, Note 5 140 °C

Thresholds, with overcurrent on slot TJ Decreasing, each slot, Note 5 130 °C

Overtemperature Shutdown & Reset TJ Increasing, both slots, Note 5 160 °C

Thresholds, all other conditions TJ Decreasing, both slots, Note 5 150 °C

(all outputs will latch OFF)

ROUT(ON) Output MOSFET Resistance

RDS(12V) 12V MOSFET IDS = 500mA, TJ = 125°C 500 mΩ

RDS(12VM) –12V MOSFET IDS = 100mA, TJ = 125°C2Ω

RDS(AUX) VAUX MOSFET IDS = 375mA, TJ = 125°C 400 mΩ

VOFF Off-State Output Offset Voltage

VOFF(+12V) 12VOUT[A/B] 12VOUT[A/B] = Off, TJ = 125°C50mV

VOFF(–12V) 12MVOUT[A/B] 12MVOUT[A/B] = Off, TJ = 125°C–50 mV

VOFF(VAUX) VAUX[A/B] VAUX[A/B] = Off, TJ = 125°C50mV

ITHSLOW Current Limit Threshold

ILIM(12) 12V MOSFET 12VOUT[A/B] = 0V 0.52 1.0 1.5 A

ILIM(12M) –12V MOSFET 12MVOUT[A/B] = 0V –0.11 –0.2 –0.3 A

ITHFAST Fast-Trip Thresholds 12VOUT[A/B] (MIC2590A-2) 1.0 2.15 3.0 A

12MVOUT[A/B] (MIC2590A-2) –0.20 –0.45 –0.6 A

IAUX(THRESH) Auxiliary Output Current Limit Threshold Current which must be drawn 0.84 A

Figure 4 from VAUX to register as a fault

ISC(TRAN)

Maximum Transient Short Circuit Current

VAUX Enabled, then Grounded IMAX = VSTBY / RDS(AUX) A

ILIM(AUX)

Regulated Current after Transient

From end of ISC(TRAN) to CFILTER Time-Out 0.375 0.7 1.35 A

RDISCH Output Discharge Resistance

R(12V) 12VOUT[A/B] 12VOUT[A/B] = 6.0V 1600 Ω

R(12MV) 12MVOUT[A/B] 12MVOUT[A/B] = –6.0V 600 Ω

R(3V) 3VOUT[A/B] 3VOUT[A/B] = 1.65V 150 Ω

R(5V) 5VOUT[A/B] 5VOUT[A/B] = 2.5V 150 Ω

R(3VAUX) 3VAUX[A/B] 5VOUT[A/B] = 1.65V 430 Ω

tOFF(3) Current Limit Response Time MIC2590A-2 with CGATE = 10nF, 1 µs

tOFF(5) for 3.3V and 5V Outputs, Figure 2 VIN – VSENSE = 200mV

TSC(TRAN) VAUX Current Limiter Response Time VAUX[A/B] = 0V, Note 5 33 µs

Figure 5

tOFF(12) 12V Current Limit Response 12VOUT[A/B] = 0V, Note 5 1µs

Figure 3

tOFF(12M) –12V Current Limit Response 12MVOUT[A/B] = 0V, Note 5 1µs

Figure 3

March 2002 9 MIC2590A

MIC2590A Micrel

Symbol Parameter Condition Min Typ Max Units

PROP(3VFAULT)

Delay from 3V[A/B] overcurrent-limit MIC2590A-2, VSENSE – VTHLIMIT =1µs

to FAULT Output 200mV, CFILTER = open

PROP(5VFAULT)

Delay from 5V[A/B] overcurrent-limit MIC2590A-2, VSENSE – VTHLIMIT =1µs

to FAULT Output 200mV, CFILTER = open

tWON[A/B], AUXEN[A/B] Pulse Width Note 5 100 ns

tPOR MIC2590A Power-On Reset Time Note 5 500 µs

after VSTBY becomes valid

8-Bit Analog to Digital Converter

Symbol Parameter Condition Min Typ Max Units

Total Unadjusted Error

Voltage, All Outputs –3+3%

Current, 3VOUT[A/B]/5VOUT[A/B] Measured as voltage across –3+3%

Current, VAUX[A/B], 12VOUT[A/B], corresponding external RSENSE ±3%

12MVOUT[A/B]

tCONV Conversion Time 60 100 ms

Resolution Specifications:

VAUXA Full Scale Voltage 3.85 V

VAUXB LSB of Voltage 15.1 mV

Full Scale Current 375 mA

LSB of Current 1.47 mA

3VOUTA Full Scale Voltage 3.85 V

3VOUTB LSB of Voltage 15.1 mV

Full Scale Current External RSENSE = 6.00mΩ11.6 A

LSB of Current 45.5 mA

5VOUTA Full Scale Voltage 5.89 V

5VOUTB LSB of Voltage 23.1 mV

Full Scale Current External RSENSE = 10.0mΩ6.96 A

LSB of Current 27.3 mA

12V

OUTA

Full Scale Voltage 13.8 V

12V

OUTB

LSB of Voltage 54.1 mV

Full Scale Current 500 mA

LSB of Current 1.96 mA

12MVOUTA Full Scale Voltage –13.6 V

12MVOUTB LSB of Voltage 53.5 mV

Full Scale Current 100 mA

LSB of Current 0.392 mA

SMBus Timing, Note 5

Symbol Parameter Condition Min Typ Max Units

t1SCL (Clock) Period Figure 1 2.5 µs

t2Data In Set-Up Time to SCL HIGH Figure 1 100 ns

t3Data Out Stable after SCL LOW Figure 1 300 ns

t4Data LOW Set-Up Time to Start Condition, Figure 1 100 ns

SCL LOW

t5Data HIGH Hold Time after Stop Condition, Figure 1 100 ns

SCL HIGH

Note 1. Exceeding the absolute maximum rating may damage the device.

Note 2. The device is not guaranteed to function outside its operating ratings.

Note 3. Devices are ESD sensitive. Employ proper handling precautions. Human body model, 1.5kΩ in series with 100pF.

Note 4. See the Applications Section.

Note 5. Parameters guaranteed by design. Not 100% production tested.

MIC2590A Micrel

MIC2590A 10 March 2002

Timing Diagrams

SCL

SDA

Data In

SDA

Data Out

Figure 1. SMBus Timing

3VGATE/5VGATE 1V

OFF35

THFAST

Figure 2. 3V/5V Current Limit Response Timing

OFF12[M]

LIM12[M]

OUT

THFAST

Figure 3. +12V/–12V Current Limit Response Timing

Must Trip

May Not Trip

OUT(AUX)

AUX(THRESH)

LIM(AUX)

Figure 4. VAUX Current Limit Threshold

tSC(TRAN)

ISC(TRAN)

ILIMAUX

IOUT(AUX)

Figure 5. VAUX Current Limit Response Timing

March 2002 11 MIC2590A

MIC2590A Micrel

Functional Description

Hot Swap Insertion

When circuit boards are inserted into systems carrying live

supply voltages (“hot-plugged”), high inrush currents often

result due to the charging of bulk capacitance that resides

across the circuit board’s supply pins. This transient inrush

current can cause the system’s supply voltages to tempo-

rarily go out of regulation, causing data loss or system lock-

up. In more extreme cases, the transients occurring during a

hot-plug event may cause permanent damage to connectors

or on-board components.

The MIC2590A addresses these issues by limiting the inrush

currents to the load (PCI Board), and thereby controlling the

rate at which the load’s circuits turn on. In addition, the

MIC2590A offers input and output voltage supervisory func-

tions and current-limiting to provide robust protection for both

the host system and the PCI board.

System Interfaces

The MIC2590A employs two system interfaces. One is the

Hot-Plug Interface (HPI) which includes ON[A/B], AUXEN[A/

B], and /FAULT[A/B]. The other is the System Management

Interface (SMI) consisting of SDA, SCL and /INT, (whose

signals conform to the specifications and format of Intel’s

SMBus standard). The MIC2590A can be operated exclu-

sively from the SMI, or can employ the HPI for power control

while continuing to use the SMI for access to all but the power

control registers.

In addition to the basic power control features of the MIC2590A

accessible by the HPI, the SMI also gives the host access to

the following information from the part:

1. Output voltage from each supply.

2. Output current from each supply.

3. Fault conditions occurring on each supply.

When using the System Management Interface for power

control, do not use the Hot-Plug Interface. Conversely, when

using the HPI for power control, do not execute power control

commands over the SMI bus (all other register accesses via

the SMI bus remain permissible while in the HPI control

mode).

Power-On Reset and Power Cycling

The MIC2590A utilizes VSTBY as the main supply input

source. It is required for proper operation of the MIC2590A

SMBus, registers and ADC and must be applied at all times.

A Power-On Reset (POR) cycle is initiated after VSTBY rises

above its UVLO threshold and remains valid at that voltage

for 500µs. All internal registers except RESULT are cleared

after POR. If VSTBY is recycled the MIC2590A enters a new

power-on reset cycle. VSTBY must be the first supply input

applied. Following the POR interval, the MAIN supply inputs

of 12VIN, 12MVIN, 5VIN and 3VIN may be applied in any

order. The SMBus is ready for access at the end of the POR

interval. During tPOR all outputs are off.

Power-Up Cycle (See Typical Application Circuit)

When a slot is off the 5VGATE and 3VGATE pins are held low

with an internal pull-down current source. When a slot’s main

outputs are enabled, and all input voltages are above their

respective undervoltage lockout thresholds, all four main

supplies execute a controlled turn on. At this time, the GATE

voltages of the 5V and 3.3V MOSFETs are ramped at a

controlled rate from 0V to approximately 11.5V. This is

sufficient to fully enhance the external MOSFETs for lowest

possible DC losses. The ramp rate is controlled by 25µA(typ)

current sources from the GATE pins charging each CGATE.

The magnitude and slew rate of the output current is propor-

tional to the value of CGATE and the load capacitance. The

minimum value of CGATE is selected to ensure that during

start-up the load current does not exceed the current-limit

threshold. The following equation is used to determine the

value of CGATE(min):

C (min) IIC

GATE GATE

LIM LOAD

=×

Where CLOAD is the load capacitance connected to the 3.3V

and 5V outputs and ILIM and IGATE are respectively the

current-limit and gate charge current specifications as given

in the Electrical Characteristics table. The output slew rate

dv/dt is computed by:

dv / dt (load) I

C10

GATE

GATE 6

=×

ISLEW = 25µA

CGATE dv/dt (load)

0.001µF 25000V/s

0.01µF 2500V/s

0.1µF 250V/s

1µF 25V/s

Table 1. 3.3V/5V Output Slew-Rate Selection

For the +12V and –12V supplies the output slew rate is

controlled by capacitors connected to the 12VSLEWA and

12VSLEWB pins. To determine the minimum value of the

slew rate capacitor, (CSLEW), connected to 12VSLEW[A/B],

the following equation is used:

C (min) IIC

SLEW SLEW

LIM LOAD

=×

where CLOAD is the load capacitance connected to the +12V

and –12V outputs, and ILIM and ISLEW are respectively the

current-limit and slew rate charge current values found in the

Electrical Characteristics table. The equation above com-

putes the minimum value to guarantee the device does not

enter into current-limit. The slew rate dv/dt is computed by:

dv / dt at load I

C10

SLEW

SLEW 6

=×

By appropriate selection of the value of CSLEW, it can be

ensured that the magnitude of the inrush current never

exceeds the current-limit for a given load capacitance. Since

one capacitor fixes the slew rate for both +12V and –12V, the

capacitor value should be chosen to provide the slower slew

rate of the two. Table 2 depicts the output slew rate for various

values of CSLEW.

MIC2590A Micrel

MIC2590A 12 March 2002

ISLEW = 22µA

CGATE dv/dt (load)

0.001µF 22000V/s

0.01µF 2200V/s

0.1µF 220V/s

1µF 22V/s

Table 2. ±12V Output Slew-Rate Selection

Power-Down Cycle

When a slot is turned off, internal switches are connected to

each of the outputs to discharge the PCI board's bypass

capacitors to ground.

Standby Mode

Standby mode is entered when any one (or more) enabled

MAIN supply input(s) (12VIN, 12MVIN, 5VIN and 3VIN) drops

below its respective UVLO threshold. The MIC2590A sup-

plies two 3.3V auxiliary outputs, VAUX[A/B], satisfying PCI

2.2 specifications. These outputs are fed via the VSTBY

input, and controlled by the AUXEN[A/B] inputs or via their

SMI bus Control Registers. These outputs are independent of

the MAIN outputs: should one or more of the MAIN supply

inputs move below its UVLO thresholds, VAUX[A/B] still

function as long as VSTBY is present. Prior to entering

standby mode, ONA and ONB (or the MAINA and MAINB bits

in the Control Registers) inputs should be de-asserted. If this

is not done, the MIC2590A will assert /FAULT, and also /INT

if interrupts are enabled, when the MIC2590A detects an

undervoltage condition on a supply input.

Circuit Breaker Functions

The MIC2590A provides an electronic circuit breaker function

that protects against excessive loads such as short circuits at

each supply. When the current from one or more of a slot’s

MAIN outputs exceeds the current-limit threshold

(50mV/RSENSE for 3.3V and 5V, 1.0A for +12V, and/or 0.2A

for –12V) for a duration greater than tFLT, the circuit breaker

is tripped and all MAIN supplies (all outputs except

VAUX[A/B]) are shut off. Should the load current exceed

ITHFAST (+12V and –12V), or cause a MAIN output’s VSENSE

to exceed VTHFAST (+3.3V and +5V), the outputs are shut off

with no delay. Undervoltage conditions on the MAIN supply

inputs also trip the circuit breaker, but only when the MAIN

outputs are enabled (to signal a supply input brown-out

condition).

The VAUX[A/B] outputs have their own separate circuit

breaker functions. VAUX[A/B] do not incorporate a fast-trip

threshold, but instead regulate the output current into a fault

to avoid exceeding their operating current-limit. The circuit

breaker will trip due to overcurrents on VAUX[A/B] when the

fault timer expires. This use of the tFLT timer prevents the

circuit breaker from tripping prematurely due to brief current

transients.

Following a fault condition, the outputs can be turned on

again via the ON inputs (if the fault occurred on one of the

MAIN outputs), via the AUXEN inputs (if the fault occurred on

the AUX outputs), or by cycling both ON and AUXEN (if faults

occurred on both the MAIN and AUX outputs). A fault condi-

tion can alternatively be cleared under SMI control of the

ENABLE bits in the CNTRL[A/B] registers. When the circuit

breaker trips, /FAULT[A/B] will be asserted if the outputs were

enabled through the Hot-Plug Interface (non-SMI mode)

inputs. At the same time, /INT will be asserted (unless

interrupts are masked). Note that /INT is de-asserted by

writing a logic 1 back into the respective fault bit position(s) in

the STAT[A/B] register or the Common Status Register.

tFLT is set by external capacitors, CFIL[A/B], connected to the

CFILTER[A/B] pins. The equation below can be used to

determine the capacitor value for a given duration of tFLT:

C 2.0 F t

1second

FIL FLT

≅×











Thermal Shutdown

The internal +12V, –12V and VAUX MOSFETs are protected

against damage not only by current-limiting, but by dual-

mode over-temperature protection as well. Each slot control-

ler on the MIC2590A is thermally isolated from the other.

Should an overcurrent condition raise the junction tempera-

ture of one slot’s controller and internal pass elements to

140°C, all of the outputs for that slot (including VAUX) will be

shut off, and the slot’s /FAULT output will be asserted. The

other slot’s operation will remain unaffected. However, should

the MIC2590A’s overall die temperature exceed 160°C, both

slots (all outputs, including VAUXA and VAUXB) will be shut

off, whether or not a current-limit condition exists. A 160°C

overtemperature condition additionally sets the

overtemperature bit (OT_INT) in the Common Status Regis-

ter.

A/D Converter

The MIC2590A has a 20-channel, 8-bit A/D converter ca-

pable of monitoring the output voltage and current of each

supply. This information is available via the System Manage-

ment Interface. The information is particularly intended for

use by systems that support the IPMI standard, but may be

used for any desired purpose.

March 2002 13 MIC2590A

MIC2590A Micrel

System Management Interface (SMI)

The MIC2590A’s System Management Interface uses the

Read_Byte and Write_Byte subset of the SMBus protocols to

communicate with its host via the System Management

Interface bus. Additionally, the /INT output signals the con-

trolling processor that one or more events need attention, if

an interrupt-driven architecture is used. Note that the

MIC2590A does not participate in the SMBus Alert Response

Address (ARA) portion of the SMBus protocol.

The SMBus Read_Byte operation consists of sending the

device’s slave address, followed by the target register’s

internal address, and then clocking out the byte to be read

from the target register. Similarly, the Write_Byte operation

consists of sending the device’s slave address, followed by

the target register’s internal address, and then clocking in the

byte to be written to the target register. The target register

addresses for the MIC2590A are given in Table 4.

Interrupt Generation

In the MIC2590A the /INT pin can be asserted (driven low)

whenever a fault condition trips the circuit breaker. The

MIC2590A can thus operate in either polled mode or interrupt

mode. In the polled mode the Interrupt Mask bit in the

Common Status Register should be set, to prevent the /INT

pin from being asserted. Upon a circuit breaker fault event the

appropriate status bit is also set in the corresponding status

AUXEN[x]

ON[x]

AUX OUT[x]

MAIN OUT[x]

FAULT DETECTED

ON AUX OUT[x]

FAULT DETECTED

ON MAIN OUT[x]

/FAULT OUTPUT[x]

/INT OUTPUT

(CLEARED BY SOFTWARE)

Figure 6. Hot-Plug Interface Mode Operation

registers. In order to clear the status bit the system must write

a logic 1 back to same bit in the status register. Upon

occurrence of the write the /INT pin will be de-asserted (if

interrupts were enabled), if no other interrupts are pending.

This method of “echo reset” allows data to be retained in the

status registers until such time as the system software is

ready to deal with that data, and then to control the earliest

time at which the next interrupt might occur.

MIC2590A SMBus Address Configuration

The MIC2590A responds to its own unique address which is

assigned using A2, A1 and A0. These represent the 3 LSBs

of its 7-bit address, as shown in Table 3. These address bits

are assigned only during power up of the VSTBY supply

input. These three bits allow up to eight MIC2590A devices in

a single system. These pins are either grounded or left

unconnected to specify a logical 0 or 1 respectively. A pin

designated as a logical 1 may also be pulled up to VSTBY.

Inputs MIC2590A Slave Address

A2 A1 A0 Binary Hex

0 0 0 1000 000b80h

0 0 1 1000 001b82h

0 1 0 1000 010b84h

0 1 1 1000 011b86h

1 0 0 1000 100b88h

1 0 1 1000 101b8Ah

1 1 0 1000 100b8Ch

1 1 1 1000 111b8Eh

Table 3. MIC2590A SMBus Addressing

MIC2590A Micrel

MIC2590A 14 March 2002

S1000

A2 A1 A0 x x x

00000XXXAxx x /Axx P

MIC2590A Slave Address

Master to slave transfer, i.e., DATA driven by master.

Slave to master transfer, i.e., DATA driven by slave.

DATA

CLK

Target Register Value read from MIC2590A

START STOP

R/W = READ ACKNOWLEDGE NOT ACKNOWLEDGE

Figure 7. READ_BYTE Protocol

S1000

A2 A1 A0 X X X

00000XXXAXX X /AXX P

MIC2590A Slave Address

Master to slave transfer, i.e., DATA driven by master.

Slave to master transfer, i.e., DATA driven by slave.

DATA

CLK

Target Register Value to be written to MIC2590A

START STOP

R/W = WRITE ACKNOWLEDGE NOT ACKNOWLEDGE

Figure 8. WRITE_BYTE Protocol

Command Power-On

Target Register Byte Value Default

Label Description Read Write

RESULT ADC Conversion Result Register 00

n/a n/a

ADCNTRL ADC Control Regster 01

CNTRLA Control Register Slot A 02

CNTRLB Control Register Slot B 03

STATA Slot A Status 04

STATB Slot B Status 05

STAT Common Status Register 06

Table 4. MIC2590A Register Addresses

March 2002 15 MIC2590A

MIC2590A Micrel

Control Register, Slot A (CNTRLA), 8-Bits Read/Write

D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]

read-only read-only read-only read-only read-only read-only read-write read-write

AUXAPG

MAINAPG

Reserved Reserved Reserved Reserved

MAINA VAUXA

Bit(s) Function Operation

AUXAPG AUX Output Power-Good 1 = Power-Good

Status, Slot A (VAUXA output is above

its VUVTH threshold)

MAINAPG MAIN Output Power-Good 1 = Power-Good

Status, Slot A (MAINA outputs are

above their VUVTH

thresholds)

D[5] Reserved Always Read As Zero

D[4] Reserved Always Read As Zero

D[3] Reserved Always Read As Zero

D[2] Reserved Always Read As Zero

MAINA MAIN Enable Control, 0 = OFF, 1 = ON

Slot A

VAUXA VAUX Enable Control, 0 = OFF, 1 = ON

Slot A

Power-Up Default Value: 0000 0000b = 00h

Command Byte (R/W): 0000 0010b = 02h

The power-up default value is 00h. Slot A is disabled upon

power-up, i.e., all supply outputs are off.

Control Register, Slot B (CNTRLB), 8-Bits Read/Write

D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]

read-only read-only read-only read-only read-only read-only read-write read-write

AUXBPG

MAINBPG

Reserved Reserved Reserved Reserved

MAINB VAUXB

Bit(s) Function Operation

AUXBPG AUX Output Power-Good 1 = Power-Good

Status, Slot B (VAUXB output is above

its VUVTH threshold)

MAINBPG MAIN Output Power-Good 1 = Power-Good

Status, Slot B (MAINB outputs are

abovetheir VUVTH

thresholds)

D[5] Reserved Always Read As Zero

D[4] Reserved Always Read As Zero

D[3] Reserved Always Read As Zero

D[2] Reserved Always Read As Zero

MAINB MAIN Enable Control, 0 = OFF, 1 = ON

Slot B

VAUXB VAUX Enable Control, 0 = OFF, 1 = ON

Slot B

Power-Up Default Value: 0000 0000b = 00h

Command Byte (R/W): 0000 0011b = 03h

The power-up default value is 00h. Slot B is disabled upon

power-up, i.e., all supply outputs are off.

Detailed Register Descriptions below:

Conversion Result Register (RESULT), 8-Bits Read Only

D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]

read-only read-only read-only read-only read-only read-only read-only read-only

Voltage or Current Data from ADC

Bit Function Operation

D[7:0] Measured data from ADC Read Only

Power-Up Default Value: Undefined following POR

Read Command Byte: 0000 0000b = 00h

(ADC Control Register (ADCNTRL), 8-Bits Read/Write

D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]

read-only read-only read-only read-write read-write read-write read-write read-write

BUSY

Reserved Reserved

SEL PAR Supply Select

SUP[2:0]

Bit(s) Function Operation

BUSY ADC Status 0 = ADC Quiescent,

1 = ADC Busy

D[6] Reserved Always Read As Zero

D[5] Reserved Always Read As Zero

SEL A/D Slot Select Specifies Channel for

A/D Conversion

0 = Slot A, 1 = Slot B

PAR Parameter Control Bit for 1 = Voltage,

ADC Conversion 0 = Current

SUP[2:0] Supply Select for 000 = No Conversion

ADC Conversion 001 = 3.3V Suppy

010 = 5.0V Supply

011 = +12V Supply

100 = –12V Supply

101 = VAUX Supply

Power-Up Default Value: 0000 0000b = 00h

Command Byte (R/W): 0000 0001b = 01h

To operate the ADC the ADCNTRL register must first be

initialized by selecting a slot, specifying whether voltage or

current is to be measured and then specifying the specific

supply that is to be monitored. The software must then

wait 100ms, or poll the BUSY bit until it is zero. The

RESULT register will then contain the valid result of the

conversion.

MIC2590A Micrel

MIC2590A 16 March 2002

Status Register, Slot A (STATA), 8-Bits Read Only

D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]

read-only read-only read-only read-write read-write read-write read-write read-write

FAULTA MAINA VAUXA

VAUXAF

12MVAF 12VAF 5VAF 3VAF

Bit(s) Function Operation

FAULTA FAULT Pin Status, Notes 1 & 2

Slot A

MAINA MAIN Enable Status, Represents actual state

Slot A (on/off) of the four main

power outputs for Slot A

(+12V, +5V, +3.3V and –12V)

1 = MAIN Power On

0 = MAIN Power Off

VAUXA VAUX Enable Status Represents actual state

Slot A (on/off) of the auxiliary

power outputs for Slot A

1 = AUX Power On

0 = AUX Power Off

VAUXFA Overcurrent Fault 1 = Fault; 0 = No Fault

VAUX Supply

12MVFA Overcurrent Fault 1 = Fault; 0 = No Fault

–12V Supply

12VFA Overcurrent Fault 1 = Fault; 0 = No Fault

+12V Supply

5VFA Overcurrent Fault 1 = Fault; 0 = No Fault

5V Supply

3VFA Overcurrent Fault 1 = Fault; 0 = No Fault

3.3V Supply

Power-Up Default Value: 0000 0000b = 00h

Read Command Byte (R/W): 0000 0100b = 04h

The power-up default value is 00h. The slot is disabled

upon power-up, i.e., all supply outputs are off. In response

to an overcurrent fault condition, writing a logical 1 back

into the active (or set) bit position will clear the bit and de-

assert /INT. The status of the /FAULTA pin is not affected

by reading the Status Register.

Status Register, Slot B (STATB), 8-Bits Read Only

D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]

read-only read-only read-only read-write read-write read-write read-write read-write

FAULTA MAINA VAUXA

VAUXAF

12MVAF 12VAF 5VAF 3VAF

Bit(s) Function Operation

FAULTB FAULT Pin Status, Notes 1 & 2

Slot B

MAINB MAIN Enable Status, Represents actual state

Slot B (on/off) of the four main

power outputs for Slot B

(+12V, +5V, +3.3V and –12V)

1 = MAIN Power On

0 = MAIN Power Off

VAUXB VAUX Enable Status Represents actual state

Slot B (on/off) of the auxiliary

power outputs for Slot B

1 = AUX Power On

0 = AUX Power Off

VAUXFB Overcurrent Fault 1 = Fault; 0 = No Fault

VAUX Supply

12MVFB Overcurrent Fault 1 = Fault; 0 = No Fault

–12V Supply

12VFB Overcurrent Fault 1 = Fault; 0 = No Fault

+12V Supply

5VFB Overcurrent Fault 1 = Fault; 0 = No Fault

5V Supply

3VFB Overcurrent Fault 1 = Fault; 0 = No Fault

3.3V Supply

Power-Up Default Value: 0000 0000b = 00h

Read Command Byte (R/W): 0000 0101b = 05h

The power-up default value is 00h. The slot is disabled

upon power-up, i.e., all supply outputs are off. In response

to an overcurrent fault condition, writing a logical 1 back

into the active (or set) bit position will clear the bit and de-

assert /INT. The status of the /FAULTB pin is not affected

by reading the Status Register.

Note 1. 1 = /FAULT[A/B] pin asserted, indicating a fault condition (/FAULT is LOW).

0 = /FAULT[A/B] pin is de-asserted (/FAULT is HIGH).

If FAULT[A/B] has been set by an overcurrent condition on one (or more) of the main outputs, the corresponding ON[A/B] must go LOW to

reset FAULT. If FAULT[A/B] has been set by an overcurrent on a VAUX output, the corresponding AUXEN[A/B] must go LOW to reset FAULT.

If an overcurrent has occurred on both a main output and VAUX output of a slot, both ON[A/B] and AUXEN[A/B] of the corresponding slot

must go LOW to reset FAULT.

Note 2. The FAULT bits, and the /FAULT pins, are not active when the MIC2590A power paths are controlled by the System Management Interface

(SMBus). When using SMI power path control for a slot, the AUXEN and ON pins for that slot must be tied to ground.

March 2002 17 MIC2590A

MIC2590A Micrel

Common Status Register, (STAT), 8-Bits Read/Write

D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]

read-only read-only read-only read-only read-write read-write read-write read-only

Reserved Reserved

GPIB GPIA INTMSK UV_INT OT_INT

Reserved

Bit(s) Function Operation

D[7] Reserved Always read as zero

D[6] Reserved Always read as zero

GPIB General Purpose Input, State of GPIB pin

Slot B

GPIA General Purpose Input, State of GPIA pin

Slot A

INTMSK Interrupt Mask 0 = /INT generation is

enabled; 1 = /INT

generation is disabled.

The MIC2590A does not

participate in the SMBus

Alert Response Address

(ARA) Protocol.

UV_INT Undervoltage Set whenever a circuit

Interrupt breaker fault condition

occurs as a result of an

undervoltage lockout

condition on one of the

main supply inputs. This

bit is only set if a UVLO

condition occurs while one

or both of the ON[A/B] pins

are asserted or the

MAIN[A/B] enable control

bits are set.

OT_INT Overtemperature Set whenever a circuit

Interrupt breaker fault occurs as a

result of an over-

temperature condition

exceeding 160°C shutting

both channels off.

D[0] Reserved Read Undefined

Power-Up Default Value: 0000 0000b = 00h

Command Byte (R/W): 0000 0110b = 06h

To reset the OT_INT and UV_INT fault bits a logical 1

must be written back to these bits.

MIC2590A Micrel

MIC2590A 18 March 2002

Application Information

Current Sensing

For the three power supplies switched with internal MOSFETs

(+12V, –12V, and V AUX), the MIC2590A provides all neces-

sary current sensing functions to protect the IC, the load, and

the power supply. For the remaining four supplies which the

part is designed to control, the high currents at which these

supplies typically operate makes sensing the current inside

the MIC2590A impractical. Therefore, each of these supplies

(3VA, 5VA, 3VB, and 5VB) requires an external current

sensing resistor. The VIN connection to the IC from each

supply (e.g., 5VINA) is connected to the positive terminal of

the slot’s current sense amplifier, and the corresponding

SENSE input (in this case, 5VSENSEA) is connected to the

negative terminal of the current sense amplifier.

Sense Resistor Selection

The MIC2590A uses low-value sense resistors to measure

the current flowing through the MOSFET switches to the

loads. These sense resistors are nominally valued at

50mΩ/ILOAD(CONT). To accommodate worst-case tolerances

for both the sense resistor, (allow ±3% over time and tem-

perature for a resistor with ±1% initial tolerance) and still

supply the maximum required steady-state load current, a

slightly more detailed calculation must be used.

The current-limit threshold voltage (the “trip point”) for the

MIC2590A may be as low as 35mV, which would equate to a

sense resistor value of 35mΩ/ILOAD(CONT). Carrying the

numbers through for the case where the value of the sense

resistor is 3% high, this yields:

1.03 I 34m

SENSE

LOAD(CONT) LOAD(CONT)

=Ω

()

=Ω

Once the value of RSENSE has been chosen in this manner,

it is good practice to check the maximum ILOAD(CONT) which

the circuit may let through in the case of tolerance build-up in

the opposite direction. Here, the worst-case maximum is

found using a 65mV trip voltage and a sense resistor which

is 3% low in value. The resulting current is:

I65mV

(0.97)(R ) 67mA

LOAD(CONT.MAX) SENSE(NOM) SENSE(NOM)

As an example, if an output must carry a continuous 4.4A

without nuisance trips occurring, RSENSE for that output

should be 34mΩ/4.4A = 7.73mΩ. The nearest standard value

is 7.5mΩ, so a 7.5mΩ ±1% resistor would be a good choice.

At the other set of tolerance extremes,

ILOAD(CONT, MAX) for the output in question is then simply

67mV/7.5mΩ = 8.93A. Knowing this final datum, we can

determine the necessary wattage of the sense resistor, using

P = I2R. Here I will be ILOAD(CONT, MAX), and R will be

(0.97)(RSENSE(NOM)). These numbers yield the following:

PMAX = (8.93A)2(7.28mΩ) = 0.581W

A 1.0W sense resistor would work well in this application.

Kelvin Sensing

Because of the low values of the sense resistors, special care

must be used to accurately measure the voltage drop across

them. Specifically, the voltage across each RSENSE must

employ Kelvin sensing. This is simply a means of making sure

that any voltage drops in the power traces connecting to the

resistors are not picked up in addition to the voltages across

the sense resistors themselves. If accuracy must be paid for,

it’s worth keeping.

Figure 9 illustrates how Kelvin sensing is performed. As can

be seen, all the high current in the circuit (let us say, from

+5VINA through RSENSE and then to the drain of the +5VA

output MOSFET) flows directly through the power PCB

traces and RSENSE. The voltage drop resulting across RSENSE

is sampled in such a way that the high currents through the

power traces will not introduce any extraneous IR drops.

SENSE

Power T race

From V

Power T race

To MOSFET Drain

Signal T race

to MIC2590A V

Signal T race

to MIC2590A V

SENSE

Figure 9. Kelvin Sensing Connections for RSENSE

MOSFET Selection

Selecting the proper MOSFET for use as current pass and

switching element for each of the 3V and 5V slots of the

MIC2590A involves four straightforward tasks:

1. Choice of a MOSFET which meets the minimum

voltage requirements.

2. Determination of maximum permissible on-state

resistance [RD-S(ON)].

3. Selection of a device to handle the maximum continu-

ous current (steady-state thermal issues).

4. Verification of the selected part’s ability to withstand

current peaks (transient thermal issues).

MOSFET Voltage Requirements

The first voltage requirement for each MOSFET is easily

stated: the drain-source breakdown voltage of the MOSFET

must be greater than VIN(MAX) for the slot in question. For

instance, the 5V input may reasonably be expected to see

high-frequency transients as high as 5.5V. Therefore, the

drain-source breakdown voltage of the MOSFET must be at

least 6V.

The second breakdown voltage criteria which must be met is

a bit subtler than simple drain-source breakdown voltage, but

is not hard to meet. Low-voltage MOSFETs generally have

low breakdown voltage ratings from gate to source as well. In

MIC2590A applications, the gates of the external MOSFETs

are driven from the +12V input to the IC. That supply may well

be at 12V + (5% x 12V) = 12.6V. At the same time, if the output

of the MOSFET (its source) is suddenly shorted to ground,

the gate-source voltage will go to (12.6V – 0V) = 12.6V. This

March 2002 19 MIC2590A

MIC2590A Micrel

means that the external MOSFETs must be chosen to have

a gate-source breakdown voltage in excess of 13V; after 12V

absolute maximum the next commonly available voltage

class has a permissible gate-source voltage of 20V maxi-

mum. This is a very suitable class of device. At the present

time, most power MOSFETs with a 20V gate-source voltage

rating have a 30V drain-source breakdown rating or higher.

As a general tip, look to surface-mount devices with a drain-

source rating of 30V as a starting point.

MOSFET Maximum On-State Resistance

The MOSFETs in the +3.3V and +5V MAIN power paths will

have a finite voltage drop, which must be taken into account

during component selection. A suitable MOSFET’s data

sheet will almost always give a value of on resistance for the

MOSFET at a gate-source voltage of 4.5V, and another value

at a gate-source voltage of 10V. As a first approximation, add

the two values together and divide by two to get the on

resistance of the device with 7 Volts of enhancement (keep

this in mind; we’ll use it in the following Thermal Issues

sections). The resulting value is conservative, but close

enough. Call this value RON. Since a heavily enhanced

MOSFET acts as an ohmic (resistive) device, almost all that

is required to calculate the voltage drop across the MOSFET

is to multiply the maximum current times the MOSFET’s RON.

The one addendum to this is that MOSFETs have a slight

increase in RON with increasing die temperature. A good

approximation for this value is 0.5% increase in RON per °C

rise in junction temperature above the point at which RON was

initially specified by the manufacturer. For instance, the

Vishay (Siliconix) Si4430DY, which is a commonly used part

in this type of application, has a specified RDS(ON) of 8.0mΩ

max. at VG-S = 4.5V, and RDS(ON) of 4.7mΩ max. at VG-S =

10V. Then RON is calculated as:

R4.7m 8.0m

26.35m

ON ΩΩ Ω

()

at 25°C TJ. If the actual junction temperature is estimated to

be 110°C, a reasonable approximation of RON for the

Si4430DY at temperature is:

6.35m 1 110 –25 0.5%

C6.35m 1 85 0.5%

C9.05mΩΩΩ+°°

()



















=+°

()



















≅

Note that this is not a closed-form equation; if more precision

were required, several iterations of the calculation might be

necessary. This is demonstrated in the section “MOSFET

Transient Thermal Issues.”

For the given case, if Si4430DY is operated at an IDRAIN of

7.6A, the voltage drop across the part will be approximately

(7.6A)(9.05mΩ) = 69mV.

MOSFET Steady-State Thermal Issues

The selection of a MOSFET to meet the maximum continuous

current is a fairly straightforward exercise. First, arm yourself

with the following data:

•The value of ILOAD(CONT, MAX) for the output in

question (see Sense Resistor Selection).

•The manufacturer’s data sheet for the candidate

MOSFET.

•The maximum ambient temperature in which the

device will be required to operate.

•Any knowledge you can get about the heat

sinking available to the device (e.g., Can heat be

dissipated into the ground plane or power plane,

if using a surface-mount part? Is any airflow

available?).

Now it gets easy: steady-state power dissipation is found by

calculating I2R. As noted in “MOSFET Maximum On-State

Resistance,” above, the one further concern is the MOSFET’s

increase in RON with increasing die temperature. Again, use

the Si4430DY MOSFET as an example, and assume that the

actual junction temperature ends up at 110°C. Then RON at

temperature is again approximately 9.05mΩ. Again allow a

maximum IDRAIN of 7.6A:

Power dissipation I R 7.6A 9.05m 0.523W

DRAIN2ON 2

≅×=

()

×≅Ω

The next step is to make sure that the heat sinking available

to the MOSFET is capable of dissipating at least as much

power (rated in °C/W) as that with which the MOSFET’s

performance was specified by the manufacturer. Formally

put, the steady-state electrical model of power dissipated at

the MOSFET junction is analogous to a current source, and

anything in the path of that power being dissipated as heat

into the environment is analogous to a resistor. It’s therefore

necessary to verify that the thermal resistance from the

junction to the ambient is equal to or lower than that value of

thermal resistance (often referred to as Rθ(JA)) for which the

operation of the part is guaranteed. As an applications issue,

surface-mount MOSFETs are often less than ideally speci-

fied in this regard—it’s become common practice simply to

state that the thermal data for the part is specified under the

conditions “Surface mounted on FR-4 board, t ≤10seconds,”

or something equally mystifying. So here are a few practical

tips:1. The heat from a surface-mount device such as

an SO-8 MOSFET flows almost entirely out of

the drain leads. If the drain leads can be sol-

dered down to one square inch or more of

copper the copper will act as the heat sink for

the part. This copper must be on the same layer

of the board as the MOSFET drain.

2. Since the rating for the part is given as “for 10

seconds,” derate the maximum junction tem-

perature by 35°C. This is the standard good

practice derating of 25°C, plus another 10°C to

allow for the time element of the specification.

3. Airflow, if available, works wonders. This is not

the place for a dissertation on how to perform

airflow calculations, but even a few LFM (linear

feet per minute) of air will cool a MOSFET down

MIC2590A Micrel

MIC2590A 20 March 2002

In terms related directly to the specification and use of power

MOSFETs, this is known as “transient thermal impedance.”

Almost all power MOSFET data sheets give a Transient

Thermal Impedance Curve, which is a handy tool for making

sure that you can safely get by with a less expensive MOSFET

than you thought you might need. For example, take the case

where tFLT for the 5V supply has been set to 50msec,

ILOAD(CONT, MAX) is 5.0A, the slow-trip threshold is 50mV

nominal, and the fast-trip threshold is 100mV. If the output is

connected to a 0.60Ω load, the output current from the

MOSFET for the slot in question will be regulated to 5.0A for

50ms before the part’s circuit breaker trips. During that time,

the dissipation in the MOSFET is given by:

P = E × IE

MOSFET = [5V–5A(0.6Ω)] = 2V

PMOSFET = (2V × 5A) = 10W for 50msec.

Wow! Looks like we need a really hefty MOSFET to withstand

just this unlikely—but plausible enough to protect against—

fault condition. Or do we? This is where the transient thermal

impedance curves become very useful. Figure 10 shows

those curves for the Vishay (Siliconix) Si4430DY, a com-

monly used SO-8 power MOSFET:

–3

–2

1 10 60010

–1

–4

100

0.1

0.01

0.2

0.1

0.05

0.02

Single Pulse

Duty Cycle = 0.5

Normalized Thermal Transient Impedance, J unction-to-Ambient

Square Wave Pulse Duration (sec)

Normalized Effectiv e Transient

Thermal Impedance

1. Duty Cycle, D =

2. Per Unit Base = R

thJA

= 67°C/W

3. T

– T

= P

thJA(t)

Notes:

4. Surface Mounted

Figure 10. Si4430DY MOSFET Transient Thermal Impedance Curve

dramatically. If you can position the MOSFET(s)

in question near the inlet of a power supply’s

fan, or the outlet of a processor’s cooling fan,

that’s always a good free ride.

4. Although it seems a rather unsatisfactory

statement, the best test of a surface-mount

MOSFET for an application (assuming the

above tips show it to be a likely fit) is an empiri-

cal one. The ideal evaluation is in the actual

layout of the expected final circuit, at full operat-

ing current. The use of a thermocouple on the

drain leads, or in infrared pyrometer on the

package, will then give a reasonable idea of the

device’s junction temperature.

MOSFET Transient Thermal Issues

Having chosen a MOSFET that will withstand the imposed

voltage stresses, and be able to handle the worst-case continu-

ous I2R power dissipation which it will see, it remains only to

verify the MOSFET’s ability to handle short-term overload

power dissipation without overheating. Here, nature and phys-

ics work in our favor: a MOSFET can handle a much higher

pulsed power without damage than its continuous dissipation

ratings would imply. The reason for this is that, like everything

else, semiconductor devices (silicon die, lead frames, etc.)

have thermal inertia. This is easily understood by all of us who

have stood waiting for a pot of water to boil.

Using this graph is not nearly as daunting as it may at first

appear. Taking the simplest case first, we’ll assume that once

a fault event such as the one in question occurs, it will be a

long time, 10 minutes or more, before the fault is isolated and

the slot is reset. In such a case, we can approximate this as

a “single pulse” event, that is to say, there’s no significant duty

cycle. Then, reading up from the X-axis at the point where

“Square Wave Pulse Duration” is equal to 0.1sec (=100msec),

we see that the effective thermal impedance of this MOSFET

to a single pulse event of this duration is only 6% of its

continuous Rθ(JA).

This particular part is specified as having an Rθ(JA) of

50°C/W for intervals of 10 seconds or less. So, some further

math, just to get things ready for the finale:

Assume TA = 55°C maximum, 1 square inch of copper at the

drain leads, no airflow.

March 2002 21 MIC2590A

MIC2590A Micrel

Assume the MOSFET has been carrying just about 5A for

some time.

Then the starting (steady-state)TJ is:

TJ ≅ 55°C + (7.3mΩ)(5A)2(30°C/W)

TJ ≅ 60.5°C

Iterate the calculation once to see if this value is within a few

percent of the expected final value. For this iteration we will

start with TJ equal to the already calculated value of 67°C:

RON at TJ = 60.5°C = [1+(60.5°C–25°)(0.5%/°C)]×6.35mΩ

RON at TJ = 60.5°C ≅ 7.48mΩ

TJ ≅ 55°C + (7.3mΩ)(5A)2(30°C/W)

TJ ≅ 60.6°C

At this point, the simplest thing to do is to approximate TJ as

61°C, which will be close enough for all practical purposes.

Finally, add (10W)(67°C/W)(0.03) = 21°C to the steady-state TJ

to get TJ(TRANSIENT MAX) = 82°C. The Si4430DY can easily

handle this value of TJ(MAX).

A second illustration of the use of the transient thermal imped-

ance curves: assume that the system will attempt multiple

retries on a slot showing a fault, with a one second interval

between retry attempts. This frequency of restarts will signifi-

cantly increase the dissipation in the Si4430DY MOSFET. Will

the MOSFET be able to handle the increased dissipation? We

get the following:

The same part is operating into a persistent fault, so it is cycling

in a square-wave fashion (no steady-state load) with a duty

cycle of (50msec/second = 0.05).

On the Transient Thermal Impedance Curves, read up from the

X-axis to the line showing Duty Cycle equaling 0.05. The

effective Rθ(JA) = (0.7 x 67°C/W) = 4.7°C/W.

Calculating the peak junction temperature:

TJ(PEAK MAX) = [(10W)(4.7°C/W) + 55°C] = 102°C.

And finally, checking the RMS power dissipation just to be

complete:

P 5A 7.47m 0.05 0.042W

RMS 2

()( )

=Ω

which will result in a negligible temperature rise.

The Si4430DY is electrically and thermally suitable for this

application.

MOSFET and Sense Resistor Selection Guide

Listed below, by Manufacturer and Type Number, are some

of the more popular MOSFET and resistor types used in PCI

hot-plug applications. Although far from comprehensive, this

information will constitute a good starting point for most

designs.

Power Supply Decoupling

In general, prudent system design requires that power sup-

plies used for logic functions should have less than 100mV of

noise at frequencies of 100kHz and above. This is especially

true given the speeds of modern logic families, such as the

1.2 micron CMOS used in the MIC2590A. The internal logic

of the MIC2590A is powered from the 3.3VAUX supply, and

that supply should not carry HF noise in excess of 100mV

peak-to-peak with respect to chip ground, especially at

frequencies ≥1MHz.

Less obviously but equally importantly, the –12V supply

should have less than 100mV of peak-to-peak noise at

frequencies of 1MHz or higher. This is because the –12V

supply is the most negative potential applied to the IC, and is

therefore connected to the device’s substrate. All of the

subcircuits integrated onto the silicon chip are hence sub-

jected by capacitive coupling to any HF noise on the –12V

supply. While the individual capacitances are quite low, the

amount of injected energy required to cause a “glitch” can

also be quite low at the internal nodes of high speed logic

circuits.

If either the 3.3VAUX source supply, the –12V source supply,

or both supplies do carry significant HF noise (as can happen

when they are locally derived by a switching converter), the

solution is both small and inexpensive. A simple LC filter

made of a ferrite bead between the noisy power supply input

and the MIC2590A, followed by one 1µF and one 10nF

ceramic capacitor from the MIC2590A input pin to ground will

suffice for almost any situation. A suggested ferrite bead for

MOSFET Vendors Key MOSFET Type(s) Web Address

Vishay (Siliconix) Si4430DY (“LittleFoot” Series) www.siliconix.com

Si4420DY (“LittleFoot” Series)

International Rectifier IRF7413A (SO-8 package part) www.irf.com

Si4420DY (second source to Vishay)

Fairchild Semiconductor FDS6644 (SO-8 package part) www.fairchildsemi.com

FDS6670A (SO-8 package part)

FDS6688 (SO-8 package part)

Resistor Vendors Sense Resistors Web Address

Vishay (Dale) “WSL” Series www.vishay.com/docs/wsl_30100.pdf

IRC “OARS” Series irctt.com/pdf_files/OARS.pdf

“LR” Series irctt.com/pdf_files/LRC.pdf

(second source to “WSL”)

MIC2590A Micrel

MIC2590A 22 March 2002

such use is Fair-Rite Products Corporation part # 2743019447

(this is a surface-mountable part). Similar parts from other

vendors will also work well, or a 0.27µH, air-core coil can be

used.

Noisy V

To MIC2590A

SMT Ferrite Bead

Fair-Rite Products

Type 2743019447 1µF

Ceramic 1µF

Ceramic

Figure 11. Filter Circuit for Noisy Supplies

(+3.3V and/or –12V)

It is theoretically possible that high-amplitude, HF noise

reflected back into one or both of the MIC2590A’s –12V

outputs could interfere with proper device operation, al-

though such noisy loads are unlikely to occur in the real world.

If this becomes an application-specific concern, a pair of

filters similar to that in Figure 11 will provide the required HF

bypassing. The capacitors would be connected to the

MIC2590A’s –12V output pins, and the ferrite beads would be

placed between the –12V output pins and the loads.

–12V Input Clamp Diode

The –12V input to the MIC2590A is the most negative

potential on the part, and is therefore connected to the chip’s

substrate (as described in “Power Supply Decoupling,” above).

Although no particular sequencing of the –12V supply rela-

tive to the other MIC2590A supplies is required for normal

operation, this substrate connection does mean that the

–12V input must never exceed the voltage on the GROUND

pin of the IC by more than 0.3 volts. In some systems, even

though the –12V supply will discharge towards ground poten-

tial when it is turned OFF, the possibility exists that power

supply output ringing or L(di/dt) effects in the wiring and on the

PCB itself will cause brief transient voltages in excess of

+0.3V to appear at the –12V input. The simplest way to deal

with such a transient is to clamp it with a Schottky diode. The

diode’s anode should be physically placed directly at the

–12V input to the MIC2590A, and its cathode should have as

short a path as possible back to the part’s ground. A good

SMT part for this application is ON Semiconductor’s type

MBRS140T3 (1A, 40V). Although the 40V rating of this part

is a bit gratuitous, it is an inexpensive industry-standard part

with many second sources. Unless it is absolutely known in

advance that the voltage on the “–12V” inputs will never

exceed 0.0V at the IC’s –12V input pins, it’s wise to at least

leave a position for this diode in the board layout and then

remove it later. This final determination should be made by

observations of the voltage at the –12V input with a fast

storage oscilloscope, under turn-on and turn-off conditions.

Gate Resistor Guidelines

The MIC2590A controls four external power MOSFETs,

which handle the high currents for each of the two 3.3V and

5V outputs. A capacitor (CGATE) is connected in the applica-

tion circuit from each GATE pin of the MIC2590A to ground.

Each CGATE controls the ramp-up rate of its respective power

output (e.g., 5VOUTB). These capacitors, which are typically

in the 10nF range, cause the GATE outputs of the MIC2590A

to have very low AC impedances to ground at any significant

frequency. It is therefore necessary to place a modest value

of gate damping resistance (RGATE) between each CGATE

and the gate of its associated MOSFET. These resistances

prevent high-frequency MOSFET source-follower oscilla-

tions from occurring. The exact value of the resistors used is

not critical; 47Ω is usually a good choice. Each RGATE should

be physically located directly adjacent to the MOSFET gate

lead to which it connects.

MIC2590A

GATE

47Ω

GATE

External

MOSFET

Figure 12. Proper Connection

of CGATE and RGATE

March 2002 23 MIC2590A

MIC2590A Micrel

Package Information

48-Pin TQFP (BTQ)

MIC2590A Micrel

MIC2590A 24 March 2002

MICREL INC. 1849 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL + 1 (408) 944-0800 FAX + 1 (408) 944-0970 WEB http://www.micrel.com

This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or

other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.