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Old Company Name in Catalogs and Other Documents
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April 1st, 2010
Renesas Electronics Corporation
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RENESAS LSIs
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
M5M5256DFP,VP -70G,-70GI,-70XG
PACKAGE
M5M5256DFP : 28 pin 450 mil SOP
M5M5256DVP : 28pin 8 X 13.4 mm TSOP
•Single 3.0~5.5V power supply
•No clocks, no refresh
•Data-Hold on +2.0V power supply
•Directly TTL compatible : all inputs and outputs
•Three-state outputs : OR-tie capability
•/OE prevents data contention in the I/O bus
•Common Data I/O
•Battery backup capability
•Low stand-by current .......... 0.05µA(typ.)
APPLICATION
Small capacity memory units
DESCRIPTION
The M5M5256DFP,VP is 262,144-bit CMOS static RAMs
organized as 32,768-words by 8-bits which is fabricated using
high-performance 3 polysilicon CMOS technology. The use of
resistive load NMOS cells and CMOS periphery results in a high
density and low power static RAM. Stand-by current is small
enough for battery back-up application. It is ideal for the memory
systems which require simple interface.
Especially the M5M5256DVP are packaged in a 28-pin thin small
outline package.
FEATURE
PIN CONFIGURATION (TOP VIEW)
1
20µA
(Vcc=5.5V)
(Vcc=5.5V)
40µA
(max) Stand-by
(max)
Active
(max)
Power supplycurrent
Type Access
time
45mA
M5M5256DFP,VP
-70G 70ns
M5M5256DFP,VP
-70GI 70ns 24µA
(Vcc=5.5V)
A14
A12
A6
A5
A4
A3
A2
A1
A0
A7
DQ1
DQ2
DQ3
GND
Vcc
A13
A8
A9
A11
A10
DQ8
DQ7
DQ6
DQ5
DQ4
/W
/OE
/S
28
26
25
24
23
21
18
17
16
15
27
22
20
19
1
2
4
5
6
7
8
9
10
3
11
12
13
14
Outline 28P2C-A (VP)
Outline 28P2W-C (FP)
2
M5M5256DVP
A14
A12
A6
A5
A4
A3
A7
A2
A1
A0
DQ1
DQ2
DQ3
GND
Vcc
A13
A8
A9
A11
/W
/OE A10
DQ7
DQ6
DQ5
DQ4
/S
DQ8
8
9
10
11
12
13
14
21
18
17
16
15
20
19
1
2
4
5
6
7
3
23
22
24
25
26
27
28
M5M5256DFP,VP
-70XG 70ns
(Vcc=3.0V Typical)
0.05µA
(Vcc=5.5V)
5µA
12µA
(Vcc=3.6V)
(Vcc=3.6V)
(Vcc=3.6V)
2.4µA
25mA
(Vcc=3.6V)
Oprating
Temperature
0~70°C
-40~85°C
0~70°C
RENESAS LSIs
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
M5M5256DFP,VP -70G,-70GI,-70XG
FUNCTION TABLE
The operation mode of the M5M5256DFP,VP is
determined by a combination of the device control inputs
/S, /W and /OE. Each mode is summarized in the function
table.
A write cycle is executed whenever the low level /W
overlaps with the low level /S. The address must be set
up before the write cycle and must be stable during the
entire cycle. The data is latched into a cell on the trailing
edge of /W, /S, whichever occurs first, requiring the set-
up and hold time relative to these edge to be maintained.
The output enable /OE directly controls the output stage.
Setting the /OE at a high level,the output stage is in a
high-impedance state, and the data bus contention
problem in the write cycle is eliminated.
Mode DQ Icc
/S /W /OE
Non selection
Write
Read
Stand-by
Active
Active
Active
High-impedance
DIN
DOUT
XX
L
L
L
LX
L
H
H
H
H
High-impedance
2
A read cycle is executed by setting /W at a high level
and /OE at a low level while /S are in an active state.
When setting /S at a high level, the chip is in a non-
selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a high-
impedance state, allowing OR-tie with other chips and
memory expansion by /S. The power supply current is
reduced as low as the stand-by current which is specified
as Icc3 or Icc4, and the memory data can be held at
+2V power supply, enabling battery back-up operation
during power failure or power-down operation in the non-
selected mode.
VCC
(5V)
GND
(0V)
27
20
22
2
3
4
6
5
7
25
26
1
8
9
10
21
23
24
2
12
11
13
15
16
17
18
19
(512 ROWS X
512 COLUMNS)
32768 WORD
X 8BIT
GENERATOR
CLOCK
A 14
A 13
A 8
A 12
A 6
A 7
A 10
A 0
A 1
A 2
A 3
A 4
A 5
A 11
A 9
/W
/OE
/S
28
14
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
ADDRESS
INPUT
DATA I/O
WRITE CONTROL
INPUT
OUTPUT ENABLE
INPUT
CHIP SELECT
INPUT
BLOCK DIAGRAM
Note • "H" and "L" in this table mean VIH and VIL, respectively.
• "X" in this table should be "H" or "L".
RENESAS LSIs
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
M5M5256DFP,VP -70G,-70GI,-70XG
3
ABSOLUTE MAXIMUM RATINGS
CAPACITANCE
Symbol Parameter
Test conditions
pF
Unit
Max
6
8
TypMin
Limits
VI=GND, VI=25mVrms, f=1MHz
VO=GND,VO=25mVrms, f=1MHz
Input capacitance
Output capacitance
CI
CO
DC ELECTRICAL CHARACTERISTICS
Symbol Parameter
V
V
V
Limits2
Test conditions
Unit
V
µA
Note 0: Direction for current flowing into an IC is positive (no mark).
1: Typical value is one at Ta = 25°C.
2: CI, C O are periodically sampled and are not 100% tested.
mA
mA
V
Active supply current
(AC, MOS level )
Icc1
Icc2
Stand-by currentIcc4
VIH High-level input voltage
VIL Low-level input voltage
IOOutput current in off-state
Icc3Stand-by current
VOH1 High-level output voltage 1 IOH=-1mA (Vcc=5.0±0.5V)
VOH2 High-level output voltage 2
VOL Low-level output voltage
IIInput current VI=0~Vcc
Vcc
+0.3
0.8
2.2
-0.3*
2.4
3
0.4
4025
2
0.4
Vcc
-0.5
±1
MaxTypMin
Parameter
Supply voltage
Input voltage
Output voltage
Power dissipation
Operating temperature
Unit
V
V
V
mW
°C
Conditions
With respect to GND
Ta=25°C 700
0~70
Ratings
Symbol
Vcc
VI
VO
Pd
Topr
-0.3*~7.0
-0.3*~Vcc+0.3
0~Vcc
(Max 7.0)
/S=VIH,other inputs=0~Vcc
/S=VIH or or /OE=VIH, VI/O=0~Vcc
mA
other inputs=VIH or VIL
4525
Active supply current
(AC, TTL level )
or >Vcc-0.2V
±1
* -3.0V in case of AC ( Pulse width < 30ns )
_
/S>Vcc-0.2V,
other inputs =0~Vcc
_
Limits1
0.6
2.0
-0.3*
2.4
0.33
0.4
2513
1.2
0.3
Vcc
-0.5
±1
MaxTypMin
2514
±1
IOH=-0.5mA (Vcc=3.3±0.3V)
IOL=2mA (Vcc=5.0±0.5V)
IOL=1mA (Vcc=3.3±0.3V)
* -3.0V in case of AC ( Pulse width < 30ns )
_
(Vcc=3.3±0.3V)
IOH=-0.1mA (Vcc=5.0±0.5V)
IOH=-0.05mA (Vcc=3.3±0.3V)
(Vcc=5.0±0.5V)
-G,-GI
-XG
5
0.1
2.4
0.05
Storage temperature -65~150
Tstg
-G,-XG
-GI -40~85 °C
Other inputs<0.2V
_
/S<0.2V, Output-open
/S=VIL, Output-open
~25°C
~40°C
~70°C
~85°C
-G,-GI
-XG
-G,-GI
-XG
-GI
6
1.2
3.6
0.8 2012
4024
pF
µA
µA
70ns
1MHz
4231.5
8431.5
70ns
1MHz
Vcc
+0.3
RENESAS LSIs
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
M5M5256DFP,VP -70G,-70GI,-70XG
4
(1) READ CYCLE
Symbol Parameter
tCR Read cycle time
Address access time
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Limits1
ta(S)
ta(OE)
tdis(S)
tdis(OE)
ten(S)
ten(OE)
tV(A)
ta(A)
AC ELECTRICAL CHARACTERISTICS
Chip select access time
Output enable access time
Output disable time after /S high
Output disable time after /OE high
Output enable time after /S low
Output enable time after /OE low
Data valid time after address
MaxMinMin Max 70
5
5
10
70
70
35
25
25
Limits2
Vcc=3.3±0.3V Vcc=5.0±0.5V
70
5
5
10
70
70
35
25
25
(2) WRITE CYCLE
Symbol Parameter Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write cycle time
Write pulse width
Address setup time
Address setup time with respect to /W high
Chip select setup time
Data setup time
Data hold time
Write recovery time
Output disable time from /W low
Output disable time from /OE high
Output enable time from /W high
Output enable time from /OE low
MaxMinMaxMin
tCW
tw(W)
tsu(A)
tsu(A-WH)
tsu(S)
tsu(D)
th(D)
trec(W)
tdis(W)
tdis(OE)
ten(W)
ten(OE)
70
50
0
65
65
30
0
0
5
5
25
25
Limits1 Limits2
Vcc=3.3±0.3V Vcc=5.0±0.5V
70
55
0
65
65
30
0
0
5
5
25
25
RENESAS LSIs
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
M5M5256DFP,VP -70G,-70GI,-70XG
5
Read cycle
(3) TIMING DIAGRAMS
DATA VALID
(Note 3) (Note 3)
ta(A)
ta (S)
tv (A)
tdis(S)
ta (OE)
ten (OE)
tdis (OE)
(Note 3) (Note 3)
tCR
ten (S)
/W = "H" level
DQ1~8
/S
/OE
A0~14
ten (W)
Write cycle (/W control mode)
th (D)tsu (D)
DQ1~8
/S tsu (S)
/OE
tsu (A-WH)
ten(OE)
tdis (OE)
(Note 3) (Note 3)
/W
tw (W) trec (W)tsu (A)
tdis (W)
tCW
A0~14
DATA IN
STABLE
(Note 3) (Note 3)
RENESAS LSIs
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
M5M5256DFP,VP -70G,-70GI,-70XG
6
Write cycle ( /S control mode)
tsu (S) trec (W)
th (D)
tCW
(Note 5)
(Note 3) (Note 3)
tsu (A)
(Note 4)
tsu (D)
DATA IN
STABLE
DQ1~8
/S
/W
A0~14
Note 3 : Hatching indicates the state is "don't care".
5 : If /W goes low simultaneously with or prior to /S, the outputs remain in the high impedance state.
6 : Don't apply inverted phase signal externally when DQ pin is output mode.
4 : Writing is executed in overlap of /S and /W low.
7 : ten, tdis are periodically sampled and are not 100% tested.
(4) MEASUREMENT CONDITIONS
Input pulse level .............. V IH=2.4V,VIL=0.6V
Input rise and fall time ..... 5ns
Reference level ................ VOH=VOL=1.5V
Output load ...................... Fig.2, CL=100pF
CL=5pF (for ten,tdis)
Transition is measured ±500mV from steady
state voltage. (for ten,tdis)
Vcc
DQ
C
L
Fig.2 Output load
1.8kΩ
990Ω
(Including
scope and JIG)
Limits1:Vcc=3.3±0.3V
Input pulse level .............. V IH=2.4V,VIL=0.4V
Input rise and fall time ..... 5ns
Reference level ................ VOH=VOL=1.5V
Output load ...................... Fig.1, CL=30pF
CL=5pF (for ten,tdis)
Transition is measured ±500mV from steady
state voltage. (for ten,tdis)
Limits2:Vcc=5.0±0.5V
DQ
C
L
Fig.1 Output load
(Including
scope and JIG)
RENESAS LSIs
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
M5M5256DFP,VP -70G,-70GI,-70XG
7
(3) POWER DOWN CHARACTERISTICS
/S control mode
POWER DOWN CHARACTERISTICS
(1) ELECTRICAL CHARACTERISTICS
Power down set up time
Power down recovery time
(2) TIMING REQUIREMENTS
tsu (PD)
trec (PD)
Symbol
Parameter
ns
MaxTyp
Limits
Min
Test conditions
Unit
0
tCR ns
2.2V
tsu (PD) 3.0V
2.2V
trec (PD)
/S > Vcc-0.2V
Vcc
/S
Symbol
Parameter
V
V
MaxTyp
Limits
Min
Test conditions
Unit
V
2
1
0.2
Vcc (PD)
Icc (PD)
Power down supply voltage
Power down supply current
2.2
VI (/S) Chip select input /S
3.0V
2.2V < VCC(PD)
2V< VCC(PD) < 2.2V VCC(PD)
_
_
_
Vcc = 3V, /S > Vcc-0.2V,
Other inputs=0~Vcc
_
_
0.05 3µA
-G,-GI
-XG
~25°C
-G,-GI
-XG
~40°C
-G,-GI
-XG
~70°C
-GI
~85°C
0.6
10
2
20
RENESAS LSIs
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
M5M5256DFP,VP -70G,-70GI,-70XG
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the information contained herein.
· Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please
contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes,
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(i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
REJ03C0054 © 2003 Renesas Technology Corp.
New publication, effective Feb 2004.
Specifications subject to change without notice
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Notes regarding these materials
Keep safety first in your circuit designs!
