Sample & Buy Product Folder Support & Community Tools & Software Technical Documents LM8261 SNOS469J - APRIL 2000 - REVISED JANUARY 2015 LM8261 Single RRIO High Output Current & Unlimited Cap Load Op Amp 1 Features 3 Description * The LM8261 is a Rail-to-Rail input and output Op Amp which can operate with a wide supply voltage range. This device has high output current drive, greater than Rail-to-Rail input common mode voltage range, unlimited capacitive load drive capability, and provides tested and guaranteed high speed and slew rate while requiring only 0.97 mA supply current. It is specifically designed to handle the requirements of flat panel TFT panel VCOM driver applications as well as being suitable for other low power, and medium speed applications which require ease of use and enhanced performance over existing devices. 1 * * * * * * * * * * * (VS = 5 V, TA = 25C, Typical Values Unless Specified) GBWP 21 MHz Wide Supply Voltage Range 2.5 V to 30 V Slew Rate 12 V/s Supply Current 0.97 mA Cap Load Limit Unlimited Output Short Circuit Current 53 mA/ -75 mA 5% Settling Time 400 ns (500 pF, 100 mVPP Step) Input Common Mode Voltage 0.3 V Beyond Rails Input Voltage Noise 15nV/Hz Input Current Noise 1pA/Hz THD+N < 0.05% 2 Applications * * * * TFT-LCD Flat Panel VCOM Driver A/D Converter Buffer High Side/low Side Sensing Headphone Amplifier Greater than Rail-to-Rail input common mode voltage range with 50 dB of Common Mode Rejection allows high side and low side sensing, among many applications, without concern over exceeding the range and with no compromise in accuracy. Exceptionally wide operating supply voltage range of 2.5 V to 30 V alleviates any concerns over functionality under extreme conditions and offers flexibility for use in multitude of applications. In addition, most device parameters are insensitive to power supply variations; this design enhancement is yet another step in simplifying its usage. The output stage has low distortion (0.05% THD+N) and can supply a respectable amount of current (15 mA) with minimal headroom from either rail (300 mV). The LM8261 is offered in the space-saving SOT-23-5 package. Device Information(1) PART NUMBER LM8261 PACKAGE SOT-23 (5) BODY SIZE (NOM) 2.9 mm x 1.6 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Output Response with Heavy Capacitive Load 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM8261 SNOS469J - APRIL 2000 - REVISED JANUARY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 7 1 1 1 2 3 4 Absolute Maximum Ratings ...................................... 4 ESD Ratings.............................................................. 4 Recommended Operating Conditions....................... 4 Thermal Information .................................................. 4 Electrical Characteristics 2.7 V ................................. 5 Electrical Characteristics 5 V .................................... 7 Electrical Characteristics 15 V ................................ 9 Typical Characteristics ............................................ 11 Application and Implementation ........................ 19 7.1 Block Diagram and Operational Description ........... 19 7.2 7.3 7.4 7.5 Driving Capacitive Loads ........................................ Estimating the Output Voltage Swing ..................... TFT Applications ..................................................... Output Short Circuit Current and Dissipation Issues....................................................................... 7.6 Other Application Hints ........................................... 8 9 20 22 23 23 24 Power Supply Recommendations...................... 25 Layout ................................................................... 25 9.1 Layout Guidelines ................................................... 25 9.2 Layout Example ...................................................... 26 10 Device and Documentation Support ................. 27 10.1 10.2 10.3 10.4 Documentation Support ........................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 27 27 27 27 11 Mechanical, Packaging, and Orderable Information ........................................................... 27 4 Revision History Changes from Revision I (March 2013) to Revision J Page * Added, updated, or revised the following sections: Pin Configuration and Functions, Specifications, Detailed Description , Application and Implementation, Power Supply Recommendations , Layout , Device and Documentation Support , and Mechanical, Packaging, and Orderable Information section ................................................. 1 * Changed from -1.0 V to -0.8 V in Specifications ................................................................................................................... 4 Changes from Revision H (March 2013) to Revision I * 2 Page Changed layout of National Data Sheet to TI format ............................................................................................................. 1 Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8261 LM8261 www.ti.com SNOS469J - APRIL 2000 - REVISED JANUARY 2015 5 Pin Configuration and Functions 5-Pin SOT-23 Package DBV (Top View) Pin Functions PIN NUMBER 1 NAME I/O DESCRIPTION Output O Output 2 V- I Negative Supply 3 IN+ I Non-inverting input 4 IN- I Inverting Input 5 V+ I Positive Supply Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8261 3 LM8261 SNOS469J - APRIL 2000 - REVISED JANUARY 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings (1) MIN VIN Differential MAX UNIT 10 V 32 V See (2) (3) Output Short Circuit Duration Supply Voltage (V+ - V-) Voltage at Input/Output pins (2) (3) (4) V +150 C (4) Soldering Information: (1) V, V -0.8 V -65 Storage Temperature Range Junction Temperature V+ +0.8 - 150 C Infrared or Convection (20 sec.) 235 C Wave Soldering (10 sec.) 260 C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Rating indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see Electrical Characteristics 2.7 V. Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150C. Allowable Output Short Circuit duration is infinite for VS 6 V at room temperature and below. For VS > 6 V, allowable short circuit duration is 1.5 ms. The maximum power dissipation is a function of TJ(max), RJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/ RJA. All numbers apply for packages soldered directly onto a PC board. 6.2 ESD Ratings VALUE V(ESD) (1) (2) (3) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) (2) UNIT 2000 Machine model (MM) (3) V 200 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 2000-V HBM is possible with the necessary precautions. Pins listed as 200 V may actually have higher performance. Human Body Model is 1.5 k in series with 100 pF. Machine Model, 0 is series with 200 pF. 6.3 Recommended Operating Conditions MIN MAX Supply Voltage (V+ - V-) 2.5 30 V Temperature Range (1) -40 +85 C (1) UNIT The maximum power dissipation is a function of TJ(max), RJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/ RJA. All numbers apply for packages soldered directly onto a PC board. 6.4 Thermal Information THERMAL METRIC (1) (2) RJA (1) (2) 4 Junction-to-ambient thermal resistance DBV (5 PINS) 325 UNIT C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The maximum power dissipation is a function of TJ(max), RJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/ RJA. All numbers apply for packages soldered directly onto a PC board. Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8261 LM8261 www.ti.com SNOS469J - APRIL 2000 - REVISED JANUARY 2015 6.5 Electrical Characteristics 2.7 V Unless otherwise specified, all limits guaranteed for TA = 25C, V+ = 2.7 V, V- = 0 V, VCM = 0.5 V, VO = V+/2, and RL > 1 M to V-. (1) PARAMETER TEST CONDITIONS VOS Input Offset Voltage VCM = 0.5 V & VCM = 2.2 V TC VOS Input Offset Average Drift VCM = 0.5 V & VCM = 2.2 V (4) Common Mode Rejection Ratio VCM = 0.5 V & VCM = 2.2 V CMVR Positive Power Supply Rejection Ratio Input Common-Mode Voltage Range -65C TJ +150C +/-2 V+ = 2.7 V to 5 V CMRR > 50 dB -65C TJ +150C Output Swing Low ISC (1) (2) (3) (4) (5) (6) (7) Output Short Circuit Current 78 -0.3 -0.1 63 -65C TJ +150C 3.0 2.8 78 70 73 67 2.59 2.49 2.53 2.45 90 100 2.7 -65C TJ +150C RL = 10K to V- 104 0.0 VO = 0.5 to 2.2 V, RL = 2K to V- RL = 2K to V dB 58 74 2.46 - VO nA 76 70 -65C TJ +150C -65C TJ +150C A 50 67 Output Swing High 250 100 -65C TJ +150C RL = 10K to V- +1.00 60 VO = 0.5 to 2.2 V, RL = 10K to V- Large Signal Voltage Gain V/C 400 100 -65C TJ +150C mV +1.60 -65C TJ +150C -65C TJ +150C UNIT -2.00 -2.70 20 -65C TJ +150C AVOL +/-7 VCM stepped from 1.7 V to 2.7 V VCM stepped from 0 V to 2.7 V +PSRR +/-5 -65C TJ +150C VCM stepped from 0 V to 1.0 V CMRR +/-0.7 +0.49 VCM = 2.2 V (5) Input Offset Current MAX (3) -65C TJ +150C Input Bias Current IOS TYP (2) -1.20 VCM = 0.5 V (5) IB MIN dB V V dB dB V 2.41 -65C TJ +150C 120 Sourcing to V- VID = 200 mV (6) (7) -65C TJ +150C 20 Sinking to V+ VID = -200 mV (6) (7) -65C TJ +150C 30 48 30 65 50 mV mA mA Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self heating where TJ > TA. Typical Values represent the most likely parametric norm. All limits are guaranteed by testing or statistical analysis. Offset voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change. Positive current corresponds to current flowing into the device. Production Short Circuit test is a momentary test. See Note 7. Allowable Output Short Circuit duration is infinite for VS 6V at room temperature and below. For VS > 6V, allowable short circuit duration is 1.5 ms. Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8261 5 LM8261 SNOS469J - APRIL 2000 - REVISED JANUARY 2015 www.ti.com Electrical Characteristics 2.7 V (continued) Unless otherwise specified, all limits guaranteed for TA = 25C, V+ = 2.7 V, V- = 0 V, VCM = 0.5 V, VO = V+/2, and RL > 1 M to V-.(1) PARAMETER TEST CONDITIONS MIN TYP (2) MAX (3) 0.95 1.20 UNIT IS Supply Current No load, VCM = 0.5 V SR Slew Rate (8) AV = +1,VI = 2 VPP fu Unity Gain-Frequency VI = 10 mV, RL = 2 K to V+/2 GBWP Gain Bandwidth Product f = 50 KHz Phim Phase Margin VI = 10 mV 50 Deg en Input-Referred Voltage Noise f = 2 KHz, RS = 50 15 nV/ Hz in Input-Referred Current Noise f = 2 KHz 1 pA/ Hz fMAX Full Power Bandwidth ZL = (20 pF || 10 K) to V+/2 1 MHz (8) 6 -65C TJ +150C 1.50 9 V/s 10 MHz 21 -65C TJ +150C mA 14 15.5 MHz Slew rate is the slower of the rising and falling slew rates. Connected as a Voltage Follower. Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8261 LM8261 www.ti.com SNOS469J - APRIL 2000 - REVISED JANUARY 2015 6.6 Electrical Characteristics 5 V (1) Unless otherwise specified, all limited guaranteed for TA = 25C, V+ = 5 V, V- = 0 V, VCM = 1 V, VO = V+/2, and RL > 1 M to V -. PARAMETER TEST CONDITIONS Input Offset Voltage VCM = 1 V & VCM = 4.5 V TC VOS Input Offset Average Drift VCM = 1 V & VCM = 4.5 V (4) IB Input Bias Current VCM = 4.5 V (5) IOS Input Offset Current VCM = 1 V & VCM = 4.5 V VCM stepped from 0 V to 3.3 V CMRR +PSRR CMVR Common Mode Rejection Ratio Positive Power Supply Rejection Ratio Input Common-Mode Voltage Range RL = 10 K to V- Sourcing to V- VID = 200 mV (6) (7) (1) (2) (3) (4) (5) (6) (7) Output Short Circuit Current -65C TJ +150C Sinking to V+ VID = -200 mV (6) (7) V/C +1.00 250 400 110 64 104 78 -0.3 -0.1 0.0 -65C TJ +150C 5.0 -65C TJ +150C 70 -65C TJ +150C 66 -65C TJ +150C 4.72 5.3 5.1 84 74 80 70 4.87 4.75 4.81 4.70 86 125 dB V V dB V 4.66 -65C TJ +150C -65C TJ +150C dB 80 -65C TJ +150C -65C TJ +150C nA 84 100 -65C TJ +150C A 72 74 RL = 2 K to V- mV +1.60 20 -65C TJ +150C Output Swing High ISC -65C TJ +150C V+ = 2.7 V to 5 V, VCM = 0.5 V RL = 10 K to V- Output Swing Low +0.49 UNIT -2.00 -2.70 61 VO = 0.5 to 4.5 V, RL = 2 K to V- VO -65C TJ +150C -65C TJ +150C Large Signal Voltage Gain +/-5 +/-2 -1.18 -65C TJ +150C MAX (3) +/- 7 VCM stepped from 0 V to 5 V VO = 0.5 to 4.5 V, RL = 10 K to V- AVOL -65C TJ +150C VCM stepped from 4 V to 5 V CMRR > 50 dB TYP (2) +/-0.7 VOS VCM = 1 V (5) MIN 135 53 35 75 60 20 mV mA 50 Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self heating where TJ > TA. Typical Values represent the most likely parametric norm. All limits are guaranteed by testing or statistical analysis. Offset voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change. Positive current corresponds to current flowing into the device. Production Short Circuit test is a momentary test. See Note 7. Allowable Output Short Circuit duration is infinite for VS 6V at room temperature and below. For VS > 6V, allowable short circuit duration is 1.5ms. Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8261 7 LM8261 SNOS469J - APRIL 2000 - REVISED JANUARY 2015 www.ti.com Electrical Characteristics 5 V(1) (continued) Unless otherwise specified, all limited guaranteed for TA = 25C, V+ = 5 V, V- = 0 V, VCM = 1 V, VO = V+/2, and RL > 1 M to V -. PARAMETER TEST CONDITIONS TYP (2) MIN 0.97 MAX (3) 1.25 UNIT IS Supply Current No load, VCM = 1 V SR Slew Rate (8) AV = +1, VI = 5 VPP fu Unity Gain Frequency VI = 10 mV, RL = 2 K to V+/2 GBWP Gain-Bandwidth Product f = 50 KHz Phim Phase Margin VI = 10 mV 53 Deg en Input-Referred Voltage Noise f = 2 KHz, RS = 50 15 nV/ hZ in Input-Referred Current Noise f = 2 KHz 1 pA/ hZ -65C TJ +150C 1.75 12 -65C TJ +150C 10 7 10.5 21 -65C TJ +150C + 15 mA V/s MHz 16 MHz fMAX Full Power Bandwidth ZL = (20 pF || 10 k) to V /2 900 KHz tS Settling Time (5%) 100 mVPP Step, 500 pF load 400 ns THD+N Total Harmonic Distortion + Noise RL = 1 K to V+/2 f = 10 KHz to AV= +2, 4 VPP swing (8) 8 0.05% Slew rate is the slower of the rising and falling slew rates. Connected as a Voltage Follower. Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8261 LM8261 www.ti.com SNOS469J - APRIL 2000 - REVISED JANUARY 2015 6.7 Electrical Characteristics 15 V (1) Unless otherwise specified, all limited guaranteed for TA = 25C, V+ = 15 V, V- = -15 V, VCM = 0 V, VO = 0 V, and RL > 1 M to 0 V. PARAMETER TEST CONDITIONS VOS Input Offset Voltage VCM = -14.5 V & VCM = 14.5 V TC VOS Input Offset Average Drift VCM = -14.5 V & VCM = 14.5 V (4) VCM = -14.5 V (5) IB Input Bias Current VCM = 14.5 V (5) IOS Input Offset Current CMRR Common Mode Rejection Ratio Negative Power Supply Rejection V- = -12 V to -15 V Ratio CMVR Input Common-Mode Voltage Range CMRR > 50 dB VO = 0 V to 13 V, RL = 10 K Large Signal Voltage Gain VO = 0 V to 13 V, RL = 2 K RL = 10 K Output Swing High RL = 2 K VO RL = 10 K Output Swing Low RL = 2 K Sourcing to ground VID = 200 mV (6) (7) ISC Output Short Circuit Current Sinking to ground VID = 200 mV (6) (7) (1) (2) (3) (4) (5) (6) (7) +/- 9 +/-2 -65C TJ +150C 275 A nA 84 100 dB 88 74 100 70 100 70 -15.3 -15.1 72 66 -65C TJ +150C 66 -65C TJ +150C -15.0 -65C TJ +150C 15.0 -65C TJ +150C 74 -65C TJ +150C 66 -65C TJ +150C 14.61 15.3 15.1 85 78 79 72 14.83 14.65 14.73 14.60 -14.91 -14.75 dB dB V V dB V 14.55 -65C TJ +150C -14.65 -14.83 -65C TJ +150C -65C TJ +150C +1.00 80 -65C TJ +150C -65C TJ +150C V/C 550 100 -65C TJ +150C mV +1.50 30 -65C TJ +150C UNIT -2.00 -2.80 VCM stepped from 14 V to 15 V -PSRR +/-7 +0.49 -65C TJ +150C V+ = 12 V to 15 V +/-0.7 -65C TJ +150C VCM stepped from -15 V to 13 V Positive Power Supply Rejection Ratio MAX (3) -1.05 -65C TJ +150C +PSRR TYP (2) -65C TJ +150C VCM = -14.5 V & VCM = 14.5 V VCM stepped from -15 V to 15 V AVOL MIN -14.65 V -14.60 60 40 100 70 25 mA 60 Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self heating where TJ > TA. Typical Values represent the most likely parametric norm. All limits are guaranteed by testing or statistical analysis. Offset voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change. Positive current corresponds to current flowing into the device. Production Short Circuit test is a momentary test. See Note 7. Allowable Output Short Circuit duration is infinite for VS 6 V at room temperature and below. For VS > 6 V, allowable short circuit duration is 1.5 ms. Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8261 9 LM8261 SNOS469J - APRIL 2000 - REVISED JANUARY 2015 www.ti.com Electrical Characteristics 15 V(1) (continued) Unless otherwise specified, all limited guaranteed for TA = 25C, V+ = 15 V, V- = -15 V, VCM = 0 V, VO = 0 V, and RL > 1 M to 0 V. PARAMETER TEST CONDITIONS IS Supply Current No load, VCM = 0 V SR Slew Rate (8) AV = +1, VI = 24 VPP fu Unity Gain Frequency VI = 10 mV, RL = 2 K MIN TYP (2) MAX (3) 1.30 1.50 -65C TJ +150C 1.90 15 -65C TJ +150C 10 8 14 24 UNIT mA V/s MHz 18 GBWP Gain-Bandwidth Product f = 50 KHz Phim Phase Margin VI = 10 mV 58 Deg en Input-Referred Voltage Noise f = 2 KHz, RS = 50 15 nV/ hZ in Input-Referred Current Noise f = 2 KHz 1 pA/ hZ fMAX Full Power Bandwidth ZL = 20 pF || 10 K 160 ts Settling Time (1%, AV = +1) Positive Step, 5 VPP 320 Negative Step, 5 VPP 600 THD+N Total Harmonic Distortion +Noise (8) 10 -65C TJ +150C RL = 1 K, f = 10 KHz, AV = +2, 28VPP swing 16 MHz KHz ns 0.01% Slew rate is the slower of the rising and falling slew rates. Connected as a Voltage Follower. Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8261 LM8261 www.ti.com SNOS469J - APRIL 2000 - REVISED JANUARY 2015 6.8 Typical Characteristics TA = 25C, Unless Otherwise Noted Figure 1. VOS vs. VCM for 3 Representative Units Figure 2. VOS vs. VCM for 3 Representative Units Figure 3. VOS vs. VCM for 3 Representative Units Figure 4. VOS vs. VS for 3 Representative Units Figure 5. VOS vs. VS for 3 Representative Units Figure 6. VOS vs. VS for 3 Representative Units Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8261 11 LM8261 SNOS469J - APRIL 2000 - REVISED JANUARY 2015 www.ti.com Typical Characteristics (continued) TA = 25C, Unless Otherwise Noted 12 Figure 7. IB vs. VCM Figure 8. IB vs. VS Figure 9. IS vs. VCM Figure 10. IS vs. VCM Figure 11. IS vs. VCM Figure 12. IS vs. VS (PNP side) Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8261 LM8261 www.ti.com SNOS469J - APRIL 2000 - REVISED JANUARY 2015 Typical Characteristics (continued) TA = 25C, Unless Otherwise Noted Figure 13. IS vs. VS (NPN side) Figure 14. Gain/Phase vs. Frequency Figure 15. Unity Gain Frequency vs. VS Figure 16. Phase Margin vs. VS Figure 17. Unity Gain Freq. and Phase Margin vs. VS Figure 18. Unity Gain Frequency vs. Load Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8261 13 LM8261 SNOS469J - APRIL 2000 - REVISED JANUARY 2015 www.ti.com Typical Characteristics (continued) TA = 25C, Unless Otherwise Noted 14 Figure 19. Phase Margin vs. Load Figure 20. Unity Gain Freq. and Phase Margin vs. CL Figure 21. CMRR vs. Frequency Figure 22. +PSRR vs. Frequency Figure 23. -PSRR vs. Frequency Figure 24. Output Voltage vs. Output Sourcing Current Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8261 LM8261 www.ti.com SNOS469J - APRIL 2000 - REVISED JANUARY 2015 Typical Characteristics (continued) TA = 25C, Unless Otherwise Noted Figure 25. Output Voltage vs. Output Sourcing Current Figure 26. Output Voltage vs. Output Sinking Current Figure 27. Max Output Swing vs. Load Figure 28. Max Output Swing vs. Frequency Figure 29. % Overshoot vs. Cap Load Figure 30. 5% Settling Time vs. Cap Load Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8261 15 LM8261 SNOS469J - APRIL 2000 - REVISED JANUARY 2015 www.ti.com Typical Characteristics (continued) TA = 25C, Unless Otherwise Noted Figure 31. +SR vs. Cap Load Figure 32. -SR vs. Cap Load 16 Figure 33. +SR vs. Cap Load Figure 34. -SR vs. Cap Load Figure 35. Settling Time vs. Error Voltage Figure 36. Settling Time vs. Error Voltage Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8261 LM8261 www.ti.com SNOS469J - APRIL 2000 - REVISED JANUARY 2015 Typical Characteristics (continued) TA = 25C, Unless Otherwise Noted Figure 37. Input Noise Voltage/Current vs. Frequency Figure 38. Input Noise Voltage for Various VCM Figure 39. Input Noise Current for Various VCM Figure 40. Input Noise Voltage vs. VCM Figure 41. Input Noise Current vs. VCM Figure 42. THD+N vs. Frequency Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8261 17 LM8261 SNOS469J - APRIL 2000 - REVISED JANUARY 2015 www.ti.com Typical Characteristics (continued) TA = 25C, Unless Otherwise Noted 18 Figure 43. THD+N vs. Frequency Figure 44. THD+N vs. Frequency Figure 45. THD+N vs. Amplitude Figure 46. THD+N vs. Amplitude Figure 47. Small Signal Step Response Figure 48. Large Signal Step Response Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8261 LM8261 www.ti.com SNOS469J - APRIL 2000 - REVISED JANUARY 2015 7 Application and Implementation 7.1 Block Diagram and Operational Description 7.1.1 A) Input Stage Figure 49. Simplified Schematic Diagram As seen in Figure 49, the input stage consists of two distinct differential pairs (Q1-Q2 and Q3-Q4) in order to accommodate the full Rail-to-Rail input common mode voltage range. The voltage drop across R5, R6, R7, and R8 is kept to less than 200 mV in order to allow the input to exceed the supply rails. Q13 acts as a switch to steer current away from Q3-Q4 and into Q1-Q2, as the input increases beyond 1.4 V of V+. This in turn shifts the signal path from the bottom stage differential pair to the top one and causes a subsequent increase in the supply current. In transitioning from one stage to another, certain input stage parameters (VOS, Ib, IOS, en, and in) are determined based on which differential pair is "on" at the time. Input Bias current, IB, will change in value and polarity as the input crosses the transition region. In addition, parameters such as PSRR and CMRR which involve the input offset voltage will also be effected by changes in VCM across the differential pair transition region. The input stage is protected with the combination of R9-R10 and D1, D2, D3, and D4 against differential input over-voltages. This fault condition could otherwise harm the differential pairs or cause offset voltage shift in case of prolonged over voltage. As shown in Figure 50, if this voltage reaches approximately 1.4 V at 25C, the diodes turn on and current flow is limited by the internal series resistors (R9 and R10). The Absolute Maximum Rating of 10 V differential on VIN still needs to be observed. With temperature variation, the point were the diodes turn on will change at the rate of 5 mV/C. Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8261 19 LM8261 SNOS469J - APRIL 2000 - REVISED JANUARY 2015 www.ti.com Block Diagram and Operational Description (continued) Figure 50. Input Stage Current vs. Differential Input Voltage 7.1.2 B) Output Stage The output stage Figure 49 is comprised of complementary NPN and PNP common-emitter stages to permit voltage swing to within a VCE(SAT) of either supply rail. Q9 supplies the sourcing and Q10 supplies the sinking current load. Output current limiting is achieved by limiting the VCE of Q9 and Q10; using this approach to current limiting, alleviates the draw back to the conventional scheme which requires one VBE reduction in output swing. The frequency compensation circuit includes Miller capacitors from collector to base of each output transistor (see Figure 49, Ccomp9 and Ccomp10). At light capacitive loads, the high frequency gain of the output transistors is high, and the Miller effect increases the effective value of the capacitors thereby stabilizing the Op Amp. Large capacitive loads greatly decrease the high frequency gain of the output transistors thus lowering the effective internal Miller capacitance - the internal pole frequency increases at the same time a low frequency pole is created at the Op Amp output due to the large load capacitor. In this fashion, the internal dominant pole compensation, which works by reducing the loop gain to less than 0dB when the phase shift around the feedback loop is more than 180C, varies with the amount of capacitive load and becomes less dominant when the load capacitor has increased enough. Hence the Op Amp is very stable even at high values of load capacitance resulting in the uncharacteristic feature of stability under all capacitive loads. 7.2 Driving Capacitive Loads The LM8261 is specifically designed to drive unlimited capacitive loads without oscillations (See Figure 30). In addition, the output current handling capability of the device allows for good slewing characteristics even with large capacitive loads (see Slew Rate vs. Cap Load plots, Figure 31 through Figure 34). The combination of these features is ideal for applications such as TFT flat panel buffers, A/D converter input amplifiers, and so forth. However, as in most Op Amps, addition of a series isolation resistor between the Op Amp and the capacitive load improves the settling and overshoot performance. Output current drive is an important parameter when driving capacitive loads. This parameter will determine how fast the output voltage can change. Referring to the Slew Rate vs. Cap Load Plots (Figure 31 through Figure 34), two distinct regions can be identified. Below about 10,000pF, the output Slew Rate is solely determined by the Op Amp's compensation capacitor value and available current into that capacitor. Beyond 10nF, the Slew Rate is determined by the Op Amp's available output current. Note that because of the lower output sourcing current compared to the sinking one, the Slew Rate limit under heavy capacitive loading is determined by the positive transitions. An estimate of positive and negative slew rates for loads larger than 100nF can be made by dividing the short circuit current value by the capacitor. 20 Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8261 LM8261 www.ti.com SNOS469J - APRIL 2000 - REVISED JANUARY 2015 Driving Capacitive Loads (continued) For the LM8261, the available output current increases with the input overdrive. As seen in Figure 51 and Figure 52, both sourcing and sinking short circuit current increase as input overdrive increases. In a closed loop amplifier configuration, during transient conditions while the fed back output has not quite caught up with the input, there will be an overdrive imposed on the input allowing more output current than would normally be available under steady state condition. Because of this feature, the Op Amp's output stage quiescent current can be kept to a minimum, thereby reducing power consumption, while enabling the device to deliver large output current when the need arises (such as during transients). Figure 51. Output Short Circuit Sourcing Current vs. Input Overdrive Figure 52. Output Short Circuit Sinking Current vs. Input Overdrive Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8261 21 LM8261 SNOS469J - APRIL 2000 - REVISED JANUARY 2015 www.ti.com Driving Capacitive Loads (continued) Figure 53 shows the output voltage, output current, and the resulting input overdrive with the device set for AV = +1 and the input tied to a 1VPP step function driving a 47nF capacitor. During the output transition, the input overdrive reaches 1 V peak and is more than enough to cause the output current to increase to its maximum value (see Figure 51 and Figure 52). Because the larger output sinking current is compared to the sourcing one, the output negative transition is faster than the positive one. Figure 53. Buffer Amplifier Scope Photo 7.3 Estimating the Output Voltage Swing It is important to keep in mind that the steady state output current will be less than the current available when there is an input overdrive present. For steady state conditions, Figure 24 through Figure 26 in Typical Characteristics can be used to predict the output swing. Figure 54 and Figure 55 show this performance along with several load lines corresponding to loads tied between the output and ground. In each cases, the intersection of the device plot at the appropriate temperature with the load line would be the typical output swing possible for that load. For example, a 1-K load can accommodate an output swing to within 250 mV of V- and to 330 mV of V+ (VS = 15 V) corresponding to a typical 29.3 VPP unclipped swing. Figure 54. Output Sourcing Characteristics with Load Lines Figure 55. Output Sinking Characteristics with Load Lines 22 Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8261 LM8261 www.ti.com SNOS469J - APRIL 2000 - REVISED JANUARY 2015 7.4 TFT Applications Figure 56 below, shows a typical application where the LM8261 is used as a buffer amplifier for the VCOM signal employed in a TFT LCD flat panel: Figure 56. VCOM Driver Application Schematic Figure 57 shows the time domain response of the amplifier when used as a VCOM buffer/driver with VREF at ground. In this application, the Op Amp loop will try and maintain its output voltage based on the voltage on its non-inverting input (VREF) despite the current injected into the TFT simulated load. As long as this load current is within the range tolerable by the LM8261 (45 mA sourcing and 65 mA sinking for 5 V supplies), the output will settle to its final value within less than 2 s. Figure 57. VCOM Driver Performance Scope Photo 7.5 Output Short Circuit Current and Dissipation Issues The LM8261 output stage is designed for maximum output current capability. Even though momentary output shorts to ground and either supply can be tolerated at all operating voltages, longer lasting short conditions can cause the junction temperature to rise beyond the absolute maximum rating of the device, especially at higher supply voltage conditions. Below supply voltage of 6 V, output short circuit condition can be tolerated indefinitely. With the Op Amp tied to a load, the device power dissipation consists of the quiescent power due to the supply current flow into the device, in addition to power dissipation due to the load current. The load portion of the power itself could include an average value (due to a DC load current) and an AC component. DC load current would flow if there is an output voltage offset, or the output AC average current is non-zero, or if the Op Amp operates in a single supply application where the output is maintained somewhere in the range of linear operation. Therefore: PTOTAL = PQ + PDC + PAC (1) Op Amp Quiescent Power Dissipation: PQ = IS * VS (2) DC Load Power: PDC = IO * (VR - VO) (3) AC Load Power: PAC = (outlined in table below) Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8261 23 LM8261 SNOS469J - APRIL 2000 - REVISED JANUARY 2015 www.ti.com Output Short Circuit Current and Dissipation Issues (continued) where * * * * * IS is Supply Current VS is Total Supply Voltage (V+ - V-) IO is Average Load Current VO is Average Output Voltage VR is V+ for sourcing and V- for sinking current (4) Table 1 shows the maximum AC component of the load power dissipated by the Op Amp for standard Sinusoidal, Triangular, and Square Waveforms: Table 1. Normalized AC Power Dissipated in the Output Stage for Standard Waveforms PAC (W./V2) Sinusoidal Triangular Square 50.7 x 10-3 46.9 x 10-3 62.5 x 10-3 The table entries are normalized to VS2/ RL. To calculate the AC load current component of power dissipation, simply multiply the table entry corresponding to the output waveform by the factor VS2/ RL. For example, with 15 V supplies, a 600- load, and triangular waveform power dissipation in the output stage is calculated as: PAC= (46.9 x 10-3) * [302/600]= 70.4 mW (5) 7.6 Other Application Hints The use of supply decoupling is mandatory in most applications. As with most relatively high speed/high output current Op Amps, best results are achieved when each supply line is decoupled with two capacitors; a small value ceramic capacitor (0.01 F) placed very close to the supply lead in addition to a large value Tantalum or Aluminum (> 4.7 F). The large capacitor can be shared by more than one device if necessary. The small ceramic capacitor maintains low supply impedance at high frequencies while the large capacitor will act as the charge "bucket" for fast load current spikes at the Op Amp output. The combination of these capacitors will provide supply decoupling and will help keep the Op Amp oscillation free under any load. 7.6.1 LM8261 Advantages Compared to other Rail-to-Rail Input/Output devices, the LM8261 offers several advantages such as: * Improved cross over distortion. * Nearly constant supply current throughout the output voltage swing range and close to either rail. * Consistent stability performance for all input/output voltage and current conditions. * Nearly constant Unity gain frequency (fu) and Phase Margin (Phim) for all operating supplies and load conditions. * No output phase reversal under input overload condition. 24 Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8261 LM8261 www.ti.com SNOS469J - APRIL 2000 - REVISED JANUARY 2015 8 Power Supply Recommendations The LM8261 can operate off a single supply or with dual supplies. The input CM capability of the parts (CMVR) extends covers the entire supply voltage range for maximum flexibility. Supplies should be decoupled with low inductance, often ceramic, capacitors to ground less than 0.5 inches from the device pins. The use of ground plane is recommended, and as in most high speed devices, it is advisable to remove ground plane close to device sensitive pins such as the inputs. 9 Layout 9.1 Layout Guidelines Generally, a good high frequency layout will keep power supply and ground traces away from the inverting input and output pins. Parasitic capacitances on these nodes to ground will cause frequency response peaking and possible circuit oscillations. Texas Instruments suggests the following evaluation boards as a guide for high frequency layout and as an aid in device testing and characterization. See Table 2 for details. The LM8261 evaluation board(s) is a good example of high frequency layout techniques as a reference. General high-speed, signal-path layout suggestions include: * Continuous ground planes are preferred for signal routing with matched impedance traces for longer runs. However, open up both ground and power planes around the capacitive sensitive input and output device pins as shown in Figure 58. After the signal is sent into a resistor, parasitic capacitance becomes more of a bandlimiting issue and less of a stability issue. * Use good, high-frequency decoupling capacitors (0.1 F) on the ground plane at the device power pins as shown in Figure 58. Higher value capacitors (2.2 F) are required, but may be placed further from the device power pins and shared among devices. For best high-frequency decoupling, consider X2Y supply-decoupling capacitors that offer a much higher self-resonance frequency over standard capacitors. * When using differential signal routing over any appreciable distance, use microstrip layout techniques with matched impedance traces. * The input summing junction is very sensitive to parasitic capacitance. Connect any Rf, and Rg elements into the summing junction with minimal trace length to the device pin side of the resistor, as shown in Figure 59. The other side of these elements can have more trace length if needed to the source or to ground. Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8261 25 LM8261 SNOS469J - APRIL 2000 - REVISED JANUARY 2015 www.ti.com 9.2 Layout Example Figure 58. LM8261 Evaluation Board Layer 1 Figure 59. LM8261 Evaluation Board Layer 2 Table 2. Evaluation Board Comparison 26 DEVICE PACKAGE EVALUATION BOARD PART NUMBER LM8261M5 SOT-23 LMH730216 Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8261 LM8261 www.ti.com SNOS469J - APRIL 2000 - REVISED JANUARY 2015 10 Device and Documentation Support 10.1 Documentation Support 10.1.1 Related Documentation For related documentation, see IC Package Thermal Metrics Application Report, SPRA953 10.2 Trademarks All trademarks are the property of their respective owners. 10.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 10.4 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 11 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8261 27 PACKAGE OPTION ADDENDUM www.ti.com 4-Aug-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LM8261M5 NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 85 A45A LM8261M5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A45A LM8261M5X NRND SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 85 A45A LM8261M5X/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A45A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 4-Aug-2015 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) LM8261M5 SOT-23 DBV 5 1000 178.0 8.4 LM8261M5/NOPB SOT-23 DBV 5 1000 178.0 LM8261M5X SOT-23 DBV 5 3000 178.0 LM8261M5X/NOPB SOT-23 DBV 5 3000 178.0 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM8261M5 SOT-23 DBV 5 1000 210.0 185.0 35.0 LM8261M5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LM8261M5X SOT-23 DBV 5 3000 210.0 185.0 35.0 LM8261M5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 1.75 1.45 PIN 1 INDEX AREA 1 0.1 C B A 5 2X 0.95 1.9 1.45 MAX 3.05 2.75 1.9 2 4 0.5 5X 0.3 0.2 3 (1.1) C A B 0.15 TYP 0.00 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. www.ti.com EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214839/C 04/2017 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X(0.95) 4 3 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. www.ti.com PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 1.75 1.45 PIN 1 INDEX AREA 1 0.1 C B A 5 2X 0.95 1.9 1.45 MAX 3.05 2.75 1.9 2 4 0.5 5X 0.3 0.2 3 (1.1) C A B 0.15 TYP 0.00 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. www.ti.com EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214839/C 04/2017 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X(0.95) 4 3 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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