NT5DS16M16BG-6K - Nanya Technology

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.4

05/2003 1

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Features

• Double data rate architecture: two data transfers per

clock cycle

• Bidirectional data strobe (DQS) is transmitted and

received with data, to be used in capturing data at the

receiver

• DQS is edge-aligned with data for reads and is center-

aligned with data for writes

• Differential clock inputs (CK and CK)

• Four internal banks for concurrent operation

• Data mask (DM) for write data

• DLL aligns DQ and DQS transitions with CK transitions

• Comm and s ente red on ea ch pos it ive CK e dge ; d ata and

data mask referenced to both edges of DQS

• Burst lengths: 2, 4, or 8

• CAS Latency: 2.5

• Auto Precha rge option for each burst access

• Auto Refresh and Self Refresh Modes

•7.8µs Maximum Average Periodic Refresh Interval

• 2.5V (SSTL_2 compatible) I/O

•V

DDQ = 2.5V ± 0.2V

•V

DD = 2.5V ± 0.2V

• -6K Speed sort: Supports PC2700/PC2100 modules

• -75B Speed sort: Supports PC2100 modules

• Lead-free and Halogen-free product available

Description

The 256Mb DDR SDRAM is a high-speed CMOS, dynamic

random-access memory containing 268,435,456 bits. It is

internally configured as a quad-bank DRAM.

The 256Mb DDR SDRAM uses a double-data-rate architec-

ture to achieve high-speed operation. The double data rate

architecture is essentially a 2n prefetch architecture with an

interface designed to transfer two data words per clock cycle

at the I/O pins. A single read or write access for the 256Mb

DDR SDRAM effectively consists of a single 2n-bit wide, one

clock cycle data transfer at the internal DRAM core and two

corresponding n-bit wide, one-half-clock-cycle data transfers

at the I/O pins.

A bidirectional data strobe (DQS) is transmitted externally,

along with data, for use in data capture at the receiver. DQS

is a strobe transmitted by the DDR SDRAM during Reads

and by the memo ry con trol ler duri ng Write s. DQS is edge-

aligned with data for Reads and center-aligned with data for

Writes.

The 256Mb DDR SDRAM operates from a differential clock

(CK and CK; the crossing of CK going high and CK going

LOW is referred to as the positive edge of CK). Commands

(address and control signals) are registered at every positive

edge of CK. Input data is registered on both edges of DQS,

and output data is referenced to both edges of DQS, as well

as to both edges of CK.

Read and write accesses to the DDR SDRAM are burst ori-

ented; accesses start at a selected location and conti nue for

a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an Active

command, which is then followed by a Read or Write com-

mand. The address bits registered coincident with the Active

command are used to select the bank and row to be

acce ssed. The address b its regis tere d coincident with the

Read or Write command are used to select the bank and the

starting column location for the burst access.

The DDR SDRAM provides for programmable Read or Write

burst lengths of 2, 4, or 8 locations. An Auto Precharge func-

tion may be enabled to provide a self-timed row precharge

that is initiated at the end of the burst access.

As with standard SDRAMs, the pipelined, multibank architec-

ture of DDR SDRAMs allows for concurrent operation,

thereby providing high effective bandwidth by hiding row pre-

charge and activation time.

An auto refresh mode is provided along with a power-saving

Power Down mode. Al l inputs are comp atible with the JED EC

Standard for SSTL_2. All outputs are SSTL_2, Class II com-

patible.

The functi onality described an d the timing specifica tions

included i n this da ta shee t are for the DLL Enab led mode

of operation.

CAS Latency and Frequency

CAS

Latency

Maximum Oper ating Frequency

(MHz)*

DDR333

(-6K)*DDR266B

(-75B)

2.5 166 133

* -6K also meets DDR266A Spec

(MHz-CL-tRCD-tRP = 133-2-3-3)

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.4

05/2003 2

NANYA TECHNOL OGY CORP. reserve s the right to change Products and Specifications without notice.

Pin Configuration - 400mil TSOP II (x4 / x8 / x16)

27 41

VDD

DQ0

VDDQ

DQ1

VSSQ

VDDQ

DQ3

VSSQ

DQ2

VDDQ

VDD

CAS

RAS

BA0

BA1

VSS

DQ7

VSSQ

DQ6

VDDQ

VSSQ

DQ4

VDDQ

DQ5

VSSQ

DQS

VREF

VSS

DM*

CKE

A12

A11

VDD

VDDQ

DQ0

VSSQ

VDDQ

DQ1

VSSQ

VDDQ

VDD

CAS

RAS

BA0

BA1

VSS

VSSQ

DQ3

VDDQ

VSSQ

DQ2

VDDQ

VSSQ

DQS

VREF

VSS

DM*

CKE

A12

A11

A10/AP

VDD

A10/AP

VDD

VSS

Column Address Table

Organization Column Address

64Mb x 4 A0-A9, A11

32Mb x 8 A0-A9

16Mb x 16 A0-A8

*DM is internally loaded to match DQ and DQS identically.

64Mb x 4

32Mb x 8

66-pin Plastic TSOP-II 400mil

16Mb x 16

VDD

DQ0

VDDQ

DQ1

DQ2

VSSQ

VDDQ

DQ5

DQ6

VSSQ

DQ7

DQ3

DQ4

VDDQ

LDQS

VDD

LDM*

CAS

RAS

BA0

BA1

A10/AP

VDD

VSS

DQ15

VSSQ

DQ14

DQ13

VDDQ

VSSQ

DQ10

DQ9

VDDQ

DQ8

DQ12

DQ11

VSSQ

UDQS

VREF

VSS

UDM*

CKE

A12

A11

VSS

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.4

05/2003 3

NANYA TECHNOL OGY CORP. reserve s the right to change Products and Specifications without notice.

Pin Configuration - 60 balls 0.8mmx1.0mm Pitch CS P Pack age

See the balls through the pac ka ge.

64 X 4

32 X 8

VSSQ

VREF

VDDQ

VSSQ

VDDQ

VSSQ

VSS

CLK

A12

A11

VSS

DQ3

DQ2

DQS

DQM

CLK

CKE

VSS

VDD

DQ0

DQ1

QFC

RAS

BA1

VDD

VSSQ

VDDQ

VSSQ

VDDQ

VDD

CAS

BA0

A10/AP

VDDQ

VSSQ

VREF

DQ7

VDDQ

VSSQ

VDDQ

VSSQ

VSS

CLK

A12

A11

VSS

DQ6

DQ5

DQ4

DQS

DQM

CLK

CKE

VSS

VDD

DQ1

DQ2

DQ3

QFC

RAS

BA1

VDD

DQ0

VSSQ

VDDQ

VSSQ

VDDQ

VDD

CAS

BA0

A10/AP

VDDQ

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.4

05/2003 4

NANYA TECHNOL OGY CORP. reserve s the right to change Products and Specifications without notice.

Pin Configuration - 60 balls 0.8mmx1.0mm Pitch CS P Pack age

See the balls through the pac ka ge.

16 X 16

VSSQ

DQ14

DQ12

DQ10

DQ8

VREF

DQ15

VDDQ

VSSQ

VDDQ

VSSQ

VSS

CLK

A12

A11

VSS

DQ13

DQ11

DQ9

DQS

DQM

CLK

CKE

VSS

VDD

DQ2

DQ4

DQ6

LDQS

LDW

RAS

BA1

VDD

DQ0

VSSQ

VDDQ

VSSQ

VDDQ

VDD

CAS

BA0

A10/AP

VDDQ

DQ1

DQ3

DQ5

DQ7

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.4

05/2003 5

NANYA TECHNOL OGY CORP. reserve s the right to change Products and Specifications without notice.

Input/Output Functional Description

Symbol Type Function

CK, CK Input Clock: CK and CK are differential clock inputs. All address and control input signals are sampled

on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is refer-

enced to the crossings of CK and CK (both directions of crossing).

CKE, CKE0, CKE1 Input

Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device

input buffers and output drivers. Taking CKE Low provides Precharge Power Down and Self

Refresh operation (all banks idle), or Active Power Down (row Active in any bank). CKE is syn-

chronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self

refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers,

excluding CK, CK and CKE are disabled during Power Down. Input buffers, excluding CKE, are

disabled during self refresh. The standard pinout includes one CKE pin. Optional pinouts might

include CKE1 on a different pin, in addition to CKE0, to facilitate independent power down control

of stacked devices.

CS, CS0, CS1Input

Chip Select: All commands are masked when CS is registered high. CS provides for external

bank selection on systems with multiple banks. CS is considered part of the command code. The

standard pinout includes one CS pin. Optional pinouts might include CS1 on a different pin, in

addition to CS0, to allow upper or lower deck selection on stacked devices.

RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.

DM Input

Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is

sampled high coincident with that input data during a Wri te access. DM is sampled on both edges

of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. Dur-

ing a Read, DM can be driven high, low, or floated.

BA0, BA1 Input Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge

command is being applied. BA0 and BA1 also determines if the mode register or extended mode

A0 - A12 Input

Address Inputs: Provide the row address for Active commands, and the column address and

Auto Precharge bit for Read/Write commands, to select one location out of the memory array in

the respective bank. A10 is sampled during a Precharge command to determine whether the Pre-

charge applies to one bank (A10 low) or all banks (A10 high). If only one bank is to be precharged,

the bank is selected by BA0, BA1. The address inputs also provide the op-code during a Mode

DQ Input/Output Data Input/Output: Data bus.

DQS, LDQS, UDQS Input/Output Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered

in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0-

DQ7; UDQS corresponds to the data on DQ8-DQ15

NC No Connect: No internal electrical connection is present.

NU Electrical connection is present. Should not be connected at second level of assembly.

VDDQ Supply DQ Power Supply: 2.5V ± 0.2V.

VSSQ Supply DQ Ground

VDD Supply Power Supply: 2.5V ± 0.2V.

VSS Supply Ground

VREF Supply SSTL_2 reference voltage: (VDDQ / 2) ± 1%.

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.4

05/2003 6

NANYA TECHNOL OGY CORP. reserve s the right to change Products and Specifications without notice.

Ordering Information

Org. Part Number Package Speed Comments

Clock (MHz) CL-tRCD-tRP Clock (MHz) CL-tRCD-tRP

64M x 4

NT5DS64M4BT-6K 66 pin TSOP-II 166 2.5-3-3 133 2-3-3 DDR333/DDR266A

NT5DS64M4BT-75B 133 2.5-3-3 100 2-2-2 DDR266B

NT5DS64M4BF-6K 60ball BGA

0.8mmx1.0mm

Pitch

166 2.5-3-3 133 2-3-3 DDR333/DDR266A

NT5DS64M4BF-75B 133 2.5-3-3 100 2-2-2 DDR266B

32M x 8

NT5DS32M8BT-6K 66 pin TSOP-II 166 2.5-3-3 133 2-3-3 DDR333/DDR266A

NT5DS32M8BT-75B 133 2.5-3-3 100 2-2-2 DDR266B

NT5DS32M8BF-6K 60ball BGA

0.8mmx1.0mm

Pitch

166 2.5-3-3 133 2-3-3 DDR333/DDR266A

NT5DS32M8BF-75B 133 2.5-3-3 100 2-2-2 DDR266B

16M x 16

NT5DS16M16BT-6K 66 pin TSOP-II 166 2.5-3-3 133 2-3-3 DDR333/DDR266A

NT5DS16M16BT-75B 133 2.5-3-3 100 2-2-2 DDR266B

NT5DS16M16BF-6K 60ball BGA

0.8mmx1.0mm

Pitch

166 2.5-3-3 133 2-3-3 DDR333/DDR266A

NT5DS16M16BF-75B 133 2.5-3-3 100 2-2-2 DDR266B

64M x 4

NT5DS64M4BS-6K166 pin TSOP-II 166 2.5-3-3 133 2-3-3 DDR333/DDR266A

NT5DS64M4BS-75B1133 2.5-3-3 100 2-2-2 DDR266B

NT5DS64M4BG-6K160ball BGA

0.8mmx1.0mm

Pitch

166 2.5-3-3 133 2-3-3 DDR333/DDR266A

NT5DS64M4BG-75B1133 2.5-3-3 100 2-2-2 DDR266B

32M x 8

NT5DS32M8BS-6K166 pin TSOP-II 166 2.5-3-3 133 2-3-3 DDR333/DDR266A

NT5DS32M8BS-75B1133 2.5-3-3 100 2-2-2 DDR266B

NT5DS32M8BG-6K160ball BGA

0.8mmx1.0mm

Pitch

166 2.5-3-3 133 2-3-3 DDR333/DDR266A

NT5DS32M8BG-75B1133 2.5-3-3 100 2-2-2 DDR266B

16M x 16

NT5DS16M16BS-6K166 pin TSOP-II 166 2.5-3-3 133 2-3-3 DDR333/DDR266A

NT5DS16M16BS-75B1133 2.5-3-3 100 2-2-2 DDR266B

NT5DS16M16BG-6K160ball BGA

0.8mmx1.0mm

Pitch

166 2.5-3-3 133 2-3-3 DDR333/DDR266A

NT5DS16M16BG-75B1133 2.5-3-3 100 2-2-2 DDR266B

Note:

1. Lead-free and Halogen-free product

2. At the present time, there are no plans to support DDR SDRAMs with the QFC function. All r e ference to QFC are for information only

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.4

05/2003 7

NANYA TECHNOL OGY CORP. reserve s the right to change Products and Specifications without notice.

Block Diagram (64Mb x 4)

Receivers

DQS

CK, CK

DLL

RAS

CAS

Control Logic

Column-Address

Counter/Latch

Mode

Command

Decode

A0-A12,

BA0, BA1

CKE

I/O Gating

DM Mask Logic

Bank0

Memory

Array

(8192 x 1024 x 8)

Sense Amplifiers

Bank1 Bank2 Bank3

Refresh Counter

Input

Register1

clk

out

Data

Mask

Data

CK,

COL0

clk

MUX

DQS

Generator

DQ0-DQ3,

DQS

Read Latch

Write

FIFO

Drivers

Note: This Functional Block Diagram is intended to facilitate user understanding of t he operation of

the device; it does not represent an actual circuit implementation.

Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-

rectional DQ and DQS signals.

Column

Decoder

1024

(x8)

Row-Address MUX

Registers

8192

Bank0

Row-Address Latch

& Decoder

8192

Address Register

Drivers

Bank Control Logic

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.4

05/2003 8

NANYA TECHNOL OGY CORP. reserve s the right to change Products and Specifications without notice.

Block Diagram (32Mb x 8)

Receivers

DQS

CK, CK

DLL

RAS

CAS

Control Logic

Column-Address

Counter/Latch

Mode

Command

Decode

A0-A12,

BA0, BA1

CKE

I/O Gating

DM Mask Logic

Bank0

Memory

Array

(8192 x 512 x 16)

Sense Amplifiers

Bank1 Bank2 Bank3

Refresh Counter

Input

Register1

clk

out

Data

Mask

Data

CK,

COL0

clk

MUX

DQS

Generator

DQ0-DQ7,

DQS

Read Latch

Write

FIFO

Drivers

Note: This Functional Block Diagram is intended to facilitate user understanding of the operati on of

the device; it does not represent an actual circuit implementation.

Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-

rectional DQ and DQS signals.

Column

Decoder

512

(x16)

Row-Address MUX

Registers

8192

Bank0

Row-Address Latch

& Decoder

8192

Address Register

Drivers

Bank Control Logic

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.4

05/2003 9

NANYA TECHNOL OGY CORP. reserve s the right to change Products and Specifications without notice.

Block Diagram (16Mb x 16)

Receivers

DQS

CK, CK

DLL

RAS

CAS

Control Logic

Column-Address

Counter/Latch

Mode

Command

Decode

A0-A12,

BA0, BA1

CKE

I/O Gating

DM Mask Logic

Bank0

Memory

Array

(8192 x 256 x 32)

Sense Amplifiers

Bank1 Bank2 Bank3

Refresh Counter

16 16

Input

Register1

clk

out

Data

Mask

Data

CK,

COL0

clk

MUX

DQS

Generator

16 16

DQ0-DQ15,

LDM, UDM

LDQS,UDQS

Read Latch

Write

FIFO

Drivers

Note: This Functional Block Diagram is intended to facilitate user understanding of the operati on of

the device; it does not represent an actual circuit implementation.

Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-

rectional DQ and DQS signals.

Column

Decoder

256

(x32)

Row-Address MUX

Registers

8192

Bank0

Row-Address Latch

& Decoder

8192

Address Register

Drivers

Bank Control Logic

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.4

05/2003 10

NANYA TECHNOL OGY CORP. reserve s the right to change Products and Specifications without notice.

Functional Description

The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268, 435, 456 bits. The 256Mb

DDR SDRAM is internally configured as a quad-bank DRAM.

The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high -speed operati on. The double-da ta-rate a rchitec-

ture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O

pins. A single read or write access for the 256Mb DDR SDRAM consists of a single 2n-bit w ide , on e c lo ck c yc le data tra ns fer a t

the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins.

Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a pro-

gramme d number of lo cations i n a programm ed sequen ce. Accesses begin wi th the regist ration of an Ac tive comman d, which is

then follo wed by a Read or Write co mman d. The addre ss bits registe red coin ciden t with the Active co mmand ar e used to select

the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The address bits registered coincident

with the Read or Write command are used to select the starting column location for the burst access.

Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed information covering

device initialization, register definition, command descriptions and device operation.

Initialization

Only one of the following two conditions must be met.

• No power sequencing is specified during power up or power down given the following criteria:

VDD and VDDQ are driven from a single power converter output

VTT meets the specification

A minimum resistance of 42 ohms limits the input current from the VTT supply into any pin and

VREF tracks VDDQ /2

• The following relationships must be followed:

VDDQ is driven after or with VDD such that VDDQ < VDD + 0.3V

VTT is driven after or with VDDQ such that VTT < VDDQ + 0.3V

VREF is driven after or with VDDQ such that VREF < VDDQ + 0.3V

The DQ and DQS outputs are in the High-Z state, where they remain until driven in normal operation (by a read access). After

all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200µs delay prior to

applying an execut able command.

Once the 200µs delay has been satisfied, a Deselect or NOP command should be applied, and CKE must be brought HIGH.

Following the NOP command, a Precharge ALL command must be applied. Next a Mode Register Set command must be

issued for the Extended Mode Register, to enable the DLL, then a Mode Register Set command must be issued for the Mode

Regis ter, to res et the DLL, and to prog ram the op era ting parameters. 200 clock cy cl es are re quired betwee n the DL L res et a nd

any read command. A Precharge ALL command should be applied, placing the device in the “all banks idle” state

Once in the idle state, two auto refresh cycles must be performed. Additionally, a Mode Register Set command for the Mode

Regis ter, with the re set DLL bit deacti vated (i.e. to program o perating p arameters wi thout rese tting the DLL ) must b e performed .

Following these cycles, the DDR SDRAM is ready for normal operation.

DDR SDRAM’s may be reinitialized at any time during normal operation by asse rting a valid MRS command to either the base

or extended mode registers without affecting the contents of the memory array. The contents of either the mode register or

extended mode register can be modified at any valid time during device operation without affecting the state of the internal

address refresh counters used for device refresh.

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.4

05/2003 11

NANYA TECHNOL OGY CORP. reserve s the right to change Products and Specifications without notice.

Mode Register

The Mode Register is used to define th e specific mode of o peration of the DDR SDRAM. T his definition includes the selection of

a burst length, a burst type, a CAS latency, and an operating mode. The Mode Register is programmed via the Mode Register

Set command (with BA0 = 0 and BA1 = 0) and retains the stored information until it is programmed again or the device loses

power (except for bit A8, which is self-clearing).

Mode Register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the

CAS latency, and A7-A12 specify the operating mode.

The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the

subsequent operation. Violating either of these requirements results in unspecified operation.

Burst Length

Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst length

deter mi nes the ma xi mu m number of co lum n lo ca tions that ca n be ac ce ss ed fo r a given Read or Write com ma nd. Burst lengths

of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types.

Reserved states should not be used, as unknown operation or incompatibility with future versions may result.

When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All accesses for

that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. The block is

uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is set to four and by A3-Ai when

the burst length is set to eight (where Ai is the most significant column address bit for a given configuration). The remaining

(least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length

applies to both Read and Write bursts.

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256Mb DDR SDRAM

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Mode Register Operation

A8 A7 A6 A5 A4

CAS Latency

A3 A2 A1 A0

Burst LengthBT

Address Bus

CAS Latency

A6 A5 A4 Latency

000 Reserved

001 Reserved

010 2

0 1 1 3 (Option)

100 Reserved

1 0 1 1.5 (Option)

110 2.5

111 Reserved

Burst Length

A2 A1 A0 Burst Length

000 Reserved

001 2

010 4

011 8

100 Reserved

101 Reserved

110 Reserved

111 Reserved

BA1 BA0 A11 A10 A9

0* 0* Mode Registe

Operating Mode

* BA0 and BA1 must be 0, 0 to select the Mode Register

(vs. the Extended Mode Register).

A12 - A9 A8 A7 A6 - A0 Opera ting Mode

0 0 0 Valid Normal operation

Do not reset DLL

0 1 0 Valid Normal operation

in DLL Reset

001VS** Vendor-Specific

Test Mode

−−− Reserved

A3 Burst

Type

0 Sequential

1 Interleave

VS** Vendor Specific

A12

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Notes:

1. For a burst length of two, A1-A i selects the two-data-element block; A0 selects the first access within the block.

2. For a burst length of four, A2-A i selects the four-data-element block; A0-A1 selects the first access within the block.

3. For a burst length of eight, A3-A i selects the eight-data- element block; A0-A2 selects the first access within the block.

4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.

Burst Type

Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type

and is se lected via bit A3. The ordering of acces ses wit hin a burs t is dete rmine d by the bu rst leng th, th e burst ty pe and th e start-

ing column address, as shown in Burst Definition on page 13.

Read Latency

The Rea d latency, or CAS latency, is the d elay, in c lock cycl es, betw een the regi stration o f a Read c ommand and the availa bility

of the first burst of output data. The latency can be programmed 2 or 2.5 clocks.

If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with

clock edge n + m.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

Burst Definition

Burst Length Starting Column Address Order of Accesses Within a Burst

A2 A1 A0 Ty pe = Sequential Type = Interleaved

20 0-1 0-1

11-0 1-0

0 0 0-1-2-3 0-1-2-3

0 1 1-2-3-0 1-0-3-2

1 0 2-3-0-1 2-3-0-1

1 1 3-0-1-2 3-2-1-0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6

0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4

1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3

1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2

1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1

1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

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Operating Mode

The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 to zero, and bits A0-A6 set

to the desired values. A DLL reset is initiated by issuing a Mode Register Set command with bits A7 and A9-A12 each set to

zero, bi t A8 s et to o ne , and bits A0 -A6 set to the de sired va lu es. A M od e Registe r Set co mm an d i ss ue d t o re se t th e D L L s ho uld

always be followed by a Mode Register Set command to select normal operating mode.

All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and reserved states

should not be used as unknown operation or incompatibility with future versions may result.

CAS Latencies

Shown with nominal tAC, tDQSCK, and tDQSQ.Don’t Care

NOP NOP NOP NOP NOPRead

CAS Latency = 2.5, BL = 4

Command

DQS

CL=2.5

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Extended Mode Register

The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions

include DLL enable/disable, bit A0; output drive strength selection, bit A1; and QFC output enable /di sa ble , bit A2 (NTC

optional). These functions are controlled via the bit settings shown in the Extended Mode Register Definition. The Extended

Mode Register is programmed via the Mode Register Set command (with BA0 = 1 and BA1 = 0) and retains the stored informa-

tion until it is programmed again or the device loses power. The Extended Mode Register must be loaded when all banks are

idle, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these require-

ments result in unspecified operation.

DLL Enable/Disable

The DL L m ust b e e nab led for normal op era tion . D L L en ab le i s requ ire d d urin g p ow er up i ni tial iz ati on, an d up on returning t o n or-

mal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically disabled when

entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled,

200 clock cycles must occur to allow time for the internal clock to lock to the externally applied clock before a Read command

can be issued. This is the reason for introducing timing parameter tXSRD for DDR SDRAM’s (Exit Self Refresh to Read Com-

mand). N on- Read com mands can be issued 2 c locks af ter the DLL is en abled via the EMRS comm and (tMRD) or 10 clock s after

the DLL is enabled via self refresh exit command (tXSNR, Exit Self Refresh to Non-Read Command).

Output Drive Strength

The normal drive strength for all outputs is specified to be SSTL_2, Class II.

QFC Enable/Disable

The QFC signal is an optional DRAM output control used to isolate module loads (DIMMs) from the system memory bus by

means o f extern al FE T switc hes when the giv en mod ule (D IMM) i s not being acce ssed. The QFC func tion is an opti onal fe ature

for NANYA and is not included on all DDR SDRAM devices.

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Extended Mode Register Definition

A8A7A6A5A4A3A2A1A0Address Bus

Drive Strength

A1Drive Strength

0Normal

1 Reserved

BA1 BA0

Operating Mode

A11 A10 A9

0*1*

* BA0 and BA1 must be 1, 0 to select the Extended Mode Register

Mode Register

Extended

DS DLL

A0DLL

0 Enable

1 Disable

A12 - A3 A2 - A0 Operating Mode

0 Valid Normal Operation

−−All other states

Reserved

(vs. the base Mode Register)

QFC

A2QFC

0 Disable

1Enable

(Optional)

A12

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Commands

Truth Tables 1a and 1b provide a refer ence of the commands supported by DDR SDRAM devices. A verbal description of each

commands follows.

Truth Table 1a: Commands

Name (Funct ion) CS RAS CAS WE Address MNE Notes

Deselect (Nop) H X X X X NOP 1, 9

No Operation (Nop) L H H H X NOP 1, 9

Active (Select Bank And Activate Row) L L H H Bank/Row ACT 1, 3

Read (Select Bank And Column, And Start Read Burst) L H L H Bank/Col Read 1, 4

Write (Select Bank And Column, And Start Write Burst) L H L L Bank/Col Write 1, 4

Burst Terminate L H H L X BST 1, 8

Precharge (Deactivate Row In Bank Or Banks) L L H L Code PRE 1, 5

Auto Refresh Or Self Refresh (Enter Self Refresh Mode) L L L H X AR / SR 1, 6, 7

Mode Register Set L L L L Op-Code MRS 1, 2

1. CKE is high for all commands shown except Self Refresh.

2. BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects

Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to be written to the selected Mode

3. BA0-BA1 provide bank address and A0-A12 provide row address.

4. BA0, BA1 provide bank address; A0-Ai provide column address (where i = 9 for x8 and 9, 11 for x4); A10 high enables the Auto Pre-

charge feature (non-persistent), A10 low disables the Auto Precharge feature.

5. A10 LOW: BA0, BA1 determine which bank is precharged.

A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care.”

6. This command is auto refresh if CKE is high; Self Refresh if CKE is low.

7. Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.

8. Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with Auto

Precharge enabled or for write bursts

9. Deselect and NOP are functionally interchangeable.

Truth Table 1b: DM Operation

Name (Function) DM DQs Notes

Write Enable L Valid 1

Write Inhibit H X 1

1. Used to mask write data; provided coincident with the corresponding data.

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Deselect

The Deselect function prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM is

effectively deselected. Operations already in progress are not affected.

No Operation (NOP)

The No Operation (NOP) command is used to perform a NOP to a DDR SDRAM. This prevents unwanted commands from

being registered during idle or wait states. Operations already in progress are not affected.

Mode Register Set

The mode registe rs a re loade d via in puts A0-A 12, BA0 and BA 1 while is suin g the Mod e Reg ister Set Comman d. See mo de reg-

ister de scription s in the R egister Definiti on secti on. The Mo de Regi ster Set co mmand c an only b e issued when all b anks are i dle

and no bursts are in progress. A subsequent executable command cannot be issued until tMRD is met.

Active

The Active command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0,

BA1 inputs s ele cts the ba nk , and the addre ss prov id ed on inpu ts A0-A1 2 se lec ts the row. Thi s row rem ain s ac tiv e (or op en) for

accesses until a Precharge (or Read or Write with Auto Precharge) is issued to that bank. A Precharge (or Read or Write with

Auto Precharge) command must be issued and completed before opening a different row in the same bank.

Read

The Read command is used to initiate a burst read access to an active (open) row. The value on the BA0, BA1 inputs selects

the bank , and th e addre ss provi ded on i nputs A0-Ai , Aj (wh ere [i = 9 , j = do n’t car e] for x8 ; wher e [i = 9, j = 11] f or x4) selects the

starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is

select ed, the row b eing a ccesse d is pr echarg ed at th e end of the Re ad burs t; if Au to Prech arge is not s elect ed, the row rema ins

open for subsequent acc esse s.

Write

The Write command is used to initiate a burst write access to an active (open) row. The value on the BA0, BA1 inputs selects

the bank , and th e addre ss provi ded on i nputs A0-Ai , Aj (wh ere [i = 9 , j = do n’t car e] for x8 ; wher e [i = 9, j = 11] f or x4) selects the

starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is

select ed, the ro w bei ng acc essed i s precharg ed at the end of the Wr ite burs t; if Auto Precharg e is not se le cted, th e row rema in s

open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DM input logic

level appearing coincident with the data. If a given DM signal is registered low, the corresponding data is written to memory; if

the DM signal is registered high, the corresponding data inputs are ignored, and a Write is not executed to that byte/column

location.

Precharge

The Precharge command is used to deactivate (close) the open row in a particular bank or the open row(s) in all banks. The

bank(s) will be available for a subsequent row access a specified time (tRP) after the Precharge command is issued. Input A10

determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs

BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle

state and must be activated prior to any Read or Write commands being issued to that bank. A precharge command is treated

as a NOP if there is no open row in that bank, or if the previously open row is already in the process of precharging.

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Auto Prechar ge

Auto Precharg e is a feature which perf orms the same individua l-bank precharg e func tion d escribed abov e, but with out req uiring

an expli ci t co mm and . Thi s is ac co mp lis he d by usi ng A1 0 to en able Auto Prec harg e in con jun cti on with a s pec ifi c R ea d or Wri te

command. A precharge of the bank/row that is addressed with the Read or Write command is automatically performed upon

comple tion of the Rea d or Write burst. Auto Precharge is non -persiste nt in that it is either enabl ed or disab led for each individual

Read or Wri te comman d. Auto Prec harge en sures th at the prec harge is init iated at the earli est val id stage withi n a burst. This is

determined as if an explicit Precharge command was issued at the earliest possible time without violating tRAS(min). The user

must not issue another command to the same bank until the precharge (tRP) is completed.

The NTC DDR SDRAM devices supports the optional tRAS lockout featu re. T his fea ture allows a Read command w ith Auto Pre-

charge to be issued to a bank that has been activated (opened) but has not yet satisfied the tRAS(min) specification. The tRAS

lockout feature essentially delays the onset of the auto precharge operation until two conditions occur. One, the entire burst

length of data has been successfully prefetched from the memory array; and two, tRAS(min) has been satisfied.

As a means to specify whethe r a DDR SDRAM device supports the tRAS lockout feature, a new parameter has been defined,

tRAP (RAS Command to Read Command with Auto Precharge or better stated Bank Activate to Read Command with Auto Pre-

charge). For devices that support the tRAS lockout feature, tRAP = tRCD(min). This allows any Read Command (with or without

Auto Precharge) to be issued to an open bank once tRCD(min) is satisfied.

Burst Terminate

The Burst Terminate command is used to truncate read bursts (with Auto Precharge disabled). The most re-cently registered

Read c omma nd p r io r to th e Burs t Te rmi nat e c omm an d is tru nc ated , as shown in th e O pera tio n s ection of th is dat a sh eet . Write

burst cycles are not to be terminated with the Burst Terminate command.

tRAP Definition

Command

DQ (BL=2)

tRAPmin

NOP ACT NOP RD A NOP NOP NOP NOP ACT NOP NOP

tRCDmin

tRASmin

DQ0 DQ1

The above timing diagrams show the effects of tRAP for devices that support tRAS lockout. In these cases, the Read

with Auto Precharge command (RDA) is issued with tRCD(m in) and dataout is available with the shortest latency from the

Bank Activate command (ACT). The internal precharge operat ion, however, does not begin until after tRAS(min) is satisfied.

CL=2, tCK=10ns

Command

DQ (BL=4)

NOP ACT NOP RD A NOP NOP NOP NOP ACT NOP NOP

DQ0 DQ1 DQ2 DQ3

Command

DQ (BL=8)

NOP ACT NOP RD A NOP NOP NOP NOP NOP ACT NOP

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

*Indicates Auto Precharge begins here

tRPmin

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Auto Refresh

Auto Refresh is used during normal operation of the DDR SDRAM and is analogous to CAS Before RAS (CBR) Refresh in pre-

vious DRAM types. This command is nonpersistent, so it must be issued each time a refresh is required.

The refresh addre ss in g is ge ne rated by the internal refres h co ntro ller. This make s the addre ss bits “Don’ t Ca re” dur ing an Auto

Refresh command. The 256Mb DDR SDRAM requires Auto Refresh cycles at an average periodic interval of 7.8µs (maximum ).

Self Refresh

The Self Refresh command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down.

When in the self refresh mode, the DDR SDRAM retains data without external clocking. The Self Refresh command is initiated

as an Auto Refresh command coincident with CKE transitioning low. The DLL is automatically disabled upon entering Self

Refres h, and is auto matical ly enable d upon ex iting Self Re fresh (200 c lock cyc les must the n occur be fore a Read c ommand ca n

be issued). Input signals except CKE (low) are “Don’t Care” during Self Refresh operation.

The procedure for exiting self refresh requires a sequence of commands. CK (and CK) must be stable prior to CKE returning

high. On ce CKE is high , the SDRAM mu st have NOP c ommands issued for tXSNR be cause tim e is require d for the comple tion of

any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for 200

clock cycles before applying any other command.

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Operations

Bank/Row Activation

Before any Read or Write commands can be issued to a bank within the DDR SDRAM, a row in that bank must be “opened”

(activa ted ). T his i s ac co mpl is hed v ia th e Acti ve c om ma nd and a ddre ss es A0 -A12, BA0 an d BA1 (se e Ac ti vat ing a Spe ci fic R o w

in a Specific Bank), which decode and select both the bank and the row to be activated. After opening a row (issuing an Active

command), a Read or Write command may be issued to that row, subject to the tRCD specification. A subsequent Active com-

mand to a di ffere nt ro w in the sam e ba nk c an o nly be is s ued after th e pre vio us act ive row has bee n “cl os ed” (p rec harg ed). The

minimum time interval between successive Active commands to the same bank is defined by tRC. A subsequent Active com-

mand to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access

overhead. The minimum time interval between successive Active commands to different banks is defined by tRRD.

Activating a Specific Row in a Specific Bank

HIGH

RA = row address.

BA = bank address.

CKE

RAS

CAS

A0-A12

BA0, BA1 Don’t Care

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Reads

Subsequent to programming the mode register with CAS latency, burst type, and burst length, Read bursts are initiated with a

Read command.

The starting column and bank addresses are provided with the Read command and Auto Precharge is either enabled or dis-

abled for that burst access. If Auto Precharge is enabled, the row that is accessed starts precharge at the completion of the

burst, provided tRAS has been satisfied. For the generic Read commands used in the following illustrations, Auto Precharge is

disabled.

During Read bur sts, th e vali d data-o ut elem ent fro m the st arting column a ddress is avai lable f ollow ing th e CAS laten cy aft er the

Read command. Each subsequent data-out element is valid nominally at the next positive or negative clock edge (i.e. at the

nex t crossing of CK and C K). The following timing figure entitled “Read Burst: CAS Latencies (Burst Length=4)” illustrates the

general timing for each supported CAS latency setting. DQS is driven by the DDR SDRAM along with output data. The initial low

state on DQS is known as the read preamble; the low state coincident with the last data-out element is known as the read post-

amble. Upon completion of a burst, assuming no other commands have been initiated, the DQs and DQS goes High-Z. Data

from any Read b urst m ay be c onca tenated with or trun cated wi th data from a subs equent Read comm and. I n eithe r cas e, a co n-

tinuous fl ow o f da ta c an be m ain tai ned . Th e first data element from the ne w bu rst follows ei the r th e l as t el em ent of a c ompl eted

burst or the last desired data element of a longer burst which is being truncated. The new Read command should be issued x

cycles after the first Read command, where x equals the number of desired data element pairs (pairs are required by the 2n

prefe tch arc hit ec ture ). Th is is sh ow n i n ti mi ng fig ure entitle d “Co nse cutive Re ad Burs ts: C AS Lat enc ie s (Bu r st Len gth =4 or 8 ) ” .

A Read c om m and ca n be ini tiated on a ny po sit iv e c loc k c y cle fol lowing a pre vi ous Rea d c om ma nd. N o nc ons ec uti ve Read data

is shown in t im ing fig ure e nti tled “Non-Consec uti ve Re ad Bu rst s: CAS Latencies (Burs t Le ngt h = 4)”. Full-spee d R an dom R ea d

Accesses: CAS Latencies (Burst Length = 2, 4 or 8) within a page (or pages) can be performed as shown on page 27.

tRCD and tRRD Definition

ROW

ACT NOP

COLROW

BA y BA yBA x

ACT NOP NOP

Command

A0-A12

BA0, BA1

Don’t Care

RD/WR

tRCD

tRRD

RD/WR NOP NOP

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Read Command

HIGH

CA = column address

BA = bank address

CKE

RAS

CAS

A10

BA0, BA1

Don’t Care

x4: A0-A9, A11

x8: A0-A9 EN AP

DIS AP

EN AP = enable Auto Precharge

DIS AP = disable Auto Precharge

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Read Burst: CAS Latencies (Burst Length = 4)

CAS Latency = 2

NOP NOP NOP NOP NOPRead

Command

Address

DQS

CAS Latency = 2.5

Don’t Care

BA a,COL n

DOa-n

CL=2.5

NOP NOP NOP NOP NOPRead

Command

Address

DQS

BA a,COL n

DOa-n

DO a-n = data out from bank a, column n.

3 subsequent elements of data out appear in the programmed order following DO a-n.

Shown with nominal tAC, tDQSCK, and tDQSQ.

CL=2

QFC

tQCS tQCH

(Optional)

tQCH

(Optional)

tQCS

QFC is an open drain driver. The output high level is achieved through an external pull up resistor connected to VDDQ.

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.4

05/2003 25

NANYA TECHNOL OGY CORP. reserve s the right to change Products and Specifications without notice.

Consecutive Read Bursts: CAS Latencies (B urst Length = 4 or 8)

CAS Latency = 2

NOP Read NOP NOP NOPRead

Command

Address

DQS

CL=2

BAa, COL n BAa, COL b

Don’t Care

DO a-n (or a-b) = data out from bank a, column n (or bank a, column b).

When burst length = 4, the bursts are concatenated.

When burst length = 8, the second burst interrupts the first.

3 subsequent elements of data out appear in the programmed order following DO a-n.

3 (or 7) subsequent elements of data out appear in the programmed order following DO a-b.

Shown with nominal tAC, tDQSCK, and tDQSQ.

CAS Latency = 2.5

NOP Read NOP NOP NOPRead

Command

Address

DQS

CL=2.5

BAa, COL n BAa,COL b

DOa-n

DOa- n DOa- b

DOa-b

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.4

05/2003 26

NANYA TECHNOL OGY CORP. reserve s the right to change Products and Specifications without notice.

Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4)

CAS Latency = 2

NOP NOP Read NOP NOPRead

Command

Address

DQS

DQ DO a-n DOa- b

DO a-n (or a-b) = data out from bank a, column n (or bank a, column b).

3 subsequent elements of data out appear in the programmed order following DO a-n (and following DO a-b).

Shown with nominal tAC, tDQSCK, and tDQSQ.Don’t Care

BAa, COL n BAa, COL b

CL=2

CAS Latency = 2.5

NOP NOP Read NOP NOPRead

DO a-n DOa- b

BAa, COL n BAa, COL b

CL=2.5

Command

Address

DQS

NOP

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.4

05/2003 27

NANYA TECHNOL OGY CORP. reserve s the right to change Products and Specifications without notice.

Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8)

DOa-n

CAS Latency = 2

Read Read Read NOP NOPRead

DOa-bDOa-n' DOa-x DOa-x' DOa-b’ DOa-g

Command

Address

DQS

DO a-n, etc. = data out from bank a, column n etc.

n' etc. = odd or even complement of n, etc. (i.e., column address LSB inverted).

Reads are to active rows in any banks.

Shown with nominal tAC, tDQSCK, and tDQSQ.

Don’t Care

BAa, COL n BAa, COL x BAa , COL b BAa, COL g

CL=2

DOa-n

CAS Latenc y = 2.5

Read Read Read NOP NOPRead

DOa-bDOa-n' DOa-x DOa-x' DOa-b’

Command

Address

DQS

BAa, COL n BAa, COL x BAa, COL b BAa, COL g

CL=2.5

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.4

05/2003 28

NANYA TECHNOL OGY CORP. reserve s the right to change Products and Specifications without notice.

Data from any Read burst may be truncated with a Burst Terminate command, as shown in timing figure entitled Terminating a

Read Bur st: CAS La ten ci es (Bur st Leng th = 8 ) on page 2 9. Th e Burs t Term in ate late nc y is eq ual to the read (CAS) late nc y, i .e.

the Burst Terminate command should be issued x cycles after the Read command, where x equals the number of desired data

element pairs.

Data from any Read burst must be completed or truncated before a subsequent Write command can be issued. If truncation is

necess ary, the Burst Term inate comm and must be us ed, as shown in tim ing figure ent itled Read to Write: C AS Latenc ies (Bu rst

Length = 4 or 8) on page 30. The example is s hown for tDQSS(min ). The tDQSS(max) case , not shown here, has a longer bu s idle

time. tDQSS(min) and tDQSS(max) are defined in the section on Writes.

A Read burst may be followed by, or truncated with, a Precharge command to the same bank (provided that Auto Precharge

was no t activated ). The Prech arge comm and shoul d be issued x cy cles afte r the Read co mmand, whe re x equa ls the numb er of

desired data element pairs (pairs are required by the 2n prefetch architecture). This is shown in timing figure Read to Pre-

charge: C AS La ten cies (Burst Length = 4 or 8) on pag e 31 f or Read latencie s of 2 and 2.5. F ollowing the Prec harg e comman d,

a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden

during the access of the last data elements.

In the case of a Read being executed to completion, a Precharge command issued at the optimum time (as described above)

provide s the sam e oper ation that wou ld res ult f rom th e sam e Read burs t with Auto Pre charge enabl ed. Th e dis advantag e of the

Precharge command is that it requires that the command and address busses be available at the appropriate time to issue the

command. The advantage of the Precharge command is that it can be used to truncate bursts.

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.4

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NANYA TECHNOL OGY CORP. reserve s the right to change Products and Specifications without notice.

Terminating a Read Burst: CAS Latencies (Burst Length = 8)

CAS Latency = 2

NOP BST NOP NOP NOPRead

Command

Address

DQS

DO a-n = data out from bank a, column n.

Cases shown are bursts of 8 terminated after 4 data elements.

3 subsequent elements of data out appear in the programmed order following DO a-n.

Shown with nominal tAC, tDQSCK, and tDQSQ.

DOa-n

Don’t Care

BAa, COL n

CL=2

CAS Latenc y = 2.5

NOP BST NOP NOP NOPRead

Command

Address

DQS

DQ DOa-n

BAa, COL n

CL=2.5

No further output data after this point.

DQS tristated.

No further output data after this point.

DQS tristated.

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.4

05/2003 30

NANYA TECHNOL OGY CORP. reserve s the right to change Products and Specifications without notice.

Read to Write: CAS Latencies (Burst Length = 4 or 8)

CAS Latency = 2

BST NOP Write NOP NOPRead

DI a-b

Command

Address

DQS

DOa-n

DO a-n = data out from bank a, column n

1 subsequent elements of data out appear in the programmed order following DO a-n.

Data In elements are applied following Dl a-b in the programmed order, according to burst length. Don’t Care

BAa, COL n BAa, COL b

CL=2 tDQSS (min)

CAS Latency = 2.5

BST NOP NOP Write NOPRead

Command

Address

DQS

DOa-n

BAa, COL n BAa, COL b

CL=2.5 tDQSS (min)

Dla-b

Shown with nominal tAC, tDQSCK, and tDQSQ.

DI a-b = data in to bank a, column b

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.4

05/2003 31

NANYA TECHNOL OGY CORP. reserve s the right to change Products and Specifications without notice.

Read to Precharge: CAS Latencies (Burst Length = 4 or 8)

CAS Latency = 2

NOP PRE NOP NOP ACTRead

Command

Address

DQS

DQ DOa-n

DO a-n = data out from bank a, column n.

Cases shown are either uninterrupted bursts of 4 or interrupted bursts of 8.

3 subsequent elements of data out appear in the programmed order following DO a-n.

Shown with nominal tAC, tDQSCK, and tDQSQ.Don’t Care

BA a, COL n BA a or all BA a, ROW

CL=2.5

CAS Latency = 2.5

NOP PRE NOP NOP ACTRead

Command

Address

DQS

DQ DOa-n

tRP

BA a, COL n BA a or all BA a, ROW

CL=2

tRP

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.4

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NANYA TECHNOL OGY CORP. reserve s the right to change Products and Specifications without notice.

Writes

Write bursts are initiated with a Write command, as shown in timing figure Write Command on page 33.

The starting column and bank addresses are provided with the Write command, and Auto Precharge is either enabled or dis-

abled for that access. If Auto Precharge is enabled, the row being accessed is precharged at the completion of the burst. For

the generic Write commands used in the following illustrations, Auto Precharge is disabled.

During Write b ursts, the fi rst va lid da ta-in e lemen t is regis ter ed on t he firs t risi ng edg e of DQ S follo wing the writ e comma nd, and

subsequent data elements are registered on successive edges of DQS. The Low state on DQS between the Write command

and the first rising edge is known as the write preamble; the Low state on DQS following the last data-in element is known as

the write postamble. The time between the Write command and the first corresponding rising edge of DQS (tDQSS) is spec ified

with a relatively wide range (from 75% to 125% of one clock cycle), so most of the Write diagrams that follow are drawn for the

two extreme cases (i.e. tDQSS(min) and tDQSS(max)). Timing figure Writ e Bur st (Burs t Length = 4) on page 34 shows the two

extremes of tDQSS for a burst of four. Upon completion of a burst, assuming no other commands have been initiated, the DQs

and DQS enters High-Z and any additional input data is ignored.

Data for any Write burst may be co ncatenate d with or trunc ated with a subs equent Write co mmand. In ei ther case, a co ntinuous

flow of input data can be maintained. The new Write command can be issued on any positive edge of clock following the previ-

ous Write command. The first data element from the new burst is applied after either the last element of a completed burst or

the last desired data element of a longer burst which is being truncated. The new Write command should be issued x cycles

after the first Write command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch

architecture). Timing figure Write to Write (Burst Length = 4) on page 35 shows concatenated bursts of 4. An example of non-

consecutive Writes is shown in timing figure Write to Write: Max DQSS, Non-Consecutive (Burst Length = 4) on page 36. Full-

speed random write accesses within a page or pages can be performed as shown in timing figure Random Write Cycles (Burst

Length = 2, 4 or 8) on page 37. Data for any Write burst may be followed by a subsequent Read command. To follow a Write

withou t tr unc ati ng the w rite bu rst, tWTR (Write to Read ) s hou ld be me t a s sho w n i n t im ing fi gure Wri te to R e ad: N on -Inte rrupt ing

(CAS Latency = 2; Burst Length = 4) on page 38.

Data for any Write burst may be truncated by a subsequent (interrupting) Read command. This is illustrated in timing figures

“Write to Read: Interrupting (CAS Latency =2; Burst Length = 8)”, “Write to Read: Minimum DQSS, Odd Number of Data (3 bit

Write), Interrupting (CAS Latency = 2; Burst Length = 8)”, and “Write to Read: Nominal DQSS, Interrupting (CAS Latency = 2;

Burst Length = 8)”. Note that only the data-in pairs that are registered prior to the tWTR period are written to the internal array,

and any subsequent data-in must be masked with DM, as shown in the diagrams noted previously.

Data for any Write burst may be followed by a subsequent Precharge command. To follow a Write without truncating the write

burst, tWR should be met as shown in timing figure Write to Precharge: Non-Interrupting (Burst Length = 4) on page 42.

Data for any Write burst may be truncated by a subsequent Precharge command, as shown in timing figures Writ e to Pre-

charge: Interrupting (Burst Length = 4 or 8) on page 43 to Write to Precharge: Nominal DQSS (2 bit Write), Interrupting (Burst

Length = 4 or 8) on p ag e 4 5. No te that only th e d ata -in pai rs tha t a r e re gis te red prio r to the tWR period a r e wri tten to th e i nte rnal

array, and any subsequent data in should be masked with DM. Following the Precharge command, a subsequent command to

the same bank cannot be issued until tRP is met.

In the case of a Write burst being executed to completion, a Precharge command issued at the optimum time (as described

above) provides the same operation that would result from the same burst with Auto Precharge. The disadvantage of the Pre-

charge c omm and is that i t require s that the comman d a nd addr ess b usses be av ailab le at th e appro priate time t o iss ue the c om-

mand. The advantage of the Precharge command is that it can be used to truncate bursts.

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.4

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NANYA TECHNOL OGY CORP. reserve s the right to change Products and Specifications without notice.

Write Command

HIGH

CA = column address

BA = bank address

CKE

RAS

CAS

A10

BA0, BA1

Don’t Care

x4: A0-A9, A11

x8: A0-A9

EN AP

DIS AP

EN AP = enable Auto Precharge

DIS AP = disable Auto Precharg

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.4

05/2003 34

NANYA TECHNOL OGY CORP. reserve s the right to change Products and Specifications without notice.

Write Burst (Burst Length = 4)

T1 T2 T3 T4

tDQSS (max)

NOP NOP NOPWrite

DI a-b = data in for bank a, column b.

3 subsequent elements of data in are applied in the programmed order following DI a-b.

A non-interrupted burst is shown.

A10 is Low with the Write command (Auto Precharge is disabled).

Command

Address

DQS

Don’t Care

Maximum DQSS

BA a, COL b

T1 T2 T3 T4

tDQSS (min)

NOP NOP NOPWrite

Command

Address

DQS

Minimum DQSS

BA a, COL b

Dla-b

QFC tQCSW(max) tQCHW(min)

(Optional)

QFC tQCSW(max) tQCHW(max)

QFC is an open drain driver. Its output high level is achieved through an externally connected pull up resistor connected to VDDQ.

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.4

05/2003 35

NANYA TECHNOL OGY CORP. reserve s the right to change Products and Specifications without notice.

Write to Write (Burst Length = 4)

T1 T2 T3 T4 T5 T6

tDQSS (max)

Maximum DQSS

NOP Write NOP NOP NOPWrite

DI a-b = data in for bank a, column b, etc.

3 subsequent elements of data in are applied in the programmed order following DI a-b.

3 subsequent elements of data in are applied in the programmed order following DI a-n.

A non-interrupted burst is shown.

Each Write command may be to any bank.

Command

Address

DQS

Don’t Care

T1 T2 T3 T4 T5 T6

Minimum DQSS

NOP Write NOP NOP NOPWrite

Command

Address

DQS

BAa, COL b BAa, COL n

BA, COL b BA, COL n

tDQSS (min)

DI a-b DI a-n

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.4

05/2003 36

NANYA TECHNOL OGY CORP. reserve s the right to change Products and Specifications without notice.

Write to Write: Max DQSS, Non- Consecutive (Burst Length = 4)

T1 T2 T3 T4 T5

tDQSS (max)

NOP NOP Write NOPWrite

DI a-b, etc. = data in for bank a, column b, etc.

3 subsequent elements of data in are applied in the programmed order following DI a-b.

3 subsequent elements of data in are applied in the programmed order following DI a-n.

A non-interrupted burst is shown.

Each Write command may be to any bank.

Command

Address

DQS

Don’t Care

BAa, COL b BAa, COL n

DI a-b DI a-n

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.4

05/2003 37

NANYA TECHNOL OGY CORP. reserve s the right to change Products and Specifications without notice.

Random Write Cycles (Burst Length = 2, 4 or 8)

T1 T2 T3 T4 T5

tDQSS (max)

Maximum DQSS

Write Write Write Write

Write

DI a-b DI a-n

DI a-b, etc. = data in for bank a, column b, etc.

b', etc. = odd or even complement of b, etc. (i.e., column address LSB inverted).

Each Write command may be to any bank.

DI a-b’ DI a-x DI a-x’ DI a-n’ DI a-a DI a-a’

Command

Address

DQS

Don’t Care

BAa, COL b BAa, COL x BAa, COL n BAa, COL a BAa, COL g

T1 T2 T3 T4 T5

Minimum DQSS

Write Write Write Write

Write

DI a-b DI a-nDI a-b’ DI a-x DI a-x’ DI a-n’ DI a-a DI a-a’

Command

Address

DQS

BAa, COL b BAa, COL x BAa, COL n BAa, COL a BAa, COL g

tDQSS (min)

DI a-g

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.4

05/2003 38

NANYA TECHNOL OGY CORP. reserve s the right to change Products and Specifications without notice.

Write to Read: Non-Interrupting (CAS Latency = 2; Burst Length = 4)

CL = 2

T1 T2 T3 T4 T5 T6

tWTR

NOP NOP NOP ReadWrite

DI a-b

NOP

DI a-b = data in for bank a, column b.

3 subsequent elements of data in are applied in the programmed order following DI a-b.

A non-interrupted burst is shown.

tWTR is referenced from the first positive CK edge after the last data in pair.

A10 is Low with the Write command (Auto Precha rge is disabled).

The Read and Write commands may be to any bank.

Command

Address

DQS

Don’t Care

Maximum DQSS

BAa, COL b BAa, COL n

T1 T2 T3 T4 T5 T6

tWTR

NOP NOP NOP ReadWrite NOP

Command

Address

Minimum DQSS

BAa, COL b BAa, COL n

tDQSS (max)

DI a-b

DQS

tDQSS (min)

CL = 2

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.4

05/2003 39

NANYA TECHNOL OGY CORP. reserve s the right to change Products and Specifications without notice.

Write to Read : Interrupting (CAS Latency = 2; Burst Length = 8)

T1 T2 T3 T4 T5 T6

tDQSS (max)

Maximum DQSS

NOP NOP NOP ReadWrite NOP

DI a-b = data in for bank a, column b.

An interrupted burst is shown, 4 data elements are written.

3 subsequent elements of data in are applied in the programmed order following DI a-b.

tWTR is referenced from the first positive CK edge after the last data in pair.

The Read command masks the last 2 data elements in the burst.

A10 is Low with the Write command (Auto Precharge is disabled).

The Read and Write commands are not necessarily to the same bank.

DIa - b

Command

Address

DQS

Don’t Care

BAa, COL b BAa, COL n

tWTR

CL = 2

T1 T2 T3 T4 T5 T6

Minimum DQSS

NOP NOP NOP ReadWrite NOP

Command

Address BAa, COL b BAa, COL n

tWTR

DI a-b

DQS

CL = 2

tDQSS (min)

1 = These bits are incorrectly written into the memory array if DM is low.

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.4

05/2003 40

NANYA TECHNOL OGY CORP. reserve s the right to change Products and Specifications without notice.

Write to Read: Minimum DQSS, Odd Number of Dat a (3 bit W rite), Interrupting (CAS

Latency = 2; Burst Length = 8)

DI a-b = data in for bank a, column b.

An interrupted burst is shown, 3 data elements are written.

2 subsequent elements of data in are applied in the programmed order following DI a-b.

tWTR is referenced from the first positive CK edge after the last desired data in pair (not the last desired data in element)

The Read command masks the last 2 data elements in the burst.

A10 is Low with the Write command (Auto Precharge is disabled).

The Read and Write commands are not necessarily to the same bank.

Don’t Care

T1 T2 T3 T4 T5 T6

NOP NOP NOP ReadWrite NOP

Command

Address BAa, COL b BAa, COL n

tWTR

DI a-b

DQS

CL = 2

tDQSS (min)

DM 122

1 = This bit is correctly written into the memory array if DM is low.

2 = These bits are incorrectly written into the memory array if DM is low.

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.4

05/2003 41

NANYA TECHNOL OGY CORP. reserve s the right to change Products and Specifications without notice.

Write to Read: Nominal DQSS, Interrupting (CAS Latency = 2; Burst Length = 8)

T1 T2 T3 T4 T5 T6

tDQSS (nom)

NOP NOP NOP ReadWrite NOP

DI a-b = data in for bank a, column b.

An interrupted burst is shown, 4 data elements are written.

3 subsequent elements of data in are applied in the programmed order following DI a-b.

tWTR is referenced from the first positive CK edge after the last desired data in pair.

The Read command masks the last 2 data elements in the burst.

A10 is Low with the Write command (Auto Precha rge is disabled).

The Read and Write commands are not necessarily to the same bank.

DI a-b

Command

Address

DQS

Don’t Care

BAa, COL b BAa, COL n

tWTR

CL = 2

1 = These bits are incorrectly written into the memory array if DM is low.

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

REV 1.4

05/2003 42

NANYA TECHNOL OGY CORP. reserve s the right to change Products and Specifications without notice.

Write to Precharge: Non-I n terrupting (Burst Length = 4)

T1 T2 T3 T4 T5 T6

tDQSS (max)

NOP NOP NOP NOPWrite

DI a-b

PRE

DI a-b = data in for bank a, column b.

3 subsequent elements of data in are applied in the programmed order following DI a-b.

A non-interrupted burst is shown.

tWR is referenced from the first positive CK edge after the last data in pair.

A10 is Low with the Write command (Auto Precharge is disabled).

Command

Address

DQS

Don’t Care

BA a, COL b BA (a or all)

tWR

Maximum DQSS

T1 T2 T3 T4 T5 T6

NOP NOP NOP NOPWrite PRE

Command

Address BA a, COL b BA (a or all)

tWR

Minimum DQSS

DI a-b

DQS

tDQSS (min)

tRP

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Write to Precharge: Interrupting (Burst Length = 4 or 8)

DI a-b = data in for bank a, column b.

An interrupted burst is shown, 2 data elements are written.

1 subsequent element of data in is applied in the programmed order following DI a-b.

tWR is referenced from the first positive CK edge after the last desired data in pair.

The Precharge command mask s the last 2 data elements in the burst, for burst length = 8.

A10 is Low with the Write command (Auto Precharge is disabled).

1 = Can be don't care for programmed burst length of 4.

2 = For programmed burst length of 4, DQS becomes don't care at this point. Don’t Care

T1 T2 T3 T4 T5 T6

NOP NOP NOP PREWrite NOP

Command

Address

Maximum DQSS

DI a-b

DQS

tDQSS (max) tRP

T1 T2 T3 T4 T5 T6

NOP NOP NOP PREWrite NOP

Command

Address BA a, COL b BA (a or all)

Minimum DQSS

tWR

tRP

DI a-b

DQS

tDQSS (min) 2

BA a, COL b BA (a or all)

tWR

3 = These bits are incorrectly written into the memory array if DM is low.

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

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Write to Precharge: Minimum DQSS, Odd Number of Data (1 bit Write), Interrupting

(Burst Length = 4 or 8)

DI a-b = data in for bank a, column b.

An interrupted burst is shown, 1 data element is written.

tWR is referenced from the first positive CK edge after the last desired data in pair.

The Precharge command masks the last 2 data elements in the burst.

A10 is Low with the Write command (Auto Precharge is disabled).

1 = Can be don't care for programmed burst length of 4.

2 = For programmed burst length of 4, DQS becomes don't care at this point.

Don’t Care

T1 T2 T3 T4 T5 T6

NOP NOP NOP PREWrite NOP

Command

Address BA a, COL b BA (a or all)

tWR

tRP

DI a-b

DQS

tDQSS (min) 2

DM 344

3 = This bit is correctly written into the memory array if DM is low .

4 = These bits are incorrectly written into the memory array if DM is low.

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NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

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NANYA TECHNOL OGY CORP. reserve s the right to change Products and Specifications without notice.

Write to Precharge: Nomina l DQSS (2 bit Write), Interrupting (Burst Length = 4 or 8)

DI a-b = Data In for bank a, column b.

An interrupted burst is shown, 2 data elements are written.

1 subsequent element of data in is applied in the programmed order following DI a-b.

tWR is referenced from the first positive CK edge after the last desired data in pair.

The Precharge command mask s the last 2 data elements in the burst.

A10 is Low with the Write command (Auto Precharge is disabled).

1 = Can be don't care for programme d burst length of 4.

2 = For programmed burst length of 4, DQS becomes don't care at this point. Don’t Care

T1 T2 T3 T4 T5 T6

NOP NOP NOP PREWrite NOP

Command

Address BA a, COL b BA (a or all)

tRP

tDQSS (nom)

DI a-b

DQS

DM 1

tWR

3 = These bits are incorrectly written into the memory array if DM is low.

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

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Precharge

The Precharge command is used to deactivate the open row in a particular bank or the open row in all banks. The

bank(s) is available for a subsequent row access some specified time (tRP) after the Precharge command is

issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank

is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are

treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any

Read or Write commands being issued to that bank.

Precharge Command

HIGH

BA = bank address

CKE

RAS

CAS

A10

BA0, BA1

Don’t Care

All Banks

One Bank

(if A10 is Low, otherwise Don’t Care).

A0-A9, A11, A12

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

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NANYA TECHNOL OGY CORP. reserve s the right to change Products and Specifications without notice.

Power Down

Power Down is entered when CKE is registered low (no accesses can be in progress). If Power Down occurs when all banks

are idle, this mode is referred to as Precharge Power Down; if Power Down occurs when there is a row active in any bank, this

mode is referred to as Active Power Down. Entering Power Down deactivates the input and output buffers, excluding CK, CK

and CKE. The DLL is still runn ing in Power Down mode, so for maxim um power sav ings, the user has the option of dis abling the

DLL pr ior to e nte ring Pow e r D own . In tha t c as e, the D LL mu st be enabled a fter ex iti ng Power Do wn, and 200 clo ck cy c les m us t

occur be fore a Re ad comm and can be issu ed. In Powe r Down mo de, CKE Low and a st able cl ock sign al mus t be mai ntaine d at

the inputs of the DDR SDRAM, and all other input signals are “Don’t Care”. However, Power Down duration is limited by the

refresh requirements of the device, so in most applications, the self refresh mode is preferred over the DLL-disabled Power

Down mode.

The Power Down state is synchronously exited when CKE is registered high (along with a Nop or Deselect command). A valid,

executable command may be applied one clock cycle later.

Power Down

tIS

CKE

Command

No column

access in

progress

VALID NOP VALID

Don’t Care

Exit

power down

mode

Enter Power Down mode

(Burst Read or Write operation

must not be in progress)

NOP

tPDEX

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

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Tr uth Table 2: Clo ck Enable (CKE)

1. CKE n is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.

2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.

3. Command n is the command registered at clock edge n, and action n is a result of command n.

4. All states and sequences not shown are illegal or reserved.

Current St ate

CKE n -1 CKEn

Command n Action n Notes

Cycle Current

Cycle

Self Refresh L L X Maintain Self-Refresh

Self Refresh L H Deselect or NOP Exit Self-Refresh 1

Power Down L L X Maintain Power Down

Power Down L H Deselect or NOP Exi t Power Down

All Banks Idle H L Deselect or NOP Precharge Power Down Entry

All Banks Idle H L Auto Refresh Self Refresh Entry

Bank(s) Active H L Deselect or NOP Active Power Down Entry

See “Truth Table 3: Current State

Bank n - Command to Bank n (Same

Bank)” on page 49

1. Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (tXSNR) period. A minimum of

200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.

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NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

NT5DS16M16BT NT5DS16M16BF NT5DS16M16BS NT5DS16M16BG

256Mb DDR SDRAM

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NANYA TECHNOL OGY CORP. reserve s the right to change Products and Specifications without notice.

Truth Table 3: Current State Bank n - Command to Bank n (Same Bank)

Current St ate CS RAS CAS WE Command Action Notes

Any H X X X Deselect NOP. Continue previous operation 1-6

L H H H No Operation NOP. Continue previous operation 1-6

Idle

L L H H Active Select and activate row 1-6

L L L H Auto Refresh 1-7

L L L L Mode Register Set 1-7

Row Active

L H L H Read Select column and start Read burst 1-6, 10

L H L L Write Select column and start Write burst 1-6, 10

L L H L Precharge Deactivate row in bank(s) 1-6, 8

Read

(Auto Precharge

Disabled)

L H L H Read Select column and start new Read burst 1-6, 10

L L H L Precharge Truncate Read burst, start Precharge 1-6, 8

L H H L Burst Terminat e Burst Terminate 1-6, 9

Write

(Auto Precharge

Disabled)

L H L H Read Select column and start Read burst 1-6, 10, 11

L H L L Write Select column and start Write burst 1-6, 10

L L H L Precharge Truncate Write burst, start Precharge 1-6, 8, 11

1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after tXSNR / tXSRD has been

met (if the previous state was self refresh).

2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed

to be issued to that bank when in that state. Exceptions are covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and tRP has been met.

Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in

progress.

Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

4. The following states must not be interrupted by a command issued to the same bank.

Precharging: Starts with registration of a Precharge command and ends when tRP is met. Once tRP is met, the bank is in the idle

state.

Row Activating: Starts with registration of an Active command and ends when tRCD is met. Once tRCD is met, the bank is in the “row

active” state.

Read w/Auto Precharge Enabled: Starts with registration of a Read command with Auto Precharge enabled and ends when tRP has been

met. Once tRP is met, the bank is in the idle state.

Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when tRP has been

met. Once tRP is met, the bank is in the idle state.

Deselect or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these

states. Allowable commands to the other bank are determined by its current state and according to Truth Table 4.

5. The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each positive

clock edge during these states.

Refreshing: Starts with registration of an Auto Refresh command and ends when tRFC is met. O nce tRFC is met, the DDR SDRAM is

in the “all banks idle” state.

Accessing Mode Register: Starts with registration of a Mode Register Set command and ends when tMRD has been met. Once tMRD is

met, the DDR SDRAM is in the “all banks idle” state.

Precharging All: Starts with registration of a Precharge All command and ends when tRP is met. Once tRP is met, all banks is in the idle

state.

6. All states and sequences not shown are illegal or reserved.

7. Not bank-specific; requires that all banks are idle.

8. May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging.

9. Not bank-s pecific; Burst term inate affects the most recent Read burst, regardless of bank.

10. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with

Auto Precharge disabled.

11. Requires appropriate DM masking.

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NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

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256Mb DDR SDRAM

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NANYA TECHNOL OGY CORP. reserve s the right to change Products and Specifications without notice.

Truth Table 4: Current State Bank n - Command to Bank m (Different bank)

(Part 1 of 2)

Current State CS RAS CAS WE Command Action Notes

Any H X X X Deselect NOP/continue previous operation 1-6

L H H H No Operation NOP/continue previous operation 1-6

Idle XXXX

Any Command Otherwise

Allowed to Bank m 1-6

Row Activating,

Active, or

Precharging

L L H H Acti ve Select and activate row 1-6

L H L H Read Select column and start Read burst 1-7

L H L L Write Select column and start Write burst 1-7

L L H L Precharge 1-6

Read

(Auto Precharge

Disabled)

L L H H Acti ve Select and activate row 1-6

L H L H Read Select column and start new Read burst 1-7

L L H L Precharge 1-6

Write

(Auto Precharge

Disabled)

L L H H Acti ve Select and activate row 1-6

L H L H Read Select column and start Read burst 1-8

L H L L Write Select column and start new Write burst 1-7

L L H L Precharge 1-6

1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after tXSNR / tXSRD has been

met (if the previous state was self refresh).

2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are

those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are cov-

ered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and tRP has been met.

Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are

in progress.

Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

Read with Auto Precharge Enabled: See note 10.

Write with Auto Precharge Enabled: See note 10.

4. Auto Refresh and Mode Register Set commands may only be issued when all banks are idle.

5. A Burst Terminate command cannot be issued to another bank; it applies to the bank represented by the current state only.

6. All states and sequences not shown are illegal or reserved.

7. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with

Auto Precharge disabled.

8. Requires appropriate DM masking.

9. A Write command may be applied after the completion of data output.

10. The Read with Auto Precharge enabled or Write with Auto Precharge enabled states can each be broken into two parts: the access

period and the precharge period. For Read with Auto Precharge, the pr echarge period is defined as if the same burst was executed with

Auto Precharge disabled and then followed with the earliest possible Precharge command that still accesses all of the data in the burst.

For Write with Auto Precharge, the precharge period begins when tWR ends, with tWR measured as if Auto Precharge was disabled. The

access period starts with registration of the command and ends where the precharge period (or tRP) begins. During the precharge period

of the Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states, Active, Precharge, Read, and Write commands to

the other bank may be applied; during the access period, only Active and Precharge commands to the other bank may be applied. In

either case, all other related limitations apply (e.g. contention between Read data and Write data must be avoided).

NT5DS64M4BT NT5DS64M4BF NT5DS64M4BS NT5DS64M4BG

NT5DS32M8BT NT5DS32M8BF NT5DS32M8BS NT5DS32M8BG

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256Mb DDR SDRAM

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Read (With

Auto Precharge)

L L H H Acti ve Select and activate row 1-6

L H L H Read Select column and start new Read burst 1-7,10

L H L L Write Select column and start Write burst 1-7,9,10

L L H L Precharge 1-6

Write (With

Auto Precharge)

L L H H Acti ve Select and activate row 1-6

L H L H Read Select column and start Read burst 1-7,10

L H L L Write Select column and start new Write burst 1-7,10

L L H L Precharge 1-6

Truth Table 4: Current State Bank n - Command to Bank m (Different bank)

(Part 2 of 2)