bq24278 www.ti.com SLUSB04 - JUNE 2012 2.5A, Single Input, Single Cell Switchmode Li-Ion BATTERY CHARGER with Power Path Management Check for Samples: bq24278 FEATURES * 1 * * * * * * High-Efficiency Switch Mode Charger with Separate Power Path Control - Instantly Startup System from a Deeply Discharged Battery or No Battery 20V input rating, with 10.5V Over-Voltage Protection (OVP) Integrated FETs for Up to 2.5A Charge Rate Highly Integrated Battery N-Channel MOSFET Controller for Power Path Management Safe and accurate Battery Management Functions - 0.5% Battery Regulation Accuracy - 10% Charge Current Accuracy Voltage-based, NTC Monitoring Input (TS) - Standard Temp Range * * * * Thermal Regulation Protection for Output Current Control Low Battery Leakage Current, BAT ShortCircuit Protection Soft-Start feature to reduce inrush current Thermal Shutdown and Protection Available in small 49-ball WCSP or QFN-24 packages APPLICATIONS * * * * Handheld Products Portable Media Players Portable Equipment Netbook and Portable Internet Devices APPLICATION SCHEMATIC IN VBUS D+ SW D- GND System Load VDPM PMID BOOT CD HOST SYS /CE ILIM BAT ISET BYP TS PGND /CHG /PG DRV_S DRV_S DRV PACK+ TEMP - + PACK- DESCRIPTION The bq24278 highly integrated single cell Li-Ion battery charger and system power path management device targeted for space-limited, portable applications with high capacity batteries. The single cell charger operates from a dedicated charging source such as an AC adapter or Wireless Power. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2012, Texas Instruments Incorporated bq24278 SLUSB04 - JUNE 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) The power path management feature allows the bq24278 to power the system from a high efficiency DC to DC converter while simultaneously and independently charging the battery. The charger monitors the battery current at all times and reduces the charge current when the system load requires current above the input current limit. This allows for proper charge termination and timer operation. The system voltage is regulated to the battery voltage but will not drop below 3.5V. This minimum system voltage support enables the system to run with a defective or absent battery pack and enables instant system turn-on even with a totally discharged battery or no battery. The power-path management architecture also permits the battery to supplement the system current requirements when the adapter cannot deliver the peak system currents. This enables the use of a smaller adapter. The battery is charged in three phases: conditioning, constant current and constant voltage. In all charge phases, an internal control loop monitors the IC junction temperature and reduces the charge current if the internal temperature threshold is exceeded. Additionally, the bq24278 offers a voltage-based battery pack thermistor monitoring input (TS) that monitors battery temperature for safe charging . ORDERING INFORMATION PART NUMBER IN OVP NTC MONITORING (TS) JEITA COMPATIBLE MINIMUM SYSTEM VOLTAGE PACKAGE bq24278YFFR 10.5 V Yes No 3.5 V WCSP bq24278YFFT 10.5 V Yes No 3.5 V WCSP bq24278RGER 10.5 V Yes No 3.5 V QFN bq24278RGET 10.5 V Yes No 3.5 V QFN ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) MIN MAX -2 20 V PMID, BYP, BOOT -0.3 20 V SW -0.7 12 V SYS, BAT, BGATE, DRV, PG, CHG, CE, CD, TS, DRV_S, ILIM, ISET, VDPM -0.3 7 V IN Pin voltage range (with respect to VSS) BOOT to SW Output current (continuous) -0.3 UNIT 7 V SW 4.5 A SYS 3.5 A 2.75 A Input current (continuous) IN Output sink current PG, CHG 10 mA Operating free-air temperature range -40 85 C Junction temperature, TJ -40 125 C Storage temperature, TSTG -65 150 C 300 C Lead temperature (soldering, 10 s) (1) 2 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted. Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s) :bq24278 bq24278 www.ti.com SLUSB04 - JUNE 2012 THERMAL INFORMATION bq24278 THERMAL METRIC (1) YFF (48 PINS) QFN (24 PINS) JA Junction-to-ambient thermal resistance 49.8 32.6 JCtop Junction-to-case (top) thermal resistance 0.2 30.5 JB Junction-to-board thermal resistance 1.1 3.3 JT Junction-to-top characterization parameter 1.1 0.4 JB Junction-to-board characterization parameter 6.6 9.3 JCbot Junction-to-case (bottom) thermal resistance N/A 2.6 UNITS C/W spacer (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. RECOMMENDED OPERATING CONDITIONS MIN MAX VIN IN voltage range 4.2 18 (1) IN operating range 4.2 10 IIN Input current IN input ISYS Ouput Current from SW, DC IBAT TJ (1) A 3 A 2.5 Discharging, using internal battery FET 2.5 0 V 2.5 Charging Operating junction temperature range UNITS 125 A C The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BOOT or SW pins. A tight layout minimizes switching noise. ELECTRICAL CHARACTERISTICS Circuit of Figure 2, VUVLO < VIN < VOVP AND VIN>VBAT+VSLP, TJ = 0C-125C and TJ = 25C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN VUVLO < VIN < VOVP AND VIN > VBAT+VSLP PWM switching IIN Input quiescent current TYP VUVLO < VIN < VOVP AND VIN > VBAT+VSLP PWM NOT switching Leakage current from BAT to the supply 0C< TJ < 85C, VBAT = 4.2V, VIN = 0 V IBAT_HIZ Battery discharge current in High Impedance mode (BAT, SW, SYS) 0C< TJ < 85C, VBAT = 4.2 V, VIN = 0 V or 5 V, High-Z Mode UNIT mA 5 0C < TJ < 85C, High-Z Mode IBATLEAK MAX 15 175 A 5 A 55 A POWER PATH MANAGEMENT VSYS(REG) VBAT < VMINSYS System regulation voltage VSYSREGFETOFF VMINSYS Minimum system regulation voltage 3.6 3.7 3.82 4.26 4.33 4.37 3.5 3.62 V Battery FET turned off, Charge disable or termination VBAT < VMINSYS, Input current limit or VINDPM active 3.4 V VBSUP1 Enter supplement mode threshold VBAT > 2.5 V VBAT - 40mV VBSUP2 Exit supplement mode threshold VBAT > 2.5 V VBAT - 10mV V ILIM(Discharge) Current limit, discharge or supplement mode Current monitored in internal FET only 7 A tDGL(SC1) Deglitch time, OUT short circuit during discharge or supplement mode Measured from (VBAT - VSYS) = 300 mV to VBGATE = (VBAT - 600 mV) 250 s tREC(SC1) Recovery time, OUT short circuit during discharge or supplement mode Battery range for BGATE operation 60 2.5 ms 4.5 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s) :bq24278 V V 3 bq24278 SLUSB04 - JUNE 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Circuit of Figure 2, VUVLO < VIN < VOVP AND VIN>VBAT+VSLP, TJ = 0C-125C and TJ = 25C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX YFF pkg 37 57 RGE pkg 50 70 UNIT BATTERY CHARGER RON(BAT-SYS) VBATREG Measured from BAT to SYS, VBAT = 4.2 V Internal battery charger MOSFET on-resistance Battery regulation voltage m TA = 25C 4.179 4.2 4.221 VWARM < VTS < VCOOL 4.160 4.2 4.24 4.04 4.06 4.08 4.02 4.06 4.1 V TA = 25C VHOT < VTS < VWARM K ICHARGE Charge current programmable range KISET Programmable fast charge current factor VBATSHRT VBATSHRThys ISET I = CHARGE R ISET 550 2500 mA TA = 0C to 125C, VWARM < VTS < VCOOL 400 490 560 TA = 0C to 125C, VCOLD < VTS < VCOOL 225 245 270 Battery short threshold VBAT Rising 2.9 3.0 3.1 Battery short threshold hysteresis VBAT Falling 100 mV IBATSHRT Battery short current VBAT < VBATSHRT 50.0 mA tDGL(BATSHRT) Deglitch time for battery short to fast charge transition A 32 ms ICHARGE 1A 7 10 11.5 ICHARGE >1A 8 10 11 ITERM Termination charge current tDGL(TERM) Deglitch time for charge termination Both rising and falling, 2-mV over-drive, tRISE, tFALL = 100 ns VRCH Recharge threshold voltage Below VBATREG tDGL(RCH) Deglitch time VBAT falling below VRCH, tFALL = 100 ns IDETECT tDETECT V %ICHARGE 32 ms 120 mV 32 ms Battery detection current before charge done (sink current) 2.5 mA Battery detection time 250 ms INPUT PROTECTION K ILIM I = INLIM R ILIM IINLIM Maximum input current limit programmable range for IN input KILIM Maximum input current factor for IN input 238 VIN_DPM_IN VIN_DPM threshold programmable range for IN Input 4.2 1000 VDPM threshold VDRV Internal bias regulator voltage IDRV DRV Output current VDO_DRV DRV Dropout voltage (VIN - VDRV) IIN = 1A, VIN = 5 V, IDRV = 10 mA VUVLO IC active threshold voltage VIN rising VUVLO_HYS IC active hysteresis VIN falling from above VUVLO VSLP Sleep-mode entry threshold, VIN-VBAT 2.0 V VBAT VOREG, VIN falling VSLP_EXIT Sleep-mode exit hysteresis 2.0 V VBAT VOREG Deglitch time for supply rising above VSLP+VSLP_EXIT Rising voltage, 2-mV over drive, tRISE = 100 ns VOVP Input supply OVP threshold voltage IN, VIN Rising VOVP(HYS) VOVP hysteresis Supply falling from VOVP VBOVP Battery OVP threshold voltage VBAT threshold over VOREG to turn off charger during charge VBOVP hysteresis Lower limit for VBAT falling from above VBOVP VBATUVLO Battery UVLO threshold voltage ILIMIT Cycle by Cycle current limit TSHUTDWN Thermal shutdown TREG Thermal regulation threshold 251 2500 mA 264 A 10 V V 1.18 1.2 1.22 5 5.2 5.45 10 450 3.6 V mA 3.8 4.0 150 mV V mV 0 40 100 mV 40 100 160 mV 30 10.3 10.5 ms 10.7 100 1.025 x VBATREG 1.05 x VBATREG 1.075 x VBATREG 2.5 10C Hysteresis 4.9 V 5.6 165 324 VIH Input high threshold 1.3 VIL Input low threshold IIH High-level leakage current VCHG = VPG = 5 V VOL Low-level output saturation voltage IO = 10 mA, sink current 360 A C 120 Safety Timer V % of VBATREG 1 4.1 V mV C 396 min CE, CD, PG, CHG 4 Submit Documentation Feedback V 0.4 V 1 A 0.4 V Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s) :bq24278 bq24278 www.ti.com SLUSB04 - JUNE 2012 ELECTRICAL CHARACTERISTICS (continued) Circuit of Figure 2, VUVLO < VIN < VOVP AND VIN>VBAT+VSLP, TJ = 0C-125C and TJ = 25C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PWM CONVERTER Internal top reverse blocking MOSFET on-resistance IIN_LIMIT = 500 mA, Measured from VIN to PMIDU 95 175 m Internal top N-channel Switching MOSFET on-resistance Measured from PMIDU to SW 100 175 m Internal bottom N-channel MOSFET on-resistance Measured from SW to PGND 65 115 m 1.50 1.65 MHz fOSC Oscillator frequency DMAX Maximum duty cycle DMIN Minimum duty cycle 1.35 95% 0 BATTERY-PACK NTC MONITOR VHOT High temperature threshold VTS falling VHYS(HOT) Hysteresis on high threshold VTS rising 29.7 30 30.5 VCOLD Low temperature threshold VTS rising 59.5 60 60.4 VWARM Warm temperature threshold VTS falling 37.9 38.3 39.6 VHYS(WARM) Hysteresis on warm threshold VTS rising VCOOL Cool temperature threshold VTS rising VHYS(COOL) Hysteresis on cool threshold VTS falling VHYS(COLD) Hysteresis on low threshold VTS falling TSOFF TS Disable threshold VTS rising, 2% VDRV Hysteresis tDGL(TS) Deglitch time on TS change 1 1 56.0 56.5 %VDRV 56.9 1 1 70 73 50 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s) :bq24278 ms 5 bq24278 SLUSB04 - JUNE 2012 www.ti.com BLOCK DIAGRAM PMID BYP 5.2V Reference DRV IN 5A + BOOT CbC Current Limit IN IINLIM ILIM Q1 IN VINDPM DC-DC CONVERTER PWM LOGIC, COMPENSATION AND BATTERY FET CONTROL VSYS(REG) IBAT (REG) VBAT (REG) SW DIE Temp Regulation Q2 PGND SYS VSUPPLY DRV_S References ISET V INOVP 10% of ICHARGE + OVP Comparator + V IN Termination Comparator Q3 IBAT BAT Recharge Comparator V IN V BAT +V SLP Start Recharge Cycle + + V BATREG - 0.12V VBAT Hi-Impedance Mode Sleep Comparator VSYSREG Comparator Enable Linear Charge + BGATE VSYS VMINSYS VBATSC Comparator /CE Enable IBATSHRT CD + VBAT V BATSHRT TS Supplement COMPARATOR VSYS + VBAT VBSUP VDRV V BOVP Comparator + VBAT VBATOVP + DISABLE TS COLD 1C/ 0.5C + TS COOL + 4.2V/ 4.06V /CHG TS WARM + DISABLE /PG CHARGE CONTROLLER TS HOT w/ Timer 6 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s) :bq24278 bq24278 www.ti.com SLUSB04 - JUNE 2012 PIN CONFIGURATION SPACER 49-BALL WCSP (TOP VIEW) 1 2 3 4 5 7 6 A IN IN IN IN AGND AGND AGND B PMID PMID PMID PMID BYP BYP BYP C SW SW SW SW SW SW SW D PGND PGND PGND PGND PGND PGND PGND E ILIM CD VDPM /CE DRV_S DRV_S BOOT SYS SYS SYS SYS BGATE /PG DRV BAT BAT BAT BAT TS /CHG ISET F G /CE BYP AGND IN PMID BOOT 24 23 22 21 20 19 24-PIN QFN (TOP VIEW) VDPM 1 18 SW CD 2 17 PGND DRV_S 3 16 PGND 15 ILIM SYS SYS DRV_S bq24278 4 ISET 5 14 DRV 6 13 7 8 9 10 11 12 /PG /CHG TS BGATE BAT BAT Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s) :bq24278 7 bq24278 SLUSB04 - JUNE 2012 www.ti.com PIN FUNCTIONS PIN NAME NUMBER I/O DESCRIPTION YFF RGE IN A1-A4 21 I Input power supply. IN is connected to the external DC supply (AC adapter or alternate power source). Bypass IN to PGND with at least a 1F ceramic capacitor. AGND A5-A7 22 I Ground terminal. Connect to the thermal pad (for QFN only) and the ground plane of the circuit. PMID B1-B4 20 O Reverse Blocking MOSFET and High Side MOSFET Connection Point for High Power Input. Bypass PMID to PGND with at least a 4.7F ceramic capacitor. Use caution when connecting an external load to PMID. The PMID output is not current limited. Any short on PMID will result in damage to the IC. BYP B5-B7 23 O Bypass for internal supply. Bypass BYP to GND with at least a 0.1F ceramic capacitor. SW C1-C7 18 O Inductor Connection. Connect to the switched side of the external inductor. PGND D1-D7 16, 17 -- Ground terminal for Switching FET. Connect to the thermal pad (for QFN only) and the ground plane of the circuit. ILIM E1 15 I IN Input Current Limit Programming Input. Connect a resistor from ILIM to GND to program the input current limit for IN. The current limit is programmable from 1A to 2.5A. CD E2 2 I IC Hardware Disable Input. Drive CD high to place the bq24278 in high-z mode. Drive CD low for normal operation. I Input DPM Programming Input. Connect a resistor divider from IN to PGND with VDPM connected to the center tap to program the Input Voltage based Dynamic Power Management (VIN_DPM) threshold. The input current is reduced to maintain the supply voltage at VIN_DPM. See the Input Voltage based Dynamic Power Management section for a detailed explanation. VDPM E3 1 E4 24 I Charge Enable Input. CE is used to disable or enable the charge process. A low logic level (0) enables charging and a high logic level (1) disables charging. When charging is disabled, the SYS output remains in regulation, but BAT is disconnected from SYS. Supplement mode is still available if the system load demands cannot be met by the supply. DRV_S E5, E6 3, 4 I Supply for Internal Circuits. Connect DRV_S to DRV directly. BOOT E7 19 I High Side MOSFET Gate Driver Supply. Connect a 0.01F ceramic capacitor (voltage rating > 10V) from BOOT to SW to supply the gate drive for the high side MOSFETs. F1-F4 13,14 I/O System Voltage Sense and Charger FET Connection. Connect SYS to the system output at the output bulk capacitors. Bypass SYS locally with 1F. BGATE F5 10 O External Discharge MOSFET Gate Connection. BGATE drives an external P-Channel MOSFET to provide a very low resistance discharge path. Connect BGATE to the gate of the external MOSFET. BGATE is low during supplement mode and when no input is connected. PG F6 7 I Power Good Open Drain Output. /PG is pulled low when a valid supply is connected to IN. A valid supply is between VBAT+VSLP and VOVP. If no supply is connected or the supply is out of this range, PG is high impedance. CE SYS DRV F7 6 O Gate Drive Supply. DRV is the bias supply for the gate drive of the internal MOSFETs. bypass DRV to PGND with a 1F ceramic capacitor. DRV may be used to drive external loads up to 10mA. DRV is active whenever the input is connected and VSUPPLY > VUVLO and VSUPPLY > (VBAT + VSLP) BAT G1-G4 11, 12 I/O Battery Connection. Connect to the positive terminal of the battery. Additionally, bypass BAT to GND with a 1F capacitor. TS G5 9 I Battery Pack NTC Monitor. Connect TS to the center tap of a resistor divider from DRV to GND. The NTC is connected from TS to GND. The TS function in the bq24278 provides 2 thresholds for Hot/ Cold shutoff, with 2 additional thresholds for JEITA compliance. See the NTC Monitor section for more details on operation and selecting the resistor values. CHG G6 8 O Charge Status Open Drain Output. CHG is pulled low when a charge cycle starts and remains low while charging. CHG is high impedance when the charging terminates and when no supply exists. CHG does not indicate recharge cycles. ISET G7 5 I Charge Current Programming Input. Connect a resistor from ISET to GND to program the fast charge current. The charge current is programmable from 550mA to 2.5A. -- There is an internal electrical connection between the exposed thermal pad and the VSS pin of the device. The thermal pad must be connected to the same potential as the VSS pin on the printed circuit board. Do not use the thermal pad as the primary ground input for the device. VSS pin must be connected to ground at all times. Thermal Pad 8 -- Pad Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s) :bq24278 bq24278 www.ti.com SLUSB04 - JUNE 2012 TYPICAL APPLICATION CIRCUIT SW VBUS IN PMID D- System Load 0.01 F D+ BOOT GND 1 F 4.7 F SYS PGND VDPM 10 F ILIM BGATE BAT BYP V DRV 0.1 F 1 F GND TS DRV PACK+ TEMP HOST DRV_S 1 F + - DRV_S ISET PACK- /PG /CHG bq24278 CD GPIO CE GPIO Figure 1. bq24278 Application Circuit, External Discharge FET Connected Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s) :bq24278 9 bq24278 SLUSB04 - JUNE 2012 www.ti.com DETAILED DESCRIPTION The bq24278 is a highly integrated single cell Li-Ion battery charger and system power path management devices targeted for space-limited, portable applications with high capacity batteries. The power path management feature allows the bq24278 to power the system from a high efficiency DC to DC converter while simultaneously and independently charging the battery. The charger monitors the battery current at all times and reduces the charge current when the system load requires current above the input current limit. This allows for proper charge termination and enables the system to run with a defective or absent battery pack. Additionally, this enables instant system turn-on even with a totally discharged battery or no battery. The power-path management architecture also permits the battery to supplement the system current requirements when the adapter cannot deliver the peak system currents. This enables the use of a smaller adapter. The battery is charged in three phases: conditioning, constant current and constant voltage. In all charge phases, an internal control loop monitors the IC junction temperature and reduces the charge current if the internal temperature threshold is exceeded. Charge Mode Operation Charge Profile Charging is done through the internal battery MOSFET. When the battery voltage is above 3.5V, the system output (SYS) is connected to the battery to maximize the charging efficiency. There are 5 loops that influence the charge current; constant current loop (CC), constant voltage loop (CV), thermal regulation loop, minimum system voltage loop (MINSYS) and input voltage dynamic power management loop (VIN-DPM). During the charging process, all five loops are enabled and the dominant one takes control. The bq24278 supports a precision Li-Ion or Li-Polymer charging system for single-cell applications. The minimum system output feature regulates the system voltage to a minimum of VSYS(REG), so that startup is enabled even for a missing or deeply discharged battery. Figure 2 shows a typical charge profile including the minimum system output voltage feature. Precharge Phase Current Regulation Phase Voltage Regulation Phase Regulation voltage Regulation Current System Voltage VSYS VBATSHORT Battery Voltage Charge Current Termination IBATSHORT 50mA Linear Charge to Close Pack Protector Linear Charge to Maintain Minimum System Voltage Battery FET is OFF Battery FET is ON Figure 2. Typical Charging Profile of bq24278 10 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s) :bq24278 bq24278 www.ti.com SLUSB04 - JUNE 2012 PWM Controller in Charge Mode The bq24278 provides an integrated, fixed 1.5 MHz frequency voltage-mode controller with to power the system and supply the charge current. The converter is internally compensated and provides enough phase margin for stable operation, allowing the use of small ceramic capacitors with very low ESR. The bq24278 input scheme prevents battery discharge when the supply voltage is lower than VBAT. The high-side N-MOSFET (Q1) switches to control the power delivered to SYS. The DRV LDO supplies the gate drive for the internal MOSFETs. The high-side MOSFET is supplied by a boot strap circuit with external boot-strap capacitor (BST). The input is protected from short circuit by a cycle-by-cycle current limit that is sensed through the high-side MOSFET. The threshold is set to a nominal 5-A peak current. The input also utilizes an input current limit that limits the current from the power source. Battery Charging Process When the battery is deeply discharged or shorted, the bq24278 applies a 50mA current to charge the battery voltage up to acceptable charging levels. During this time, the battery FET is linearly regulated to maintain the system output regulation at VSYS(REG). Once the battery rises above VSHORT, the charge current increases to the fastcharge current setting. The SYS voltage is regulated to VSYS(REG) while the battery is linearly charged through the battery FET. Additionally, the thermal regulation loop reduces the charge current to maintain the die temperature at safe levels. Under normal conditions, the time spent in this region is a very short percentage of the total charging time, so if the charge current is reduced, the reduced charge rate does not have a major negative effect on total charge time. If the current limit for the SYS output is reached (limited by the input current limit, or VIN_DPM), the charge current is reduced to provide the system with all the current that is needed. If the charge current is reduced to 0mA, pulling further current from SYS causes the output to fall to the battery voltage and enter supplement mode (see the "Dynamic Power Path Management" section for more details). Once the battery is charged enough to where the system voltage begins to rise above VSYSREG (depends on the charge current setting), the battery FET is turned on fully and the battery is charged with the programmed charge current programmed using the ISET input, ICHARGE. The slew rate for fast charge current is controlled to minimize the current and voltage over-shoot during transient. The charge current is programmed by connecting a resistor from ISET to GND. The value for RISET is calculated using Equation 1. KISET RISET = ICHARGE (1) Where ICHARGE is the programmed fast charge current and KISET is the programming factor found in the Electrical Characteristics table. The charge current is regulated to ICHARGE until the battery is charged to the regulation voltage. Once the battery voltage is close to the regulation voltage, VBATREG, the charge current is tapered down as shown in Figure 2 while the SYS output remains connected to the battery. The voltage regulation feedback occurs by monitoring the battery-pack voltage between the BAT and PGND pins. The bq24278 monitors the charging current during the voltage regulation phase. Once the termination threshold, ITERM, is detected and the battery voltage is above the recharge threshold, the bq24278 terminates charge and turns off the battery charging FET and begins battery detection. The system output is regulated to the VBAT(REG) voltage and supports the full current available from the input and the battery supplement mode (see the "Dynamic Power Path Management" section for more details) is still available. A charge cycle is initiated when one of the following conditions is detected: 1. The battery voltage falls below the VBAT(REG)-VRCH threshold. 2. VIN Power-on reset (POR) 3. CE toggle 4. Toggle Hi-Impedance mode (using CD) If the battery voltage is ever greater than VBAT(REG), the PWM converter is turned off and the battery is discharged to VBAT(REG). This prevents further overcharging the battery and allows the battery to discharge to safe operating levels. Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s) :bq24278 11 bq24278 SLUSB04 - JUNE 2012 www.ti.com Battery Detection When termination conditions are met, a battery detection cycle is started. During battery detection, IDETECT is pulled from VBAT for tDETECT to verify there is a battery. If the battery voltage remains above VDETECT for the full duration of tDETECT, a battery is determined to be present and the IC enters "Charge Done". If VBAT falls below VDETECT, a "Battery Not Present" fault is signaled and battery detection continues. During the next cycle of battery detection, the bq24278 turns on IBATSHORT for tDETECT. If VBAT rises to VDETECT, the current source is turned off and after tDETECT, the battery detection continues through another current sink cycle. Battery detection continues until charge is disabled or a battery is detected. Once a battery is detected, the fault status clears and a new charge cycle begins. Battery detection is disabled when termination is disabled. Dynamic Power Path Management The bq24278 features a SYS output that powers the external system load connected to the battery. This output is active whenever a source is connected to IN or BAT. The following sections discuss the behavior of SYS with a source connected to the supply or a battery source only. Input Source Connected When a source is connected to IN, and the bq24278 is enabled, the buck converter starts up. If charging is enabled using CE, the charge cycle is initiated. When VBAT > 3.5V, the SYS output is connected to VBAT. If the SYS voltage falls to VSYS(REG), it is regulated to that point to maintain the system output even with a deeply discharged or absent battery. In this mode, the SYS output voltage is regulated by the buck converter and the battery FET is linearly regulated to regulate the charge current into the battery. The current from the supply is shared between charging the battery and powering the system load at SYS. The dynamic power path management (DPPM) circuitry of the bq24278 monitors the SYS voltage continuously and if VSYS falls to VMINSYS, adjusts charge current to maintain the load on SYS while preventing the system voltage from crashing. If the charge current is reduced to zero and the load increases further, the bq24278 enters battery supplement mode. During supplement mode, the battery FET is turned on and the battery supplements the system load. When the charge current is reduced by the DPPM regulation loop, the safety timer runs at half speed, so that it is twice a long. This prevents false safety timer faults. See the Safety Timer section for more details. 12 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s) :bq24278 bq24278 www.ti.com SLUSB04 - JUNE 2012 2000mA 1800mA IOUT 800mA 0mA 1500mA IIN ~850mA 0mA 1A IBAT 0mA -200mA 3.7V 3.5V DPPM loop active VOUT ~3.1V Supplement Mode Figure 3. Example DPPM Response (VSupply=5V, VBAT = 3.1V, 1.5A Input current limit) If the VBAT(REG) threshold is ever less than the battery voltage, the battery FET is turned off to allow the battery to relax down to VBAT(REG) and the SYS output is regulated to VSYSREG(FETOFF). If the battery is ever above VBOVP, the battery OVP circuit shuts the PWM converter off and the battery FET is turned on to discharge the battery to safe operating levels. The input current limit for IN is programmable using the ILIM input. Connect a resistor from ILIM to GND to set the maximum input current limit. The programmable range for the IN input current limit is 1000mA to 2.5A. RILIM is calculated using Equation 2: K RILIM = ILIM IIN _ LIM (2) Where IIN_LIM is the programmed input current limit and KILIM is the programming factor found in the Electrical Characteristics table. Battery Only Connected When the battery is connected with no input source, the battery FET is turned on similar to supplement mode. In this mode, the current is not regulated; however, there is a short circuit current limit. If the short circuit limit is reached, the battery FET is turned off for the deglitch time. After the deglitch time, the battery FET is turned on to test and see if the short has been removed. If it has not, the FET turns off and the process repeats until the short is removed. Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s) :bq24278 13 bq24278 SLUSB04 - JUNE 2012 www.ti.com Battery Discharge FET (BGATE) The bq24278 contains a MOSFET driver to drive an external P-Channel MOSFET between the battery and the system output. This external FET provides a low impedance path for supply the system from the battery. Connect BGATE to the gate of the external discharge MOSFET. BGATE is on under the following conditions: 1. No valid input supply connected. 2. CD=high (High-Impedance Mode) This FET is optional and runs in parallel with the internal charge FET during discharge. Note that this FET is not protected by the short circuit current limit. Safety Timer At the beginning of charging process, the bq24278 starts the 6 hour safety timer. This timer is active during the entire charging process. If charging has not terminated before the safety timer expires, the charge cycle is terminated and the battery FET is turned off. A new charge cycle must be entered using CE or High Impedance mode or input power must be toggled in order to clear the safety timer fault. During the fast charge phase, several events increase the timer durations. 1. The system load current reduces the available charging current 2. The input current is reduced because the VINDPM loop is preventing the supply from crashing. 3. The device has entered thermal regulation because the IC junction temperature has exceed TJ(REG) During these events, the timer is slowed by half to extend the timer and prevent any false timer faults. Starting a new charge cycle by toggling the input, toggling the CE pin to disable/enable charge, resets the safety timer. Additionally, thermal shutdown events cause the safety timer to reset. LDO Output (DRV) The bq24278 contains a linear regulator (DRV) that is used to supply the internal MOSFET drivers and other circuitry. Additionally, DRV supplies up to 10mA external loads to power the STAT LED or other external circuitry. The LDO is on whenever a supply is connected to the input of the. The DRV is disabled under the following conditions: 1. VIN < UVLO 2. VIN < VBAT + VSLP 3. Thermal Shutdown External NTC Monitoring (TS) The I2C interface allows the user to easily implement the JEITA standard for systems where the battery pack thermistor is monitored by the host. Additionally, the bq24278 provides a flexible, voltage-based TS input for monitoring the battery pack NTC thermistor, Figure 4. The voltage at TS is monitored to determine that the battery is at a safe temperature during charging. The bq24278 enables the user to easily implement the JEITA standard for charging temperature. The JEITA specification is shown in Figure 5. 14 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s) :bq24278 bq24278 www.ti.com SLUSB04 - JUNE 2012 VDRV DISABLE TS COLD + VDRV TS HOT RHI + TS PACK + TEMP bq24278 RLO PACK - Figure 4. TS Circuit 1.0 C 0.5 C Portion of spec not covered by TS Implementation on bq 24278 4.25 V 4.15 V 4.1 V T1 (0C) T2 (10C) T3 T4 (45C) (50C) T5 (60C) Figure 5. Charge Current During TS Conditions To satisfy the JEITA requirements, four temperature thresholds are monitored; the cold battery threshold; the cold battery threshold (TNTC < 0C), the cool battery threshold (0C < TNTC < 10C), the warm battery threshold (45C < TNTC < 60C) and the hot battery threshold (TNTC > 60C). These temperatures correspond to the VCOLD, VCOOL, VWARM, and VHOT thresholds. Charging is suspended and timers are suspended when VTS < VHOT or VTS > VCOLD. When VHOT < VTS < VWARM, the battery regulation voltage is reduced by 140 mV from the programmed regulation threshold. When VCOOL < VTS < VCOLD, the charging current is reduced to half of the programmed charge current. The TS function is voltage based for maximum flexibility. Connect a resistor divider from DRV to GND with TS connected to the center tap to set the threshold. The connections are shown in Figure 10. The resistor values are calculated using the following equations: Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s) :bq24278 15 bq24278 SLUSB04 - JUNE 2012 www.ti.com e 1 1 u VDRV RCOLD RHOT e u V V e COLD HOT u RLO = eV u e V u RHOT e DRV - 1u - RCOLD e DRV - 1u e VHOT u e VCOLD u (3) VDRV -1 VCOLD RHI = 1 1 + RLO RCOLD (4) Where: VCOLD = 0.60 x VDRV VHOT = 0.30 x VDRV Where RHOT is the NTC resistance at the hot temperature and RCOLD is the NTC resistance at cold temperature. The WARM and COOL thresholds are not independently programmable. The COOL and WARM NTC resistances for a selected resistor divider are calculated using the following equations: RLO 0.564 RHI RCOOL = RLO - RLO 0.564 - RHI 0.564 (5) RLO 0.383 RHI RWARM = RLO - RLO 0.383 - RHI 0.383 (6) Thermal Regulation and Protection During the charging process, to prevent the IC from overheating, bq24278 monitor the junction temperature, TJ, of the die and begins to taper down the charge current once TJ reaches the thermal regulation threshold, TCF. The charge current is reduced to zero when the junction temperature increases about 10C above TCF. Once the charge current is reduced, the system current is reduced while the battery supplements the load to supply the system. This may cause a thermal shutdown of the bq24278 if the die temperature rises too high. At any state, if TJ exceeds TSHTDWN, bq24278 suspends charging and disables the buck converter. During thermal shutdown mode, PWM is turned off, and the timer is reset. The charging cycle resets when TJ falls below TSHTDWN by approximately 10C. Input Voltage Protection in Charge Mode Sleep Mode The bq24278 enters the low-power sleep mode if the voltage on VIN falls below sleep-mode entry threshold, VBAT+VSLP, and VVBUS is higher than the undervoltage lockout threshold, VUVLO. This feature prevents draining the battery during the absence of VIN. When VIN < VBAT+ VSLP, the bq24278 turns off the PWM converter, and turns the battery FET and BGATE on. Once VIN > VBAT+ VSLP, the device initiates a new charge cycle. Input Voltage Based DPM During normal charging process, if the input power source is not able to support the programmed or default charging current, the supply voltage decreases. Once the supply drops to VIN_DPM (set by VDPM), the input current limit is reduced down to prevent the further drop of the supply. This feature ensures IC compatibility with adapters with different current capabilities without a hardware change. Figure 6 shows the VIN-DPM behavior to a current limited source. In this figure the input source has a 750mA current limit and the charging is set to 750mA. The SYS load is then increased to 1.2A. 16 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s) :bq24278 bq24278 www.ti.com SLUSB04 - JUNE 2012 Figure 6. bq24278 VIN-DPM The VINDPM threshold for the IN input is set using a resistor divider with VDPM connected to the center tap. Select 10k for the bottom resistor. The top resistor is selected using Equation 7: RTOP = 10kW ( VINDPM - VDPM ) VDPM (7) Where VINDPM is the desired VINDPM threshold and VDPM is the regulation threshold specified in the Electrical Characteristics table. Bad Source Detection When a source is connected to IN, the bq24278 runs a Bad Source Detection procedure to determine if the source is strong enough to provide some current to charge the battery. A current sink is turned on (70mA) for 32ms. If the source is valid after the 32ms (VBADSOURCE < VIN < VOVP), the buck converter starts up and normal operation continues. If the supply voltage falls below VBAD_SOURCE during the detection, the current sink shuts off for 2s and then retries. The detection circuits retries continuously until a valid source is detected after the detection time. If during normal operation the source falls to VBAD_SOURCE, the bq24278 turns off the PWM converter, turns the battery FET on and runs the bad source detection. Once a good source is detected, the device returns to normal operation. Input Over-Voltage Protection The bq24278 provides over-voltage protection on the input that protects downstream circuitry. The built-in input over-voltage protection to protect the device and other components against damage from overvoltage on the input supply (Voltage from VIN to PGND). When VIN > VOVP, the bq24278 turns off the PWM converter, suspends the charging cycle and turns the battery FET on. Once the OVP fault is removed, the device returns to the operation it was in prior to the OVP fault. Status Indicators (CHG, PG) The bq24278 contains two open-drain outputs that signal its status. The PG output indicates that a valid input source is connected to IN. PG is low when (VBAT+VSLP) < VIN < VOVP. When there is no supply connected to the input within this range, PG is high impedance. Table 1 illustrates the PG behavior under different conditions. Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s) :bq24278 17 bq24278 SLUSB04 - JUNE 2012 www.ti.com The CHG output indicates new charge cycles. When a new charge cycle is initiated by CE, toggling High Impedance mode or toggling the input power, CHG goes low and remains low until termination. After termination, CHG remains high impedance until a new charge cycle is initiated. CHG does not go low during recharge cycles. Table 2 illustrates the CHG behavior under different conditions. Connect PG and CHG to the DRV output through an LED for visual indication, or connect through a 100k pullup to the required logic rail for host indication. Table 1. PG Status Indicator CHARGE STATE PG BEHAVIOR VIN < VUVLO High-Impedance VIN < (VBAT+VSLP) High-Impedance (VBAT+VSLP) < VIN < VOVP VIN > VOVP Low High-Impedance Table 2. CHG Status Indicator CHARGE STATE CHG BEHAVIOR Charge in progress Low (first charge cycle) High-Impedance (recharge cycles) Charging suspended by thermal loop Charge Done Recharge Cycle after Termination Timer Fault High-Impedance No Valid Supply, VIN>VOVP or VIN < VSLEEP No Battery Present 18 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s) :bq24278 bq24278 www.ti.com SLUSB04 - JUNE 2012 APPLICATION INFORMATION Output Inductor and Capacitor Selection Guidelines When selecting an inductor, several attributes must be examined to find the right part for the application. First, the inductance value should be selected. The bq24278 is designed to work with 1.5H to 2.2H inductors. The chosen value will have an effect on efficiency and package size. Due to the smaller current ripple, some efficiency gain is reached using the 2.2H inductor, however, due to the physical size of the inductor, this may not be a viable option. The 1.5H inductor provides a good tradeoff between size and efficiency. Once the inductance has been selected, the peak current must be calculated in order to choose the current rating of the inductor. Use Equation 8 to calculate the peak current. ae % o IPEAK = ILOAD(MAX) c 1 + RIPPPLE / 2 e o (8) The inductor selected must have a saturation current rating less than or equal to the calculated IPEAK. Due to the high currents possible with the bq24278, a thermal analysis must also be done for the inductor. Many inductors have 40C temperature rise rating. This is the DC current that will cause a 40C temperature rise above the ambient temperature in the inductor. For this analysis, the typical load current may be used adjusted for the duty cycle of the load transients. For example, if the application requires a 1.5A DC load with peaks at 2.5A 20% of the time, a 40C temperature rise current must be greater than 1.7A: ITEMPRISE = ILOAD + D x)IPEAK - ILOAD) = 1.5 A + 0.2 x (2.5 A - 1.5 A) = 1.7 A (9) The bq24278 provides internal loop compensation. Using this scheme, the bq24278 is stable with 10F to 200F of local capacitance. The capacitance on the SYS rail can be higher if distributed amongst the rail. To reduce the output voltage ripple, a ceramic capacitor with the capacitance between 10F and 47F is recommended for local bypass to SYS. Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s) :bq24278 19 bq24278 SLUSB04 - JUNE 2012 www.ti.com PCB Layout Guidelines It is important to pay special attention to the PCB layout. Figure 7 provides a sample layout for the high current paths of the bq24278. GND PMID BYP BOOT SW PGND ILIM ISET SYS SYS BAT (RGE Package) Figure 7. Recommended bq24278 PCB Layout for RGE Device IN PMID GND SW SW PGND BOOT ILIM SYS BAT ISET PGND SW SYS (YFF Package) Figure 8. Recommended bq24278 PCB Layout for YFF Device The following provides some guidelines: * To obtain optimal performance, the power input capacitors, connected from the PMID input to PGND, must be placed as close as possible to the bq24278 * Place 4.7F input capacitor as close to PMID pin and PGND pin as possible to make high frequency current loop area as small as possible. Place 1F input capacitor GNDs as close to the respective PMID cap GND and PGND pins as possible to minimize the ground difference between the input and PMID. * The local bypass capacitor from SYS to GND should be connected between the SYS pin and PGND of the IC. The intent is to minimize the current path loop area from the SW pin through the LC filter and back to the PGND pin. * Place ISET resistor very close to the ISET pin. * Place ILIM resistor very close to the ILIIM pin. * Place all decoupling capacitor close to their respective IC pin and as close as to PGND (do not place components such that routing interrupts power stage currents). All small control signals should be routed away from the high current paths. * The PCB should have a ground plane (return) connected directly to the return of all components through vias (two vias per capacitor for power-stage capacitors, one via per capacitor for small-signal components). It is 20 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s) :bq24278 bq24278 www.ti.com * * SLUSB04 - JUNE 2012 also recommended to put vias inside the PGND pads for the IC, if possible. A star ground design approach is typically used to keep circuit block currents isolated (high-power/low-power small-signal) which reduces noisecoupling and ground-bounce issues. A single ground plane for this design gives good results. With this small layout and a single ground plane, there is no ground-bounce issue, and having the components segregated minimizes coupling between signals. The high-current charge paths into IN, BAT, SYS and from the SW pins must be sized appropriately for the maximum charge current in order to avoid voltage drops in these traces. The PGND pins should be connected to the ground plane to return current through the internal low-side FET. For high-current applications, the balls for the power paths should be connected to as much copper in the board as possible. This allows better thermal performance as the board pulls heat away from the IC. PACKAGE SUMMARY 1 2 3 4 5 6 7 A IN IN IN IN GND GND GND B PMID PMID PMID PMID BYP BYP BYP C SW SW SW SW SW SW SW D PGN D PGN D PGN D PGN D PGN D PGN D PGN D E ILIM CD VDP M /CE DRV_ S DRV_ S BOO T SYS SYS SYS SYS BGATE /PG DRV BAT BAT BAT BAT TS /CHG ISET TI YMLLLLS bq24278 D F G E 0-Pin A 1 Marker, TI-TI Letters, YM- Year Month Date Code , LLLL-Lot Trace Code , S-Assembly Site Code CHIP SCALE PACKAGING DIMENSIONS The bq 2427x devices are available in a 49-bump chip scale package (YFF, NanoFree TM). The package dimensions are : D - 2.78mm 0.05mm E - 2.78mm 0.05mm Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s) :bq24278 21 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) Top-Side Markings (3) (4) BQ24278RGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ 24278 BQ24278RGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ 24278 BQ24278YFFR ACTIVE DSBGA YFF 49 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 BQ24278 BQ24278YFFT ACTIVE DSBGA YFF 49 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 BQ24278 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 24-Aug-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device BQ24278RGER Package Package Pins Type Drawing VQFN RGE 24 BQ24278RGET VQFN RGE BQ24278YFFR DSBGA YFF BQ24278YFFT DSBGA YFF SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 49 3000 180.0 8.4 2.93 2.93 0.81 4.0 8.0 Q1 49 250 180.0 8.4 2.93 2.93 0.81 4.0 8.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Aug-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) BQ24278RGER VQFN RGE 24 3000 367.0 367.0 35.0 BQ24278RGET VQFN RGE 24 250 210.0 185.0 35.0 BQ24278YFFR DSBGA YFF 49 3000 182.0 182.0 17.0 BQ24278YFFT DSBGA YFF 49 250 182.0 182.0 17.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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