12
Z5U Dielectric
General Specifications
Z5U formulations are “general-purpose” ceramics which are
meant primarily for use in limited temperature applications
where small size and cost are important. Z5U show wide
variations in capacitance under influence of environmental
and electrical operating conditions.
Despite their capacitance instability, Z5U formulations
are very popular because of their small size, low ESL, low
ESR and excellent frequency response. These features are
particularly important for decoupling application where only a
minimum capacitance value is required.
Capacitance Range 0.01 µF to 1.0 µF
Capacitance Tolerances Preferred +80 –20%
others available: ±20%, +100 –0%
Operating Temperature Range +10°C to +85°C
Temperature Characteristic +22% to –56% max.
Voltage Ratings 25 and 50VDC (+85°C)
Dissipation Factor 4% max.
Insulation Resistance (+25°C, RVDC) 10,000 megohms min. or 1000 MΩ- µF min., whichever is less
Dielectric Strength 250% of rated voltage for 5 seconds at 50 mamp max. current
Test Voltage 0.5 ± 0.2 Vrms
Test Frequency 1 KHz
PERFORMANCE CHARACTERISTICS
0805
Size
(L" x W")
5
Voltage
25V = 3
50V = 5
E
Dielectric
Z5U = E
104
Capacitance
Code
Z
Capacitance
Tolerance
Preferred
Z = +80%
–20%
M = ±20%
A
Failure
Rate
A = Not
Applicable
T
Terminations
T = Plated Ni
and Solder
2
Packaging
2 = 7" Reel
4 = 13" Reel
A
Special
Code
A = Std.
Product
PART NUMBER (see page 3 for complete part number explanation)
13
Z5U Dielectric
Typical Characteristic Curves**
% ⌬ Capacitance
+30
0
-10
+10 +25 +30 +40 +50 +55 +65+35 +85
+45
Temperature °C
Temperature Coefficient
+20
+10
-30
-20
-40
-50
-60
% ⌬ Capacitance
-10
0
-20
-30
-40
1KHz 10 KHz 100 KHz 1 MHz 10 MHz
Frequency
⌬ Capacitance vs. Frequency
Insulation Resistance (Ohm-Farads
)
1,000
10,000
100,000
100
0+20 +30 +40 +60 +80
Temperature °C
nsu a
ti
on
R
es
i
s
t
ance vs
T
empera
t
ure
+70
+50
Impedance, ⍀
110
100 1,000
Frequency, MHz
Variation of Impedance with Cap Value
Impedance vs. Frequency
1206 -Z5U
0.10
0.01
1.00
100,000 pF
10,000 pF
100.00
10.00
|Z| (ohms)
10.10.010.001 10 100 1,000
Frequency, MHz
Variation of Impedance with Chip Size
Impedance vs. Frequency
.33 ␮F - Z5U
1
10
0.1
100
1000
Z5U 1206
Z5U 1210
Z5U 1812
|Z| (ohms)
10.10.010.001 10 100 1,000
Frequency, MHz
Variation of Impedance with Ceramic Formulation
Impedance vs. Frequency
.1␮F X7R vs. Z5U
0805
1
10
0.01
0.1
100
10000
1000 X7R 0805
Z5U 0805
SUMMARY OF CAPACITANCE RANGES VS. CHIP SIZE
Style 25V 50V
0603* .01µF - .047µF .01µF - .027µF
0805* .01µF - .12µF .01µF - 0.1µF
1206* .01µF - .33µF .01µF - .33µF
1210* .01µF - .56µF .01µF - .47µF
1808 .01µF - .56µF .01µF - .47µF
1812* .01µF - 1.0µF .01µF - 1.0µF
1825* .01µF - 1.0µF .01µF - 1.0µF
2225 .01µF - 1.0µF .01µF - 1.0µF
* Standard Sizes
** For additional information on performance changes with operating conditions consult AVX’s software SpiCap.
14
SIZE 0603* 0805 1206 1210
Standard Reel Packaging All Paper Paper/Embossed Paper/Embossed Paper/Embossed
(L) Length MM 1.60 ± .15 2.01 ± .20 3.20 ± .20 3.20 ± .20
(in.) (.063 ± .006) (.079 ± .008) (.126 ± .008) (.126 ± .008)
(W) Width MM .81 ± .15 1.25 ± .20 1.60 ± .20 2.50 ± .20
(in.) (.032 ± .006) (.049 ± .008) (.063 ± .008) (.098 ± .008)
(T) Max. Thickness MM .90 1.30 1.50 1.70
(in.) (.035) (.051) (.059) (.067)
(t) Terminal MM .35 ± .15 .50 ± .25 .50 ± .25 .50 ± .25
(in.) (.014 ± .006) (.020 ± .010) (.020 ± .010) (.020 ± .010)
WVDC 25 50 25 50 25 50 25 50
Cap .010
(µF) .012
.015
.018
.022
.027
.033
.039
.047
.056
.068
.082
.10
.12
.15
.18
.22
.27
.33
.39
.47
.56
.68
.82
1.0
1.5
Z5U Dielectric
Capacitance Range
*Reflow soldering only.
NOTES: For low profile chips, see page 19.
PREFERRED SIZES ARE SHADED
= Paper Tape
= Embossed Tape
L
䉲
䉲
䉲
䉲
W
䉲
䉲
䉲
䉲
T
t
15
Z5U Dielectric
Capacitance Range
SIZE 1808* 1812* 1825* 2225*
Standard Reel Packaging All Embossed All Embossed All Embossed All Embossed
(L) Length MM 04.57 ± .25 4.50 ± .30 4.50 ± .30 5.72 ± .25
(in.) (.180 ± .010) (.177 ± .012) (.177 ± .012) (.225 ± .010)
(W) Width MM 2.03 ± .25 3.20 ± .20 6.40 ± .40 6.35 ± .25
(in.) (.080 ± .010) (.126 ± .008) (.252 ± .016) (.250 ± .010)
(T) Max. Thickness MM 1.52 1.70 1.70 1.70
(in.) (.060) (.067) (.067) (.067)
(t) Terminal MM .64 ± .39 .61 ± .36 .61 ± .36 .64 ± .39
(in.) (.025 ± .015) (.024 ± .014) (.024 ± .014) (.025 ± .015)
WVDC 25 50 25 50 25 50 25 50
Cap .010
(µF) .012
.015
.018
.022
.027
.033
.039
.047
.056
.068
.082
.10
.12
.15
.18
.22
.27
.33
.39
.47
.56
.68
.82
1.0
1.5
PREFERRED SIZES ARE SHADED
= Paper Tape
= Embossed Tape
L
䉲
䉲
䉲
䉲
W
䉲
䉲
䉲
䉲
T
t
*Reflow soldering only.
NOTES: For low profile chips, see page 19.
2
I. Capacitance (farads)
English: C = .224 K A
TD
Metric: C = .0884 K A
TD
II. Energy stored in capacitors (Joules, watt - sec)
E = 1⁄2 CV2
III. Linear charge of a capacitor (Amperes)
I = C dV
dt
IV. Total Impedance of a capacitor (ohms)
Z = R2
S + (XC- XL)2
V. Capacitive Reactance (ohms)
xc=1
2 πfC
VI. Inductive Reactance (ohms)
xL= 2 πfL
VII. Phase Angles:
Ideal Capacitors: Current leads voltage 90°
Ideal Inductors: Current lags voltage 90°
Ideal Resistors: Current in phase with voltage
VIII. Dissipation Factor (%)
D.F.= tan ␦(loss angle) = E.S.R. = (2 πfC) (E.S.R.)
Xc
IX. Power Factor (%)
P.F. = Sine ␦(loss angle) = Cos f(phase angle)
P.F. = (when less than 10%) = DF
X. Quality Factor (dimensionless)
Q = Cotan ␦(loss angle) = 1
D.F.
XI. Equivalent Series Resistance (ohms)
E.S.R. = (D.F.) (Xc) = (D.F.) / (2 πfC)
XII. Power Loss (watts)
Power Loss = (2 πfCV2) (D.F.)
XIII. KVA (Kilowatts)
KVA = 2 πfCV2x 10-3
XIV. Temperature Characteristic (ppm/°C)
T.C. = Ct – C25 x 106
C25 (Tt– 25)
XV. Cap Drift (%)
C.D. = C1– C2x 100
C1
XVI. Reliability of Ceramic Capacitors
L0=VtXT
tY
Lt(Vo )(
To )
XVII. Capacitors in Series (current the same)
Any Number: 1 = 1 + 1 --- 1
CTC1C2CN
C1C2
Two: CT=C1+ C2
XVIII. Capacitors in Parallel (voltage the same)
CT= C1+ C2--- + CN
XIX. Aging Rate
A.R. = %DC/decade of time
XX. Decibels
db = 20 log V1
V2
冑
Pico X 10-12
Nano X 10-9
Micro X 10-6
Milli X 10-3
Deci X 10-1
Deca X 10+1
Kilo X 10+3
Mega X 10+6
Giga X 10+9
Tera X 10+12
K = Dielectric Constant f = frequency Lt= Test life
A = Area L = Inductance Vt= Test voltage
TD= Dielectric thickness ␦= Loss angle Vo= Operating voltage
V = Voltage f= Phase angle Tt= Test temperature
t = time X & Y = exponent effect of voltage and temp. To= Operating temperature
Rs= Series Resistance Lo= Operating life
METRIC PREFIXES SYMBOLS
Basic Capacitor Formulas
3
How to Order
Part Number Explanation
EXAMPLE: 08055A101JAT2A
0805
Size
(L" x W")
0402
0504
0603
0805
1005
0907
1206
1210
1505
1805
1808
1812
1825
2225
3640
5
Voltage
10V = Z
16V = Y
25V = 3
50V = 5
100V = 1
200V = 2
250V = V
500V = 7
600V = C
1000V = A
1500V = S
2000V = G
2500V = W
3000V = H
4000V = J
5000V = K
A
Dielectric
C0G (NP0) = A
X7R = C
X5R = D
Z5U = E
Y5V = G
101
Capacitance
Code
(2 significant
digits + no. of
zeros)
Examples:
J
Capacitance
Tolerance
A
Failure
Rate
A = Not
Applicable
T
Terminations
2A
Special**
Code
10 pF = 100
100 pF = 101
1,000 pF = 102
22,000 pF = 223
220,000 pF = 224
1 µF = 105
C = ±.25 pF*
D = ±.50 pF*
F = ±1% (≥25 pF)
G = ±2% (≥13 pF)
J = ±5%
K = ±10%
M = ±20%
Z = +80%, -20%
P = +100%, -0%
Others:
7 = Bulk Cassette
9 = Bulk
*C&D tolerances for ⱕ10 pF values.
** Standard Tape and Reel material depends upon chip size and thickness.
See individual part tables for tape material type for each capacitance value.
Note: Unmarked product is standard. Marked product is available on special request, please contact AVX.
Standard packaging is shown in the individual tables.
Non-standard packaging is available on special request, please contact AVX.
Standard:
T = Ni and Tin
Plated
A = Standard
Product
Non-Standard
P = Embossed
unmarked
M = Embossed
marked
E = Standard
packaging
marked
Low Profile
Chips Only
Max. Thickness
T = .66mm (.026")
S = .56mm (.022")
R = .46mm (.018")
For values below 10 pF,
use “R” in place of
decimal point, e.g., 9.1
pfd = 9R1.
Recommended:
2 =7" Reel
4 =13" Reel
Others:
7 = Plated Ni
Gold Plated
1 = Pd/Ag
Packaging**
22
Specification
Appearance
No visual defects
Capacitance Variation
C0G (NP0): ± 2.5% or ± .25pF, whichever is greater
X7R: ≤± 7.5%
Z5U: ≤± 20%
Y5V: ≤± 20%
Q, Tan Delta
To meet initial requirement
Insulation Resistance
C0G (NP0), X7R: To meet initial requirement
Z5U, Y5V: ≥Initial Value x 0.1
Dielectric Strength
No problem observed
Measuring Conditions
Step Temperature °C Time (minutes)
1+65 +5/-0 15 ± 2
Pure Water
20 ± 3 15 ± 2
NaCl solution
Repeat cycle 2 times and wash with water and dry.
Store at room temperature for 48 ± 4 hours (24 hours for
C0G (NP0)) and measure.
General Specifications
Environmental
Specification
Appearance
No visual defects
Capacitance Variation
C0G (NP0): ± 2.5% or ± .25pF, whichever is greater
X7R: ≤± 7.5%
Z5U: ≤± 20%
Y5V: ≤± 20%
Q, Tan Delta
To meet initial requirement
Insulation Resistance
C0G (NP0), X7R: To meet initial requirement
Z5U, Y5V: ≥Initial Value x 0.1
Dielectric Strength
No problem observed
Measuring Conditions
Step Temperature °C Time (minutes)
C0G (NP0), X7R: -55° ± 2°
1 Z5U: +10° ± 2° 30 ± 3
Y5V: -30° ± 2°
2 Room Temperature # 3
3C0G (NP0), X7R: +125° ± 2° 30 ± 3
Z5U, Y5V: +85° ± 2°
4 Room Temperature # 3
Repeat for 5 cycles and measure after 48 hours ± 4 hours
(24 hours for C0G (NP0)) at room temperature.
THERMAL SHOCK
IMMERSION
MOISTURE RESISTANCE
Specification
Appearance
No visual defects
Capacitance Variation
C0G (NP0): ± 5% or ± .5pF, whichever is greater
X7R: ≤± 10%
Z5U: ≤± 30%
Y5V: ≤± 30%
Q, Tan Delta
C0G (NP0):≥30pF........................Q ≥350
≥10pF, < 30pF...........Q ≥275+5C/2
< 10pF ........................Q ≥200+10C
X7R: Initial requirement + .5%
Z5U: Initial requirement + 1%
Y5V: Initial requirement + 2%
Insulation Resistance
≥Initial Value x 0.3
Measuring Conditions
Step Temp. °C Humidity % Time (hrs)
1 +25->+65 90-98 2.5
2 +65 90-98 3.0
3 +65->+25 80-98 2.5
4 +25->+65 90-98 2.5
5 +65 90-98 3.0
6 +65->+25 80-98 2.5
7 +25 90-98 2.0
7a -10 uncontrolled –
7b +25 90-98 –
Repeat 20 cycles (1-7) and store for 48 hours (24 hours
for C0G (NP0)) at room temperature before measuring.
Steps 7a & 7b are done on any 5 out of first 9 cycles.
23
General Specifications
Environmental
Specification
Appearance
No visual defects
Capacitance Variation
C0G (NP0): ± 5% or ± .5pF, whichever is greater
X7R: ≤± 10%
Z5U: ≤± 30%
Y5V: ≤± 30%
Q, Tan Delta
C0G (NP0): ≥30pF......................Q ≥350
≥10pF, < 30pF.........Q ≥275+5C/2
< 10pF ....................Q ≥200+10C
X7R: Initial requirement + .5%
Z5U: Initial requirement + 1%
Y5V: Initial requirement + 2%
Insulation Resistance
≥Initial Value x 0.3
Measuring Conditions
Store at 85 ± 5% relative humidity and 85°C for 1000
hours, without voltage. Remove from test chamber
and stabilize at room temperature and humidity for
48 ± 4 hours (24 ±2 hours for C0G (NP0)) before
measuring.
Charge and discharge currents must be less than
50ma.
STEADY STATE HUMIDITY
(No Load)
Specification
Appearance
No visual defects
Capacitance Variation
C0G (NP0): ± 5% or ± .5pF, whichever is greater
X7R: ≤± 10%
Z5U: ≤± 30%
Y5V: ≤± 30%
Q, Tan Delta
C0G (NP0): ≥30pF .....................Q ≥350
≥10pF,< 30pF.........Q ≥275+5C/2
< 10pF ....................Q ≥200+10C
X7R: Initial requirement + .5%
Z5U: Initial requirement + 1%
Y5V: Initial requirement + 2%
LOAD HUMIDITY
Specification
Appearance
No visual defects
Capacitance Variation
C0G (NP0): ± 3% or ± .3pF, whichever is greater
X7R: ≤± 10%
Z5U: ≤± 30%
Y5V: ≤± 30%
Q, Tan Delta
C0G (NP0): ≥30pF......................Q ≥350
≥10pF, < 30pF.........Q ≥275+5C/2
< 10pF ....................Q ≥200+10C
X7R: Initial requirement + .5%
Z5U: Initial requirement + 1%
Y5V: Initial requirement + 2%
Insulation Resistance
C0G (NP0), X7R: To meet initial value x 0.3
Z5U, Y5V: ≥Initial Value x 0.1
Charge devices with twice rated voltage in test
chamber set at +125°C ± 2°C for C0G (NP0) and X7R,
+85° ± 2°C for Z5U, and Y5V for 1000 (+48,-0) hours.
Remove from test chamber and stabilize at room
temperature for 48 ± 4 hours (24 ±2 hours for C0G
(NP0)) before measuring.
Charge and discharge currents must be less than
50ma.
LOAD LIFE
Insulation Resistance
C0G (NP0), X7R: To meet initial value x 0.3
Z5U, Y5V: ≥Initial Value x 0.1
Charge devices with rated voltage in test chamber set
at 85 ± 5% relative humidity and 85°C for 1000
(+48,-0) hours. Remove from test chamber and
stabilize at room temperature and humidity for 48 ± 4
hours (24 ±2 hours for C0G (NP0)) before measuring.
Charge and discharge currents must be less than
50ma.
24
General Specifications
Mechanical
Specification
No evidence of peeling of end terminal
Measuring Conditions
After soldering devices to circuit board apply 5N
(0.51kg f) for 10 ± 1 seconds, please refer to Figure 1.
Specification
Appearance:
No visual defects
Capacitance
Within specified tolerance
Q, Tan Delta
To meet initial requirement
Insulation Resistance
C0G (NP0), X7R ⱖInitial Value x 0.3
Z5U, Y5V ⱖInitial Value x 0.1
Measuring Conditions
Vibration Frequency
10-2000 Hz
Maximum Acceleration
20G
Swing Width
1.5mm
Test Time
X, Y, Z axis for 2 hours each, total 6 hours of test
END TERMINATION ADHERENCE
RESISTANCE TO VIBRATION
Specification
ⱖ95% of each termination end should be covered with
fresh solder
Measuring Conditions
Dip device in eutectic solder at 230 ± 5°C for
2 ± .5 seconds
Figure 2. Bend Strength
Figure 1.
Terminal Adhesion
SOLDERABILITY
Specification
Appearance:
No visual defects
Capacitance Variation
C0G (NP0): ± 5% or ± .5pF, whichever is larger
X7R: ≤± 12%
Z5U: ≤± 30%
Y5V: ≤± 30%
Insulation Resistance
C0G (NP0): ≥Initial Value x 0.3
X7R: ≥Initial Value x 0.3
Z5U: ≥Initial Value x 0.1
Y5V: ≥Initial Value x 0.1
Measuring Conditions
Please refer to Figure 2
Deflection:
2mm
Test Time:
30 seconds
BEND STRENGTH
Specification
Appearance:
No serious defects, <25% leaching of either end
terminal
Capacitance Variation
C0G (NP0): ± 2.5% or ± 2.5pF, whichever is greater
X7R: ≤± 7.5%
Z5U: ≤± 20%
Y5V: ≤± 20%
Q, Tan Delta
To meet initial requirement
Insulation Resistance
To meet initial requirement
Dielectric Strength
No problem observed
Measuring Conditions
Dip device in eutectic solder at 260°C, for 1 minute.
Store at room temperature for 48 hours (24 hours for
C0G (NP0)) before measuring electrical parameters.
Part sizes larger than 3.20mm x 2.49mm are reheated
at 150°C for 30 ±5 seconds before performing test.
RESISTANCE TO SOLDER HEAT
Speed = 1mm/sec
R340mm
Supports
2mm
Deflection
45mm 45mm
5N FORCE
DEVICE UNDER TEST
TEST BOARD
31
0805
Size
(L" x W")
5
Voltage
50V = 5
100V = 1
200V = 2
C
Dielectric
1B CG = A
2R1 = C
2F4 = G
103
Capacitance
Code
M
Capacitance
Tolerance
See Dielectrics
C0G, X7R, Y5V
T
Specification
CECC32101-801
T
Terminations
T = Plated Ni
and Sn
2
Marking
Packaging
2 = 7" Reel
4 = 13" Reel
A
Special
Code
A = Std.
Product
PART NUMBER (example)
RANGE OF APPROVED COMPONENTS
Case Dielectric Voltage and Capacitance Range
Size Type 50V 100V 200V
1BCG
0603 1B CG 0.47pF - 150pF 0.47pF - 120pF 0.47pF - 100pF
0805 1B CG 0.47pF - 560pF 0.47pF - 560pF 0.47pF - 330pF
1206 1B CG 0.47pF - 3.3nF 0.47pF - 3.3nF 0.47pF - 1.5nF
1210 1B CG 0.47pF - 4.7nF 0.47pF - 4.7nF 0.47pF - 2.7nF
1808 1B CG 0.47pF - 6.8nF 0.47pF - 6.8nF 0.47pF - 4.7nF
1812 1B CG 0.47pF - 15nF 0.47pF - 15nF 0.47pF - 10nF
2220 1B CG 0.47pF - 39nF 0.47pF - 39nF 0.47pF - 15nF
2R1
0603 2R1 10pF - 6.8nF 10pF - 6.8nF 10pF - 1.2nF
0805 2R1 10pF - 33nF 10pF - 18nF 10pF - 3.3nF
1206 2R1 10pF - 100nF 10pF - 68nF 10pF - 18nF
1210 2R1 10pF - 150nF 10pF - 100nF 10pF - 27nF
1808 2R1 10pF - 270nF 10pF - 180nF 10pF - 47nF
1812 2R1 10pF - 470nF 10pF - 330nF 10pF - 100nF
2220 2R1 10pF - 1.2µF 10pF - 680nF 10pF - 220nF
2F4
0805 2F4 10pF - 100nF
1206 2F4 10pF - 330nF
1210 2F4 10pF - 470nF
1808 2F4 10pF - 560nF
1812 2F4 10pF - 1.8µF
2220 2F4 10pF - 2.2µF
European Detail Specifications
CECC 32 101-801/Chips
Standard European Ceramic Chip Capacitors
32
Packaging of Chip Components
Automatic Insertion Packaging
TAPE & REEL QUANTITIES
All tape and reel specifications are in compliance with RS481.
8mm 12mm
Paper or Embossed Carrier 0805, 1005, 1206,
1210
Embossed Only 0504, 0907 1505, 1805, 1812, 1825
1808 2220, 2225
Paper Only 0402, 0603
Qty. per Reel/7" Reel 2,000 or 4,000(1) 3,000 1,000
Qty. per Reel/13" Reel 10,000 10,000 4,000
(1) Dependent on chip thickness. Low profile chips shown on page 27 are 5,000 per reel for 7" reel. 0402 size chips are 10,000 per 7" reels and are
not available on 13" reels. For 3640 size chip contact factory for quantity per reel.
REEL DIMENSIONS
Tape A B* CD* N W1W2W3
Size(1) Max. Min. Min. Min. Max.
+1.0 7.9 Min.
8mm 8.4 –0.0 14.4 (.311)
(.331 +.060 ) (.567) 10.9 Max.
330 1.5 13.0±0.20 20.2 50
–0.0 (.429)
(12.992) (.059) (.512±.008) (.795) (1.969)
+2.0 11.9 Min.
12mm 12.4 –0.0 18.4 (.469)
(.488 +.076) (.724) 15.4 Max.
–0.0 (.607)
Metric dimensions will govern.
English measurements rounded and for reference only.
(1) For tape sizes 16mm and 24mm (used with chip size 3640) consult EIA RS-481 latest revision.
33
Tape Size B1D1FP
1RT
2WA
0 B0 K0
Max. Min. Min.
See Note 6 See Note 5 See Note 2
8mm 4.55 1.0 3.5 ± 0.05 4.0 ± 0.10 25 2.5 Max See Note 1
(.179) (.039) (.138 ± .002) (.157 ± .004) (.984) (.098)
12mm 8.2 1.5 5.5 ± 0.05 4.0 ± 0.10 30 6.5 Max. 12.0 ± .30 See Note 1
(.323) (.059) (.217 ± .002) (.157 ± .004) (1.181) (.256) (.472 ± .012)
8mm 4.55 1.0 3.5 ± 0.05 2.0 ± 0.10 25 2.5 Max. See Note 1
1/2 Pitch (.179) (.039) (.138 ± .002) 0.79 ± .004 (.984) (.098)
12mm 8.2 1.5 5.5 ± 0.05 8.0 ± 0.10 30 6.5 Max. 12.0 ± .30 See Note 1
Double (.323) (.059) (.217 ± .002) (.315 ± .004) (1.181) (.256) (.472 ± .012)
Pitch
Embossed Carrier Configuration
8 & 12mm Tape Only
8 & 12mm Embossed Tape
Metric Dimensions Will Govern
CONSTANT DIMENSIONS
Tape Size D0EP
0P2T Max. T1G1G2
8mm 8.4 +0.10 1.75 ± 0.10 4.0 ± 0.10 2.0 ± 0.05 0.600 0.10 0.75 0.75-0.0
and (.059 +.004) (.069 ± .004) (.157 ± .004) (.079 ± .002) (.024) (.004) (.030) (.030)
12mm -0.0 Max. Min. Min.
See Note 3 See Note 4
VARIABLE DIMENSIONS
NOTES:
1. A0, B0, and K0are determined by the max. dimensions to the ends of the terminals extending from the component body and/or the body dimensions of the component. The
clearance between the end of the terminals or body of the component to the sides and depth of the cavity (A0, B0, and K0) must be within 0.05 mm (.002) min. and 0.50 mm
(.020) max. The clearance allowed must also prevent rotation of the component within the cavity of not more than 20 degrees (see sketches C & D).
2. Tape with components shall pass around radius “R” without damage. The minimum trailer length (Note 2 Fig. 3) may require additional length to provide R min. for 12 mm
embossed tape for reels with hub diameters approaching N min. (Table 4).
3. G1dimension is the flat area from the edge of the sprocket hole to either the outward deformation of the carrier tape between the embossed cavities or to the edge of the
cavity whichever is less.
4. G2dimension is the flat area from the edge of the carrier tape opposite the sprocket holes to either the outward deformation of the carrier tape between the embossed cavity
or to the edge of the cavity whichever is less.
5. The embossment hole location shall be measured from the sprocket hole controlling the location of the embossment.
Dimensions of embossment location and hole location shall be applied independent of each other.
6. B1dimension is a reference dimension for tape feeder clearance only.
8.0 +0.3
-0.1
(.315 +.012 )-.004
8.0 +0.3
-0.1
(.315 +.012 )-.004
Tape Size P1FWA
0 B0T
8mm 4.0 ± 0.10 3.5 ± 0.05 See Note 1 See Note 3
(.157 ± .004) (.138 ± .002)
12mm 4.0 ± .010 5.5 ± 0.05 12.0 ± 0.3
(.157 ± .004) (.217 ± .002) (.472 ± .012)
8mm 2.0 ± 0.10 3.5 ± 0.05
1/2 Pitch (.079 ± .004) (.138 ± .002)
12mm 8.0 ± 0.10 5.5 ± 0.05 12.0 ± 0.3
Double (.315 ± .004) (.217 ± .002) (.472 ± .012)
Pitch
34
Paper Carrier Configuration
8 & 12mm Tape Only
8 & 12mm Paper Tape
Metric Dimensions Will Govern
CONSTANT DIMENSIONS
Tape Size D0EP
0P2T1G1G2R MIN.
8mm 1.5 +0.1 1.75 ± 0.10 4.0 ± 0.10 2.0 ± 0.05 0.10 0.75 0.75 25 (.984)-0.0
and (.059 +.004) (.069 ± .004) (.157 ± .004) (.079 ± .002) (.004) (.030) (.030) See Note 2
12mm -.000 Max. Min. Min.
VARIABLE DIMENSIONS
NOTES:
1. A0, B0, and T are determined by the max. dimensions to the ends of the terminals extending from the component body and/or the body dimensions of the component. The
clearance between the ends of the terminals or body of the component to the sides and depth of the cavity (A0, B0, and T) must be within 0.05 mm (.002) min. and 0.50 mm
(.020) max. The clearance allowed must also prevent rotation of the component within the cavity of not more than 20 degrees (see sketches A & B).
2. Tape with components shall pass around radius “R” without damage.
3. 1.1 mm (.043) Base Tape and 1.6 mm (.063) Max. for Non-Paper Base Compositions.
8.0 +0.3
-0.1
(.315 +.012 )-.004
8.0 +0.3
-0.1
(.315 +.012 )-.004
Bar Code Labeling Standard
AVX bar code labeling is available and follows latest version of EIA-556-A.
35
Bulk Case Packaging
CASE QUANTITIES
Part Size 0402 0603 0805
Qty. 10,000 (T=0.6mm)
(pcs / cassette) 80,000 15,000 5,000 (T¯≥0.6mm)
BENEFITS BULK FEEDER
• Easier handling
• Smaller packaging volume
(1/20 of T/R packaging)
• Easier inventory control
• Flexibility
• Recyclable
CASE DIMENSIONS
Shutter
Slider
Attachment Base
110mm
12mm
36mm
Case
Cassette
Gate
Shooter
Chips
Expanded Drawing Mounter
Head
36
General Description
Formulations – Multilayer ceramic capacitors are available
in both Class 1 and Class 2 formulations. Temperature
compensating formulation are Class 1 and temperature
stable and general application formulations are classified
as Class 2.
Class 1 – Class 1 capacitors or temperature compensating
capacitors are usually made from mixtures of titanates
where barium titanate is normally not a major part of the
mix. They have predictable temperature coefficients and
in general, do not have an aging characteristic. Thus they
are the most stable capacitor available. The most popular
Class 1 multilayer ceramic capacitors are C0G (NP0)
temperature compensating capacitors (negative-positive
0 ppm/°C).
Class 2 – EIA Class 2 capacitors typically are based on the
chemistry of barium titanate and provide a wide range of
capacitance values and temperature stability. The most
commonly used Class 2 dielectrics are X7R and Y5V. The
X7R provides intermediate capacitance values which vary
only ±15% over the temperature range of -55°C to 125°C. It
finds applications where stability over a wide temperature
range is required.
The Y5V provides the highest capacitance values and is
used in applications where limited temperature changes are
expected. The capacitance value for Y5V can vary from
22% to -82% over the -30°C to 85°C temperature range.
The Z5U dielectric is between X7R and Y5V in both stability
and capacitance range.
All Class 2 capacitors vary in capacitance value under the
influence of temperature, operating voltage (both AC and
DC), and frequency. For additional information on perfor-
mance changes with operating conditions, consult AVX’s
software, SpiCap.
Basic Construction – A multilayer ceramic (MLC) capaci-
tor is a monolithic block of ceramic containing two sets of
offset, interleaved planar electrodes that extend to two
opposite surfaces of the ceramic dielectric. This simple
structure requires a considerable amount of sophistication,
both in material and manufacture, to produce it in the quality
and quantities needed in today’s electronic equipment.
Ceramic Layer Electrode
Terminated
Edge
Terminated
Edge
End Terminations
Margin Electrodes
37
General Description
Effects of Voltage – Variations in voltage have little effect
on Class 1 dielectric but does affect the capacitance and
dissipation factor of Class 2 dielectrics. The application of
DC voltage reduces both the capacitance and dissipation
factor while the application of an AC voltage within a
reasonable range tends to increase both capacitance and
dissipation factor readings. If a high enough AC voltage is
applied, eventually it will reduce capacitance just as a DC
voltage will. Figure 2 shows the effects of AC voltage.
Capacitor specifications specify the AC voltage at which to
measure (normally 0.5 or 1 VAC) and application of the
wrong voltage can cause spurious readings. Figure 3 gives
the voltage coefficient of dissipation factor for various AC
voltages at 1 kilohertz. Applications of different frequencies
will affect the percentage changes versus voltages.
The effect of the application of DC voltage is shown in
Figure 4. The voltage coefficient is more pronounced for
higher K dielectrics. These figures are shown for room tem-
perature conditions. The combination characteristic known
as voltage temperature limits which shows the effects of
rated voltage over the operating temperature range is
shown in Figure 5 for the military BX characteristic.
Cap. Change vs. D.C. Volts
AVX X7R T.C.
Typical Cap. Change vs. Temperature
AVX X7R T.C.
Effects of Time – Class 2 ceramic capacitors change
capacitance and dissipation factor with time as well as tem-
perature, voltage and frequency. This change with time is
known as aging. Aging is caused by a gradual re-alignment
of the crystalline structure of the ceramic and produces an
exponential loss in capacitance and decrease in dissipation
factor versus time. A typical curve of aging rate for semi-
stable ceramics is shown in Figure 6.
If a Class 2 ceramic capacitor that has been sitting on the
shelf for a period of time, is heated above its curie point,
(125°C for 4 hours or 150°C for 1⁄2hour will suffice) the part
will de-age and return to its initial capacitance and dissi-
pation factor readings. Because the capacitance changes
rapidly, immediately after de-aging, the basic capacitance
measurements are normally referred to a time period some-
time after the de-aging process. Various manufacturers use
different time bases but the most popular one is one day
or twenty-four hours after “last heat.” Change in the aging
curve can be caused by the application of voltage and
other stresses. The possible changes in capacitance due to
de-aging by heating the unit explain why capacitance
changes are allowed after test, such as temperature cycling,
moisture resistance, etc., in MIL specs. The application of
high voltages such as dielectric withstanding voltages also
25% 50% 75% 100%
Percent Rated Volts
Capacitance Change Percent
2.5
0
-2.5
-5
-7.5
-10
0VDC
RVDC
-55 -35 -15 +5 +25 +45 +65 +85 +105 +125
Temperature Degrees Centigrade
Capacitance Change Percent
+20
+10
0
-10
-20
-30
Figure 2
50
40
30
20
10
0 12.5 25 37.5 50
Volts AC at 1.0 KHz
Capacitance Change Percent
Cap. Change vs. A.C. Volts
AVX X7R T.C.
Figure 3
Curve 3 - 25 VDC Rated Capacitor
Curve 2 - 50 VDC Rated Capacitor
Curve 1 - 100 VDC Rated Capacitor Curve 3
Curve 2
Curve 1
.5 1.0 1.5 2.0 2.5
AC Measurement Volts at 1.0 KHz
Dissipation Factor Percent
10.0
8.0
6.0
4.0
2.0
0
D.F. vs. A.C. Measurement Volts
AVX X7R T.C.
Figure 4
Figure 5
tends to de-age capacitors and is why re-reading of capac-
itance after 12 or 24 hours is allowed in military specifica-
tions after dielectric strength tests have been performed.
Effects of Frequency – Frequency affects capacitance
and impedance characteristics of capacitors. This effect is
much more pronounced in high dielectric constant ceramic
formulation that is low K formulations. AVX’s SpiCap soft-
ware generates impedance, ESR, series inductance, series
resonant frequency and capacitance all as functions of fre-
quency, temperature and DC bias for standard chip sizes
and styles. It is available free from AVX.
Effects of Mechanical Stress – High “K” dielectric
ceramic capacitors exhibit some low level piezoelectric
reactions under mechanical stress. As a general statement,
the piezoelectric output is higher, the higher the dielectric
constant of the ceramic. It is desirable to investigate this
effect before using high “K” dielectrics as coupling capaci-
tors in extremely low level applications.
Reliability – Historically ceramic capacitors have been one
of the most reliable types of capacitors in use today.
The approximate formula for the reliability of a ceramic
capacitor is:
Lo=VtXTtY
LtVoTo
where
Lo= operating life Tt= test temperature and
Lt= test life To= operating temperature
Vt= test voltage in °C
Vo= operating voltage X,Y = see text
Historically for ceramic capacitors exponent X has been
considered as 3. The exponent Y for temperature effects
typically tends to run about 8.
A capacitor is a component which is capable of storing
electrical energy. It consists of two conductive plates (elec-
trodes) separated by insulating material which is called the
dielectric. A typical formula for determining capacitance is:
C = .224 KA
t
C= capacitance (picofarads)
K= dielectric constant (Vacuum = 1)
A= area in square inches
t= separation between the plates in inches
(thickness of dielectric)
.224 = conversion constant
(.0884 for metric system in cm)
Capacitance – The standard unit of capacitance is the
farad. A capacitor has a capacitance of 1 farad when 1
coulomb charges it to 1 volt. One farad is a very large unit
and most capacitors have values in the micro (10-6), nano
(10-9) or pico (10-12) farad level.
Dielectric Constant – In the formula for capacitance given
above the dielectric constant of a vacuum is arbitrarily cho-
sen as the number 1. Dielectric constants of other materials
are then compared to the dielectric constant of a vacuum.
Dielectric Thickness – Capacitance is indirectly propor-
tional to the separation between electrodes. Lower voltage
requirements mean thinner dielectrics and greater capaci-
tance per volume.
Area – Capacitance is directly proportional to the area of
the electrodes. Since the other variables in the equation are
usually set by the performance desired, area is the easiest
parameter to modify to obtain a specific capacitance within
a material group.
38
1 10 100 1000 10,000 100,000
Hours
Capacitance Change Percent
+1.5
0
-1.5
-3.0
-4.5
-6.0
-7.5
Characteristic Max. Aging Rate %/Decade
C0G (NP0)
X7R
Z5U
Y5V
None
2
3
5
Figure 6
Typical Curve of Aging Rate
X7R Dielectric
共
共
共
共
General Description
39
General Description
Energy Stored – The energy which can be stored in a
capacitor is given by the formula:
E= 1⁄2CV2
E= energy in joules (watts-sec)
V= applied voltage
C= capacitance in farads
Potential Change – A capacitor is a reactive component
which reacts against a change in potential across it. This is
shown by the equation for the linear charge of a capacitor:
Iideal = C dV
dt
where
I= Current
C= Capacitance
dV/dt = Slope of voltage transition across capacitor
Thus an infinite current would be required to instantly
change the potential across a capacitor. The amount of
current a capacitor can “sink” is determined by the above
equation.
Equivalent Circuit – A capacitor, as a practical device,
exhibits not only capacitance but also resistance and induc-
tance. A simplified schematic for the equivalent circuit is:
C= Capacitance L = Inductance
Rs= Series Resistance Rp= Parallel Resistance
Reactance – Since the insulation resistance (Rp) is normally
very high, the total impedance of a capacitor is:
Z = R2
S+ (XC - XL)2
where
Z= Total Impedance
Rs= Series Resistance
XC= Capacitive Reactance = 1
2πfC
XL= Inductive Reactance = 2 πfL
The variation of a capacitor’s impedance with frequency
determines its effectiveness in many applications.
Phase Angle – Power Factor and Dissipation Factor are
often confused since they are both measures of the loss in a
capacitor under AC application and are often almost identi-
cal in value. In a “perfect” capacitor the current in the
capacitor will lead the voltage by 90°.
In practice the current leads the voltage by some other
phase angle due to the series resistance RS. The comple-
ment of this angle is called the loss angle and:
Power Factor (P.F.) = Cos for Sine ␦
Dissipation Factor (D.F.) = tan ␦
for small values of ␦the tan and sine are essentially equal
which has led to the common interchangeability of the two
terms in the industry.
Equivalent Series Resistance – The term E.S.R. or
Equivalent Series Resistance combines all losses both
series and parallel in a capacitor at a given frequency so
that the equivalent circuit is reduced to a simple R-C series
connection.
Dissipation Factor – The DF/PF of a capacitor tells what
percent of the apparent power input will turn to heat in the
capacitor.
Dissipation Factor =E.S.R. = (2 πfC) (E.S.R.)
XC
The watts loss are:
Watts loss = (2 πfCV2) (D.F.)
Very low values of dissipation factor are expressed as their
reciprocal for convenience. These are called the “Q” or
Quality factor of capacitors.
Parasitic Inductance – The parasitic inductance of capac-
itors is becoming more and more important in the decou-
pling of today’s high speed digital systems. The relationship
between the inductance and the ripple voltage induced on
the DC voltage line can be seen from the simple inductance
equation:
V = L di
dt
R
LR
C
P
S
冑
␦
I (Ideal) I (Actual)
Phase
Angle
Loss
Angle
V
IRs
f
E.S.R. C
40
The seen in current microprocessors can be as high as
0.3 A/ns, and up to 10A/ns. At 0.3 A/ns, 100pH of parasitic
inductance can cause a voltage spike of 30mV. While this
does not sound very drastic, with the Vcc for microproces-
sors decreasing at the current rate, this can be a fairly large
percentage.
Another important, often overlooked, reason for knowing
the parasitic inductance is the calculation of the resonant
frequency. This can be important for high frequency, by-
pass capacitors, as the resonant point will give the most
signal attenuation. The resonant frequency is calculated
from the simple equation:
fres = 1
2␲LC
Insulation Resistance – Insulation Resistance is the resis-
tance measured across the terminals of a capacitor and
consists principally of the parallel resistance RPshown in
the equivalent circuit. As capacitance values and hence the
area of dielectric increases, the I.R. decreases and hence
the product (C x IR or RC) is often specified in ohm farads
or more commonly megohm-microfarads. Leakage current
is determined by dividing the rated voltage by IR (Ohm’s
Law).
Dielectric Strength – Dielectric Strength is an expression
of the ability of a material to withstand an electrical stress.
Although dielectric strength is ordinarily expressed in volts, it
is actually dependent on the thickness of the dielectric and
thus is also more generically a function of volts/mil.
Dielectric Absorption – A capacitor does not discharge
instantaneously upon application of a short circuit, but
drains gradually after the capacitance proper has been dis-
charged. It is common practice to measure the dielectric
absorption by determining the “reappearing voltage” which
appears across a capacitor at some point in time after it has
been fully discharged under short circuit conditions.
Corona – Corona is the ionization of air or other vapors
which causes them to conduct current. It is especially
prevalent in high voltage units but can occur with low voltages
as well where high voltage gradients occur. The energy
discharged degrades the performance of the capacitor and
can in time cause catastrophic failures.
di
dt
General Description
冑
41
Surface Mounting Guide
MLC Chip Capacitors
Component Pad Design
Component pads should be designed to achieve good sol-
der filets and minimize component movement during reflow
soldering. Pad designs are given below for the most com-
mon sizes of multilayer ceramic capacitors for both wave
and reflow soldering. The basis of these designs is:
• Pad width equal to component width. It is permissible to
decrease this to as low as 85% of component width but it
is not advisable to go below this.
• Pad overlap 0.5mm beneath component.
• Pad extension 0.5mm beyond components for reflow and
1.0mm for wave soldering.
D1
D2
D3
D4
D5
Case Size D1 D2 D3 D4 D5
0402 1.70 (0.07) 0.60 (0.02) 0.50 (0.02) 0.60 (0.02) 0.50 (0.02)
0603 2.30 (0.09) 0.80 (0.03) 0.70 (0.03) 0.80 (0.03) 0.75 (0.03)
0805 3.00 (0.12) 1.00 (0.04) 1.00 (0.04) 1.00 (0.04) 1.25 (0.05)
1206 4.00 (0.16) 1.00 (0.04) 2.00 (0.09) 1.00 (0.04) 1.60 (0.06)
1210 4.00 (0.16) 1.00 (0.04) 2.00 (0.09) 1.00 (0.04) 2.50 (0.10)
1808 5.60 (0.22) 1.00 (0.04) 3.60 (0.14) 1.00 (0.04) 2.00 (0.08)
1812 5.60 (0.22) 1.00 (0.04)) 3.60 (0.14) 1.00 (0.04) 3.00 (0.12)
1825 5.60 (0.22) 1.00 (0.04) 3.60 (0.14) 1.00 (0.04) 6.35 (0.25)
2220 6.60 (0.26) 1.00 (0.04) 4.60 (0.18) 1.00 (0.04) 5.00 (0.20)
2225 6.60 (0.26) 1.00 (0.04) 4.60 (0.18) 1.00 (0.04) 6.35 (0.25)
Dimensions in millimeters (inches)
REFLOW SOLDERING
42
WAVE SOLDERING
Component Spacing
For wave soldering components, must be spaced sufficiently
far apart to avoid bridging or shadowing (inability of solder
to penetrate properly into small spaces). This is less impor-
tant for reflow soldering but sufficient space must be
allowed to enable rework should it be required.
Preheat & Soldering
The rate of preheat should not exceed 4°C/second to
prevent thermal shock. A better maximum figure is about
2°C/second.
For capacitors size 1206 and below, with a maximum
thickness of 1.25mm, it is generally permissible to allow a
temperature differential from preheat to soldering of 150°C.
In all other cases this differential should not exceed 100°C.
For further specific application or process advice, please
consult AVX.
Cleaning
Care should be taken to ensure that the capacitors are
thoroughly cleaned of flux residues especially the space
beneath the capacitor. Such residues may otherwise
become conductive and effectively offer a low resistance
bypass to the capacitor.
Ultrasonic cleaning is permissible, the recommended
conditions being 8 Watts/litre at 20-45 kHz, with a process
cycle of 2 minutes vapor rinse, 2 minutes immersion in the
ultrasonic solvent bath and finally 2 minutes vapor rinse.
Surface Mounting Guide
MLC Chip Capacitors
D1
D2
D3
D4
D5
Case Size D1 D2 D3 D4 D5
0603 3.10 (0.12) 1.20 (0.05) 0.70 (0.03) 1.20 (0.05) 0.75 (0.03)
0805 4.00 (0.15) 1.50 (0.06) 1.00 (0.04) 1.50 (0.06) 1.25 (0.05)
1206 5.00 (0.19) 1.50 (0.06) 2.00 (0.09) 1.50 (0.06) 1.60 (0.06)
1210 5.00 (0.19) 1.50 (0.06) 2.00 (0.09) 1.50 (0.06) 2.50 (0.10)
Dimensions in millimeters (inches)
43
Surface Mounting Guide
MLC Chip Capacitors
APPLICATION NOTES
Storage
Good solderability is maintained for at least twelve months,
provided the components are stored in their “as received”
packaging at less than 40°C and 70% RH.
Solderability
Terminations to be well soldered after immersion in a 60/40
tin/lead solder bath at 235 ±5°C for 2±1 seconds.
Leaching
Terminations will resist leaching for at least the immersion
times and conditions shown below.
Recommended Soldering Profiles
General
Surface mounting chip multilayer ceramic capacitors
are designed for soldering to printed circuit boards or other
substrates. The construction of the components is such that
they will withstand the time/temperature profiles used in both
wave and reflow soldering methods.
Handling
Chip multilayer ceramic capacitors should be handled with
care to avoid damage or contamination from perspiration
and skin oils. The use of tweezers or vacuum pick ups
is strongly recommended for individual components. Bulk
handling should ensure that abrasion and mechanical shock
are minimized. Taped and reeled components provides the
ideal medium for direct presentation to the placement
machine. Any mechanical shock should be minimized during
handling chip multilayer ceramic capacitors.
Preheat
It is important to avoid the possibility of thermal shock during
soldering and carefully controlled preheat is therefore
required. The rate of preheat should not exceed 4°C/second
and a target figure 2°C/second is recommended. Although
an 80°C to 120°C temperature differential is preferred,
recent developments allow a temperature differential
between the component surface and the soldering temper-
ature of 150°C (Maximum) for capacitors of 1210 size and
below with a maximum thickness of 1.25mm. The user is
cautioned that the risk of thermal shock increases as chip
size or temperature differential increases.
Soldering
Mildly activated rosin fluxes are preferred. The minimum
amount of solder to give a good joint should be used.
Excessive solder can lead to damage from the stresses
caused by the difference in coefficients of expansion
between solder, chip and substrate. AVX terminations are
suitable for all wave and reflow soldering systems. If hand
soldering cannot be avoided, the preferred technique is the
utilization of hot air soldering tools.
Cooling
Natural cooling in air is preferred, as this minimizes stresses
within the soldered joint. When forced air cooling is used,
cooling rate should not exceed 4°C/second. Quenching
is not recommended but if used, maximum temperature
differentials should be observed according to the preheat
conditions above.
Cleaning
Flux residues may be hygroscopic or acidic and must be
removed. AVX MLC capacitors are acceptable for use with
all of the solvents described in the specifications MIL-STD-
202 and EIA-RS-198. Alcohol based solvents are acceptable
and properly controlled water cleaning systems are also
acceptable. Many other solvents have been proven successful,
and most solvents that are acceptable to other components
on circuit assemblies are equally acceptable for use with
ceramic capacitors.
Termination Type Solder Solder Immersion Time
Tin/Lead/Silver Temp. °C Seconds
Nickel Barrier 60/40/0 260±5 30±1
Reflow
300
250
200
150
100
50
0
Solder Temp.
10 sec. max
1min
1min
(Minimize soldering time)
Natural
Cooling
220°C
to
250°C
Preheat
Wave
300
250
200
150
100
50
0
Solder Temp.
(Preheat chips before soldering)
T/maximum 150°C
3 sec. max
1 to 2 min
Preheat Natural
Cooling
230°C
to
250°C
T