LTC4242
1
4242f
Dual Slot Hot Swap
Controller for PCI Express
The LTC®4242 Hot SwapTM controller allows safe board
insertion and removal for two independent slots on a PCI
Express backplane. External N-channel transistors control
the 12V and 3.3V supplies while integrated switches control
the 3.3V auxiliary supplies. Both 12V and 3.3V supplies
can be ramped up at an adjustable rate. Dual level circuit
breakers and fast active current limiting protect all supplies
against overcurrent faults.
A supply fi lter at the VCC pin allows the LTC4242 to endure
supply transients. The EN input detects the presence of a
card in the PCI Express slot. The FAULT and AUXFAULT
outputs alert the system of overcurrent conditions on the
main and auxiliary supplies, respectively. PGOOD and
AUXPGOOD outputs indicate proper main and auxiliary
supply outputs.
■ PCI Express-Based PC and Servers
■ Hot Swap Application for Triple Supply Systems
■ Allows Live Insertion into PCI Express® Backplane
■ Controls Two Independent PCI Express Slots
■ Independent Control of Main and Auxiliary Supplies
■ 20V Rating for 12V Supply Input Pins
■ Integrated 0.25Ω AUX Switches
■ Limits Fault Current in ≤1µs
■ Force On Test Mode
■ Adjustable Supply Voltage Power-Up Rate
■ High Side Drivers for N-Channel MOSFETs
■ Thermal Shutdown Protection
■ Available in 38-Lead QFN and 36-Lead SSOP
Packages
APPLICATIO S
U
FEATURES DESCRIPTIO
U
TYPICAL APPLICATIO
U
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
Hot Swap is a trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
PCI Express Application
Normal Power-Up Sequence
3VSENSE1 3VGATE1
3VIN1
4242 TA01a
PCIe
CONNECTOR
PLUG-IN
CARD
PCIe
CONNECTOR
PLUG-IN
CARD
3.3VOUT
3.3VOUT
12VOUT
3VOUT1
3VOUT2
12VSENSE1 12VGATE1
12VIN1
VCC
AUXIN1
AUXOUT1
FON1
EN1
GND
EN2
FON2
3.3V
3.3V
12V
AUXOUT2
3.3V
AUXON1
ON1
FAULT1
AUXFAULT1
PGOOD1
PGOOD2
AUXFAULT2
FAULT2
ON2
AUXON2
12V
3.3V
12VOUT1
3VSENSE2 3VGATE2
3VIN2
LTC4242G
12VSENSE2 12VGATE2
12VIN2 12VOUT2
BD_PRST1
12VOUT
3.3VOUT
3.3VOUT
BD_PRST2
PCI EXPRESS
HOT PLUG
CONTROLLER
AUXIN2
AUXOUTn
5V/DIV
12VOUTn
5V/DIV
3VOUTn
5V/DIV
PGOODn
5V/DIV
10ms/DIV 4242 F04
ENn
5V/DIV
LTC4242
2
4242f
Supply Voltages
V
CC ........................................................... –0.3V to 7V
12VINn .................................................... –0.3V to 20V
3VINn ...................................................... –0.3V to 10V
AUXINn .................................................. –0.3V to 10V
Input Voltages
ONn, AUXONn, FONn ............................... –0.3V to 7V
ENn .......................................................... –0.3V to 7V
Output Voltages
FAULTn, PGOODn, AUXFAULTn,
AUXPGOODn ........................................... –0.3V to 7V
Analog Voltages
12VSENSEn .............................................. –0.3V to 20V
(Note 1)
ABSOLUTE AXI U RATI GS
W
WW
U
PACKAGE/ORDER I FOR ATIO
UUW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
TOP VIEW
G PACKAGE
36-LEAD PLASTIC SSOP
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
EN1
FON1
ON1
AUXON1
3VOUT1
3VGATE1
3VSENSE1
3VIN1
AUXIN1
VCC
AUXIN2
3VIN2
3VSENSE2
3VGATE2
3VOUT2
AUXON2
ON2
FON2
FAULT1
AUXFAULT1
PGOOD1
12VIN1
12VSENSE1
12VGATE1
12VOUT1
AUXOUT1
GND
AUXOUT2
12VOUT2
12VGATE2
12VSENSE2
12VIN2
PGOOD2
AUXFAULT2
FAULT2
EN2
TJMAX = 125°C, θJA = 95°C/W
13 14 15 16
TOP VIEW
39
UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
17 18 19
38 37 36 35 34 33 32
24
25
26
27
28
29
30
31
8
7
6
5
4
3
2
1AUXON1
3VOUT1
3VGATE1
3VSENSE1
3VIN1
AUXIN1
VCC
AUXIN2
3VIN2
3VSENSE2
3VGATE2
3VOUT2
12VIN1
12VSENSE1
12VGATE1
12VOUT1
AUXOUT1
GND
AUXOUT2
12VOUT2
12VGATE2
12VSENSE2
12VIN2
AUXPGOOD2
ON1
FON1
EN1
FAULT1
AUXFAULT1
PGOOD1
AUXPGOOD1
AUXON2
ON2
FON2
EN2
FAULT2
AUXFAULT2
PGOOD2
23
22
21
20
9
10
11
12
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN 39) IS GND, PCB ELECTRICAL CONNECTION OPTIONAL
ORDER PART NUMBER ORDER PART NUMBER UHF PART MARKING*
LTC4242CG
LTC4242IG
LTC4242CUHF
LTC4242IUHF
4242
4242
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
*The temperature grade is identifi ed by a label on the shipping container. Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.
12VGATEn ................................................ –0.3V to 25V
12VOUTn (Note 3) .. 12VGATEn – 5V to 12VGATEn + 0.3V
AUXOUTn, 3VSENSEn .............................. –0.3V to 10V
3VGATEn .................................................. –0.3V to 14V
3VOUTn (Note 3) ....... 3VGATEn – 5V to 3VGATEn + 0.3V
Operating Temperature Range
LTC4242C ................................................ 0°C to 70°C
LTC4242I ............................................. –40°C to 85°C
Storage Temperature Range
SSOP ................................................. –65°C to 150°C
QFN .................................................... –65°C to 125°C
Lead Temperature (Soldering, 10 sec)
SSOP ................................................................ 300°C
LTC4242
3
4242f
The ● denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VCC = VAUXINn = V3VINn = 3.3V, V12VINn = 12V, unless otherwise noted.
(Note 2)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Supplies
VIN Operating Voltage VCC
12VINn
3VINn
AUXINn
●
●
●
●
2.7
10.1
3.0
3.0
6.0
14.4
6.0
6.0
V
V
V
V
IDD Input Supply Current
VCC
12VINn
3VINn
VAUXONn = 2V, VONn = 2V
●
●
●
1.6
0.5
0.35
4
1
1
mA
mA
mA
VUVL Supply Undervoltage Lockout VCC Rising
12VINn Rising
3VINn Rising
AUXINn Rising
●
●
●
●
2.3
9.48
2.57
2.57
2.45
9.78
2.67
2.67
2.6
10.08
2.77
2.77
V
V
V
V
ΔVLKO(HYST) Supply Undervoltage Lockout Hysteresis VCC
12VINn
3VINn
AUXINn
●
●
●
●
30
90
20
20
100
130
35
35
200
170
50
50
mV
mV
mV
mV
Current Limit
ΔVSENSE(CB) Circuit Breaker Trip Sense Voltage
12VINn – 12VSENSEn
3VINn – 3VSENSEn
●
●
45
45
50
50
55
55
mV
mV
ΔVSENSE(ACL) Active Current Limit Sense Voltage
12VINn – 12VSENSEn
3VINn – 3VSENSEn
●
●
75
75
100
100
125
125
mV
mV
ICBAUX Circuit Breaking Current for AUX Supply ●385 550 715 mA
tCB Circuit Breaker Response Time ●10 20 40 µs
Switch Resistance
RAUX Internal Switch Resistance
RAUX = (VAUXINn – VAUXOUTn)/I
(Note 4)
I = 375mA ●0.25 0.4 Ω
External Gate Drive
IGATE(UP) External N-Channel Gate Pull-Up Current Gate Drive On
V12VGATEn = 1V
V3VGATEn = 1V
●
●
–5
–5
–9
–9
–13
–13
µA
µA
IGATE(DN) External N-Channel Gate Pull-Down Current Gate Drive Off
V12VGATEn = 17V, V12VOUTn = 12V
V3VGATEn = 8.3V, V3VOUTn = 3.3V
●
●
0.5
0.5
1
1
2
2
mA
mA
IGATE(FPD) External N-Channel Gate Fast Pull-Down
Current
Fast Turn Off
V12VGATEn = 17V, V12VOUTn = 12V
V3VGATEn = 8.3V, V3VOUTn = 3.3V
●
●
150
150
250
250
400
400
mA
mA
ΔVGATE External N-Channel Gate Drive
12VGATEn – 12VOUTn
3VGATEn – 3VOUTn
IGATE = 1µA (Note 3)
●
●
4.5
4.5
5.5
5.5
7.9
7.9
V
V
Input Pins
VPG(TH) Power Good Threshold Voltage 12VOUTn Falling
3VOUTn Falling
AUXOUTn Falling (Note 5)
●
●
●
10.08
2.772
2.772
10.38
2.855
2.855
10.68
2.937
2.937
V
V
V
VPG(HYST) Power Good Hysteresis 12VOUTn
3VOUTn
AUXOUTn (Note 5)
●
●
●
20
5
5
70
20
20
110
30
30
mV
mV
mV
ELECTRICAL CHARACTERISTICS
LTC4242
4
4242f
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VON(TH) ONn, AUXONn Pin Threshold Voltage Rising Edge ●1.173 1.235 1.297 V
ΔVON(TH) ONn, AUXONn Pin Hysteresis ●30 70 120 mV
VON(RTH) ONn, AUXONn Pin Reset Threshold Voltage Falling Edge ●0.5 0.6 0.7 V
ION(IN) ONn, AUXONn Pin Input Current VONn = VAUXONn = 1.2V ●±1 µA
VEN(TH) ENn Pin Threshold Voltage ENn Rising ●1.173 1.235 1.297 V
ΔVEN(HYST) ENn Pin Hysteresis ●30 70 120 mV
IEN(UP) ENn Pull-Up Current VENn = 1V ●–5 –9 –13 µA
VFON FONn Pin Logic Threshold ●0.7 2.6 V
ISENSE SENSE Pin Input Current
12VSENSEn
3VSENSEn
V12VSENSEn = 12V
V3VSENSEn = 3.3V
●
●
40
40
100
100
µA
µA
IOUT OUT Pin Input Current
12VOUTn
3VOUTn
Gate Drive On
V12VOUTn = 12V
V3VOUTn = 3.3V
●
●
45
27
90
60
µA
µA
ROUT(DIS) OUT Pin Discharge Resistance
12VOUTn
3VOUTn
AUXOUTn
Gate Drive Off
V12VOUTn = 6V
V3VOUTn = 2V
VAUXOUTn = 2V
●
●
●
350
165
375
700
330
750
1400
660
1500
Ω
Ω
Ω
Output Pins
VOL Output Low Voltage
FAULTn, AUXFAULTn, PGOODn,
AUXPGOODn (Note 5)
IPIN = 3mA
●0.14 0.4 V
IPU Pull-Up Current
FAULTn, AUXFAULTn, PGOODn,
AUXPGOODn (Note 5)
VPIN = 1.5V
●–5 –9 –13 µA
Slew Rate
SRAUXOUT AUXOUTn Slew Rate ●1.25 1.7 V/ms
Delays
tPLH(GATE) Input High (ONn) to GATEs High Prop Delay ●714 µs
tPLH(UVL) Input Supply Low (12VINn, 3VINn) to GATEs
Low Prop Delay
●18 36 µs
tPLH(PG) Out Low (12VOUTn, 3VOUTn) to PGOOD High
Prop Delay
●20 40 µs
tPHL(SENSE) Sense Voltage High to GATE Low ΔVSENSE = 200mV, CGATE = 10nF ●0.4 1 µs
The ● denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VCC = VAUXINn = V3VINn = 3.3V, V12VINn = 12V, unless otherwise noted.
(Note 2)
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All current into device pins is positive, all current out of the device
pins is negative. All voltages are referenced to GND unless otherwise
specifi ed.
Note 3: An internal clamp limits the GATE pins to a minimum of 5V above
VOUT. Driving this pin to voltages beyond the clamp may damage the
device.
Note 4: For the QFN package, the AUX FET on resistance is guaranteed by
correlation to wafer level measurements.
Note 5: Available on QFN package only.
LTC4242
5
4242f
IDD vs VCC
VCC, 12VINn and 3VINn Supply
Current vs Temperature
12VINn UV Rising Threshold
vs Temperature
3VINn, AUXINn Rising Threshold
vs Temperature
12VOUTn Power Good Threshold
vs Temperature
3VOUTn, AUXOUTn Power Good
Threshold vs Temperature
OUT Discharge Resistance
vs Temperature
TYPICAL PERFOR A CE CHARACTERISTICS
UW
TA = 25°C. VCC = VAUXINn = V3VINn = 3.3V, V12VINn = 12V, unless otherwise noted. (Note 2)
ONn, AUXONn, ENn Low-to-High
Threshold vs Temperature
ONn, AUXONn, ENn Hysteresis
vs Temperature
VCC (V)
3
IDD (mA)
1.0
2.5
7
4242 G01
1.5
1.0 456
3.0
TEMPERATURE (°C)
–50
0.3
SUPPLY CURRENT (mA)
0.6
0.9
1.2
1.5
VCC
1.8
–25 02550
4242 G02
75 100
12VINn
3VINn
TEMPERATURE (°C)
–50
9.4
12VINn UV RISING THRESHOLD (V)
9.6
9.8
10.0
10.2
–25 0 25 50
4242 G03
75 100
TEMPERATURE (°C)
–50
2.64
3VINn AUXINn UV RISING THRESHOLD (V)
2.66
2.68
2.70
2.72
–25 0 25 50
4242 G04
75 100
TEMPERATURE (°C)
–50
9.8
12VOUTn POWER GOOD THRESHOLD (V)
10.0
10.2
10.4
10.6
–25 0 25 50
4242 G05
75 100
TEMPERATURE (°C)
–50
2.84
3VOUTn AUXOUTn POWER GOOD THRESHOLD (V)
2.86
2.88
2.90
2.92
–25 0 25 50
4242 G06
75 100
TEMPERATURE (°C)
–50
200
OUT DISCHARGE RESISTANCE (Ω)
400
600
800
1000
–25 0 25 50
4242 G07
75 100
AUXOUTn
12VOUTn
3VOUTn
TEMPERATURE (°C)
–50
1.232
ONn, AUXONn, ENn LOW-HIGH THRESHLD (V)
1.234
1.236
1.238
1.240
1.242
–25 02550
4242 G08
75 100
TEMPERATURE (°C)
–50
50
ONn, AUXONn, ENn HYSTERESIS (mV)
60
70
80
90
–25 0 25 50
4242 G09
75 100
LTC4242
6
4242f
FONn High-to- Low Threshold
vs VCC RON vs Temperature
FONn Low-to-High Threshold
vs VCC
Circuit Breaker Trip Sense
Voltage vs Temperature
Aux Circuit Breaker Trip Current
vs Temperature
Circuit Breaker Trip Filter Time
vs Temperature
TYPICAL PERFOR A CE CHARACTERISTICS
UW
TA = 25°C. VCC = VAUXINn = V3VINn = 3.3V, V12VINn = 12V, unless otherwise noted. (Note 2)
Gate Drive vs IGATE
RON vs AUXINn
Current Limit Propagation Delay
vs Sense Voltage
VCC (V)
2
FONn LOW-HIGH THRESHOLD (V)
3
4
5
6
4242 G10
2
1
03457
VCC (V)
0
FONn HIGH-LOW THRESHOOLD (V)
1
2
3
3456
4242 G11
72
TEMPERATURE (°C)
–50
0.15
RON (Ω)
0.20
0.25
0.30
0.35
–25 0 25 50
4242 G12
75 100
AUXINn (V)
3
0.15
RON (Ω)
0.20
0.25
0.30
0.35
3.5 4 4.5 5
4242 G13
5.5 6 6.5
SENSE VOLTAGE (mV)
0
0.01
CURRENT LIMIT PROPAGATION DELAY (µs)
0.1
1
10
100
50 100 150 200
4242 G14
250 300
TEMPERATURE (°C)
–50
48
CIRCUIT BREAKER TRIP SENSE VOLTAGE (mV)
49
50
51
52
–25 0 25 50
4242 G14
75 100
TEMPERATURE (°C)
–50
450
AUX CIRCUIT BREAKER TRIP CURRENT (mA)
500
550
600
650
–25 0 25 50
4242 G14
75 100
TEMPERATURE (°C)
–50
15.0
CIRCUIT BREAKER TRIP FILTER TIME (µs)
17.5
20.0
22.5
25.0
–25 0 25 50
4242 G17
75 100
IGATE (µA)
2
1
0
GATE DRIVE (V)
2
3
4
5
6
46 810
4242 G18
LTC4242
7
4242f
Gate Drive vs Temperature IGATE Pull-Up vs Temperature
IGATE Off Current vs Temperature
Gate Fast Pull-Down Current
vs Temperature
TYPICAL PERFOR A CE CHARACTERISTICS
UW
TA = 25°C. VCC = VAUXINn = V3VINn = 3.3V, V12VINn = 12V, unless otherwise noted. (Note 2)
TEMPERATURE (°C)
–50
5.0
GATE DRIVE (V)
5.2
5.4
5.6
5.8
6.0
–25 02550
4242 G19
75 100
TEMPERATURE (°C)
–50
0
IGATE PULL-UP (µA)
–5
–10
–15
–25 0 25 50
4242 G20
75 100
TEMPERATURE (°C)
–50
0.7
IGATE OFF CURRENT (mA)
0.8
0.9
1.0
1.1
1.2
–25 02550
4242 G21
74 100
TEMPERATURE (°C)
–50
200
GATE FAST PULL-DOWN CURRENT (mA)
225
250
275
300
–25 0 25 50
4242 G22
75 100
LTC4242
8
4242f
PI FU CTIO S
UUU
12VGATE1/12VGATE2: Gate Drive for 12V Supply External
N-Channel MOSFET. An internal charge pump provides
a 9µA pull-up current to ramp up 12VGATEn. During turn
off, a 1mA pull-down current source discharges 12VGATEn
to ground. 12VGATEn is internally clamped to 5.5V above
12VOUTn. During an overcurrent fault, a 250mA pull-down
current source between 12VGATEn and 12VOUTn is activated.
An external RC network is required at the pin for optimum
current limit response.
12VSENSE1/12VSENSE2: 12V Supply Current Limit Sense
Input. A sense resistor is placed in the supply path between
12VINn and 12VSENSEn to sense the 12V channel’s load
current. The voltage across the sense resistor is monitored
for active current limit and circuit breaker fault detection.
To disable the circuit breaker function for the 12V channel,
connect 12VSENSEn to 12VINn.
12VIN1/12VIN2: 12V Supply Input. An undervoltage lockout
circuit disables the 12V and 3.3V supplies when 12VINn
voltage is less than 9.78V.
12VOUT1/12VOUT2: 12V Output Connection. Connect this
pin to the source of the 12V supply external N-channel
MOSFET for gate drive return. PGOOD1/PGOOD2 cannot
pull low until this pin goes above 10.38V. A 700Ω active
pull-down discharges 12VOUTn to ground when the external
MOSFET is turned off.
3VGATE1/3VGATE2: Gate Drive for 3.3V Supply External
N-Channel MOSFET. An internal charge pump provides
a 9µA pull-up current to ramp up 3VGATEn. During turn
off, a 1mA pull-down current source discharges 3VGATEn
to ground. 3VGATEn is internally clamped to 5.5V above
3VOUTn. During an overcurrent fault, a 250mA pull-down
current source between 3VGATEn and 3VOUTn is activated.
An external RC network is required at the pin for optimum
current limit response.
3VSENSE1/3VSENSE2: 3.3V Supply Current Limit Sense Input.
A sense resistor is placed in the supply path between 3VINn
and 3VSENSEn to sense 3.3V channel’s load current. The
voltage across the sense resistor is monitored for active
current limit and circuit breaker fault detection. To disable
the circuit breaker function for the 3.3V channel, connect
3VSENSEn to 3VINn.
3VIN1/3VIN2: 3.3V Supply Input. An undervoltage lockout
circuit disables the 3.3V and 12V supplies when 3VINn
voltage is less than 2.67V.
3VOUT1/3VOUT2: 3.3V Output Connection. Connect this
pin to the source of the 3.3V supply external N-channel
MOSFET for gate drive return. PGOOD1/PGOOD2 cannot
pull low until this pin goes above 2.855V. A 375Ω active
pull-down discharges 3VOUTn to ground when the external
MOSFET is turned off.
AUXFAULT1/AUXFAULT2: AUX Supply Fault Status Out-
put. AUXFAULTn is normally pulled high by an internal 9µA
pull-up. It asserts low if the AUX channel shuts off due
to an overcurrent fault or due to the device temperature
rising above 150°C. Indicates switch ON status when
FONn and ENn are high.
AUXON1/AUXON2: AUX Supply On Control Input. A rising
edge turns on the internal FET, while a falling edge turns it
off. Pulling this pin below 0.6V for more than 3.5µs clears
the fault on the AUX channel.
AUXIN1/AUXIN2: AUX Supply Input. An undervoltage
lockout circuit disables the AUX supply when the voltage
at AUXINn is less than 2.67V. AUXINn is the input to the
internal pass FET.
AUXOUT1/AUXOUT2: AUX Supply Output. AUXOUTn
is the output from the internal pass FET. AUXPGOOD1/
AUXPGOOD2 cannot pull low until this pin goes above
2.855V. A 750Ω active pull-down discharges AUXOUTn
to ground when the internal FET is turned off.
LTC4242
9
4242f
AUXPGOOD1/AUXPGOOD2 (QFN): AUX Supply Power
Status Output. This open-drain pin is pulled high by an
internal 9µA pull-up when AUXOUTn is below power good
threshold, when ENn is high, during thermal shutdown,
AUXONn is low or when VCC or AUXINn are in UVLO.
EN1/EN2: Card Presence/Slot Insert Detect Input. ENn
pin must be pulled below 1.235V to enable the system.
An internal 9µA pull-up current source is present on this
pin.
Exposed Pad (QFN): Power Ground. PCB electrical con-
nection is optional.
FAULT1/FAULT2: Main Supplies Fault Status Output.
FAULTn is pulled high by an internal 9µA pull-up. When an
overcurrent fault occurs at either the 12V or 3.3V supply,
FAULTn is latched low.
FON1/FON2: Force On Digital Input. For diagnostic pur-
poses, a high input overrides undervoltage and overcurrent
faults on 12V, 3.3V and AUX channels and input commands
PI FU CTIO S
UUU
on the ONn and AUXONn pins. However, UVLO on VCC
would shut off the switches. Caution! There is no current
limit mechanism in this mode. Connect FONn to ground
to disable the fault override feature.
GND: Device Ground. Connect to a ground plane.
ON1/ON2: Main Supply On Control Input. A rising edge
turns on the external MOSFETs for the 12V and 3.3V sup-
plies, while a falling edge turns them off. Pull this pin below
0.6V to clear the faults on 12V and 3.3V channels.
PGOOD1/PGOOD2: Main Supply Power Status Output. This
open-drain pin is pulled high by an internal 9µA pull-up
when 12VOUTn or 3VOUTn is below power good threshold,
when ENn is high, ONn is low or when VCC or any of the
main supplies are in UVLO.
VCC: Device Supply Input. Operates from 2.7V to 6V. An
internal undervoltage lockout circuit disables the part until
the voltage at VCC exceeds 2.45V.
LTC4242
10
4242f
FU CTIO AL DIAGRA
UU
W
+
–
–
+
–
–
+
–
EN
VCC
10µA
VCC
9µA
CP12V
CP3V
CPAUX
1.235V
0.6V
1.235V
0.6V
1.235V
ON1
FON
ON2
BOARD PRSNT
MAIN ON
FORCE ON
AUX ON
SYSTEM
CONTROL
SYSTEM CONTROL
UVLO
CHARGE
PUMP
GATE
DRIVER
OSCILLATOR
4
3 3
VCC
12VIN
3VIN
AUXIN
ENn
ONn
AUXONn
FONn
FAULTn
VCC
GND
VCC
9µA
PGOODn
+
–
+
–
+
–
ACL1
CP12V
9µA
1.235V
7.4R
R
ECB1
PG1
12V PWR GOOD
12V SUPPLY
CONTROL
12VINn
12VOUTn
12VSENSEn
100mV
12VGATEn
12V SUPPLY
1mA
5.5V
12VOUTn
+–
50mV
+–
+
–
+
–
+
–
ACL2
CP3V
9µA
1.235V
1.31R
R
ECB2
PG2
3.3V PWR GOOD
3.3V SUPPLY
CONTROL
3VINn
3VOUTn
3VSENSEn
100mV
3VGATEn
3.3V SUPPLY
1mA
+–
50mV
+–
VCC
9µA
AUX SUPPLY
CONTROL
AUXINn
AUXFAULTn
AUX SUPPLY
4242 FD
THERMAL
SHUTDOWN
VCC
CPAUX
AUX FET 9µA
AUXPGOODn
AUXOUTn
GATE
DRIVER 5.5V
3VOUTn
LTC4242
11
4242f
OPERATIO
U
The Functional Diagram displays the main functional ele-
ments of this device. The LTC4242 is designed to control
the power for two independent slots on a PCI Express
backplane, allowing two boards to be safely inserted and
removed. During normal operation, the charge pump
sources 9µA to turn on the gate of the external N-chan-
nel MOSFETs to pass power to the load. The gates of the
external MOSFETs are clamped about 5.5V above their
sources. The gates of the AUX FETs rise at a slew rate of
about 1.25V/ms to control the inrush current.
The electronic circuit breaker (ECB) comparator and ana-
log current limit (ACL) amplifi er monitor the load current
using the difference between the VIN and SENSE voltage.
The threshold of the ACL is set at 2x the ECB threshold.
The ACL amplifi er limits the current in the load by reduc-
ing the gate-to-source voltage of the external MOSFETs
in an active control loop. When an overcurrent condition
persists for more than 20µs, the MOSFETs are shut off to
prevent overheating. FAULT is latched low to signal that
an overcurrent condition has occurred on the external
MOSFETs controlling the main channels.
The AUX FET’s control circuitry has a circuit breaker that
trips at 550mA after 20µs. It also incorporates an active
current limit amplifi er that would limit the current fl ow-
ing in the AUX FET to about 1.65A. A thermal shutdown
circuit shuts off the AUX FET when the die temperature
rises above 150°C. AUXFAULT is latched low to signal
an overcurrent conditon on the internal FET or thermal
shutdown has occurred.
When the switches are off (both internal and external),
the OUT pins are discharged to ground through internal
N-channel transistors.
The output voltages are monitored using the OUT pins
and the PG comparators to determine if the voltage
is valid. The power good conditon is signaled by the
PGOOD/AUXPGOOD pins using open-drain pull-down
transistors.
The Functional Diagram shows the monitoring blocks of
the LTC4242. The group of comparators in the system
control includes the UVLO, ON and EN comparators.
These comparators are used to determine if the external
conditions are valid prior to turning on the switches. But
fi rst the undervoltage lockout circuit (UVLO) must validate
the input supplies and the main supply VCC and generate
the power up initialization to the logic circuits.
The FON inverter in the system control is used for op-
erating the LTC4242 in diagnostic mode. In this mode
of operation, all pass transistors are forced to turn on,
ignoring the undervoltage, circuit breaker/current limit-
ing status and input commands. However, if VCC drops
below its UVLO voltage, all switches would be shut off,
regardless of FON.
APPLICATIO S I FOR ATIO
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The typical LTC4242 application is in a backplane or moth-
erboard that controls power to two PCI Express slots. The
device reports fault and power good status to the system
hot plug controller (HPC).
The basic LTC4242 application circuit is shown in Fig-
ure 1. Discussion begins with board presence detection
in a PCI Express system, the normal turn on and off
sequence, the various fault conditons and recovery from
fault situations. The force on operation is discussed next
followed by the considerations for PCB layout. External
component selection is discussed in detail in the Design
Example section.
Board Presence Detect
In PCI Express systems, the system board connector uses
two signals, PRSNT1 and PRSNT2, to detect the pres-
ence of a board and ensure a fully inserted board in the
connector as shown in Figure 2. PRSNT2 is routed to the
system HPC. Upon a board insertion into the connector,
a turn-on command is generated by the HPC to LTC4242
after a programmed HPC debounce delay, as shown in
Figure 1. Another method to generate the debounce delay
is through the delay network shown in Figure 3.
LTC4242
12
4242f
3VSENSE1 3VGATE1
Q2
Si7336ADP
Q1
Si7336ADP
3VIN1
876
R6
10Ω
R8
10Ω
R7
10Ω
RG2
18Ω
SLOT A
SLOT B
12V
5.5A
3.3V
3A
12V
5.5A
4242 F01
3.3V
3A
3.3V
375mA
3.3V
375mA
RG1
47Ω
RS
33Ω
R2
13mΩ
R1
8mΩ
CG2
47nF
RG4
18Ω
CG4
47nF
CG1
15nF
C1
1µF
3VOUT1
5
RG3
47Ω
CG3
15nF
12VSENSE1 12VGATE1
12VIN1
VCC
33
10
3.3V
AUXIN1 AUXOUT1
FON1
EN1
GND
EN2
FON2
9 29
PCIe CONNECTOR ×1
PCIe CONNECTOR ×1
27
2
1
28
19
18
3.3V
3.3V
12V
AUXIN2 AUXOUT2
11
FAULT1
36
AUXFAULT1
35
PGOOD1
34
MRL1
BD_PRST1
PWRFLT1
AUXPWRFLT1
PGOOD1
AUXON1
ON1
4
MRL2
HPC
AUXON2
16
PWREN1
PWREN2
3
12V
3.3V
32 31
R5
10Ω
12VOUT1
3VSENSE2 3VGATE2
3VIN2
LTC4242G
3VOUT2
12VSENSE2 12VGATE2
12VIN2 12VOUT2
30
23 24 25 26 12 13 14 15
ON2
17
FAULT2
20
AUXFAULT2
21
PGOOD2
22
PWRFLT2
AUXPWRFLT2
PGOOD2
BD_PRST2
Q3
Si7336ADP
R3
8mΩ
Q4
Si7336ADP
R4
13mΩ
33
SMBus SMBus
33
SMBus SMBus
BD_PRST1 PRSNT2
PRSNT1
BD_PRST2 PRSNT2
PRSNT1
Figure 1. Typical PCI Express Application
APPLICATIO S I FOR ATIO
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LTC4242
13
4242f
When PRSNT2 pulls low after insertion of a board, the
ENn pin goes low after a delay as determined by the
values of CD and RD. For plug-in debounce delay of 1ms
and RD of 47k:
Ctms
µF µF
DDELAY
==
1
43 5 0 023
()
..
Choose CD to be 33nF.
SYSTEM
BOARD
CONNECTOR
GOLD FINGERS
HOT PLUG
CONTROL
LOGIC
PULL-UP
PRSNT1
4242 F02
PRSNT2
SYSTEM BOARD
MATE LAST/BREAK FIRST
PCI EXPRESS ADD-IN CARD
TRACE ON THE ADD-IN CARD
(ACTUAL TRACE ROUTING IS LEFT
UP TO THE BOARD DESIGNER)
Figure 2. Plug-In Card Insertion/Removal
APPLICATIO S I FOR ATIO
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–
+
9µA
LTC4242 VOUT
OUT
GND
1.235V CD
33nF
RD
47k BD_PRSNT
ENn
4242 F03
CONNECTOR
MOTHERBOARD
PLUG-IN
CARD
LOAD
When the board is removed, the power to the slot is dis-
abled after a delay of:
tCsms
DELAY D
2
0 765
928==
..
Turn-On Sequence
The PCI Express power supplies are controlled by the
external N-channel pass transistors, Q1 through Q4, in the
12V and 3.3V power paths, and internal pass transistors
Figure 3. RC Network to Generate Delay During Card Plug-In
LTC4242
14
4242f
for the 3.3V auxiliary power paths. Sense resistors R1 to
R4 provide input for current fault detection. Resistors RG1
to RG4 and capacitors CG1 to CG4 compensate the current
control loops. Capacitors CG1 to CG4 also control the output
power-up rate and the inrush current while resistors R5
to R8 prevent high frequency oscillations in N-channel
MOSFETs, Q1 to Q4 respectively.
The following conditions must be satisfi ed before the
external and internal switches can be turned on.
1. The device’s power supply, VCC, must exceed its
undervoltage lockout threshold. To turn on the exter-
nal/internal switches, the main/auxiliary input supplies
must exceed their UVLO thresholds.
2. The EN pin must be pulled low to begin the start-up
sequence.
When these initial conditions are satisfi ed, the ON pins are
checked. The LTC4242 features per slot ON pins, the AUXON
and ON, to allow independent control of the main input
supplies (12V and 3.3V) and the 3.3V auxiliary supplies. If
the ON pin is high, the switches turn on. If ON is low, the
switches turn on when the ON pin is brought high. Figure 4
shows all supplies turning on after EN goes low.
Each of the external switches is turned on by charging
the GATE with a 9µA current source. The voltage at the
GATE pins rises with a slope equal to 9µA/C
G
and the
supply inrush current is set at C
L
/C
G
• 9µA, where C
L
is
the capacitance at the supply output.
The gate of the internal switch is slewed resulting in the
3.3V
AUX
supply output powering up at an internally set
rate of about 1.25V/ms.
The circuit breaker (ECB) of the input supplies is armed
after the input supplies clear UVLO. Once the supplies
have been turned on and the outputs are within tolerance,
PGOOD for the main input supplies and AUXPGOOD for
the auxiliary input supplies (available for the QFN only)
are pulled low.
Turn-Off Sequence
The switches can be turned off by a variety of conditions.
1. The ON/AUXON pin going low would turn off the main/
internal switches.
2. EN going high turns off all switches.
3. A variety of fault conditions will turn off the switches.
These include supply undervoltage and overcurrent
circuit breaker faults.
4. When thermal shutdown activates, the internal switch
is shut off.
When ON goes low, the main switches are turned off with
a 1mA current pulling down the gate to ground. When
the main supplies are shut off, the PGOOD signal pulls
high and the outputs are discharged to ground through
internal switches. Similarly, when an auxiliary supply is
turned off, the AUXPGOOD signal pulls high and its output
is discharged to ground through internal switches. Figure
5 shows all supplies being turned off by EN going high.
APPLICATIO S I FOR ATIO
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Figure 4. Normal Power-Up Sequence
AUXOUTn
5V/DIV
12VOUTn
5V/DIV
3VOUTn
5V/DIV
PGOODn
5V/DIV
10ms/DIV 4242 F04
ENn
5V/DIV
LTC4242
15
4242f
Figure 5. Normal Power-Down Sequence
APPLICATIO S I FOR ATIO
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Figure 6. Overcurrent Fault on 3.3V Output
Figure 7. Short-Circuit Fault on 3.3V Output
Thermal Shutdown
Each of the two internal switches for the 3.3V auxiliary
supplies is protected by an independent thermal shutdown
circuit. If the temperature of an internal switch reaches
150°C, the switch shuts down immediately and AUXFAULT
is latched low. All other power switches are not affected.
The switch is allowed to turn on again by recycling the
AUXON pin low then high with the temperature falling
below 120°C.
Overcurrent Fault
The LTC4242 features dual level glitch tolerant protection
against overcurrent faults for all the supplies. The sense
resistor (both internal and external) voltage drop is moni-
tored by an electronic circuit breaker (ECB) comparator
and an active current limit (ACL) amplifi er. In the event that
a supply’s current exceeds the ECB threshold, an internal
timer is started. If the supply is still overcurrent after 20µs,
the ECB trips and the MOSFET turns off immediately, as
shown in Figure 6.
During start-up, a supply output could be shorted to ground
in the worst case. The inrush current would be limited to
the ACL threshold, which is 2x the ECB threshold, and the
part will latch off after 20µs.
AUXOUTn
5V/DIV
12VOUTn
5V/DIV
3VOUTn
5V/DIV
PGOODn
5V/DIV
100ms/DIV 4242 F05
ENn
5V/DIV
3VGATEn
5V/DIV
3VOUTn
5V/DIV
ILOAD
3A/DIV
5µs/DIV 4242 F06
FAULTn
5V/DIV
3VGATEn
5V/DIV
3VOUTn
5V/DIV
ILOAD
10A/DIV
5µs/DIV 4242 F07
FAULTn
5V/DIV
During an output short circuit, the surge current must be
brought to a controlled level within the shortest amount of
time to protect the system. The LTC4242’s active current
limit enters a high current protection mode that immediately
turns off the output MOSFET by pulling its gate-to-source
voltage to zero. Current in the output MOSFET drops from
tens of amps to zero in a few hundred nanoseconds. The
input voltage drops during the high current and then
spikes upwards due to lead parasitic inductances as the
LTC4242
16
4242f
MOSFET shuts off (see Supply Transients). The compen-
sation network RG/CG assists the gate voltage recovery.
The ACL limits the current level to 2x the ECB threshold
by regulating the gate voltage.
For the internal switch, the ACL limits the supply current
to about 3x the circuit breaker current level of 550mA.
The ECB has a 20µs fi lter delay before latching off to prevent
unnecessary resets of the system due to minor transient
surges. An overcurrent fault on any of the main outputs
(12V or 3.3V) latches off both main outputs without af-
fecting the 3.3V auxiliary output. Similarly, an overcurrent
fault on the 3.3V auxiliary output latches off the auxiliary
output, without affecting the main outputs.
When there is a shorted load with signifi cant supply lead
inductance, the supply pin voltage could collapse before
the ACL brings down the gate of the external MOSFET. In
this case, the undervoltage lockout circuit, with 18µs fi lter
time, turns off the pass MOSFETs.
Undervoltage Fault
An undervoltage fault occurs when any of the input sup-
plies, 12VIN, 3VIN or AUXIN, falls below its undervoltage
threshold for more than 18µs. This turns off the switches
immediately. An undervoltage on the 3.3V auxiliary sup-
ply will not cause the main supplies to shut off and vice
versa. An undervoltage fault on any of the main supplies
shuts off both main supply switches. If VCC falls below
its UVLO threshold for more than 38µs, all switches are
turned off. The switches are allowed to turn on when
the supply voltages and VCC rise above their respective
undervoltage thresholds.
Power Good Fault
A power good fault occurs when any supply output drops
below its power good threshold for more than 20µs.
A power good fault on the main/AUX supplies causes
the PGOOD/AUXPGOOD to be pulled high. There are a
variety of conditions which must be satisfi ed for PGOOD/
AUXPGOOD to be asserted low:
1. The output voltage is above power good threshold
2. EN pin is low
3. The input voltage is above the undervoltage threshold
4. ON pin is high
5. Thermal shutdown not activated
Resetting Faults
To reset an overcurrent fault on the main outputs, bring ON
low or the faulting supply below its undervoltage lockout
(UVLO) threshold. To reset an overcurrent or thermal
shutdown fault on the auxiliary output, bring AUXON low
or the auxiliary suppy below its UVLO threshold. Bringing
VCC below its UVLO threshold resets all overcurrent and
thermal shutdown faults. The part cannot be reset when
fault overide, FON, is high.
Auto-Retry After a Fault
As shown in Figure 9, the LTC4242 can be confi gured to
automatically retry after a fault condition by connecting
both the FAULT and ON pins together with an RC network.
The auto-retry circuit will attempt to restart the LTC4242
after a circuit breaker trip, as shown in the timing diagram
of Figure 10.
tRC V
RµA
OFF AUTO AUTO OL
AUTO
≈
()
+
••.–
.•
1 235
2 065 9
For the component values shown, tOFF = 3.3ms. Since the
duration of a short is less than 40µs in the worst case, the
auto-retry duty cycle is 1.3%.
APPLICATIO S I FOR ATIO
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Figure 8. Short-Circuit Fault on 3.3VAUX Output
AUXINn
5V/DIV
AUXOUTn
5V/DIV
ILOAD
5A/DIV
5µs/DIV 4242 F08
AUXFAULTn
5V/DIV
LTC4242
17
4242f
VCC Power Supply
The LTC4242 derives its power from VCC. A bypass capacitor
of 1µF should be connected between this pin and ground.
If VCC is derived from the input supplies of 3VIN or AUXIN,
a lowpass fi lter shown in Figure 11 should be used.
This RC network allows the LTC4242 to ride through a
3VIN/AUXIN short-circuit transient without collapsing
below the VCC UVLO threshold. AUXIN or 3VIN may have
narrow but high glitches due to parasitic inductance. Since
the absolute maximum rating for VCC is 7V compared to
10V for AUXIN and 3VIN, the RS and C1 values should be
chosen to damp the peak voltage seen by VCC below 7V.
Figure 11. RC Network for VCC Filtering
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3VSENSE 3VOUT
EN BD_PRST
3.3V
RAUTO
200k
CAUTO
0.1µF
3VIN
3VGATE
Q2
Si7336ADP
R2
13mΩ
GND
LTC4242*
FAULT
*ADDITIONAL DETAILS OMITTED FOR CLARITY
ON
LOAD
4242 F09
1.235V
ON/FAULT
3VIN
3VGATE
3VIN – 3VSENSE
0.6V
VOL
VTH
VCB
tCB
tOFF
4242 F10
Figure 9. Auto-Retry Application
Figure 10. Auto-Retry Timing
GATE Pin Voltage
The minimum gate drive voltage is 4.5V, therefore, logic
level N-channel MOSFETs should be used for the external
switches to maintain adequate gate enhancement. The
GATE pins are clamped at a typical value of 5.5V above
the respective OUT pins.
Compensating the Active Current Loop
The active current limit circuit is compensated using the
resistor RG and the slew rate control capacitor CG. The value
of CG is selected based on the inrush current allowed. The
RG value should be experimentally determined. A suggested
value range for RG is between 10Ω and 100Ω.
C1
1
m
F
4242 F11
RS
33
W
AUXIN
OR
3VIN
VCC
Force ON Operation
When the FON pin is pulled high and EN is low, the
LTC4242 operates in the diagnostic mode. All the input
supplies’ power switches are forced to turn on, regardless
of undervoltage conditions on the input supplies, status of
the ON pins and the fault latch. The contents in the fault
latch would be preserved during this time and no change
of state would occur after the part is confi gured to operate
in the diagnostic mode. If the output current exceeds the
ECB threshold, FAULT/AUXFAULT is pulled low immedi-
ately, but does not latch. The undervoltage lockout on VCC
turns off all the switches, regardless of the status of FON.
During thermal shutdown, the internal switch is shut off to
prevent overheating, even if FON is high. The main power
switches remain on as FON is high. Care must be taken to
ensure the outputs are not short circuited since there is
no current limit mechanism in diagnostic mode.
LTC4242
18
4242f
Yet another mode of operation is the Force ON with cur-
rent limit mode. To enter this mode, pull both FON and
EN high. In this mode of operation, the ACLs are enabled
with the 20µs fi lter time disabled. The fault latch of the
AUX supply can be latched if the AUX’s ICBAUX is exceeded.
AUXFAULT indicates whether the AUX channel FET is on
or off. To enter normal operation, pull FON and EN low
and recycle the ON and AUXON pins.
PCB Layout Considerations
For proper operation of the LTC4242’s circuit breaker,
a Kelvin connection to the sense resistors is required.
The Kelvin sense PCB layout traces should be minimum
length, closed together, balanced and symmetrical to
minimize wiring errors. In addition, the PCB layout for the
sense resistors and the power MOSFETs should include
good thermal management techniques for optimal device
power dissipation. A recommended PCB layout for the
12V sense resistor and the power MOSFET is illustrated
in Figure 12.
In Hot Swap applications where load currents can be 10A,
narrow PCB tracks exhibit more resistance than wider
tracks and hence, operate at higher temperatures. Since
the sheet resistance of 1oz copper foil is approximately
0.5mΩ/square, track resistances and voltage drops add
up quickly in high current applications. Thus, to keep PCB
track resistance, voltage drop and temperature rise to a
minimum, the suggested trace width in these applica-
tions for 1oz copper foil is 0.03" for each ampere of DC
current.
In the majority of applications, it will be necessary to use
plated-through vias to make circuitry connections from
components layers to power and ground layers internal
to the PCB. For 1oz copper foil plating, a general rule is
1A of DC current per via making sure the via is properly
dimensioned so that solder completely fi lls any void.
Check with your PCB fabrication facility for via current
specifi cations.
APPLICATIO S I FOR ATIO
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CURRENT FLOW
TO LOAD
TRACK WIDTH W:
0.03" PER AMPERE
ON 1OZ Cu FOIL C1
SENSE
RESISTOR
POWER PAK
SO-8
12VOUT1
12V
12VIN1
12V
GND
4242 F12
GND
CG1
12VGATE1
VIA PATH
TO GND
33
32
31
30
LTC4242G*
•
•
CURRENT FLOW
TO LOAD
W
CURRENT FLOW
TO SOURCE
*ADDITIONAL DETAILS OMITTED FOR CLARITY, DRAWING NOT TO SCALE!
VIA TO
GND PLANE
W
W
RG1
R5
Figure 12. Recommended Layout for Power MOSFET, Sense Resistor and GATE Components for the 12V Rail
LTC4242
19
4242f
APPLICATIO S I FOR ATIO
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In system board applications, large bypass capacitors
(≥10µF) are recommended at each of the system input
supplies to minimize supply glitches as a result of large
inrush or fault currents.
It is important to put C1, the bypass capacitor for the VCC
pin as close as possible between the VCC and GND pins.
Design Example
Consider a PCI Express Hot Swap application example
with the following power supply requirements:
Table 1. PCI Express Power Supply Requirements
SUPPLY VOLTAGE
MAXIMUM SUPPLY
CURRENT
MAXIMUM LOAD
CAPACITANCE
12V 5.5A 2000µF
3.3V 3.0A 1000µF
3.3VAUX 375mA 150µF
1. Select an RSENSE value for each supply. Calculate the
RSENSE value based on the maximum load current and the
lower circuit breaker threshold limit, ΔVSENSE(CB)(MIN). In
a PCI Express connector, fi ve pins are allocated for the
12V supply, three pins for the 3.3V supply and one pin for
3.3VAUX. The current rating of a connector pin is 1.1A. If
a 1% tolerance is assumed for the sense resistors, then
the following values of resistances should suffi ce:
Table 2. Sense Resistance Values
VOLTAGE SUPPLY RSENSE (1%) ITRIP(MIN) ITRIP(MAX)
12V 8mΩ5.6A 6.9A
3.3V 13mΩ3.4A 4.3A
2. Assume no load current at start-up and the inrush current
charges the load capacitance. Compute gate capacitance
with:
CIt
V
GATE GATE UP
OUT
=()
•1
(2)
t1 is the time to charge up the load capacitor.
With IGATE(UP)(MAX) = 13µA and t1 = 10ms:
a. For 12V Supply, CGATE = 11nF
b. For 3.3V Supply, CGATE = 39nF
So a value of 15nF and 47nF (±10%) should suffi ce for
the 12V and 3.3V supplies respectively. The worst-case
t1 and inrush currents are tabulated in Table 3.
Table 3. Worst-Case t1 and Inrush Current
VOLTAGE SUPPLY t1(MIN) t1(MAX) MAX IINRUSH
12V 13ms 40ms 2.4A
3.3V 11ms 34ms 0.4A
For the internal switch, the slew rate (SR) at the 3.3VAUX
supply output is limited to 1.7V/ms max. The inrush cur-
rent can then be calculated according to:
I
INRUSH(MAX) = CLOAD • SRMAX (3)
The inrush current must be lower than 385mA (ICBAUX(MIN))
for proper start-up. Assuming a tolerance of 30% for the
load capacitance, the value of CLOAD should not exceed
170µF.
3. Next is the selection of MOSFETs for the 12V and 3.3V
main input supplies. The Si7336ADP’s on resistance is less
than 4mΩ at VGS = 4.5V, 25°C and it is a good choice for
3.3V and 12V main supplies.
Since the maximum load for the 3.3V supply is 3A, the
MOSFET may dissipate up to 36mW. The Si7336ADP
has a maximum junction-to-ambient thermal resistance
of 50°C/W. This gives a junction temperature of 51.8°C
when operating at a case temperature of 50°C. Accord-
ing to the Si7336ADP’s Normalized On-Resistance vs
Junction Temperature curve, the device’s on resistance
can be expected to increase by about 12% over its room
temperature value. Recalculation for steady-state RON
and junction temperature yield approximately 4.5mΩ
and 52°C, respectively. The voltage drop across the 3.3V
sense resistor and series MOSFET at 3A and at 50°C PCB
temperature is less than 53mV.
The MOSFET dissipates power during inrush charging of
the output load capacitor. Assuming no load current, the
MOSFET’s dissipated power equals the fi nal load capaci-
tor stored energy. Therefore, average MOSFET dissipated
power is:
PCV
t
ON LOUT
=•
•
2
1
2
(4)
LTC4242
20
4242f
APPLICATIO S I FOR ATIO
WUUU
Using PON and t1 to look up the MOSFETs’ single pulse
θJA(MAX) from the manufacturer’s Transient Thermal
Impedance Graph, the worst-case junction-to-ambient
temperature rise occurs for the 12V MOSFET.
Table 4. MOSFET Power-Up Temperature Rise Calculation
VOLTAGE SUPPLY PON θJA(MAX) ΔT
12V 11W 0.75°C/W 8.3°C
3.3V 0.5W 0.6°C/W 0.3°C
There is a 20µs fi lter time when large current of 2x circuit
breaker’s threshold can fl ow in the switches. This time is
short enough to cause minimal increase in the junction-
to-ambient temperature of the MOSFETs, in the event of
powering up into short circuit or short circuiting after
power up. Therefore, in these events, it can be safely
assumed that the MOSFETs would have minimal thermal
stress on them.
If the LTC4242 operates in the diagnostic mode, user must
ensure a safe joule heating limit of the external MOSFET.
The internal switch will be disabled once the temperature
reaches 150°C, thereby preventing overheating.
LTC4242
21
4242f
TYPICAL APPLICATIO
U
Standalone Hot Swap Application for Four Supplies: 12V, 5V, 3.3V and 3.3V Standby
3VSENSE1 3VGATE1
Si7336ADP
Si7336ADP
3VIN1
10Ω
VCC
AUXIN1
AUXIN2
AUXOUT1
AUXOUT2
PGOOD1
PGOOD2
FON1
FON2
12VGATE2
LTC4242
47Ω
18Ω
18Ω
33Ω
10ΩSMAJ5.0A
100nF
8mΩ
Si7336ADP
8mΩ
4mΩ
47nF
2000µF
10Ω47nF
4242 TA02
15nF
1µF
3VOUT1
12VSENSE2 12VGATE1
3VSENSE2 3VGATE2
3VIN2 3VOUT2
GND
12VIN2
10Ω
12VOUT2
10ΩSMAJ5.0A
100nF
PLUG-IN
CARD
5VIN
5V
10ΩSMAJ7.0A
100nF
10ΩSMAJ15A
100nF
BACKPLANE
AUXON1
AUXON2
ON1
ON2
AUXFAULT2
AUXFAULT1
FAULT1
FAULT2
EN1
EN2
+
1000µF
+
150µF
3.3V STANDBY
385mA
5V
5A
3.3V
5A
12V
10A
NC
+
1000µF
+
FAULT
BD_PRST
ON
3.3VIN
3.3V
12VIN
12V
VSTANDBY
3.3V
AUXFAULT
12VOUT1
12VSENSE1
12VIN1
10k
10k10k
2N2222
4.7µF
LTC4242
22
4242f
PACKAGE DESCRIPTIO
U
G Package
36-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
G36 SSOP 0204
0.09 – 0.25
(.0035 – .010)
0° – 8°
0.55 – 0.95
(.022 – .037)
5.00 – 5.60**
(.197 – .221)
7.40 – 8.20
(.291 – .323)
12345678 9 10 11 12 14 15 16 17 1813
12.50 – 13.10*
(.492 – .516)
2526 22 21 20 19232427282930313233343536
2.0
(.079)
MAX
0.05
(.002)
MIN
0.65
(.0256)
BSC 0.22 – 0.38
(.009 – .015)
TYP
MILLIMETERS
(INCHES)
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
*
**
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
0.42 ±0.03 0.65 BSC
5.3 – 5.7
7.8 – 8.2
RECOMMENDED SOLDER PAD LAYOUT
1.25 ±0.12
LTC4242
23
4242f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTIO
U
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701)
5.00 ± 0.10
(2 SIDES)
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
PIN 1
TOP MARK
(SEE NOTE 6)
0.40 ± 0.10
37
1
2
38
BOTTOM VIEW—EXPOSED PAD
5.15 ± 0.10
(2 SIDES)
7.00 ± 0.10
(2 SIDES)
0.75 ± 0.05
R = 0.115
TYP
0.25 ± 0.05
(UH) QFN 0205
0.50 BSC
0.200 REF
0.200 REF
0.00 – 0.05
RECOMMENDED SOLDER PAD LAYOUT
3.15 ± 0.10
(2 SIDES)
0.40 ±0.10
0.00 – 0.05
0.75 ± 0.05
0.70 ± 0.05
0.50 BSC
5.15 ± 0.05 (2 SIDES)
3.15 ± 0.05
(2 SIDES)
4.10 ± 0.05
(2 SIDES)
5.50 ± 0.05
(2 SIDES)
6.10 ± 0.05 (2 SIDES)
7.50 ± 0.05 (2 SIDES)
0.25 ± 0.05
PACKAGE
OUTLINE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
LTC4242
24
4242f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2006
LT 1106 • PRINTED IN USA
PART NUMBER DESCRIPTION COMMENTS
LTC4210 Hot Swap Contoller 6-Lead SOT-23 Package
LTC4213 No RSENSETM Electronic Circuit Breaker Three Selectable Circuit Breaker Thresholds
LTC4214 Negative Low Voltage Hot Swap Controller Controls Supplies from 0V to –16V
LTC4215 Hot Swap Controller with I2C Compatible Monitoring 2.9V to 15V, 8-Bit ADC Monitors Current and Voltages
LTC4216 Ultralow Voltage Hot Swap Controller Load Voltages from 0V to 6V
LT®4220 Dual Supply Hot Swap Controller ±2.7V to ±16V Operation
LTC4221 Dual Hot Swap Controller Power Sequencer with Dual Speed, Dual Level Fault Protection
LTC4241 PCI-Bus Hot Swap Controller 3.3V Auxiliary Supply
No RSENSE is a trademark of Linear Technology Corporation.
RELATED PARTS
TYPICAL APPLICATIO
U
Hot Swap Application for Two Advanced Mezzanine Cards (AMC)
3VSENSE1 3VGATE1
3VIN1
4242 TA03
CARRIER AMC
CARD
MODULE 1
MODULE 2
CARRIER AMC
CARD
3VOUT1
12VOUT2
12VSENSE1 12VGATE1
12VIN1
33Ω
1µF
33nF 33nF
VCC AUXFAULT1
AUXFAULT2
AUXIN1
AUXIN2
AUXOUT1
AUXOUT2
FON1
FON2
AUXON1
AUXON2
EN1
EN2
GND
ON1
PGOOD1
ON2
PGOOD2
FAULT1
FAULT2
PAYLOAD
POWER
SOURCE
MANAGEMENT
POWER
SOURCE
PAYLOAD
POWER
SOURCE
MANAGEMENT
POWER
SOURCE
12VOUT1
12VSENSE2 12VGATE2
12VIN2
LTC4242G
3VSENSE2 3VGATE2
3VIN2 3VOUT2
BD_PRSNT1
12V
5.6A
3.3V
100mA
12V
5.6A
3.3V
100mA
PS0
PS1
BD_PRSNT1
BD_PRSNT2
BD_PRSNT2
22Ω
0.008Ω
0.4ΩSi2306DS
0.4ΩSi2306DS
Si7336ADP
0.008ΩSi7336ADP
10Ω
33nF 33nF
22Ω
10Ω
10Ω10Ω
INTELLIGENT
PLATFORM
MANAGEMENT
CONTROLLER
NC
PS1
PS0
