1
LT5514
5514f
Ultralow Distortion IF
Amplifier/ADC Driver with
Digitally Controlled Gain
■
Output IP3 at 100MHz: 47dBm
■
Maximum Output Power: 21dBm
■
Bandwidth: LF to 850MHz
■
Propagation Delay: 0.8ns
■
Maximum Gain: 33dB
■
Noise Figure: 7.3dB (Max Gain)
■
Gain Control Range: 22.5dB
■
Gain Control Step: 1.5dB
■
Gain Control Settling Time: 500ns
■
Output Noise Floor: –134dBm/Hz (Max Gain)
■
Reverse Isolation: –80dB
■
Single Supply: 4.75V to 5.25V
■
Low Power Mode
■
Shutdown Mode
■
Enable/Disable Time: 1µs
■
Differential I/O Interface
■
20-Lead TSSOP Package
■
High Linearity ADC Driver
■
IF Sampling Receivers
■
VGA IF Power Amplifier
■
50Ω Driver
■
Instrumentation Applications
, LTC and LT are registered trademarks of Linear Technology Corporation.
DESCRIPTIO
U
FEATURES
APPLICATIO S
U
The LT
®
5514 is a programmable gain amplifier (PGA) with
bandwidth extending from low frequency (LF) to 850MHz.
It consists of a digitally controlled variable attenuator,
followed by a high linearity amplifier. The amplifier is
configured with two identical transconductance amplifi-
ers, hard wired in parallel with individual dedicated enable
pins. When both amplifiers are enabled (Standard mode),
the LT5514 offers an OIP3 of +47dBm (at 100MHz).
Power dissipation can be reduced when a single amplifier
is enabled (Low Power mode). Four parallel digital inputs
control the gain over a 22.5dB range with 1.5dB step
resolution. An on-chip power supply regulator/filter helps
isolate the amplifier signal path from external noise sources.
The LT5514’s open-loop architecture offers stable opera-
tion for any practical load conditions, including peaking-
free AC response when driving capacitive loads, and
excellent reverse isolation.
The LT5514 may be operated broadband, where the out-
put differential RC time constant sets the bandwidth, or it
may be used as a narrowband driver with the appropriate
output filter.
TYPICAL APPLICATIO
U
FREQUENCY (MHz)
0
47
50
56
150
5514 TA02
44
41
50 100 200
38
35
53
OIP3 (dBm)
R
OUT
= 200Ω
R
OUT
= 100Ω
LT5514 ADC
0.1µF 0.1µF
100Ω
5V
CHOKE
GAIN CONTROL
CHOKE
0.1µF5514 TA01
0.1µF
IF
AMP
IF
BPF
LO
RF
INPUT
4 LINES
Output IP3 vs Frequency
(Standard Mode)
2
LT5514
5514f
ORDER PART
NUMBER
(Notes 1, 2)
Power Supply Voltage (V
CC1
, V
CC2
) .......................... 6V
Output Supply Voltage (OUT
+
, OUT
–
) ....................... 8V
Control Input Voltage (ENA, ENB, PGAx) .. –0.5V to V
CC
Signal Input Voltage (IN
+
, IN
–
) ................... –0.5V to 3V
Operating Ambient Temperature Range.. – 40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
LT5514EFE
T
JMAX
= 150°C, θ
JA
= 38°C/W
EXPOSED PAD (PIN 21) IS GND
MUST BE SOLDERED TO PCB
ABSOLUTE MAXIMUM RATINGS
W
WW
U
PACKAGE/ORDER INFORMATION
W
UU
Consult LTC Marketing for parts specified with wider operating temperature ranges.
1
2
3
4
5
6
7
8
9
10
TOP VIEW
20
19
18
17
16
15
14
13
12
11
ENA
V
CC1
GND
GND
IN
+
IN
–
GND
GND
PGA0
PGA1
ENB
V
CC2
GND
GND
OUT
–
OUT
+
GND
GND
PGA3
PGA2
FE PACKAGE
20-LEAD PLASTIC TSSOP
21
ODES OF OPERATIO
UW
MODES ENA ENB AMP A AMP B LT5514 STATE
1 Full Power (Standard) High High On On Enable Amp A and Amp B
2 Low Power A High Low On Off Enable Amp A
3 Low Power B Low High Off On Enable Amp B
4 Shutdown Low Low Off Off Sleep, All Amps Disabled
ATTENUATION STEP POWER GAIN
RELATIVE TO MAX GAIN PGA0 PGA1 PGA2 PGA3 STANDARD MODE* LOW POWER MODE**
1 0dB High High High High 33.0dB 30.0dB
2 –1.5dB Low High High High 31.5dB 28.5dB
3 –3.0dB High Low High High 30.0dB 27.0dB
4 –4.5dB Low Low High High 28.5dB 25.5dB
5 –6.0dB High High Low High 27.0dB 24.0dB
6 –7.5dB Low High Low High 25.5dB 22.5dB
7 –9.0dB High Low Low High 24.0dB 21.0dB
8 –10.5dB Low Low Low High 22.5dB 19.5dB
9 –12.0dB High High High Low 21.0dB 18.0dB
10 –13.5dB Low High High Low 19.5dB 16.5dB
11 –15.0dB High Low High Low 18.0dB 15.0dB
12 –16.5dB Low Low High Low 16.5dB 13.5dB
13 –18.0dB High High Low Low 15.0dB 12.0dB
14 –19.5dB Low High Low Low 13.5dB 10.5dB
15 –21.0dB High Low Low Low 12.0dB 9.0dB
16 –22.5dB Low Low Low Low 10.5dB (Note 3) 7.5dB (Note 3)
*R
OUT
= 200Ω **R
OUT
= 400Ω
PROGRA ABLE GAI SETTI GS
UU WW
3
LT5514
5514f
VCC = 5V, VCCO = 5V, ENA = ENB = 3V, TA = 25°C, unless otherwise
noted. (Note 7) (Test circuits shown in Figures 9 and 10)
DC ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Normal Operating Conditions
V
CC
Supply Voltage (Pins 2, 19) (Note 4) 4.75 5 5.25 V
V
CCO
OUT
+
, OUT
–
Output Pin DC Common Mode Voltage OUT
+
, OUT
–
Connected to V
OSUP
via 3 5 6 V
Choke Inductors or Resistors (Note 5)
V
OUT
OUT
+
, OUT
–
Pin Instantaneous Voltage with Min/Max Limits Apply 2 8 V
Respect to GND
Shutdown DC Characteristics, ENA = ENB = 0.6V
V
IN(BIAS)
IN
+
, IN
–
Bias Voltage Max Gain (Note 6) 1.15 1.3 1.5 V
I
IL(PGA)
PGAO, PGA1, PGA2, PGA3 Input Current V
IN
= 0.6V 20 µA
I
IH(PGA)
PGAO, PGA1, PGA2, PGA3 Input Current V
IN
= 5V 20 µA
I
OUT
OUT
+
, OUT
–
Current All Gain Settings 20 µA
I
CC
V
CC
Supply Current All Gain Settings (Note 4) 44 100 µA
Enable and PGA Inputs DC Characteristics
V
IL
ENA, ENB and PGAx Input Low Voltage x = 0, 1, 2, 3 0.6 V
V
IH
ENA, ENB and PGAx Input High Voltage x = 0, 1, 2, 3 3 V
I
IL(PGA)
PGAO, PGA1, PGA2, PGA3 Input Current V
IN
= 0.6V 20 µA
I
IH(PGA)
PGAO, PGA1, PGA2, PGA3 Input Current V
IN
= 3V and 5V 15 30 µA
I
IL(EN)
ENA, ENB Input Current V
IN
= 0.6V 4 20 µA
I
IH(EN)
ENA, ENB Input Current V
IN
= 3V 18 µA
V
IN
= 5V 38 100 µA
Standard Mode DC Characteristics, ENA = ENB = 3V
V
IN(BIAS)
IN
+
, IN
–
Bias Voltage Max Gain (Note 6) 1.34 1.49 1.65 V
R
IN
Input Differential Resistance All Gain Settings (DC) 108 Ω
g
m
Amplifier Transconductance Max Gain 0.3 S
I
OUT
OUT
+
, OUT
–
Quiescent Current All Gain Settings, V
OUT
= 5V 33 40 47 mA
I
OUT(OFFSET)
Output Current Mismatch All Gain Settings, IN
+
, IN
–
Open 200 µA
I
CC
V
CC1
+ V
CC2
Supply Current Max Gain (Note 4) 64 75 mA
Min Gain (Note 4) 68 80 mA
I
CC(TOTAL)
Total Supply Current I
CC
+ 2 • I
OUT
(Max Gain) 148 174 mA
Low Power Mode DC Characteristics, ENA = O.6V, ENB = 3V or ENA = 3V, ENB = 0.6V
V
IN(BIAS)
IN
+
, IN
–
Bias Voltage Max Gain (Note 6) 1.34 1.48 1.65 V
R
IN
Input Differential Resistance All Gain Settings (DC) 122 Ω
g
m
Amplifier Transconductance Max Gain 0.15 S
I
OUT
OUT
+
, OUT
–
Quiescent Current All Gain Settings, V
OUT
= 5V 17 20 24 mA
I
OUT(OFFSET)
Output Current Mismatch All Gain Settings, IN
+
, IN
–
Open 100 µA
I
CC
V
CC1
+ V
CC2
Supply Current Max Gain (Note 4) 34 40 mA
Min Gain (Note 4) 36 43 mA
I
CC(TOTAL)
Total Supply Current I
CC
+ 2 • I
OUT
(Max Gain) 76 91 mA
4
LT5514
5514f
(Standard Mode)
VCC = 5V, VCCO = 5V, ENA = ENB = 3V, TA = 25°C, ROUT = 200Ω. Maximum gain specifications are with respect to differential inputs
and differential outputs, unless otherwise noted. (Note 7) (Test circuits shown in Figures 9 and 10)
AC ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Dynamic Performance
BW Large-Signal –3dB Bandwidth All Gain Settings (Note 8)
R
OUT
= 100ΩLF to 850 MHz
R
OUT
= 200Ω; L1, L2 = 33nH (Figure 9) LF to 500 MHz
P
OUT(MAX)
Clipping Limited Maximum Sinusoidal All Gain Settings, Single Tone, R
OUT
= 150Ω21 dBm
Output Power f
IN
= 100MHz (Note 10)
g
m
Amplifier Transconductance Max Gain, f
IN
= 100MHz 0.30 S
PGA1 = Low, f
IN
= 100MHz 0.21 S
S12 Reverse Isolation f
IN
= 100MHz (Note 9) –92 dB
f
IN
= 400MHz (Note 9) –78 dB
t
r
, t
f
Step Response Rise and Fall Time All Gain Settings, 10% to 90%, R
OUT
= 100Ω500 ps
Group Delay All Gain Settings, R
OUT
= 100Ω800 ps
Group Delay Variation 30MHz to 300MHz Frequency Range, ±50 ps
R
OUT
= 100Ω
PGA Settling Time 500 ns
Enable/Disable Time 600 ns
Distortion and Noise
OIP3 Output Third Order Intercept Point for P
OUT
= 9dBm (Each Tone), 200kHz Tone Spacing
PGA0 = High (PGA1, PGA2, PGA3 Any State) f
IN
= 100MHz +47.0 dBm
f
IN
= 200MHz +40.5 dBm
Output Third Order Intercept Point for P
OUT
= 9dBm (Each Tone), 200kHz Tone Spacing
PGA0 = Low (PGA1, PGA2, PGA3 Any State) f
IN
= 100MHz +42.0 dBm
f
IN
= 200MHz +37.5 dBm
HD2 Second Harmonic Distortion P
OUT
= 11dBm (Single Tone), f
IN
= 50MHz –82 dBc
HD3 Third Harmonic Distortion P
OUT
= 11dBm (Single Tone), f
IN
= 50MHz –72 dBc
N
FLOOR
Output Noise Floor PGA1 = High, f
IN
= 100MHz –134 dBm/Hz
(PGAO, PGA2, PGA3 Any State) PGA1 = Low, f
IN
= 100MHz –136 dBm/Hz
NF Noise Figure Max Gain, f
IN
= 100MHz 7.4 dB
–3dB Step, f
IN
= 100MHz 7.7 dB
Amplifier Power Gain and Gain Step
G
MAX
Maximum Gain f
IN
= 20MHz and 200MHz 33 dB
G
MIN
Minimum Gain f
IN
= 20MHz and 200MHz 10.5 dB
G
STEP
Gain Step Size f
IN
= 20MHz and 200MHz 1.05 1.5 1.95 dB
Gain Step Accuracy f
IN
= 20MHz and 200MHz ±0.1 dB
Amplifier I/O Impedance (Parallel Values Specified Differentially)
R
IN
Input Resistance f
IN
= 100MHz 108 Ω
C
IN
Input Capacitance f
IN
= 100MHz 2.8 pF
R
O
Output Resistance f
IN
= 100MHz 3.4 kΩ
C
O
Output Capacitance f
IN
= 100MHz 1.9 pF
5
LT5514
5514f
(Low Power Mode)
VCC = 5V, VCCO = 5V, ENA = 3V, ENB = 0.6V, TA = 25°C, ROUT = 200Ω. Maximum gain specifications are with respect to differential
inputs and differential outputs, unless otherwise noted. (Note 7) (Test circuits shown in Figures 9 and 10)
AC ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 2: All voltage values are with respect to ground.
Note 3: Default state for open PGA inputs.
Note 4: V
CC1
and V
CC2
(Pins 2 and 19) are internally connected.
Note 5: External V
OSUP
is adjusted such that V
CCO
output pin common
mode voltage is as specified when resistors are used. For choke inductors
or transformer, V
OSUP
= V
CCO
= 5V typ.
Note 6: Internally generated common mode input bias voltage requires
capacitive or transformer coupling to the signal source.
Note 7: Specifications over the –40°C to 85°C operating temperature
range are assured by design, characterization and correlation with
statistical process controls. Gain always refers to power gain. Input
matching is assumed. P
IN
is the available input power. P
OUT
is the power
into the external load, R
OUT
, as seen by the LT5514 differential outputs. All
dBm figures are with respect to 50Ω.
Note 8: High frequency operation is limited by the RC time constants at
the input and output ports. The low frequency (LF) roll-off is set by I/O
interface choice.
Note 9: Limited by package and board isolation.
Note 10: See “Clipping Free Operation” in the Applications Information
section. Refer to Figure 7.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Dynamic Performance
BW Large-Signal –3dB Bandwidth All Gain Settings (Note 8),
R
OUT
= 100ΩLF to 540 MHz
P
OUT(MAX)
Clipping Limited Maximum Sinusoidal All Gain Settings, Single Tone, 16 dBm
Output Power f
IN
= 100MHz (Note 10)
g
m
Amplifier Transconductance Max Gain, f
IN
= 100MHz 0.15 S
S12 Reverse Isolation f
IN
= 100MHz (Note 9) –92 dB
Distortion and Noise
OIP3 Output Third Order Intercept Point for P
OUT
= 4dBm (Each Tone), 200kHz Tone Spacing,
PGA0 = High (PGA1, PGA2, PGA3 Any State) f
IN
= 100MHz +40 dBm
Output Third Order Intercept Point for P
OUT
= 4dBm (Each Tone), 200kHz Tone Spacing,
PGA0 = Low (PGA1, PGA2, PGA3 Any State) f
IN
= 100MHz +36 dBm
HD2 Second Harmonic Distortion P
OUT
= 5dBm (Single Tone), f
IN
= 50MHz –76 dBc
HD3 Third Harmonic Distortion P
OUT
= 5dBm (Single Tone), f
IN
= 50MHz –72 dBc
N
FLOOR
Output Noise Floor PGA1 = High, f
IN
= 100MHz –138 dBm/Hz
(PGAO, PGA2, PGA3 Any State) PGA1 = Low, f
IN
= 100MHz –140 dBm/Hz
NF Noise Figure Max Gain Setting, f
IN
= 100MHz 8.6 dB
Amplifier Power Gain and Gain Step
G
MAX
Maximum Gain f
IN
= 20MHz and 200MHz 27 dB
G
MIN
Minimum Gain f
IN
= 20MHz and 200MHz 4.5 dB
G
STEP
Gain Step Size f
IN
= 20MHz and 200MHz 1.05 1.5 1.95 dB
Gain Step Accuracy f
IN
= 20MHz and 200MHz ±0.1 dB
Amplifier I/O Impedance
R
IN
Input Resistance f
IN
= 100MHz, Parallel Values Specified 122 Ω
Differentially
C
IN
Input Capacitance f
IN
= 100MHz, Parallel Values Specified 2 pF
Differentially
R
O
Output Resistance f
IN
= 100MHz, Parallel Values Specified 5 kΩ
Differentially
C
O
Output Capacitance f
IN
= 100MHz, Parallel Values Specified 1.7 pF
Differentially
6
LT5514
5514f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Frequency Response for All Gain
Steps, ROUT = 100ΩFrequency Response for All Gain
Steps, ROUT = 200Ω
(Standard Mode) TA = 25°C, VCC = 5V, VCCO = 5V,
ENA = ENB = 3V, control input levels VIL = 0.6V, VIH = 3V unless otherwise noted. (Test circuit shown in Figure 9)
Frequency Response at 3dB
Attenuation Step with COUT as
Parameter, ROUT = 200Ω
Max Gain Frequency Response
with COUT as Parameter,
ROUT = 200Ω
Gain Error vs Attenuation at
25MHz, ROUT = 200ΩGain Error vs Attenuation at
100MHz, ROUT = 200Ω
FREQUENCY (MHz)
10
0
3
POWER GAIN (dB)
12
18
24
100 1000
5514 G01
6
15
21
30
33
27
9
FREQUENCY (MHz)
10
0
3
POWER GAIN (dB)
12
18
24
100 1000
5514 G02
6
15
21
30
36
33
27
9
FREQUENCY (MHz)
10
0
POWER GAIN (dB)
9
15
21
30
100 1000
5514 G03
3
12
18
27
36
33
24
6
COUT = OPEN
COUT = 2.2pF
COUT = 4.7pF
COUT = 10pF
COUT = 22pF
FREQUENCY (MHz)
10
0
POWER GAIN (dB)
9
15
21
30
100 1000
5514 G04
3
12
18
27
36
33
24
6
COUT = OPEN
COUT = 2.2pF
COUT = 4.7pF
COUT = 10pF
COUT = 22pF
ATTENUATION STEP (dB)
0
GAIN ERROR (dB)
0.2
0.4
0.6
21
1544 G05
–0.2
–0.8 369
12 15 18
0.8
0
–0.4
–0.6
25°C
–40°C
85°C
ATTENUATION STEP (dB)
0
GAIN ERROR (dB)
0.2
0.4
0.6
21
1544 G06
–0.2
–0.8 369
12 15 18
0.8
0
–0.4
–0.6
25°C
–40°C
85°C
FREQUENCY (MHz)
10
27
POWER GAIN (dB)
30
33
36
100 1000
5514 G07
25°C
–40°C
85°C
R
OUT
= 200Ω
R
OUT
= 100Ω
FREQUENCY (MHz)
10
4
POWER GAIN (dB)
7
10
13
100 1000
5514 G08
25°C
–40°C
85°CR
OUT
= 200Ω
R
OUT
= 100Ω
PIN (dBm)
–31
–5
POUT (dBm)
0
5
10
15
–25 –19 –13 –7
5514 G09
20
25
–28 –22 –16 –10
STANDARD
ROUT = 200Ω
STANDARD
ROUT = 100Ω
LOW POWER
ROUT = 200Ω
Minimum Gain vs Frequency,
ROUT = 100Ω and 200Ω
Maximum Gain vs Frequency,
ROUT = 100Ω and 200ΩPOUT vs PIN at 50MHz, Max Gain
7
LT5514
5514f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Harmonic Distortion vs Attenuation
Step at POUT = 7dBm,
Freq = 50MHz, ROUT = 200ΩHarmonic Distortion vs POUT at
50MHz, Max Gain, ROUT = 200Ω
(Standard Mode) TA = 25°C, VCC = 5V, VCCO = 5V,
ENA = ENB = 3V, control input levels VIL = 0.6V, VIH = 3V unless otherwise noted. (Test circuit shown in Figure 9)
Harmonic Distortion vs POUT at
50MHz, Max Gain, ROUT = 100Ω
Minimum Gain vs VCC at 120MHz,
ROUT = 100Ω
Harmonic Distortion vs
Attenuation Step at POUT = 7dBm,
Freq = 50MHz, ROUT = 200Ω
V
CC
(V)
4.5
7.4
7.6
7.8
5.3
5514 G10
7.2
7.0
4.7 4.9 5.1 5.5
6.8
6.6
6.4
GAIN (dB)
25°C
85°C
–40°C
Maximum Gain vs VCC at
120MHz, ROUT = 100Ω
V
CC
(V)
4.5
30.0
30.2
30.4
5.3
5514 G11
29.8
29.6
4.7 4.9 5.1 5.5
29.4
29.2
29.0
GAIN (dB)
25°C
85°C
–40°C
ATTENUATION STEP (dB)
0
HD (dBc)
–78
–75
–72
915
5514 G12
–81
–84
36 12 18 21
–87
–90
HD2
FIGURE 10 TEST CIRCUIT HD3
PGA0 = LOW
HD3
PGA0 = HIGH
ATTENUATION STEP (dB)
0
HD (dBc)
–78
–75
–72
915
5514 G12
–81
–84
36 12 18 21
–87
–90
HD2
HD3
PGA0 = LOW
HD3
PGA0 = HIGH
P
OUT
(dBm)
–3
HD (dBc)
–70
–55
–50
21
5514 G14
–75
–80
–100 3915
0612 18
–90
–40
–45
–60
–65
–85
–95
HD2
HD3
HD4HD5
P
OUT
(dBm)
–5
HD (dBc)
–70
–55
–50
19
5514 G15
–75
–80
–100 1713
–2 410 16
–90
–40
–45
–60
–65
–85
–95
HD2
HD3
HD4HD5
FREQUENCY (MHz)
0
6.0
NF (dB)
6.5
7.0
7.5
8.0
100 200 300 400
5514 G16
8.5
9.0
50 150 250 350
MAX GAIN
FIGURE 10 TEST CIRCUIT
1.5dB ATTENUATION STEP
(PGA0 = LOW)
3dB ATTENUATION STEP
(PGA1 = LOW)
ATTENUATION STEP (dB)
0
NF (dB)
18
24
30
15
5514 G17
12
6
15
21
27
9
3
036912 18
21
FIGURE 10 TEST CIRCUIT
ATTENUATION STEP (dB)
0
–139
NOISE FLOOR (dBm/Hz)
–138
–137
–136
–135
–133
36912
5514 G18
1815 21
–134
PGA1 = HIGH
FIGURE 10 TEST CIRCUIT
PGA1 = LOW
NF vs Attenuation Step at
Freq = 100MHz Output Noise Floor vs Attenuation
Step, Freq = 100MHz, ROUT = 200ΩNoise Figure vs Frequency
8
LT5514
5514f
ATTENUATION STEP (dB)
0
38
CURRENT (mA)
39
40
41
36912
5514 G25
15 18 21
85°C
25°C
–40°C
OIP3 vs Frequency at PIN = –23dBm
Max Gain, ROUT = 200Ω
OIP3 vs Attenuation Step at
Freq = 100MHz, PIN = –23dB,
ROUT = 200ΩICC Shutdown Current vs VCC,
ENA = ENB = 0.6V
OIP3 vs Frequency at PIN = –23dBm
Max Gain, ROUT = 100Ω
OIP3 vs Frequency at PIN = –23dBm
Max Gain and 1.5dB Attenuation
Step, ROUT = 200Ω
Total ICC vs Attenuation Step
TYPICAL PERFOR A CE CHARACTERISTICS
UW
(Standard Mode) Two tones, 200kHz spacing,
TA = 25°C, ENA = ENB = 5V, VCC = 5V, VCCO = 3V, control input levels VIL = 0.6V, VIH = 3V unless otherwise noted. (Test circuit shown
in Figure 10)
FREQUENCY (MHz)
0
48
51
57
150
5514 G19
45
42
50 100 200
39
36
54
OIP3 (dBm)
25°C
–40°C
85°C
FREQUENCY (MHz)
0
48
51
57
150
5514 G20
45
42
50 100 200
39
36
54
OIP3 (dBm)
25°C
–40°C
85°C
FREQUENCY (MHz)
0
48
51
57
150
5514 G21
45
42
50 100 200
39
36
54
OIP3 (dBm)
MAX GAIN
1.5dB
ATTENUATION
STEP
ATTENUATION STEP (dB)
0
OIP3 (dBm)
46
47
48
21
1544 G22
44
41 369
12 15 18
49
45
43
42
3dB ATTENUATION STEP
(PGA0 = HIGH)
1.5dB ATTENUATION STEP
(PGA0 = LOW)
INPUT V
CC
(V)
4.5
50
60
70
25°C
85°C
–40°C
5.3
5514 G23
40
30
4.7 4.9 5.1 5.5
20
10
0
CURRENT (µA)
ATTENUATION STEP (dB)
0
130
CURRENT (mA)
135
140
145
150
160
36912
5514 G24
15 18 21
155
85°C
25°C
–40°C
Single-Ended Output Current
vs Attenuation Step
ATTENUATION STEP (dB)
0
1.40
VIN(BIAS) (V)
1.50
1.45
1.55
1.60
36912
5514 G26
15 18 21
85°C
25°C
–40°C
VIN(BIAS) vs Attenuation Step
9
LT5514
5514f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Pulse Response vs COUT at Max
Gain. Output Level is 2VP-P into
50Ω External Load
(Standard Mode) TA = 25°C, VCC = 5V, VCCO = 5V,
ENA = ENB = 3V, control input levels VIL = 0.6V, VIH = 3V unless otherwise noted. Test circuit shown in Figure 10 unless otherwise
noted. Note 1: Subtract 0.75ns calibration delay from output plots to estimate the LT5514 group delay. Note 2: When specified, COUT
is connected differentially across the LT5514 OUT+, OUT– output pins.
2ns/DIV 5514 G27
0pF
22pF TO
GROUND
EACH
OUTPUT
COUT
0pF
1pF
1.8pF
3.3pF
4.7pF
6.8pf
10pF
11pF
18pF
INPUT
RMATCH = 255Ω
2ns/DIV 5514 G28
4VP-P
3VP-P
2VP-P
INPUTS
COUT = 0.82pF
1ns/DIV
5514 G29
MAX GAIN
1.5dB STEP
3dB STEP
6dB STEP
12dB STEP
INPUT
Pulse Response vs Output Level at
Max Gain. Indicated Voltage
Levels are into 50Ω External Load
Pulse Response vs Attenuation,
Output Level is 4VP-P at Max Gain
into 50Ω External Load
Pulse Response vs Attenuation,
Output Level is 2VP-P at Max Gain
into 50Ω External Load
1ns/DIV
5514 G30
MAX GAIN
1.5dB STEP
3dB STEP
6dB STEP
12dB STEP
INPUT
R
MATCH
= 255Ω
Pulse Response vs Attenuation,
Output Level is 2VP-P at Max Gain
into 50Ω External Load
1ns/DIV
5514 G31
MAX GAIN
1.5dB STEP
3dB STEP
6dB STEP
12dB STEP
INPUT
R
MATCH
= 255Ω, C
OUT
= 1.8pF
Pulse Response vs Attenuation,
LT5514 Levels are: VIN = 66mVP-P,
VOUT = 2VP-P at Max Gain
1ns/DIV 5514 G32
MAX GAIN
1.5dB STEP
3dB STEP
6dB STEP
12dB STEP
INPUT
ROUT = 100Ω
FIGURE 9 TEST CIRCUIT
Pulse Response vs Attenuation,
LT5514 Levels are: VIN = 66mVP-P,
VOUT = 4VP-P at Max Gain
1ns/DIV 5514 G33
MAX GAIN
1.5dB STEP
3dB STEP
6dB STEP
12dB STEP
INPUT
ROUT = 200Ω
FIGURE 9 TEST CIRCUIT
10
LT5514
5514f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Total ICC vs VCC
Single-Ended Output Current
vs Attenuation Step
(Low Power Mode) TA = 25°C, VCC = 5V, VCCO = 5V,
ENA = 3V, ENB = 0.6V or ENA = 0.6V, ENB = 3V, control input levels VIL = 0.6V, VIH = 3V unless otherwise noted. (Test circuit shown in
Figure 10)
VIN(BIAS) vs Attenuation Step
Noise Figure vs Frequency
Harmonic Distortion vs POUT at
50MHz, Max Gain, ROUT = 200Ω
OIP3 vs Frequency at Pin = –23dBm,
Max Gain and 1.5dB Attenuation
Step, ROUT = 200Ω
FREQUENCY (MHz)
0
OIP3 (dBm)
42
45
48
200
5514 G34
39
36
30 50 100 150
33
54
51
1.5dB
ATTENUATION
STEP
MAX GAIN
P
OUT
(dBm)
–6
HD(dBc)
–80
–50
–45
–40
069
5514 G35
–90
–60
–70
–85
–55
–100
–95
–65
–75
–3 312 15
HD2HD3
HD4HD5
FREQUENCY (MHz)
0
7.0
NF (dB)
7.5
8.0
8.5
9.0
100 200 300 400
5514 G36
9.5
10.0
50 150 250 350
MAX GAIN
1.5dB ATTENUATION STEP
(PGA0 = LOW)
3dB ATTENUATION STEP
(PGA1 = LOW)
NF vs Attenuation Step at
Freq = 100MHz
ATTENUATION STEP (dB)
0
NF (dB)
18
24
30
15
5514 G37
12
6
15
21
27
9
3
03 6 9 12 18 21
Output Noise Floor vs Attenuation
Step, Freq = 100MHz, ROUT = 200Ω
ATTENUATION STEP (dB)
0
–142
NOISE FLOOR (dBm/Hz)
–141
–140
–139
–138
–136
36912
5514 G38
1815 21
–137
PGA1 = HIGH
PGA1 = LOW
Pulse Response vs Output Level at
Max Gain. Indicated Voltage Levels
are into 50Ω External Load
2ns/DIV 5514 G39
2VP-P
1.5VP-P
1VP-P
INPUTS
COUT = 0.82pF
ATTENUATION STEP (dB)
0
65
CURRENT (mA)
68
70
73
75
80
36912
5514 G40
15 18 21
78 85°C
25°C
–40°C
ATTENUATION STEP (dB)
0
19.0
CURRENT (mA)
20.0
19.5
20.5
21.0
36912
5514 G41
15 18 21
85°C
25°C
–40°C
ATTENUATION STEP (dB)
0
1.40
VIN(BIAS) (V)
1.50
1.45
1.55
1.60
36912
5514 G42
15 18 21
85°C
25°C
–40°C
11
LT5514
5514f
UU
U
PI FU CTIO S
ENA (Pin 1): Enable Pin for Amplifier A. When the input
voltage is higher than 3V, amplifier A is turned on. When
the input voltage is less than or equal to 0.6V, amplifier A
is turned off. This pin is internally pulled to ground if not
connected.
V
CC1
(Pin 2): Power Supply. This pin is internally connected
to V
CC2
(Pin 19). Decoupling capacitors (1000pF and 0.1µF
for example) may be required in some applications.
GND (Pins 3, 4, 7, 8, 13, 14, 17, 18): Ground.
IN
+
(Pin 5): Positive Signal Input Pin with Internal DC
Bias.
IN
–
(Pin 6): Negative Signal Input Pin with Internal DC
Bias.
PGA0 (Pin 9): Amplifier PGA Control Input Pin for the
1.5dB Attenuation Step (see Programmable Gain table).
Input is high when input voltage is greater than 3V. Input
is low when input voltage is less than or equal to 0.6V. This
pin is internally pulled to ground if not connected.
PGA1 (Pin 10): Amplifier PGA Control Input Pin for the
3dB Attenuation Step (see Programmable Gain table).
Input is high when input voltage is greater than 3V. Input
is low when input voltage is less than or equal to 0.6V. This
pin is internally pulled to ground if not connected.
PGA2 (Pin 11): Amplifier PGA Control Input Pin for the
6dB Attenuation Step (see Programmable Gain table).
Input is high when input voltage is greater than 3V. Input
is low when input voltage is less than or equal to 0.6V. This
pin is internally pulled to ground if not connected.
PGA3 (Pin 12): Amplifier PGA Control Input Pin for 12dB
Attenuation Step (see Programmable Gain table). Input is
high when input voltage is greater than 3V. Input is low
when input voltage is less than or equal to 0.6V. This pin
is internally pulled to ground if not connected.
OUT
+
(Pin 15): Positive Amplifier Output. A transformer
with center tap tied to V
CC
or a choke inductor is recom-
mended to source the DC quiescent current.
OUT
–
(Pin 16): Negative Amplifier Output. A transformer
with center tap tied to V
CC
or a choke inductor is recom-
mended to source the DC quiescent current.
V
CC2
(Pin 19): Power Supply. This pin is internally con-
nected to V
CC1
(Pin 2).
ENB (Pin 20): Enable Pin for Amplifier B. When the input
voltage is higher than 3V, amplifier B is turned on. When
the input voltage is less than or equal to 0.6V, amplifier B
is turned off. This pin is internally pulled to ground if not
connected.
Exposed Pad (Pin 21): Ground. This pin must be soldered
to the printed circuit board ground plane for good heat
transfer.
BLOCK DIAGRA
W
AMPLIFIER A
OUT+
AMPLIFIER B
1
15
OUT–16
20
ENABLE
CONTROL
ENA 21
5514 F01
ENB
910
GAIN CONTROL
LOGIC
ATTENUATOR
LT5514
PGA0PGA1
1112
PGA2PGA3
192
6
5
VOLTAGE REGULATOR
AND BIAS
VCC2
VCC1
IN+
IN–
GND (3, 4, 7, 8
13, 14, 17, 18)
RIN
100Ω
Figure 1. Functional Block Diagram
12
LT5514
5514f
APPLICATIO S I FOR ATIO
WUUU
Circuit Operation
The LT5514 is a high linearity amplifier with high imped-
ance output (Figure 1). It consists of the following
sections:
• An input variable attenuator “gain-control” block with
100Ω input impedance
• Two parallel, differential transconductance amplifiers,
each with independent enable inputs
• An internal bias block with internal voltage regulator
• A gain control logic block
The LT5514 amplifier provides amplification with very low
distortion using a linearized open-loop architecture. In
contrast with high linearity amplifiers employing negative
feedback, the LT5514 offers:
• Stable operation for any practical load
• A capacitive output reactance (not inductive) that pro-
vides peaking free AC response to capacitive loads
• Exceptional reverse isolation of –100dB at 50MHz and
–78dB at 300MHz (package and board leakage limited)
The LT5514 is a transconductance amplifier and its opera-
tion can be understood conceptually as consisting of two
steps: First, the input signal voltage is converted to an
output current. The intermodulation distortion (in dBc) of
the LT5514 output current is determined by the input
signal level, and is almost independent of the output load
conditions. Thus, the LT5514’s input IP3 is also nearly
independent of the output load.
Next, the external output load (R
OUT
) converts the output
current to output voltage (or power). The LT5514’s volt-
age and power gain both increase with increasing R
OUT
.
Accordingly, the output power and output IP3 also im-
prove with increasing R
OUT
. The actual output linearity
performance in the application will thus be set by the
choice of output load, as well as by the output network.
Maximum Gain Calculation
The maximum power gain (with the 0dB attenuation step)
is:
G
PWR
(dB) = 10 • log(g
m2
• R
IN
• R
OUT
)
where:
g
m
is the LT5514 transconductance = 0.3S in Standard
mode (0.15S in Low Power mode).
R
IN
is the LT5514 differential input impedance ≅ 108Ω
in Standard mode (122Ω in Low Power mode). Input
impedance matching is assumed.
R
OUT
is the external differential output impedance as
seen by the LT5514’s differential outputs. R
OUT
should
be distinguished from the actual load impedance, R
LOAD
,
which will typically be coupled to the LT5514 output by
an impedance transformation network.
The power gain as a function of R
OUT
is plotted in Figure␣ 2.
The ideal curves are straight lines. The curved lines
indicate the roll-off due to the finite (noninfinite) output
resistance of the LT5514.
ROUT (Ω)
20
25
GAIN (dB)
30
35
40
45
100 1000 2000
5514 F02
20
15
5
0
10 STANDARD MODE
LOW POWER MODE
STD WITH RO
LP WITH RO
Figure 2. Power Gain as a Function of ROUT
The actual available output power (as well as power gain
and OIP3) will be reduced by losses in the output interface,
consisting of:
• The insertion loss of the output impedance transforma-
tion network (for example the transformer insertion
loss in Figure 6)
• About –3dB loss if a matching resistor (R
MATCH
in
Figure 6) is used to provide output load impedance
back-matching (for example when driving transmis-
sion lines)
13
LT5514
5514f
Input Interface
For the lowest noise and highest linearity, the LT5514
should be driven with a differential input signal. Single-
ended drive will severely degrade linearity and noise
performance.
Example input matching networks are shown in Figures 3
and 4.
Input matching network design criteria are:
• DC block the LT5514 internal bias voltage (see Input
Bias Voltage section for DC coupling information)
• Match the source impedance to the LT5514, R
IN
≅ 108Ω
• Provide well balanced differential input drive (capacitor
C2 in Figure 4)
• Minimize insertion loss to avoid degrading the noise
figure (NF)
Note: In Figure 5, (choke) inductors may be placed in
parallel with or used to replace resistors R1 and R2, thus
eliminating the DC voltage drop across these resistors.
APPLICATIO S I FOR ATIO
WUUU
+
–
R
IN
100Ω
IN
+
V
SRC
LT5514
LT5514 F03
C1
R1
50Ω
R2
50ΩC2 IN
–
Figure 3. Input Capacitively-Coupled to a Differential Source
+
–
R
IN
100Ω
IN
+
C2
0.33µF
LT5514
LT5514 F04
R
SRC
50ΩT1
1:2
•
•
•
V
SRC
IN
–
Figure 4. Input Transformer-Coupled to a Single-Ended Source
Output Interface
The output interface network provides an impedance
transformation between the actual load impedance, R
LOAD
,
and the LT5514 output loading, R
OUT
, chosen to maximize
power or linearity, or to minimize output noise, or for some
other criteria as explained in the following sections.
Two examples of output matching networks are shown in
Figures 5 and 6 (as implemented in the LT5514 demo
boards).
Figure 5. Output Impedance-Matched
and Capacitively Coupled to a Differential Load
+
–
R
IN
100Ω
IN
+
LT5514 C1
C3
C2
R1
51ΩR2
51Ω
V
OSUP
R
LOAD
50Ω
R
LOAD
50Ω
R
OUT
LT5514 F05
IN
–
Figure 6. Output Impedance-Matched and
Transformer-Coupled to a Single-Ended Load
+
–
RIN
100Ω
IN+LT5514
C1
RMATCH
255Ω
(OPTIONAL)
VOSUP
RLOAD
50Ω
T2
4:1
ROUT
LT5514 F06
IN–
•
•
•
Output network design criteria are:
• Provide DC isolation between the LT5514 DC output
voltage and R
LOAD
.
• Provide a path for the output DC current from the output
voltage source V
OSUP
.
• Provide an impedance transformation, if required, be-
tween the load impedance, R
LOAD
, and the optimum
R
OUT
loading.
• Set the bandwidth of the output network.
• Optional: Provide board output impedance matching
using resistor R
MATCH
(when driving a transmission
line).
• Use high linearity passive parts to avoid introducing
noninearity.
Note that there is a noise penalty of up to 6dB when using
power delivered by only one output in Figure 5.
14
LT5514
5514f
APPLICATIO S I FOR ATIO
WUUU
Clipping Free Operation
The LT5514 is a class A amplifier. To avoid signal distor-
tion, the user must ensure that the LT5514 outputs do not
enter into current or voltage limiting. The following discus-
sion applies to standard mode operation at maximum gain.
To avoid current clipping, the output signal current should
not exceed the DC quiescent current, I
OUT
= 40mA (typi-
cal). Correspondingly, the maximum input voltage,
V
IN(MAX)
, is I
OUT
/g
m
= 133mV (peak). In power terms,
P
IN(MAX)
= –10.8dBm (assuming R
IN
= 108Ω).
To avoid output voltage clipping (due to LT5514 output
stage saturation or breakdown), the single-ended output
voltage swing should stay within the specified limits; i.e.,
2V ≤ VOUT ≤ 8V. For a DC output bias of 5V, the maximum
single ended swing will be 3Vpeak and the maximum
differential swing will be 6Vpeak. The simultaneous onset
of both current and voltage limiting occurs when ROUT =
6Vpeak/40mA =150Ω (typ) for a maximum POUT =
20.8dBm. This calculation applies for a sinusoidal signal.
For nonsinusoidal signals, use the appropriate crest fac-
tor to calculate the actual maximum power that avoids
output clipping.
For nonoptimal R
OUT
values, the maximum available out-
put power will be lower and can be calculated (considering
current limiting for R
OUT
< 150Ω, and voltage limiting for
R
OUT
> 150Ω). The result of this calculation is shown in
Figure 7.
The LT5514 input should not be overdriven (P
IN
>
–10dBm). The consequences of overdrive are reduced
bandwidth and, when the frequency is greater than 50MHz,
reduced output power.
Input Bias Voltage
The LT5514 IN
+
, IN
–
signal inputs are internally biased to
1.48V common mode when enabled, and to 1.26V in
shutdown mode. These inputs are typically coupled by
means of a capacitor or a transformer to a signal source,
and impedance matching is assumed. In shutdown mode,
the internal bias can handle up to 1µA leakage on the input
coupling capacitors. This reduces the turn-on delay due to
the input coupling RC time constant when exiting shut-
down mode.
If DC coupling to the input is required, the external
common mode bias should track the LT5514’s internal
common mode level. The DC current from the LT5514
inputs should not exceed I
IN(SINK)
= –400µA and I
IN(SOURCE)
= 800µA in Standard mode and half of these values in Low
Power mode.
Stability Considerations
The LT5514’s open-loop architecture allows it to drive any
practical load. Note that LT5514 gain is proportional to the
load impedance, and may exceed the reverse isolation at
frequencies above 1GHz if the LT5514’s outputs are left
unloaded, with instability as the undesirable consequence.
In such cases, placing a resistive differential load (e.g., 2k)
or a small capacitor at the LT5514 outputs can be used to
limit the maximum gain.
The LT5514 has about 30GHz gain-bandwidth product.
Hence, attention must be paid to the printed circuit board
layout to avoid output pin to input pin signal coupling (the
evaluation board layout is a good example). Due to the
LT5514’s internal power supply regulator, external supply
decoupling capacitors typically are not required. Likewise,
decoupling capacitors on the LT5514 control inputs typi-
cally are not needed. Note, however, that the Exposed Pad
on the LT5514 package must be soldered to a good ground
plane on the PCB.
PGA Function, Linearity and NF
As described in the Circuit Operation section, the LT5514
consists of a variable (step) attenuator followed by a high
Figure 7. Maximum Output Power as a Function of ROUT
R
OUT
(Ω)
20
P
OUT(MAX)
(dBm)
25
100 1000 2000
5514 F07
20
15
5
0
10
STANDARD MODE
LOW POWER MODE
V
CC
= V
CCO
= 5V
CURRENT
LIMIT VOLTAGE
LIMIT
15
LT5514
5514f
gain output amplifier. The overall gain of the LT5514 is
digitally controlled by means of four gain control pins with
internal pull-down. Minimum gain is programmed when
the gain control pins are set low or left floating. In
shutdown mode, these PGA inputs draw <10µA leakage
current, regardless of the applied voltage.
The 6dB and 12dB attenuation steps (PGA2 and PGA3) are
implemented by switching the amplifier inputs to an input
attenuator tap. The 3dB attenuation step (PGA1) changes
the amplifier transconductance. The output IP3 is approxi-
mately independent of the PGA1, PGA2 and PGA3 gain
settings. However, the 1.5dB attenuation step utilizes a
current steering technique that disables the internal linear-
ity compensation circuit, and the OIP3 can be reduced by
as much as 6dB when PGA0 is low. Therefore, to achieve
the LT5514’s highest linearity performance, the PGA0 pin
should be set high.
The LT5514 noise figure is 7.3dB in the maximum gain state.
For the –3dB attenuation setting, the NF is 7.6dB. The noise
figure increases in direct proportion to the amount of pro-
grammed gain reduction for the 1.5dB, 6dB and 12dB steps.
The output noise floor is proportional to the output load
impedance, R
OUT
. It is almost constant for PGA1 = high
and for any PGA0, PGA2, PGA3 state. When PGA1 = low,
the output noise floor is 2.7dB lower (see Typical Perfor-
mance Characteristics).
Other Linearity Considerations
LT5514 linearity is a strong function of signal frequency.
OIP3 decreases about 13dB for every octave of frequency
increase above 100MHz.
As noted in the Circuit Operation section, at any given
frequency and input level, the LT5514 provides a current
output with fairly constant intermodulation distortion fig-
ure in dBc, regardless of the output load value. For higher
R
OUT
values, more gain and output power is available, and
better OIP3 figures can be achieved. However, high R
OUT
values are not easily implemented in practice, limited by
the availability of high ratio output impedance transforma-
tion networks.
Linearity can also be limited by the output RC time con-
stant (bandwidth limitations), particularly for high R
OUT
values. A solution is outlined in the Bandpass Applications
section.
The LT5514 linearity degrades when common mode sig-
nal is present. The input transformer center tap should be
decoupled to ground to provide a balanced input differen-
tial signal and to avoid linearity degradation for high
attenuation steps. When the signal frequency is lower than
50MHz, and there is significant common mode signal,
then high attenuation settings may result in degraded
linearity.
At signal frequencies below 100MHz, the LT5514’s inter-
nal linearity compensation circuitry may provide “sweet
spots” with very high OIP3, in excess of +60dBm. This
almost perfect distortion correction cannot be sustained
over the full operating temperature range and with varia-
tions of the LT5514 output load (complex impedance
Z
OUT
). Users are advised to rely on data shown in the
Typical Performance Characteristics curves to estimate
the dependable linearity performance.
Wideband Applications
At low frequencies, the value of the decoupling capacitors,
choke inductors and choice of transformer will set the
minimum frequency of operation. Output DC coupling is
possible, but this typically reduces the LT5514’s output
DC bias voltage, and thus the output swing and available
power.
At high frequencies, the output RC time constants set an
upper limit to the maximum frequency of operation in the
case of the wideband output networks presented so far.
For example the LT5514 output capacitance, C
OUT
= 1.9pF,
and a pure resistive load, R
OUT
= 200Ω, will set the –3dB
bandwidth to about 400MHz. In an actual application, the
R
LOAD
• C
LOAD
product may be even more restrictive. The
use of wideband output networks will not only limit the
bandwidth, but will also degrade linearity because part of
the available power is wasted driving the capacitive load.
The LT5514’s output reactance is capacitive. Therefore
improved AC response is possible by using external series
output inductors. When driving purely resistive loads, an
inductor in series with the LT5514 output may help to
achieve maximally flat AC response as exemplified in the
characterization setup schematic (Figure 9).
APPLICATIO S I FOR ATIO
WUUU
16
LT5514
5514f
For example, for R
OUT
= 200Ω, L1, L2 = 33nH results in
500MHz bandwidth.
The series inductor can extend the application bandwidth,
but it provides no improvement in linearity performance.
Series inductance may also produce peaking in the AC
response. This can be the case when (high Q) choke
inductors are used in an output interface such as in
Figure␣ 5, and the PCB trace (connection) to the load is too
long. Since the LT5514’s output impedance is relatively
high, the PCB trace acts as a series inductor. The most
direct solution is to shorten the connection lines by
placing the driver closer to the load. Another solution to
flatten the AC response is to place resistance close to the
LT5514 outputs. In this way the connection line behaves
more like a terminated transmission line, and the AC
peaking due to the capacitive load can be removed.
Bandpass Applications
For narrow band IF applications, the LT5514’s output
capacitance and the application load capacitance can be
incorporated as part of an LC impedance transformation
network, giving improved linearity performance for signal
frequencies greater than 100MHz. Figure 8 is an example
of such a network.
The network consists of two parallel resonant LC tank
circuits critically coupled by capacitors C1 and C2. The
R
OUT
to R
LOAD
transformation ratio in this particular
implementation is 2. The choice of impedance transfor-
mation ratio is more flexible than in the wideband case.
The LC network is a bandpass filter, a useful feature in
many applications.
A variety of bandpass matching network configurations
are conceivable, depending on the requirements of the
particular application. The design of these networks is
facilitated by the fact that the LT5514 outputs are not
destabilized by reactive loading.
Note that these LC networks may distort the output signal
if their amplitude and phase response exhibit nonlinear
behavior. For example, if resistors R1 and R2 in Figure 5
are replaced with LC resonant tank circuits, then severe
OIP3 degradation may occur (e.g., 4dB to 6dB at 200MHz).
Low Output Noise Floor Applications
In some applications the maximum output noise floor is
specified. The LT5514 output noise floor is elevated above
the available noise power (–174dBm/Hz into 50Ω) by the
NF + Gain. Consequently, reduction of the LT5514’s power
gain is the only way to reduce the output noise floor.
In fixed gain applications, the LT5514 can be set to 3dB
attenuation relative to maximum gain. As shown in the
Typical Performance Characteristics, this gives a 2.8dB
reduction in the output noise floor with no loss of linearity.
In general, the output noise floor can be reduced by
decreasing R
OUT
(and hence power gain), at the cost of
reduced OIP3.
In some situations, it may be feasible to use two LT5514
parts in parallel. In this case, the effective g
m
doubles,
APPLICATIO S I FOR ATIO
WUUU
–
+
100
C9
0.33µF
T1
1:2
DUT
LT5514
R
OUT
200Ω
IN
+
IN
–
C8
0.1µF
PGA0 PGA1 PGA2 PGA3
R
SRC
50Ω
V
SRC
V
CC
ENA ENB
R
LOAD
100Ω
C6
2.2pF
GAIN = 33dB
OIP3 (LOAD) = +41dBm
UP TO 9dBm PER TONE
1dB BANDWIDTH:
f
L
= 130MHz
f
U
= 220MHz
C1
12pF
L6
56nH L3
56nH
L5
56nH
C7
0.1µF
NOTE:
C3 + C
LOAD
= 12pF
C4 + C
LOAD
= 12pF
C5
5.6pF
C4
C3
C2
12pF L4
56nH
R
LOAD
50ΩC
LOAD
5514 F08
C
LOAD
V
OSUP
R
LOAD
50Ω
TC2-1T
Figure 8. Bandpass Output Transformation Network Example
17
LT5514
5514f
allowing all impedances to be scaled downward by a factor
of two. The NF and power gain remain the same in this
case, but the OIP3 increases by 3dB. Then, with a further
reduction of R
OUT
by a factor of two, the gain and output
noise floor decrease by 3dB, while yielding the same
linearity as for one part. As an added benefit, two LT5514
parts in parallel can drive an R
OUT
reduced by a factor of
four, thus relaxing or eliminating the need in some cases
for an output impedance transformation network.
Low Power Mode
As described in the Circuit Operation section, the LT5514
consists of two parallel gain blocks. These blocks are in-
dependently enabled or disabled. “Low Power mode”
refers to circuit operation with only a single block enabled.
An amplifier in Low Power mode will have the same basic
characteristics as in Standard mode (both gain blocks
enabled), except that the g
m
decreases from 0.3S to 0.15S,
and the maximum output current is halved. In Low Power
mode, the standard LT5514 evaluation board will produce
about 6dB less gain, (because the LT5514’s g
m
is reduced,
while R
IN
and R
OUT
are the same) and 6dB lower OIP3.
LT5514 Characterization
The LT5514’s typical performance data are based on the
test circuits shown in Figures 9 and 10. Figure 9 does not
necessarily reflect the use of the LT5514 in an actual
application. (For that, see the Application Boards section.)
APPLICATIO S I FOR ATIO
WUUU
–
+
T1
1:1 T1
1:1
C7
47nF
DUT
LT5514
R
OUT
V
CCO
MONITOR
IN
+
IN
–
C2
0.1µF
C1
0.33µF
C8
47nF
ETC-1-
1-13
PGA0 PGA1 PGA2 PGA3
R
SRC
50Ω
R9
35.7ΩR10
35.7Ω
R7
35.7Ω
R8
35.7Ω
R5
51k R6
51k
C
OUT
(OPT)
C
OUT
(OPT)
V
SRC
V
CC
ENA ENB
L1
(OPT) R3
37.4Ω
R1
25ΩR1
25Ω
R
LOAD
50Ω
R4
37.4Ω
C4
0.1µF
C5
47nF
C6
47nF
L2
(OPT)
C3
4.7µF
5514 F09
V
OSUP
ETC-1-
1-13
ATT =
7.7dB R
OUT
100Ω
200Ω
R3, R4
37.4Ω
87.4Ω
ATT
9dB
12dB
Figure 9. Characterization Board (Simplified Schematic)
C1
0.47µF
J1
0
T1
1:2
IF
IN T2
4:1
•
•
•
C2
0.1µF
R
OUT
100Ω
R
LOAD
50Ω
5514 F10
V
OSUP
TC2-1T TC4-1W J2
0
TRANSFORMER DEMO BOARD
R
MATCH
255Ω
ENA
V
CC1
GND
GND
IN
+
IN
–
GND
GND
PGA0
PGA1
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
ENB
V
CC2
GND
GND
OUT
–
OUT
+
GND
GND
PGA3
PGA2
C3
4.7µFIF
OUT
C4
0.1µF
LT5514
PGA1
ENA ENB
V
CC
PGA0 PGA2 PGA3
Figure 10. Output Transformer Application Board (Simplified Schematic)
18
LT5514
5514f
Rather, it represents a compromise that most accurately
measures the actual operation of the part by itself,
undistorted by the artifacts of the impedance transformation
network, or by external bandwidth limiting factors. Balun
transformers are used to interface with single-ended test
equipment. Input and output resistive attenuators (not
shown) provide broadband I/O impedance control. The
L1, L2 inductors are selected for maximally flat AC output
response. C
OUT
(normally open) shows the placement of
capacitive loading when this is specified as a
characterization variable. The V
CCO
monitor pin allows
setting the output DC level (5V typical) by adjusting
voltage V
OSUP
.
Application (Demo) Boards
The LT5514 demo boards are provided in the versions
shown in Figure 10 (with output transformer) and Fig-
ure␣ 11 (without output transformer). All I/O signal ports
are matched to 50Ω. Moreover, 1k resistors (not shown)
connect all six control pins (ENA, ENB, PGA0, PGA1,
PGA2, PGA3) to V
CC
, such that the LT5514 is shipped in
maximum gain state and with both amplifier blocks en-
abled (Standard mode).
The gain setting can be changed by connecting the control
pins to ground. Test points (TP1, TP2, TP3) are provided
to monitor the input and output DC bias voltage. Jumper
J1 can be removed when differential input is desired, but
APPLICATIO S I FOR ATIO
WUUU
in that case, T1 should be changed to a 1:1 center-tap
transformer to preserve 50Ω input matching. The demo
board is shipped with optional output back-matching
resistor R
MATCH
= 255Ω. This results in a net output load,
R
OUT
= 100Ω, presented to the LT5514.
The Output Transformer Application Board (Figure 10) is
one example of an output impedance transformation
(T2 transformer). For the Typical Performance Character-
istics curves, all linearity tests are performed on this
board. By removing R
MATCH
, the performance with R
OUT
= 200Ω can be evaluated (provided the lack of impedance
back-matching is suitably remedied). Measured OIP3 for
both cases, R
OUT
= 100Ω and 200Ω, is shown in Figure 12.
C1
0.47µF
J1
0
T1
1:2
IF
IN
C2
0.1µF
R
OUT
50Ω
R
LOAD
100Ω
5514 F11
V
OSUP
TC2-1T
DIFFERENTIAL OUTPUT
RESISTIVE DEMO BOARD
ENA
V
CC1
GND
GND
IN
+
IN
–
GND
GND
PGA0
PGA1
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
ENB
V
CC2
GND
GND
OUT
–
OUT
+
GND
GND
PGA3
PGA2
R1
50ΩR2
50Ω
C3
4.7µFIF
OUT
C4
0.1µF
C5
47nF
C6
47nF
LT5514
PGA1
ENA ENB
V
CC
PGA0 PGA2 PGA3
J2
0PEN
Figure 11. Wideband Differential Output Application Board (Simplified Schematic)
FREQUENCY (MHz)
0
OIP3 (dBm)
46
49
52
200
5514 F12
43
40
34 50 100 150
37
58
55
DUT R
MATCH
= 255Ω
BOARD R
MATCH
= 255Ω
DUT R
MATCH
= OPEN
BOARD R
MATCH
= OPEN
Figure 12. Typical OIP3 for Transformer Board
19
LT5514
5514f
APPLICATIO S I FOR ATIO
WUUU
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
At high frequency, the difference between the top and
bottom curves in Figure 12 is simply power loss. Starting
from the LT5514 intrinsic performance at R
OUT
= 200Ω
(top curve), the next lower curve takes into account the
transformer insertion loss. The next curve below this
shows the LT5514 OIP3 with R
OUT
= 100Ω. The bottom
curve in the plot includes the effects of transformer
insertion loss, with R
OUT
= 100Ω, and the additional effect
of loss due to R
MATCH
.
The transformer board can provide a differential output
when Jumper J2 is removed.
The Wideband Differential Output Application Board (Fig-
ure 11) is an example of direct coupling (no transformer)
to the load, and has wider output bandwidth. This board
gives direct access to the LT5514’s output pins, and was
used for stability tests. Higher V
OSUP
(7V) is required to
compensate for the DC voltage drop on R1 and R2. Use
TP2, TP3 to monitor the actual LT5514 output bias volt-
age. By replacing R1 and R2 with inductors, this board can
operate with a 5V supply. However, this may limit the
minimum signal frequency. For example, an 820nH choke
inductor will limit the lowest signal frequency to 40MHz.
U
PACKAGE DESCRIPTIO
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation CB
FE20 (CB) TSSOP 0204
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
RECOMMENDED SOLDER PAD LAYOUT
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
134
5678910
111214 13
6.40 – 6.60*
(.252 – .260)
3.86
(.152)
2.74
(.108)
20 1918 17 16 15
1.20
(.047)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC 0.195 – 0.30
(.0077 – .0118)
TYP
2
2.74
(.108)
0.45 ±0.05
0.65 BSC
4.50 ±0.10
6.60 ±0.10
1.05 ±0.10
3.86
(.152)
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
20
LT5514
5514f
LINEAR TECHNOLOGY CORPORATION 2004
LT/TP 0504 1K • PRINTED IN THE USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
Infrastructure
LT5511 High Linearity Upconverting Mixer RF Output to 3GHz, 17dBm IIP3, Integrated LO Buffer
LT5512 DC-3GHz High Signal Level Downconverting Mixer DC to 3GHz, 21dBm IIP3, Integrated LO Buffer
LT5515 1.5GHz to 2.5GHz Direct Conversion Quadrature Demodulator 20dBm IIP3, Integrated LO Quadrature Generator
LT5516 0.8GHz to 1.5GHz Direct Conversion Quadrature Demodulator 21.5dBm IIP3, Integrated LO Quadrature Generator
LT5517 40MHz to 900MHz Quadrature Demodulator 21dBm IIP3, Integrated LO Quadrature Generator
LT5519 0.7GHz to 1.4GHz High Linearity Upconverting Mixer 17.1dBm IIP3 at 1GHz, Integrated RF Output Transformer with 50Ω
Matching, Single-Ended LO and RF Ports Operation
LT5520 1.3GHz to 2.3GHz High Linearity Upconverting Mixer 15.9dBm IIP3 at 1.9GHz, Integrated RF Output Transformer with 50Ω
Matching, Single-Ended LO and RF Ports Operation
LT5522 600MHz to 2.7GHz High Signal Level Downconverting Mixer 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB,
50Ω Single-Ended RF and LO Ports
RF Power Detectors
LT5504 800MHz to 2.7GHz RF Measuring Receiver 80dB Dynamic Range, Temperature Compensated,
2.7V to 5.25V Supply
LTC®5505 RF Power Detectors with >40dB Dynamic Range 300MHz to 3GHz, Temperature Compensated, 2.7V to 6V Supply
LTC5507 100kHz to 1000MHz RF Power Detector 100kHz to 1GHz, Temperature Compensated, 2.7V to 6V Supply
LTC5508 300MHz to 7GHz RF Power Detector 44dB Dynamic Range, Temperature Compensated, SC70 Package
LTC5509 300MHz to 3GHz RF Power Detector 36dB Dynamic Range, Low Power Consumption, SC70 Package
LTC5530 300MHz to 7GHz Precision RF Power Detector Precision V
OUT
Offset Control, Shutdown, Adjustable Gain
LTC5531 300MHz to 7GHz Precision RF Power Detector Precision V
OUT
Offset Control, Shutdown, Adjustable Offset
LTC5532 300MHz to 7GHz Precision RF Power Detector Precision V
OUT
Offset Control, Adjustable Gain and Offset
Low Voltage RF Building Blocks
LT5500 1.8GHz to 2.7GHz Receiver Front End 1.8V to 5.25V Supply, Dual-Gain LNA, Mixer, LO Buffer
LT5502 400MHz Quadrature IF Demodulator with RSSI 1.8V to 5.25V Supply, 70MHz to 400MHz IF, 84dB Limiting Gain,
90dB RSSI Range
LT5503 1.2GHz to 2.7GHz Direct IQ Modulator and 1.8V to 5.25V Supply, Four-Step RF Power Control,
Upconverting Mixer 120MHz Modulation Bandwidth
LT5506 500MHz Quadrature IF Demodulator with VGA 1.8V to 5.25V Supply, 40MHz to 500MHz IF, –4dB to 57dB
Linear Power Gain, 8.8MHz Baseband Bandwidth
LT5546 500MHz Ouadrature IF Demodulator with 17MHz Baseband Bandwidth, 40MHz to 500MHz IF, 1.8V to 5.25V
VGA and 17MHz Baseband Bandwidth Supply, –7dB to 56dB Linear Power Gain
