ispLSI® 2096VE
3.3V In-System Programmable
SuperFAST™ High Density PLD
2096ve_08 1
Features
•SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC
—4000 PLD Gates
—96 I/O Pins, Six Dedicated Inputs
—96 Registers
—High Speed Global Interconnect
—Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
—Small Logic Block Size for Random Logic
—100% Functional, JEDEC and Pinout Compatible
with ispLSI 2096V Devices
—Pinout Compatible with ispLSI 2192VE
•3.3V LOW VOLTAGE 2096 ARCHITECTURE
—Interfaces with Standard 5V TTL Devices
•HIGH PERFORMANCE E2CMOS® TECHNOLOGY
—fmax = 250MHz Maximum Operating Frequency
—tpd = 4.0ns Propagation Delay
—Electrically Erasable and Reprogrammable
— Non-Volatile
—100% Tested at Time of Manufacture
—Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
—3.3V In-System Programmability (ISP™) Using
Boundary Scan Test Access Port (TAP)
—Open-Drain Output Option for Flexible Bus Interface
Capability, Allowing Easy Implementation of
Wired-OR or Bus Arbitration Logic
—Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
—Reprogram Soldered Devices for Faster Prototyping
•100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
•THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS
—Enhanced Pin Locking Capability
—Three Dedicated Clock Input Pins
—Synchronous and Asynchronous Clocks
—Programmable Output Slew Rate Control
—Flexible Pin Placement
—Optimized Global Routing Pool Provides Global
Interconnectivity
•LEAD-FREE PACKAGE OPTIONS
Description
The ispLSI 2096VE is a High Density Programmable
Logic Device containing 96 Registers, six Dedicated
Input pins, three Dedicated Clock Input pins, two dedi-
cated Global OE input pins and a Global Routing Pool
(GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 2096VE
features in-system programmability through the Bound-
ary Scan Test Access Port (TAP) and is 100% IEEE
1149.1 Boundary Scan Testable. The ispLSI 2096VE
offers non-volatile reprogrammability of the logic, as well
as the interconnect to provide truly reconfigurable sys-
tems.
The basic unit of logic on the ispLSI 2096VE device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. C7 (see Figure 1). There are a total of 24 GLBs in the
ispLSI 2096VE device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
The devices also have 96 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
individually programmed to be a combinatorial input,
output or bi-directional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mA. Each output can
Global Routing Pool
(GRP)
Output Routing Pool (ORP)
Output Routing Pool (ORP)
0919/2096VE
C7 C4
C5
C6
A4 A7
A6
A5
GLB
Logic
Array
DQ
DQ
DQ
DQ
Output Routing Pool (ORP)
Output Routing Pool (ORP)
C3 C0
C1
C2
B0 B3
B2
B1
Output Routing Pool (ORP)
Output Routing Pool (ORP)
B7
B6
B4
B5
A0
A1
A3
A2
Copyright © 2004 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. August 2004
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
Functional Block Diagram
Lead-
Free
Package
Options
Available!
Specifications ispLSI 2096VE
2
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.
Device pins can be safely driven to 5V signal levels to
support mixed-voltage systems.
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the two ORPs. Each
ispLSI 2096VE device contains three Megablocks.
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2096VE device are selected using
the dedicated clock pins. Three dedicated clock pins (Y0,
Y1, Y2) or an asynchronous clock can be selected on a
GLB basis. The asynchronous or Product Term clock can
be generated in any GLB for its own clock.
A0
A3
A1
A2
B7
B4
B6
B5
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Input Bus
Input Bus
Global
Routing
Pool
(GRP)
CLK 0
CLK 1
CLK 2
I/O 95
I/O 94
I/O 93
I/O 92
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 32
I/O 33
I/O 34
I/O 35
TDO/IN 2
TCK/IN 3
I/O 36
I/O 37
I/O 38
I/O 39
I/O 40
I/O 41
I/O 42
I/O 43
I/O 44
I/O 45
I/O 46
I/O 47
Y0
Y1
Y2
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 63
I/O 62
I/O 61
I/O 60
I/O 59
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
TDI/IN 0
TMS/IN 1
RESET
BSCAN
GOE 1
GOE 0
I/O 91
I/O 90
I/O 89
I/O 88
I/O 87
I/O 86
I/O 85
I/O 84
I/O 83
I/O 82
I/O 81
I/O 80
Input Bus
0917/2096VE
Megablock
C7 C6 C5 C4
A4 A5 A6 A7
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Input Bus
Input Bus
B0 B1 B2 B3
Output Routing Pool (ORP)
C3 C2 C1 C0
Output Routing Pool (ORP)
Input Bus
I/O 79
I/O 78
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64
IN 5
IN 4
Generic Logic
Blocks (GLBs)
Functional Block Diagram
Figure 1. ispLSI 2096VE Functional Block Diagram
Programmable Open-Drain Outputs
In addition to the standard output configuration, the
outputs of the ispLSI 2096VE are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. The default configuration when the
device is in bulk erased state is totem-pole configuration.
The open-drain/totem-pole option is selectable through
the ispLEVER software tools.
Specifications ispLSI 2096VE
3
Absolute Maximum Ratings 1
Supply Voltage Vcc .................................. -0.5 to +5.4V
Input Voltage Applied............................... -0.5 to +5.6V
Off-State Output Voltage Applied ............ -0.5 to +5.6V
Storage Temperature................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125 °C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
Table 2-0008/2096VE
PARAMETER MINIMUM MAXIMUM UNITS
Erase/Reprogram Cycles 10000 – Cycles
CSYMBOL
Table 2-0006/2096VE
C
PARAMETER
I/O Capacitance 6
UNITSTYPICAL TEST CONDITIONS
1
2
8Dedicated Input Capacitance pf
pf V = 3.3V, V = 0.0V
V = 3.3V, V = 0.0V
CC
CC I/O
IN
CClock and Global Output Enable Capacitance 10
3
pf V = 3.3V, V = 0.0V
CC Y
T
A
= 0°C to + 70°C
T
A
= -40°C to + 85°C
SYMBOL
Table 2-0005/2096VE
VCC
VIH
VIL
PARAMETER
Supply Voltage
Input High Voltage
Input Low Voltage
MIN. MAX. UNITS
3.0
3.0
2.0
V – 0.5
3.6
3.6
5.25
0.8
V
V
V
V
SS
Commercial
Industrial
DC Recommended Operating Condition
Capacitance (TA=25°C, f=1.0 MHz)
Erase Reprogram Specifications
Specifications ispLSI 2096VE
4
Input Pulse Levels
Table 2-0003/2096VE
Input Rise and Fall Time
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
GND to 3.0V
≤ 1.5ns 10% to 90%
1.5V
1.5V
See Figure 2
3-state levels are measured 0.5V from
steady-state active level.
TEST CONDITION R1 R2 CL
A 316Ω348Ω35pF
B∞348Ω35pF
316Ω348Ω35pF
Active High
Active Low
C316Ω348Ω5pF
∞348Ω5pF
Active Low to Z
at V +0.5V
OL
Active High to Z
at V -0.5V
OH
Table 2-0004/2096VE
VOL
SYMBOL
1. One output at a time for a maximum duration of one second. V = 0.5V was selected to avoid test
problems by tester ground degradation. Characterized but not 100% tested.
2. Measured using six 16-bit counters.
3. Typical values are at V = 3.3V and T = 25°C.
4. Maximum I varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum I .
Table 2-0007A/2096VE
1
VOH
IIH
IIL
IIL-isp
PARAMETER
IIL-PU
IOS
2, 4
ICC
Output Low Voltage
Output High Voltage
Input or I/O High Leakage Current
Input or I/O Low Leakage Current
BSCAN Input Low Leakage Current
I/O Active Pull-Up Current
Output Short Circuit Current
Operating Power Supply Current
I = 8 mA
I = -4 mA
0V ≤ V ≤ V (Max.)
0V ≤ V ≤ V
0V ≤ V ≤ V
V = 3.3V, V = 0.5V
V = 0.0V, V = 3.0V
f = 1 MHz
OL
OH
IN IL
IN IL
IN IL
CC OUT
CLOCK
IL IH
CONDITION MIN. TYP. MAX. UNITS
3
–
2.4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
125
0.4
–
10
10
-10
-150
-150
-100
–
V
V
µA
µA
µA
µA
µA
mA
mA
CC A
OUT
CC
CC
(V – 0.2)V ≤ V ≤ V
V ≤ V ≤ 5.25V
IN
CC CC
IN
CC
+ 3.3V
R1
R2CL*
Device
Output Test
Point
*CL includes Test Fixture and Probe Capacitance.
0213A/2096VE
Figure 2. Test Load
Switching Test Conditions
Output Load Conditions (see Figure 2)
DC Electrical Characteristics
Over Recommended Operating Conditions
Specifications ispLSI 2096VE
5
USE ispLSI 2096VE-250
FOR NEW DESIGNS
External Timing Parameters
Over Recommended Operating Conditions
t
pd1
UNITS
TEST
COND.
1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.
2. Standard 16-bit counter using GRP feedback.
3. Reference Switching Test Conditions section.
Table 2-0030A/2096VE
v.1.0
1
3
2
1
tsu2 + tco1
( )
DESCRIPTION#PARAMETER
A1Data Propagation Delay, 4PT Bypass, ORP Bypass ns
t
pd2 A2Data Propagation Delay ns
f
max A3Clock Frequency with Internal Feedback MHz
f
max (Ext.) –4Clock Frequency with External Feedback MHz
f
max (Tog.) –5Clock Frequency, Max. Toggle MHz
t
su1 –6GLB Reg. Setup Time before Clock, 4 PT Bypass ns
t
co1 A7GLB Reg. Clock to Output Delay, ORP Bypass ns
t
h1 –8GLB Reg. Hold Time after Clock, 4 PT Bypass ns
t
su2 –9GLB Reg. Setup Time before Clock ns
t
co2 A10GLB Reg. Clock to Output Delay ns
t
h2 –11GLB Reg. Hold Time after Clock ns
t
r1 A12Ext. Reset Pin to Output Delay, ORP Bypass ns
t
rw1 –13Ext. Reset Pulse Duration ns
t
ptoeen B14Input to Output Enable ns
t
ptoedis C15Input to Output Disable ns
t
goeen B16Global OE Output Enable ns
t
goedis C17Global OE Output Disable ns
t
wh –18External Synchronous Clock Pulse Duration, High ns
t
wl –19External Synchronous Clock Pulse Duration, Low ns
-250
MIN. MAX.
–4.0
–
250 –
–
–
–
–
0.0
3.3
–
0.0
–
3.5
–
–
–
–
1.8 –
1.8 –
158
277
2.5 3.0
–
–
3.7
–
6.0
–
6.0
6.0
4.0
4.0
6.0
-200
MIN. MAX.
– 4.5
–
200 –
–
–
–
–
0.0
4.0
–
0.0
–
4.0
–
–
–
–
2.5 –
2.5 –
133
200
3.0 3.5
–
–
4.5
–
6.0
–
8.0
8.0
5.0
5.0
7.0
Specifications ispLSI 2096VE
6
External Timing Parameters
Over Recommended Operating Conditions
tpd1
UNITS
-135
MIN.
TEST
COND.
1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.
2. Standard 16-bit counter using GRP feedback.
3. Reference Switching Test Conditions section.
Table 2-0030B/2096VE
v.1.0
1
3
2
1
tsu2 + tco1
( )
-100
MIN.MAX. MAX.
DESCRIPTION#PARAMETER
A1Data Propagation Delay, 4PT Bypass, ORP Bypass – 7.5 – 10.0 ns
tpd2 A2Data Propagation Delay – – ns
fmax A3Clock Frequency with Internal Feedback 135 – 100 – MHz
fmax (Ext.) –4Clock Frequency with External Feedback – – MHz
fmax (Tog.) –5Clock Frequency, Max. Toggle – – MHz
tsu1 –6GLB Reg. Setup Time before Clock, 4 PT Bypass – – ns
tco1 A7GLB Reg. Clock to Output Delay, ORP Bypass – – ns
th1 –8GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 – ns
tsu2 –9GLB Reg. Setup Time before Clock 6.0 – ns
tco2 A10GLB Reg. Clock to Output Delay – – ns
th2 –11GLB Reg. Hold Time after Clock 0.0 – ns
tr1 A12Ext. Reset Pin to Output Delay, ORP Bypass – – ns
trw1 –13Ext. Reset Pulse Duration 5.0 – ns
tptoeen B14Input to Output Enable – – ns
tptoedis C15Input to Output Disable – – ns
tgoeen B16Global OE Output Enable – – ns
tgoedis C17Global OE Output Disable – – ns
twh –18External Synchronous Clock Pulse Duration, High 3.5 – – ns
twl –19External Synchronous Clock Pulse Duration, Low 3.5 – – ns
100
143
5.0 4.0
–
–
5.0
–
9.0
–
12.0
12.0
7.0
7.0
10.0
77
100
6.5
0.0
8.0
0.0
6.5
5.0
5.0
13.0
5.0
6.0
12.5
15.0
15.0
9.0
9.0
Specifications ispLSI 2096VE
7
USE ispLSI 2096VE-250 FOR NEW DESIGNS
Internal Timing Parameters1
Over Recommended Operating Conditions
t
io
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Table 2-0036A/2096VE
v.1.0
Inputs
UNITS
-250
MIN. MAX.
DESCRIPTION#
2
PARAMETER
20 Input Buffer Delay ns
t
din 21 Dedicated Input Delay ns
t
grp 22 GRP Delay ns
GLB
t
1ptxor 25 1 Product Term/XOR Path Delay ns
t
20ptxor 26 20 Product Term/XOR Path Delay ns
t
xoradj 27 XOR Adjacent Path Delay ns
t
gbp 28 GLB Register Bypass Delay ns
t
gsu 29 GLB Register Setup Time before Clock ns
t
gh 30 GLB Register Hold Time after Clock ns
t
gco 31 GLB Register Clock to Output Delay ns
3
t
gro 32 GLB Register Reset to Output Delay ns
t
ptre 33 GLB Product Term Reset to Register Delay ns
t
ptoe 34 GLB Product Term Output Enable to I/O Cell Delay ns
t
ptck 35 GLB Product Term Clock Delay ns
ORP
t
ob 38 Output Buffer Delay ns
t
sl 39 Output Slew Limited Delay Adder ns
GRP
t
4ptbpc 23 4 Product Term Bypass Path Delay (Combinatorial) ns
t
4ptbpr 24 4 Product Term Bypass Path Delay (Registered) ns
t
orp 36 ORP Delay ns
t
orpbp 37 ORP Bypass Delay ns
Outputs
t
oen 40 I/O Cell OE to Output Enabled ns
t
odis 41 I/O Cell OE to Output Disabled ns
t
goe 42 Global Output Enable ns
t
gy0 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) ns
t
gy1/2 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line ns
Clocks
t
gr 45 Global Reset to GLB
0.5
0.7
0.2
2.8
2.8
2.8
0.0
–
–
0.2
0.3
3.7
2.9
3.6
1.4
2.0
1.5
2.0
1.1
0.4
2.4
2.4
1.6
1.0
1.2
3.9
–
–
–
–
–
–
–
0.8
1.7
–
–
–
–
0.8
–
–
–
–
–
–
–
–
–
1.0
1.2
–ns
Global Reset
-200
MIN. MAX.
0.5
1.1
0.6
2.9
2.9
2.9
0.0
–
–
0.3
0.4
4.3
3.9
4.0
1.5
2.0
1.4
1.9
1.5
0.5
3.0
3.0
2.0
1.2
1.4
3.6
–
–
–
–
–
–
–
1.2
1.8
–
–
–
–
1.0
–
–
–
–
–
–
–
–
–
1.2
1.4
–
Specifications ispLSI 2096VE
8
Internal Timing Parameters1
Over Recommended Operating Conditions
t
io
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Table 2-0036B/2096VE
v.1.0
Inputs
UNITS
-135
MIN.
-100
MIN.MAX. MAX.
DESCRIPTION#
2
PARAMETER
20 Input Buffer Delay ns
t
din 21 Dedicated Input Delay ns
t
grp 22 GRP Delay ns
GLB
t
1ptxor 25 1 Product Term/XOR Path Delay ns
t
20ptxor 26 20 Product Term/XOR Path Delay ns
t
xoradj 27 XOR Adjacent Path Delay ns
t
gbp 28 GLB Register Bypass Delay ns
t
gsu 29 GLB Register Setup Time before Clock ns
t
gh 30 GLB Register Hold Time after Clock ns
t
gco 31 GLB Register Clock to Output Delay ns
3
t
gro 32 GLB Register Reset to Output Delay ns
t
ptre 33 GLB Product Term Reset to Register Delay ns
t
ptoe 34 GLB Product Term Output Enable to I/O Cell Delay ns
t
ptck 35 GLB Product Term Clock Delay ns
ORP
t
ob 38 Output Buffer Delay ns
t
sl 39 Output Slew Limited Delay Adder ns
GRP
t
4ptbpc 23 4 Product Term Bypass Path Delay (Combinatorial) ns
t
4ptbpr 24 4 Product Term Bypass Path Delay (Registered) ns
t
orp 36 ORP Delay ns
t
orpbp 37 ORP Bypass Delay ns
Outputs
t
oen 40 I/O Cell OE to Output Enabled ns
t
odis 41 I/O Cell OE to Output Disabled ns
t
goe 42 Global Output Enable ns
t
gy0 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) ns
t
gy1/2 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line ns
Clocks
t
gr 45 Global Reset to GLB
0.5
1.7
1.2
4.7
4.7
4.7
0.5
–
–
0.3
1.1
6.1
6.9
5.0
1.6
2.0
3.7
3.7
1.5
0.5
3.4
3.4
3.6
1.6
1.8
5.8
–
–
–
–
–
–
–
1.2
3.8
–
–
–
–
1.6
–
–
–
–
–
–
–
–
–
1.6
1.8
–
0.7
2.5
1.8
6.2
6.2
6.2
1.0
–
–
0.3
3.1
7.1
9.1
5.6
1.6
2.0
5.2
4.7
1.7
0.7
3.4
3.4
5.6
2.4
2.6
7.1
–
–
–
–
–
–
–
1.7
4.8
–
–
–
–
2.6
–
–
–
–
–
–
–
–
–
2.4
2.6
–ns
Global Reset
Specifications ispLSI 2096VE
9
ispLSI 2096VE Timing Model
GLB Reg
Delay
I/O Pin
(Output)
ORP
Delay
Feedback
Reg 4 PT Bypass
20 PT
XOR Delays
Control
PTs
I/O Pin
(Input)
Y0,1,2
GRP GLB Reg Bypass ORP Bypass
DQ
RST
RE
OE
CK
I/O Delay
I/O CellORPGLBGRPI/O Cell
#24
#25, 26, 27
#33, 34,
35
#43, 44
#36
Reset
Ded. In #21
#20 #28
#29, 30,
31, 32
#38,
39
GOE 0 #42
#40, 41
0491/2032
#22
Comb 4 PT Bypass #23
#37
#45
Table 2-0042/2096VE
Derivations of tsu, th and tco from the Product Term Clock
=
=
=
=
t
su
2.8ns
Logic + Reg su - Clock (min)
(
t
io +
t
grp +
t
20ptxor) + (
t
gsu) - (
t
io +
t
grp +
t
ptck(min))
(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
(0.5 + 0.2 + 2.8) + (0.8) - (0.5 + 0.2 + 0.8)
=
=
=
=
t
h Clock (max) + Reg h - Logic
(
t
io +
t
grp +
t
ptck(max)) + (
t
gh) - (
t
io +
t
grp +
t
20ptxor)
(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
(0.5 + 0.2 + 3.6) + (1.7) - (0.5 + 0.2 + 2.8)
=
=
=
=
t
co
Note: Calculations are based upon timing specifications for the ispLSI 2096VE-250L.
Clock (max) + Reg co + Output
(
t
io +
t
grp +
t
ptck(max)) + (
t
gco) + (
t
orp +
t
ob)
(#20 + #22 + #35) + (#31) + (#36 + #38)
(0.5 + 0.2 + 3.6) + (0.2) + (1.1 + 1.4)
2.5ns
7.0ns
Specifications ispLSI 2096VE
10
Power Consumption
Power consumption in the ispLSI 2096VE device de-
pends on two primary factors: the speed at which the
device is operating and the number of Product Terms
used. Figure 3 shows the relationship between power
and operating speed.
Figure 3. Typical Device Power Consumption vs fmax
0127/2096VE
ICC can be estimated for the ispLSI 2096VE using the following equation:
ICC (mA) = 8.0 + (# of PTs * 0.63) + (# of Nets * Fmax * 0.005)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The ICC estimate is based on typical conditions (VCC = 3.3V, room temperature) and an assumption of two
GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to
operating conditions and the program in the device, the actual ICC should be verified.
Notes: Configuration of six 16-bit counters
Typical current at 3.3V, 25° C
140
120
180
050100 150 200 250
fmax (MHz)
ICC (mA)
ispLSI 2096VE
200
220
240
260
160
Specifications ispLSI 2096VE
11
Pin Description
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
NAME
Table 2-0002-2096VE
TQFP PIN NUMBERS DESCRIPTION
21,
27,
35,
41,
51,
57,
64,
71,
85,
91,
99,
105,
115,
121,
128,
7,
19
48
77
14
15
112
20
22,
28,
36,
42,
52,
58,
65,
72,
86,
92,
100,
106,
116,
122,
1,
8,
80, 17
23,
29,
37,
43,
53,
59,
67,
73,
87,
93,
101,
107,
117,
123,
3,
9,
I/O 0 - I/O 5
I/O 6 - I/O 11
I/O 12 - I/O 17
I/O 18 - I/O 23
I/O 24 - I/O 29
I/O 30 - I/O 35
I/O 36 - I/O 41
I/O 42 - I/O 47
I/O 48 - I/O 53
I/O 54 - I/O 59
I/O 60 - I/O 65
I/O 66 - I/O 71
I/O 72 - I/O 77
I/O 78 - I/O 83
I/O 84 - I/O 89
I/O 90 - I/O 95
24,
30,
38,
44,
54,
60,
68,
74,
88,
94,
102,
108,
118,
124,
4,
10,
25,
32,
39,
45,
55,
61,
69,
75,
89,
96,
103,
109,
119,
125,
5,
11,
26
33
40
46
56
62
70
76
90
97
104
110
120
126
6
12
18,
111, 34,
127 50, 63,
2,
95, 16,
114 31, 47, 66, 81,
79, 98,
Global Output Enables input pins.GOE 0, GOE 1
GND
V
VCC CC
Ground (GND)
Dedicated Clock input. This clock input is connected to one of the clock
inputs of all the GLBs on the device.
Active Low (0) Reset pin which resets all of the registers in the device.
RESET
Y0, Y1, Y2
13, 49, 82 No Connect.
NC1
TDI/IN 0
BSCAN
TMS/IN 1
11384,
78
83,
Dedicated input pins to the device.IN 4, IN 5
TDO/IN 2
TCK/IN 3
Output/Input — This pin performs two functions. When BSCAN is logic
low, it functions as an output pin to read serial shift register data. When
BSCAN is high, it functions as a dedicated input pin.
Input — Dedicated in-system programming Boundary Scan enable input
pin. This pin is brought low to enable the programming mode. The TMS,
TDI, TDO and TCK controls become active.
Input — This pin performs two functions. When BSCAN is logic low, it
functions as a serial data input pin to load programming data into the
device. When BSCAN is high, it functions as a dedicated input pin.
Input — This pin performs two functions. When BSCAN is logic low, it
functions as a mode control pin for the Boundary Scan state machine.
When BSCAN is high, it functions as a dedicated input pin.
Input — This pin performs two functions. When BSCAN is logic low, it
functions as a clock pin for the Boundary Scan state machine. When
BSCAN is high, it functions as a dedicated input pin.
1. NC pins are not to be connected to any active signal, VCC or GND.
Specifications ispLSI 2096VE
12
Pin Configuration
ispLSI 2096VE 128-Pin TQFP Pinout Diagram (0.4mm Lead Pitch/14.0 x 14.0mm Body Size)
VCC
I/O 85
I/O 86
I/O 87
I/O 88
I/O 89
I/O 90
I/O 91
I/O 92
I/O 93
I/O 94
I/O 95
1NC
Y0
RESET
VCC
GOE 1
GND
BSCAN
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
VCC
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
IN 4
Y1
NC1
VCC
GOE 0
Y2
TCK/IN 3
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
VCC
I/O 84
GND
I/O 83
I/O 82
I/O 81
I/O 80
I/O 79
I/O 78
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
IN 5
GND
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64
I/O 63
I/O 62
I/O 61
I/O 60
GND
I/O 59
I/O 10
GND
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
TMS/IN 1
1NC
GND
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 32
I/O 33
I/O 34
I/O 35
GND
ispLSI 2096VE
Top View
VCC
TDI/IN 0
I/O 58
TDO/IN 2
GND
I/O 37
I/O 11
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
128
127
126
125
124
123
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
9764
96
122
I/O 36
VCC
1. NC pins are not to be connected to any active signals, VCC or GND.
0124-2096VE
Specifications ispLSI 2096VE
13
Part Number Description
ispLSI 2096VE Ordering Information
Table 2-0041A/2096VE
FAMILY fmax (MHz)
200
135
ORDERING NUMBER PACKAGE
128-Pin TQFP
tpd (ns)
4.5
7.5
ispLSI ispLSI 2096VE-200LT128*
250 128-Pin TQFP4.0 ispLSI 2096VE-250LT128
*Use ispLSI 2096VE-250 for new designs
128-Pin TQFPispLSI 2096VE-135LT128
100 128-Pin TQFP10 ispLSI 2096VE-100LT128
COMMERCIAL
INDUSTRIAL
Table 2-0041B/2096VE
FAMILY fmax (MHz)
135
ORDERING NUMBER PACKAGE
128-Pin TQFP
tpd (ns)
7.5
ispLSI ispLSI 2096VE-135LT128I
Device Number
ispLSI 2096VE XX X XXXXX
Grade
X
Speed
250 = 250 MHz
f
max
200 = 200 MHz
f
max*
135 = 135 MHz
f
max
100 = 100 MHz
f
max
*Use ispLSI 2096VE-250 for new designs
Power
L = Low
Package
–
Device Family
0212/2096VE
T128 = 128-Pin TQFP
TN128 = Lead-Free 128-Pin TQFP
Blank = Commercial
I = Industrial
Conventional Packaging
Lead-Free Packaging
FAMILY fmax (MHz)
135
ORDERING NUMBER PACKAGEtpd (ns)
7.5
ispLSI 250 Lead-Free 128-Pin TQFP4.0 ispLSI 2096VE-250LTN128 Lead-Free 128-Pin TQFPispLSI 2096VE-135LTN128
100 Lead-Free 128-Pin TQFP10 ispLSI 2096VE-100LTN128
COMMERCIAL
INDUSTRIAL
FAMILY fmax (MHz)
135
ORDERING NUMBER PACKAGE
Lead-Free 128-Pin TQFP
tpd (ns)
7.5
ispLSI ispLSI 2096VE-135LTN128I
