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RT8010/A
11
DS8010/A-09 September 2012 www.richtek.com
©
Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
The output ripple is highest at maximum input voltage
since ΔIL increa ses with input voltage. Multiple ca pacitors
placed in parallel may be needed to meet the ESR and
RMS current handling requirements. Dry tantalum, special
polymer, aluminum electrolytic and cera mic capacitors are
all available in surfa ce mount packages. Special polymer
ca pacitors offer very low ESR but have lower ca pa citance
density than other types. Tantalum capacitors have the
highest capacitance density but it is important to only
use types that have been surge tested for use in switching
power supplies. Aluminum electrolytic capacitors have
significantly higher ESR but can be used in cost-sensitive
a pplications provided that consideration is given to ripple
current ratings and long term reliability . Ceramic ca pacitors
have excellent low ESR characteristics but can have a
high voltage coefficient and audible piezoelectric effects.
The high Q of ceramic capacitors with trace inductance
ca n also lea d to significa nt ringing.
Using Ceramic In put and Output Cap acitors
Higher values, lower cost ceramic capacitors are now
becoming available in smaller ca se sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However , care must
be taken when these ca pacitors are used at the input and
output. When a ceramic capacitor is used at the input
a nd the power is supplied by a wall ada pter through long
wires, a load ste p at the output ca n induce ringing at the
input, VIN. At best, this ringing can couple to the output
and be mistaken as loop instability. At worst, a sudden
inrush of current through the long wires can potentially
cause a voltage spike at VIN large enough to da mage the
part.
Output Voltage Programming
The resistive divider allows the FB pin to sense a fra ction
of the output voltage a s shown in Figure 4.
Figure 4. Setting the Output Voltage
where VREF is the internal reference voltage (0.6V typ.)
For adjustable voltage mode, the output voltage is set by
an external resistive divider according to the following
equation :
Efficiency Considerations
The efficiency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Ef ficiency ca n be expressed as :
Efficiency = 100% − (L1+ L2+ L3+ ...)
where L1, L2, etc. are the individual losses a s a percentage
of input power. Although all dissipative elements in the
circuit produce losses, two main sources usually a ccount
for most of the losses : VIN quiescent current and I2R
losses.
The VIN quiescent current loss dominates the efficiency
loss at very low load currents whereas the I2R loss
dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve
at very low load currents can be misleading since the
a ctual power lost is of no consequence.
1. The VIN quiescent current a ppears due to two factors
including : the DC bias current as given in the electrical
characteristics and the internal main switch and
synchronous switch gate charge currents. The gate charge
current results from switching the gate ca pacitance of the
internal power MOSFET switche s. Ea ch ti me the gate is
switched from high to low to high again, a packet of charge
ΔQ moves from VIN to ground.
The resulting ΔQ/Δt is the current out of VIN that is typically
larger tha n the DC bia s current. In continuous mode,
IGATECHG = f (QT + QB)
where QT and QB are the gate charges of the internal top
and bottom switches. Both the DC bias a nd gate charge
losses are proportional to VIN and thus their effects will
be more pronounced at higher supply voltages.
RT8010/A
GND
FB
R1
R2
VOUT
⎛⎞
=⎜⎟
⎝⎠
OUT REF R1
VV1+
R2