A-Data ADD8616A8A
Revision History
Revision 1 ( Dec. 2001 )
1.Fister release.
Revision 2 ( Apr. 2002 )
1. Changed module current specification.
2. Add Performance range.
3. Changed AC Characteristics.
4. Changed typo size on module PCB in package dimensions.
Rev 2 April, 2002 1
A-Data ADD8616A8A
Double Data Rate SDRAM 4M x 16 Bit x 4 Banks
General Description
The ADD8616A8A are four-bank Double Data
Rate(DDR) Synchronous DRAMs organized as
4,194,304 words x 16 bits x 4 banks,
Synchronous design allows precise cycle control
with the use of system clock I/O transactions are
possible on every clock cycle.
Data outputs occur at both rising edges of CK and
/CK.
Range of operating frequencies, programmable
burst length and programmable latencies allow the
same device to be useful for a variety of high
bandwidth high performance memory system
applications
Features
•2.5V for VDDQ power supply
•SSTL_2 interface
•MRS Cycle with address key programs
-CAS Latency (2, 2.5)
-Burst Length (2,4 &8)
-Burst Type (sequential & Interleave)
•4 banks operation
•Differential clock input (CK, /CK) operation
•Double data rate interface
•Auto & Self refresh
•8192 refresh cycle
•DQM for masking
•Package:66-pins 400 mil TSOP-Type II
Ordering Information.
Part No. Frequency Interface Package
VDD8608A8A-75BA 133Mhz(7.5ns /CL=2)
ADD8616A8A-75B 133Mhz(7.5ns /CL=2.5) SSTL_2 400mil 66pin TSOPII
Pin Assignment
1
2
3
4
5
6
7
8
9
V
DD
DQ0
V
DDQ
NC
DQ1
V
SSQ
NC
DQ2
V
DDQ
6
4
3
62
61
60
59
58
V
SS
DQ7
V
SSQ
NC
DQ6
V
DDQ
NC
DQ5
V
SSQ
10
11
12
13
14
15
1
6
1
18
19
20
NC
DQ3
V
SSQ
NC
NC
V
DDQ
NC
WE
CAS
RAS
CS
NC
DQ4
V
DDQ
NC
NC
V
SSQ
DQS
NC
V
DM
A6
A5
A4
V
SS
REF
V
SS
21
22
23
24
25
26
27
28
29
NC
BA0
BA1
A10/AP
A0
A1
A2
V
DD
30
31
32
33 34
35
36
37
38
39
NC
A3
VDD
NC
40
41
42
43
CK
CK
CKE
NC
NC
A11
A9
A8
A7
57
56
55
54
53
52
51
50
49
48
47
46
45
44
6
65
6
6
7
NC
66-pin plastic TSOP II 400 mil
Rev 2 April, 2002 2
A-Data ADD8616A8A
Pin Description
PIN NAME FUNCTION
CK, /CK System Clock Differential clock input.
CKE Clock Enable Masks system clock to freeze operation from the next clock cycle. CKE
should be enabled at least on cycle prior new command. Disable input
buffers for power down in standby
/CS Chip Select Disables or Enables device operation by masking or enabling all input
except CK, CKE and DQ
A0~A12 Address Row / Column address are multiplexed on the same pins.
Row address : A0~A12
Column address : A0~A9
BS0~BS1 Banks Select Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
DQ0~DQ15 Data Data inputs / outputs are multiplexed on the same pins.
/RAS Row Address Strobe Latches row addresses on the positive edge of the CLK with /RAS low
/CAS Column Address Strobe Latches Column addresses on the positive edge of the CLK with /CAS
low
/WE Write Enable Enables write operation and row recharge.
VDD/VSS Power Supply/Ground Power and Ground for the input buffers and the core logic.
VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers.
VREF Reference Voltage Reference voltage for inputs for SSTL interface.
NC No Connection This pin is recommended to be left No Connection on the device.
Block Diagram
CK
CKE
Clock
Generator
Address
/CS
/RAS
/CAS
/WE
DQM
Mode
Register
Command Decoder
Control Logic
Row Decoder
Address
Buffer
&
Refresh
Counter
Column
Address
Buffer
&
Refresh
Counter
Bank0
Bank2
Bank3
Bank1
Amplifier
Column Decoder
Data Control Circuit
Data Latch
DQ0~DQn
DQS
Rev 2 April, 2002 3
A-Data ADD8616A8A
Absolute Maximum Ratings
Parameter Symbol Value Unit
Voltage on any pin relative to Vss VIN, Vout -0.3 ~ VDDQ+0.3 V
Voltage on VDD supply relative to Vss VDD, VDDQ -0.3 ~ 3.6 V
Storage temperature TSTG -55 ~ +150 ℃
Power dissipation PD 1 W
Short circuit current IOUT 50 mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operating Condition
Voltage referenced to Vss = 0V, TA = 0 to 70 ℃
Parameter Symbol Min Max Unit Note
Supply voltage VDD 2.3 2.7 V
Supply voltage VDDQ 2.3 VDD 1
Input logic high voltage VIH VREF+0.15 VDDQ+0.3 V
Input logic low voltage VIL -0.3 VREF-0.15 V 2
Differential Clock DC Input voltage VICK -0.3 VDDQ+0.3 V
Input Differential CLK&/CLK voltage VID 0.7 VDDQ+0.6 V
Input leakage current IIL -5 5 uA 3
Output leakage current IOL -5 5 uA 4
Reference Voltage VREF 0.49* VDDQ 0.51* VDDQ V
Termination Voltage VTT VREF-0.04 VREF+0.04 V 5
Note : 1. VDDQ must not exceed the level of VDDQ.
2.VIL(min)=-0.9V with a pulse width ≦ 5ns .
3.Any input 0V ≦ V
IN ≦ 3.6V, all other pins are not under test = 0V.
4.Dout is disabled, 0V ≦ V
OUT ≦ 2.7V.
5. VREF is expected to be equal to 0.5* VDDQ of the transmitting device, and to track variations in the DC level of
the same. Peak to peak noise on VREF may not exceed ±2% of the DC value.
Rev 2 April, 2002 4
A-Data ADD8616A8A
AC Test Condition
Voltage referenced to Vss = 0V, TA = 0 to 70 ℃
Parameter Symbol Value Unit Note
AC input high level voltage VIH VREF+0.31 V
AC input low level voltage VIL VREF-0.31 V
Input Reference Voltage VREF 0.5xVDDQ V
Termination Voltage VTT 0.5xVDDQ V
Input Signal Peak to Peak Swing VSWING 1.0 V
Input Difference Voltage. CLK and /CLK Inputs VID 1.5 V
Capacitance
TA=25℃, f-=1Mhz
Parameter Pin Symbol Min Max Unit
CK, /CK Cl1 2 3.0 pF Input capacitance
A0~A12,BS0,BS1,CKE,/CS,/RAS,
/CAS,/WE,DQM
Cl2 2 3.0 pF
Data input / output capacitance DQM CI/O 4 5 pF
Output load circuit
Output Load Circuit (SSTL_2)
Output Z0=50Ω
C
LOAD
=30pF
V
REF
=0.5*V
DDQ
R
T
=50Ω
V
tt
=0.5*V
DDQ
Rev 2 April, 2002 5
A-Data ADD8616A8A
DC Characteristics II
Speed
Parameter Symbol Test condition
-75BA/ -75B
Unit Note
Operating Current IDD1
Burst length=2, One bank active
Trc=tRC(min),IOUT=0mA
110 mA 1
Precharge standby
current in power
down mode
IDD2P CKE≦VIL(max), tCK=min 20 mA
Precharge standby
current in Non power
down mode
IDD2N
CKE≧VIH(min), /CS≧VIH(min),
tCK= tCK min input signals are
changed one time during 2clks.
40 mA
Active standby
current in power
down mode
IDD3P CKE≦VIL(max), tCK= tCK min 20 mA
Active standby
current in Non power
down mode
IDD3N
CKE≧VIH(min), /CS≧VIH(min),
tCK=min input signals are
changed one time during 2clks.
65 mA
Burst mode operating
current
IDD4R
tCK≧tCK(min),IOUT=0 mA
All banks active
155 mA 1
Auto refresh current IDD5
tRRC≧tRRC(min), All banks
active
190 mA 2
Self refresh current IDD6 CKE≦0.2V 3 mA
Note: 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output
open.
2. Min. of tRRC is shown at AC characteristics.
Rev 2 April, 2002 6
A-Data ADD8616A8A
AC Characteristics
-75BA -75B
Parameter Symbol
Min Max Min Max
Unit
/CAS Latency = 2.5 tCK2.5 7.5 12 7.5 12
System clock
Cycle time /CAS Latency = 2 tCK2 7.5 12 10 12
ns
Clock high pulse width tCHW 0.45 0.55 0.45 0.55 CLK
Clock low pulse width tCLW 0.45 0.55 0.45 0.55 CLK
Access time form CK to /CK tAC -0.75 0.75 -0.75 0.75 ns
Data strobe edge to clock edge tDQSCK -0.75 0.75 -0.75 0.75 ns
Clock to first rising edge of DQS delay tDQSS 0.75 1.25 0.75 1.25 CLK
/RAS cycle time tRC 65 - 65 - ns
/RAS to /CAS delay tRCD 20 - 20 - ns
/RAS active time tRAS 45 120K 45 120K ns
/RAS precharge time tRP 20 - 20 - ns
/RAS to /RAS bank active delay tRRD 15 - 15 - ns
/CAS to /CAS delay tCCD 1 - 1 - CLK
Data-in setup time (to DQS) tDS 0.5 - 0.5 - ns
Data-in hold time (to DQS) tDH 0.5 - 0.5 - ns
DQS Falling Edge to CLK Setup Time tDSS 0.2 - 0.2 - CLK
DQS Falling Edge Hold Time from CLK tDSH 0.2 - 0.2 - CLK
Input setup time tIS 0.9 - 0.9 - ns
Input hold time tIH 0.9 - 0.9 - ns
DQS-in high level width tDSH 0.35 - 0.35 - CLK
DQS-in low level width tDSL 0.35 - 0.35 - CLK
Clock to DQS write preamble setup time tWPRES 0 - 0 - ns
Write preamble tWPST 0.4 06 0.4 06 CLK
Data strobe edge to output data edge tDQSQ 0.5 0.5 ns
Mode register set cycle time tMRD 15 15
DQS read preamble tRPRE 0.9 1.1 0.9 1.1 CLK
Rev 2 April, 2002 7
A-Data ADD8616A8A
Command Truth-Table
SYM. Command CKEn-1 CKEn /CS /RAS /CAS /WE DM ADDR A10/AP BS
MRS Mode Register Set H X L L L L X CA CA L
NOP No Operation H X L H H H X X
ACT Bank Active H X L L H H X V V
READ Read L
READA Read with Auto Precharge
H X L H L H X V
H
V
WRIT Write L
WRITA Write with Auto Precharge
H X L H L L X V
H
V
PREA Precharge All Bank H X L L H L X X H X
BST Burst Stop H X L H H L X X
AREF Auto Refresh H H L L L H X X
Entry H L L L L H X
HXX X
SELF
SELEX Self Refresh
Exit L H
L H H H
X
X
HXX X
Entry H L
L H H H
X
HXX X
PD
PDEX
Precharge
Power down
Exit L H
L H H X
X
X
Enable H X X X X X L
WDE
WDD Data write
Disable H X X X X X H
X
Rev 2 April, 2002 8
A-Data ADD8616A8A
Package Information
MILLIMETER INCH
SYMBOL MIN. NOM. MAX. MIN. NOM. MAX.
A 1.20 0.047
A1 0.05 0.15 0.002 0.006
A2 0.95 1.00 1.05 0.037 0.039 0.041
B 0.17 0.24 0.32 0.007 0.009 0.013
c 0.09 0.2 0.004 0.008
D 22.62 BSC 0.891 BSC
HE 11.74 11.76 11.78 0.462 0.463 0.464
E 10.15 10.16 10.17 0.3996 0.400 0.4004
e 0.65 BSC 0.026
L 0.40 0.50 0.60 0.016 0.020 0.024
L1 0.80 REF 0.031 REF
S
0.71 REF 0.028 REF
θ
0 ° - 8 ° 0 ° - 8 °
33
34
1
66
0.145 0.0006
400mil 66pin TSOP II Package
Rev 2 April, 2002 9
