To our customers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company nam e remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
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Rev.3.00, Dec. 04.2003, page 1 of 26
HN58V65A Series
HN58V66A Series
64 k EEPROM (8-kword × 8-bit)
Ready/Busy Function, RES Function (HN58V66A)
REJ03C0149-0300Z
(Previous ADE-203-539B (Z) Rev. 2.0)
Rev. 3.00
Dec. 04. 2003
Description
Renesas Technology's HN58V65A series and HN58V66A series are a electrically erasable and
programmable EEPROM’s organized as 8192-word × 8-bit. They have realized high speed, low power
consumption and high relisbility by employing advanced MNOS memory technology and CMOS process
and circuitry technology. They also have a 64-byte page programming function to make their write
operations faster.
Features
• Single supply: 2.7 to 5.5 V
• Access time:
100 ns (max) at 2.7 V ≤ VCC < 4.5 V
70 ns (max) at 4.5 V ≤ VCC ≤ 5.5 V
• Power dissipation:
• Active: 20 mW/MHz (typ)
• Standby: 110 µW (max)
• On-chip latches: address, data, CE, OE, WE
• Automatic by te wr ite: 1 0 ms (max)
• Automatic page write (64 bytes): 10 ms (max)
• Ready/Busy
• Data polling and Toggle bit
• Data protection circuit on power on/off
• Conforms to JEDEC byte-wide standard
• Reliable CMOS with MNOS cell technology
HN58V65A Series, HN58V66A Series
Rev.3.00, Dec. 04.2003, page 2 of 26
Features (cont)
• 105 erase/write cycles (in page mode)
• 10 years data retention
• Software data protection
• Write protection by RES pin (only the HN58V66A series)
• Industrial versions (Temperatur range: −20 to 85°C and −40 to 85°C) are also available.
• There are also lead free products.
Ordering Information
Access time
Type No. 2.7 V ≤
≤≤
≤ VCC < 4.5 V 4.5 V ≤
≤≤
≤ VCC ≤
≤≤
≤ 5.5 V Package
HN58V65AP-10 100 ns 70 ns 600 mil 28-pin plastic DIP (DP-28)
HN58V66AP-10 100 ns 70 ns
HN58V65AFP-10 100 ns 70 ns 400 mil 28-pin plastic SOP (FP-28D)
HN58V66AFP-10 100 ns 70 ns
HN58V65AT-10 100 ns 70 ns 28-pin plastic TSOP(TFP-28DB)
HN58V66AT-10 100 ns 70 ns
HN58V65AP-10E 100 ns 70 ns 600 mil 28-pin plastic DIP (DP-28V)
HN58V66AP-10E 100 ns 70 ns Lead free
HN58V65AFP-10E 100 ns 70 ns 400 mil 28-pin plastic SOP (FP-28DV)
HN58V66AFP-10E 100 ns 70 ns Lead free
HN58V65AT-10E 100 ns 70 ns 28-pin plastic TSOP(TFP-28DBV)
HN58V66AT-10E 100 ns 70 ns Lead free
HN58V65A Series, HN58V66A Series
Rev.3.00, Dec. 04.2003, page 3 of 26
Pin Arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
NC
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
RDY/
Busy
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
(Top view)
HN58V65AP Series
HN58V65AFP Series
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
RES
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
RDY/
Busy
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
(Top view)
HN58V66AP Series
HN58V66AFP Series
HN58V65A Series, HN58V66A Series
Rev.3.00, Dec. 04.2003, page 4 of 26
Pin Arrangement (cont)
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A2
A1
A0
I/O0
I/O1
I/O2
V
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
SS
A3
A4
A5
A6
A7
A12
RDY/
Busy
V
WE
NC
A8
A9
A11
OE
CC
(Top view)
HN58V65AT Series
15
16
17
18
19
20
21
22
23
24
25
26
27
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A2
A1
A0
I/O0
I/O1
I/O2
V
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
SS
A3
A4
A5
A6
A7
A12
RDY/
Busy
V
WE
RES
A8
A9
A11
OE
CC
(Top view)
HN58V66AT Series
15
16
17
18
19
20
21
22
23
24
25
26
27
28
HN58V65A Series, HN58V66A Series
Rev.3.00, Dec. 04.2003, page 5 of 26
Pin Description
Pin name Function
A0 to A12 Address input
I/O0 to I/O7 Data input/output
OE Output enable
CE Chip enable
WE Write enable
VCC Power supply
VSS Ground
RDY/Busy Ready busy
RES*1 Reset
NC No connection
Note: 1. This function is supported by only the HN58V66A series.
Block Diagram
Note: 1. This function is supported by only the HN58V66A series.
V
V
OE
CE
A5
A0
A6
A12
WE
CC
SS
I/O0 I/O7
High voltage generator
Control logic and timing
Y decoder
X decoder
Address
buffer and
latch
I/O buffer
and
input latch
Y gating
Memory array
Data latch
RES
RDY/
Busy
RES
*
1
*
1
to
to
to
HN58V65A Series, HN58V66A Series
Rev.3.00, Dec. 04.2003, page 6 of 26
Operation Table
Operation CE
CECE
CE OE
OEOE
OE WE
WEWE
WE RES
RESRES
RES*3 RDY/Busy
BusyBusy
Busy I/O
Read VIL V
IL V
IH V
H*1 High-Z Dout
Standby VIH ×*2 × × High-Z High-Z
Write VIL V
IH V
IL V
H High-Z to VOL Din
Deselect VIL V
IH V
IH V
H High-Z High-Z
Write Inhibit × × V
IH ×
× V
IL × ×
Data Polling VIL V
IL V
IH V
H V
OL Dout (I/O7)
Program reset × × × V
IL High-Z High-Z
Notes: 1. Refer to the recommended DC operating conditions.
2. × : Don’t care
3. This function supported by only the HN58V66A series.
Absolute Maximum Ratings
Parameter Symbol Value Unit
Power supply voltage relative to VSS V
CC −0.6 to +7.0 V
Input voltage relative to VSS Vin −0.5*1 to +7.0*3 V
Operating temperature range *2 Topr 0 to +70 °C
Storage temperature range Tstg −55 to +125 °C
Notes: 1. Vin min : −3.0 V for pulse width ≤ 50 ns.
2. Including electrical characteristics and data retention.
3. Should not exceed VCC + 1 V.
Recommended DC Operating Conditions
Parameter Symbol Min Typ Max Unit
Supply voltage VCC 2.7 5.5 V
V
SS 0 0 0 V
Input voltage VIL −0.3*1 0.6*5 V
V
IH 1.9*2 V
CC + 0.3*3 V
V
H*4 V
CC −0.5 V
CC + 1.0 V
Operating temperature Topr 0 +70 °C
Notes: 1. VIL min: −1.0 V for pulse width ≤ 50 ns.
2. VIH = 2.2 V for VCC = 3.6 to 5.5 V.
3. VIH ma x: VCC + 1.0 V for pulse width ≤ 50 ns.
4. This function is supported by only the HN58V66A series.
5. VIL = 0.8 V for VCC = 3.6 V to 5.5 V
HN58V65A Series, HN58V66A Series
Rev.3.00, Dec. 04.2003, page 7 of 26
DC Characteristics (Ta = 0 to + 70°C, VCC = 2.7 to 5.5 V)
Parameter Symbol Min Typ Max Unit Test conditions
Input leakage current ILI 2*1 µA Vin = 0 V to VCC
Output leakage current ILO 2 µA Vout = 0 V to VCC
Standby VCC curren ICC1 1 to 2 5 µA CE = VCC – 0.3 V to VCC + 1.0 V
I
CC2 1 mA CE = VIH
Operating VCC current ICC3 6 mA Iout = 0 mA, Duty = 100%,
Cycle = 1 µs, VCC = 3.6 V
8 mA Iout = 0 mA, Duty = 100%,
Cycle = 1 µs, VCC = 5.5 V
12 mA Iout = 0 mA, Duty = 100%,
Cycle = 100 ns, VCC = 3.6 V
25 mA Iout = 0 mA, Duty = 100%,
Cycle = 70 ns, VCC = 5.5 V
Output low voltage VOL 0.4 V IOL = 2.1 mA
Output high voltage VOH V
CC × 0.8 V IOH = –400 µA
Note: 1. ILI on RES : 100 µA max (only the HN58V66A series)
Capacitance (Ta = +25°C, f = 1 MHz)
Parameter Symbol Min Typ Max Unit Test conditions
Input capacitance Cin*1 6 pF Vin = 0 V
Output capacitance Cout*1 12 pF Vout = 0 V
Note: 1. This parameter is sampled and not 100% tested.
HN58V65A Series, HN58V66A Series
Rev.3.00, Dec. 04.2003, page 8 of 26
AC Characteristics (Ta = 0 to + 70°C, VCC = 2.7 to 5.5 V)
Test Condit ions
• Input pulse levels : 0.4 V to 2.4 V (VCC = 2.7 to 3.6 V), 0.4 V to 3.0 V (VCC = 3.6 to 5.5 V)
0 V to V
CC (RES pin*2)
• Input rise and fall time : ≤ 5 ns
• Input timing reference levels : 0.8, 1.8 V
• Output load : 1TTL Gate +100 pF
• Output reference levels : 1.5 V, 1.5 V
Read Cycle 1 (2.7 V ≤ VCC < 4.5 V)
HN58V65A/HN58V66A
-10
Parameter Symbol Min Max Unit Test conditions
Address to output delay tACC 100 ns CE = OE = VIL, WE = VIH
CE to output delay tCE 100 ns OE = VIL, WE = VIH
OE to output delay tOE 10 50 ns CE = VIL, WE = VIH
Address to output hold tOH 0 ns CE = OE = VIL, WE = VIH
OE (CE) high to output float*1 t
DF 0 40 ns CE = VIL, WE = VIH
RES low to output float*1, 2 t
DFR 0 350 ns CE = OE = VIL, WE = VIH
RES to output delay*2 t
RR 0 450 ns CE = OE= VIL, WE = VIH
HN58V65A Series, HN58V66A Series
Rev.3.00, Dec. 04.2003, page 9 of 26
Write Cycle 1 (2.7 V ≤ VCC < 4.5 V)
Parameter Symbol Min*3 Typ Max Unit Test conditions
Address setup time tAS 0 ns
Address hold time tAH 50 ns
CE to write setup time (WE controlled) tCS 0 ns
CE hold time (WE controlled) tCH 0 ns
WE to write setup time (CE controlled) tWS 0 ns
WE hold time (CE controlled) tWH 0 ns
OE to write setup time tOES 0 ns
OE hold time tOEH 0 ns
Data setup time tDS 50 ns
Data hold time tDH 0 ns
WE pulse width (WE controlled) tWP 200 ns
CE pulse width (CE controlled) tCW 200 ns
Data latch time tDL 100 ns
Byte load cycle tBLC 0.3 30 µs
Byte load window tBL 100 µs
Write cycle time tWC — 10*4 ms
Time to device busy tDB 120 ns
Write start time tDW 0*5 ns
Reset protect time*2 t
RP 100 µs
Reset high time*2, 6 t
RES 1 µs
Notes: 1. tDF and tDFR are defined as the time at which the outputs achieve the open circuit conditions and
are no longer driven.
2. This function is supported by only the HN58V66A series.
3. Use this device in longer cycle than this value.
4. tWC must be longer than this value unless polling techniques or RDY/Busy are used. This device
automatically completes the internal write operation within this value.
5. Next read or write operation can be initiated after tDW if polling techniques or RDY/Busy are used.
6. This parameter is sampled and not 100% tested.
7. A6 through A12 are page addresses and these addresses are latched at the first falling edge of
WE.
8. A6 through A12 are page addresses and these addresses are latched at the first falling edge of
CE.
9. See AC read characteristics.
HN58V65A Series, HN58V66A Series
Rev.3.00, Dec. 04.2003, page 10 of 26
Read Cycle 2 (4.5 V ≤ VCC ≤ 5.5 V)
HN58V65A/HN58V66A
-10
Parameter Symbol Min Max Unit Test conditions
Address to output delay tACC 70 ns CE = OE = VIL, WE = VIH
CE to output delay tCE 70 ns OE = VIL, WE = VIH
OE to output delay tOE 10 40 ns CE = VIL, WE = VIH
Address to output hold tOH 0 ns CE = OE = VIL, WE = VIH
OE (CE) high to output float*1 t
DF 0 30 ns CE = VIL, WE = VIH
RES low to output float*1, 2 t
DFR 0 350 ns CE = OE = VIL, WE = VIH
RES to output delay*2 t
RR 0 450 ns CE = OE= VIL, WE = VIH
HN58V65A Series, HN58V66A Series
Rev.3.00, Dec. 04.2003, page 11 of 26
Write Cycle 2 (4.5 V ≤ VCC ≤ 5.5 V)
Parameter Symbol Min*3 Typ Max Unit Test conditions
Address setup time tAS 0 ns
Address hold time tAH 50 ns
CE to write setup time (WE controlled) tCS 0 ns
CE hold time (WE controlled) tCH 0 ns
WE to write setup time (CE controlled) tWS 0 ns
WE hold time (CE controlled) tWH 0 ns
OE to write setup time tOES 0 ns
OE hold time tOEH 0 ns
Data setup time tDS 50 ns
Data hold time tDH 0 ns
WE pulse width (WE controlled) tWP 100 ns
CE pulse width (CE controlled) tCW 100 ns
Data latch time tDL 50 ns
Byte load cycle tBLC 0.2 30 µs
Byte load window tBL 100 µs
Write cycle time tWC — 10*4 ms
Time to device busy tDB 120 ns
Write start time tDW 0*5 ns
Reset protect time*2 t
RP 100 µs
Reset high time*2, 6 t
RES 1 µs
Notes: 1. tDF and tDFR are defined as the time at which the outputs achieve the open circuit conditions and
are no longer driven.
2. This function is supported by only the HN58V66A series.
3. Use this device in longer cycle than this value.
4. tWC must be longer than this value unless polling techniques or RDY/Busy are used. This device
automatically completes the internal write operation within this value.
5. Next read or write operation can be initiated after tDW if polling techniques or RDY/Busy are used.
6. This parameter is sampled and not 100% tested.
7. A6 through A12 are page addresses and these addresses are latched at the first falling edge of
WE.
8. A6 through A12 are page addresses and these addresses are latched at the first falling edge of
CE.
9. See AC read characteristics.
HN58V65A Series, HN58V66A Series
Rev.3.00, Dec. 04.2003, page 12 of 26
Timing Waveforms
Read Timing Waveform
Address
CE
OE
WE
Data Out
High
Data out valid
tACC
tCE
tOE
tOH
tDF
tRR
tDFR
RES
*2
HN58V65A Series, HN58V66A Series
Rev.3.00, Dec. 04.2003, page 13 of 26
Byte Write Timing Waveform(1) (WE Controlled)
Address
CE
WE
OE
Din
RDY/
Busy
tWC
tCH
tAH
tCS
tAS tWP
tOEH
tBL
tOES
tDS tDH
tDB
tRP
RES
*2
VCC
tRES
High-Z High-Z
tDW
HN58V65A Series, HN58V66A Series
Rev.3.00, Dec. 04.2003, page 14 of 26
Byte Writ e Timing Waveform(2) (CE Controlled)
Address
CE
WE
OE
Din
RDY/
Busy
t
WC
t
AH
t
WS
t
AS
t
OEH
t
WH
t
OES
t
DS
t
DH
t
DB
t
RP
RES
*
2
V
CC
t
CW
t
BL
t
DW
t
RES
High-Z High-Z
HN58V65A Series, HN58V66A Series
Rev.3.00, Dec. 04.2003, page 15 of 26
Page Write Timing Waveform(1) (WE Controlled)
Address
A0 to A12
WE
CE
OE
Din
RDY/
Busy
tAS tAH tBL
tWC
tOEH
tDH
tDB
tOES
tRP
tRES
RES
*2
VCC
tCH
tCS
tWP tDL tBLC
tDS
tDW
High-Z High-Z
*7
HN58V65A Series, HN58V66A Series
Rev.3.00, Dec. 04.2003, page 16 of 26
Page Write Timing Waveform(2) (CE Controlled)
Address
A0 to A12
WE
CE
OE
Din
RDY/
Busy
tAS tAH tBL
tWC
tOEH
tDH
tDB
tOES
tRP
tRES
RES
*2
VCC
tWH
tWS
tCW
tDL tBLC
tDS
tDW
High-Z High-Z
*8
HN58V65A Series, HN58V66A Series
Rev.3.00, Dec. 04.2003, page 17 of 26
Data
DataData
Data Polling Timing Wa veform
tCE
tOEH
tWC
tDW
tOES
Address
CE
WE
OE
I/O7
tOE
Din X
An An
Dout
X
Dout X
*9
*9
An
HN58V65A Series, HN58V66A Series
Rev.3.00, Dec. 04.2003, page 18 of 26
Toggle Bit
This device provide another function to determine the internal programming cycle. If the EEPROM is set
to read mode during the internal programming cycle, I/O6 will charge from “1” to “0” (toggling) for each
read. When the internal progr amming cycle is finished, toggling o f I /O6 will stop and the dev ice can be
accessible for next read or program.
Toggle Bit Waveform
Notes: 1. I/O6 begining state is “1”.
2. I /O6 ending state will vary.
3. See AC read characteristics.
4. Any address location can be used, but the address must be fixed.
WE
t
OES
OE
CE
Dout
I/O6 Dout Dout Dout
Next mode
t
OE
t
CE
t
DW
t
WC
t
OEH
*1 *2 *2
Address
*3
*3
*4
Din
HN58V65A Series, HN58V66A Series
Rev.3.00, Dec. 04.2003, page 19 of 26
Software Data Protection Timing Waveform(1) (in protection mode)
V
CE
WE
Address
Data 1555
AA 0AAA
55 1555
A0
tBLC tWC
CC
Write address
Write data
Software Data Protection Timing Waveform(2) (in non-protection mode)
V
CE
WE
Address
Data
t
WC
CC
Normal active
mode
1555
AA 0AAA
55 1555
80 1555
AA 0AAA
55 1555
20
HN58V65A Series, HN58V66A Series
Rev.3.00, Dec. 04.2003, page 20 of 26
Functional Description
Automatic Page Write
Page-mod e wr ite feature allows 1 to 64 bytes of data to be written into the EEPROM in a single write
cycle. Following the initial byte cycle, an additional 1 to 63 bytes can be written in the same manner. Each
additional byte load cycle must be started within 30 µs from the preceding falling edge of WE or CE.
When CE or WE is kept high for 100 µs after data input, the EEPROM enters write mode automatically
and the input data are written into the EEPROM.
Data
DataData
Data Polling
Data polling indicates the status that the EEPROM is in a write cycle or not. If EEPROM is set to read
mode during a write cycle, an inversion of the last byte of data outputs from I/O7 to indicate that the
EEPROM is performing a write operation.
RDY/Busy
BusyBusy
Busy Signal
RDY/Busy signal also allows status of the EEPROM to be determined. Th e RDY/Busy signal has high
impedance except in write cycle and is lowered to VOL after the first write signal. At the end of a write
cycle, the RDY/Busy signal changes state to high impedance.
RES
RESRES
RES Signal (only the HN58V66A series)
When RES is low, the EEPROM cannot be read or programmed. Therefore, data can be protected by
keeping RES low when VCC is switched. RES should be high during read and programming because it
doesn’t provide a latch function.
V
Program inhibit
CC
RES
Program inhibit
Read inhibit Read inhibit
HN58V65A Series, HN58V66A Series
Rev.3.00, Dec. 04.2003, page 21 of 26
WE
WEWE
WE, CE
CECE
CE Pin Operation
During a write cycle, addresses are latched by the falling edge of WE or CE, and data is latched by the
rising edge of WE or CE.
Write/Erase Endurance and Data Retention Time
The endurance is 105 cycles in case of the page programming and 104 cycles in case of the byte
programming (1% cumulative failur e rate). The data retentio n time is more than 1 0 years when a device is
page-programmed less than 10 4 cycles.
Data Protection
To prevent this phenomenon, this device has a noise cancellation function th at cuts noise if its width is 15
ns or less.
1. Data Protection against Noise on Control Pins (CE, OE, WE) during Operation
During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM to
programming mode by mistake. Be careful not to allow noise of a width of more than 15 ns on the
control pins.
WE
CE
OE
V
0 V
V
0 V
15 ns max
IH
IH
HN58V65A Series, HN58V66A Series
Rev.3.00, Dec. 04.2003, page 22 of 26
2. Data protection at VCC on/off
When VCC is turned on or off, noise on the control pins generated by external circuits (CPU, etc) may
act as a trigger and tu rn the EEPROM to program mode by mistake. To prevent th is unintentional
programming, the EEPROM must be kept in an unprogrammable state while the CPU is in an unstable
state.
Note: The EEPROM shoud be kept in unprogrammable state during VCC on/off by using CPU RESET
signal.
VCC
CPU
RESET
Unprogrammable Unprogrammable
**
2.1 Protection by CE, OE, WE
To realize the unprogrammable state, the input level of control pins must be held as shown in the
table below.
CE VCC × ×
OE × V
SS ×
WE × × V
CC
×: Don’t care.
VCC: Pull-up to VCC level.
VSS: Pull-down to VSS level.
2.2 Protection by RES (only the HN58V66A series)
The unprogrammable state can be realized by that the CPU’s reset signal inputs directly to the
EEPROM’s RES pin. RES should be kept VSS level during VCC on/off. The EEPROM breaks off
programming operation when RES becomes low, programming operation doesn’t finish correctly
in case that RES falls low during programming operation. RES should be kept high for 10 ms
after the last data input.
V
CC
RES
WE
or
CE
100 µs min 10 ms min
1 µs min
Program inhibit Program inhibit
HN58V65A Series, HN58V66A Series
Rev.3.00, Dec. 04.2003, page 23 of 26
3. Software data protection
To prevent unintentional programming caused by noise generated by external circuits, this device has
the software data protection function. In software data protection mode, 3 bytes of data must be input
before write data as follows. And these bytes can switch the non-protection mode to the protection
mode. SDP is enabled if only the 3 bytes code is input.
Data
AA
↓
55
↓
A0
↓
Write data }
Address
1555
↓
0AAA
↓
1555
↓
Write address Normal data input
Software data protection mode can be cancelled by inputting the following 6 bytes. After that, this
device turns to the non-protection mode and can write data normally. But when the data is input in the
cancelling cycle, the data cannot be written.
Data
AA
↓
55
↓
80
↓
AA
↓
55
↓
20
Address
1555
↓
0AAA
↓
1555
↓
1555
↓
0AAA
↓
1555
The software data protection is not enabled at the ship ment.
Note: There are some differences between Renesas Technology’s and other company’s for enable/disable
sequence of software data protection. If there are any questions , please contact with Renesas
Technology’s sales offices.
HN58V65A Series, HN58V66A Series
Rev.3.00, Dec. 04.2003, page 24 of 26
Package Dimensions
HN58V65AP Series
HN58V66AP Series (DP-28, DP-28V)
Package Code
JEDEC
JEITA
Mass
(reference value)
DP-28, DP-28V
—
Conforms
4.6 g
0.51 Min
2.54 Min
0.25
+ 0.11
– 0.05
2.54 ± 0.25 0.48 ± 0.10 0˚ – 15˚
15.24
1.2
35.6
36.5 Max
13.4
14.6 Max
114
15
28
5.70 Max
1.9 Max
Unit: mm
HN58V65A Series, HN58V66A Series
Rev.3.00, Dec. 04.2003, page 25 of 26
Package Dimensions (cont)
HN58V65AFP Series
HN58V66AFP Series (FP-28D, FP-28DV)
Package Code
JEDEC
JEITA
Mass
(reference value)
FP-28D, FP-28DV
Conforms
—
0.7 g
*Dimension including the plating thickness
Base material dimension
0˚ – 8˚
*0.17 ± 0.05
1.0 ± 0.2
0.20 ± 0.10
2.50 Max
8.4
18.3
18.8 Max
1.12 Max
28 15
114 11.8 ± 0.3
1.7
0.20
0.15
M
1.27
*0.40 ± 0.08
0.38 ± 0.06
0.15 ± 0.04
Unit: mm
HN58V65A Series, HN58V66A Series
Rev.3.00, Dec. 04.2003, page 26 of 26
Package Dimensions (cont)
HN58V65AT Series
HN58V66AT Series (T FP-28DB, TFP-2 8DBV)
Package Code
JEDEC
JEITA
Mass
(reference value)
TFP-28DB, TFP-28DBV
—
—
0.23 g
*Dimension including the plating thickness
Base material dimension
0.10
M
0.55
8.00
*0.22 ± 0.08
13.40 ± 0.30
*0.17 ± 0.05
0.13
1.20 Max
11.80
0˚ – 5˚
28
114
15
8.20 Max
0.10
+0.07
–0.08
0.50 ± 0.10
0.80
0.45 Max
0.20 ± 0.06
0.15 ± 0.04
Unit: mm
Revision History HN58V65A/HN58V66A Series Data Sheet
Contents of Modification Rev. Date
Page Description
0.0 Mar. 18. 1996 Initial issue
0.1 Nov. 12. 1996
Change of FP-28DA to DP-28
Addition of 5 V specification
0.2 Mar. 7. 1997
6
7
Change of page size: 32 byte to 64 byte
Recommended DC Operating Conditions
VCC (typ) : 0.3 V to
Addition of note 5
Change of note 2 (VIH = 2.4 V to VIH = 2.2 V)
DC Characteristics
ICC1 (min/typ/max): //20 µA to /1 to 2/5 µA
Change of Test conditions
ILI: VCC = 5.5 V, Vin = 5.5 V to Vin = 0 V to VCC
ILO: VCC = 5.5 V, Vout = 5.5/0.4 V to
Vout = 0 V to VCC
ICC1: CE = VCC to CE = VCC –0.3 V to VCC + 1 V
1.0 Aug. 28. 1997 7
8
12
20
DC Characteristics
ICC3: //10 µA to //8 µA
AC Characteristic
Input pules level: 0.4 V to VSS to 0 V to VSS
Timing Waveform
Read Timing Waveform: Correct error
Functional Description
Data Protection: Addition of description
2.0 Jan. 22.1998 Change of Subtitle
3.00 Dec. 04. 2003
2
24-26
Change format issued by Renesas Technology Corp.
Ordering Information
Addition of HN58V65AP-10E, HN58V66AP-10E, HN58V65AFP-10E,
HN58V66AFP-10E, HN58V65AT-10E, HN58V66AT-10E
Package Dimensions
DP-28 to DP-28, DP-28V
FP-28D to FP-28D, FP-28DV
TFP-28DB to TFP-28DB, TFP-28DBV
©
2003. Renesas Technolo
gy
Corp., All ri
g
hts reserved. Printed in Japan
.
Colo
p
hon 1.0
Keep safet
y
first in
y
our circuit desi
g
ns
!
1. Renesas Technolo
gy
Corp. puts the maximum effort into makin
g
semiconductor products better and more reliable, but there is alwa
y
s the possibilit
y
that trouble
m
a
y
occur with them. Trouble with semiconductors ma
y
lead to personal in
j
ur
y
, fire or propert
y
dama
g
e
.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of
publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is
therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product
information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor
home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to
evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes
no responsibility for any damage, liability or other loss resulting from the information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life
is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a
product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater
use.
6. The prior written approval of Renesas Technolo
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.
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other than the approved destination.
An
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diversion or reexport contrar
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s of Japan and/or the countr
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.
8. Please contact Renesas Technolo
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