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Rev 15 Feb 2013 14:22 | Page 1
BeMicro FPGA Project for AD5111 with Nios
driver
Supported Devices
AD5111
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AD5113
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AD5115
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Evaluation Boards
EVAL-AD5111SDZ
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Overview
This lab presents the steps to setup an environment for using the EVAL-AD5111SDZ evaluation
board together with the BeMicro SDK USB stick, the Nios II Embedded Development Suite (EDS) and
the Micrium μC-Probe run-time monitoring tool. Below is presented a picture of the EVAL-AD5111SDZ
Evaluation Board with the BeMicro SDK Platform.
For component evaluation and performance purposes, as opposed to quick prototyping, the user is
directed to use the part evaluation setup. This consists of:
1. A controller board like the SDP-B ( EVAL-SDP-CS1Z)
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2. The component SDP compatible product evaluation board
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3. Corresponding PC software ( shipped with the product evaluation board)
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The SDP-B controller board is part of Analog Devices System Demonstration Platform (SDP). It
provides a high speed USB 2.0 connection from the PC to the component evaluation board. The PC
runs the evaluation software. Each evaluation board, which is an SDP compatible daughter board,
includes the necessary installation file required for performance testing.
Note: it is expected that the analog performance on the two platforms may differ.
28 Sep 2012 08:00 · Adrian Costina
Below is presented a picture of SDP-B Controller Board with the EVAL-AD5111SDZ Evaluation Board.
The EVAL-AD5111SDZ evaluation board is a member of a growing number of boards available for
the SDP. Designed to help customers evaluate performance or quickly prototype new AD5111
circuits and reduce design time, the EVAL-AD5111SDZ evaluation board can operate in
single-supply and dual-supply mode and incorporates an internal power supply powered from the USB.
The AD5111 provides a nonvolatile solution for 128-/64-/32-position adjustment applications, offering
guaranteed low resistor tolerance errors of ±8% and up to ±6 mA current density in the A, B, and W
pins. The low resistor tolerance, low nominal temperature coefficient, and high bandwidth simplify
open-loop applications, as well as tolerance matching applications. The new low wiper resistance
feature minimizes the wiper resistance in the extremes of the resistor array to only 45 Ω, typical. A
simple 3-wire up/down interface allows manual switching or high speed digital control with clock rates
up to 50 MHz.
The EVAL-AD5111SDZ evaluation board is designed to help customers quickly prototype new
AD5111 circuits and reduce design time. The EVAL-AD5111SDZ incorporates several test circuits to
evaluate the AD5111 performance.
More information
AD5111 Product Info - pricing, samples, datasheet
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EVAL-AD5111SDZ evaluation board user guide
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BeMicro SDK
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Nios II Embedded Development Suite (EDS)
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Micrium uC-Probe
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Rev 15 Feb 2013 14:22 | Page 3
Getting Started
The first objective is to ensure that you have all of the items needed and to install the software tools
so that you are ready to create and run the evaluation project.
Hardware Items
Below is presented the list of required hardware items:
Arrow Electronics BeMicro SDK FPGA-based MCU Evaluation Board
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BeMicro SDK/SDP Interposer adapter board
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EVAL-AD5111SDZ evaluation board
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Intel Pentium III or compatible Windows PC, running at 866MHz or faster, with a minimum of 512MB
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of system memory
Software Tools
Below is presented the list of required software tools:
Quartus II Web Edition design software v11.0
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Nios II EDS v11.0
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uC-Probe run-time monitoring tool, version 2.5
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The Quartus II design software and the Nios II EDS is available via the Altera Complete Design Suite
DVD or by downloading from the web.
The Micrium uC/Probe Trial version 2.5 is available via download from the web at
http://micrium.com/tools/ucprobe/trial/. After installation add to the “Path” system variable the entry ”
%QUARTUS_ROOTDIR%\bin\“ on the third position in the list.
Downloads
Lab Design Files
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Extract the Lab Files
Create a folder called “ADIEvalBoardLab” on your PC and extract the ad5111_evalboardlab.zip
archive to this folder. Make sure that there are NO SPACES in the directory path. After extracting the
archive the following folders should be present in the ADIEvalBoardLab folder: FPGA, Software,
ucProbeInterface, NiosCpu.
Install the USB-Blaster Device Driver
After the Quartus II and Nios II software packages are installed, you can plug the BeMicro SDK
board into your USB port. Your Windows PC will find the new hardware and try to install the driver.
Since Windows cannot locate the driver for the device the automatic installation will fail and the driver
has to be installed manually. In the Device Manager right click on the USB-Blaster device and select
Update Driver Software.
Rev 15 Feb 2013 14:22 | Page 7
15 Sep 2011 14:23 · Andrei Cozma
Quick Evaluation
The next sections of this lab present all the steps needed to create a fully functional project that can
be used for evaluating the operation of the ADI platform. It is possible to skip these steps and load
into the FPGA an image that contains a fully functional system that can be used together with the
uC-Probe interface for the ADI platform evalution. The first step of the quick evaluation process is to
program the FPGA with the image provided in the lab files. Before the image can be loaded the
Quartus II Web Edition tool or the Quartus II Programmer must be installed on your computer. To
load the FPGA image run the program_fpga.bat batch file located in the ADIEvalBoardLab/FPGA
folder. After the image was loaded the system must be reset. Now the FPGA contains a fully functional
system and it is possible to skip directly to the DEMONSTRATION PROJECT USER INTERFACE
section of this lab.
15 Sep 2011 14:43 · Andrei Cozma
FPGA Design
The lab is delivered together with a set of design files that are used to evaluate the ADI part. The
FPGA image that must be loaded into the BeMicroSDK FPGA is included in the design files. This section
presents the components included in the FPGA image and also the procedure to load the image into
the FPGA.
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FPGA Components
The following components are implemented in the FPGA design:
Name Address IRQ
CPU 800 -
Main PLL 80 -
JTAG UART 90 0
uC-Probe UART A0 1
EPCS FLASH CONTROLLER 1800 2
OnChip RAM 10000 -
LED GPIO 100 -
SPI_0_P0 2000 4
SPI_1_P0 2040 6
GPIO 2080 -
CTRL GPIO 20A0 -
SPI_0_P1 0 5
SPI_1_P1 20 7
SYS ID 40 -
TIMER 60 3
I2C_0 C0 8
I2C_1 E0 9
Load the FPGA Image
To load the FPGA image the following steps must be performed:
Plug in the BeMicroSDK Stick into a USB port
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Start Altera Quartus Web edition and start the programmer by selecting the menu option
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Tools→Programmer
Select Add File and select the file ADIEvalBoardLab/FPGA/SDP1_bemicro2.jic
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Check the Program/Configure box and press Start
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After finishing, the image is permanently loaded to the configuration Flash and the system will start
with a blinking LED after reset or power up.
15 Sep 2011 14:47 · Andrei Cozma
NIOS II Software Design
This section presents the steps for developing a software application that will run on the
BeMicroSDK system and will be used for controlling and monitoring the operation of the ADI
evaluation board.
Create a new project using the NIOS II Software Build Tools
for Eclipse
Launch the Nios II SBT from the Start → All Programs → Altera → Nios II EDS 11.0 → Nios II
11.0 Software Build Tools for Eclipse (SBT).
NOTE: Windows 7 users will need to right-click and select Run as administrator. Another
method is to right-click and select Properties and click on the Compatibility tab and select the
Run This Program As An Administrator checkbox, which will make this a permanent change.
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1. Initialize Eclipse workspace
When Eclipse first launches, a dialog box appears asking what directory it should use for its
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workspace. It is useful to have a separate Eclipse workspace associated with each hardware project
that is created in SOPC Builder. Browse to the ADIEvalBoardLab directory and click Make New
Folder to create a folder for the software project. Name the new folder “eclipse_workspace”.
After selecting the workspace directory, click OK and Eclipse will launch and the workbench will
appear in the Nios II perspective.
2. Create a new software project in the SBT
Select File → New → Nios II Application and BSP from Template.
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Click the Browse button in the SOPC Information File Name dialog box.
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Select the uC.sopcinfo file located in the ADIEvalBoardLab/FPGA directory.
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Set the name of the Application project to “ADIEvalBoard”.
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Select the Blank Project template under Project template.
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Click the Finish button.
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The tool will create two new software project directories. Each Nios II application has 2 project
directories in the Eclipse workspace.
The application software project itself - this where the application lives.
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The second is the Board Support Package (BSP) project associated with the main application
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software project. This project will build the system library drivers for the specific SOPC system. This
project inherits the name from the main software project and appends “_bsp” to that.
Since you chose the blank project template, there are no source files in the application project
directory at this time. The BSP contains a directory of software drivers as well as a system.h header
file, system initialization source code and other software infrastructure.
Configure the Board Support Package
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Configure the board support package to specify the properties of this software system by using the
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BSP Editor tool. These properties include what interface should be used for stdio and stderr
messages, the memory in which stack and heap should be allocated and whether an operating
system or network stack should be included with this BSP.
Right click on the ADIEvalBoard_bsp project and select Nios II → BSP Editor… from the
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right-click menu.
The software project provided in this lab does not make use of an operating system. All stdout, stdin
and stderr messages will be directed to the jtag_uart.
Select the Common settings view. In the Common settings view, change the following settings:
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Select the jtag_uart for stdin, stdout and stderr messages. Note that you have more than one
❍
choice.
Select none for the sys_clk_timer and timestamp_timer.
❍
Rev 15 Feb 2013 14:22 | Page 13
Select File → Save to save the board support package configuration to the settings.bsp file.
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Click the Generate button to update the BSP.
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When the generate has completed, select File → Exit to close the BSP Editor.
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Configure BSP Project Build Properties
In addition to the board support package settings configured using the BSP Editor, there are other
compilation settings managed by the Eclipse environment such as compiler flags and optimization
level.
Right click on the ADIEvalBoard_bsp software project and select Properties from the right-click
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menu.
On the left-hand menu, select Nios II BSP Properties.
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During compilation, the code may have various levels of optimization which is a tradeoff between
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code size and performance. Change the Optimization level setting to Level 2
Since our software does not make use of C++, uncheck Support C++.
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Check the Reduced device drivers option
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Check the Small C library option
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Press Apply and OK to regenerate the BSP and close the Properties window.
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Rev 15 Feb 2013 14:22 | Page 14
Add source code to the project
In Windows Explorer locate the project directory which contains a directory called Software. In
Windows Explorer select all the files and directories from the Software folder and drag and drop
them into the Eclipse software project ADIEvalBoard.
Select all the files and folders and drag them over the ADIEvalBoard project in the SBT window and
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drop the files onto the project folder.
Rev 15 Feb 2013 14:22 | Page 15
A dialog box will appear to select the desired operation. Select the option Copy files and folders
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and press OK.
This should cause the source files to be physically copied into the file system location of the
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software project directory and register these source files within the Eclipse workspace so that they
appear in the Project Explorer file listing.
Configure Application Project Build Properties
Just as you configured the optimization level for the BSP project, you should set the optimization level
for the application software project ADIEvalBoard as well.
Right click on the ADIEvalBoard software project and select Properties from the right-click menu.
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On the left-hand menu, select the Nios II Application Properties tab
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Rev 15 Feb 2013 14:22 | Page 16
Change the Optimization level setting to Level 2.
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Press Apply and OK to save the changes.
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Define Application Include Directories
Application code can be conveniently organized in a directory structure. This section shows how to
define these paths in the makefile.
In the Eclipse environment double click on my_include_paths.in to open the file.
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Click the Ctrl and A keys to select all the text. Click the Ctrl and C keys to copy all the text.
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Double click on Makefile to open the file.
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If you see the message shown here about resources being out of sync, right click on the Makefile
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and select Refresh.
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Select the line APP_INCLUDE_DIRS :=
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Click the Ctrl and V keys to replace the selected line with the include paths.
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Click the Ctrl and S keys to save the Makefile.
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Compile, Download and Run the Software Project
1. Build the Application and BSP Projects
Right click the ADIEvalBoard_bsp software project and choose Build Project to build the board
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support package.
When that build completes, right click the ADIEvalBoard application software project and choose
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Build Project to build the Nios II application.
These 2 steps will compile and build the associated board support package, then the actual
application software project itself. The result of the compilation process will be an Executable and
Linked Format (.elf) file for the application, the ADIEvalBoard.elf file.
Rev 15 Feb 2013 14:22 | Page 18
2. Verify the Board Connection
The BeMicroSDK hardware is designed with a System ID peripheral. This peripheral is assigned a
unique value based on when the hardware design was last modified in the SOPC Builder tool. SOPC
Builder also places this information in the .sopcinfo hardware description file. The BSP is built based
on the information in the .sopcinfo file.
Select the ADIEvalBoard application software project.
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Rev 15 Feb 2013 14:22 | Page 19
Select Run → Run Configurations…
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Select the Nios II Hardware configuration type.
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Press the New button to create a new configuration.
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Change the configuration name to BeMicroSDK and click Apply.
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On the Target Connection tab, press the Refresh Connections button. You may need to expand
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the window or scroll to the right to see this button.
Select the jtag_uart as the Byte Stream Device for stdio.
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Check the Ignore mismatched system ID option.
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Check the Ignore mismatched system timestamp option.
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Rev 15 Feb 2013 14:22 | Page 20
3. Run the Software Project on the Target
To run the software project on the Nios II processor:
Press the Run button in the Run Configurations window.
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This will re-build the software project to create an up–to-date executable and then download the code
into memory on the BeMicroSDK hardware. The debugger resets the Nios II processor, and it
executes the downloaded code. Note that the code is verified in memory before it is executed.
The code size and start address might be different than the ones displayed in the above
screenshot.
12 Sep 2011 10:39 · Robin Getz
uC-Probe Interface
A notable challenge in embedded systems development is to overcome the lack of feedback that such
systems typically provide. Many developers resort to blinking LEDs or instrumenting their code with
printf() in order to determine whether or not their systems are running as expected. Micrium
provides a unique tool named μC-Probe to assist these developers. With this tool, developers can
effortlessly read and write the variables on a running embedded system. This section presents the
steps required to install the Micrium uC-Probe software tool and to run the demonstration project
for the ADI evaluation board. A description of the uC-Probe demonstration interface is provided.
Configure uC-Probe
Launch uC-Probe from the Start → All Programs → Micrium → uC-Probe.
Rev 15 Feb 2013 14:22 | Page 21
Select uC-Probe options.
Click on the uC-Probe icon on the top left portion of the screen.
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Click on the Options button to open the dialog box.
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Set target board communication protocol as JTAG UART
Click on the Communication tab icon on the top left portion of the dialog box
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Select the JTAG UART option.
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Setup JTAG UART communication settings
Select the JTAG-UART option from the Communication tab.
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Press the Open File button to select the JTAG Debug Information file (.jdi)
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Navigate to the ADIEvalBoardLab/FPGA folder and select the BeMicroSDK.jdi file. Press Open.
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Type the value 1 in the the Device Id window.
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Rev 15 Feb 2013 14:22 | Page 22
Select uCProbe_uart(0) from the Instance Id pulldown menu.
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Press Apply and OK to exit the options menu. The embedded target has two UARTs. uC-Probe will
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be communicating with the uCProbe_uart.
Load and Run the Demonstration Project
Click the Open option from the uC-Probe menu and select the file
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ADIEvalBoardLab/ucProbeInterface/AD5111_Interface.wsp.
Rev 15 Feb 2013 14:22 | Page 23
Before opening the interface uC-Probe will ask for a symbols file that must be associated with the
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interface. If the lab was done according to the steps provided in the Quick Evaluation section,
select the file ADIEvalBoardLab/ucProbeInterface/ADIEvalBoard.elf to be loaded as a symbol
file, otherwise select the file
ADIEvalBoardLab/FPGA/software/ADIEvalBoard/ADIEvalBoard.elf to be loaded as a symbol
file.
Run the demonstration project by pressing the Play button.
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Rev 15 Feb 2013 14:22 | Page 24
Demonstration Project User Interface
The following figure presents the uC-Probe interface that can be used for monitoring and controlling
the operation of the EVAL-AD5111SDZ evaluation board.
Section A is used to activate the board and monitor activity. The communication with the board is
activated / deactivated by toggling the ON/OFF switch. The Activity LED turns green when the
communication is active. If the ON/OFF switch is set to ON and the Activity LED is BLACK it means that
there is a communication problem with the board. See the Troubleshooting section for indications on
how to fix the communication problems.
Section B is used to set the operation mode, changing between manual increment or high speed
digital increment.
Section C is used to set the value programmed in high speed mode, using the slider provided.
Rev 15 Feb 2013 14:22 | Page 25
Section D is used to simulate a buton. By clicking it, you can increase/decrease the resistor value,
based on the Up/Down switch position.
Section E displays the current position of the wiper (between 0 and 128)
Troubleshooting
In case there is a communication problem with the board the follwing actions can be perfomed in
order to try to fix the issues:
Check that the evaluation board is powered.
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Check that the USB connection cable is properly connected to the device and to the computer and
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that the USB Blaster Device Driver driver is installed correctly. If the deriver is not correctly
installed perform the steps described in the Getting Started → Install te USB-Blaster Device
Driver section.
In uC-Probe right-click on the System Browser window select Remove Symbols. A dialog box will
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open to select the symbols to remove. Press OK to remove the symbols.
Rev 15 Feb 2013 14:22 | Page 26
After removing the symbols a new set of symbols must be added in order for the interface to be
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functional. In uC-Probe right-click on the System Browser window select Add Symbols. A dialog
box will open to select the symbols to be added. If the lab was done according to the steps provided
in the Quick Evaluation section, select the file
ADIEvalBoardLab/ucProbeInterface/ADIEvalBoard.elf to be loaded as a symbol file, otherwise
select the file ADIEvalBoardLab/FPGA/software/ADIEvalBoard/ADIEvalBoard.elf to be loaded
as a symbol file.
If the communication problem persists even after performing the previous steps, restart the
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uC-Probe application and try to run the interface again.
Rev 15 Feb 2013 14:22 | Page 27
More information
ask questions about the FPGA reference design
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Example questions:
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What do I need for FMCJESDADC1-EBZ eval? by rgetz
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AD9222 with Altera Stratix by rgetz
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Amplitude of digital signals after A/D is too small with FMCOMMS1-EBZ by Marchzh
❍
fmcomms1 i/q imbalance by Stu_Adaptive
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Probleme with I/Q samples fmcomms card by LKmi
❍
21 Sep 2011 08:17 · Andrei Cozma
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