LTC3869/LTC3869-2
1
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For more information www.linear.com/LTC3869
Typical applicaTion
DescripTion
Dual, 2-Phase
Synchronous Step-Down
DC/DC Controllers
The LT C
®
3869 is a high performance dual synchronous
step-down switching regulator controller that drives all
N-channel synchronous power MOSFET stages. A constant
frequency current mode architecture allows a phase-
lockable frequency of up to 780kHz. Power loss and noise
due to the ESR of the input capacitors are minimized by
operating the two controller output stages out-of-phase.
OPTI-LOOP
®
compensation allows the transient response
to be optimized over a wide range of output capacitance
and ESR values. A wide 4V to 38V input supply range
encompasses most battery chemistries. Independent TK/
SS pins for each controller ramp the output voltage during
start-up. Current foldback limits MOSFET heat dissipation
during short-circuit conditions. The MODE/PLLIN pin
selects among Burst Mode
®
operation, pulse-skipping
mode, or continuous inductor current mode and allows
the IC to be synchronized to an external clock.
The LTC3869 is available in low profile 4mm × 4mm and
4mm × 5mm QFN packages. The LTC3869-2 is available
in an SSOP-28 package. The LTC3869 is pin-compatible
with the LTC3850.
L, LT , LT C , LT M , Linear Technology, the Linear logo, µModule, OPTI-LOOP, Burst Mode
and PolyPhase are registered trademarks and No RSENSE is a trademark of Linear Technology
Corporation. All other trademarks are the property of their respective owners. Protected by
U.S. Patents including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6580258,
6498466, 6611131.
FeaTures
applicaTions
n Dual, 180° Phased Controllers Reduce Required
Input Capacitance and Power Supply Induced Noise
n Accurate Multiphase Current Matching
n RSENSE or DCR Current Sensing
n ±0.75% 0.6V Output Voltage Accuracy
n Phase-Lockable Fixed Frequency 250kHz to 780kHz
n High Efficiency: Up to 95%
n Dual N-channel MOSFET Synchronous Drive
n Wide VIN Range: 4V to 38V (40V Max) Operation
n Wide VOUT Range: 0.6V to 12.5V Operation
n Adjustable Soft-Start Current Ramping or Tracking
n Foldback Output Current Limiting
n Output Overvoltage Protection
n Power Good Output Voltage Monitor
n 5V Low Dropout Regulator
n Small 28-Lead QFN and Narrow SSOP Packages
n Server Systems
n Telecom Systems
n Industrial and Medical Instruments
n High Power Battery-Operated Devices
n DC Power Distribution Systems
High Efficiency Dual 5V/3.3V Step-Down Converter Efficiency and Power Loss
LOAD CURRENT (A)
0.01
EFFICIENCY (%)
POWER LOSS (mW)
100
10
90
70
50
30
80
60
40
20
0
1300
500
1000
1100
1200
400
700
600
3869 TA01b
1010.1
EFFICIENCY
POWER LOSS
900
800
VIN = 12V, VOUT = 3.3V
VIN = 12V, VOUT = 5V
147k
470pF
22µF
47µF 20k
15k
V
OUT1
5V
5A
470pF 56µF
20k
15k
122k
VOUT2
3.3V
5A
TG1 TG2
BOOST1 BOOST2
SW1 SW2
BG1 BG2
PGND
FREQ
SENSE1+SENSE2+
PINS NOT USED IN
THIS CIRCUIT:
ILIM, MODE/PLLIN,
PGOOD, RUN1, RUN2
SENSE1–SENSE2–
VFB1 VFB2
ITH1
ITH2
VIN INTVCC
TK/SS1 TK/SS2
V
IN
7V TO
24V
3869 TA01
SGND
0.1µF 0.1µF
LTC3869
4.7µF
+
+
+
90.9k
LTC3869/LTC3869-2
2
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For more information www.linear.com/LTC3869
absoluTe MaxiMuM raTings
(Note 1)
pin conFiguraTion
orDer inForMaTion
Input Supply Voltage: VIN ........................... 40V to –0.3V
Top Side Driver Voltages:
BOOST1, BOOST2 ...................................... 46V to –0.3V
Switch Voltage: SW1, SW2 ........................... 40V to –5V
INTVCC, RUN1, RUN2, PGOOD, EXTVCC,
BOOST1-SW1, BOOST2-SW2 ....................... 6V to –0.3V
SENSE1+, SENSE2+, SENSE1–,
SENSE2– Voltages ......................................13V to –0.3V
MODE/PLLIN, ILIM, TK/SS1, TK/SS2,
FREQ Voltages ......................................INTVCC to –0.3V
ITH1, ITH2, VFB1, VFB2 Voltages .............INTVCC to –0.3V
INTVCC Peak Output Current ................................100mA
Operating Junction Temperature Range
(Note 2) ..................................................–40°C to 125°C
Junction Temperature (Note 3) ............................. 125°C
Storage Temperature Range ..................–65°C to 150°C
Lead Temperature (Soldering, 10 sec)
GN Package ...................................................... 300°C
9 10
TOP VIEW
SGND
29
UFD PACKAGE
28-LEAD (4mm × 5mm) PLASTIC QFN
11 12 13
28 27 26 25 24
14
23
6
5
4
3
2
1
SENSE1–
TK/SS1
ITH1
VFB1
VFB2
ITH2
TK/SS2
SENSE2–
BOOST1
BG1
VIN
INTVCC
BG2
PGND
BOOST2
TG2
SENSE1+
RUN1
FREQ
MODE/PLLIN
SW1
TG1
SENSE2+
RUN2
ILIM
EXTVCC
PGOOD
SW2
7
17
18
19
20
21
22
16
815
TJMAX = 125°C, θJA = 34°C/W,
EXPOSED PAD (PIN 29) IS SGND, MUST BE
SOLDERED TO PCB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
GN PACKAGE
28-LEAD PLASTIC SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RUN1
SENSE1+
SENSE1–
VFB1
TK/SS1
ITH1
SGND
ITH2
TK/SS2
VFB2
SENSE2–
SENSE2+
RUN2
EXTVCC
FREQ
MODE/PLLIN
SW1
TG1
BOOST1
BG1
VIN
INTVCC
BG2
PGND
BOOST2
TG2
SW2
PGOOD
TJMAX = 125°C, θJA = 80°C/W
28 27 26 25 24 23
8 9
TOP VIEW
SGND
29
UF PACKAGE
28-LEAD (4mm × 4mm) PLASTIC QFN
10 11 12 13 14
TK/SS1
ITH1
VFB1
VFB2
ITH2
TK/SS2
SENSE2
–
BOOST1
BG1
VIN
INTVCC
BG2
PGND
BOOST2
SENSE1–
SENSE1+
RUN1
FREQ
MODE/PLLIN
SW1
TG1
SENSE2+
RUN2
ILIM
EXTVCC
PGOOD
SW2
TG2
16
15
17
18
19
20
21
6
7
5
4
3
2
1
22
TJMAX = 125°C, θJA = 37°C/W, θJC = 2.6°C/W
EXPOSED PAD (PIN 29) IS SGND, MUST BE
SOLDERED TO PCB
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3869EUF#PBF LTC3869EUF#TRPBF 3869 28-Lead (4mm × 4mm) Plastic QFN –40°C to 125°C
LTC3869IUF#PBF LTC3869IUF#TRPBF 3869 28-Lead (4mm × 4mm) Plastic QFN –40°C to 125°C
LTC3869EUFD#PBF LTC3869EUFD#TRPBF 3869 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C
LTC3869IUFD#PBF LTC3869IUFD#TRPBF 3869 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C
LTC3869IGN-2#PBF LTC3869IGN-2#TRPBF LTC3869GN-2 28-Lead Narrow Plastic SSOP –40°C to 125°C
Consult LT C Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LT C Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
LTC3869/LTC3869-2
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SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loops
VIN Input Voltage Range 4 38 V
VOUT Output Voltage Range 0.6 12.5 V
VFB1,2 Regulated Feedback Voltage
(Notes 2, 4)
ITH1,2 Voltage = 1.2V, 0°C to 85°C
ITH1,2 Voltage = 1.2V, –40°C to 125°C
l
l
0.5955
0.5940
0.600
0.600
0.6045
0.6060
V
V
IFB1,2 Feedback Current (Note 4) –15 –50 nA
VREFLNREG Reference Voltage Line Regulation VIN = 4.0V to 38V (Note 4) 0.002 0.01 %/V
VLOADREG Output Voltage Load Regulation (Note 4)
Measured in Servo Loop; ∆ITH Voltage = 1.2V to 0.7V
Measured in Servo Loop; ∆ITH Voltage = 1.2V to 1.6V
l
l
0.01
–0.01
0.1
–0.1
%
%
gm1,2 Transconductance Amplifier gmITH1,2 = 1.2V; Sink/Source 5µA; (Note 4) 2 mmho
IQInput DC Supply Current
Normal Mode
Shutdown
(Note 5)
VIN = 15V
VRUN1,2 = 0V
3
30
50
mA
µA
DFMAX Maximum Duty Factor In Dropout 94 95 %
UVLO Undervoltage Lockout VINTVCC Ramping Down l3.0 3.2 3.4 V
UVLOHYS UVLO Hysteresis 0.6 V
VOVL Feedback Overvoltage Lockout Measured at VFB1,2 l0.64 0.66 0.68 V
ISENSE Sense Pins Bias Current (Each Channel); VSENSE1,2 = 3.3V l±1 ±2 µA
ITK/SS1,2 Soft-Start Charge Current VTK/SS1,2 = 0V l1.0 1.25 1.5 µA
VRUN1,2 RUN Pin On Threshold VRUN1, VRUN2 Rising l1.1 1.22 1.35 V
VRUN1,2(HYS)RUN Pin On Hysteresis 80 mV
VSENSE(MAX) Maximum Current Sense Threshold,
0°C to 85°C (Note 2)
VFB1,2 = 0.5V, VSENSE1,2 = 3.3V, ILIM = 0V
VFB1,2 = 0.5V, VSENSE1,2 = 3.3V, ILIM = Float
VFB1,2 = 0.5V, VSENSE1,2 = 3.3V, ILIM = INTVCC
l
l
l
25
45
68
30
50
75
35
55
82
mV
mV
mV
Maximum Current Sense Threshold,
–40°C to 125°C (Note 2)
VFB1,2 = 0.5V, VSENSE1,2 = 3.3V, ILIM = 0V
VFB1,2 = 0.5V, VSENSE1,2 = 3.3V, ILIM = Float
VFB1,2 = 0.5V, VSENSE1,2 = 3.3V, ILIM = INTVCC
VFB1,2 = 0.5V, VSENSE1,2 = 3.3V, LTC3869IGN-2
l
l
l
l
23
43
68
40
30
50
75
50
37
57
82
60
mV
mV
mV
mV
VMISMATCH Channel to Channel Current Sense
Mismatch Voltage of VSENSE(MAX)
ILIM = Float 2 mV
TG1, 2 tr
TG1, 2 tf
TG Transition Time:
Rise Time
Fall Time
(Note 8)
CLOAD = 3300pF
CLOAD = 3300pF
25
25
ns
ns
BG1, 2 tr
BG1, 2 tf
BG Transition Time:
Rise Time
Fall Time
(Note 8)
CLOAD = 3300pF
CLOAD = 3300pF
25
25
ns
ns
TG/BG t1D Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time
CLOAD = 3300pF Each Driver (Note 6) 30 ns
BG/TG t2D Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time
CLOAD = 3300pF Each Driver (Note 6) 30 ns
tON(MIN) Minimum On-Time (Note 7) 90 ns
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 15V, VRUN1,2 = 5V unless otherwise noted.
LTC3869/LTC3869-2
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Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3869 is tested under pulsed load conditions such that
TJ ≈ TA. The LTC3869E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 125°C operating
junction temperature range are assured by design, characterization
and correlation with statistical process controls. The LTC3869I is
guaranteed to meet performance specifications over the full –40°C to
125°C operating junction temperature range. The maximum ambient
temperature consistent with these specifications is determined by specific
operating conditions in conjunction with board layout, the package thermal
impedance and other environmental factors.
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 15V, VRUN1,2 = 5V unless otherwise noted.
Note 3: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formulas:
LTC3869UFD: TJ = TA + (PD • 34°C/W)
LTC3869GN-2: TJ = TA + (PD • 80°C/W)
LTC3869UFD: TJ = TA + (PD • 37°C/W)
Note 4: The LTC3869 is tested in a feedback loop that servos VITH1,2 to a
specified voltage and measures the resultant VFB1,2.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 6: Delay times are measured using 50% levels.
Note 7: The minimum on-time condition is specified for an inductor
peak-to-peak ripple current ≥40% of IMAX (see Minimum On-Time
Considerations in the Applications Information section).
Note 8: Guaranteed by design.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
INTVCC Linear Regulator
VINTVCC Internal VCC Voltage 6V < VIN < 38V 4.8 5 5.2 V
VLDO INT INTVCC Load Regulation ICC = 0mA to 20mA 0.5 2 %
VEXTVCC EXTVCC Switchover Voltage EXTVCC Ramping Positive l4.5 4.7 V
VLDOHYS EXTVCC Hysteresis 200 mV
VLDO EXT EXTVCC Voltage Drop ICC = 20mA, VEXTVCC = 5V 50 100 mV
PGOOD Output
VPGL PGOOD Voltage Low IPGOOD = 2mA 0.1 0.3 V
IPGOOD PGOOD Leakage Current VPGOOD = 5V ±2 µA
VPG PGOOD Trip Level VFB with Respect to Set Output Voltage
VFB Ramping Negative
VFB Ramping Positive
–10
10
%
%
Oscillator and Phase-Locked Loop
fNOM Nominal Frequency VFREQ = 1.2V 450 500 550 kHz
fLOW Lowest Frequency VFREQ = 0V 210 250 290 kHz
fHIGH Highest Frequency VFREQ ≥ 2.4V 700 780 850 kHz
RMODE/PLLIN MODE/PLLIN Input Resistance 250 kΩ
IFREQ Frequency Setting Current 9 10 11 µA
On Chip Driver
TG RUP TG Pull-Up RDS(ON) TG High 2.6 Ω
TG RDOWN TG Pull-Down RDS(ON) TG Low 1.5 Ω
BG RUP BG Pull-Up RDS(ON) BG High 2.4 Ω
BG RDOWN BG Pull-Down RDS(ON) BG Low 1.1 Ω
LTC3869/LTC3869-2
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Efficiency vs Output Current
and Mode
Efficiency vs Output Current
and Mode
Full Load Efficiency and Power
Loss vs Input Voltage
LOAD CURRENT (A)
0.01
EFFICIENCY (%)
100
10
90
70
50
30
80
60
40
20
010
3869 G01
10010.1
VIN = 12V
VOUT = 1.8V
Burst Mode
OPERATION
DCM
CCM
CIRCUIT OF FIGURE 16
LOAD CURRENT (A)
0.01
EFFICIENCY (%)
100
10
90
70
50
30
80
60
40
20
010
3869 G02
10010.1
VIN = 12V
VOUT = 1.2V
Burst Mode
OPERATION
DCM
CCM
CIRCUIT OF FIGURE 16
INPUT VOLTAGE (V)
5
75
EFFICIENCY (%)
80
85
90
2
POWER LOSS (W)
3
4
5
10 2015
3869 G03
1.8V
1.8V
1.2V
1.2V
EFFICIENCY
POWER LOSS
CIRCUIT OF FIGURE 16
Typical perForMance characTerisTics
Load Step
(Burst Mode Operation)
Load Step
(Forced Continuous Mode)
Load Step
(Pulse-Skipping Mode)
Inductor Current at Light Load Prebiased Output at 2V
TA = 25°C, unless otherwise noted.
VIN = 12V
VOUT = 1.8V
ILOAD = 400mA
1µs/DIV 3869 G07
FORCED
CONTINUOUS
MODE
5A/DIV
Burst Mode
OPERATION
5A/DIV
PULSE-
SKIPPING
MODE
5A/DIV
VIN = 12V
VOUT = 3.3V
2ms/DIV 3869 G08
TK/SS
500mV/DIV
VFB
500mV/DIV
VOUT
2V/DIV
VIN = 12V
VOUT = 1.8V
50µs/DIV 3869 G04
IL
5A/DIV
VOUT
100mV/DIV
AC-COUPLED
ILOAD
5A/DIV
300mA TO 5A
VIN = 12V
VOUT = 1.8V
50µs/DIV 3869 G05
IL
5A/DIV
VOUT
100mV/DIV
AC-COUPLED
ILOAD
5A/DIV
300mA TO 5A
VIN = 12V
VOUT = 1.8V
50µs/DIV 3869 G06
IL
5A/DIV
VOUT
100mV/DIV
AC-COUPLED
ILOAD
5A/DIV
300mA TO 5A
LTC3869/LTC3869-2
6
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For more information www.linear.com/LTC3869
Typical perForMance characTerisTics
Current Sense Threshold
vs ITH Voltage
Maximum Current Sense
Threshold vs Common Mode
Voltage
Maximum Current Sense
Threshold vs Duty Cycle
Maximum Current Sense Voltage
vs Feedback Voltage (Current
Foldback)
Tracking Up and Down
with External Ramp
Quiescent Current without EXTVCC
vs Temperature INTVCC Line Regulation
VIN = 12V
VOUT1 = 1.8V, 1.5Ω LOAD
VOUT2 = 1.2V, 1Ω LOAD
10ms/DIV 3869 G10
TK/SS1
TK/SS2
2V/DIV
VOUT1
VOUT2
500mA/DIV
VOUT1
VOUT2
INTVCC VOLTAGE (V)
5.5
5.0
4.5
4.0
3.0
3.5
2.5
2.0
INPUT VOLTAGE (V)
0 10 30
3869 G12
4020
VITH (V)
0
–40
VSENSE (mV)
–20
0
20
40
60
80
0.5 1 1.5 2
3869 G13
ILIM = GND
ILIM = FLOAT
ILIM = INTVCC
VSENSE COMMON MODE VOLTAGE (V)
0
CURRENT SENSE THRESHOLD (mV)
30
40
50
12
20
10
02 6 8 10
4
60
70
80
3869 G14
ILIM = GND
ILIM = FLOAT
ILIM = INTVCC
60
80
40
20
50
70
30
10
0
DUTY CYCLE (%)
0
CURRENT SENSE THRESHOLD (mV)
60 100
20 40 80
3869 G15
ILIM = GND
ILIM = FLOAT
ILIM = INTVCC
FEEDBACK VOLTAGE (V)
0
MAXIMUM CURRENT SENSE THRESHOLD (mV)
30
40
50
0.6
20
10
00.1 0.3 0.4 0.5
0.2
60
70
90
80
3869 G16
ILIM = GND
ILIM = FLOAT
ILIM = INTVCC
TA = 25°C, unless otherwise noted.
QUIESCENT CURRENT (mA)
4.0
3.0
2.0
1.0
3.5
2.5
1.5
0.5
0
TEMPERATURE (°C)
–50 500 100
3869 G11
12525–25 75
Coincident Tracking
5ms/DIV 3869 G09
RUN
2V/DIV
VOUT1
VOUT2
1V/DIV
VOUT1
VOUT2
VOUT1 = 1.8V, 1.5Ω LOAD
VOUT2 = 1.2V, 1Ω LOAD
LTC3869/LTC3869-2
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TK/SS Pull-Up Current
vs Temperature
TK/SS CURRENT (µA)
1.6
1.2
1.4
1.0
TEMPERATURE (°C)
–50 500 100
3869 G17
12525–25 75
Typical perForMance characTerisTics
Undervoltage Lockout Threshold
(INTVCC) vs Temperature
Oscillator Frequency
vs Input Voltage
Shutdown (RUN) Threshold
vs Temperature
Regulated Feedback Voltage
vs Temperature
Oscillator Frequency
vs Temperature
TEMPERATURE (°C)
–50
900
800
700
500
600
0
100
200
300
400
25 75
3869 G20
–25 0 50 125100
FREQUENCY (kHz)
VFREQ = GND
VFREQ = 1.2V
VFREQ = INTVCC
TEMPERATURE (°C)
–40
4.1
3.9
2.9
3.7
2.7
3.1
3.5
2.5
3.3
20 60
3869 G21
–20 0 40 10080
UVLO THRESHOLD (V)
FALLING
RISING
INPUT VOLTAGE (V)
5
520
510
500
490
480 25 35
3869 G22
10 15 20 4030
FREQUENCY (kHz)
TA = 25°C, unless otherwise noted.
TEMPERATURE (°C)
–50
1.24
1.22
1.20
1.18
1.12
1.16
1.14
1.10
1.08 25 75
3869 G18
–25 0 50 125100
RUN PIN THRESHOLD (V)
OFF
ON
TEMPERATURE (°C)
–40
604
602
600
598
590
592
594
596
35 85
3869 G19
–15 10 60 125110
REGULATED FEEDBACK VOLTAGE (mV)
LTC3869/LTC3869-2
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Shutdown Current
vs Input Voltage
Shutdown Current
vs Temperature
Quiescent Current
vs Input Voltage without EXTVCC
INPUT VOLTAGE (V)
5
60
50
40
30
20
10
025 35
3869 G23
10 15 20 4030
SHUTDOWN INPUT CURRENT (µA)
INPUT VOLTAGE (V)
5
3.8
3.6
3.4
2.6
2.4
1.8
2.0
2.2
2.8
3.0
3.2
25 35
3869 G25
10 15 20 4030
SUPPLY CURRENT (mA)
45
40
35
30
20
10
25
15
5
0
3869 G24
SHUTDOWN CURRENT (µA)
TEMPERATURE (°C)
–50 25 75
–25 0 50 125100
Typical perForMance characTerisTics
TA = 25°C, unless otherwise noted.
LTC3869/LTC3869-2
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pin FuncTions
RUN1, RUN2 (Pin 26, Pin 9/Pin 27, Pin 10/Pin 1, Pin
13): Run Control Inputs. A voltage above 1.2V on either
pin turns on the IC. However, forcing either of these pins
below 1.2V causes the IC to shut down the circuitry required
for that particular channel. There are 1µA pull-up currents
for these pins. Once the RUN pin raises above 1.2V, an
additional 4.5µA pull-up current is added to the pin.
VFB1, VFB2 (Pin 3, Pin 4/Pin 4, Pin 5/Pin 4, Pin 10): Error
Amplifier Feedback Inputs. These pins receive the remotely
sensed feedback voltages for each channel from external
resistive dividers across the outputs.
ITH1, ITH2 (Pin 2, Pin 5/Pin 3, Pin 6/Pin 6, Pin 8): Current
Control Thresholds and Error Amplifier Compensation
Points. Each associated channels’ current comparator
tripping threshold increases with its ITH control voltage.
SGND (Pin 29/Pin 29/Pin 7): Signal Ground. All small-
signal components and compensation components should
connect to this ground, which in turn connects to PGND
at one point. Pin 29 is the exposed pad, only available for
the UF/UFD package. The exposed pad must be soldered
to PCB ground for electrical connection and rated thermal
performance.
TK/SS1, TK/SS2 (Pin 1, Pin 6/Pin 2, Pin 7/Pin 5, Pin
9): Output Voltage Tracking and Soft-Start Inputs. When
one particular channel is configured to be the master of
two channels, a capacitor to ground at this pin sets the
ramp rate for the master channel’s output voltage. When
the channel is configured to be the slave of two channels,
the VFB voltage of the master channel is reproduced by a
resistor divider and applied to this pin. Internal soft-start
currents of 1.2µA are charging these pins.
MODE/PLLIN (Pin 24/Pin 25/Pin 27): Forced Continuous
Mode, Burst Mode Operation, or Pulse-Skipping Mode
Selection Pin and External Synchronization Input to Phase
Detector Pin. Connect this pin to SGND to force both chan-
nels in continuous mode of operation. Connect to INTVCC
to enable pulse-skipping mode of operation. Leave the
pin floating will enable Burst Mode operation. A clock on
the pin will force the controller into continuous mode of
operation and synchronize the internal oscillator with the
clock on this pin. The PLL compensation components are
integrated inside the IC.
FREQ (Pin 25/Pin 26/Pin 28): There is a precision 10µA
current flowing out of this pin. Connect a resistor to ground
set the controllers’ operating frequency. Alternatively, this
pin can be driven with a DC voltage to vary the frequency
of the internal oscillator.
ILIM (Pin 10/Pin 11/NA): Current Comparator Sense
Voltage Range Inputs. This pin is to be programmed to
SGND, FLOAT or INTVCC to set the maximum current
sense threshold to three different levels for each compara-
tor. The current limit default value is set to be 50mV for
LTC3869GN-2.
EXTVCC (Pin 11/Pin 12/Pin 14): External Power Input
to an Internal Switch Connected to INTVCC. This switch
closes and supplies the IC power, bypassing the internal
low dropout regulator, whenever EXTVCC is higher than
4.7V. Do not exceed 6V on this pin.
VIN (Pin 19/Pin 20/Pin 22): Main Input Supply. Decouple
this pin to PGND with a capacitor (0.1µF to 1µF).
BOOST1, BOOST2 (Pin 21, Pin 15/Pin 22, Pin 16/Pin
24, Pin 18): Boosted Floating Driver Supplies. The (+)
terminal of the booststrap capacitors connect to these
pins. These pins swing from a diode voltage drop below
INTVCC up to VIN + INTVCC.
TG1, TG2 (Pin 22, Pin 14/Pin 23, Pin 15/Pin 25, Pin 17):
Top Gate Driver Outputs. These are the outputs of floating
drivers with a voltage swing equal to INTVCC superimposed
on the switch nodes voltages.
(UF/UFD/GN)
LTC3869/LTC3869-2
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SW1, SW2 (Pin 23, Pin 13/Pin 24, Pin 14/Pin 26, Pin
16): Switch Node Connections to Inductors. Voltage swing
at these pins is from a Schottky diode (external) voltage
drop below ground to VIN.
SENSE1+, SENSE2+ (Pin 27, Pin 8/Pin 28, Pin 9/Pin 2,
Pin 12): Current Sense Comparator Inputs. The (+) inputs
to the current comparators are normally connected to DCR
sensing networks or current sensing resistors.
SENSE1–, SENSE2– (Pin 28, Pin 7/Pin 1, Pin 8/Pin 3,
Pin 11): Current Sense Comparator Inputs. The (–) inputs
to the current comparators are connected to the outputs.
PGND (Pin 16/Pin 17/Pin 19): Power Ground Pin. Connect
this pin closely to the sources of the bottom N-channel
MOSFETs, the (–) terminal of CVCC and the (–) terminal
of CIN.
BG1, BG2 (Pin 20, Pin 17/Pin 21, Pin 18/Pin 23, Pin
20): Bottom Gate Driver Outputs. These pins drive the
gates of the bottom N-channel MOSFETs between PGND
and INTVCC.
INTVCC (Pin 18/Pin 19/Pin 21): Internal 5V Regulator
Output. The control circuits are powered from this voltage.
Decouple this pin to PGND with a minimum of 4.7µF low
ESR tantalum or ceramic capacitor. It is not recommended
to power other applications with this power source.
PGOOD (Pin 12/Pin 13/Pin 15): Power Good Indicator
Output. Open drain logic out that is pulled to ground when
either channel output exceeds ±10% regulation windows,
after the internal 20µs power bad mask timer expires.
pin FuncTions
(UF/UFD/GN)
LTC3869/LTC3869-2
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FuncTional block DiagraM
4.7V
–
+
+–
–
+
VIN
1µA
SLOPE COMPENSATION
UVLO
LTC3869
UF/UFD
ONLY
SLOPE RECOVERY
ACTIVE CLAMP
OSC S
RQ
3k
RUN
SWITCH
LOGIC
AND
ANTI-
SHOOT
THROUGH
BG
ON
FCNT
0.6V
OV
1.2V0.5V
ITH RC
INTVCC
INTVCC
ILIM
ICMP
CC1
SS SGND
R1
0.66V
R2
RUN
PGND
PGOOD
INTVCC
EXTVCC
IREV
SW
TG CB
VIN
CIN
VIN SLEEP
BOOST
BURSTEN
–
+
–
+
UV
OV
CVCC
VOUT
COUT
M2
M1
L1
DB
MODE/PLLIN
SENSE+
SENSE–
–+
0.6V
REF
TK/SSRUN
0.5V
+–
VFB
FREQ
PLL-SYNC
MODE/SYNC
DETECT
+
5V
REG
1.2µA
CSS
+
–+
–+
F
F
0.54V
3869 FD
1
51k
ITHB
–+
EA
+
10µA
LTC3869/LTC3869-2
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For more information www.linear.com/LTC3869
operaTion
Main Control Loop
The LTC3869 is a constant-frequency, current mode step-
down controller with two channels operating 180 degrees
out-of-phase. During normal operation, each top MOSFET
is turned on when the clock for that channel sets the RS
latch, and turned off when the main current comparator,
ICMP, resets the RS latch. The peak inductor current at
which ICMP resets the RS latch is controlled by the voltage
on the ITH pin, which is the output of each error ampli-
fier EA. The VFB pin receives the voltage feedback signal,
which is compared to the internal reference voltage by the
EA. When the load current increases, it causes a slight
decrease in VFB relative to the 0.6V reference, which in
turn causes the ITH voltage to increase until the average
inductor current matches the new load current. After the
top MOSFET has turned off, the bottom MOSFET is turned
on until either the inductor current starts to reverse, as
indicated by the reverse current comparator IREV, or the
beginning of the next cycle.
INTVCC/EXTVCC Power
Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTVCC pin.
When the EXTVCC pin is left open or tied to a voltage less
than 4.7V, an internal 5V linear regulator supplies INTVCC
power from VIN. If EXTVCC is taken above 4.7V, the 5V
regulator is turned off and an internal switch is turned on
connecting EXTVCC. Using the EXTVCC pin allows the INTVCC
power to be derived from a high efficiency external source
such as one of the LTC3869 switching regulator outputs.
Each top MOSFET driver is biased from the floating
bootstrap capacitor CB, which normally recharges during
each off cycle through an external diode when the top
MOSFET turns off. If the input voltage VIN decreases to
a voltage close to VOUT, the loop may enter dropout and
attempt to turn on the top MOSFET continuously. The
dropout detector detects this and forces the top MOSFET
off for about one-twelfth of the clock period plus 100ns
every third cycle to allow CB to recharge. However, it is
recommended that a load be present or the IC operates
at low frequency during the drop-out transition to ensure
CB is recharged.
Shutdown and Start-Up (RUN1, RUN2 and TK/SS1,
TK/SS2 Pins)
The two channels of the LTC3869 can be independently
shut down using the RUN1 and RUN2 pins. Pulling either
of these pins below 1.2V shuts down the main control
loop for that controller. Pulling both pins low disables
both controllers and most internal circuits, including the
INTVCC regulator. Releasing either RUN pin allows an
internal 1µA current to pull up the pin and enable that
controller. Alternatively, the RUN pin may be externally
pulled up or driven directly by logic. Be careful not to
exceed the Absolute Maximum Rating of 6V on this pin.
The start-up of each controller’s output voltage VOUT is
controlled by the voltage on the TK/SS1 and TK/SS2 pins.
When the voltage on the TK/SS pin is less than the 0.6V
internal reference, the LTC3869 regulates the VFB voltage
to the TK/SS pin voltage instead of the 0.6V reference. This
allows the TK/SS pin to be used to program the soft-start
period by connecting an external capacitor from the TK/SS
pin to SGND. An internal 1.2µA pull-up current charges
this capacitor, creating a voltage ramp on the TK/SS pin.
As the TK/SS voltage rises linearly from 0V to 0.6V (and
beyond), the output voltage VOUT rises smoothly from zero
to its final value. Alternatively the TK/SS pin can be used
to cause the start-up of VOUT to “track” that of another
supply. Typically, this requires connecting to the TK/SS
pin an external resistor divider from the other supply to
ground (see the Applications Information section). When
the corresponding RUN pin is pulled low to disable a
controller, or when INTVCC drops below its undervoltage
lockout threshold of 3.2V, the TK/SS pin is pulled low
by an internal MOSFET. When in undervoltage lockout,
both controllers are disabled and the external MOSFETs
are held off.
LTC3869/LTC3869-2
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Light Load Current Operation (Burst Mode Operation,
Pulse-Skipping, or Continuous Conduction)
The LTC3869 can be enabled to enter high efficiency Burst
Mode operation, constant-frequency pulse-skipping mode,
or forced continuous conduction mode. To select forced
continuous operation, tie the MODE/PLLIN pin to a DC
voltage below 0.6V (e.g., SGND). To select pulse-skipping
mode of operation, tie the MODE/PLLIN pin to INTVCC. To
select Burst Mode operation, float the MODE/PLLIN pin.
When a controller is enabled for Burst Mode operation,
the peak current in the inductor is set to approximately
one-third of the maximum sense voltage even though the
voltage on the ITH pin indicates a lower value. If the average
inductor current is higher than the load current, the error
amplifier EA will decrease the voltage on the ITH pin. When
the ITH voltage drops below 0.5V, the internal sleep signal
goes high (enabling sleep mode) and the top MOSFET is
turned off immediately, but the bottom MOSFET is turned
off when the inductor current reaches zero.
In sleep mode, the load current is supplied by the output
capacitor. As the output voltage decreases, the EA’s output
begins to rise. When the output voltage drops enough, the
sleep signal goes low, and the controller resumes normal
operation by turning on the top external MOSFET on the
next cycle of the internal oscillator. When a controller is
enabled for Burst Mode operation, the inductor current is
not allowed to reverse. The reverse current comparator
(IREV) turns off the bottom external MOSFET just before
the inductor current reaches zero, preventing it from
reversing and going negative. Thus, the controller oper-
ates in discontinuous operation. In forced continuous
operation, the inductor current is allowed to reverse at
light loads or under large transient conditions. The peak
inductor current is determined by the voltage on the ITH
pin. In this mode, the efficiency at light loads is lower than
in Burst Mode operation. However, continuous mode has
the advantages of lower output ripple and less interference
with audio circuitry.
When the MODE/PLLIN pin is connected to INTVCC, the
LTC3869 operates in PWM pulse-skipping mode at light
loads. At very light loads, the current comparator ICMP may
remain tripped for several cycles and force the external top
MOSFET to stay off for the same number of cycles (i.e.,
skipping pulses). The inductor current is not allowed to
reverse (discontinuous operation). This mode, like forced
continuous operation, exhibits low output ripple as well as
low audio noise and reduced RF interference as compared
to Burst Mode operation. It provides higher low current
efficiency than forced continuous mode, but not nearly as
high as Burst Mode operation.
Single Output Multiphase Operation
The LTC3869 can be used for single output multiphase
converters by making these connections
• Tie all of the ITH pins together.
• Tie all of the VFB pins together.
• Tie all of the TK/SS pins together.
• Tie all of the RUN pins together.
LTC3869 has excellent current matching performance
between channels to ensure that there are equal thermal
stress for both channels.
Frequency Selection and Phase-Locked Loop
(FREQ and MODE/PLLIN Pins)
The selection of switching frequency is a trade-off between
efficiency and component size. Low frequency operation
increases efficiency by reducing MOSFET switching losses,
but requires larger inductance and/or capacitance to main-
tain low output ripple voltage. The switching frequency of
the LTC3869 controller can be selected using the FREQ pin.
If the MODE/PLLIN pin is not being driven by an external
clock source, the FREQ pin can be used to program the
controller’s operating frequency from 250kHz to 780kHz.
There is a precision 10µA current flowing out of the FREQ
pin, so the user can program the controller’s switch-
ing frequency with a single resistor to SGND. A curve
is provided later in the application section showing the
relationship between the voltage on the FREQ pin and
switching frequency.
A phase-locked loop (PLL) is integrated on the LTC3869
to synchronize the internal oscillator to an external clock
source that is connected to the MODE/PLLIN pin. The
controller is operating in forced continuous mode when
it is synchronized.
operaTion
LTC3869/LTC3869-2
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The PLL loop filter network is integrated inside the
LTC3869. The phase-locked loop is capable of locking
any frequency within the range of 250kHz to 780kHz. The
frequency setting resistor should always be present to set
the controller’s initial switching frequency before locking
to the external clock.
Power Good (PGOOD Pin)
When VFB pin voltage is not within ±10% of the 0.6V
reference voltage, the PGOOD pin is pulled low. The
PGOOD pin is also pulled low when the RUN pin is below
1.2V or when the LTC3869 is in the soft-start or tracking
phase. The PGOOD pin will flag power good immediately
when both VFB pins are within the ±10% of the reference
window. However, there is an internal 20µs power bad
mask when VFB goes out the ±10% window. The PGOOD
pin is allowed to be pulled up by an external resistor to a
source of up to 6V.
Output Overvoltage Protection
An overvoltage comparator, OV, guards against transient
overshoots (>10%) as well as other more serious condi-
tions that may overvoltage the output. In such cases, the
top MOSFET is turned off and the bottom MOSFET is turned
on until the overvoltage condition is cleared.
operaTion
LTC3869/LTC3869-2
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applicaTions inForMaTion
The Typical Application on the first page is a basic LTC3869
application circuit. LTC3869 can be configured to use either
DCR (inductor resistance) sensing or low value resistor
sensing. The choice between the two current sensing
schemes is largely a design trade-off between cost, power
consumption, and accuracy. DCR sensing is becoming
popular because it saves expensive current sensing resis-
tors and is more power efficient, especially in high current
applications. However, current sensing resistors provide
the most accurate current limits for the controller. Other
external component selection is driven by the load require-
ment, and begins with the selection of RSENSE (if RSENSE is
used) and inductor value. Next, the power MOSFETs are
selected. Finally, input and output capacitors are selected.
Current Limit Programming
The ILIM pin is a tri-level logic input which sets the maxi-
mum current limit of the controller. When ILIM is either
grounded, floated or tied to INTVCC, the typical value for
the maximum current sense threshold will be 30mV, 50mV
or 75mV, respectively.
Which setting should be used? For the best current limit
accuracy, use the 75mV setting. The 30mV setting will
allow for the use of very low DCR inductors or sense
resistors, but at the expense of current limit accuracy.
The 50mV setting is a good balance between the two. For
single output dual phase applications, use the 50mV or
75mV setting for optimal current sharing.
SENSE+ and SENSE– Pins
The SENSE+ and SENSE– pins are the inputs to the current
comparators. The common mode input voltage range of
the current comparators is 0V to 12.5V. Both SENSE pins
are high impedance inputs with small base currents of less
than 1µA. When the SENSE pins ramp up from 0V to 1.4V,
the small base currents flow out of the SENSE pins. When
the SENSE pins ramp down from 12.5V to 1.1V, the small
base currents flow into the SENSE pins. The high imped-
ance inputs to the current comparators allow accurate
DCR sensing. However, care must be taken not to float
these pins during normal operation. The LTC3869GN-2
defaults to 50mV current limit value.
Filter components mutual to the sense lines should be
placed close to the LTC3869, and the sense lines should
run close together to a Kelvin connection underneath the
current sense element (shown in Figure 1). Sensing cur-
rent elsewhere can effectively add parasitic inductance
and capacitance to the current sense element, degrading
the information at the sense terminals and making the
programmed current limit unpredictable. If DCR sensing
is used (Figure 2b), sense resistor R1 should be placed
close to the switching node, to prevent noise from coupling
into sensitive small-signal nodes. The capacitor C1 should
be placed close to the IC pins.
Figure 1. Sense Lines Placement with Sense Resistor
COUT
TO SENSE FILTER,
NEXT TO THE CONTROLLER
R
SENSE
3869 F01
Low Value Resistors Current Sensing
A typical sensing circuit using a discrete resistor is shown
in Figure 2a. RSENSE is chosen based on the required
output current.
The current comparator has a maximum threshold
VSENSE(MAX) determined by the ILIM setting. The input
common mode range of the current comparator is 0V to
12.5V. The current comparator threshold sets the peak of
the inductor current, yielding a maximum average output
current IMAX equal to the peak value less half the peak-to-
peak ripple current, ∆IL. To calculate the sense resistor
value, use the equation:
RSENSE =
V
SENSE(MAX)
IMAX +∆IL
2
Because of possible PCB noise in the current sensing loop,
the AC current sensing ripple of ∆VSENSE = ∆IL • RSENSE
also needs to be checked in the design to get a good
signal-to-noise ratio. In general, for a reasonably good
PCB layout, a 10mV ∆VSENSE voltage is recommended as
a conservative number to start with, either for RSENSE or
DCR sensing applications, for duty cycles less than 40%.
LTC3869/LTC3869-2
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For previous generation current mode controllers, the
maximum sense voltage was high enough (e.g., 75mV for
the LTC1628 / LTC3728 family) that the voltage drop across
the parasitic inductance of the sense resistor represented
a relatively small error. For today’s highest current density
solutions, however, the value of the sense resistor can be
less than 1mΩ and the peak sense voltage can be as low
as 20mV. In addition, inductor ripple currents greater than
50% with operation up to 1MHz are becoming more com-
mon. Under these conditions the voltage drop across the
sense resistor’s parasitic inductance is no longer negligible.
A typical sensing circuit using a discrete resistor is shown
in Figure 2a. In previous generations of controllers, a small
RC filter placed near the IC was commonly used to reduce
the effects of capacitive and inductive noise coupled in
the sense traces on the PCB. A typical filter consists of
two series 10Ω resistors connected to a parallel 1000pF
capacitor, resulting in a time constant of 20ns.
This same RC filter, with minor modifications, can be
used to extract the resistive component of the current
sense signal in the presence of parasitic inductance.
For example, Figure 3 illustrates the voltage waveform
across a 2mΩ sense resistor with a 2010 footprint for the
1.2V/15A converter operating at 100% load. The waveform
is the superposition of a purely resistive component and a
purely inductive component. It was measured using two
scope probes and waveform math to obtain a differential
measurement. Based on additional measurements of the
inductor ripple current and the on-time and off-time of
the top switch, the value of the parasitic inductance was
determined to be 0.5nH using the equation:
ESL =
V
ESL(STEP)
∆IL
tON •tOFF
tON +tOFF
applicaTions inForMaTion
Figure 2. Tw o Different Methods of Sensing Current
(2a) Using a Resistor to Sense Current (2b) Using the Inductor DCR to Sense Current
VIN VIN
INTVCC
BOOST
TG
SW
BG
PGND
FILTER COMPONENTS
PLACED NEAR SENSE PINS
SENSE+
SENSE–
SGND
LTC3869 VOUT
3869 F02a
CF • 2RF ≤ ESL/RS
POLE-ZERO
CANCELLATION
SENSE RESISTOR
PLUS PARASITIC
INDUCTANCE
RSESL
CF
RF
RF
VIN VIN
INTVCC
BOOST
TG
SW
BG
PGND
*PLACE C1 NEAR SENSE+,
SENSE– PINS
**PLACE R1 NEXT TO
INDUCTOR
INDUCTOR
DCRL
SENSE+
SENSE–
SGND
LTC3869
VOUT
3869 F02b
R1**
R2C1*
R1||R2 × C1 = L
DCR RSENSE(EQ) = DCR R2
R1 + R2
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If the RC time constant is chosen to be close to the
parasitic inductance divided by the sense resistor (L/R),
the resulting waveform looks resistive again, as shown
in Figure 4. For applications using low maximum sense
voltages, check the sense resistor manufacturer’s data
sheet for information about parasitic inductance. In the
absence of data, measure the voltage drop directly across
the sense resistor to extract the magnitude of the ESL
step and use the equation above to determine the ESL.
However, do not over-filter. Keep the RC time constant
less than or equal to the inductor time constant to maintain
a high enough ripple voltage on VRSENSE.
The above generally applies to high density/high current
applications where IMAX >10A and low values of inductors
are used. For applications where IMAX <10A, set RF to 10Ω
and CF to 1000pF. This will provide a good starting point.
applicaTions inForMaTion
Figure 3. Voltage Waveform Measured
Directly Across the Sense Resistor
Figure 4. Voltage Waveform Measured After the
Sense Resistor Filter. CF = 1000pF, RF = 100Ω
500ns/DIV
VSENSE
20mV/DIV
3869 F03
VESL(STEP)
500ns/DIV
VSENSE
20mV/DIV
3869 F04
The filter components need to be placed close to the IC.
The positive and negative sense traces need to be routed
as a differential pair and Kelvin connected to the sense
resistor.
Inductor DCR Sensing
For applications requiring the highest possible efficiency
at high load currents, the LTC3869 is capable of sensing
the voltage drop across the inductor DCR, as shown in
Figure 2b. The DCR of the inductor represents the small
amount of DC winding resistance of the copper, which
can be less than 1mΩ for today’s low value, high current
inductors. In a high current application requiring such an
inductor, conduction loss through a sense resistor would
cost several points of efficiency compared to DCR sensing.
If the external R1|| R2 • C1 time constant is chosen to be
exactly equal to the L/DCR time constant, the voltage drop
across the external capacitor is equal to the drop across
the inductor DCR multiplied by R2/(R1 + R2). R2 scales the
voltage across the sense terminals for applications where
the DCR is greater than the target sense resistor value.
To properly dimension the external filter components, the
DCR of the inductor must be known. It can be measured
using a good RLC meter, but the DCR tolerance is not
always the same and varies with temperature; consult
the manufacturers’ data sheets for detailed information.
Using the inductor ripple current value from the Inductor
Value Calculation section, the target sense resistor value is:
RSENSE(EQUIV) =
V
SENSE(MAX)
IMAX +∆IL
2
To ensure that the application will deliver full load current
over the full operating temperature range, choose the
minimum value for the Maximum Current Sense Threshold
(VSENSE(MAX)) in the Electrical Characteristics table (23mV,
43mV, or 68mV, depending on the state of the ILIM pin).
Next, determine the DCR of the inductor. Where provided,
use the manufacturer’s maximum value, usually given at
20°C. Increase this value to account for the temperature
coefficient of resistance, which is approximately 0.4%/°C.
A conservative value for TL(MAX) is 100°C.
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applicaTions inForMaTion
To scale the maximum inductor DCR to the desired sense
resistor value, use the divider ratio:
RD=
SENSE(EQUIV)
DCR(MAX) at T
L(MAX)
C1 is usually selected to be in the range of 0.047µF to
0.47µF. This forces R1|| R2 to around 2kΩ, reducing er-
ror that might have been caused by the SENSE pins’ ±1µA
current. TL(MAX) is the maximum inductor temperature.
The equivalent resistance R1|| R2 is scaled to the room
temperature inductance and maximum DCR:
R1||R2 =
L
(DCR at 20°C) •C1
The sense resistor values are:
R1=
R1||R2
RD
; R2 =
R1•R
D
1−RD
The maximum power loss in R1 is related to duty cycle,
and will occur in continuous mode at the maximum input
voltage:
PLOSS R1=V
IN(MAX) −VOUT
( )
•VOUT
R1
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing or
sense resistors. Light load power loss can be modestly
higher with a DCR network than with a sense resistor,
due to the extra switching losses incurred through R1.
However, DCR sensing eliminates a sense resistor, reduces
conduction losses and provides higher efficiency at heavy
loads. Peak efficiency is about the same with either method.
To maintain a good signal to noise ratio for the current
sense signal, use a minimum ∆VSENSE of 10mV for duty
cycles less than 40%. For a DCR sensing application, the
actual ripple voltage will be determined by the equation:
∆VSENSE =
V
IN
−V
OUT
R1•C1
V
OUT
V
IN •fOSC
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant-
frequency architectures by preventing subharmonic oscil-
lations at high duty cycles. It is accomplished internally by
adding a compensating ramp to the inductor current signal
at duty cycles in excess of 40%. Normally, this results in
a reduction of maximum inductor peak current for duty
cycles >40%. However, the LTC3869 uses a scheme that
counteracts this compensating ramp, which allows the
maximum inductor peak current to remain unaffected
throughout all duty cycles.
Inductor Value Calculation
Given the desired input and output voltages, the inductor
value and operating frequency fOSC directly determine the
inductor’s peak-to-peak ripple current:
IRIPPLE =VOUT
VIN
VIN – VOUT
fOSC •L
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors, and output voltage
ripple. Thus, highest efficiency operation is obtained at
low frequency with a small ripple current. Achieving this,
however, requires a large inductor.
A reasonable starting point is to choose a ripple current
that is about 40% of IOUT(MAX) for a duty cycle less than
40%. Note that the largest ripple current occurs at the
highest input voltage. To guarantee that ripple current does
not exceed a specified maximum, the inductor should be
chosen according to:
L≥
V
IN
– V
OUT
fOSC •IRIPPLE
•
V
OUT
VIN
For duty cycles greater than 40%, the 10mV current
sense ripple voltage requirement is relaxed because the
slope compensation signal aids the signal-to-noise ratio
and because a lower limit is placed on the inductor value
to avoid subharmonic oscillations. To ensure stability for
LTC3869/LTC3869-2
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For more information www.linear.com/LTC3869
duty cycles up to the maximum of 95%, use the following
equation to find the minimum inductance.
LMIN >
V
OUT
fSW •ILOAD(MAX)
•1.4
where
LMIN is in units of µH
fSW is in units of MHz
Inductor Core Selection
Once the inductance value is determined, the type of in-
ductor must be selected. Core loss is independent of core
size for a fixed inductor value, but it is very dependent on
inductance selected. As inductance increases, core losses
go down. Unfortunately, increased inductance requires
more turns of wire and therefore copper losses will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Power MOSFET and Schottky Diode
(Optional) Selection
Tw o external power MOSFETs must be selected for each
controller in the LTC3869: one N-channel MOSFET for
the top (main) switch, and one N-channel MOSFET for
the bottom (synchronous) switch.
The peak-to-peak drive levels are set by the INTVCC
voltage. This voltage is typically 5V during start-up
(see EXTVCC Pin Connection). Consequently, logic-level
threshold MOSFETs must be used in most applications.
The only exception is if low input voltage is expected (VIN
< 5V); then, sub-logic level threshold MOSFETs (VGS(TH)
< 3V) should be used. Pay close attention to the BVDSS
specification for the MOSFETs as well; most of the logic
level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the
on-resistance RDS(ON), Miller capacitance CMILLER, input
voltage and maximum output current. Miller capacitance,
CMILLER, can be approximated from the gate charge curve
usually provided on the MOSFET manufacturers’ data
sheet. CMILLER is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
flat divided by the specified change in VDS. This result is
then multiplied by the ratio of the application applied VDS
to the gate charge curve specified VDS. When the IC is
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
Main Switch Duty Cycle =
V
OUT
V
IN
Synchronous Switch Duty Cycle =V
IN – VOUT
V
IN
The MOSFET power dissipations at maximum output
current are given by:
P
MAIN =
V
OUT
V
IN
IMAX
( )
21+d
( )
RDS(ON) +
V
IN
( )
2IMAX
2
RDR
( )
CMILLER
( )
•
1
V
INTVCC – VTH(MIN)
+1
VTH(MIN)
2
•fOSC
P
SYNC =V
IN – VOUT
V
IN
IMAX
( )
21+d
( )
RDS(ON)
where d is the temperature dependency of RDS(ON) and
RDR (approximately 2Ω) is the effective driver resistance
at the MOSFET’s Miller threshold voltage. VTH(MIN) is the
typical MOSFET minimum threshold voltage.
Both MOSFETs have I2R losses while the topside N-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For VIN < 20V
the high current efficiency generally improves with larger
MOSFETs, while for VIN > 20V the transition losses rapidly
increase to the point that the use of a higher RDS(ON) device
with lower CMILLER actually provides higher efficiency.
The synchronous MOSFET losses are greatest at high input
applicaTions inForMaTion
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voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
The term (1 + d) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs Temperature curve, but
d = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
The optional Schottky diodes conduct during the dead time
between the conduction of the two power MOSFETs. These
prevent the body diodes of the bottom MOSFETs from turn-
ing on, storing charge during the dead time and requiring
a reverse recovery period that could cost as much as 3%
in efficiency at high VIN. A 1A to 3A Schottky is generally
a good compromise for both regions of operation due to
the relatively small average current. Larger diodes result
in additional transition losses due to their larger junction
capacitance. A Schottky diode in parallel with the bottom
FET may also provide a modest improvement in Burst
Mode efficiency.
Soft-Start and Tracking
The LTC3869 has the ability to either soft-start by itself
with a capacitor or track the output of another channel or
external supply. When one particular channel is configured
to soft-start by itself, a capacitor should be connected to
its TK/SS pin. This channel is in the shutdown state if its
RUN pin voltage is below 1.2V. Its TK/SS pin is actively
pulled to ground in this shutdown state.
Once the RUN pin voltage is above 1.2V, the channel pow-
ers up. A soft-start current of 1.2µA then starts to charge
its soft-start capacitor. Note that soft-start or tracking is
achieved not by limiting the maximum output current of
the controller but by controlling the output ramp voltage
according to the ramp rate on the TK/SS pin. Current
foldback is disabled during this phase to ensure smooth
soft-start or tracking. The soft-start or tracking range is
defined to be the voltage range from 0V to 0.6V on the
TK/SS pin. The total soft-start time can be calculated as:
tSOFTSTART =0.6 •
C
SS
1.2µA
Regardless of the mode selected by the MODE/PLLIN pin,
the regulator will always start in pulse-skipping mode
up to TK/SS = 0.5V. Between TK/SS = 0.5V and 0.54V, it
will operate in forced continuous mode and revert to the
selected mode once TK/SS > 0.54V. The output ripple
is minimized during the 40mV forced continuous mode
window ensuring a clean PGOOD signal.
When the channel is configured to track another supply,
the feedback voltage of the other supply is duplicated by
a resistor divider and applied to the TK/SS pin. There-
fore, the voltage ramp rate on this pin is determined by
the ramp rate of the other supply’s voltage. Note that
the small soft-start capacitor charging current is always
flowing, producing a small offset error. To minimize this
error, select the tracking resistive divider value to be small
enough to make this error negligible.
In order to track down another channel or supply after
the soft-start phase expires, the LTC3869 is forced into
continuous mode of operation as soon as VFB is below the
undervoltage threshold of 0.54V regardless of the setting
on the MODE/PLLIN pin. However, the LTC3869 should
always be set in force continuous mode tracking down
when there is no load. After TK/SS drops below 0.1V, its
channel will operate in discontinuous mode.
applicaTions inForMaTion
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Output Voltage Tracking
The LTC3869 allows the user to program how its output
ramps up and down by means of the TK/SS pins. Through
these pins, the output can be set up to either coincidentally
or ratiometrically track another supply’s output, as shown
in Figure 5. In the following discussions, VOUT1 refers to
the LTC3869’s output 1 as a master channel and VOUT2
refers to the LTC3869’s output 2 as a slave channel. In
practice, though, either phase can be used as the master.
To implement the coincident tracking in Figure 5a, con-
nect an additional resistive divider to VOUT1 and connect
its midpoint to the TK/SS pin of the slave channel. The
ratio of this divider should be the same as that of the
slave channel’s feedback divider shown in Figure 6a. In
this tracking mode, VOUT1 must be set higher than VOUT2.
To implement the ratiometric tracking in Figure 6b, the
ratio of the VOUT2 divider should be exactly the same as
the master channel’s feedback divider shown in Figure 6b.
By selecting different resistors, the LTC3869 can achieve
different modes of tracking including the two in Figure 5.
So which mode should be programmed? While either
mode in Figure 5 satisfies most practical applications,
some trade-offs exist. The ratiometric mode saves a pair
of resistors, but the coincident mode offers better output
regulation.
When the master channel’s output experiences dynamic
excursion (under load transient, for example), the slave
channel output will be affected as well. For better output
regulation, use the coincident tracking mode instead of
ratiometric.
Figure 5. Tw o Different Modes of Output Voltage Tracking
Figure 6. Setup for Coincident and Ratiometric Tracking
TIME
(5a) Coincident Tracking
VOUT1
VOUT2
OUTPUT VOLTAGE
3869 F05a
VOUT1
VOUT2
TIME 3869 F08b
(5b) Ratiometric Tracking
OUTPUT VOLTAGE
R3 R1
R4 R2
R3
VOUT2
R4
(6a) Coincident Tracking Setup
TO
VFB1
PIN
TO
TK/SS2
PIN
TO
VFB2
PIN
VOUT1
R1
R2
R3
VOUT2
R4
3869 F09
(6b) Ratiometric Tracking Setup
TO
VFB1
PIN
TO
TK/SS2
PIN
TO
VFB2
PIN
VOUT1
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applicaTions inForMaTion
INTVCC Regulators and EXTVCC
The LTC3869 features a true PMOS LDO that supplies
power to INTVCC from the VIN supply. INTVCC powers the
gate drivers and much of the LTC3869’s internal circuitry.
The linear regulator regulates the voltage at the INTVCC pin
to 5V when VIN is greater than 5.5V. EXTVCC connects to
INTVCC through a P-channel MOSFET and can supply the
needed power when its voltage is higher than 4.7V. Each
of these can supply a peak current of 100mA and must
be bypassed to ground with a minimum of 4.7µF ceramic
capacitor or low ESR electrolytic capacitor. No matter
what type of bulk capacitor is used, an additional 0.1µF
ceramic capacitor placed directly adjacent to the INTVCC
and PGND pins is highly recommended. Good bypassing
is needed to supply the high transient currents required
by the MOSFET gate drivers and to prevent interaction
between the channels.
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi-
mum junction temperature rating for the LTC3869 to be
exceeded. The INTVCC current, which is dominated by the
gate charge current, may be supplied by either the 5V linear
regulator or EXTVCC. When the voltage on the EXTVCC pin
is less than 4.7V, the linear regulator is enabled. Power
dissipation for the IC in this case is highest and is equal
to VIN • IINTVCC. The gate charge current is dependent
on operating frequency as discussed in the Efficiency
Considerations section. The junction temperature can be
estimated by using the equations given in Note 3 of the
Electrical Characteristics. For example, the LTC3869 INTVCC
current is limited to less than 42mA from a 38V supply in
the UFD package and not using the EXTVCC supply:
TJ = 70°C + (42mA)(38V)(34°C/W) = 125°C
To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked while
operating in continuous conduction mode (MODE/PLLIN =
SGND) at maximum VIN. When the voltage applied to EXT-
VCC rises above 4.7V, the INTVCC linear regulator is turned
off and the EXTVCC is connected to the INTVCC. The EXTVCC
remains on as long as the voltage applied to EXTVCC remains
above 4.5V. Using the EXTVCC allows the MOSFET driver
and control power to be derived from one of the LTC3869’s
switching regulator outputs during normal operation and
from the INTVCC when the output is out of regulation
(e.g., start-up, short-circuit). If more current is required
through the EXTVCC than is specified, an external Schottky
diode can be added between the EXTVCC and INTVCC pins.
Do not apply more than 6V to the EXTVCC pin and make
sure that EXTVCC < VIN at all times.
Significant efficiency and thermal gains can be realized
by powering INTVCC from the output, since the VIN cur-
rent resulting from the driver and control currents will be
scaled by a factor of (Duty Cycle)/(Switcher Efficiency).
Tying the EXTVCC pin to a 5V supply reduces the junction
temperature in the previous example from 125°C to:
TJ = 70°C + (42mA)(5V)(34°C/W) = 77°C
However, for 3.3V and other low voltage outputs, additional
circuitry is required to derive INTVCC power from the output.
The following list summarizes the four possible connec-
tions for EXTVCC:
1. EXTVCC left open (or grounded). This will cause
INTVCC to be powered from the internal 5V regulator
resulting in an efficiency penalty of up to 10% at high
input voltages.
2. EXTVCC connected directly to VOUT. This is the
normal connection for a 5V regulator and provides
the highest efficiency.
3. EXTVCC connected to an external supply. If a 5V
external supply is available, it may be used to power
EXTVCC providing it is compatible with the MOSFET
gate drive requirements.
4. EXTVCC connected to an output-derived boost net-
work. For 3.3V and other low voltage regulators,
efficiency gains can still be realized by connecting
EXTVCC to an output-derived voltage that has been
boosted to greater than 4.7V.
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applicaTions inForMaTion
For applications where the main input power is below 5V,
tie the VIN and INTVCC pins together and tie the combined
pins to the 5V input with a 1Ω or 2.2Ω resistor as shown
in Figure 7 to minimize the voltage drop caused by the
gate charge current. This will override the INTVCC linear
regulator and will prevent INTVCC from dropping too low
due to the dropout voltage. Make sure the INTVCC voltage
is at or exceeds the RDS(ON) test voltage for the MOSFET
which is typically 4.5V for logic level devices.
UVLO comparator constantly monitors the INTVCC voltage
to ensure that an adequate gate-drive voltage is present.
It locks out the switching action when INTVCC is below
3.2V. To prevent oscillation when there is a disturbance
on the INTVCC, the UVLO comparator has 600mV of preci-
sion hysteresis.
Another way to detect an undervoltage condition is to
monitor the VIN supply. Because the RUN pins have a
precision turn-on reference of 1.2V, one can use a resistor
divider to VIN to turn on the IC when VIN is high enough.
An extra 4.5µA of current flows out of the RUN pin once
the RUN pin voltage passes 1.2V. One can program the
hysteresis of the run comparator by adjusting the values
of the resistive divider. For accurate VIN undervoltage
detection, VIN needs to be higher than 4.5V.
CIN and COUT Selection
The selection of CIN is simplified by the 2-phase architec-
ture and its impact on the worst-case RMS current drawn
through the input network (battery/fuse/capacitor). It can
be shown that the worst-case capacitor RMS current oc-
curs when only one controller is operating. The controller
with the highest (VOUT)(IOUT) product needs to be used
in the formula below to determine the maximum RMS
capacitor current requirement. Increasing the output cur-
rent drawn from the other controller will actually decrease
the input RMS ripple current from its maximum value.
The out-of-phase technique typically reduces the input
capacitor’s RMS ripple current by a factor of 30% to 70%
when compared to a single phase power supply solution.
In continuous mode, the source current of the top MOSFET
is a square wave of duty cycle (VOUT)/(VIN). To prevent
large voltage transients, a low ESR capacitor sized for the
maximum RMS current of one channel must be used. The
maximum RMS capacitor current is given by:
CIN Required IRMS ≈
I
MAX
V
IN
VOUT
( )
V
IN – VOUT
( )
1/2
This formula has a maximum at VIN = 2VOUT
, where IRMS =
IOUT/2. This simple worst-case condition is commonly used
for design because even significant deviations do not of-
fer much relief. Note that capacitor manufacturers’ ripple
current ratings are often based on only 2000 hours of life.
Figure 7. Setup for a 5V Input
Topside MOSFET Driver Supply (CB, DB)
External bootstrap capacitors CB connected to the BOOST
pins supply the gate drive voltages for the topside MOS-
FETs. Capacitor CB in the Functional Diagram is charged
though external diode DB from INTVCC when the SW pin
is low. When one of the topside MOSFETs is to be turned
on, the driver places the CB voltage across the gate source
of the desired MOSFET. This enhances the MOSFET and
turns on the topside switch. The switch node voltage,
SW, rises to VIN and the BOOST pin follows. With the
topside MOSFET on, the boost voltage is above the input
supply: VBOOST = VIN + VINTVCC. The value of the boost
capacitor CB needs to be 100 times that of the total
input capacitance of the topside MOSFET(s). The reverse
breakdown of the external Schottky diode must be greater
than VIN(MAX). Make sure the diode is a low leakage di-
ode even at hot temperature to prevent leakage current
feeding INTVCC. When adjusting the gate drive level, the
final arbiter is the total input current for the regulator. If
a change is made and the input current decreases, then
the efficiency has improved. If there is no change in input
current, then there is no change in efficiency.
Undervoltage Lockout
The LTC3869 has two functions that help protect the
controller in case of undervoltage conditions. A precision
INTVCC
LTC3869 RVIN
1Ω
CIN
3869 F07
4.7µF
5V
CINTVCC +
VIN
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applicaTions inForMaTion
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet
size or height requirements in the design. Due to the high
operating frequency of the LTC3869, ceramic capacitors
can also be used for CIN. Always consult the manufacturer
if there is any question.
The benefit of the LTC3869 2-phase operation can be
calculated by using the equation above for the higher
power controller and then calculating the loss that would
have resulted if both controller channels switched on at
the same time. The total RMS power lost is lower when
both controllers are operating due to the reduced overlap
of current pulses required through the input capacitor’s
ESR. This is why the input capacitor’s requirement cal-
culated above for the worst-case controller is adequate
for the dual controller design. Also, the input protection
fuse resistance, battery resistance, and PC board trace
resistance losses are also reduced due to the reduced
peak currents in a 2-phase system. The overall benefit of
a multiphase design will only be fully realized when the
source impedance of the power supply/battery is included
in the efficiency testing. The sources of the top MOSFETs
should be placed within 1cm of each other and share a
common CIN(s). Separating the sources and CIN may pro-
duce undesirable voltage and current resonances at VIN.
A small (0.1µF to 1µF) bypass capacitor between the chip
VIN pin and ground, placed close to the LTC3869, is also
suggested. A 2.2Ω to 10Ω resistor placed between CIN
(C1) and the VIN pin provides further isolation between
the two channels.
The selection of COUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
output ripple (∆VOUT) is approximated by:
∆VOUT ≈IRIPPLE ESR+1
8fCOUT
where f is the operating frequency, COUT is the output
capacitance and IRIPPLE is the ripple current in the induc-
tor. The output ripple is highest at maximum input voltage
since IRIPPLE increases with input voltage.
Setting Output Voltage
The LTC3869 output voltages are each set by an external
feedback resistive divider carefully placed across the out-
put, as shown in Figure 8. The regulated output voltage
is determined by:
VOUT =0.6V •1+RB
RA
To improve the frequency response, a feed-forward ca-
pacitor, CFF, may be used. Great care should be taken to
route the VFB line away from noise sources, such as the
inductor or the SW line.
Figure 8. Setting Output Voltage
Fault Conditions: Current Limit and Current Foldback
The LTC3869 includes current foldback to help limit load
current when the output is shorted to ground. If the out-
put falls below 50% of its nominal output level, then the
maximum sense voltage is progressively lowered from its
maximum programmed value to one-third of the maximum
value. Foldback current limiting is disabled during the
soft-start or tracking up. Under short-circuit conditions
with very low duty cycles, the LTC3869 will begin cycle
skipping in order to limit the short-circuit current. In this
situation the bottom MOSFET will be dissipating most of
the power but less than in normal operation. The short-
circuit ripple current is determined by the minimum on-
time tON(MIN) of the LTC3869 (≈ 90ns), the input voltage
and inductor value:
∆IL(SC) =tON(MIN) •
V
IN
L
The resulting short-circuit current is:
ISC =
1/3 V
SENSE(MAX)
RSENSE
–1
2∆IL(SC
)
1/2 LTC3869
VFB
VOUT
RBCFF
RA
3869 F08
LTC3869/LTC3869-2
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applicaTions inForMaTion
Phase-Locked Loop and Frequency Synchronization
The LTC3869 has a phase-locked loop (PLL) comprised of
an internal voltage-controlled oscillator (VCO) and a phase
detector. This allows the turn-on of the top MOSFET of
controller 1 to be locked to the rising edge of an external
clock signal applied to the MODE/PLLIN pin. The turn-on
of controller 2’s top MOSFET is thus 180 degrees out-
of-phase with the external clock. The phase detector is
an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
The output of the phase detector is a pair of complementary
current sources that charge or discharge the internal filter
network. There is a precision 10µA of current flowing out
of FREQ pin. This allows the user to use a single resistor
to SGND to set the switching frequency when no external
clock is applied to the MODE/PLLIN pin. The internal switch
between FREQ pin and the integrated PLL filter network
is ON, allowing the filter network to be pre-charged to the
same voltage potential as the FREQ pin. The relationship
between the voltage on the FREQ pin and the operating
frequency is shown in Figure 9 and specified in the Electri-
cal Characteristics table. If an external clock is detected on
the MODE/PLLIN pin, the internal switch mentioned above
will turn off and isolate the influence of FREQ pin. Note
that the LTC3869 can only be synchronized to an external
clock whose frequency is within range of the LTC3869’s
internal VCO. This is guaranteed to be between 250kHz and
780kHz. A simplified block diagram is shown in Figure 10.
If the external clock frequency is greater than the inter-
nal oscillator’s frequency, fOSC, then current is sourced
continuously from the phase detector output, pulling up
the filter network. When the external clock frequency is
less than fOSC, current is sunk continuously, pulling down
the filter network. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the filter network is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the filter capacitor holds the voltage.
Typically, the external clock (on MODE/PLLIN pin)
input high threshold is 1.6V, while the input low threshold
is 1V. It is not recommended to apply the external clock
when IC is in shutdown.
Minimum On-Time Considerations
Minimum on-time tON(MIN) is the smallest time duration
that the LTC3869 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that
tON(MIN) <
V
OUT
V
IN
(ƒ)
Figure 9. Relationship Between Oscillator
Frequency and Voltage at the FREQ Pin
Figure 10. Phase-Locked Loop Block Diagram
FREQ PIN VOLTAGE (V)
0
FREQUENCY (kHz)
0.5 1 1.5 2
3869 F09
2.5
0
100
300
400
500
900
800
700
200
600
DIGITAL
PHASE/
FREQUENCY
DETECTOR
SYNC
VCO
2.4V 5V
10µA
RSET
3869 F10
FREQ
EXTERNAL
OSCILLATOR
MODE/
PLLIN
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If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTC3869 is approximately
90ns, with reasonably good PCB layout, minimum 40%
inductor current ripple and at least 10mV – 15mV ripple
on the current sense signal. The minimum on-time can be
affected by PCB switching noise in the voltage and current
loop. As the peak sense voltage decreases the minimum
on-time gradually increases to 130ns. This is of particular
concern in forced continuous applications with low ripple
current at light loads. If the duty cycle drops below the
minimum on-time limit in this situation, a significant
amount of cycle skipping can occur with correspondingly
larger current and voltage ripple.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3869 circuits: 1) IC VIN current, 2) INTVCC
regulator current, 3) I2R losses, 4) Topside MOSFET
transition losses.
1. The VIN current is the DC supply current given in
the Electrical Characteristics table, which excludes
MOSFET driver and control currents. VIN current typi-
cally results in a small (<0.1%) loss.
2. INTVCC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
from INTVCC to ground. The resulting dQ/dt is a cur-
rent out of INTVCC that is typically much larger than the
control circuit current. In continuous mode, IGATECHG
= f(QT + QB), where QT and QB are the gate charges of
the topside and bottom side MOSFETs.
Supplying INTVCC power through EXTVCC from an
output-derived source will scale the VIN current required
for the driver and control circuits by a factor of (Duty
Cycle)/(Efficiency). For example, in a 20V to 5V applica-
tion, 10mA of INTVCC current results in approximately
2.5mA of VIN current. This reduces the mid-current loss
from 10% or more (if the driver was powered directly
from VIN) to only a few percent.
3. I2R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resistor.
In continuous mode, the average output current flows
through L and RSENSE, but is “chopped” between the
topside MOSFET and the synchronous MOSFET. If the
two MOSFETs have approximately the same RDS(ON),
then the resistance of one MOSFET can simply be
summed with the resistances of L and RSENSE to ob-
tain I2R losses. For example, if each RDS(ON) = 10mΩ,
RL = 10mΩ, RSENSE = 5mΩ, then the total resistance
is 25mΩ. This results in losses ranging from 2% to
8% as the output current increases from 3A to 15A for
a 5V output, or a 3% to 12% loss for a 3.3V output.
Efficiency varies as the inverse square of VOUT for the
same external components and output power level. The
combined effects of increasingly lower output voltages
and higher currents required by high performance digital
systems is not doubling but quadrupling the importance
of loss terms in the switching regulator system!
4. Transition losses apply only to the topside MOSFET(s),
and become significant only when operating at high
input voltages (typically 15V or greater). Transition
losses can be estimated from:
Transition Loss = (1.7) VIN2 IO(MAX) CRSS ƒ
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these “system” level losses during
the design phase. The internal battery and fuse resistance
applicaTions inForMaTion
LTC3869/LTC3869-2
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losses can be minimized by making sure that CIN has ad-
equate charge storage and very low ESR at the switching
frequency. A 25W supply will typically require a minimum
of 20µF to 40µF of capacitance having a maximum of
20mΩ to 50mΩ of ESR. The LTC3869 2-phase architecture
typically halves this input capacitance requirement over
competing solutions. Other losses including Schottky
conduction losses during dead time and inductor core
losses generally account for less than 2% total additional
loss.
Modest improvements in Burst Mode efficiency may be
realized by using a smaller inductor value, a lower switch-
ing frequency or for DCR sensing applications, making the
DCR filter’s time constant smaller than the L/DCR time
constant for the inductor. A small Schottky diode with a
current rating equal to about 20% of the maximum load
current or less may yield minor improvements, too.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, VOUT shifts by an
amount equal to ∆ILOAD (ESR), where ESR is the effective
series resistance of COUT. ∆ILOAD also begins to charge or
discharge COUT generating the feedback error signal that
forces the regulator to adapt to the current change and
return VOUT to its steady-state value. During this recovery
time VOUT can be monitored for excessive overshoot or
ringing, which would indicate a stability problem. The
availability of the ITH pin not only allows optimization of
control loop behavior but also provides a DC coupled and
AC filtered closed loop response test point. The DC step,
rise time and settling at this test point truly reflects the
closed loop response. Assuming a predominantly second
order system, phase margin and/or damping factor can be
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining the
rise time at the pin. The ITH external components shown
in the Typical Application circuit will provide an adequate
starting point for most applications.
The ITH series RC-CC filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time of 1µs to 10µs will
produce output voltage and ITH pin waveforms that will
give a sense of the overall loop stability without break-
ing the feedback loop. Placing a power MOSFET directly
across the output capacitor and driving the gate with an
appropriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This
is why it is better to look at the ITH pin signal which is in
the feedback loop and is the filtered and compensated
control loop response. The gain of the loop will be in-
creased by increasing RC and the bandwidth of the loop
will be increased by decreasing CC. If RC is increased by
the same factor that CC is decreased, the zero frequency
will be kept the same, thereby keeping the phase shift the
same in the most critical frequency range of the feedback
loop. The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance.
A second, more severe transient is caused by switching
in loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT, causing a rapid drop in VOUT. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
CLOAD to COUT is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited
to approximately 25 • CLOAD. Thus a 10µF capacitor would
require a 250µs rise time, limiting the charging current
to about 200mA.
applicaTions inForMaTion
LTC3869/LTC3869-2
28
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PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 11. Figure 12 illustrates the
current waveforms present in the various branches of
the 2-phase synchronous regulators operating in the
continuous mode. Check the following in your layout:
1. Are the top N-channel MOSFETs M1 and M3 located
within 1 cm of each other with a common drain con-
nection at CIN? Do not attempt to split the input de-
coupling for the two channels as it can cause a large
resonant loop.
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
of CINTVCC must return to the combined COUT (–) ter-
minals. The VFB and ITH traces should be as short as
possible. The path formed by the top N-channel MOS-
FET, Schottky diode and the CIN capacitor should have
short leads and PC trace lengths. The output capacitor
(–) terminals should be connected as close as possible
to the (–) terminals of the input capacitor by placing
the capacitors next to each other and away from the
Schottky loop described above.
3. Do the LTC3869 VFB pins’ resistive dividers connect to
the (+) terminals of COUT? The resistive divider must be
connected between the (+) terminal of COUT and signal
ground. The feedback resistor connections should not
be along the high current input feeds from the input
capacitor(s).
4. Are the SENSE+ and SENSE– leads routed together
with minimum PC trace spacing? The filter capacitor
between SENSE+ and SENSE– should be as close as
possible to the IC. Ensure accurate current sensing with
Kelvin connections at the sense resistor or inductor,
whichever is used for current sensing.
5. Is the INTVCC decoupling capacitor connected close
to the IC, between the INTVCC and the power ground
pins? This capacitor carries the MOSFET drivers current
peaks. An additional 1µF ceramic capacitor placed im-
mediately next to the INTVCC and PGND pins can help
improve noise performance substantially.
6. Keep the switching nodes (SW1, SW2), top gate nodes
(TG1, TG2), and boost nodes (BOOST1, BOOST2) away
from sensitive small-signal nodes, especially from the
opposite channel’s voltage and current sensing feed-
back pins. All of these nodes have very large and fast
moving signals and therefore should be kept on the
“output side” of the LTC3869 and occupy minimum
PC trace area. If DCR sensing is used, place the top
resistor (Figure 2b, R1) close to the switching node.
7. Use a modified “star ground” technique: a low imped-
ance, large copper area central grounding point on
the same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTVCC
decoupling capacitor, the bottom of the voltage feedback
resistive divider and the SGND pin of the IC.
PC Board Layout Debugging
Start with one controller at a time. It is helpful to use a
DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
to the internal oscillator and probe the actual output voltage
as well. Check for proper performance over the operating
voltage and current range expected in the application.
The frequency of operation should be maintained over
the input voltage range down to dropout and until the
output load drops below the low current operation
threshold—typically 10% of the maximum designed cur-
rent level in Burst Mode operation.
The duty cycle percentage should be maintained from
cycle to cycle in a well-designed, low noise PCB imple-
mentation. Variation in the duty cycle at a subharmonic
rate can suggest noise pickup at the current or voltage
sensing inputs or inadequate loop compensation. Over-
compensation of the loop can be used to tame a poor PC
layout if regulator bandwidth optimization is not required.
Only after each controller is checked for its individual
performance should both controllers be turned on at the
same time. A particularly difficult region of operation is
when one controller channel is nearing its current com-
parator trip point when the other channel is turning on
its top MOSFET. This occurs around 50% duty cycle on
either channel due to the phasing of the internal clocks
and may cause minor duty cycle jitter.
applicaTions inForMaTion
LTC3869/LTC3869-2
29
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Figure 11. Recommended Printed Circuit Layout Diagram
applicaTions inForMaTion
CB2
CB1
CINTVCC
+
CIN
D1
1µF
CERAMIC
M1 M2
M3 M4 D2
+
CVIN
VIN
RIN
L1
L2
COUT1
VOUT1
GND
VOUT2
3869 F11
+
COUT2
+
RSENSE
RSENSE
RPU2
PGOOD
VPULL-UP
fIN
1µF
CERAMIC
ITH1
VFB1
SENSE1+
SENSE1–
FREQ
SENSE2–
SENSE2+
VFB2
ITH2
TK/SS2
TK/SS1
PGOOD
SW1
BOOST1
BG1
VIN
PGND
EXTVCC
INTVCC
BG2
BOOST2
SW2
TG2
SGND
ILIM
MODE/PLLIN
RUN1
RUN2
LTC3869
TG1
LTC3869/LTC3869-2
30
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For more information www.linear.com/LTC3869
applicaTions inForMaTion
Figure 12. Branch Current Waveforms
R
L1
D1
L1
SW1 RSENSE1 VOUT1
COUT1
VIN
CIN
R
IN
R
L2
D2
BOLD LINES INDICATE
HIGH SWITCHING
CURRENT. KEEP LINES
TO A MINIMUM LENGTH.
L2
SW2
3869 F12
RSENSE2 VOUT2
COUT2
LTC3869/LTC3869-2
31
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Reduce VIN from its nominal level to verify operation of
the regulator in dropout. Check the operation of the un-
dervoltage lockout circuit by further lowering VIN while
monitoring the outputs to verify operation.
Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
for inductive coupling between CIN, Schottky and the top
MOSFET components to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
SGND pin of the IC.
Design Example
As a design example for a two channel high current regu-
lator, assume VIN = 12V(nominal), VIN = 20V(maximum),
VOUT1 = 1.8V, VOUT2 = 1.2V, IMAX1,2 = 15A, and f = 400kHz
(see Figure 13).
The regulated output voltages are determined by:
VOUT =0.6V •1+RB
R
A
Using 20k 1% resistors from both VFB nodes to ground,
the top feedback resistors are (to the nearest 1% standard
value) 40.2k and 20k.
The frequency is set by biasing the FREQ pin to 1V (see
Figure 9).
The inductance values are based on a 35% maximum
ripple current assumption (5.25A for each channel). The
highest value of ripple current occurs at the maximum
input voltage:
L=VOUT
ƒ•∆IL(MAX)
1−VOUT
VIN(MAX)
Channel 1 will require 0.78µH, and channel 2 will require
0.54µH. The Vishay IHLP4040DZ-01, 0.56µH inductor is
chosen for both rails. At the nominal input voltage (12V),
the ripple current will be:
∆IL(NOM) =VOUT
ƒ•L1−VOUT
V
IN(NOM)
Channel 1 will have 6.8A (46%) ripple, and channel 2 will
have 4.8A (32%) ripple. The peak inductor current will be
the maximum DC value plus one-half the ripple current,
or 18.4A for channel 1 and 17.4A for channel 2.
The minimum on-time occurs on channel 2 at the maximum
VIN, and should not be less than 90ns:
tON(MIN) =
V
OUT
V
IN(MAX) ƒ=
1.2V
20V(400kHz) =150ns
With ILIM floating, the equivalent RSENSE resistor value
can be calculated by using the minimum value for the
maximum current sense threshold (43mV).
RSENSE(EQUIV) =
V
SENSE(MIN)
ILOAD(MAX) +∆IL(NOM)
2
The equivalent required RSENSE value is 2.4mΩ for chan-
nel 1 and 2.5mΩ for channel 2. The DCR of the 0.56µH
inductor is 1.7mΩ typical and 1.8mΩ maximum for a
25°C ambient. At 100°C, the estimated maximum DCR
value is 2.3mΩ. The maximum DCR value is just slightly
under the equivalent RSENSE values. Therefore, R2 is not
required to divide down the signal.
applicaTions inForMaTion
LTC3869/LTC3869-2
32
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For more information www.linear.com/LTC3869
applicaTions inForMaTion
Figure 14. DCR Sense Efficiency vs RSENSE Efficiency
Figure 13. High Efficiency Dual 400kHz 1.8V/1.2V Step-Down Converter
LOAD CURRENT (A)
0
85
EFFICIENCY (%)
POWER LOSS (W)
90
161412108642
80
75
70
95
4
3
2
1
0
5
3869 F14
1.2V RSENSE
1.2V DCR SENSE
1.8V RSENSE
1.8V DCR SENSE
VIN = 12V
MODE = CCM
DCR SENSE APP: SEE FIGURE 16
R
SENSE
APP: SEE FIGURE 19
EFFICIENCY
POWER LOSS
D3 D4
M1
M2
0.1µF
40.2k
1%
L1
0.56µH
3.09k
1%
1nF
150pF
0.1µF 0.1µF
82µF
25V
COUT1
330µF
×2
L1, L2: VISHAY IHLP4040DZ-01, 0.56µH
M1, M3: RENESAS RJK0305DPB
M2, M4: RENESAS RJK0330DPB
20k
1%
12.1k
1%
V
OUT1
1.8V
15A
M3
M4
0.1µF L2
0.56µH
1nF
150pF COUT2
330µF
×2
20k
1%
4.99k
1%
100k
1%
V
OUT2
1.2V
15A
TG1 TG2
BOOST1 BOOST2
SW1 SW2
BG1 BG2
SGND
PGND
FREQ
SENSE1+SENSE2+
SENSE1–SENSE2–
VFB1 VFB2
ITH1 ITH2
VIN INTVCC
TK/SS1 TK/SS2
V
IN
4.5V TO
20V
3869 F13
0.1µF 0.1µF
LTC3869
3.09k
1%
4.7µF
1µF
2.2Ω
+
+
10µF
25V
×2
+
20k
1%
PINS NOT USED IN THIS CIRCUIT:
EXTVCC, ILIM, MODE/PLLIN,
PGOOD, RUN1, RUN2
LTC3869/LTC3869-2
33
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For more information www.linear.com/LTC3869
For a 2mΩ sense resistor, a short-circuit to ground will
result in a folded back current of:
ISC =1/ 3
( )
50mV
0.002Ω–1
2
90ns(20V)
0.56µH
=6.7A
A Renesas RJK0330DPB, RDS(ON) = 3.9mΩ, is chosen for
the bottom FET. The resulting power loss is:
P
SYNC =
20V – 1.8V
20V 15A
( )
2•
1+0.005
( )
•75°C – 25°C
( )
•0.0039Ω
PSYNC = 1W
CIN is chosen for an RMS current rating of at least 7.5A at
temperature assuming only channel 1 or 2 is on. COUT is
chosen with an equivalent ESR of 4.5mΩ for low output
ripple. The output ripple in continuous mode will be highest
at the maximum input voltage. The output voltage ripple
due to ESR is approximately:
VORIPPLE = RESR (∆IL) = 0.0045Ω • 6.8A = 31mVP–P
Further reductions in output voltage ripple can be made
by placing a 100µF ceramic across COUT.
applicaTions inForMaTion
For each channel, 0.1µF is selected for C1.
R1=
L
(DCRMAX at 25°C) •C1 =
0.56µH
1.8mΩ•0.1µF =3.11k
Choose R1 = 3.09k
The power loss in R1 at the maximum input voltage is:
PLOSSR1=
(V
IN(MAX)
−V
OUT
)•V
OUT
R1
The resulting power loss for R1 is 11mW for channel 1
and 7mW for channel 2.
The sum of the sense resistor and DCR is 2.5mΩ (max)
for the RSENSE application whereas the inductor DCR for
the DCR sense application is 1.8mΩ (max). As a result
of the lower conduction losses from the switch node to
VOUT, the DCR sensing application has higher efficiency.
The power dissipation on the topside MOSFET can be
easily estimated. Choosing a Renesas RJK0305DPB
MOSFET results in: RDS(ON) = 13mΩ (max), VMILLER =
2.6V, CMILLER ≅ 150pF. At maximum input voltage with
TJ (estimated) = 75°C:
P
MAIN =
1.8V
20V 15A
( )
21+(0.005)(75°C – 25°C)
[ ]
•
0.013Ω
( )
+20V
( )
215A
2
2Ω
( )
150pF
( )
•
1
5V – 2.6V +1
2.6V
400kHz
( )
=329mW +288mW
=617mW
LTC3869/LTC3869-2
34
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For more information www.linear.com/LTC3869
Typical applicaTions
Figure 15. 2.5V, 15A and 1.8V, 15A Supply with DCR Sensing, fSW = 350kHz
L1, L2: VISHAY IHLP5050CE-01, 0.68µH
COUT1, COUT3: MURATA GRM32ER60J107ME20
COUT2, COUT4: KEMET T520V337M004ATE009
RNTC1, RNTC2: MURATA NCP18WF104J03RB
3869 F15
TG1
BOOST1
PGND1
BG1
VIN
INTVCC
BG2
PGND
BOOST2
TK/SS1
ITH1
VFB1
SGND
VFB2
ITH2
TK/SS2
SENSE2–
SENSE2+
20k
0.1µF
40.2k
SENSE1–
SENSE1+
FREQ
MODE/PLLIN
SW1
PGOOD
PGOOD
SW2
TG2
63.4k
86.6k
100k
20k
2.2Ω
4.7µF
0.1µF
0.1µF
LTC3869
1nF
20k
0.1µF
100pF
10µF
×2
82µF
25V
×2
1nF
15k
0.1µF
100pF
0.1µF
CMDSH-3
M4
RJK0330DPB
M3
RJK0305DPB
M2
RJK0330DPB
M1
RJK0305DPB
CMDSH-3
0.1µF
L1
0.68µH
L2
0.68µH
24.9k
3.01k
3.01k
VOUT2
1.8V
15A
VIN
4.5V TO
20V
VOUT1
2.5V
15A
+
COUT1
100µF
6.3V
COUT2
330µF
4V
×2
+
COUT3
100µF
6.3V
COUT4
330µF
4V
×2
+
PINS NOT USED IN THIS CIRCUIT:
EXTVCC, ILIM, RUN1, RUN2
24.9k
LTC3869/LTC3869-2
35
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For more information www.linear.com/LTC3869
Typical applicaTions
Figure 16. 1.8V, 15A and 1.2V, 15A Supply, fSW = 400kHz
3869 F16
TG1
BOOST1
PGND
BG1
VIN
INTVCC
BG2
PGND1
BOOST2
TK/SS1
ITH1
VFB1
SGND
VFB2
ITH2
TK/SS2
SENSE2–
SENSE2+
20k
20k
SENSE1–
SENSE1+
FREQ
SW1
PGOOD
PGOOD
SW2
TG2
63.4k
86.6k
100k
20k
2.2Ω
4.7µF
0.1µF
0.1µF
LTC3869
1nF
18k
0.1µF
150pF
10µF
×2
82µF
25V
×2
1.5nF
15k
0.1µF
150pF
0.1µF
CMDSH-3
M4
RJK0330DPB
M3
RJK0305DPB
M2
RJK0330DPB
M1
RJK0305DPB
CMDSH-3
0.1µF
L2, 0.4µH VOUT2
1.2V
15A
VIN
4.5V TO
20V
VOUT1
1.8V
15A
+
COUT1
100µF
6.3V
COUT2
330µF
4V
×2
+
COUT3
100µF
6.3V
COUT4
330µF
4V
×2
+
L1, L2: VITEC 59PR9875
COUT1, COUT3: MURATA GRM31CR60J107ME39L
C
OUT2
, C
OUT4
: SANYO 2R5TPE330M9
100Ω
0.002Ω
L1
0.4µH
0.002Ω
0.1µF
PINS NOT USED IN THIS CIRCUIT:
EXTVCC, ILIM, MODE/PLLIN,
RUN1, RUN2
100Ω
100Ω 100Ω
LTC3869/LTC3869-2
36
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Typical applicaTions
Figure 17. High Efficiency Dual Phase 1.2V, 40A Supply, fSW = 250kHz
3869 F17
TG1
BOOST1
PGND1
BG1
VIN
INTVCC
BG2
PGND
BOOST2
TK/SS1
ITH1
VFB1
SGND
VFB2
ITH2
TK/SS2
SENSE2–
SENSE2+
SENSE1–
SENSE1+
FREQ
SW1
ILIM
PGOOD
PGOOD
SW2
TG2
86.6k
100k
20k 2.2Ω
0.1µF
4.7µF
0.1µF
0.1µF
LTC3869
10µF
×4
270µF
16V
CMDSH-3
M4
RJK0330DPB
M3
RJK0305DPB
M2
RJK0330DPB
×2
M1
RJK0305DPB
CMDSH-3
0.1µF
L1
0.44µH
L2
0.44µH
0.001Ω
1% VOUT
1.2V
40A
VIN
4.5V TO
14V
+
COUT1
100µF
6.3V
×4
COUT2
330µF
2.5V
×4
+
0.001Ω
1%
2200pF
5.9k
100pF
20k
L1, L2: PULSE PA0513.441NLT
COUT1: MURATA GRM31CR60J107ME39L
C
OUT2
: SANYO 2R5TPE330M9
100Ω
0.1µF
PINS NOT USED IN THIS CIRCUIT:
EXTVCC, MODE/PLLIN,
RUN1, RUN2
100Ω
100Ω
0.1µF
100Ω
LTC3869/LTC3869-2
37
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Figure 18. High Efficiency Dual Phase 1.2V, 40A Supply with DCR Sensing, fSW = 250kHz
Typical applicaTions
3869 F18
TG1
BOOST1
BG1
VIN
INTVCC
BG2
PGND
PGND1
BOOST2
TK/SS1
ITH1
VFB1
SGND
VFB2
ITH2
TK/SS2
SENSE2–
SENSE2+SENSE1–
SENSE1+
FREQ
MODE/PLLIN
SW1
ILIM
PGOOD
PGOOD
SW2
TG2
100k
20k
2.2Ω
0.1µF
4.7µF
0.1µF
0.1µF
LTC3869
10µF
×4
270µF
16V
CMDSH-3
M4
RJK0330DPB
×2
M3
RJK0305DPB
M2
RJK0330DPB
×2
M1
RJK0305DPB
CMDSH-3
1µF
L1
0.47µH
L2
0.47µH
VOUT
1.2V
40A
VIN
4.5V TO
14V
+
COUT1
100µF
6.3V
×4
COUT2
330µF
2.5V
×4
+
3300pF
10k
330pF
20k
L1, L2: VISHAY IHLP5050FD-01, 0.47µH
COUT1: MURATA GRM31CR60J107ME39L
C
OUT2
: SANYO 2R5TPE330M9
PINS NOT USED IN THIS CIRCUIT:
EXTVCC, RUN1, RUN2
0.1µF
0.1µF
3.92k
3.92k
LTC3869/LTC3869-2
38
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For more information www.linear.com/LTC3869
Typical applicaTions
Figure 19. Small Size, Dual Phase 0.9V, 50A Supply, fSW = 400kHz
3869 F19
TG1
BOOST1
PGND1
BG1
VIN
INTVCC
BG2
PGND
BOOST2
TK/SS1
ITH1
VFB1
SGND
VFB2
ITH2
TK/SS2
SENSE2–
SENSE2+
SENSE1–
SENSE1+
FREQ
MODE/PLLIN
SW1
ILIM
PGOOD
PGOOD
SW2
TG2
100k
100k
10k
2.2Ω
0.1µF
4.7µF
0.1µF
0.1µF
LTC3869
10µF
×4
270µF
16V
400kHz
CMDSH-3
M4
RJK0330DPB
×2
M3
RJK0305DPB
×2
M2
RJK0330DPB
×2
M1
RJK0305DPB
×2
CMDSH-3
1µF
L1
0.23µH
L2
0.23µH
0.001Ω
1% VOUT
0.9V
50A
VIN
4.5V TO
14V
+
COUT1
100µF
6.3V
×2
COUT2
330µF
2.5V
×4
+
0.001Ω
1%
2700pF
5.1k
220pF
20k
L1, L2: PULSE PA0513.441NLT
COUT1: MURATA GRM31CR60J107ME39L
COUT2: SANYO 2R5TPE330M9
PINS NOT USED IN THIS CIRCUIT:
EXTVCC, RUN1, RUN2
100Ω
0.1µF
100Ω
0.1µF
100Ω100Ω
LTC3869/LTC3869-2
39
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For more information www.linear.com/LTC3869
Figure 20. 12V, 6A and 5V, 10A Supply with DCR Sensing, fSW = 250kHz
Typical applicaTions
3869 F20
TG1
BOOST
BG1
VIN
INTVCC
EXTVCC
BG2
PGND1
PGND
BOOST2
TK/SS1
ITH1
VFB1
SGND
VFB2
ITH2
TK/SS2
SENSE2–
SENSE2+
20k
147k
SENSE1–
SENSE1+
FREQ
MODE/PLLIN
SW1
ILIM
PGOOD
PGOOD
SW2
TG2
383k
100k
20k
2.2Ω
4.7µF
0.1µF
0.1µF
LTC3869
5.6nF
10k
0.1µF
47pF
4.7µF
×6
100µF
50V
5.6nF
4.99k
0.1µF
47pF
SDM10K45
M4
BSC093N040LS
M3
BSC093N040LS
M2
BSC093N040LS
M1
BSC093N040LS
SDM10K45
0.1µF
L1
13µH
L2
3.7µH
24k
18k
8.2k
VOUT2
5V
10A
VIN
13V TO
38V
VOUT1
12V
6A
+
COUT2
39µF
16V
×2
+
COUT2
39µF
16V
×2
+
L1: WURTH 7443551131
L2: WURTH 7443551370
C
OUT1
, C
OUT2
: SANYO 16SVPC39MV
PINS NOT USED IN THIS CIRCUIT:
RUN1, RUN2
0.1µF
24k
0.1µF
LTC3869/LTC3869-2
40
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For more information www.linear.com/LTC3869
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
4.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.05
2827
1
2
BOTTOM VIEW—EXPOSED PAD
2.64 ±0.10
(4-SIDES)
0.75 ±0.05 R = 0.115
TYP
0.20 ±0.05
0.40 BSC
0.200 REF
0.00 – 0.05
(UF28) QFN 0106 REVA
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
0.20 ±0.05
0.40 BSC
2.64 ±0.05
(4 SIDES)
3.10 ±0.05
4.50 ±0.05
PACKAGE
OUTLINE
PIN 1 NOTCH
R = 0.20 TYP
OR 0.35 ×
45°
CHAMFER
R = 0.05
TYP
UF Package
28-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1721 Rev A)
LTC3869/LTC3869-2
41
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For more information www.linear.com/LTC3869
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
4.00 ±0.10
(2 SIDES)
2.50 REF
5.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.10
27 28
1
2
BOTTOM VIEW—EXPOSED PAD
3.50 REF
0.75 ±0.05 R = 0.115
TYP
R = 0.05
TYP
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
0.25 ±0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UFD28) QFN 0506 REV B
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
0.25 ±0.05
0.50 BSC
2.50 REF
3.50 REF
4.10 ±0.05
5.50 ±0.05
2.65 ±0.05
3.10 ±0.05
4.50 ±0.05
PACKAGE OUTLINE
2.65 ±0.10
3.65 ±0.10
3.65 ±0.05
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev B)
LTC3869/LTC3869-2
42
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For more information www.linear.com/LTC3869
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
.386 – .393*
(9.804 – 9.982)
GN28 REV B 0212
1 2 345678 9 10 11 12
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
202122232425262728 19 18 17
13 14
1615
.016 – .050
(0.406 – 1.270)
.015 ±.004
(0.38 ±0.10) × 45°
0° – 8° TYP
.0075 – .0098
(0.19 – 0.25)
.0532 – .0688
(1.35 – 1.75)
.008 – .012
(0.203 – 0.305)
TYP
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
BSC
.033
(0.838)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 – .165
.0250 BSC.0165 ±.0015
.045 ±.005
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
GN Package
28-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641 Rev B)
LTC3869/LTC3869-2
43
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For more information www.linear.com/LTC3869
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER
A 04/13 Revised schematics
Updated package drawings
35-38
39-40
B 09/15 Added UF package 1, 2, 4, 8, 9,
10, 40
LTC3869/LTC3869-2
44
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For more information www.linear.com/LTC3869
LINEAR TECHNOLOGY CORPORATION 2011
LT 0915 REV B • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC3869
relaTeD parTs
Typical applicaTion
3.3V/5A, 5V/5A Converter Using Sense Resistors
PART NUMBER DESCRIPTION COMMENTS
LT M
®
4630/
LTM4630A
Dual 18A or Single 36A DC/DC μModule
®
Regulator ±1.5% Max Total VOUT Error, 4.5V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤
1.8V, 16mm × 16mm BGA and LGA Packages
LTC3887/
LTC3887-1
Dual Output Multiphase Step-Down DC/DC Controller with Digital
Power System Management, 70ms Start-Up
VIN Up to 24V, 0.5V ≤ VOUT0,1 ≤ 5.5V, 70mS Start-Up, Analog
Control Loop, I2C/PMBus Interface with EEPROM and 16-Bit ADC
LTC3774 Dual Multiphase, Current Mode Synchronous Step Down DC/DC
Controller for Sub-mΩ DCR Sensing
Operates with DrMOS Power Blocks or External Drivers/MOSFETs,
4.5V ≤ VIN ≤ 38V, 0.6V ≤ VOUT ≤ 3.5V
LTC3855 Dual, Multiphase, Synchronous Step-Down DC/DC Controller with
Differential Output Sensing and DCR Temperature Compensation
PLL Fixed Frequency 250kHz to 770kHz, 4.5V ≤ VIN ≤ 38V,
0.8V ≤ VOUT ≤ 12V
LTC3838/
LTC3838-1/
LTC3838-2
Dual, Fast, Accurate Step-Down Controlled On-Time DC/DC
Controller with Differential Output Sensing
Synchronizable Fixed Frequency 200kHz to 2MHz, 4.5V ≤ VIN
≤ 38V, 0.8V ≤ VOUT ≤ 5.5V
LTC3861/
LTC3861-1
Dual, Multiphase, Synchronous Step-Down Voltage Mode DC/DC
Controller with Diff Amp and Accurate Current Sharing
Operates with Power Blocks, DrMOS Devices or External Drivers/
MOSFETs, 3V ≤ VIN ≤ 24V
LTC3856 Single Output, Multiphase Synchronous Step-Down DC/DC
Controller with Differential Output Sensing and DCR Temperature
Compensation
Phase-Lockable Fixed 250kHz to 770kHz Frequency, 4.5V ≤ VIN ≤
38V, 0.8V ≤ VOUT ≤ 5V
0.1µF
90.9k
1%
L2
2.2µH
1000pF
1000pF 1000pF
22µF
50V
20k
1% 10k
1%
V
OUT1
3.3V
5A
0.1µF
147k
1%
L2
3.3µH
1000pF
COUT2
150µF
20k
1%
15k
1%
122k
1%
V
OUT2
5V
5A
TG1 TG2
BOOST1 BOOST2
SW1 SW2
BG1 BG2
SGND
PGND
FREQ
SENSE1+SENSE2+
EXTVCC
SENSE1–SENSE2–
VFB1
VFB2
ITH1
ITH2
VIN INTVCC
TK/SS1 TK/SS2
V
IN
7V TO
24V
3869 TA02
0.1µF
100pF 0.1µF
LTC3869
ILIM
4.7µF
+
COUT1
220µF
+
10pF
15pF
100pF
10Ω
10Ω
10Ω
10Ω
2.2Ω
1µF
D4
D3
L1: TDK RLF 7030T-2R2M5R4
L2: TDK ULF10045T-3R3N6R9
COUT1: SANYO 4TPE220MF
COUT2: SANYO 6TPE150MI
8mΩ 8mΩ
M1 M2
Si4816BDYSi4816BDY
PINS NOT USED IN THIS CIRCUIT:
MODE/PLLIN, PGOOD, RUN1, RUN2