Single-Channel, 128-/64-/32-Position, I2C, ±8%
Resistor Tolerance, Nonvolatile Digital Potentiometer
Data Sheet AD5110/AD5112/AD5114
Rev. A
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FEATURES
Nominal resistor tolerance error: ±8% maximum
Wiper current: ±6 mA
Rheostat mode temperature coefficient: 35 ppm/°C
Low power consumption: 2.5 mA max @ 2.7 V and 125°C
Wide bandwidth: 4 MHz (5 kΩ option)
Power-on EEPROM refresh time < 50 μs
50-year typical data retention at 125°C
1 million write cycles
2.3 V to 5.5 V analog supply operation
1.8 V to 5.5 V logic supply operation
Wide operating temperature: −40°C to +125°C
Thin, 2 mm × 2 mm × 0.55 mm 8-lead LFCSP package
APPLICATIONS
Mechanical potentiometer replacement
Portable electronics level adjustment
Audio volume control
Low resolution DAC
LCD panel brightness and contrast control
Programmable voltage to current conversion
Programmable filters, delays, time constants
Feedback resistor programmable power supply
Sensor calibration
FUNCTIONAL BLOCK DIAGRAM
POWER-ON
RESET
V
LOGIC
V
DD
DATA
DATA
SD
A
A
W
B
SCL
EEPROM
AD5110/AD5112/AD5114
RDAC
REGISTER
GND
I
2
C
SERIAL
INTERFACE
09582-001
Figure 1.
Table 1. ±8% Resistance Tolerance Family
Model Resistance (kΩ) Position Interface
AD5110 10, 80 128 I2C
AD5111 10, 80 128 Up/down
AD5112 5, 10, 80 64 I2C
AD5113 5, 10, 80 64 Up/down
AD5116 5, 10, 80 64 Push-button
AD5114 10, 80 32 I2C
AD5115 10, 80 32 Up/down
GENERAL DESCRIPTION
The AD5110/AD5112/AD5114 provide a nonvolatile solution
for 128-/64-/32-position adjustment applications, offering
guaranteed low resistor tolerance errors of ±8% and up to
±6 mA current density in the A, B, and W pins. The low resistor
tolerance, low nominal temperature coefficient and high
bandwidth simplify open-loop applications, as well as tolerance
matching applications.
The new low wiper resistance feature minimizes the wiper
resistance in the extremes of the resistor array to only 45 Ω,
typical.
The wiper settings are controllable through an I2C-compatible
digital interface that is also used to readback the wiper register
and EEPROM content. Resistor tolerance is stored within
EEPROM, providing an end-to-end tolerance accuracy of 0.1%.
The AD5110/AD5112/AD5114 are available in a 2 mm × 2 mm
LFCSP package. The parts are guaranteed to operate over the
extended industrial temperature range of −40°C to +125°C.
AD5110/AD5112/AD5114 Data Sheet
Rev. A | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics—AD5110 .......................................... 3
Electrical Characteristics—AD5112 .......................................... 5
Electrical Characteristics—AD5114 .......................................... 7
Interface Timing Specifications .................................................. 9
Shift Register and Timing Diagram ......................................... 10
Absolute Maximum Ratings .......................................................... 11
Thermal Resistance .................................................................... 11
ESD Caution ................................................................................ 11
Pin Configuration and Function Descriptions ........................... 12
Typical Performance Characteristics ........................................... 13
Test Circuits ..................................................................................... 18
Theory of Operation ...................................................................... 19
RDAC Register and EEPROM .................................................. 19
I2C Serial Data Interface ............................................................ 19
Input Shift Register .................................................................... 20
Write Operation.......................................................................... 21
EEPROM Write Acknowlegde Polling .................................... 23
Read Operation........................................................................... 23
Reset ............................................................................................. 23
Shutdown Mode ......................................................................... 23
RDAC Architecture .................................................................... 24
Programming the Variable Resistor ......................................... 24
Programming the Potentiometer Divider ............................... 25
Terminal Voltage Operating Range ......................................... 26
Power-Up Sequence ................................................................... 26
Layout and Power Supply Biasing ............................................ 26
Outline Dimensions ....................................................................... 27
Ordering Guide .......................................................................... 27
REVISION HISTORY
4/12—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Changes to Positive Supply Current, Table 2 ................................ 4
Changes to Positive Supply Current, Table 3 ................................ 6
Changes to Positive Supply Current, Table 4 ................................ 8
Updated Outline Dimensions ....................................................... 27
10/11—Revision 0: Initial Version
Data Sheet AD5110/AD5112/AD5114
Rev. | Page 3 of 28
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—AD5110
10 kΩ and 80 kΩ versions: VDD = 2.3 V to 5.5 V, VLOGIC = 1.8 V to VDD, VA = VDD, VB = 0 V, −40°C < TA < +125°C, unless otherwise noted.
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resolution N 7 Bits
Resistor Integral Nonlinearity2 R-INL RAB = 10 kΩ, VDD = 2.3 V to 2.7 V −2.5 ±0.5 +2.5 LSB
R
AB = 10 kΩ, VDD = 2.7 V to 5.5 V −1 ±0.25 +1 LSB
R
AB = 80 kΩ −0.5 ±0.1 +0.5 LSB
Resistor Differential Nonlinearity2 R-DNL −1 ±0.25 +1 LSB
Nominal Resistor Tolerance ΔRAB/RAB −8 +8 %
Resistance Temperature Coefficient3 (ΔRAB/RAB)/ΔT × 106 Code = full scale 35 ppm/°C
Wiper Resistance RW Code = zero scale 70 140 Ω
R
BS Code = bottom scale 45 80 Ω
R
TS Code = top scale 70 140 Ω
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE
Integral Nonlinearity4 INL −0.5 ±0.15 +0.5 LSB
Differential Nonlinearity4 DNL −0.5 ±0.15 +0.5 LSB
Full-Scale Error VWFSE R
AB = 10 kΩ −2.5 LSB
R
AB = 80 kΩ −1.5 LSB
Zero-Scale Error VWZSE R
AB = 10 kΩ 1.5 LSB
R
AB = 80 kΩ 0.5 LSB
Voltage Divider Temperature Coefficient3 (ΔVW/VW)/ΔT × 106 Code = half scale ±10 ppm/°C
RESISTOR TERMINALS
Maximum Continuous IA, IB, and IW
Current3
R
AB = 10 kΩ −6 +6 mA
R
AB = 80 kΩ −1.5 +1.5 mA
Terminal Voltage Range5 GND VDD V
Capacitance A, Capacitance B3 CA, CB f = 1 MHz, measured to GND,
code = half scale,
VW = VA = 2.5 V or VW = VB = 2.5 V
20 pF
Capacitance W3 CW f = 1 MHz, measured to GND,
code = half scale, VA = VB = 2.5 V
35 pF
Common-Mode Leakage Current3 V
A = VW = VB −500 ±15 +500 nA
DIGITAL INPUTS
Input Logic3
High VINH V
LOGIC = 1.8 V to 2.3 V 0.8 × VLOGIC V
V
LOGIC = 2.3 V to 5.5 V 0.7 × VLOGIC V
Low VINL V
LOGIC = 1.8 V to 2.3 V 0.2 × VLOGIC V
V
LOGIC = 2.3 V to 5.5 V 0.3 × VLOGIC V
Input Hysteresis3 VHYST 0.1 × VLOGIC V
Input Current3 IN ±1 μA
Input Capacitance3 CIN 5 pF
DIGITAL OUTPUT (SDA)
Output Low Voltage3 VOL I
SINK = 3 mA 0.2 V
I
SINK = 6 mA 0.4 V
Three-State Leakage Current −1 +1 μA
Three-State Output Capacitance3 2 pF
A
AD5110/AD5112/AD5114 Data Sheet
Rev. A | Page 4 of 28
Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit
POWER SUPPLIES
Single-Supply Power Range 2.3 5.5 V
Logic Supply Range 1.8 VDD V
Positive Supply Current IDD V
DD = 5 V 0.75 3.5 mA
V
DD = 2.7 V 2.5 mA
V
DD = 2.3 V 2.4 mA
EEMEM Store Current3, 6 IDD_NVM_STORE 2 mA
EEMEM Read Current3, 7 IDD_NVM_READ 320 μA
Logic Supply Current ILOGIC V
IH = VLOGIC or VIL = GND 30 nA
Power Dissipation8 P
DISS V
IH = VLOGIC or VIL = GND 5 μW
Power Supply Rejection3 PSR ∆VDD/∆VSS = 5 V ± 10%
R
AB = 10 kΩ −50 dB
R
AB = 80 kΩ −64 dB
DYNAMIC CHARACTERISTICS3, 9
Bandwidth BW Code = half scale, −3 dB
R
AB = 10 kΩ 2 MHz
R
AB = 80 kΩ 200 kHz
Total Harmonic Distortion THD VA = VDD/2 +1 V rms, VB = VDD/2,
f = 1 kHz, code = half scale
R
AB = 10 kΩ −80 dB
R
AB = 80 kΩ −85 dB
VW Settling Time ts V
A = 5 V, VB = 0 V,
±0.5 LSB error band
R
AB = 10 kΩ 3 μs
R
AB = 80 kΩ 12 μs
Resistor Noise Density eN_WB Code = half scale, TA = 25°C,
f = 100 kHz
R
AB = 10 kΩ 9 nV/√Hz
R
AB = 80 kΩ 20 nV/√Hz
FLASH/EE MEMORY RELIABILITY3
Endurance10 T
A = 25°C 1 MCycles
100 kCycles
Data Retention11 50
Years
1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to 0.75 × VDD/RAB.
3 Guaranteed by design and characterization, not subject to production test.
4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
6 Different from operating current; supply current for NVM program lasts approximately 30 ms.
7 Different from operating current; supply current for NVM read lasts approximately 20 μs.
8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC).
9 All dynamic characteristics use VDD = 5.5 V, and VLOGIC = 5 V.
10 Endurance is qualified at 100,000 cycles per JEDEC Standard 22, Method A117 and measured at 150°C.
11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV
derates with junction temperature in the Flash/EE memory.
Data Sheet AD5110/AD5112/AD5114
Rev. | Page 5 of 28
ELECTRICAL CHARACTERISTICS—AD5112
5 kΩ, 10 kΩ, and 80 kΩ versions: VDD = 2.3 V to 5.5 V, VLOGIC = 1.8 V to VDD, VA = VDD, VB = 0 V, −40°C < TA < +125°C, unless otherwise noted.
Table 3.
Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resolution N 6 Bits
Resistor Integral Nonlinearity2 R-INL RAB = 5 kΩ, VDD = 2.3 V to 2.7 V −2.5 ±0.5 +2.5 LSB
R
AB = 5 kΩ, VDD = 2.7 V to 5.5 V −1 ±0.25 +1 LSB
R
AB = 10 kΩ −1 ±0.25 +1 LSB
R
AB = 80 kΩ −0.25 ±0.1 +0.25 LSB
Resistor Differential Nonlinearity2 R-DNL +1 ±0.25 +1 LSB
Nominal Resistor Tolerance ΔRAB/RAB −8 +8 %
Resistance Temperature Coefficient3 (ΔRAB/RAB)/ΔT × 106 Code = full scale 35 ppm/°C
Wiper Resistance RW Code = zero scale 70 140 Ω
R
BS Code = bottom scale 45 80 Ω
R
TS Code = top scale 70 140 Ω
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE
Integral Nonlinearity4 INL −0.5 ±0.15 +0.5 LSB
Differential Nonlinearity4 DNL −0.5 ±0.15 +0.5 LSB
Full-Scale Error VWFSE R
AB = 5 kΩ −2.5 LSB
R
AB =10 kΩ −1.5 LSB
R
AB = 80 kΩ −1 LSB
Zero-Scale Error VWZSE R
AB = 5 kΩ 1.5 LSB
R
AB =10 kΩ 1 LSB
R
AB = 80 kΩ 0.25 LSB
Voltage Divider Temperature Coefficient3 (ΔVW/VW)/ΔT × 106 Code = half scale ±10 ppm/°C
RESISTOR TERMINALS
Maximum Continuous IA, IB, and IW
Current3
R
AB = 5 kΩ, 10 kΩ −6 +6 mA
R
AB = 80 kΩ −1.5 +1.5 mA
Terminal Voltage Range5 GND VDD V
Capacitance A, Capacitance B3 CA, CB f = 1 MHz, measured to GND,
code = half scale, VW = VA =
2.5 V or VW = VB = 2.5 V
20 pF
Capacitance W3 CW f = 1 MHz, measured to GND,
code = half scale,
VA = VB = 2.5 V
35 pF
Common-Mode Leakage Current3 V
A = VW = VB −500 ±15 +500 nA
DIGITAL INPUTS
Input Logic3
High VINH V
LOGIC = 1.8 V to 2.3 V 0.8 × VLOGIC V
V
LOGIC = 2.3 V to 5.5 V 0.7 × VLOGIC V
Low VINL V
LOGIC = 1.8 V to 2.3 V 0.2 × VLOGIC V
V
LOGIC = 2.3 V to 5.5 V 0.3 × VLOGIC V
Input Hysteresis3 VHYST 0.1 × VLOGIC V
Input Current3 IN ±1 μA
Input Capacitance3 CIN 5 pF
DIGITAL OUTPUT (SDA)
Output Low Voltage3 VOL I
SINK = 3 mA 0.2 V
I
SINK = 6 mA 0.4 V
Three-State Leakage Current −1 +1 μA
Three-State Output Capacitance3 2 pF
A
AD5110/AD5112/AD5114 Data Sheet
Rev. A | Page 6 of 28
Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit
POWER SUPPLIES
Single-Supply Power Range 2.3 5.5 V
Logic Supply Range 1.8 VDD V
Positive Supply Current IDD V
DD = 5 V 0.75 3.5 mA
V
DD = 2.7 V 2.5 mA
V
DD = 2.3 V 2.4 mA
EEMEM Store Current3, 6 IDD_NVM_STORE 2 mA
EEMEM Read Current3, 7 IDD_NVM_READ 320 μA
Logic Supply Current ILOGIC V
IH = VLOGIC or VIL = GND 30 nA
Power Dissipation8 P
DISS V
IH = VLOGIC or VIL = GND 5 μW
Power Supply Rejection3 PSR ∆VDD/∆VSS = 5 V ± 10%
R
AB = 5 kΩ −43 dB
R
AB =10 kΩ −50 dB
R
AB = 80 kΩ −64 dB
DYNAMIC CHARACTERISTICS3, 9
Bandwidth BW Code = half scale − 3 dB
R
AB = 5 kΩ 4 MHz
R
AB = 10 kΩ 2 MHz
R
AB = 80 kΩ 200 kHz
Total Harmonic Distortion THD VA = VDD/2 + 1 V rms,
VB = VDD/2, f = 1 kHz,
code = half scale
R
AB = 5 kΩ −75 dB
R
AB = 10 kΩ −80 dB
R
AB = 80 kΩ −85 dB
VW Settling Time ts V
A = 5 V, VB = 0 V,
±0.5 LSB error band
μs
R
AB = 5 kΩ 2.5 μs
R
AB = 10 kΩ 3 μs
R
AB = 80 kΩ 10 μs
Resistor Noise Density eN_WB Code = half scale, TA = 25°C,
f = 100 kHz
R
AB = 5 kΩ 7 nV/√Hz
R
AB = 10 kΩ 9 nV/√Hz
R
AB = 80 kΩ 20 nV/√Hz
FLASH/EE MEMORY RELIABILITY3
Endurance10 T
A = 25°C 1 MCycles
100 kCycles
Data Retention11 50 Years
1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to 0.75 × VDD/RAB.
3 Guaranteed by design and characterization, not subject to production test.
4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
6 Different from operating current; supply current for NVM program lasts approximately 30 ms.
7 Different from operating current; supply current for NVM read lasts approximately 20 μs.
8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC).
9 All dynamic characteristics use VDD = 5.5 V, and VLOGIC = 5 V.
10 Endurance is qualified at 100,000 cycles per JEDEC Standard 22, Method A117 and measured at 150°C.
11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV
derates with junction temperature in the Flash/EE memory.
Data Sheet AD5110/AD5112/AD5114
Rev. | Page 7 of 28
ELECTRICAL CHARACTERISTICS—AD5114
10 kΩ and 80 kΩ versions: VDD = 2.3 V to 5.5 V, VLOGIC = 1.8 V to VDD, VA = VDD, VB = 0 V, −40°C < TA < +125°C, unless otherwise noted.
Table 4.
Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resolution N 5 Bits
Resistor Integral Nonlinearity2 R-INL −0.5 +0.5 LSB
Resistor Differential Nonlinearity2 R-DNL −0.25 +0.25 LSB
Nominal Resistor Tolerance ΔRAB/RAB −8 +8 %
Resistance Temperature Coefficient3 (ΔRAB/RAB)/ΔT × 106 Code = full scale 35 ppm/°C
Wiper Resistance RW Code = zero scale 70 140 Ω
R
BS Code = bottom scale 45 80 Ω
R
TS Code = top scale 70 140 Ω
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE
Integral Nonlinearity4 INL −0.25 +0.25 LSB
Differential Nonlinearity4 DNL −0.25 +0.25 LSB
Full-Scale Error VWFSE R
AB = 10 kΩ −1 LSB
R
AB = 80 kΩ −0.5 LSB
Zero-Scale Error VWZSE R
AB = 10 kΩ 1 LSB
R
AB = 80 kΩ 0.25 LSB
Voltage Divider Temperature Coefficient3 (ΔVW/VW)/ΔT × 106 Code = half scale ±10 ppm/°C
RESISTOR TERMINALS
Maximum Continuous IA, IB, and IW
Current3
R
AB = 10 kΩ −6 +6 mA
R
AB = 80 kΩ −1.5 +1.5 mA
Terminal Voltage Range5 GND VDD V
Capacitance A, Capacitance B3 CA, CB f = 1 MHz, measured to GND,
code = half scale, VW = VA =
2.5 V or VW = VB = 2.5 V
20 pF
Capacitance W3 CW f = 1 MHz, measured to
GND, code = half scale, VA =
VB = 2.5 V
35 pF
Common-Mode Leakage Current3 V
A = VW = VB −500 ±15 +500 nA
DIGITAL INPUTS
Input Logic3
High VINH V
LOGIC = 1.8 V to 2.3 V 0.8 × VLOGIC V
V
LOGIC = 2.3 V to 5.5 V 0.7 × VLOGIC V
Low VINL V
LOGIC = 1.8 V to 2.3 V 0.2 × VLOGIC V
V
LOGIC = 2.3 V to 5.5 V 0.3 × VLOGIC V
Input Hysteresis3 VHYST 0.1 × VLOGIC V
Input Current3 IN ±1 μA
Input Capacitance3 CIN 5 pF
DIGITAL OUTPUT (SDA)
Output Low Voltage3 VOL I
SINK = 3 mA 0.2 V
I
SINK = 6 mA 0.4 V
Three-State Leakage Current −1 +1 μA
Three-State Output Capacitance3 2 pF
A
AD5110/AD5112/AD5114 Data Sheet
Rev. A | Page 8 of 28
Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit
POWER SUPPLIES
Single-Supply Power Range 2.3 5.5 V
Logic Supply Range 1.8 VDD V
Positive Supply Current IDD V
DD = 5 V 0.75 3.5 mA
V
DD = 2.7 V 2.5 mA
V
DD = 2.3 V 2.4 mA
EEMEM Store Current3, 6 IDD_NVM_STORE 2 mA
EEMEM Read Current3, 7 IDD_NVM_READ 320 μA
Logic Supply Current ILOGIC V
IH = VLOGIC or VIL = GND 30 nA
Power Dissipation8 P
DISS V
IH = VLOGIC or VIL = GND 5 μW
Power Supply Rejection3 PSR ∆VDD/∆VSS = 5 V ± 10%
R
AB = 10 kΩ −50 dB
R
AB = 80 kΩ −64 dB
DYNAMIC CHARACTERISTICS3, 9
Bandwidth BW Code = half scale, −3 dB
R
AB = 10 kΩ 2 MHz
R
AB = 80 kΩ 200 kHz
Total Harmonic Distortion THD VA = VDD/2 + 1 V rms,
VB = VDD/2, f = 1 kHz,
code = half scale
R
AB = 10 kΩ −80 dB
R
AB = 80 kΩ −85 dB
VW Settling Time ts V
A = 5 V, VB = 0 V, ±0.5 LSB
error band
R
AB = 10 kΩ 2.7 μs
R
AB = 80 kΩ 9.5 μs
Resistor Noise Density eN_WB Code = half scale, TA = 25°C,
f = 100 kHz
R
AB = 10 kΩ 9 nV/√Hz
R
AB = 80 kΩ 20 nV/√Hz
FLASH/EE MEMORY RELIABILITY3
Endurance10 T
A = 25°C 1 MCycles
100 kCycles
Data Retention11 50
Years
1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to 0.75 × VDD/RAB.
3 Guaranteed by design and characterization, not subject to production test.
4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
6 Different from operating current; supply current for NVM program lasts approximately 30 ms.
7 Different from operating current; supply current for NVM read lasts approximately 20 μs.
8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC).
9 All dynamic characteristics use VDD = 5.5 V, and VLOGIC = 5 V.
10 Endurance is qualified at 100,000 cycles per JEDEC Standard 22, Method A117 and measured at 150°C.
11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV
derates with junction temperature in the Flash/EE memory.
Data Sheet AD5110/AD5112/AD5114
Rev. | Page 9 of 28
INTERFACE TIMING SPECIFICATIONS
VLOGIC = 1.8 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 5.
Parameter1
Test Conditions/
Comments Min Typ Max Unit Description
fSCL2 Standard mode 100 kHz Serial clock frequency
Fast mode 400 kHz
t1 Standard mode 4.0 µs tHIGH, SCL high time
Fast mode
0.6
µs
t2 Standard mode 4.7 µs tLOW, SCL low time
Fast mode 1.3 µs
t3 Standard mode 250 ns tSU;DAT, data setup time
Fast mode 100 ns
t4 Standard mode 0 3.45 µs tHD;DAT, data hold time
Fast mode 0 0.9 µs
t5 Standard mode 4.7 µs tSU;STA, setup time for a repeated start condition
Fast mode 0.6 µs
t6 Standard mode 4 µs tHD;STA, hold time (repeated) start condition
Fast mode 0.6 µs
t7 Standard mode 4.7 µs tBUF, bus free time between a stop and a start
condition
Fast mode 1.3 µs
t8 Standard mode 4 µs tSU;STO, setup time for stop condition
Fast mode 0.6 µs
t9 Standard mode 1000 ns tRDA, rise time of SDA signal
Fast mode
20 + 0.1 C
L
300
ns
t10 Standard mode 300 ns tFDA, fall time of SDA signal
Fast mode 20 + 0.1 CL 300 ns
t11 Standard mode 1000 ns tRCL, rise time of SCL signal
Fast mode 20 + 0.1 CL 300 ns
t11A Standard mode 1000 ns tRCL1, rise time of SCL signal after a repeated start
condition and after an acknowledge bit.
Fast mode 20 + 0.1 CL 300 ns
t12 Standard mode 300 ns tFCL, fall time of SCL signal
Fast mode 20 + 0.1 CL 300 ns
tSP3 Fast mode 0 50 ns Pulse width of suppressed spike
tEEPROM_PROGRAM4 15 50 ms Memory program time
tPOWER_UP5 50 µs Power-on EEPROM restore time
t
RESET
25
µs
Reset EEPROM restore time
1 Maximum bus capacitance is limited to 400 pF.
2 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior
of the part.
3 Input filtering on the SCL and SDA inputs suppress noise spikes that are less than 50 ns for fast mode.
4 EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at a lower temperature and higher write cycles.
5 Maximum time after VDD is equal to 2.3 V.
A
AD5110/AD5112/AD5114 Data Sheet
Rev. | Page 10 of 28
SHIFT REGISTER AND TIMING DIAGRAM
DATA BIT S
DB7 (MSB) DB0 (LSB)
D7 D6 D5 D4 D3 D2 D1 D0
CONTRO L BI TS
C0C1
C200000
09582-002
Figure 2. Input Register Content
t
12
t
11
t
2
t
6
SCL
t
1
t
6
t
5
t
4
t
3
t
10
t
9
t
8
t
7
SDA
PS S P
09582-003
Figure 3. 2-Wire Serial Interface Timing Diagram
A
Data Sheet AD5110/AD5112/AD5114
Rev. | Page 11 of 28
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter
Rating
VDD to GND –0.3 V to +7.0 V
VLOGIC to GND –0.3 V to +7.0 V
VA, VW, VB to GND GND − 0.3 V to VDD + 0.3 V
IA, IW, IB
Pulsed1
Frequency > 10 kHz
R
AW
= 5 kΩ and 10 kΩ
±6 mA/d2
RAW = 80 kΩ ±1.5 mA/d2
Frequency ≤ 10 kHz
RAW = 5 kΩ and 10 kΩ ±6 mA/√d2
RAW = 80 kΩ ±1.5 mA/√d2
Continuous
RAW = 5 kΩ and 10 kΩ ±6 mA
R
AW
= 80 kΩ
±1.5 mA
Digital Inputs SDA and SCL −0.3 V to +7 V or VLOGIC + 0.3
V
(whichever is less)
Operating Temperature Range3 −40°C to +125°C
Maximum Junction Temperature (TJ Max) 150°C
Storage Temperature Range −65°C to +150°C
Reflow Soldering
Peak Temperature 260°C
Time at Peak Temperature 20 sec to 40 sec
Package Power Dissipation (TJ max − TA)/θJA
1 Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2 Pulse duty factor.
3 Includes programming of EEPROM memory.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is defined by JEDEC specification JESD-51, and the value is
dependent on the test board and test environment.
Table 7. Thermal Resistance
Package Type θJA θJC Unit
8-Lead LFCSP 901 25 °C/W
1 JEDEC 2S2P test board, still air (0 m/sec air flow).
ESD CAUTION
A
AD5110/AD5112/AD5114 Data Sheet
Rev. | Page 12 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
TOP VIEW
(Not t o Scale)
AD5110/
AD5112/
AD5114
3W
4B
1V
DD
2A
6 SCL
5GND
8 V
LOGIC
7 SDA
09582-004
NOTES
1. THE EXPOSED PAD IS INTE RNALLY FLOATING.
Figure 4. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD Positive Power Supply; 2.3 V to 5.5 V. This pin should be decoupled with 0.1 µF ceramic capacitors and 10 µF
capacitors.
2 A Terminal A of RDAC. GND ≤ VA ≤ VDD.
3 W Wiper Terminal of RDAC. GND ≤ VW ≤ VDD.
4 B Terminal B of RDAC. GND ≤ VB ≤ VDD.
5 GND Ground Pin, Logic Ground Reference.
6 SCL Serial Clock Line. This pin is used in conjunction with the SDA line to clock data into or out of the 16-bit input
registers.
7 SDA Serial Data Line. This pin is used in conjunction with the SCL line to clock data into or out of the 16-bit input
registers. It is a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up
resistor.
8 VLOGIC Logic Power Supply; 1.8 V to VDD. This pin should be decoupled with 0.1
µ
F ceramic capacitors and 10
µ
F
capacitors.
EPAD Exposed Pad. The exposed pad is internally floating.
A
Data Sheet AD5110/AD5112/AD5114
Rev. | Page 13 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
–0.06
–0.04
CODE ( Decimal)
R-INL (LSB)
–0.02
0
0.02
0.04
0.06
0.08
0.10
0
7
14
21
28
35
42
49
56
63
70
77
84
91
98
105
112
119
127
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
80kΩ, –40°C
80kΩ, +25°C
80kΩ, +125°C
09582-005
Figure 5. R-INL vs. Code (AD5110)
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63
5kΩ, –40°C
5kΩ, +25°C
5kΩ, +125°C
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
80kΩ, –40°C
80kΩ, +25°C
80kΩ, +125°C
CODE ( Decimal )
R-INL (LSB)
09582-006
Figure 6. R-INL vs. Code (AD5112)
–0.015
–0.010
–0.005
0
0.005
0.010
0.015
0.020
0246810 12 14 16 18 20 22 24 26 28 31
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
80kΩ, –40°C
80kΩ, +25°C
80kΩ, +125°C
CODE ( Decimal)
R-INL (LSB)
09582-007
Figure 7. R-INL vs. Code (AD5114)
–0.07
–0.06
–0.05
–0.04
–0.03
–0.02
–0.01
0
0.01
0.02
0
7
14
21
28
35
42
49
56
63
70
77
84
91
98
105
112
119
127
10kΩ, –40°C 10kΩ, +25°C 10kΩ, +125°C
80kΩ, –40°C 80kΩ, +25°C 80kΩ, +125°C
CODE ( Decimal)
R-DNL (LSB)
09582-008
Figure 8. R-DNL vs. Code (AD5110)
0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63
5kΩ, –40°C 5kΩ, +25°C 5kΩ, +125°C
10kΩ, –40°C 10kΩ, +25°C 10kΩ, +125°C
80kΩ, –40°C 80kΩ, +25°C 80kΩ, +125°C
–0.07
–0.06
–0.05
–0.04
–0.03
–0.02
–0.01
0
0.01
0.02
09582-009
CODE ( Decimal)
R-DNL (LSB)
Figure 9. R-DNL vs. Code (AD5112)
0246810 12 14 16 18 20 22 24 26 28 31
–0.018
–0.016
–0.014
–0.012
–0.010
–0.008
–0.006
–0.004
–0.002
0
0.002
0.004
10kΩ, –40°C 10kΩ, +25°C 10kΩ, +125°C
80kΩ, –40°C 80kΩ, +25°C 80kΩ, +125°C
CODE ( Decimal)
R-DNL (LSB)
09582-010
Figure 10. R-DNL vs. Code (AD5114)
A
AD5110/AD5112/AD5114 Data Sheet
Rev. | Page 14 of 28
CODE ( Decimal)
INL (LSB)
0
7
14
21
28
35
42
49
56
63
70
77
84
91
98
105
112
119
127
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
80kΩ, –40°C
80kΩ, +25°C
80kΩ, +125°C
09582-011
Figure 11. INL vs. Code (AD5110)
5kΩ, –40°C
5kΩ, +25°C
5kΩ, +125°C
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
80kΩ, –40°C
80kΩ, +25°C
80kΩ, +125°C
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63
CODE ( Decimal)
INL (LSB)
09582-012
Figure 12. INL vs. Code (AD5112)
0246810 12 14 16 18 20 22 24 26 28 31
CODE ( Decimal )
INL (LSB)
09582-013
–0.020
–0.015
–0.010
–0.005
0
0.005
0.010
0.015
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
80kΩ, –40°C
80kΩ, +25°C
80kΩ, +125°C
Figure 13. INL vs. Code (AD5114)
–0.07
–0.06
–0.05
–0.04
–0.03
–0.02
–0.01
0
0.01
0.02
0
7
14
21
28
35
42
49
56
63
70
77
84
91
98
105
112
119
127
10kΩ, –40°C 10kΩ, +25°C 10kΩ, +125°C
80kΩ, –40°C 80kΩ, +25°C 80kΩ, +125°C
09582-014
CODE ( Decimal)
DNL (LSB)
Figure 14. DNL vs. Code (AD5110)
–0.06
–0.05
–0.04
–0.03
–0.02
–0.01
0
0.01
0.02
0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63
5kΩ, –40°C 5kΩ, +25°C 5kΩ, +125°C
10kΩ, –40°C 10kΩ, +25°C 10kΩ, +125°C
80kΩ, –40°C 80kΩ, +25°C 80kΩ, +125°C
CODE ( Decimal)
09582-015
DNL (LSB)
Figure 15. DNL vs. Code (AD5112)
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 31
CODE ( Decimal )
DNL (LSB)
09582-016
–0.016
–0.014
–0.012
–0.010
–0.008
–0.006
–0.004
–0.002
0
0.002
0.004 10kΩ, –40°C 10kΩ, +25°C 10kΩ, +125°C
80kΩ, –40°C 80kΩ, +25°C 80kΩ, +125°C
Figure 16. DNL vs. Code (AD5114)
A
Data Sheet AD5110/AD5112/AD5114
Rev. | Page 15 of 28
0
100
–100
200
300
400
SUPPLY CURRENT ( nA)
500
600
700
800
–40 –25 –10 520 35
TEMPERATURE ( °C)
50 65 80 95 110 125
2.3V AVERAGE OF IDD
2.3V AVERAGE OF ILOGIC
3.3V AVERAGE OF IDD
3.3V AVERAGE OF ILOGIC
5.0V AVERAGE OF IDD
5.0V AVERAGE OF ILOGIC
09582-017
Figure 17. Supply Current vs. Temperature
0
20
40
60
80
100
120
140
160
180
200
POTENTIOMETER MODE TEMPCO (ppm/°C)
10kΩ
80kΩ
5kΩ
09582-018
020 40 60
CODE ( Decimal)
80 100 120
010 20 30 40 50 60
0 5 10 15 20 25 30
AD5110
AD5112
AD5114
V
DD
= 5V
Figure 18. Potentiometer Mode Tempco ((ΔVW/VW)/ΔT × 106) vs. Code
0
–60
–50
–40
–30
–20
–10
100M10M1M100k10k
GAI N ( dB)
FREQUENCY (Hz)
0x20
0x10
0x08
0x04
0x02
0x01
0x00
09582-019
Figure 19. 5 kΩ Gain vs. Frequency vs. Code
–0.02
0
0.02
0.04
0.06
0.08
0.10
0.12
5.04.54.03.53.02.5
DIGITAL I NP UT VOLTAGE (V)
SUPPLY CURRENT, I
LOGIC
(mA)
2.01.51.00.50
V
LOGIC
= 5.0V
V
LOGIC
= 3.3V
V
LOGIC
= 2.3V
V
LOGIC
= 1.8V
09582-020
Figure 20. Supply Current (ILOGIC) vs. Digital Input Voltage
0
20
40
60
80
100
120
140
160
180
200
POTENTIOMETER MODE TEMPCO (ppm/°C)
09582-021
020 40 60
CODE ( Decimal)
80 100 120
010 20 30 40 50 60
0 5 10 15 20 25 30
10kΩ
80kΩ
5kΩ
V
DD
= 5V
AD5110
AD5112
AD5114
Figure 21. Rheostat Mode Tempco ((ΔRWB/RWB)/ΔT × 106) vs. Code
–50
–40
–30
–10
0
1M 10M100k10k
GAIN (d B)
FREQUENCY (Hz)
0x40
0x10
0x04
0x02
–20
–70
–60
0x08
0x01
0x20
0x00
(0x20)
(0x08)
(0x02)
(0x01)
(0x04)
(0x00)
(0x10)
[0x10]
[0x04]
[0x01]
[0x00]
[0x02]
[0x08]
AD5110 (AD5112) [ AD5114]
09582-022
Figure 22. 10 kΩ Gain vs. Frequency vs. Code
A
AD5110/AD5112/AD5114 Data Sheet
Rev. | Page 16 of 28
–60
–50
–40
–30
–10
0
10k 1M100k
GAI N ( dB)
FREQUENCY (Hz)
–20
–80
–70
0x40
0x10
0x04
0x02
0x08
0x01
0x20
0x00
(0x20)
(0x08)
(0x02)
(0x01)
(0x04)
(0x00)
(0x10)
[0x10]
[0x04]
[0x01]
[0x00]
[0x02]
[0x08]
AD5110 (AD5 112) [AD5 114]
09582-023
Figure 23. 80 kΩ Gain vs. Frequency vs. Code
–80
–70
–60
–50
–40
–30
–20
–10
0
10k 100k 1M 10M
PHASE ( Degrees)
FREQUENCY (Hz)
FULL SCALE
HALF S CALE
QUART E R S CALE
AD5110
RAB = 10kΩ
09582-024
Figure 24. Normalized Phase Flatness vs. Frequency
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
THD + N ( dB)
FREQUENCY (Hz)
20 200 2k 20k 200k
10kΩ
5kΩ
80kΩ
09582-025
VDD = 5V,
VA = 2.5V + 1VRMS
VB = 2.5V
CODE = HALF S CALE
NOISE FILTER = 22kHz
Figure 25. Total Harmonic Distortion + Noise (THD + N) vs. Frequency
0
10
20
30
40
50
60
70
BANDWIDTH ( M Hz )
80
CODE ( Decimal)
5k + 250pF
10k + 75pF
10k + 150pF
10k + 250pF
80k + 0pF
80k + 75pF
80k + 150pF
80k + 250pF
5k + 0pF
5k + 75pF
5k + 150pF
10k + 0pF
010 20 30 40 50 60
0 5 10 15 20 25 30
0 5 10 15
09582-026
AD5110
AD5112
AD5114
Figure 26. Maximum Bandwidth vs. Code vs. Net Capacitance
0
30
60
90
INCREMENTAL WIPER ON RESISTANCE (Ω)
120
150
0 1 2 3
V
DD
(V) 4 5 6
5.5V
5V
3.3V
2.7V
2.3V
TEMPERATURE = 25°C
09582-027
Figure 27. Incremental Wiper On Resistance vs. VDD
THD + N ( dB)
AMPLITUDE ( V rms)
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0.001 0.01 0.1 1
09582-028
10kΩ
5kΩ
80kΩ
VDD = 5V,
VA = 2.5V + VIN
VB = 2.5V
fIN = 1kHz
CODE = HALF S CALE
NOISE FILTER = 22kHz
Figure 28. Total Harmonic Distortion + Noise (THD + N) vs. Amplitude
A
Data Sheet AD5110/AD5112/AD5114
Rev. | Page 17 of 28
–0.10
–0.05
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
–1 1 3 5
TIME (µs)
RELAT I VE VOLTAGE (V)
7 9
09582-029
V
DD
= 5V
V
A
= V
DD
V
B
= GND
10kΩ
80kΩ
5kΩ
Figure 29. Maximum Transition Glitch
0
0.2
0.4
0.6
0.8
1.0
1.2
0
0.0005
0.0010
0.0015
0.0020
0.0025
–400–500–600 –300 –200 –100 0100 200 300 400 500 600
CUMULATIVE PROBABILITY
PROBABILITY DENSITY
RESISTOR DRIFT (ppm)
09582-051
Figure 30. Resistor Lifetime Drift
–70
–60
–50
–40
–30
–20
–10
0
FREQUENCY (Hz)
PSRR ( dB)
10 100 1k 10k 100k 1M
5kΩ
10kΩ
80kΩ
09582-031
V
DD
= 5V ± 10% AC
V
A
= 4V
V
B
= GND
HALF SCAL E
T
A
= 25° C
Figure 31. Power Supply Rejection Ratio (PSRR) vs. Frequency
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
10kΩ
80kΩ
5kΩ
2.50.6 1.2 1.80
VOLTAGE (mV)
TIME (µs)
V
DD
= 5V
V
A
= V
DD
V
B
= GND
09582-032
Figure 32. Digital Feedthrough
–70
–60
–50
–40
–30
–20
–10
0
1k 10k 1M 10M
GAIN (d B)
FREQUENCY (Hz)
5kΩ
10kΩ
80kΩ
09582-033
Figure 33. Shutdown Isolation vs. Frequency
0
1
2
3
4
5
6
7
THEORETICAL IMAX (mA)
10kΩ
80kΩ
5kΩ
020 40 60
CODE ( Decimal)
80 100 120
010 20 30 40 50 60
0 5 10 15 20 25 30
AD5110
AD5112
AD5114
09582-034
Figure 34. Theoretical Maximum Current vs. Code
A
AD5110/AD5112/AD5114 Data Sheet
Rev. | Page 18 of 28
TEST CIRCUITS
Figure 35 to Figure 40 define the test conditions used in the Specifications section.
AW
B
NC
I
W
DUT
V
MS
NC = NO CONNECT
09582-035
Figure 35. Resistor Position Nonlinearity Error
(Rheostat Operation: R-INL, R-DNL)
AW
B
DUT
V
MS
V+
V+ = V
DD
1LSB = V+/2
N
09582-036
Figure 36. Potentiometer Divider Nonlinearity Error (INL, DNL)
+
–
DUT
0.1V
=0.1V
I
WB
I
WB
W
B
NC = NO CONNECT
R
W
A
NC
GND TO V
DD
09582-037
Figure 37. Wiper Resistance
AW
BV
MS
~
V
A
V
DD
V+
V+ = V
DD
±10%
ΔV
MS
%
ΔV
DD
%
PSS (%/%) =
PSRR (dB) = 20 logΔV
MS
ΔV
DD
09582-038
Figure 38. Power Supply Sensitivity (PSS, PSRR)
OFFSET
GND
A
B
DUT W
+15V
VIN VOUT
AD8652
–15V
2.5V
09582-039
Figure 39. Gain and Phase vs. Frequency
DUT I
CM
W
B
V
DD
GND
A
V
DD
GND
GND
V
DD
GND
V
DD
09582-040
Figure 40. Common-Mode Leakage Current
A
Data Sheet AD5110/AD5112/AD5114
Rev. | Page 19 of 28
THEORY OF OPERATION
The AD5110/AD5112/AD5114 digital programmable resistors
are designed to operate as true variable resistors for analog
signals within the terminal voltage range of GND < VTERM <
VDD. The resistor wiper position is determined by the RDAC
register contents. The RDAC register acts as a scratchpad
register that allows unlimited changes of resistance settings.
The RDAC register can be programmed with any position
setting using the I2C interface. Once a desirable wiper position
is found, this value can be stored in the EEPROM memory.
Thereafter, the wiper position is always restored to that position
for subsequent power-up. The storing of EEPROM data takes
approximately 18 ms; during this time, the device is locked and
does not acknowledge any new command, thus preventing any
changes from taking place.
RDAC REGISTER AND EEPROM
The RDAC register directly controls the position of the digital
potentiometer wiper. For example, when the RDAC register is
loaded with 0x3F (128-taps), the wiper is connected to full scale
of the variable resistor. The RDAC register is a standard logic
register; there is no restriction on the number of changes
allowed.
It is possible to both write to and read from the RDAC register
using the I2C interface (see Table 10).
The contents of the RDAC register can be stored to the
EEPROM using Command 1 (Table 10). Thereafter, the
RDAC register is always set at that position for any future
on-off-on power supply sequence. It is possible to read back
the data saved into the EEPROM with Command 6 in Table 10.
In addition, the resistor tolerance error is saved within the
EEPROM; this can be read back and used to calculate the end-
to-end tolerance, providing an accuracy of 0.1%.
Low Wiper Resistance Feature
The AD5110/AD5112/AD5114 include extra steps to achieve a
minimum resistance between Terminal W and Terminal A or
Terminal B. These extra steps are called bottom scale and top
scale. At bottom scale, the typical wiper resistance decreases
from 70 Ω to 45 Ω. At top scale, the resistance between
Terminal A and Terminal W is decreased by 1 LSB, and the
total resistance is reduced to 70 Ω. The extra steps are not equal
to 1 LSB and are not included in the INL, DNL, R-INL, and
R-DNL specifications.
I2C SERIAL DATA INTERFACE
The AD5110/AD5112/AD5114 have 2-wire I2C-compatible
serial interfaces. These devices can be connected to an I2C bus
as a slave device under the control of a master device. See
Figure 3 for a timing diagram of a typical write sequence.
The AD5110/AD5112/AD5114 support standard (100 kHz) and
fast (400 kHz) data transfer modes. Support is not provided for
10-bit addressing and general call addressing.
The 2-wire serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a start
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high. The following byte is
the address byte, which consists of the 7-bit slave address
and an R/W bit. The slave device corresponding to the
transmitted address responds by pulling SDA low during
the ninth clock pulse (this is termed the acknowledge bit).
At this stage, all other devices on the bus remain idle while
the selected device waits for data to be written to, or read
from, its shift register.
2. If the R/W bit is set high, the master reads from the slave
device. However, if the R/W bit is set low, the master writes
to the slave device.
3. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge
bit). The transitions on the SDA line must occur during
the low period of SCL and remain stable during the high
period of SCL.
4. When all data bits have been read or written, a stop
condition is established. In write mode, the master pulls
the SDA line high during the 10th clock pulse to establish
a stop condition. In read mode, the master issues a no
acknowledge for the ninth clock pulse (that is, the SDA line
remains high). The master brings the SDA line low before
the 10th clock pulse, and high during the 10th clock pulse to
establish a stop condition.
I2C Address
The AD5110/AD5112/AD5114 each have two different slave
address options available. See Table 9 for a list of slave addresses.
Table 9. Device Address Selection
Model 7-Bit I2C Device Address
AD511X1 BCPZ Y2 0101111
AD511X1 BCPZ Y2-1 0101100
1 Model.
2 Resistance.
A
AD5110/AD5112/AD5114 Data Sheet
Rev. | Page 20 of 28
INPUT SHIFT REGISTER
For the AD5110/AD5112/AD5114, the input shift register is
16 bits wide (see Figure 2). The 16-bit word consists of five
unused bits (should be set to zero), followed by three control
bits, and eight RDAC data bits. If the RDAC register is read from
or written to in the AD5112, Bit DB0 is a don’t care. The RDAC
register is read from or written to in the AD5114, Bit DB0 and
DB1 are don’t cares. Data is loaded MSB first (Bit DB15).
The three control bits determine the function of the software
command (Table 10). Figure 3 shows a timing diagram of a
typical AD5110/AD5112/AD5114 write sequence.
The command bits (Cx) control the operation of the digital
potentiometer and the internal EEPROM. The data bits (Dx)
are the values that are loaded into the decoded register.
Table 10. Command Operation Truth Table
Command
Number
Command Data1
DB10 DB8 DB7 DB0
C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 Operation
0 0 0 0 X X X X X X X X No operation
1 0 0 1 X X X X X X X X Write contents of RDAC register to EEPROM
2 0 1 0
7
MSB
6 5 4 3 2 12 02, 3
LSB
Write contents of serial register data to RDAC
1 0 0 0 0 0 0 0 Top scale
1 1 1 1 1 1 1 1 Bottom scale
3 0 1 1 X X X X X X X A0 Software shutdown
0: shutdown off
1: shutdown on
4 1 0 0 X X X X X X X X Software reset: refresh RDAC register with EEPROM
5 1 0 1 X X X X X X X X Read contents of RDAC register
6 1 1 0 X X X X X X A1 A0 Read contents of EEPROM
A1 A0 Data
0 0 Wiper position saved
0 1 Resistor tolerance
1 X is don’t care.
2 In the AD5114, this bit is a don’t care.
3 In the AD5112, this bit is a don’t care.
A
Data Sheet AD5110/AD5112/AD5114
Rev. | Page 21 of 28
WRITE OPERATION
When writing to the AD5110/AD5112/AD5114, the user
must begin with a start command followed by an address
byte (R/W = 0), after which the AD5110/AD5112/AD5114
acknowledge that it is prepared to receive data by pulling
SDA low.
Two bytes of data are then written to the DAC, the most
significant byte, followed by the least significant byte. Both of
these data bytes are acknowledged by the AD5110/AD5112/
AD5114. A stop condition follows. The write operations for
the AD5110/AD5112/AD5114 are shown in Figure 41,
Figure 42, and Figure 43.
A repeated write function gives the user flexibility to update
the device a number of times after addressing the part only
once, as shown in Figure 44.
SCL
SDA
START BY
MASTER ACK. B Y
AD5110 ACK. B Y
AD5110
FRAME 1
SERIAL BUS ADDRES S BY TE FRAME 2
MOST SIGNIFICANT DATA BYT E
FRAME 3
LEAST SIGNIFICANT DATA BYT E
SCL (CONT INUED)
SDA (CONTINUED)
ACK. B Y
AD5110 STOP BY
MASTER
0
1 9
1
9 9
91
10 1 1 A1 A0 0 0 0 0 0 C2 C1 C0
D7 D6 D5 D4 D3 D2 D1 D0
R/W
09582-041
Figure 41. AD5110 Interface Write Command
SCL
SDA
START BY
MASTER ACK. B Y
AD5112 ACK. B Y
AD5112
FRAME 1
SERIAL BUS ADDRES S BY TE FRAME 2
MOST SIGNIFICANT DATA BYT E
FRAME 3
LEAST SIGNIFICANT DATA BYT E
SCL (CONT INUED)
SDA (CONTINUED)
ACK. B Y
AD5112 STOP BY
MASTER
0
1 9
1
9 9
91
10 1 1 A1 A0 0 0 0 0 0 C2 C1 C0
D6 D5 D4 D3 D2 D1 D0 0
R/W
09582-042
Figure 42. AD5112 Interface Write Command
A
AD5110/AD5112/AD5114 Data Sheet
Rev. | Page 22 of 28
SCL
SDA
START BY
MASTER ACK. B Y
AD5114 ACK. B Y
AD5114
FRAME 1
SERIAL BUS ADDRES S BY TE FRAME 2
MOST SIGNIFICANT DATA BYT E
FRAME 3
LEAST SIGNIFICANT DATA BYT E
SCL (CONT INUED)
SDA (CONTINUED)
ACK. B Y
AD5114 STOP BY
MASTER
0
1 9
1
9 9
91
10 1 1 A1 A0 0 0 0 0 0 C2 C1 C0
D2 D1D3D5 D4 D0 0 0
R/W
09582-043
Figure 43. AD5114 Interface Write Command
SCL
SDA 0
1 9
1
9 9
91
10 1 1 A1 A0 R/W 00000C2 C1 C0
D7 D6 D5 D4 D3 D2 D1 D0
SCL (CONT INUED)
SDA (CONTINUED)
SCL (CONT INUED)
SDA (CONTINUED)
SCL (CONT INUED)
SDA (CONTINUED)
19 9
D7 D6 D5 D4 D3 D2 D1 D0
19 9
0 0 0 0 0 C2 C1 C0
FRAM E 4
MOST SIGNIFICANT DATA BYT E
FRAM E 5
LEAST SIGNIFICANT DATA BYT E
START BY
MASTER ACK. BY
AD5110
ACK. BY
AD5110
ACK. BY
AD5110
ACK. BY
AD5110
ACK. BY
AD5110 STOP BY
MASTER
FRAM E 1
SERIAL BUS ADDRES S BY TE FRAM E 2
MOST SIGNIFICANT DATA BYT E
FRAM E 3
LEAST SIGNIFICANT DATA BYT E
09582-044
Figure 44. AD5110 Interface Multiple Write
A
Data Sheet AD5110/AD5112/AD5114
Rev. | Page 23 of 28
EEPROM WRITE ACKNOWLEGDE POLLING
After each write operation to the EEPROM, an internal write
cycle begins. The I2C interface of the device is disabled. To
determine if the internal write cycle is complete and the I2C
interface is enabled, interface polling can be executed. I2C
interface polling can be conducted by sending a start condition,
followed by the slave address and the write bit. If the I2C
interface responds with an acknowledge, the write cycle is
complete, and the interface is ready to proceed with further
operations. Otherwise, I2C interface polling can be repeated
until it succeeds.
READ OPERATION
The AD5110/AD5112/AD5114 allow read back of the contents
of the RDAC register and EEPROM memory through the I2C
interface by using Command 6 (see Table 10).
When reading data back from the AD5110/AD5112/AD5114,
the user must first issue a readback command to the device.
This begins with a start command, followed by an address
byte (R/W = 0), after which the AD5110/AD5112/AD5114
acknowledges that it is prepared to receive data by pulling
SDA low.
Two bytes of data are then written to the AD5110/AD5112/
AD5114, the most significant byte followed by the least
significant byte. Both of these data bytes are acknowledged by
the AD5110/AD5112/AD5114. A stop condition follows. These
bytes contain the read instruction, which enables readback of
the RDAC register, EEPROM memory. The user can then read
back the data. This begins with a start command followed by an
address byte (R/W = 1), after which the device acknowledges
that it is prepared to transmit data by pulling SDA low. Two
bytes of data are then read from the device, which are both
acknowledged by the master, as shown in Figure 45. A stop
condition follows. If the master does not acknowledge the first
byte, then the second byte is not transmitted by the AD5110/
AD5112/AD5114.
The AD5110/AD5112/AD5114 does not support repeat
readback.
RESET
The AD5110/AD5112/AD5114 can be reset by executing
Command 4 (see Table 10). The reset command loads the
RDAC register with the contents of the EEPROM and takes
approximately 25 µs. EEPROM is pre-loaded to midscale at the
factory, and initial power-up is, accordingly, at midscale.
SHUTDOWN MODE
The AD5110/AD5112/AD5114 can be shut down by executing
the software shutdown command, Command 3 (see Table 10).
This feature places the RDAC in a zero-power-consumption
state where Terminal A is open-circuited and the wiper,
Terminal W is connected to Terminal B but a finite wiper
resistance of 45 Ω is present. The part can be taken out of
shutdown mode by executing Command 3 (see Table 10)
and setting Bit DB0 to 0.
SCL
SDA
START BY
MASTER ACK. BY
AD5110 ACK. BY
AD5110
FRAM E 1
SERIAL BUS ADDRES S BY TE FRAM E 2
MOST SIGNIFICANT DATA BYT E
FRAM E 3
LEAST SIGNIFICANT DATA BYT E
SCL (CONT INUED)
SDA (CONTINUED)
ACK. BY
AD5110 STOP BY
MASTER
STOP BY
MASTER
0
1 9
1
9 9
91
10 1 1 A1 A0 0 0 0 0 0 C2 C1 C0
D4 D3D5D7 D6 D2 D1 D0
R/W
SCL
SDA
START BY
MASTER ACK. BY
AD5110 NO ACK.
BY MASTER
FRAM E 1
SERIAL BUS ADDRES S BY TE FRAM E 2
MOST SIGNIFICANT DATA BYT E
0
1 9 91
10 1 1 A1 A0 0 0 0 0 0 C2 C1 C0
R/W
09582-045
Figure 45. AD5110 Interface Read Command
A
AD5110/AD5112/AD5114 Data Sheet
Rev. | Page 24 of 28
RDAC ARCHITECTURE
To achieve optimum performance, Analog Devices, Inc., has
patented the RDAC segmentation architecture for all the digital
potentiometers. In particular, the AD5110/AD5112/AD5114
employ a two-stage segmentation approach as shown in
Figure 46. The AD5110/AD5112/AD5114 wiper switch is
designed with the transmission gate CMOS topology and with
the gate voltage derived from VDD.
R
L
R
L
R
L
R
L
R
S
W
R
S
A
B
BS
6-BIT/7-BIT/8-BIT
ADDRESS
DECODER
TS
09582-046
Figure 46. AD5110/AD5112/AD5114 Simplified RDAC Circuit
Top Scale/Bottom Scale Architecture
In addition, the AD5110/AD5112/AD5114 include a new
feature to reduce the resistance between terminals. These extra
steps are called bottom scale and top scale. At bottom scale, the
typical wiper resistance decreases from 70 Ω to 45 Ω. At top
scale, the resistance between Terminal A and Terminal W is
decreased by 1 LSB, and the total resistance is reduced to 70 Ω.
The extra steps are not equal to 1 LSB and are not included in
the INL, DNL, R-INL, and R-DNL specifications.
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation—±8% Resistor Tolerance
The AD5110/AD5112/AD5114 operate in rheostat mode when
only two terminals are used as a variable resistor. The unused
terminal can be floating or tied to the Terminal W as shown in
Figure 47.
A
W
B
A
W
B
A
W
B
09582-047
Figure 47. Rheostat Mode Configuration
The nominal resistance between Terminal A and Terminal B,
RAB, is available in 5 k, 10 k, and 80 k and has 32/64/128
tap points accessed by the wiper terminal. The 5-/6-/7-bit data
in the RDAC latch is decoded to select one of the 32/64/128
possible wiper settings. The general equations for determining
the digitally programmed output resistance between the W
terminal and B terminal are
AD5110:
BS
WB RR
Bottom scale (0xFF) (1)
W
AB
WB RR
D
DR
128
)( From 0x00 to 0x80 (2)
AD5112:
BS
WB RR
Bottom scale (0xFF) (3)
W
AB
WB RR
D
DR
64
)( From 0x00 to 0x40 (4)
AD5114:
BS
WB RR
Bottom scale (0xFF) (5)
W
AB
WB RR
D
DR
32
)( From 0x00 to 0x20 (6)
where:
D is the decimal equivalent of the binary code in the 5-/6-/7-bit
RDAC register.
RAB is the end-to-end resistance.
RW is the wiper resistance.
RBS is the wiper resistance at bottom scale
A
Data Sheet AD5110/AD5112/AD5114
Rev. | Page 25 of 28
Similar to the mechanical potentiometer, the resistance of
the RDAC between the W terminal and the A terminal also
produces a digitally controlled complementary resistance, RWA.
RWA also gives a maximum of 8% absolute resistance error. RWA
starts at the maximum resistance value and decreases as the
data loaded into the latch increases. The general equations for
this operation are
AD5110:
W
ABAW RRR +=
Bottom scale (0xFF) (7)
W
ABAW RR
D
DR +×
−
=
128
128
)(
From 0x00 to 0x7F (8)
TS
AW
RR =
Top scale (0x80) (9)
AD5112:
W
ABAW RRR +=
Bottom scale (0xFF) (10)
W
ABAW RR
D
DR +×
−
=
64
64
)(
From 0x00 to 0x3F (11)
TS
AW RR =
Top scale (0x40) (12)
AD5114:
W
ABAW RRR +=
Bottom scale (0xFF) (13)
W
ABAW RR
D
DR +×
−
=
32
32
)(
From 0x00 to 0x1F (14)
TS
AW
RR =
Top scale (0x20) (15)
where:
D is the decimal equivalent of the binary code in the 5-/6-/7-bit
RDAC register.
RAB is the end-to-end resistance.
RW is the wiper resistance.
RTS is the wiper resistance at top scale.
In the bottom-scale condition or top-scale condition, a finite
total wiper resistance of 45 Ω is present. Regardless of which
setting the part is operating in, take care to limit the current
between Terminal A to Terminal B, Terminal W to Terminal A,
and Terminal W to Terminal B, to the maximum continuous
current of ±6 mA or to the pulse current specified in Table 6.
Otherwise, degradation or possible destruction of the internal
switch contact can occur.
Calculating the Actual End-to-End Resistance
The resistance tolerance is stored in the internal memory
during factory testing. The actual end-to-end resistance can,
therefore, be calculated, which is valuable for calibration,
tolerance matching, and precision applications.
The resistance tolerance in percentage is stored in fixed-point
format, using an 8-bit sign magnitude binary. The data can be
read back by executing Command 6 and setting Bit DB0 (A0).
The MSB is the sign bit (0 = − and 1 = +) and the next four bits
are the integer part, the fractional part is represented by the
three LSBs, as shown in Table 11.
Table 11. Tolerance Format
Data Byte
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Sign 24 23 22 21 . 2-1 2-2 2-3
For example, if RAB = 10 kΩ and the data readback shows
01010010, the end-to-end resistance can be calculated as,
if,
DB[7] is 0 = negative
DB[6:3] is 1010 = 10
DB[2:0] is 010 = 2 × 2−3 = 0.25
then,
tolerance = −10.25% and, therefore, RAB = 8.975 kΩ
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A that is proportional to the input
voltage at A to B, as shown in Figure 48. Unlike the polarity of
VDD to GND, which must be positive, voltage across A-to-B, W-
to-A, and W-to-B can be at either polarity.
A
V
I
W
B
V
O
09582-048
Figure 48. Potentiometer Mode Configuration
Connecting Terminal A to 5 V and Terminal B to ground
produces an output voltage at the Wiper W to Terminal B
ranging from 0 V to 5 V. The general equation defining the
output voltage at VW with respect to ground for any valid input
voltage applied to Terminal A and Terminal B, is:
B
AB
AW
A
AB
WB
W
V
R
DR
V
R
DR
DV ×+×= )(
)(
)(
(16)
where:
RWB(D) can be obtained from Equation 1 to Equation 6.
RAW(D) can be obtained from Equation 7 to Equation 15.
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors, RAW and RWB, and not the
absolute values. Therefore, the temperature drift reduces to
5 ppm/°C.
A
AD5110/AD5112/AD5114 Data Sheet
Rev. | Page 26 of 28
TERMINAL VOLTAGE OPERATING RANGE
The AD5110/AD5112/AD5114 are designed with internal
ESD diodes for protection. These diodes also set the voltage
boundary of the terminal operating voltages. Positive signals
present on Terminal A, Terminal B, or Terminal W that
exceed VDD are clamped by the forward-biased diode. There
is no polarity constraint between VA, VW, and VB, but they
cannot be higher than VDD or lower than GND.
GND
V
DD
A
W
B
09582-049
Figure 49. Maximum Terminal Voltages Set by VDD and GND
POWER-UP SEQUENCE
Because there are diodes to limit the voltage compliance at
Terminal A, Terminal B, and Terminal W (Figure 49), it is
important to power VDD first before applying any voltage
to Terminal A, Terminal B, and Terminal W. Otherwise,
the diode is forward-biased such that VDD is powered
unintentionally. The ideal power-up sequence is GND,
VDD, VLOGIC, digital inputs, and VA, VB, and VW. The order
of powering VA, VB, VW, and digital inputs is not important as
long as they are powered after VDD and VLOGIC. Regardless of the
power-up sequence and the ramp rates of the power supplies,
once VLOGIC is powered, the power-on preset activates, which
restores EEPROM values to the RDAC registers.
LAYOUT AND POWER SUPPLY BIASING
It is always a good practice to use compact, minimum lead
length layout design. The leads to the input should be as direct
as possible with a minimum conductor length. Ground paths
should have low resistance and low inductance. It is also good
practice to bypass the power supplies with quality capacitors.
Low equivalent series resistance (ESR) 1 μF to 10 μF tantalum
or electrolytic capacitors should be applied at the supplies to
minimize any transient disturbance and to filter low frequency
ripple. Figure 50 illustrates the basic supply bypassing
configuration for the AD5110/AD5112/AD5114.
V
DD
V
LOGIC
V
DD
+
GND
C1
0.1µF
C2
10µF
V
LOGIC
+
C3
0.1µF C4
10µF
AD5110/
AD5112/
AD5114
09582-050
Figure 50. Power Supply Bypassing
A
Data Sheet AD5110/AD5112/AD5114
Rev. A | Page 27 of 28
OUTLINE DIMENSIONS
1.70
1.60
1.50
0.425
0.350
0.275
TOP VIEW
8
1
5
4
0.30
0.25
0.20
BOTTOM VIEW
PIN 1 INDEX
AREA
2.00
BSC SQ
SEATING
PLANE
0.60
0.55
0.50
1.10
1.00
0.90
0.20 RE F
0.175 REF
0.05 MAX
0.02 NOM
0.50 BSC
EXPOSED
PAD
PIN 1
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CO NF IG URATI O N AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
07-11-2011-B
Figure 51. 8-Lead Frame Chip Scale Package[LFCSP_UD]
2.00 mm × 2.00 mm Body, Ultra Thin, Dual Lead
(CP-8-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2 RAB (kΩ) Resolution
Temperature
Range
Package
Description I2C Address
Package
Option Branding
AD5110BCPZ10-RL7 10 128 −40°C to +125°C 8-Lead LFCSP_UD 0101111 CP-8-10 4J
AD5110BCPZ10-500R7 10 128 −40°C to +125°C 8-Lead LFCSP_UD 0101111 CP-8-10 4J
AD5110BCPZ10-1-RL7 10 128 −40°C to +125°C 8-Lead LFCSP_UD 0101100 CP-8-10 4H
AD5110BCPZ80-RL7 80 128 −40°C to +125°C 8-Lead LFCSP_UD 0101111 CP-8-10 4L
AD5110BCPZ80-500R7 80 128 −40°C to +125°C 8-Lead LFCSP_UD 0101111 CP-8-10 4L
AD5110BCPZ80-1-RL7 80 128 −40°C to +125°C 8-Lead LFCSP_UD 0101100 CP-8-10 4K
AD5112BCPZ5-RL7 5 64 −40°C to +125°C 8-Lead LFCSP_UD 0101111 CP-8-10 7P
AD5112BCPZ5-500R7 5 64 −40°C to +125°C 8-Lead LFCSP_UD 0101111 CP-8-10 7P
AD5112BCPZ5-1-RL7 5 64 −40°C to +125°C 8-Lead LFCSP_UD 0101100 CP-8-10 7N
AD5112BCPZ10-RL7 10 64 −40°C to +125°C 8-Lead LFCSP_UD 0101111 CP-8-10 7L
AD5112BCPZ10-500R7 10 64 −40°C to +125°C 8-Lead LFCSP_UD 0101111 CP-8-10 7L
AD5112BCPZ10-1-RL7 10 64 −40°C to +125°C 8-Lead LFCSP_UD 0101100 CP-8-10 7K
AD5112BCPZ80-RL7 80 64 −40°C to +125°C 8-Lead LFCSP_UD 0101111 CP-8-10 7R
AD5112BCPZ80-500R7 80 64 −40°C to +125°C 8-Lead LFCSP_UD 0101111 CP-8-10 7R
AD5112BCPZ80-1-RL7 80 64 −40°C to +125°C 8-Lead LFCSP_UD 0101100 CP-8-10 7Q
AD5114BCPZ10-RL7 10 32 −40°C to +125°C 8-Lead LFCSP_UD 0101111 CP-8-10 81
AD5114BCPZ10-500R7 10 32 −40°C to +125°C 8-Lead LFCSP_UD 0101111 CP-8-10 81
AD5114BCPZ10-1-RL7 10 32 −40°C to +125°C 8-Lead LFCSP_UD 0101100 CP-8-10 80
AD5114BCPZ80-RL7 80 32 −40°C to +125°C 8-Lead LFCSP_WD 0101111 CP-8-10 83
AD5114BCPZ80-500R7 80 32 −40°C to +125°C 8-Lead LFCSP_WD 0101111 CP-8-10 83
AD5114BCPZ80-1-RL7 80 32 −40°C to +125°C 8-Lead LFCSP_WD 0101100 CP-8-10 82
EVAL-AD5110SDZ Evaluation Board
1 Z = RoHS Compliant Part.
2 The EVAL-AD5110SDZ has an RAB of 10 kΩ.
AD5110/AD5112/AD5114 Data Sheet
Rev. A | Page 28 of 28
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09582-0-4/12(A)
