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Preliminary Datasheet
R2A20133ASP
Critical Conduction Mode PFC Control IC
Description
The R2A20133A controls a boost converter to provide an active power factor correction.
The R2A20133A adopts critical conduction mode for power factor correction and realizes high efficiency and a low
switching noise by zero current switching.
Because the zero current is detected by using the GND current, the ZCD Auxiliary winding is unnecessary.
The feedback loop open detection , two mode overvoltag e protection , overcurren t protection are built in the R2A20133A ,
and can constitute a power supply system of high reliability with few external parts.
Features
Absolute Maximum Ratings
Supply volta ge Vcc: 24 V
Operating junction temperature Tjopr: –40 to +150°C
Electrical characteristics
UVLO operation start voltage VH: 12 V 0.8 V
UVLO operation shutdown volta ge VL: 9. 2 V 0. 7 V
UVLO hysteres i s vol ta ge Hy suvl: 2.8 V 0.7 V
Functions
Boost converter control with critical conduction mode
Two mode overvoltage protection and OVP2
Mode 1: Dynamic OVP corresponding to a voltage rise by load change
Mode 2: Static OVP corresponding to overvoltage in stable.
OVP2: OVP2 sense the PFC output voltage by independenced pin.
Feedback loop open det ect i on
Overcurrent protection
Dynamic UVP corresponding to a voltage fall by load change
Off Time Control function (Frequency Limiter)
Package lineup: Pb-free SOP-8 (JEDEC)
Ordering Information
Part No. Package Name Package Code Package
Abbreviation Taping Abbreviation
(Quantity)
R2A20133ASP#W5 — PRSP0008DJ-A SP W (2,500 pcs/reel)
R03DS0049EJ0200
Rev.2.00
Nov 02, 2011
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Pin Arrangement
(Top view)
FB 1
RT 2
COMP 3
OVP2
VCC
OUT
GND
CS
4
8
7
6
5
Pin Function
Pin No. Pin Name Function
1 FB Error amplifier input terminal
2 RT A resistor connection terminal for RAMP current setting
3 COMP Error amplifier output terminal
4 OVP2 Over voltage detection terminal
5 CS Zero current detection and overcurrent detec t ion input terminal
6 GND Ground
7 OUT Power MOSFET drive terminal
8 VCC Supply voltage terminal
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Block Diagram
UVLO
OVP & FB_LOW BLOCK
FB
GD Disable (OVP & FB_LOW)
ON: 12V
OFF: 9.2V
VREF: 5.02V
Ramp Control
LOGIC BLOCK
OVP2
CS
5
RT
2
VCC
8
OUT
7
GND
6
FB
1
COMP
3
OVP2
4
–0.6V
60k
VREF
5p
–
+
0V
+
–
42μA
1V
10p
–
+
VREF
ErrorAmp
4.1V 2.51V
–
+
COMP
Discharge
VFB × 1.04V
Dynamic OVP
Dynamic UVP
+
–
VFB × 0.92V
+
–
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Absolute Maximum Ratings
(Ta = 25°C)
Item Symbol Ratings Unit Note
Supply Voltage VCC –0.3 to +24 V
Ipk-snk-out 0.9 OUT terminal peak current Ipk-src-out –0.50 A 3
Idc-snk-out 100 OUT terminal DC current Idc-src-out –50 mA
COMP terminal current Icomp +1
–1 mA
RT terminal current Irt –60 to –2 A
Vt-group1 –0.3 to VCC 4 Terminal voltage Vt-group2 –0.3 to 5.3 V 5
CS terminal voltage Vcs –5 to +0.3 V
Power dissipation Pt 0.68 W 6
Operating junction temperatur e Tj-opr –40 to +150 °C
Storage temperature Tstg –55 to +150 °C
Notes: 1. Rated voltages are with reference to the GND terminal.
2. For rated currents, inflow to the IC is indicated by (+), and outflow by (–).
3. Shows the transient current when driving a capacitive load.
4. This is the rated voltage for the following pins:
OUT
5. This is the rated voltage for the following pins:
FB, COMP, OVP2, RT
6. In case of R2A20133ASP (SOP): ja = 120°C/W
This value is a thing mounting on 40 40 1.6 [mm], a glas s epoxy board of wiring density 10%.
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Electrical Characteristics
(Ta = 25°C, VCC = 12 V, CS = 0.1 V, FB = COMP, OVP2 = 0 V, RRT = 200 k)
Item Symbol Min Typ Max Unit Test Conditions
UVLO turn-on threshold Vuvlh 11.2 12 12.8 V
UVLO turn-off threshold Vuvll 8.5 9.2 9.9 V
UVLO hysteresis Hysuvl 2.1 2.8 3.5 V
Standby current Istby — 130 250 A VCC = Vuvlh – 0.2 V
Supply
Operating current Icc — 1.8 2.6 mA
Feedback voltage Vfb 2.472 2.510 2.548 V FB-COMP short
Temperature stability dVfb — 80 — ppm/°C Ta = –40 to +125°C *1
Input bias current Ifb –0.40 –0.15 –0.05 A Measured pin: FB
Open loop gain Av — 65 — dB *1
Upper clamp voltage Vclamp-comp 3.65 4.10 4.3 V FB = 2.0 V
COMP: Open
Low voltage Vl-comp — 0.1 0.3 V FB = 3.0 V
COMP: Open
Source current1 Isrc-comp1 –13.5 –10 –6 A FB = 1.7 V
COMP = 2.5 V
Source current2 Isrc-comp2 Isrc-comp1
3.3 Isrc-comp1
3.0 Isrc-comp1
2.7
A FB = 1.5 V
COMP = 2.5 V
Sink current Isnk-comp 6 10 13.5 A FB = 3.5 V
COMP = 2.5 V
Error
amplifier
Transconductance gm 25 46 75 s FB = 2.45V 2.55 V
COMP = 2.5 V
RAMP offset voltage Voff_ramp — 1.0 — V *1
RAMP amplitude dVramp 2.90 3.1 3.3 V *2
RT
RT voltage V-rt 1.9 2.0 2.1 V
ZCD threshold voltage Vzcd –4 0 4 mV
Zero
current
detector Input bias current Ics –58 –42 –25 A Vcs = 0 V
Restart Restart time delay Tstart 75 150 330 s FB = 2.0 V,
COMP = 2.5 V
Off time
control Minimum off time Toff-min 1.0 1.4 1.8 s
Notes: *1 Design spec
*2 dVramp = Vclamp_comp – Voff_ramp
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Electrical Characteristics (cont.)
(Ta = 25°C, VCC = 12 V, CS = 0.1 V, FB = COMP, OVP2 = 0 V, RRT = 200 k)
Item Symbol Min Typ Max Unit Test Conditions
Rise time tr-out — 35 100 ns CL = 1000 pF
tr
90%
10%
Fall time tf-out — 35 100 ns CL = 1000 pF
tf
90%
10%
Vol1-out — 0.08 0.2 V Isink = 20 mA Out low voltage Vol2-out — 0.05 0.7 V Isink = 10 mA, VCC = 5 V
Out
Out high voltage Voh-out 11.5 11.8 — V Isource = –20 mA
Over
current
protection
OCP threshold voltage Vocp –0.63 –0.6 –0.57 V
Dynamic OVP threshold voltage Vdovp — Vfb
1.040 — V *1
Dynamic UVP threshold voltage Vduvp — Vfb
0.920 — V *1
Static OVP threshold voltage Vsovp Vfb
1.075 Vfb
1.090 Vfb
1.105 V
Static OVP hysteresis Hys-sovp 50 100 150 mV
FB low detect threshold voltage Vfblow 0.25 0.3 0.35 V
FB low detect hysteresis Hysfblow 0.16 0.20 0.24 V
OVP2 threshold voltage Vovp2 Vfb
1.075 Vfb
1.090 Vfb
1.105 V
Over &
Under
voltage
protection
OVP2 source current Isrc-ovp2 –0.40 –0.15 –0.05 A
Note: *1 Design spec
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Waveforms
1. Start-up
OUT
VREF GOOD
(Internal signal)
COMP
FB
0.5V (Vfblow + Hysfblow)
VREF
(Internal signal)
VCC 12V (Vuvlh)
5.02V (Vref)
3.6V
1.0V (Voff_ramp)
2. Shut-down
OUT
Normal operation
9.2V
(Vuvll)
VCC
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3. Gate Drive Output
RAMP
(Internal signal)
0V (Vzcd)
0V (Vzcd)
OUT
RAMP+1V
(Internal signal)
RAMP
(Internal signal)
RAMP+1V
(Internal signal)
COMP
IL
CS
0.44μs
0mA
Enlargement around Zero-current detection
COMP
OUT
IL
CS
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4. Overvoltage Protection (OVP)
VFB
OUT
COMP
Hys-sovp: 100mV
Vsovp: Vfb × 1.09V
OUT OFF
(Internal signal)
5. FB Low Detection
VFB
OUT
0.3V (Vfblow) 0.5V (Vfblow + Hysfblow)
FB LOW
(Internal signal)
COMP
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6. Overcurrent Protection (OCP)
0V
(Vzcd)
–0.6V
(Vocp)
COMP
CS
IL
OUT
RAMP
(Internal signal)
RAMP+1V
(Internal signal)
7. Off Time Control (Frequency Limiter )
0A
1.4μs
(Toff_min)
IL
ZCD_pulse
(Internal signal)
ZCD_mask
(Internal signal)
1.4μs
(Toff_min)
1.4μs
(Toff_min)
OUT
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8. Overvoltage Protection 2 (OVP2)
OVP2
9.2V
(Vuvll)
Vovp2: Vfb × 1.09V
VCC
OUT OFF 2
(Internal signal)
OUT
12V (Vuvlh)
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System Diagram
PFC OUT
(390V dc)
To
Q1 gate
1μ
AUX
0.022μ
0.047μ
200k
200k
100
1000p
GND
L1
220μ
(450V)
D1
+
6M
VRB1
6M
VRB2
CS
5
RT
2
VCC
8
OUT
7
GND
6
FB
1
COMP
3
OVP2
4
R2A20133A
1.0μ
From OUT
Q1
0.05
(5W)
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Package Dimensions
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
0.10
1.27
0.56
5.84 6.20
0.410.35
4.98
MaxNom
Min
4.80
3.993.81
Dimension in Millimeters
Symbol
Reference
1.73
0.890.640.41
3.94
1.47
0.250.150.10
0.49
0.250.200.19
5.99
8°0°
0.25
1.03
4.93
e
HE
L
A
D
E
A2
A1
bp
b1
c
x
y
Z
L1
c1
θ
Previous Code
JEITA Package Code RENESAS Code
PRSP0008DJ-A —
MASS[Typ.]
0.073gP-SOP8-3.94x4.93-1.27
c
Terminal cross section
(Ni/Pd/Au plating)
Detail F
L
58
4
F
*1
*2
*3
Mx
1
Index mark
S
S
y
A
D
e
Z
E
L
1
A
1
b
p
b
p
H
E
θ
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