8752 www.icst.com/products/hiperclocks.html REV. B MAY 4, 2001
1
Integrated
Circuit
Systems, Inc.
ICS8752
LOW SKEW 1-TO-8
L VCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
PRELIMINARY
BLOCK DIAGRAM PIN ASSIGNMENT
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
QB1
QB0
VDDO
VDDO
QA3
QA2
GND
DIV_SELB0
DIV_SELB1
DIV_SELA0
DIV_SELA1
MR/nOE
REF_CLK1
GND
FB_IN
VDDO
QA1
QA0
GND
REF_CLK2
VDDI
VDDA
CLK_SEL
VDDO
QB2
QB3
GND
GND
nc
PLL_SEL
VDDI
ICS8752
32-Lead LQFP
Y package
Top View
÷2
÷4
÷6
÷8
÷12
PLL
PHASE
DETECTOR
PLL_SEL
FB_IN
REF_CLK1
REF_CLK2
CLK_SEL
DIV_SELA1
DIV_SELA0
DIV_SELB1
DIV_SELB0
MR/nOE
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
0
11
0
00
01
10
11
00
01
10
11
VCO
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
GENERAL DESCRIPTION
The ICS8752 is a low voltage, low skew clock
generator and a member of the HiPerClockS™
family of High Performance Clock Solutions
from ICS. With output frequencies up to 240MHz
the ICS8752 is targeted for high performance
clock applications. Along with a fully integrated PLL the
ICS8752 contains frequency configurable outputs and an
external feedback input for regenerating clocks with “zero de-
lay”.
Dual clock inputs, REF_CLK1 and REF_CLK2, support
redundant clock applications. The CLK_SEL input determines
which reference clock is used. The output divider values of
Bank A and B are controlled by the DIV_SELA0:1, and
DIV_SELB0:1, respectively.
For test and system debug purposes the PLL_SEL input
allows the PLL to be bypassed. When HIGH the MR/nOE
input resets the internal dividers and forces the outputs to
the high impedance state.
The low impedance LVCMOS outputs of the ICS8752 are
designed to drive terminated transmission lines. The ef fec-
tive fanout of each output can be doubled by utilizing the
ability of each output to drive two series terminated trans-
mission lines.
FEATURES
•Fully integrated PLL
•8 L VCMOS outputs, 7Ω typical output impedance
•External feedback for ”zero delay” clock regeneration
•Output frequency up to 240MHz
•VCO range 220MHz to 480MHz
•Dual L VCMOS clock inputs for redundant clock applications
•L VCMOS control inputs
•Bank skew, tsk(b), 100ps
•Output skew , tsk(o), 150ps
•Multiple-frequency skew , tsk(w), 200ps
•Cycle-to-cycle jitter , tjit(cc), 100ps, typical
•PLL reference zero delay , t(Ø), ±150ps, typical
•Full 3.3V
•32 lead low-profile QFP (LQFP)
•7mm x 7mm x 1.4mm package body , 0.8mm lead pitch
•0°C to 70°C ambient operating temperature
•Functionally compatible with the MPC952 in some applications
HiPerClockS™
,&6