PRELIMINARY ICS8752 Integrated Circuit Systems, Inc. LOW SKEW 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER GENERAL DESCRIPTION FEATURES The ICS8752 is a low voltage, low skew clock generator and a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions from ICS. With output frequencies up to 240MHz the ICS8752 is targeted for high performance clock applications. Along with a fully integrated PLL the ICS8752 contains frequency configurable outputs and an external feedback input for regenerating clocks with "zero delay". * Fully integrated PLL ,&6 * 8 LVCMOS outputs, 7 typical output impedance * External feedback for "zero delay" clock regeneration * Output frequency up to 240MHz * VCO range 220MHz to 480MHz * Dual LVCMOS clock inputs for redundant clock applications * LVCMOS control inputs Dual clock inputs, REF_CLK1 and REF_CLK2, support redundant clock applications. The CLK_SEL input determines which reference clock is used. The output divider values of Bank A and B are controlled by the DIV_SELA0:1, and DIV_SELB0:1, respectively. * Bank skew, tsk(b), 100ps * Output skew, tsk(o), 150ps * Multiple-frequency skew, tsk(w), 200ps For test and system debug purposes the PLL_SEL input allows the PLL to be bypassed. When HIGH the MR/nOE input resets the internal dividers and forces the outputs to the high impedance state. * Cycle-to-cycle jitter, tjit(cc), 100ps, typical The low impedance LVCMOS outputs of the ICS8752 are designed to drive terminated transmission lines. The effective fanout of each output can be doubled by utilizing the ability of each output to drive two series terminated transmission lines. * 32 lead low-profile QFP (LQFP) BLOCK DIAGRAM PIN ASSIGNMENT * PLL reference zero delay, t(O), 150ps, typical * Full 3.3V * 7mm x 7mm x 1.4mm package body, 0.8mm lead pitch * 0C to 70C ambient operating temperature * Functionally compatible with the MPC952 in some applications 00 01 10 11 DIV_SELA1 DIV_SELA0 00 01 10 11 VDDO 0 /2 /4 /6 /8 /12 QB2 1 QB3 CLK_SEL VCO GND REF_CLK2 1 PHASE DETECTOR GND REF_CLK1 0 nc VDDI PLL FB_IN PLL_SEL PLL_SEL 32 31 30 29 28 27 26 25 QA0 DIV_SELB0 1 24 GND QA1 DIV_SELB1 2 23 QB1 QA2 DIV_SELA0 3 22 QB0 QA3 DIV_SELA1 4 21 VDDO MR/nOE 5 20 VDDO REF_CLK1 6 19 QA3 GND 7 18 QA2 FB_IN 8 17 GND QB0 QB1 DIV_SELB1 QB2 DIV_SELB0 QB3 ICS8752 9 10 11 12 13 14 15 16 VDDO QA1 QA0 GND REF_CLK2 VDDI VDDA CLK_SEL 32-Lead LQFP Y package Top View MR/nOE The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 8752 www.icst.com/products/hiperclocks.html 1 REV. B MAY 4, 2001 PRELIMINARY ICS8752 Integrated Circuit Systems, Inc. LOW SKEW 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER TABLE 1. PIN DESCRIPTIONS Number 1, 2 3, 4 Name DIV_SELB0, DIV_SELB1 DIV_SELA0, DIV_SELA1 Type Input Input Description Determines output divider values for bank B as described in Table 3. Pulldown LVCMOS / LVTTL interface levels. Determines output divider values for bank A as described in Table 3. Pulldown LVCMOS / LVTTL interface levels. When HIGH, resets dividers and forces output into high impedance state. Pulldown LVCMOS / LVTTL interface levels. 5 MR/nOE Input 6 REF_CLK1 Input 7, 13 17, 24, 28, 29 GND Power 8 FB_IN Input 9 CLK_SEL Input 10 VDDA Power PLL power supply pin. Connect to 3.3V. 11, 32 VDDI Power Input and core power supply pin. Connect to 3.3V. Pulldown Reference clock input. LVCMOS interface levels. Ground pin. Connect to ground. Feedback input to phase detector for regenerating clocks with "zero delay". LVCMOS / LVTTL interface levels. Selects between REF_CLK1 or REF_CLK2 as phase detector reference. Pulldown When LOW selects REF_CLK1. When HIGH selects REF_CLK2. LVCMOS / LVTTL interface levels. Pulldown 12 REF_CLK2 Input 14, 15, 18, 19 16, 20, 21, 25 22, 23, 26, 27 QA0, QA1, QA2, QA3 Output Bank A clock outputs.7 typical output impedance. LVCMOS interface levels. VDDO Power Output power supply pins. Connect to 3.3V. QB0, QB1, QB2, QB3 Output Bank B clock outputs.7 typical output impedance. LVCMOS interface levels. 30 nc Unused Unused pin. 31 PLL_SEL Input 32 VDDI Power 8752 Pulldown Reference clock input. LVCMOS interface levels. Pullup Selects between the PLL and the reference clock as the input to the dividers. When HIGH select PLL. When LOW selects reference clock. LVCMOS / LVTTL interface levels. Input power supply pin. Connect to 3.3V. www.icst.com/products/hiperclocks.html 2 REV. B MAY 4, 2001 PRELIMINARY ICS8752 Integrated Circuit Systems, Inc. LOW SKEW 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Input Capacitance CIN RPULLUP RPULLDOWN CPD ROUT Minimum Typical REF_CLK1, REF_CLK2 PLL_SEL, FB_IN, CLK_SEL DIV_SELA1, DIV_SELA0, DIV_SELB1, DIV_SELB0 Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance VDDA, VDDI, VDDO = 3.47V Maximum Units TBD pF TBD pF 51 K 51 K TBD pF 7 TABLE 3. CONTROL INPUTS FUNCTION TABLE Inputs DIV_ SELA1 X Outputs DIV_ SELA0 X DIV_ SELB1 X DIV_ SELB0 X MR/nOE PLL_SEL CLK_SEL QAx QBx 1 X X Hi-Z Hi-Z 0 1 X 0 0 0 0 1 X 0 1 0 0 fVCO/2 fVCO/4 1 fVCO/4 fVCO/6 0 1 X 1 0 1 0 fVCO/6 fVCO/8 0 1 X 1 1 1 1 fVCO/8 fVCO/12 0 0 0 0 0 0 0 fREF_CLK1/2 fREF_CLK1/4 0 0 0 0 1 0 1 fREF_CLK1/4 fREF_CLK1/6 0 0 0 1 0 1 0 fREF_CLK1/6 fREF_CLK1/8 0 0 0 1 1 1 1 fREF_CLK1/8 fREF_CLK1/12 0 0 1 0 0 0 0 fREF_CLK2/2 fREF_CLK2/4 0 0 1 0 1 0 1 fREF_CLK2/4 fREF_CLK2/6 0 0 1 1 0 1 0 fREF_CLK2/6 fREF_CLK2/8 0 0 1 1 1 1 1 fREF_CLK2/8 fREF_CLK2/12 NOTE: For normal operation MR/nOE is LOW. When MR/nOE is HIGH all ouputs are disabled. 8752 www.icst.com/products/hiperclocks.html 3 REV. B MAY 4, 2001 PRELIMINARY ICS8752 Integrated Circuit Systems, Inc. LOW SKEW 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER TABLE 4A. QA OUTPUT FREQUENCY W/FB_IN = QB INPUTS FB_IN QB QB QB QB DIV_SELB1 0 0 1 1 DIV_SELB0 0 1 0 1 QB OUPUT DIVIDER MODE /4 /6 /8 /12 OUTPUT REF_CLK1, REF_CLK2 (MHz) MIN MAX 62.5 41.67 31.25 20.83 125 83.33 62.5 41.67 DIV_SELA1 DIV_SELA0 QA OUPUT DIVIDER MODE 0 0 /2 2 0 1 /4 1 1 0 /6 0.667 1 1 /8 0.5 0 0 /2 3 0 1 /4 1.5 1 0 /6 1 1 1 /8 0.75 0 0 /2 4 0 1 /4 2 1 0 /6 1.33 1 1 /8 1 0 1 /2 6 0 1 /4 3 1 0 /6 2 1 /8 1.5 1 NOTE 1: NOTE 1: VCO frequency range is 250MHz to 500MHz. NOTE 2: QA output frequency equal to reference clock frequency times the multiplier ; QB output frequency equal to reference clock. 8752 www.icst.com/products/hiperclocks.html 4 QA Multiplier (NOTE 1) REV. B MAY 4, 2001 PRELIMINARY ICS8752 Integrated Circuit Systems, Inc. LOW SKEW 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER TABLE 4B. QB OUTPUT FREQUENCY W/FB_IN = QA FB_IN QA QA QA QA DIV_SELA1 DIV_SELA0 0 0 1 1 INPUTS REF_CLK1, QA REF_CLK2 OUPUT (MHz) DIVIDER MODE MIN MAX 0 1 0 1 /2 /4 /6 /8 125 62.5 41.67 31.25 250 125 83.33 62.5 OUTPUT DIV_SELB1 DIV_SELB0 QB OUPUT DIVIDER MODE 0 0 /4 0.5 0 1 /6 0.333 1 0 /8 0.25 1 1 /12 0.083 0 0 /4 1 0 1 /6 0.667 1 0 /8 0.5 1 1 /12 0.333 0 0 /4 1.5 0 1 /6 1 1 0 /8 0.75 1 1 /12 0.5 QB Multiplier (NOTE 2) 0 1 /4 2 0 1 /6 1.333 1 0 /8 1 1 /12 0.667 1 NOTE 1: VCO frequency range is 250MHz to 500MHz. NOTE 2: QB output frequency equal to reference clock frequency times the multiplier ; QA output frequency equal to reference clock. TABLE 5. PLL INPUT REFERENCE CHARACTERISTICS, VDDI=VDDA=3.3V5%, TA=0C TO 70C Symbol Parameter fREF Input Reference Frequency tR Input Rise Time tF Input Fall Time tDC Input Reference Duty Cycle 8752 Test Conditions Minimum Maximum Units 240 MHz Measured at 20% to 80% points TBD ns Measured at 20% to 80% point TBD ns TBD % 20 TBD www.icst.com/products/hiperclocks.html 5 Typical REV. B MAY 4, 2001 PRELIMINARY ICS8752 Integrated Circuit Systems, Inc. LOW SKEW 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage 4.6V Inputs -0.5V to VDD+0.5 V Outputs -0.5V to VDD+0.5V Ambient Operating Temperature 0C to 70C Storage Temperature -65C to 150C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 6A. POWER SUPPLY DC CHARACTERISTICS, VDDI=VDDA=VDDO=3.3V5%, TA=0C TO 70C Symbol Parameter Minimum Typical Maximum Units VDDI Input Power Supply Voltage Test Conditions 3.135 3.3 3.465 V VDDA Analog Power Supply Voltage 3.135 3.3 3.465 V VDDO Output Power Supply Voltage 3.135 3.3 3.465 V IDD Input Power Supply Current 70 mA TABLE 6B. LVCMOS/LVTTL DC CHARACTERISTICS, VDDI=VDDA=VDDO=3.3V5%, TA=0C TO 70C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH IIL Input High Current Input Low Current VOH Output High Voltage VOL Output Low Voltage 8752 Test Conditions REF_CLK1, REF_CLK2 FB_IN, CLK_SEL, DIV_SELA1, DIV_SELA0, DIV_SELB1, DIV_SELB0, MR/nOE PLL_SEL REF_CLK1, REF_CLK2 FB_IN, CLK_SEL, DIV_SELA1, DIV_SELA0, DIV_SELB1, DIV_SELB0, MR/nOE PLL_SEL Minimum Maximum Units 2 Typical 3.765 V -0.3 0.8 V VIN = 3.465V 150 A VIN = 3.465V 5 A VIN = 0V -5 A VIN = 0V VDDO = 3.135V IOH = -36mA VDDO = 3.135V IOL = 36mA -150 A 2.6 V www.icst.com/products/hiperclocks.html 6 0.5 V REV. B MAY 4, 2001 PRELIMINARY Integrated Circuit Systems, Inc. ICS8752 LOW SKEW 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER TABLE 7. AC CHARACTERISTICS, VDDI=VDDA=VDDO=3.3V5%, TA=0C TO 70C Symbol fMAX fVCO Parameter Maximum Output Frequency Propagation Delay, Low-to-High tpHL Propagation Delay, High-to-Low tsk(b) tsk(o) Minimum Maximum Units /2 240 MHz /4 120 MHz /6 80 MHz /8 60 MHz /12 40 MHz 240 480 MHz TBD TBD ns TBD TBD ns PLL VCO Lock Range tpLH t(O) Test Conditions PLL Reference Zero Delay; NOTE 2 Bank A Bank Skew; NOTE 3 Bank B Output Skew; NOTE 4 PLL_SEL=0V, 0MHz f 240MHz PLL_SEL=0V, 0MHz f 240MHz PLL_SEL=3.3V, fREF=TBD, fVCO=TBD Typical 150 Measured on rising edge at VDDO/2 Measured on rising edge at VDDO/2 Measured on rising edge at VDDO/2 ps 75 ps 100 ps 150 ps 200 ps tjit(cc) Multiple Frequency Skew; NOTE 5 Cycle-to-Cycle Jitter ; NOTE 6 tjit(O) Phase Jitter tL PLL Lock Time 1 mS tR Output Rise Time 20% to 80% 300 800 ps tF Output Fall Time 20% to 80% Output Pulse Width 800 tCYCLE/2 +500 4.35 ps tPW 300 tCYCLE/2 -500 3.65 ps TBD ns tsk(w) 0MHz f 240MHz f = 120MHz tEN Output Enable Time 100 ps 150 ps tCYCLE/2 4.0 ns tDIS Output Disable Time TBD ns NOTE 1: All parameters measured at fMAX unless noted otherwise. All outputs terminated with 50 to VDDO/2. NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 4: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions. NOTE 5: Defined as skew across banks of outputs operating at different frequency with the same supply voltages and equal load conditions. NOTE 6: Defined as the variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent pairs of cycles. 8752 www.icst.com/products/hiperclocks.html 7 REV. B MAY 4, 2001 PRELIMINARY ICS8752 Integrated Circuit Systems, Inc. LOW SKEW 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER PACKAGE OUTLINE - Y SUFFIX D D2 E 25 24 32 1 2 3 L E1 E2 N 8 17 16 9 e A D1 A2 -Cccc C b A1 SEATING PLANE c TABLE 8. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. e 0.80 BASIC L 0.45 0.60 0.75 q 0 -- 7 ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 8752 www.icst.com/products/hiperclocks.html 8 REV. B MAY 4, 2001 PRELIMINARY ICS8752 Integrated Circuit Systems, Inc. LOW SKEW 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS8752BY ICS8752BYT ICS8752BY 32 Lead LQFP 250 per tray 0C to 70C ICS8752BY 32 Lead LQFP on Tape and Reel 1000 0C to 70C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8752 www.icst.com/products/hiperclocks.html 9 REV. B MAY 4, 2001