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AN1419.0
ISL282X8MSOPEVAL1Z ISL282X8SOICEVAL1Z
Evaluation Board User’s Guide
Introduction
The ISL282X8MSOPEVAL1Z and ISL282X8SOICEVAL1Z
evaluation board are design platforms containing all the
circuitry needed to characterize critical performance
parameters of the ISL282X8 operational amplifiers in both
MSOP-8 and SOIC-8 packages, using a variety of user
defined test circuits.
The ISL28238 and ISL28248 high-speed operational
amplifiers feature low power consumption, while ISL28258
and ISL28268 operational amplifiers feature ultra-low power
consumption. All op amps have rail-to-rail output drive
capability and are designed to operate with a single lithiu m
cell or two Ni_Cd batteries.
Reference Documents
• ISL28238 Data Sheet, FN6336
• ISL28248 Data Sheet, FN6337
• ISL28258 Data Sheet, FN6377
• ISL28268 Data Sheet, FN6378
Evaluation Board Key Features
The ISL282xEV AL1Z is designed to enable the IC to operate
from a single supply, +2.4VDC to +5.5VDC or from split
supplies, ±1.2VDC to ±2.75V. The board is configured for a
dual op amp connected for differential input with a closed
loop gain of 10. A single external reference voltage (VREF)
pin and provisions for a user-selectable voltage divider-filter
are included.
Power Supplies
External power connections are made through the +V, -V,
VREF and Ground connections on the evaluation board.
User-selectable SMA edge connectors are also provided for
+V and -V. For single supply operation, the -V and Ground
pins are tied together to the power supply negative terminal.
For split supplies +V and -V terminals connect to their
respective power supply terminals. De-coupling capacitors
C2 and C4 connect to their respective supplies through R16
and R31 0Ω resistors. These resistors are 0Ω but can be
changed by the user to provide additional power supply
filtering, or to reduce the voltage rate-of-rise to less than
±1V/µS. Two add itional capacitors, C3 and C5 are
connected close to the part to filter out high frequency noise.
Anti-reverse diode D1 protects the circuit in the case of
accidental polarity reversal (see Figure 1).
Amplifier Configuration
The schematic of 1/2 of the op amp with the components
supplied is shown in Figure 2. The circuit implements a
dif f e rential input amp with a closed loop gain of 10. The
circuit can operate from a single supply or from dual
supplies. The VREF pin must be connected to ground to
J11
C5
R31
R16
D1
C2 C4
C3
J14
J12 J13
J6
J8
0.01µF0.01µF
4.7µF4.7µF
0
0
VREF
V+V-
FIGURE 1. POWER SUPPYLY CIRCUIT
RF
100kΩ
IN-
IN+
VREF
IN -
IN +
GND
REF+
VOUT
ISL282X8 (1/2)
VP
V-
0Ω
VM
VCM
IN-
IN+
VREF
V+
RIN-
10kΩ
RIN+
10kΩ
-
+
100kΩ
RL
10kΩ
FIGURE 2. BASIC AMPLIFIER CONFIGURATION
Application Note August 28, 2008
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2AN1419.0
August 28, 2008
establish a ground referenced input for dual supply
operation, or can be externally set to any reference level for
single supply operation. VREF should not be left floating.
User-selectable Options
Component pads are included to enable a variety of
user-selectable circuits to be added to the amplifier VREF,
inputs, outputs, and the amplifier feedback loops. The Inputs
(see Figure 3) have additional resistor and capacitor, and
jumper placements for loading and/or measurement of
frequency sensitive parameters.
The outputs (see Figure 4) have a 10k Ω load resistor to
ground and have additional resistor and capacitor
placements for loading.
NOTE: Operational amplifiers are sensitive to output
capacitance and may oscillate. In the event of oscillation,
reduce output capacitance by using shorter cables, or add a
resistor in series with the output.
FIGURE 3. INPUT STAGE FIGURE 4. OUTPUT STAGE
IN- OUTNODEIN+
J18
J20
J19
J17
C1
R5
R4
J2
J1 R1
R6
R17
R2 R14
R3
R18R15
R12R10
R13R11
DNP DNP
DNP
DNP
DNP
DNP
DNP
OPEN
DNP
DNP
10k 100k
100k
10k
0
VREF
TO OUTPUT
TO IN+
TO IN-
R26
C6
C8
R28
10k
OPEN
OPEN
0
FROM
OUTPUT
TABLE 1. ISL282X8EVAL1Z COMPONENTS PARTS LIST
DEVICE # DESCRIPTION COMMENTS
C2, C4 CAP-TANTALUM, SMD, D, 4.7µF, 50V, 10% LOW ESR, ROHS Power Supply Decoupling
C3, C5 CAP, SMD, 0603,1µF, 25V,10%, X7R, ROHS Power Supply Decoupling
C1, C6 to C10 CAP, SMD, 0603, DNP-Place Holder, ROHS User-Selectable Capacitors - Not Populated
D1 Diode-Schottky Barrier, SMD, SOT-23, 3P, 40V, ROHS Reverse Power Protection
U1 (ISL28238FUZ) IC-5 MHz RRIO OP AMP, 8P, MSOP, ROHS
U1 (ISL28238FBZ) IC-5 MHz RRIO OP AMP, 8P, SOIC, ROHS
U1 (ISL28248FUZ) IC-5 MHz RRIO OP AMP, 8P, MSOP, ROHS
U1 (ISL28248FBZ) IC-5 MHz RRIO OP AMP, 8P, SOIC, ROHS
U1 (ISL28258FUZ) IC-39µA RRIO OP AMP, 8P, MSOP, ROHS
U1 (ISL28258FBZ) IC-39µA RRIO OP AMP, 8P, SOIC, ROHS
U1 (ISL28268FUZ) IC-39µA RRIO OP AMP, 8P, MSOP, ROHS
U1 (ISL28268FBZ) IC-39µA RRIO OP AMP, 8P, SOIC, ROHS
R30, R32, R34 to R36 RES, SMD, 0603, 0.1%, MF, DNP-PLACE HOLDER User-Selectable Resistors - Not Populated
R4, R16, R25 to R27, R31 RES, SMD, 0603, 0Ω, 1/10W, TF, ROHS 0Ω User-Selectable Resistors
R11, R14, R21, R24, R28, R29 RES, SMD, 0603, 10k, 1/10W, 1%, TF, ROHS Gain and Other User-Selectable Resistors
R13, R18, R19, R23 RES, SMD, 0603, 100k, 1/10W, 1%, TF, ROHS Gain Resistors
Application Note 1419
3AN1419.0
August 28, 2008
Application Note 1419
ISL282X8EVAL1Z Top Vi ew (SOIC Shown)
4
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to
verify that the A pplicat i on Note or Technica l Brief is cur rent befor e pr oceedi ng.
For information regarding Intersil Corporation and its products, see www.intersil.com
AN1419.0
August 28, 2008
Application Note 1419
ISL282X8EVAL1Z Schematic Diagram
NODEIN- IN+OUTNODE IN-OUTIN+
J11
C5
R31
R16
J23
J18
J24
J22
J21
J20
J19
J17
R36
R32 R34
R35
R30
32
1
D1
R20
C10
R8
R7
R5
R4 R24
C2 C4
C3
J2
J1
J3
J4
J14
J12
J13
J6
J8
R26
R27
C7
C6
C8 C9
R1
R29
R25
R23
R6
R17
R2
R28
R3
R13R11
8
7
6
5
4
3
2
1U1
0.01µF0.01µF
4.7µF4.7µF
0
SOIC 8
0
DNP
0
DNP
OPEN
DNP
OPEN
OPEN
OPEN
0
DNP
DNP
DNP
DNP
OPEN
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
OPEN
DNP
DNP
10k 10k
100k 100k
100k 100k
10k 10k
0
0
DNP
VREF
VREF
V+V-
5
6
7
8
3
4
1
2
MSOP 8
J15
J16
