ASMP5P2304A August 2004 rev 2.0 3.3 V Zero Delay Buffer Features Zero input - output propagation delay, adjustable by capacitive load on FBK input. Multiple configurations - Refer "ASM5P2304A Configurations Table". Input frequency range: 10MHz to 133MHz Multiple low-skew outputs. Output-output skew less than 200 ps. Device-device skew less than 500 ps. Two banks of four outputs. Less than 200 ps cycle-to-cycle jitter (-1, -1H, -5H). Available in space saving, 8-pin 150-mil SOIC packages and standard TSSOP. 3.3V operation. Advanced 0.35 CMOS technology. Industrial temperature available. than 250ps, and the output-to-output skew is guaranteed to be less than 200ps. The ASM5P2304A has two banks of two outputs each. Multiple ASM5P2304A devices can accept the same input clock and distribute it. In this case the skew between the outputs of the two devices is guaranteed to be less than 500ps. The ASM5P2304A is available in two different configurations (Refer "ASM5P2304A Configurations Table). The ASM5P2304A-1 is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. The ASM5P2304A-1H is the high-drive version of the -1 and the rise and fall times on this device are much faster. Functional Description ASM5P2304A is a versatile, 3.3V zero-delay buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom and other high-performance applications. It is available in a 8-pin package. The part has an on-chip PLL which locks to an input clock presented on the REF pin. The PLL feedback is required to be driven to FBK pin, and can be obtained from one of the outputs. The The ASM5P2304A-2 allows the user to obtain Ref, 1/2 X and 2X frequencies on each output bank. The exact configuration and output frequencies depend on which output drives the feedback pin. The ASM5P2304A-5H is a high-drive version with REF/2 on both banks input-to-output propagation delay is guaranteed to be less Block Diagram FBK CLKA1 REF PLL CLKA2 /2 Extra Divider (-2) CLKB1 CLKB2 Alliance Semiconductor 2575, Augustine Drive Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com Notice: The information in this document is subject to change without notice. ASM5P2304A August 2004 rev 2.0 ASM5P2304A Configurations Device Feedback From Bank A Frequency Bank B Frequency ASM5P2304A-1 Bank A or Bank B Reference Reference ASM5P2304A-1H Bank A or Bank B Reference Reference ASM5P2304A-2 Bank A Reference Reference /2 ASM5P2304A-2 Bank B 2 X Reference Reference ASM5P2304A-5H Bank A or Bank B Reference /2 Reference /2 Zero Delay and Skew Control For applications requiring zero input-output delay, all outputs must be equally loaded. 1500 REF-Input to CLKA/CLKB Delay (ps) 1000 500 0 -30 -25 -20 -15 -10 -5 5 0 10 15 20 25 30 -500 -1000 -1500 Output Load Difference: FBK Load - CLKA/CLKB Load (pF) REF Input to CLKA/CLKB Delay Vs Difference in Loading between FBK pin and CLKA/CLKB pins To close the feedback loop of the ASM5P2304A, the FBK pin can be driven from any of the four available output pins. The output driving the FBK pin will be driving a total load of 7 pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust the input For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. If input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and remaining outputs. For zero output-output skew, be sure to load outputs equally. output delay. This is shown in the above graph. 3.3 Zero Delay Buffer Notice: The information in this document is subject to change without notice. 2 of 13 ASM5P2304A August 2004 rev 2.0 Pin Configuration REF 1 CLKA1 2 CLKA2 3 GND 4 ASM5P2304A 8 FBK 7 V 6 CLKB2 DD 5 CLKB1 Pin Description for ASM5P2304A Pin # Pin Name Description 1 REF1 2 CLKA12 Buffered clock output, bank A 3 CLKA22 Buffered clock output, bank A 4 GND 5 CLKB12 Buffered clock output, bank B 6 CLKB2 2 Buffered clock output, bank B 7 VDD 3.3V supply 8 FBK PLL feedback input Input reference frequency, 5V tolerant input Ground Notes: 1. Weak pull-down. 2. Weak pull-down on all outputs. 3.3 Zero Delay Buffer Notice: The information in this document is subject to change without notice. 3 of 13 ASM5P2304A August 2004 rev 2.0 Absolute Maximum Ratings Parameter Min Max Unit Supply Voltage to Ground Potential -0.5 +7.0 V DC Input Voltage (Except REF) -0.5 VDD + 0.5 V DC Input Voltage (REF) -0.5 7 V Storage Temperature -65 +150 uC Max. Soldering Temperature (10 sec) 260 uC Junction Temperature 150 uC >2000 V Static Discharge Voltage (per MIL-STD-883, Method 3015) Note: These are stress ratings only and functional usage is not implied. Exposure to absolute maximum ratings for prolonged periods can affect device reliability. Operating Conditions for ASM5P2304A Commercial Temperature Devices Parameter Description Min Max Unit 3.0 3.6 V 0 70 uC VDD Supply Voltage TA Operating Temperature (Ambient Temperature) CL Load Capacitance, below 100 MHz 30 pF CL Load Capacitance, from 100 MHz to 133 MHz 15 pF CIN Input Capacitance3 7 pF Note: 3. Applies to both Ref Clock and FBK. 3.3 Zero Delay Buffer Notice: The information in this document is subject to change without notice. 4 of 13 ASM5P2304A August 2004 rev 2.0 Electrical Characteristics Parameter for ASM5P2304A Commercial Temperature Devices Description Test Conditions Min Max Unit 0.8 V VIL Input LOW Voltage VIH Input HIGH Voltage IIL Input LOW Current VIN = 0V 50.0 A IIH Input HIGH Current VIN = VDD 100.0 A VOL Output LOW Voltage 4 0.4 V VOH Output HIGH Voltage 4 2.0 IOL = 8mA (-1, -2) IOH = 12mA (-1H, -5H) IOL = -8mA (-1, -2) IOH = -12mA (-1H, -5H) 2.4 Unloaded outputs 100MHz REF, Select inputs at VDD or GND IDD Supply Current V Unloaded outputs, 66MHz REF (-1, -2) Unloaded outputs, 33MHz REF (-1, -2) V TBD TBD TBD TBD Note: 4. Parameter is guaranteed by design and characterization. Not 100% tested in production. 3.3 Zero Delay Buffer Notice: The information in this document is subject to change without notice. 5 of 13 mA ASM5P2304A August 2004 rev 2.0 Switching Characteristics for ASM5P2304A Commercial Temperature Devices Paramete r Description Test Conditions Min Typ Max Unit t1 Output Frequency 30-pF load, All devices 10 100 MHz t1 Output Frequency 20-pF load, -1H, -5H devices 10 133.3 MHz t1 Output Frequency 15-pF load, -1, -2 devices 10 133.3 MHz 4 Duty Cycle = (t2 / t1) * 100 (-1, -2, -1H, -5H) Measured at 1.4V, FOUT = 66.66 MHz 30-pF load 40.0 50.0 60.0 % Measured at 1.4V, FOUT = <50 MHz 15-pF load 45.0 50.0 55.0 % Measured between 0.8V and 2.0V 30-pF load 2.20 ns Measured between 0.8V and 2.0V 15-pF load 1.50 ns Measured between 0.8V and 2.0V 30-pF load 1.50 ns Measured between 2.0V and 0.8V 30-pF load 2.20 ns Measured between 2.0V and 0.8V 15-pF load 1.50 ns Measured between 2.0V and 0.8V 30-pF load 1.25 ns All outputs equally loaded 200 Output-to-output skew (-1H, -5H) All outputs equally loaded 200 Output bank A -to- output bank B skew (-1, 5H) All outputs equally loaded 200 All outputs equally loaded 400 4 Duty Cycle = (t2 / t1) * 100 (-1, -2,-1H, -5H) Output Rise Time (-1, -2) 4 t3 Output Rise Time (-1, -2) 4 t3 Output Rise Time (-1H, -5H) 4 t3 Output Fall Time (-1, -2) 4 t4 Output Fall Time (-1, -2) 4 t4 Output Fall Time (-1H, -5H) 4 t4 Output-to-output skew on same bank (-1, -2) t5 4 ps Output bank A to output bank b skew (-2) t6 Delay, REF Rising Edge to FBK Rising Edge t7 Device-to-Device Skew t8 Output Slew Rate tJ tJ tLOCK Cycle-to-cycle jitter (-2,) PLL Lock Time 4 Measured at VDD /2 0 250 ps Measured at VDD/2 on the FBK pins of the device 0 500 ps Measured between 0.8V and 2.0V using Test Circuit #2 4 Cycle-to-cycle jitter (-1, -1H, -5H) 4 3 1 V/ns Measured at 66.67 MHz, loaded outputs, 15 pF load 175 Measured at 66.67 MHz, loaded outputs, 30 pF load 200 Measured at 133.3 MHz, loaded outputs, 15 pF load 100 Measured at 66.67 MHz, loaded outputs, 30pF load 400 Measured at 66.67 MHz, loaded outputs, 15 pF load 375 Stable power supply, valid clock presented on REF and FBK pins 1.0 4 4 3.3 Zero Delay Buffer Notice: The information in this document is subject to change without notice. ps ps 6 of 13 ms ASM5P2304A August 2004 rev 2.0 Operating Conditions for ASM5I2304A Industrial Temperature Devices Parameter Description Min Max Unit VDD Supply Voltage 3.0 3.6 V TA Operating Temperature (Ambient Temperature) -40 85 uC CL Load Capacitance, below 100 MHz 30 pF CL Load Capacitance, from 100 MHz to 133 MHz 15 pF CIN Input Capacitance3 7 pF Electrical Characteristics for ASM5I2304A Industrial Temperature Devices Parameter Description Test Conditions Min Max Unit 0.8 V VIL Input LOW Voltage VIH Input HIGH Voltage IIL Input LOW Current VIN = 0V 50.0 A IIH Input HIGH Current VIN = VDD 100.0 A VOL Output LOW Voltage 4 0.4 V VOH Output HIGH Voltage 4 2.0 IOL = 8mA (-1, -2) IOH = 12mA (-1H, -5H) IOL = -8mA (-1, -2) IOH = -12mA (-1H, -5H) Unloaded outputs 100MHz REF, Select inputs at VDD or GND IDD Supply Current Unloaded outputs, 66MHz REF (-1, -2) Unloaded outputs, 33MHz REF (-1, -2) 3.3 Zero Delay Buffer Notice: The information in this document is subject to change without notice. V 2.4 V TBD TBD TBD TBD 7 of 13 mA ASM5P2304A August 2004 rev 2.0 Switching Characteristics for ASM5I2304A Industrial Temperature Devices All parameters are specified with loaded outputs Parameter Description Test Conditions Min Typ Max Unit t1 Output Frequency 30-pF load, All devices 10 100 MHz t1 Output Frequency 20-pF load, -1H, -5H devices 10 133.3 MHz t1 Output Frequency 15-pF load, -1 and -2 devices 10 133.3 MHz 4 Duty Cycle = (t2 / t1) * 100 (-1, -2, -1H, -5H) Measured at 1.4V, FOUT = <66.66 MHz 30-pF load 40.0 50.0 60.0 % Measured at 1.4V, FOUT = <50 MHz 15-pF load 45.0 50.0 55.0 % Measured between 0.8V and 2.0V 30-pF load 2.50 ns Measured between 0.8V and 2.0V 15-pF load 1.50 ns Measured between 0.8V and 2.0V 30-pF load 1.50 ns Measured between 2.0V and 0.8V 30-pF load 2.50 ns Measured between 2.0V and 0.8V 15-pF load 1.50 ns Measured between 2.0V and 0.8V 30-pF load 1.25 ns All outputs equally loaded 200 Output-to-output skew (-1H, -5H) All outputs equally loaded 200 Output bank A -to- output bank B skew (-1, -5H) All outputs equally loaded 200 Output bank A -to- output bank B skew (-2) All outputs equally loaded 400 4 Duty Cycle = (t2 / t1) * 100 (-1, -2, -1H, -5H) Output Rise Time (-1, -2) 4 t3 Output Rise Time (-1, -2) 4 t3 Output Rise Time (-1H, -5H) 4 t3 Output Fall Time (-1, -2) 4 t4 Output Fall Time (-1, -2) 4 t4 Output Fall Time (-1H, -5H) 4 t4 Output-to-output skew on same bank (-1, -2) t5 t6 Delay, REF Rising Edge to FBK Rising Edge t7 Device-to-Device Skew t8 Output Slew Rate tJ tJ tLOCK Cycle-to-cycle jitter (-2) PLL Lock Time 4 4 ps Measured at VDD /2 0 250 ps Measured at VDD/2 on the FBK pins of the device 0 500 ps Measured between 0.8V and 2.0V using Test Circuit #2 4 Cycle-to-cycle jitter (-1, -1H, -5H) 4 4 1 V/ns Measured at 66.67 MHz, loaded outputs, 15 pF load 180 Measured at 66.67 MHz, loaded outputs, 30 pF load 200 Measured at 133.3 MHz, loaded outputs, 15 pF load 100 Measured at 66.67 MHz, loaded outputs, 30pF load 400 Measured at 66.67 MHz, loaded outputs, 15 pF load 380 Stable power supply, valid clock presented on REF and FBK pins 1.0 4 4 ps ps 3.3 Zero Delay Buffer Notice: The information in this document is subject to change without notice. 8 of 13 ms ASM5P2304A August 2004 rev 2.0 Switching Waveforms Duty Cycle Timing t1 t2 1.4 V 1.4 V 1.4 V All Outputs Rise/Fall Time 2.0 V OUTPUT 2.0 V 0.8 V 0.8 V 3.3 V 0V t4 t3 Output - Output Skew 1.4 V OUTPUT 1.4 V OUTPUT t5 Input - Output Propagation Delay /2 V DD INPUT V /2 V /2 DD OUTPUT t6 Device - Device Skew V /2 DD FBK, Device 1 FBK, Device 2 DD t7 3.3 Zero Delay Buffer Notice: The information in this document is subject to change without notice. 9 of 13 ASM5P2304A August 2004 rev 2.0 Test Circuits Test Circuit #2 Test Circuit #1 V V DD OUTPUTS 0.1 yF 1k DD OUTPUTS 0.1 yF 1k C LOAD V 0.1 yF V DD GND GND 0.1 yF 10 pF DD GND GND For parameter 8t (output slew rate) on -1H devices 3.3 Zero Delay Buffer Notice: The information in this document is subject to change without notice. 10 of 13 ASM5P2304A August 2004 rev 2.0 Package Information: 8-lead (150 Mil) Molded SOIC H E D A e D A1 C L B Symbo Dimensions in inches Dimensions in millimeters l Min Max Min Max A 0.053 0.069 1.35 1.75 A1 0.004 0.010 0.10 0.25 B 0.013 0.022 0.33 0.53 C 0.007 0.012 0.18 0.27 D 0.188 0.197 4.78 5.00 E 0.150 0.158 3.80 4.01 H 0.228 0.244 5.80 6.20 e L 0.050 BSC 1.27 BSC 0.016 0.035 0.40 0.89 0u 8u 0u 8u 3.3 Zero Delay Buffer Notice: The information in this document is subject to change without notice. 11 of 13 ASM5P2304A August 2004 rev 2.0 Ordering Code Package Type Operating Range ASM5P2304A-1-08-SR 8-pin 150-mil SOIC-TAPE & REEL Commercial ASM5P2304A-1-08-ST 8-pin 150-mil SOIC-TUBE Commercial ASM5I2304A-1-08-SR 8-pin 150-mil SOIC-TAPE & REEL Industrial ASM5I2304A-1-08-ST 8-pin 150-mil SOIC-TUBE Industrial ASM5P2304A-1H-08-SR 8-pin 150-mil SOIC-TAPE & REEL Commercial ASM5P2304A-1H-08-ST 8-pin 150-mil SOIC-TUBE Commercial ASM5I2304A-1H-08-SR 8-pin 150-mil SOIC-TAPE & REEL Industrial ASM5I2304A-1H-08-ST 8-pin 150-mil SOIC-TUBE Industrial ASM5P2304A-2-08-SR 8-pin 150-mil SOIC-TAPE & REEL Commercial ASM5P2304A-2-08-ST 8-pin 150-mil SOIC-TUBE Commercial ASM5I2304A-2-08-SR 8-pin 150-mil SOIC-TAPE & REEL Industrial ASM5I2304A-2-08-ST 8-pin 150-mil SOIC-TUBE Industrial ASM5P2304A-5H-08-SR 8-pin 150-mil SOIC-TAPE & REEL Commercial ASM5P2304A-5H-08-ST 8-pin 150-mil SOIC-TUBE Commercial ASM5I2304A-5H-08-SR 8-pin 150-mil SOIC-TAPE & REEL Industrial ASM5I2304A-5H-08-ST 8-pin 150-mil SOIC-TUBE Industrial Licensed under US patent Nos 5,488,627, 6,646,463 and 5,631,920. Preliminary datasheet. Specification subject to change without notice. 3.3 Zero Delay Buffer Notice: The information in this document is subject to change without notice. 12 of 13 ASM5P2304A August 2004 rev 2.0 Use the chart below for device ordering *note Lead Free Option... DEVICE ORDERING INFORMATION Package Suffix ASM5P2304A F - 08-OR OR = SOT23/ T/R TT = TSSOP, TUBE TR = TSSOP, T/R VT = TVSOP,TUBE VR = TVSOP, T/R ST = SOIC, TUBE DEVICE PIN COUNT F = Pb FREE PART NUMBER X= Automotive 1 2 3 4 5 = = = = = I= Industrial reserved Non PLL based EMI Reduction DDR support products STD Zero Delay Buffer SR = SOIC,T/R JT = SSOP, TUBE JR = SSOP, T/R QR = QFN, T/R QT = QFN, TUBE BT = BGA, TUBE BR = BGA, T/R P or n/c = Commercial 6 = Power Management * * * 7 = Power Management * * * 8 = Power Management * * * 9 = Hi Performance 0 = reserved Alliance Semiconductor Mixed Signal Product * * * NOTE: Industry Standard Part Numbers May Be used That Differ from this part numbering system... Alliance Semiconductor Corporation 2595, Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com Copyright (c) Alliance Semiconductor All Rights Reserved Note: This product utilizes US# 6,646,463 Impedance Emulator Patent issued to Dan Hariton / Alliance Semiconductor, dated 11-11-2003 Part Number: ASM5P2304A Document Version: 2.0 8_30_2004 (c) Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. 3.3 Zero Delay Buffer Notice: The information in this document is subject to change without notice. 13 of 13