ADVANCED AND EVER ADVANCING MITSUBISHI ELECTRIC MITSUBISHI 16-BIT SINGLE-CHIP MICROCOMPUTER 7700 FAMILY / 7900 SERIES 7902 Group User's Manual MITSUBISHI ELECTRIC Keep safety first in your circuit designs! Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. 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The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. REVISION DESCRIPTION LIST Rev. No. 7902 Group User's Manual Revision Description Rev. date 1.0 First Edition. 990910 2.0 The following are revised/added points: 991220 (1) Corrections and Supplementary Explanation for 7902 Group User's Manual (REV. A) (2) "2. Remark" in "BEFORE USING THIS MANUAL" <Rev.1.0> Product expansion Refer to the latest datasheet and catalog, or contact the appropriate office, as listed in "CONTACT ADDRESSES FOR FURTHER INFORMATION" on the last page. ********* Development support tools Refer to the "Mitsubishi Microcomputer Development Support Tools" Homepage (http://www.tool-spt.mesc.co.jp/index_e.htm). <Rev.2.0 and after> Product expansion Mitsubishi Microcomputers General Catalog ********* Development Support Tools Datasheets Microcomputers Development Support Tools Catalog Microcomputers Development Support Tools Accessory Guide Please Visit Our Web Site. * Mitsubishi MCU Technical Information (http://www.infomicom.mesc.co.jp/indexe.htm) * Mitsubishi Microcomputer Development Support Tools (http://www.tool-spt.mesc.co.jp/index_e.htm) (3) Page 1-2 The item name has been changed. (The definition of this item is not changed.) Operating temperature range Operating ambient temperature range (4) Page 10-6, Figure 10.2.5/Functions <Error> When using this pin as timer Ai's input pin, **** <Correction> When using this pin as timer Bi's input pin, **** (5) "Topr" in Page 21-110 and Page 21-128 The parameter name has been changed. (The definition of this parameter is not changed.) Operating temperature Operating ambient temperature (1/1) Corrections and Supplementary Explanation for "7902 Group User's Manual" (REV.A) No.1 Page Error Correction P2-7 Processor mode register 1 (Address 5F16) Figure 2.1.5, P3-9 6 Recovery-cycle-insert Figure 3.2.2, number select bit P21-26 Internal ROM bus cycle 7 (Address 5F16) select bit (Note 6) Processor mode register 1 (Address 5F16) 6 Recovery-cycle-insert number select bit (Note 6) 7 Internal ROM bus cycle select bit (Note 7) 5: After reset, this bit can be set only once. 5: After reset, this bit can be set to "1" only once. 6: In the microprocessor mode, **** reprogramming 6: Make sure that a program to be used to change mode.") this bit's contents is allocated in the internal area. 7: In the microprocessor mode, **** reprogramming mode.") P3-10 Last line P3-32 Figure 3.2.18 P5-6 First line P5-8 Figure 5.2.3 and bit 6 at addresses 8016, 8216, 8416, or 8616) must be set to "1." and bit 6 at address 8016, 8216, 8416, or 8616) must be set to "1." Make sure that a program to be used to change this bit's contents is allocated in the internal area. Burst ROM access Burst ROM access 1 1 RD BLW, BHW RD Figure 5.2.2 shows ***, and Figure 5.2.3 shows the procedure for setting or changing the PLL multiplication ratio. Figure 5.2.2 shows ***, and Figure 5.2.3 shows the setting procedure for the clock control register when using the PLL frequency multiplier. Fig. 5.2.3 Procedure for setting or changing PLL multiplication ratio Fig. 5.2.3 Setting procedure for clock control register when using PLL frequency multiplier (1/4) Corrections and Supplementary Explanation for "7902 Group User's Manual" (REV.A) No.2 Page P5-8 Figure 5.2.3 Correction (Revised figure) b7 b0 0 0 1 1 Clock control register (Address BC16) PLL frequency multiplier is active, and pin VCONT is valid. PLL multiplication ratio select bits (Note 1) b3 b2 0 1 : Double 1 0 : Triple 1 1 : Quadruple System clock select bit 0 : fXIN (Note 2) N 2 ms elapsed ? Y Setting of system clock select bit to "1." b7 b0 1 0 1 1 Clock control register (Address BC16) System clock select bit 0 : fPLL Notes 1: After reset, these bits are allowed to be changed only once. If it is necessary to write a certain value to these bits, be sure to write the same value that has been written after the latest reset. 2: This decision is unnecessary if "double" is selected and the period of RESET = "L" is "the oscillation stabilizing time of an oscillator + 2 ms" or more. Page Error Correction P5-11 *** (bits 2, 3 at address BC16). (See Figure 5.2.3.) [Precautions for clock generating circuit] Last line P9-35 Timer Ai mode register (i = 0 to 4) (Addresses 5616 Figure 9.6.1, to 5A16) P21-20 b4 b3 (Addresses 3 Trigger 0 0 : Writing "1" to one-shot 5616 to 5A16) select bits 01: *** (bits 2, 3 at address BC16). (See Figure 5.2.3.) After reset, the PLL multiplication ratio select bits are allowed to be changed only once. If it is necessary to write a certain value to these bits, be sure to write the same value that has been written after the latest reset. Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16) 3 start bit (***) 4 4 10: 11: P12-6 Notes 1: Valid when the CTS/RTS enable bit Figure 12.2.3, (bit 4) is "0." P21-14 (Addresses 3416, 3C16) (2/4) Trigger select bits b4 b3 00: 01: Writing "1" to count start bit (***) 10: 11: Notes 1: Valid when the CTS/RTS enable bit (bit 4) is "0" and CTSi/RTSi separate select bit (bit 0 or 1 at address AC16) is "0." Corrections and Supplementary Explanation for "7902 Group User's Manual" (REV.A) No.3 Page Error Correction P12-17 Serial I/O pin control register (Address AC16) Figure 12.2.13, Bit Bitname Function P21-41 0 CTS0/RTS0 separate select bit (Address AC16) 1 CTS1/RTS1 separate select bit Serial I/O pin control register (Address AC16) Bit Bitname Function 0 CTS0/RTS0 separate select bit (Note) 1 CTS1/RTS1 separate select bit (Note) Note: Valid when the CTS/RTS enable bit (bit 4 at addresses 3416 and 3C16) is "0." P12-23 12.3.3 line 13, P12-28 12.3.5 line 12, P12-40 12.4.3 line 12, P12-47 12.4.5 line 6 By connecting the RTS pin (receiver side) and CTS pin (transmitter side), *** P14-3 D-A control register (Address 9616) Figure 14.2.2, Bit Bit name Function P21-37 0 D-A0 output enable 0 : Output is disabled. (Address 9616) By connecting the RTSi pin (receiver side) and CTSi pin (transmitter side), *** D-A control register (Address 9616) Bit Bit name Function 0 D-A0 output enable 0 : Output is disabled. 1 : Output is enabled. (Notes 1, 2) bit 0 : Output is disabled. 1 : Output is enabled. (Note) 1 D-A1 output enable 0 : Output is disabled. 1 : Output is enabled. (Notes 1, 2) bit 0 : Output is disabled. 1 : Output is enabled. (Note) 2 D-A2 output enable 0 : Output is disabled. 1 : Output is enabled. (Notes 1, 2) bit bit 1 : Output is enabled. (Note) 1 D-A1 output enable bit 2 D-A2 output enable bit Note: Pin DAi is multiplexed ***** (including programmable I/O port pin). Notes 1: Pin DAi is multiplexed ***** (including programmable I/O port pin). 2: When not using the D-A converter, be sure to clear the contents of this bit to "0." P14-3 D-A register i (i = 0 to 2) (Addresses 9816 to 9A16) Figure 14.2.3, Bit Function P21-37 7 to 0 Any value from 00 16 through FF16 can be set, (Addresses and this value is D-A converted and is output. 9816 to 9A16) D-A register i (i = 0 to 2) (Addresses 9816 to 9A16) Bit Function 7 to 0 Any value from 0016 through FF16 can be set (Note), and this value is D-A converted and is output. Note: When not using the D-A converter, be sure to clear the contents of these bits to "0016." P14-7 any other multiplexed input/output pin (including programmable I/O port pin). [Precautions for D-A converter] 4. When not using the D-A converter, be sure to do as follows: *Clear the D-Ai (i = 0 to 2) output enable bit (bits 0 to 2 at address 9616) to "0." *Clear the contents of the D-A register i (addresses 9816 to 9A16) to "0016." Last line P16-2 Table 16.1.1 any other multiplexed input/output pin (including programmable I/O port pin). Item Stop mode Item PLL frequency multiplier Operates. Inactive. fCPU, fBIU Stop mode PLL frequency multiplier Stopped. CPU, BIU Inactive. (3/4) Corrections and Supplementary Explanation for "7902 Group User's Manual" (REV.A) No.4 Page Error P18-8 Figure 18.3.2, P18-9 Figure 18.3.3 Correction STAB A, LG : 0h (Note 3) RTI RTI 3. Make sure that this instruction is executed in the absolute long addressing mode. The above is just an example. In an actual programming, be sure to refer to the format of the assembler description to be used. P21-80 PLP P21-82 PUL P21-95 Last line PLP PLP (Note 22) PUL (Note 18) PUL (Notes 18 and 22) Note 21. Do not use the SEP **** SEI instruction.) (4/4) Note 21. Do not use the SEP **** SEI instruction.) Note 22. Be sure to keep flag I = "1" when executing the PLP or PUL instruction. Also, be sure to use the SEI instruction when setting flag I to "1." Preface This manual describes the hardware of the Mitsubishi CMOS 16-bit microcomputers 7902 Group. After reading this manual, the user will be able to understand the functions, so that they can utilize their capabilities fully. For details of software, refer to the "7900 Series Software Manual." For details of development support tools, refer to the "Mitsubishi Microcomputer Development Support Tools" Homepage (http://www.tool-spt.mesc.co.jp/index_e.htm). BEFORE USING THIS MANUAL 1. Constitution This user's manual consists of the following chapters. Refer to the chapters relevant to the products and processor mode. In this manual, "M37902" means all of or one of the 7902 Group products, unless otherwise noted. Each chapter, except for Chapter 20, describes functions of the 7902 Group product at MD1 = Vss level. Chapter 1. DESCRIPTION to Chapter 18. DEBUG FUNCTION (Except for Chapter 3) Functions which are common to all products and all processor modes are described. Chapter 3. CONNECTION WITH EXTERNAL DEVICES Functions used for connection with external devices in the memory expansion and microprocessor modes are explained. Chapter 19. APPLICATIONS Connection examples with external devices are described. Chapter 20. FLASH MEMORY VERSION Characteristics information for the flash memory version is described. Appendix Practical information for using the 7902 Group is described. 2. Remark Product expansion Mitsubishi Microcomputers General Catalog Electrical characteristics Refer to the latest datasheet. Software Refer to the "7900 Series Software Manual." Development support tools Datasheets Microcomputers Development Support Tools Catalog Microcomputers Development Support Tools Accessory Guide Please Visit Our Web Site. * Mitsubishi MCU Technical Information (http://www.infomicom.mesc.co.jp/indexe.htm) * Mitsubishi Microcomputer Development Support Tools (http://www.tool-spt.mesc.co.jp/index_e.htm) 3. Signal levels in Figure As a rule, signal levels in each operation example and timing diagram are as follows. * Signal levels The upper line indicates "1," and the lower line indicates "0." * Input/Output levels of pin The upper line indicates "H," and the lower line indicates "L." Foe the exception, the level is shown on the left side of a signal. 1 4. Register structure The view of the register structure is described below: 2 XXX register (address XX16) Bit 1 b7 b6 b5 b4 b3 b2 b1 b0 5 X 0 Bit name Function 0 * * * select bit 0:... 1:... The value is "0" at reading. 1 * * * select bit b2 b1 00:... 01:... 10:... 11:... 2 0:... 1:... At reset R/W Undefined WO 0 RW 0 RW 0 RO 3 * * * flag 4 Fix this bit to "0." 0 RW 5 This bit is invalid in ... mode. 0 RW 6 Nothing is assigned. Undefined -- 7 The value is "0" at reading. 0 -- 6 4 1 Blank 0 1 : Set to "0" or "1" according to the usage. : Set to "0" at writing. : Set to "1" at writing. : Invalid depending on the mode or state. It may be "0" or "1." : Nothing is assigned. 2 0 1 Undefined : "0" immediately after reset. : "1" immediately after reset. : Undefined immediately after reset. 3 RW RO WO -- 4 2 : It is possible to read the bit state at reading. The written value becomes valid. : It is possible to read the bit state at reading. The written value becomes invalid. Accordingly, the written value may be "0" or "1." : The written value becomes valid. It is impossible to read the bit state. The value is undefined at reading. However, when ["0" at reading"] is indicated in the "Function" or "Note" column, the bit is always "0" at reading. (See 5 above.) : It is impossible to read the bit state. The value is undefined at reading. However, when ["0" at reading"] is indicated in the "Function" or "Note" column, the bit is always "0" at reading. (See 6 above.) The written value becomes invalid. Accordingly, the written value may be "0" or "1." Invalid for that function or mode. 3 Table of contents Table of contents CHAPTER 1. DESCRIPTION 1.1 1.2 1.3 1.4 Performance overview .......................................................................................................... 1-2 Pin configuration ................................................................................................................... 1-3 Pin description ....................................................................................................................... 1-5 Block diagram ........................................................................................................................ 1-9 CHAPTER 2. CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit (CPU) ........................................................................................... 2-2 2.1.1 Accumulator (Acc) .......................................................................................................... 2-3 2.1.2 Index register X (X) ....................................................................................................... 2-3 2.1.3 Index register Y (Y) ....................................................................................................... 2-3 2.1.4 Stack pointer (S) ............................................................................................................ 2-4 2.1.5 Program counter (PC) ................................................................................................... 2-5 2.1.6 Program bank register (PG) ......................................................................................... 2-5 2.1.7 Data bank register (DT) ................................................................................................ 2-5 2.1.8 Direct page register 0 to 3 (DPR0 to DPR3) ............................................................ 2-6 2.1.9 Processor status register (PS) ..................................................................................... 2-8 2.2 Bus interface unit (BIU) ..................................................................................................... 2-10 2.2.1 Instruction prefetch ...................................................................................................... 2-11 2.2.2 Data Transfer (read and write) .................................................................................. 2-14 2.3 Access space ....................................................................................................................... 2-18 2.4 Memory assignment ............................................................................................................ 2-19 2.4.1 Memory assignment in internal area ......................................................................... 2-19 2.5 Processor modes ................................................................................................................. 2-22 2.5.1 Single-chip mode .......................................................................................................... 2-23 2.5.2 Memory expansion and Microprocessor modes ....................................................... 2-23 2.5.3 Setting of processor mode.......................................................................................... 2-25 [Precautions for setting of processor mode] ...................................................................... 2-27 CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES 3.1 Signals required for accessing external devices .......................................................... 3-2 3.2 Chip select wait controller .................................................................................................. 3-7 3.2.1 Related registers ............................................................................................................ 3-8 3.2.2 External bus operations .............................................................................................. 3-23 3.2.3 Setting method ............................................................................................................. 3-30 3.2.4. Address output selection ............................................................................................ 3-31 [Precautions for CSWC] ............................................................................................................ 3-33 3.3 Ready function ..................................................................................................................... 3-34 3.3.1 Operation description ................................................................................................... 3-35 3.4 Hold function ........................................................................................................................ 3-36 3.4.1 Operation description ................................................................................................... 3-37 7902 Group User's Manual i Table of contents CHAPTER 4. RESET 4.1 Reset operation ...................................................................................................................... 4-2 4.1.1 Hardware reset ............................................................................................................... 4-2 4.1.2 Software reset ................................................................................................................ 4-3 4.1.3 Power-on reset ............................................................................................................... 4-4 4.2 Pin state .................................................................................................................................. 4-5 4.3 State of internal area ............................................................................................................ 4-6 4.4 Internal processing sequence after reset ...................................................................... 4-13 CHAPTER 5. CLOCK GENERATING CIRCUIT 5.1 Oscillation circuit examples ............................................................................................... 5-2 5.1.1 Connection example with resonator/oscillator ............................................................ 5-2 5.1.2 Externally generated clock input example .................................................................. 5-2 5.1.3 Connection example of filter circuit ............................................................................. 5-3 5.2 Clocks ...................................................................................................................................... 5-4 5.2.1 Clocks generated in clock generating circuit ............................................................. 5-5 5.2.2 Clock control register ..................................................................................................... 5-6 5.2.3 Particular function select register 0 ............................................................................. 5-9 [Precautions for clock generating circuit] ........................................................................... 5-11 CHAPTER 6. INPUT/OUTPUT PINS 6.1 Overview .................................................................................................................................. 6-2 6.2 Programmable I/O ports ....................................................................................................... 6-2 6.2.1 Direction register ............................................................................................................ 6-3 6.2.2 Port register .................................................................................................................... 6-4 6.2.3 Selectable functions ....................................................................................................... 6-7 6.3 Examples of handling unused pins .................................................................................. 6-8 6.3.1 In the single-chip mode ................................................................................................. 6-8 6.3.2 In memory expansion and microprocessor modes .................................................... 6-9 CHAPTER 7. INTERRUPTS 7.1 Overview .................................................................................................................................. 7-2 7.2 Interrupt sources ................................................................................................................... 7-4 7.3 Interrupt control ..................................................................................................................... 7-8 7.3.1 Interrupt disable flag (I) ................................................................................................ 7-8 7.3.2 Interrupt request bit ....................................................................................................... 7-8 7.3.3 Interrupt priority level select bits and Processor interrupt priority level (IPL) ...... 7-5 7.4 Interrupt priority level ........................................................................................................ 7-10 7.5 Interrupt priority level detection circuit ......................................................................... 7-11 7.6 Interrupt priority level detection time ............................................................................ 7-13 7.7 Sequence from acceptance of interrupt request until execution of interrupt routine ... 7-14 7.7.1 Change in IPL at acceptance of interrupt request .................................................. 7-15 7.7.2 Push operation for registers ....................................................................................... 7-16 7.8 Return from interrupt routine ........................................................................................... 7-17 7.9 Multiple interrupts ............................................................................................................... 7-17 ii 7902 Group User's Manual Table of contents 7.10 External interrupts ............................................................................................................ 7-19 7.10.1 NMI interrupt ............................................................................................................... 7-19 7.10.2 INT i interrupt ............................................................................................................... 7-19 7.10.3 Functions of INT i interrupt request bit .................................................................... 7-23 7.10.4 Switching of INT k to (k = 0 to 2) interrupt request occurrence factor ............... 7-24 [Precautions for interrupts] ..................................................................................................... 7-25 CHAPTER 8. KEY INPUT INTERRUPT 8.1 Overview .................................................................................................................................. 8-2 8.2 Block description .................................................................................................................. 8-3 8.2.1 External interrupt input control register ...................................................................... 8-4 8.2.2 INT 3 interrupt control register ....................................................................................... 8-5 8.2.3 Port P5 direction register .............................................................................................. 8-6 8.3 Initial setting example for related registers ................................................................... 8-7 CHAPTER 9. TIMER A 9.1 Overview .................................................................................................................................. 9-2 9.2 Block description .................................................................................................................. 9-3 9.2.1 Counter and Reload register (timer Ai register) ........................................................ 9-4 9.2.2 Timer A clock division select register ......................................................................... 9-5 9.2.3 Count start register ........................................................................................................ 9-6 9.2.4 Timer Ai mode register ................................................................................................. 9-6 9.2.5 Timer Ai interrupt control register ................................................................................ 9-7 9.2.6 Port P5 and port P6 direction registers ...................................................................... 9-8 9.3 Timer mode ............................................................................................................................. 9-9 9.3.1 Setting for timer mode ................................................................................................ 9-11 9.3.2 Operation in timer mode ............................................................................................. 9-12 9.3.3 Select function .............................................................................................................. 9-13 [Precautions for timer mode] .................................................................................................. 9-15 9.4 Event counter mode ........................................................................................................... 9-16 9.4.1 Setting for event counter mode ................................................................................. 9-19 9.4.2 Operation in event counter mode .............................................................................. 9-21 9.4.3 Switching between countup and countdown ............................................................ 9-22 9.4.4 Selectable functions ..................................................................................................... 9-23 [Precautions for event counter mode] .................................................................................. 9-25 9.5 One-shot pulse mode ......................................................................................................... 9-26 9.5.1 Setting for one-shot pulse mode ............................................................................... 9-28 9.5.2 Trigger ........................................................................................................................... 9-30 9.5.3 Operation in one-shot pulse mode ............................................................................ 9-31 [Precautions for one-shot pulse mode] ................................................................................ 9-33 9.6 Pulse width modulation (PWM) mode ............................................................................ 9-34 9.6.1 Setting for PWM mode ................................................................................................ 9-36 9.6.2 Trigger ........................................................................................................................... 9-38 9.6.3 Operation in PWM mode ............................................................................................. 9-39 [Precautions for pulse width modulation (PWM) mode] ................................................... 9-43 7902 Group User's Manual iii Table of contents CHAPTER 10. TIMER B 10.1 Overview .............................................................................................................................. 10-2 10.2 Block description .............................................................................................................. 10-2 10.2.1 Counter and Reload register (timer Bi register) .................................................... 10-3 10.2.2 Count start register .................................................................................................... 10-4 10.2.3 Timer Bi mode register ............................................................................................. 10-4 10.2.4 Timer Bi interrupt control register............................................................................ 10-5 10.2.5 Port P6 direction register .......................................................................................... 10-6 10.2.6 Count source (in timer mode and pulse period/pulse width measurement mode) ..... 10-6 10.3 Timer mode ......................................................................................................................... 10-7 10.3.1 Setting for timer mode .............................................................................................. 10-9 10.3.2 Operation in timer mode ......................................................................................... 10-10 [Precautions for timer mode] ................................................................................................ 10-11 10.4 Event counter mode ....................................................................................................... 10-12 10.4.1 Count source ............................................................................................................ 10-14 10.4.2 Setting for event counter mode ............................................................................. 10-15 10.4.3 Operation in event counter mode .......................................................................... 10-16 [Precautions for event counter mode] ................................................................................ 10-17 10.5 Pulse period/Pulse width measurement mode ......................................................... 10-18 10.5.1 Setting for pulse period/pulse width measurement mode .................................. 10-20 10.5.2 Operation in pulse period/pulse width measurement mode ............................... 10-21 [Precautions for pulse period/pulse width measurement mode] .................................. 10-23 CHAPTER 11. REAL-TIME OUTPUT 11.1 Overview .............................................................................................................................. 11-2 11.2 Block description .............................................................................................................. 11-4 11.2.1 Real-time output control register ............................................................................. 11-4 11.2.2 Pulse output data registers 0 and 1 ....................................................................... 11-5 11.2.3 Port P5 direction register .......................................................................................... 11-6 11.2.4 Timers A0 and A2 ...................................................................................................... 11-6 11.3 Setting of real-time output .............................................................................................. 11-7 11.4 Real-time output operation ........................................................................................... 11-10 CHAPTER 12. SERIAL I/O 12.1 Overview .............................................................................................................................. 12-2 12.2 Block description .............................................................................................................. 12-3 12.2.1 UARTi transmit/receive mode register .................................................................... 12-4 12.2.2 UARTi transmit/receive control register 0 ............................................................... 12-6 12.2.3 UARTi transmit/receive control register 1 ............................................................... 12-8 12.2.4 UARTi transmit register and UARTi transmit buffer register ............................. 12-10 12.2.5 UARTi receive register and UARTi receive buffer register ................................ 12-12 12.2.6 UARTi baud rate register (BRGi) ........................................................................... 12-14 12.2.7 UARTi transmit interrupt control and UARTi receive interrupt control registers . 12-15 12.2.8 Serial I/O pin control register ................................................................................. 12-17 12.2.9 Port P8 direction register ........................................................................................ 12-18 12.2.10 CTS/RTS function .................................................................................................. 12-19 12.3 Clock synchronous serial I/O mode ........................................................................... 12-20 12.3.1 Transfer clock (Synchronizing clock) ..................................................................... 12-20 12.3.2 Transfer data format ................................................................................................ 12-22 iv 7902 Group User's Manual Table of contents 12.3.3 Method of transmission ........................................................................................... 12-23 12.3.4 Transmit operation ................................................................................................... 12-26 12.3.5 Method of reception ................................................................................................. 12-28 12.3.6 Receive operation .................................................................................................... 12-31 12.3.7 Processing on detecting overrun error .................................................................. 12-34 [Precautions for clock synchronous serial I/O mode] .................................................... 12-35 12.4 Clock asynchronous serial I/O (UART) mode ...........................................................12-36 12.4.1 Transfer rate (Frequency of transfer clock) ......................................................... 12-37 12.4.2 Transfer data format ................................................................................................ 12-39 12.4.3 Method of transmission ........................................................................................... 12-40 12.4.4 Transmit operation ................................................................................................... 12-44 12.4.5 Method of reception ................................................................................................. 12-47 12.4.6 Receive operation .................................................................................................... 12-50 12.4.7 Processing on detecting error ................................................................................ 12-52 12.4.8 Sleep mode ...............................................................................................................12-53 [Precautions for clock asynchronous serial I/O (UART) mode].................................... 12-54 CHAPTER 13. A-D CONVERTER 13.1 Overview .............................................................................................................................. 13-2 13.2 Block description .............................................................................................................. 13-3 13.2.1 A-D control register 0, 1 ........................................................................................... 13-4 13.2.2 A-D register i (i = 0 to 7) ......................................................................................... 13-8 13.2.3 A-D conversion interrupt control register ................................................................ 13-9 13.2.4 Port P7 direction register ........................................................................................ 13-10 13.3 A-D conversion method ................................................................................................. 13-11 13.4 Absolute accuracy and Differential non-linearity error .......................................... 13-14 13.4.1 Absolute accuracy .................................................................................................... 13-14 13.4.2 Differential non-linearity error ................................................................................. 13-15 13.5 Comparison voltage in 8-bit resolution mode .......................................................... 13-16 13.6 One-shot mode................................................................................................................. 13-17 13.6.1 Settings for one-shot mode ....................................................................................13-17 13.6.2 One-shot mode operation ....................................................................................... 13-18 13.7 Repeat mode ..................................................................................................................... 13-19 13.7.1 Settings for repeat mode ........................................................................................ 13-19 13.7.2 Repeat mode operation ........................................................................................... 13-20 13.8 Single sweep mode ......................................................................................................... 13-21 13.8.1 Settings for single sweep mode ............................................................................ 13-21 13.8.2 Single sweep mode operation ................................................................................ 13-22 13.9 Repeat sweep mode ....................................................................................................... 13-23 13.9.1 Settings for repeat sweep mode ............................................................................ 13-23 13.9.2 Repeat sweep mode operation .............................................................................. 13-24 [Precautions for A-D converter] ............................................................................................ 13-25 CHAPTER 14. D-A CONVERTER 14.1 Overview .............................................................................................................................. 14-2 14.2 Block description .............................................................................................................. 14-2 14.2.1 D-A control register ................................................................................................... 14-3 14.2.2 D-A Register i (i = 0 to 2)........................................................................................ 14-3 14.2.3 A-D control register 1 ................................................................................................ 14-4 7902 Group User's Manual v Table of contents 14.3 D-A conversion method ................................................................................................... 14-5 14.4 Setting method ................................................................................................................. 14-6 14.5 Operation description ....................................................................................................... 14-6 [Precautions for D-A converter] .............................................................................................. 14-7 CHAPTER 15. WATCHDOG TIMER 15.1 Block description .............................................................................................................. 15-2 15.1.1 Watchdog timer .......................................................................................................... 15-3 15.1.2 Watchdog timer frequency select register .............................................................. 15-3 15.1.3 Particular function select register 2 ......................................................................... 15-4 15.2 Operation description ....................................................................................................... 15-5 15.2.1 Basic operation ........................................................................................................... 15-5 15.2.2 Stop period ................................................................................................................. 15-7 15.2.3 Operations in stop mode .......................................................................................... 15-7 [Precautions for watchdog timer] ........................................................................................... 15-8 CHAPTER 16. STOP AND WAIT MODES 16.1 Overview .............................................................................................................................. 16-2 16.2 Block description .............................................................................................................. 16-3 16.2.1 Particular function select register 0 ......................................................................... 16-4 16.2.2 Particular function select register 1 ......................................................................... 16-6 16.2.3 Watchdog timer frequency select register .............................................................. 16-7 16.3 Stop mode ........................................................................................................................... 16-8 16.3.1 Terminate operation at interrupt request occurrence (when using watchdog timer) ... 16-8 16.3.2 Terminate operation at interrupt request occurrence (when not using watchdog timer) 16-9 16.3.3 Terminate operation at hardware reset ................................................................. 16-11 16.4 Wait mode ......................................................................................................................... 16-12 16.4.1 Terminate operation at interrupt request occurrence .......................................... 16-12 16.4.2 Terminate operation at hardware reset ................................................................. 16-12 CHAPTER 17. POWER SAVING FUNCTION 17.1 Overview .............................................................................................................................. 17-2 17.1.1 Particular function select register 0 ......................................................................... 17-3 17.1.2 Particular function select register 1 ......................................................................... 17-5 17.2 Bus fixation in stop and wait modes............................................................................. 17-6 17.3 Stop of system clock in wait mode ............................................................................... 17-8 17.4 Stop of oscillation circuit ................................................................................................ 17-9 17.5 Pin VREF disconnection ..................................................................................................... 17-9 CHAPTER 18. DEBUG FUNCTION 18.1 Overview .............................................................................................................................. 18-2 18.2 Block description .............................................................................................................. 18-2 18.2.1 Debug control register 0 ........................................................................................... 18-3 18.2.2 Debug control register 1 ........................................................................................... 18-4 18.2.3 Address compare registers 0 and 1 ........................................................................ 18-5 18.3 Address matching detection mode ............................................................................... 18-6 18.3.1 Setting procedure for address matching detection mode..................................... 18-6 vi 7902 Group User's Manual Table of contents 18.3.2 Operations in address matching detection mode .................................................. 18-7 18.4 Out-of-address-area detection mode ............................................................................... 18-10 18.4.1 Setting procedure for out-of-address-area detection mode ............................... 18-10 18.4.2 Operations in out-of-address-area detection mode ............................................. 18-11 [Precautions for debug function] ......................................................................................... 18-12 CHAPTER 19. APPLICATIONS 19.1 Connection examples with external devices .............................................................. 19-2 19.1.1 Examples with ready function used ......................................................................... 19-3 19.1.2 Connection examples with memories ...................................................................... 19-6 19.1.3 I/O expansion examples .......................................................................................... 19-10 19.2 Examples of handling control pins in flash memory serial I/O mode ............... 19-13 19.2.1 With control signals not affecting user system circuit ........................................ 19-13 19.2.2 With control signals affecting user system circuit ............................................... 19-14 CHAPTER 20. FLASH MEMORY VERSION 20.1 Overview .............................................................................................................................. 20-2 20.1.1 Memory assignment ................................................................................................... 20-4 20.1.2 Boot mode ................................................................................................................. 20-12 20.2 Flash memory CPU reprogramming mode ................................................................ 20-13 20.2.1 Flash memory control register ............................................................................... 20-14 20.2.2 Status register .......................................................................................................... 20-16 20.2.3 Data protect function ............................................................................................... 20-17 20.2.4 Setting and Terminate procedure for flash memory CPU reprogramming mode .....20-17 20.2.5 Software commands ................................................................................................ 20-18 20.2.6 Full status check ......................................................................................................20-22 20.2.7 Electrical characteristics .......................................................................................... 20-24 [Precautions for flash memory CPU reprogramming mode] ......................................... 20-25 20.3 Flash memory serial I/O mode ..................................................................................... 20-26 20.3.1 Pin description .......................................................................................................... 20-26 [Precautions for flash memory serial I/O mode] .............................................................. 20-30 20.4 Flash memory parallel I/O mode ................................................................................. 20-31 [Precautions for flash memory parallel I/O mode] ...........................................................20-32 APPENDIX Appendix Appendix Appendix Appendix Appendix Appendix Appendix Appendix Appendix Appendix Appendix Appendix 1. Memory assignment in SFR area .................................................................... 21-2 2. Control registers ................................................................................................. 21-8 3. Package outline ................................................................................................. 21-43 4. Examples of handling unused pins .............................................................. 21-44 5. Hexadecimal instruction code table ............................................................. 21-46 6. Machine instructions ........................................................................................ 21-54 7. Countermeasure against noise ...................................................................... 21-96 8. 7902 Group Q & A .......................................................................................... 21-102 9. M37902FGCGP electrical characteristics ................................................... 21-110 10. M37902FGMHP electrical characteristics ................................................ 21-128 11. Standard characteristics ............................................................................. 21-146 12. Memory assignment of 7902 Group ......................................................... 21-153 7902 Group User's Manual vii CHAPTER 1 DESCRIPTION 1.1 1.2 1.3 1.4 Performance overview Pin configuration Pin description Block diagram DESCRIPTION 1.1 Performance overview 1.1 Performance overview Table 1.1.1 lists the performance overview of the M37902FGCGP/HP. Table 1.1.1 M37902FGCGP/HP performance overview Items Number of basic instructions Instruction execution time External clock input frequency f(XIN) System clock frequency f(fsys) Memory sizes Flash memory Performance 203 38.46 ns (the minimum instruction at f(fsys) = 26 MHz) 26 MHz (maximum) 26 MHz (maximum) 248 Kbytes (User ROM area) 16 Kbytes (Boot ROM area) RAM 6144 bytes Programmable P0-P2, P4-P8, P10, P11 8 bits 10 Input/Output ports P3 4 bits 1 Multifunctional TA0-TA4 16 bits 5 timer TB0-TB2 16 bits 3 Serial I/O UART0, UART1 (UART or clock synchronous serial I/O) 2 A-D converter 10-bit successive approximation method 1 (8 channels) D-A converter 8 bits 3 Watchdog timer 12 bits 1 ______ ______ Chip select wait controller Chip select 4 (CS0-CS3). Each chip select area can select its bus cycle and external data bus's width, respectively. Real-time output 4 bits 2 channels, or 6 bits 1 channel + 2 bits 1 channel 5 external, 13 internal Interrupt Maskable (Any of priority levels 0 through 7 can be set for each interrupt, by software.) Non-maskable 1 external, 3 internal Clock generating circuit Built-in (externally connected to a ceramic resonator or a quartz-crystal oscillator) PLL frequency multiplier Double, Triple, or Quadruple Power source voltage 5 V 0.5 V Power dissipation 150 mW (at f(fsys) = 26 MHz, typ, the PLL frequency multiplier is stopped.) Port Input/Output Input/Output withstand voltage 5 V characteristics Output current 5 mA Memory expansion Maximum 16 Mbytes (Bank FF16 is a reserved area.) Operating ambient temperature range -20 C to 85 C Device structure CMOS high-performance silicon gate process Package 100-pin plastic molded QFP (GP: 100P6S-A, HP: 100P6Q-A) 1-2 7902 Group User's Manual DESCRIPTION 1.2 Pin configuration 1.2 Pin configuration Figures 1.2.1 and 1.2.2 show the M37902 pin configuration. P100/A0 P87/TXD1 P86/RXD1 P85/CTS1/CLK1 P84/CTS1/RTS1/INT4 P83/TXD0 P82/RXD0 P81/CTS0/CLK0 VCC AVCC VREF AVSS VSS NMI P80/CTS0/RTS0/DA2/INT3 P77/AN7/ADTRG/DA1/(INT2) P76/AN6/DA0 P75/AN5/(INT4) P74/AN4/(INT3) P73/AN3 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 P72/AN2 P71/AN1 P70/AN0 P67/TB2IN P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/RTP13/KI3 P56/TA3OUT/RTP12/KI2 P55/TA2IN/RTP11/KI1 P54/TA2OUT/RTP10/KI0 P53/TA1IN/RTP03 P52/TA1OUT/RTP02 P51/TA0IN/RTP01 P50/TA0OUT/RTP00 P47/CS3 P46/CS2 P45/CS1 P44/CS0 P43/HOLD P42/HLDA P41/1 P40/ALE P33/BHW P32/BLW P31/RD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P101/A1 P102/A2 P103/A3 P104/A4 P105/A5 P106/A6 P107/A7 P110/A8 P111/A9 P112/A10 P113/A11 P114/A12 P115/A13 P116/A14 P117/A15 P00/A16 P01/A17 P02/A18 P03/A19 P04/A20 P05/A21 P06/A22 P07/A23 VSS MD1 P10/D0/LA0 P11/D1/LA1 P12/D2/LA2 P13/D3/LA3 P14/D4/LA4 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P15/D5/LA5 P16/D6/LA6 P17/D7/LA7 P20/D8 P21/D9 P22/D10 P23/D11 P24/D12 P25/D13 P26/D14 P27/D15 VCC XOUT XIN VSS MD0 RESET VCONT BYTE P30/RDY Outline 100P6S-A Fig. 1.2.1 M37902 pin configuration (outline 100P6S-A, top view) 7902 Group User's Manual 1-3 DESCRIPTION 1.2 Pin configuration P103/A3 P102/A2 P101/A1 P100/A0 P87/TXD1 P86/RXD1 P85/CTS1/CLK1 P84/CTS1/RTS1/INT4 P83/TXD0 P82/RXD0 P81/CTS0/CLK0 VCC AVCC VREF AVSS VSS NMI P80/CTS0/RTS0/DA2/INT3 P77/AN7/ADTRG/DA1/(INT2) P76/AN6/DA0 P75/AN5/(INT4) P74/AN4/(INT3) P73/AN3 P72/AN2 P71/AN1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 P70/AN0 P67/TB2IN P66/TB1IN P65/TB0IN P63/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/RTP13/KI3 P56/TA3OUT/RTP12/KI2 P55/TA2IN/RTP11/KI1 P54/TA2OUT/RTP10/KI0 P53/TA1IN/RTP03 P52/TA1OUT/RTP02 P51/TA0IN/RTP01 P50/TA0OUT/RTP00 P47/CS3 P46/CS2 P45/CS1 P44/CS0 P43/HOLD P42/HLDA P41/1 P40/ALE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P13/D3/LA3 P14/D4/LA4 P15/D5/LA5 P16/D6/LA6 P17/D7/LA7 P20/D8 P21/D9 P22/D10 P23/D11 P24/D12 P25/D13 P26/D14 P27/D15 VCC XOUT XIN VSS MD0 RESET VCONT BYTE P30/RDY P31/RD P32/BLW P33/BHW Outline 100P6Q-A Fig. 1.2.2 M37902 pin configuration (outline 100P6Q-A, top view) 1-4 7902 Group User's Manual P104/A4 P105/A5 P106/A6 P107/A7 P110/A8 P111/A9 P112/A10 P113/A11 P114/A12 P115/A13 P116/A14 P117/A15 P00/A16 P01/A17 P02/A18 P03/A19 P04/A20 P05/A21 P06/A22 P07/A23 VSS MD1 P10/D0/LA0 P11/D1/LA1 P12/D2/LA2 DESCRIPTION 1.3 Pin description 1.3 Pin description Tables 1.3.1 to 1.3.4 list the pin description. Table 1.3.1 Pin description (1) Pin Name Vcc, Vss MD0 MD1 Power source input MD0 Input/Output -- Input Function Apply 5 V 0.5 V to pin Vcc and 0 V to pin Vss. This pin switches the operating mode. MD1 MD1 Vss MD0 Vss Vss Vcc Vcc Vss Vcc Vcc Operating mode Single-chip mode (Note), Memory expansion mode, Microprocessor mode Microprocessor mode Boot mode Flash memory parallel I/O mode Note: When MD1 = Vss and MD0= Vss, the microcomputer starts RESET X IN Reset input Clock input Input Input X OUT Clock output BYTE External data bus width select input Input NMI NMI interrupt input Input V CONT Filter circuit connection -- AVcc Analog power source input -- Output Reference voltage input Input AVss V REF operation in the single-chip mode after reset. It's processor mode can be switched to the memory expansion or microprocessor mode by software. The microcomputer is reset when "L" level is input to this pin. Pins X IN and X OUT are the input and output pins of the clock generating circuit, respectively. Connect these pins via a ceramic resonator or a quartz-crystal oscillator. When an external clock is input, this clock should be input to pin X IN, and pin X OUT should be left open. The input level to this pin determines whether the external data bus has a 16-bit width or an 8-bit width. A 16-bit width is selected when the input level = Vss, and an 8-bit width is selected when the input level = Vcc. When BYTE = Vss, by software, the external data bus width can be set to 8 bits for each of areas CS1 to CS 3. This is the input pin for the NMI interrupt. While pin RESET is at "L" level or after reset, this pin is pulled up. This pullup state can be removed by software. To use the PLL frequency multiplier, be sure to connect this pin to the filter circuit. The power source input pin for the A-D and D-A converters. Connect this pin to pin Vcc. The power source input pin for the A-D and D-A converters. Connect this pin to pin Vss. This is the reference voltage input pin for the A-D and D-A converters. 7902 Group User's Manual 1-5 DESCRIPTION 1.3 Pin description Table 1.3.2 Pin description (2) Pin P0 0-P0 7 Name I/O port P0 A 16 -A23 P1 0-P1 7 Output I/O port P1 D0-D 7, LA 0-LA 7 P2 0-P2 7 I/O I/O port P2 I/O P2 is an 8-bit I/O port with the same function as port P0. [Memory expansion mode][Microprocessor mode] When the external data bus width = 8 bits (BYTE = Vcc level) P2 is an 8-bit I/O port with the same function as port P0. When the external data bus width = 16 bits (BYTE = Vss level) I/O I/O port P3 Each pin can function as an input or output port pin. [Memory expansion mode][Microprocessor mode] High-order 8 bits (A16 -A23 ) of an address are output. By software, these pins can function as an I/O port with the same function as port P0. [Single-chip mode] P1 is an 8-bit I/O port with the same function as port P0. [Memory expansion mode][Microprocessor mode] Low-order 8 bits (D 0-D 7) of data are input or output. When area CS2 is accessed with the external data bus width = 8 bits, by software, address (LA 0-LA 7) output and data (D0-D7) input/output can be performed with the time-sharing method. [Single-chip mode] I/O P2 0/D 8- P2 7/D15 P3 0-P3 3 Input/Output Function I/O [Single-chip mode] P0 is an 8-bit CMOS I/O port and has an I/O direction register. I/O P3 0, RDY, I/O, Input, RD, BLW, BHW Output, Output, Output High-order 8 bits (D8-D 15 ) of data are input and output. [Single-chip mode] P3 is a 4-bit I/O port with the same function as port P0. [Memory expansion mode][Microprocessor mode] When MD1 = Vss level, MD0 = Vss level P30 functions as an I/O port pin with the same function as port P0. By software, P30 can function as pin RDY. When MD1 = Vss level, MD0 = Vcc level P30 functions as pin RDY. By software, P3 0 can function as an I/O port with the same function as port P0. While pin RDY's input level = "L," the microcomputer is placed in Ready state. P31, P32, and P33 become pins RD, BLW, and BHW, respectively. The microcomputer reads data or instruction codes while pin RD's level = "L." When the external data bus width = 8 bits (BYTE = Vcc level) The microcomputer writes data when pin BLW's level = "L." Pin BHW functions as an I/O port pin (P3 3), with the same function as port P0. When the external data bus width = 16 bits (BYTE = Vss level) The microcomputer writes data into an even-numbered address while pin BLW's level = "L." The microcomputer writes data into an odd-numbered address when pin BHW's evel = "L." 1-6 7902 Group User's Manual DESCRIPTION 1.3 Pin description Table 1.3.3 Pin description (3) Pin P40-P47 Name I/O port P4 P40-P47 Input/Output I/O [Single-chip mode] P4 is an 8-bit I/O port with the same function as port P0. By software, P41 can function as the clock 1 output pin. While pin RESET = "L" level and after reset, P4 4-P4 7 are pulled up. This pullup state can be removed by software. [Memory expansion mode] P4 is an 8-bit I/O port with the same function as port P0. By software, P40 can function as pin ALE, P4 1 as the clock 1 output pin, P42 as pin HLDA, P43 as pin HOLD, P44-P47 as pins CS 0-CS3. While pin RESET = "L" level and after reset, P44-P4 7 are pulled up. This pullup state can be removed by software. I/O ALE, Output, Output, 1, HLDA, HOLD, CS 0, P45-P47 Function Output, Input, Output, I/O [Microprocessor mode] P40 functions as pin ALE, P41 as the clock 1 output pin, P42 as pin HLDA, P4 3 as pin HOLD, P4 4 as pin CS0. Signal ALE This signal is used to latch an address. Signal 1 This signal has the same period as system clock fsys . Signal HOLD The microcomputer is in Hold state while pin HOLD's input level = "L." Signal HLDA This signal informs the external whether this microcomputer enters Hold state or not. Signal CS0 This signal is a chip select signal. P4 5-P4 7 function as I/O port pins with the same function as port P0. By software, pin ALE, the clock 1 output pin, pins HLDA, HOLD can function as I/O port pins (P40, P41, P42, P43) and P4 5-P4 7 as pins CS1 to CS3. P50-P57 I/O port P5 I/O P60-P67 I/O port P6 I/O P70-P77 I/O port P7 I/O Also, P4 5-P4 7 are pulled up while pin RESET = "L" level and after reset. This pullup state can be removed by software. P5 is an 8-bit I/O port with the same function as port P0. By software, these pins can function as I/O pins for timers A0 to A3, pulse output pins for real-time output, or input pins for the key input interrupt. P6 is an 8-bit I/O port with the same function as port P0. By software, these pins can function as I/O pins for timer A4, input pins for the external interrupts, or input pins for timers B0 to B2. P7 is an 8-bit I/O port with the same function as port P0. By software, these pins can function as input pins for the A-D converter, output pins for the D-A converter, or input pins for the external interrupts. 7902 Group User's Manual 1-7 DESCRIPTION 1.3 Pin description Table 1.3.4 Pin description (4) Pin Name P8 0-P8 7 I/O port P8 P100-P10 7 I/O port P10 A 0-A7 P110-P11 7 A 8-A15 1-8 I/O port P11 Function Input/Output I/O P8 is an 8-bit I/O port with the same function as port P0. By software, these pins can function as I/O pins for serial I/O, output pins for the D-A converter, or input pins for the external interrupts. I/O [Single-chip mode] P10 is an 8-bit I/O port with the same function as port P0. Output [Memory expansion mode][Microprocessor mode] I/O Output Low-order 8 bits (A 0-A7) of an address are output. [Single-chip mode] P11 is an 8-bit I/O port with the same function as port P0. [Memory expansion mode][Microprocessor mode] Middle-order 8 bits (A 8-A 15) of an address are output. By software, these pins can funtion as an 8-bit I/O port with the same function as port P0. 7902 Group User's Manual DESCRIPTION 1.4 Block diagram 1.4 Block diagram Figure 1.4.1 shows the M37902 block diagram. Data Bus (Even) Data Bus (Odd) Data Buffer DQ2 (8) Input/Output port P0 P0(8) Data Buffer DQ1 (8) BYTE Address Bus Data Buffer DQ3 (8) P1(8) NMI Instruction Queue Buffer Q0 (8) Instruction Queue Buffer Q1 (8) Input/Output port P1 External data bus width select input Data Buffer DQ0 (8) Instruction Queue Buffer Q4 (8) Input/Output port P2 P2(8) Instruction Queue Buffer Q3 (8) VREF Reference voltage input Instruction Queue Buffer Q2 (8) Input/Output port P4 Input/Output port P5 P3(4) P4(8) P5(8) P6(8) D-A0 converter (8) Program Counter PC (16) Input/Output port P6 MD0 Incrementer/Decrementer (24) UART0 (9) UART1 (9) MD1 Data Address Register DA (24) Bus Interface Unit (BIU) Incrementer (24) Program Address Register PA (24) A-D converter (10) D-A2 converter (8) Instruction Queue Buffer Q8 (8) Instruction Queue Buffer Q9 (8) D-A1 converter (8) Instruction Queue Buffer Q7 (8) (0V) AVSS AVcc Instruction register (8) Instruction Queue Buffer Q6 (8) Input/Output port P3 Instruction Queue Buffer Q5 (8) Input/Output port P7 Input/Output port P8 Timer TB0 (16) Timer TA0 (16) P7(8) Timer TB1 (16) P8(8) Timer TB2 (16) Timer TA1 (16) Vcc Direct Page Register DPR0 (16) Watchdog timer Processor Status Register PS (11) Timer TA4 (16) Input Buffer Register IB (16) Timer TA2 (16) (0V) Vss Data bank Register DT (8) Timer TA3 (16) Program Bank Register PG (8) RAM P10(8) Input/Output port P10 ROM P11(8) Input/Output port P11 Direct Page Register DPR1 (16) RESET Direct Page Register DPR3 (16) Stack Pointer S (16) Clock Generating Circuit XOUT XIN VCONT Clock input Clock output Index Register Y (16) Index Register X (16) Accumulator B (16) Accumulator A (16) Arithmetic Logic Unit (16) Central Processing Unit (CPU) Reset input Direct Page Register DPR2 (16) Fig. 1.4.1 M37902 block diagram 7902 Group User's Manual 1-9 DESCRIPTION 1.4 Block diagram MEMORANDUM 1-10 7902 Group User's Manual CHAPTER 2 CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit (CPU) 2.2 Bus interface unit (BIU) 2.3 Access space 2.4 Memory assignment 2.5 Processor modes [Precautions for setting of processor mode] CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit (CPU) 2.1 Central processing unit (CPU) The CPU (Central Processing Unit) has 13 registers shown in Figure 2.1.1. b8 b7 b15 AH b8 b7 b15 b0 Accumulator A (A) AL b0 BH Accumulator B (B) BL b0 b31 Accumulator E (E) E b8 b7 b15 XH Index register X (X) b8 b7 b15 YH b0 Index register Y (Y) YL b8 b7 b15 SH b7 b0 XL b0 Stack pointer (S) SL b0 Data bank register (DT) DT b23 b16 b15 PG b7 b8 b7 P CH b0 Program counter (PC) P CL b0 Program bank register (PG) b15 b8 b7 DPR0H b15 b8 b7 b15 b8 b7 0 0 0 b0 b8 b7 b10 Direct page register 3 (DPR3) b0 Processor status register (PS) PSL b8 IPL Direct page register 2 (DPR2) DPR3L PSH 0 b0 b8 b7 b15 Direct page register 1 (DPR1) DPR2L DPR3H 0 b0 DPR1L DPR2H b15 Direct page register 0 (DPR0) DPR0L DPR1H b15 b0 b7 b6 b5 b4 b3 b2 b1 b0 N V m x D I Z C Carry flag Zero flag Interrupt disable flag Decimal mode flag Index register length flag Data length flag Overflow flag Negative flag Processor interrupt priority level Fig. 2.1.1 CPU registers 2-2 7902 Group User's Manual CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit (CPU) 2.1.1 Accumulator (Acc) Accumulators A and B are available. Also, accumulators A and B can be connected in series in order to be used as a 32-bit accumulator (accumulator E). (1) Accumulator A (A) Accumulator A is the main register of the microcomputer. The transaction of data such as calculation, data transfer, and input/output are performed mainly through accumulator A. It consists of 16 bits, and the low-order 8 bits can also be used separately. The data length flag (m) determines whether the register is used as a 16-bit register or as an 8-bit register. Flag m is a part of the processor status register, which is described later. When an 8-bit register is selected, only the low-order 8 bits of accumulator A are used, and the contents of the high-order 8 bits is unchanged. (2) Accumulator B (B) Accumulator B is a 16-bit register with the same function as accumulator A. Accumulator B can be used instead of accumulator A. The use of accumulator B, however except for some instructions, requires more instruction bytes and execution cycles than those of accumulator A. Accumulator B is also affected by flag m just as in accumulator A. (3) Accumulator E (E) This 32-bit accumulator consists of accumulator A located in the low-order 16 bits and accumulator B located in the high-order 16 bits. This accumulator is used by an instruction that handles 32-bit data. It is not affected by flag m. 2.1.2 Index register X (X) Index register X consists of 16 bits and the low-order 8 bits can also be used separately. The index register length flag (x) determines whether the register is used as a 16-bit register or as an 8-bit register. Flag x is a part of the processor status register, which is described later. When an 8-bit register is selected, only the low-order 8 bits of index register X are used, and the contents of the high-order 8 bits are not unchanged. In an addressing mode in which index register X is used as an index register, the address obtained by adding the contents of this register to the operand's contents is accessed. Also, each of the MVP, MVN and RMPA instructions uses index register X. Refer to "7900 Series Software Manual" for addressing modes and instructions. 2.1.3 Index register Y (Y) Index register Y is a 16-bit register with the same function as index register X. Just as in index register X, this register is affected by flag X. 7902 Group User's Manual 2-3 CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit (CPU) 2.1.4 Stack pointer (S) The stack pointer (S) is a 16-bit register. It is used for a subroutine call or an interrupt. It is also used when addressing modes using the stack are executed. The contents of S indicate an address (stack area) for storing registers during subroutine calls and interrupts. Bank 016 is specified for the stack area. (Refer to section "2.3 Access space.") When an interrupt request is accepted, the microcomputer stores the contents of the program bank register (PG) at the address indicated by the contents of S and decrements the contents of S by 1. Then the contents of the program counter (PC) and the processor status register (PS) are stored. The contents of S after accepting an interrupt request is equal to the contents of S decremented by 5 before accepting of the interrupt request. (See Figure 2.1.2.) When completing the process in the interrupt routine and returning to the original routine, the contents of Stack area registers stored in the stack area are restored into Address the original registers in the reverse sequence S-5 (PSPCPG) by executing the RTI instruction. The contents of S is returned to the state before accepting S-4 Processor status register's low-order byte (PSL) an interrupt request. S-3 Processor status register's high-order byte (PSH) The same operation is performed during a subroutine Program counter's low-order byte (PCL) S-2 call, however, the contents of PS is not automatically stored. (The contents of PG may not be stored. Program counter's high-order byte (PCH) S-1 This depends on the addressing mode.) Program bank register (PG) S During interrupts or subroutine calls, the other registers are not automatically stored. Therefore, if the contents of these registers need to be held on, "S" is the initial address that the stack pointer (S) indicates at accepting an interrupt request. be sure to store them by software. The S's contents become "S - 5" after storing the Additionally, the S's contents become "0FFF 16 " at above registers. reset. The stack area changes when subroutines are nested or when multiple interrupt requests are accepted. Therefore, make sure of the subroutine's Fig. 2.1.2 Contents of stack area after accepting interrupt request nesting depth not to destroy the necessary data. Refer to "7900 Series Software Manual" for addressing modes and instructions. 2-4 7902 Group User's Manual CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit (CPU) 2.1.5 Program counter (PC) The program counter is a 16-bit counter that indicates the low-order 16 bits of the address (24 bits) at which an instruction to be executed next (in other words, an instruction to be read out from an instruction queue buffer next) is stored. The contents of the high-order program counter (PC H ) become "FF16," and the low-order program counter (PC L) becomes "FE 16" at reset. The contents of the program counter becomes the contents of the reset's vector address (addresses FFFE 16 , FFFF 16) just after reset. Figure 2.1.3 shows the program counter and the program bank register. (b23) b7 (b16) b0 b15 PG b8 b7 PCH b0 PCL Fig. 2.1.3 Program counter and Program bank register 2.1.6 Program bank register (PG) The memory space is divided into units of 64 Kbytes. This unit is called "bank." (Refer to section "2.3 Access space.") The program bank register is an 8-bit register that indicates the high-order 8 bits of the address (24 bits) at which an instruction to be executed next (in other words, an instruction to be read out from an instruction queue buffer next) is stored. These 8 bits indicate a bank. When a carry occurs after adding the contents of the program counter or adding the offset value to the contents of the program counter in the branch instruction and others, the contents of the program bank register is automatically incremented by 1. When a borrow occurs after subtracting the contents of the program counter, the contents of the program bank register is automatically decremented by 1. Therefore, there is no need to consider bank boundaries during programming, usually. This register is cleared to "0016" at reset. 2.1.7 Data bank register (DT) The data bank register is an 8-bit register. In the following addressing modes using the data bank register, the contents of this register is used as the high-order 8 bits (bank) of a 24-bit address to be accessed. Use the LDT instruction when setting a value to this register. This register is cleared to "0016" at reset. Addressing modes using data bank register *Direct indirect *Direct indexed X indirect *Direct indirect indexed Y *Absolute *Absolute indexed X *Absolute indexed Y *Absolute bit relative *Stack pointer relative indirect indexed Y *Multiplied accumulation Refer to "7900 Series Software Manual" for addressing modes. 7902 Group User's Manual 2-5 CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit (CPU) 2.1.8 Direct page register 0 to 3 (DPR0 to DPR3) Each of direct page registers 0 to 3 (hereafter called the "DPRi") is a 16-bit register. The contents of this register specify the direct page area in bank 0 16 or in the space across banks 0 16 and 116 . The following addressing modes use DPRi. The contents of the DPRi indicate the base address (the lowest address) of the direct page area. The direct page area is specified in the space above this address. After reset, whether to use DPR0 only or DPR0 to DPR3 can be selected by the direct page register select bit. (See Figure 2.1.5). This selection specifies the direct page area. Table 2.1.1 lists the selection of the direct page register. Figure 2.1.4 shows setting examples of the direct page area. At reset, DPR0 = "000016 ," and each of DPR1 to DPR3 becomes undefined. Addressing modes using direct page register * Direct * Direct indexed X * Direct indexed Y * Direct indirect * Direct indexed X indirect * Direct indirect indexed Y * Direct indirect long * Direct indirect long indexed Y * Direct bit relative Table 2.1.1 Selection of direct page register Direct page register select bit 0 1 DPR0 DPR0 to DPR3 Usable DPRi 256 bytes 64 bytes at Direct page area each DPRi Refer to "7900 Series Software Manual" for addressing modes and instructions. Direct page register select bit = 0 016 Direct page register select bit = 1 016 016 When DPR0 000016 FF16 Bank 016 12316 When DPR0 012316 When DPR0 FF1016 Bank 016 016 3F16 4016 7F16 80016 83F16 When DPR0 000016 When DPR1 004016 When DPR2 080016 FFD016 1000F16 When DPR3 FFD016 22216 FF1016 FFFF16 1000016 1000F16 Bank 116 FFFF16 1000016 Bank 116 The direct page area is specified in space across banks 016 and 116 when DPR0 is "FF0116" or more. The direct page area is specified in the space across banks 016 and 116 when DPRi is "FFC116" or more. Note: When the low-order 8 bits of DPRi = "00," the number of cycles required for address generation becomes 1 cycle smaller. Fig. 2.1.4 Setting examples of direct page area 2-6 7902 Group User's Manual CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit (CPU) b7 b6 b5 b4 b3 b2 b1 b0 Processor mode register 1 (Address 5F16) Bit Bit name Function At reset R/W 0 External bus cycle select bit 1 (Note 1) The combination of this bit and the external bus cycle select bit 0 selects the bus cycle. 0 : 1 + 1, 1 + 2, 1 + 3, or 2 + 2 1 : 2 + 3, 2 + 4, 3 + 3, or 3 + 4 0 RW 1 Direct page register switch bit 0 : Only DPR0 is used. 1 : DPR0 through DPR3 are used. 0 RW (Note 2) 2 RDY input select bit (Note 3) (Note 4) RW 0 : RDY input is disabled. (P30 functions as a programmable I/O port pin.) (Note 5) 1 : RDY input is enabled. (P30 functions as pin RDY.) 3 ALE output select bit (Note 3) (Note 4) 0 : ALE output is disabled. (P40 functions as a programmable I/O port pin.) 1 : ALE output is enabled. (P40 functions as pin ALE.) 4 Recovery cycle insert select bit 0 : No recovery cycle is inserted at access to external area. (Note 4) RW 1 : Recovery cycle is inserted at access to external area. (Note 3) (Note 4) RW HOLD input, HLDA output select 0 : HOLD input and HLDA output are disabled. 3 and P42 function as programmable I/O port pins.) (Note 5) (P4 bit (Note 3) 1 : HOLD input and HLDA output are enabled. (P43 and P42 function as pins HOLD and HLDA.) 5 6 7 Recovery-cycle-insert number select bit (Note 6) Internal ROM bus cycle select bit (Note 7) RW 0 : 1 cycle 1 : 2 cycles 0 RW 0 : 3 1 : 2 0 RW Notes 1: This bit is valid for the external area except for area CSi. Regardless of these bits' contents, the bus cycle of area CSi is decided by the corresponding area CSi bus cycle select bits 0, 1 (bits 0, 1 at addresses 8016 , 8216, 84 16, 8616 , and bit 3 at addresses 8116 , 8316 , 8516 , 8716). 2: After reset, this bit can be set only once. (During the software execution, be sure not to change this bit's contents.) 3: In the single-chip mode, all of these bits' functions are disabled regardless of these bits' contents. 4: When the Vss-level voltage is applied to pin MD0, this bit is "0"; when the Vcc-level voltage is applied to pin MD0, this bit is "1." 5: After reset, this bit can be set to "1" only once. Once this bit has been cleared from "1" to "0," it cannot be back to "1" again. (Fixed to "0.") 6: Make sure that a program to be used to change this bit's contents is allocated in the internal area. 7: In the microprocessor mode, this bit is invalid. This bit is not assigned to the external ROM version. ("0" at reading.) To reprogram the internal flash memory by using the CPU reprogramming mode, clear this bit to "0." (Refer to section "20.2 Flash memory CPU reprogramming mode.") Fig. 2.1.5 Structure of processor mode register 1 7902 Group User's Manual 2-7 CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit (CPU) 2.1.9 Processor status register (PS) PS is an 11-bit register. Figure 2.1.6 shows the structure of PC. Refer to "7900 Series Software Manual" for detale about the change of each bit. b15 b14 b13 b12 b11 b10 b9 0 0 0 0 0 IPL b8 b7 b6 b5 b4 b3 b2 b1 b0 N V m x D I Z C Processor status register (PS) Note: Be sure to fix bits 15 through 11 to "0." Fig. 2.1.6 Structure of PS (1) Bit 0: Carry flag (C) This flag retains a carry or a borrow generated in the arithmetic and logic unit (ALU) during an arithmetic operation. This flag is also affected by shift and rotate instructions. Be sure to use the SEC or SEP instruction to set this flag to "1"; and be sure to use the CLC or CLP instruction to clear it to "0". The contents of this flag is undefined at reset. (2) Bit 1: Zero flag (Z) This flag is set to "1" when the result of an arithmetic operation or data transfer is "0," and cleared to "0" when otherwise. This flag is invalid in the decimal arithmetic operation. Be sure to use the SEP instruction to set this flag to "1"; and be sure to use the CLP instruction to clear it to "0." The contents of this flag is undefined at reset. (3) Bit 2: Interrupt disable flag (I) This flag disables all maskable interrupts except the following: the address matching detection, NMI, watchdog timer, and 0 division interrupts. Interrupts are disabled when this flag is "1." When an interrupt request has been accepted, this flag is automatically set to "1," and multiple interrupts become disabled. Be sure to use the SEI instruction to set this flag to "1"; and be sure to use the CLI or CLP instruction to clear this flag to "0." This flag is set to "1" at reset. (4) Bit 3: Decimal mode flag (D) This flag determines whether addition and subtraction are performed in binary or decimal. Binary arithmetic operation is performed when this flag is "0." When it is "1," decimal arithmetic operation is performed with each 8 bits treated as 2-digit decimal (at m = 1) or each 16 bits treated as 4-digit decimal (at m = 0). Decimal adjust is automatically performed. Decimal operation is possible only with the ADC, ADCB, SBC and SBCB instructions. Be sure to use the SEP instruction to set this flag to "1"; and be sure to use the CLP instruction to clear it to "0." This flag is cleared to "0" at reset. (5) Bit 4: Index register length flag (x) This flag determines whether each of index register X and index register Y is used as a 16-bit register or an 8-bit register. That register is used as a 16-bit register when this flag is "0," and as an 8-bit register when it is "1" (Note). Be sure to use the SEP instruction to set this flag to "1"; and be sure to use the CLP instruction to clear it to "0." This flag is cleared to "0" at reset. 2-8 7902 Group User's Manual CENTRAL PROCESSING UNIT (CPU) 2.1 Central processing unit (CPU) (6) Bit 5: Data length flag (m) This flag determines whether to use data as a 16-bit unit or as an 8-bit unit. Each data is treated as a 16-bit unit when this flag is "0," and as an 8-bit unit when it is "1" (Note). Be sure to use the SEM or SEP instruction to set this flag to "1," and be sure to use the CLM or CLP instruction to clear it to "0." This flag is cleared to "0" at reset. Note: When transferring data between registers which are different in bit length, this data is transferred with the length of the transfer destination register, except for the case where the TXA, TYA, TXB, TYB, and TXS instructions used. Refer to "7900 series software manual" for detail. (7) Bit 6: Overflow flag (V) This flag is used when addition or subtraction is performed with a word regarded as signed binary. The overflow flag is set to "1" when the result of addition or subtraction exceeds the range between -2147483648 and +2147483647 (when 32-bit length operation), the range between -32768 and +32767 (when 16-bit length operation), or the range between -128 and +127 (when 8-bit length operation). The overflow flag is also set to "1" when the operation result of the DIV or DIVS instruction exceeds the length of the register which will store that result. This flag is invalid in the decimal mode. Be sure to use the SEP instruction to set this flag to "1," and be sure to use the CLV or CLP instruction to clear it to "0." The contents of this flag is undefined at reset. (8) Bit 7: Negative flag (N) This flag is set to "1" when the result of arithmetic operation or data transfer is negative. (The most significant bit of the result is "1.") It is cleared to "0" in all other cases. This flag is invalid in the decimal mode. Be sure to use the SEP instruction to set this flag to "1," and be sure to use the CLP instruction to clear it to "0." The contents of this flag is undefined at reset. (9) Bits 10 to 8: Processor interrupt priority level (IPL) These 3 bits can determine the processor interrupt priority level to one of levels 0 through 7. When the interrupt priority level of a requested interrupt, which has been set in the corresponding interrupt control register, is higher than IPL, that interrupt becomes enabled. When an interrupt request is accepted, IPL is stored in the stack area, and IPL is replaced by the interrupt priority level of the accepted interrupt request. There are no instruction to directly set or clear the bits of IPL. IPL can be changed by storing the new IPL into the stack area and updating PS with the PUL or PLP instruction. The contents of IPL is cleared to "000 2" at reset. 7902 Group User's Manual 2-9 CENTRAL PROCESSING UNIT (CPU) 2.2 Bus interface unit (BIU) 2.2 Bus interface unit The bus interface unit (hereafter called "BIU") performs the following two operations: Instruction prefetch Data transfer (read and write) Figure 2.2.1 shows the bus and BIU. BIU is structured with four kinds of registers shown in Figure 2.2.2. Table 2.2.1 lists the function of the BIU registers. M37902 Internal buses Internal code bus (CB0 to CB31) CPU bus Central processing unit (CPU) Bus interface unit (BIU) Internal data bus (DB0 to DB15) Internal address bus (AD0 to AD23) Internal memory Internal control signal Internal peripheral devices (SFR) External buses A0 to A23 Bus conversion circuit Hold request D0 to D7 (LA0 to LA7) D8 to D15 Control signals HOLD HLDA SFR : Special Function Register Notes 1: The CPU bus, internal bus, and external bus are independent of one another. 2: Refer to "CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES" about the signals of the external buses. Fig. 2.2.1 Bus and BIU 2-10 7902 Group User's Manual External devices CENTRAL PROCESSING UNIT (CPU) 2.2 Bus interface unit (BIU) b0 b23 PA Program address register b7 b0 Q0 Instruction queue buffer Q9 b23 b0 DA b31 Data address register b0 DB Data buffer Fig. 2.2.2 BIU registers' structure Table 2.2.1 Functions of BIU registers Name Functions Program Indicates a storage address of the address instruction to be fetched into an register instruction queue buffer, next. Instruction Temporarily stores an instruction queue buffer which has been fetched. Data address Indicates an address from which data register will be read or to which data will be written, next. Data buffer Temporarily stores data which has been read from memory*I/O device by BIU or which will be written to memory*I/O device by the CPU. In the M37902, the internal buses are used when the CPU accesses the internal area (the internal memory and SFR) or the external area (the external devices). 2.2.1 Instruction prefetch While the CPU does not use the internal buses, the BIU reads instructions from the memory and then stores them in the instruction queue buffer. The CPU reads instructions from the instruction queue buffer and executes them, so that the CPU can operate at high speed without access to the memory, which requires a long access time. The instruction queue buffer can store instructions up to ten bytes. The contents of the instruction queue buffer is initialized when a branch is made, and the BIU reads a new instruction from the branch destination address. When instructions in the instruction queue buffer are insufficient for the CPU's needs, the BIU extends the low-level duration of CPU (See Figure 5.2.1.) in order to keep the CPU waiting until the BIU fetches instructions of the required byte number or more. The operation of instruction prefetch is determined whether instructions are fetched from the internal memory or external memory. Figure 2.2.3 shows operating waveform examples at instruction prefetch. Note that the operation of BIU's instruction prefetch also vary with the store addresses of instructions. Table 2.2.2 lists the store address of prefetched instructions. Table 2.2.2 Store address of prefetched instruction Low-order 3 bits at store address Even-numbered address 4-byte boundaries 8-byte boundaries AD 2 (A2) 0 AD 1 (A1) 0 0 AD 0(A0) 0 0 0 X: It may be "0" or "1." (1) Instruction prefetch from internal memory Instructions are fetched from 4-byte boundaries, 4 bytes at a time. (See Figure 2.2.3-(a).) Also, at branch, regardless of the low-order 2 bits' contents (AD 1 and AD 0) of the branch destination address, 4 bytes are fetched at at time from the 4-byte boundaries. (See Figure 2.2.3 (a).) In this case, out of the data (instructions) which will be output onto the internal code buses, 4 bytes at a time, the instructions assigned at the branch destination address and the following addresses will be fetched into the instruction queue buffer. Accordingly, as listed in Table 2.2.3, the number of bytes to be fetched into the instruction queue buffer varies according to the branch destination address. 7902 Group User's Manual 2-11 CENTRAL PROCESSING UNIT (CPU) 2.2 Bus interface unit (BIU) Table 2.2.3 Number of bytes to be fetched into instruction queue buffer Low-order 2 bits of branch destination address AD1 (A 1) AD0 (A 0) 0 0 0 1 1 0 1 1 Low-order 2 bits of address to be output onto address bus AD1 (A 1) 0 0 0 0 AD0 (A 0) 0 0 0 0 Number of bytes to be fetched into instruction queue buffer 4 3 2 1 (2) Instruction prefetch from external memory With external data bus width = 16 bits (BYTE = Vss level) 8 bytes are fetched at a time from 8-byte boundaries. (See Figure 2.2.3-(b): 4 successive accesses). At branch, regardless of the low-order 2 bits' contents (A 1, A 0) of the branch destination address, 4 bytes are fetched at a time from 4-byte boundaries. (See Figure 2.2.3-(c): 2 successive accesses). At this time, the number of prefetched bytes varies according to the branch destination address. The operations succeedingly performed vary according to the address to be fetched next, as follows: * When the address is at an 8-byte boundary, 8 bytes will be fetched from the next time. (See Figure 2.2.3-(b): 4 successive accesses). * When the address is at a 4-byte boundary, 4 bytes will be fetched. (See Figure 2.2.3-(c): 2 successive accesses). Then, from the next time, 8 bytes will be fetched. (See Figure 2.2.3(b): 4 successive accesses). With external data bus width = 8 bits (BYTE = Vcc level) 4 bytes are fetched at a time from 4-byte boundaries. (See Figure 2.2.3-(b): 4 successive accesses). At branch, when the branch destination is at an even-numbered address, 2 bytes are fetched from even-numbered addresses; when the branch destination is at an odd-numbered address, 2 bytes are fetched from the address given by (odd-numbered address - 1). (See Figure 2.2.3 (c): 2 successive accesses); The operations succeedingly performed vary according to the address to be fetched next, as follows: * When the address is at a 4-byte boundary, 4 bytes will be fetched from the next time. (See Figure 2.2.3-(b): 4 successive accesses). * When the address is at an even-numbered one, 2 bytes will be fetched. (See Figure 2.2.3(c) : 2 successive accesses). Then, from the next time, 4 bytes will be fetched. (See Figure 2.2.3-(b): 4 successive accesses). 2-12 7902 Group User's Manual CENTRAL PROCESSING UNIT (CPU) 2.2 Bus interface unit (BIU) (a) BIU Internal address bus (AD0-AD23) Address Internal code bus (CB0-CB31) Data (instruction) BIU: Operation clock of BIU (Refer to "CHAPTER 5. CLOCK GENERATING CIRCUIT.") (b) 1 RD External address bus (A0-A23) Address Address Address Address External data bus (D0-D7) (Note 1) Data (instruction) Data (instruction) Data (instruction) Data (instruction) External data bus (D8-D15) Data (instruction) Data (instruction) Data (instruction) Data (instruction) (c) 1 RD External address bus (A0-A23) External data bus (D0-D7) (Note 1) External data bus (D8-D15) Address Address Data (instruction) Data (instruction) Data (instruction) Data (instruction) Notes 1: When the external data bus width = 8 bits (BYTE = Vcc), external data bus D 0 to D 7 is used only. 2: Waveform (a) applies when bus cycle = 2. For details of the bus cycle at access to the internal area, see Table 2.2.4. Waveforms (b) and (c) apply when bus cycle = 1 + 1 at normal access. For any of the bus cycle, recovery cycle, and burst ROM access at access to the external area, refer to "CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES." Fig. 2.2.3 Waveform examples at instruction prefetch 7902 Group User's Manual 2-13 CENTRAL PROCESSING UNIT (CPU) 2.2 Bus interface unit (BIU) 2.2.2 Data Transfer (read and write) When the CPU reads or writes data from or to the internal/external area, it requests the BIU to read or write data. The BIU outputs control signals in order to control the internal address and data buses in response to the request from the CPU. The cycle where the following are performed is referred to "bus cycle": * The BIU controls buses. * Data transfer is performed between the external and internal areas. Table 2.2.4 lists the bus cycles at access to the internal area. For details of bus cycles and each signal at access to the external area, refer to "CHAPTER. 3 CONNECTION WITH EXTERNAL DEVICES." Figure 2.2.4 shows operating waveform examples at reading from or writing to the internal area. Figures 2.2.5 and 2.2.6 show operating waveform examples at reading from and writing to the external area. (1) Reading data The CPU informs the BIU's data address register of the address where the data to be read is stored, so the CPU requests the data. In this case, the CPU waits until the requested data is ready in the BIU. The BIU outputs the address informed by the CPU onto the internal address bus. Then, the CPU reads the contents of the informed address and takes them into the data buffer. The CPU continues processing using data in the data buffer. (2) Writing data The CPU informs the BIU's data address register of the address to which the data will be written, so the CPU writes the data into the data buffer. The BIU outputs the address informed by the CPU onto the internal address bus. Then, the BIU writes the data in the data buffer into the informed address. Table 2.2.4 Bus cycles at access to internal area Bus cycle = 3 (Note) Bus cycle = 2 (Internal ROM bus cycle select bit = 0) (Internal ROM bus cycle select bit = 1) 1 bus cycle = 2 1 bus cycle = 3 BIU ROM Internal address bus Internal data bus BIU Internal address bus Address Internal data bus Data Address Data 1 bus cycle = 2 RAM BIU Internal address bus SFR Address Internal data bus Data Internal ROM bus cycle select bit: Bit 7 at address 5F 16 Note: When reprogramming the internal flash memory in the CPU reprogramming mode, be sure to select bus cycle = 3. (Refer to section "20.2 Flash memory CPU reprogramming mode.") 2-14 7902 Group User's Manual CENTRAL PROCESSING UNIT (CPU) 2.2 Bus interface unit (BIU) (a) When accessing 8-bit data (Note 1) or accessing 16-bit data starting from an even-numbered address BIU Internal address bus (AD0 -AD23) Internal data bus (DB0-DB7) Internal data bus (DB8-DB15) Address RD (even) WD (even) RD (odd) Note 1: When reading 8-bit data at an even-numbered address, only RD (even) will be taken into an instruction queue buffer. When reading 8-bit data at an odd-numbered address, only RD (odd) will be taken into an instruction queue buffer. When writing 8-bit data to an even-numbered address, only WD (even) will be written to an instruction queue buffer. When writing 8-bit data to an odd-numbered address, only WD (odd) will be written to an instruction queue buffer. WD (odd) (b) When accessing 16-bit data starting from an odd-numbered address BIU Internal address bus (AD0-AD23) Address Address + 1 RD (even) Internal data bus (DB0-DB7) Internal data bus (DB8-DB15) WD (even) RD (odd) WD (odd) (c) When accessing 32-bit data starting from an even-numbered address BIU Internal address bus (AD0-AD23) Internal data bus (DB0-DB7) Internal data bus (DB8-DB15) Address Address + 2 RD (even) WD (even) RD (even) WD (even) RD (odd) WD (odd) RD (odd) WD(odd) (d) When accessing 32-bit data starting from an odd-numbered address BIU Internal address bus (AD0-AD23) Address Address + 1 RD (even) Internal data bus (DB0-DB7) Internal data bus (DB8-DB15) Address + 3 WD (even) RD (odd) WD (odd) RD (even) WD (even) RD (odd) WD (odd) RD: Data to be read, WD: Data to be written Note 2: The above waveforms apply when bus cycle = 2. For the bus cycles at access to the internal area, see Table 2.2.4. Fig. 2.2.4 Operating waveform examples at reading from or writing to internal area 7902 Group User's Manual 2-15 CENTRAL PROCESSING UNIT (CPU) 2.2 Bus interface unit (BIU) When the external data bus width = 16 bits (BYTE = VSS level) (a) When accessing 16-bit data starting from an even-numbered address < At reading > < At writing > 1 1 External address bus ( A0-A23 ) External address bus (A0-A23) Address Address External data bus ( D0-D7 ) RD (even) External data bus (D0-D7) WD (even) External data bus ( D8-D15 ) RD (odd) External data bus (D8-D15) WD (odd) RD BLW BHW RD H H BLW H BHW (b) When accessing 16-bit data starting from an odd-numbered address or accessing 8-bit data < At reading > < At writing > 1 1 External address bus (A0-A23) Address External data bus (D0-D7) External data bus (D8-D15) External address bus (A0-A23) Address + 1 RD (even) Invalid External data bus (D8-D15) RD (odd) RD RD BLW BHW Address External data bus (D0-D7) H Address + 1 WD (even) WD (odd) H BLW H BHW 16-bit data access starting from an odd-numbered address 16-bit data access starting from odd-numbered address 8-bit data access to odd-numbered address 8-bit data access to 8-bit data access to odd-numbered even-numbered address address 8-bit data access to even-numbered address (c) When accessing 32-bit data starting from an even-numbered address < At reading > < At writing > 1 1 External address bus (A0-A23) Address External address bus (A0-A23) Address + 2 Address Address + 2 External data bus (D0-D7) RD (even) RD (even) External data bus (D0-D7) WD (even) WD (even) External data bus (D8-D15 ) RD (odd) RD (odd) External data bus (D8-D15) WD (odd) WD (odd) H RD BLW BHW RD H BLW H BHW (d) When accessing 32-bit data starting from odd-numbered address < At reading > < At writing > 1 1 External address bus (A0-A23) Address Address + 1 Address + 3 External address bus (A0-A23) External data bus (D0-D7) Invalid RD (even) RD (even) External data bus (D0-D7) External data bus (D8-D15) RD (odd) RD (odd) Invalid External data bus (D8-D15) BHW Address + 1 Address + 3 WD (even) WD (odd) WD (odd) H RD BLW Address RD H BLW H BHW RD: Data to be read, WD: Data to be written Invalid: Invalid data. At reading, this data is not taken into a data buffer. Note: The above waveforms apply when bus cycle = 1 + 1 at normal access. For any of the bus cycle, recovery cycle, and burst ROM access, refer to "CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES." Fig. 2.2.5 Operating waveform examples at reading from or writing to external area (1) 2-16 7902 Group User's Manual WD (even) CENTRAL PROCESSING UNIT (CPU) 2.2 Bus interface unit (BIU) When the external data bus width = 8 bits (e) When accessing 8-, 16-, 32-bit data BYTE = Vcc level < At reading > < At writing > 1 1 External address bus (A0-A23) Address External data bus (D0-D7) Address + 1 RD Address + 2 RD RD Address + 3 RD Address External data bus (D0-D7) Address + 1 WD Address + 2 WD WD Address + 3 WD H RD BLW External address bus (A0-A23) RD H BLW 8-bit data access 8-bit data access 16-bit data access 16-bit data access 32-bit data access 32-bit data access BYTE = Vcc level and the external data bus width select bit (bit 2 at addresses 8216, 8416, 8616) = 1 < At reading > < At writing > 1 1 External address bus (A0-A23) Address External data bus (D0-D7) Address + 1 RD Address + 2 RD RD Address + 3 RD External address bus (A0-A23) External data bus (D0-D7) Address Address + 1 WD Address + 2 WD WD Address + 3 WD H RD RD H BLW BLW H H BHW BHW 8-bit data access 8-bit data access 16-bit data access 16-bit data access 32-bit data access 32-bit data access RD: Data to be read, WD: Data to be written Notes 1: When BYTE = Vcc level, D8 to D15 and BHW serve as programable I/O port pins (P2 and P33). 2: The above waveforms apply when bus cycle = 1 + 1 at normal access. For any of the bus cycle, recovery cycle, and burst ROM access, refer to "CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES." Fig. 2.2.6 Operating waveform examples at reading from or writing to external area (2) 7902 Group User's Manual 2-17 CENTRAL PROCESSING UNIT (CPU) 2.3 Access space 2.3 Access space The memory space of the M37902 is assigned to a 16-Mbyte space from addresses 0 16 to FFFFFF 16. (See Figure 2.3.1.) Note that, however, addresses FF0000 16 to FFFFFF 16 cannot be used because this area is reserved. The space of 15.9 Mbytes (addresses from 016 through FEFFFF16 ) can be accessed by combination of the program counter (PC), which consists of 16 bits, and the program bank register (PG). Refer to "CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES" about the access to the external area. The memory and I/O devices are assigned in the same access space. Accordingly, it is possible to perform transfer and arithmetic operations using the same instructions, without discrimination of the memory from I/O devices. 016 FF16 SFR area Internal RAM area (Note 1) Bank 016 FFFF16 1000016 Internal ROM area (Note 2) Bank 116 2000016 FE000016 * * * * * * * * Bank FE16 : Memory assignment of internal area FEFFFF16 FF000016 : Nothing is assigned. Reserved area FFFFFF16 Bank FF16 : Reserved area (Do not use.) Notes 1: When the internal RAM area is followed by an unused area or an external area, do not assign a program to the last 8 bytes of the internal RAM area. 2: Do not assign a program to the last 8 bytes of the internal ROM area. 3: The memory assignment of the internal area varies according to the product type. Refer to section "Appendix 12. Memory assignment of 7902 Group," or the latest datasheets, catalogs. SFR : Special Function Register Fig. 2.3.1 M37902's access space 2-18 7902 Group User's Manual CENTRAL PROCESSING UNIT (CPU) 2.4 Memory assignment 2.4 Memory assignment This section describes the memory assignment in the internal area. For more information about the external area, refer to "2.5 Processor modes," also. 2.4.1 Memory assignment in internal area SFR (Special Function Register), internal RAM, and internal ROM are assigned to the internal area. Figure 2.4.1 shows the memory assignment in the internal area. (1) SFR area The registers used to set the internal peripheral devices are assigned to addresses 0 16 to FF16. This area is called SFR. Figures 2.4.2 shows the SFR area's memory assignment. For each register in the SFR area, refer to each functional description in this manual. For the state of the SFR area immediately after reset, refer to section "4.3 State of internal area." (2) Internal RAM area The internal RAM area is used as a stack area, as well as an area to store data. Accordingly, be sure to set the nesting depth of a subroutine and multiple interrupts' level not to destroy the necessary data. When the internal RAM area is followed by an unused area or an external area, do not assign a program to the last 8 bytes of the internal RAM area. (Data is allowed to be assigned there. Also, when the internal RAM area is followed by the internal ROM area succeedingly, a program is allowed to be assigned there.) (3) Internal ROM area Addresses FFC0 16 to FFFF 16 are the vector addresses for reset and interrupts. (This is called the interrupt vector table.) For the external ROM version or the microcomputers in the microprocessor mode, where the internal ROM area cannot be used, be sure to assign a ROM to addresses FFC0 16 to FFFF 16. Do not assign a program to the last 8 bytes of the internal ROM area. (Data is allowed to be assigned there.) 7902 Group User's Manual 2-19 CENTRAL PROCESSING UNIT (CPU) 2.4 Memory assignment 016 FF16 SFR area AE See Fig.2.4.2. Interrupt vector table FFC016 FFC216 FFC416 FFC616 Internal RAM area FFC816 FFCA16 FFCC16 FFCE16 FFD016 FFD216 FFD416 FFD616 FFD816 FFDA16 FFDC16 FFDE16 FFE016 FFE216 Internal ROM area FFE416 FFE616 FFE816 FFEA16 FFEC16 FFEE16 FFF016 FFF216 FFF416 FFC016 FFF616 FFF816 FFFA16 FFFC16 FFFE16 FFFF16 L H L Reserved area H L Reserved area H L Reserved area H L Reserved area H L Address matching detection H L Reserved area H L Reserved area H L INT4 H L INT3 H L A-D conversion H L UART1 transmit H L UART1 receive H L UART0 transmit H L UART0 receive H L Timer B2 H L Timer B1 H L Timer B0 H L Timer A4 H L Timer A3 H L Timer A2 H L Timer A1 H L Timer A0 H L INT2 H L INT1 H L INT0 H L NMI H L Watchdog timer H L DBC (Note 1) H L BRK instruction (Note 1) H L Zero divide H L RESET H Reserved area : The internal memory is not assigned Notes 1: These are interrupts only for debugging; do not use these interrupts. 2: The access to the internal area is disabled in the microprocessor mode. (Refer to section "2.5 Processor modes"). 3: Memory assignment in the internal area varies according to the type of microcomputer. Refer to section "Appendix 12. Memory assignment of 7902 Group" or the latest catalogues, datasheets. Fig. 2.4.1 Memory assignment in internal area 2-20 7902 Group User's Manual CENTRAL PROCESSING UNIT (CPU) 2.4 Memory assignment Address 016 116 216 316 416 516 616 716 816 916 A16 B16 C16 D16 E16 F16 1016 1116 1216 1316 1416 1516 1616 1716 1816 1916 1A16 1B16 1C16 1D16 1E16 1F16 2016 2116 2216 2316 2416 2516 2616 2716 2816 2916 2A16 2B16 2C16 2D16 2E16 2F16 3016 3116 3216 3316 3416 3516 3616 3716 3816 3916 3A16 3B16 3C16 3D16 3E16 3F16 (Note 1) (Note 1) Port P0 register Port P1 register Port P0 direction register Port P1 direction register Port P2 register Port P3 register Port P2 direction register Port P3 direction register Port P4 register Port P5 register Port P4 direction register Port P5 direction register Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register Port P8 direction register Port P10 register Port P11 register Port P10 direction register Port P11 direction register A-D control register 0 A-D control register 1 A-D register 0 A-D register 1 A-D register 2 A-D register 3 A-D register 4 A-D register 5 A-D register 6 A-D register 7 UART0 transmit/receive mode register UART0 baud rate register (BRG0) UART0 transmit buffer register UART0 transmit/receive control register 0 UART0 transmit/receive control register 1 UART0 receive buffer register UART1 transmit/receive mode register UART1 baud rate register (BRG1) UART1 transmit buffer register UART1 transmit/receive control register 0 UART1 transmit/receive control register 1 UART1 receive buffer register Address 4016 4116 4216 4316 4416 4516 4616 4716 4816 4916 4A16 4B16 4C16 4D16 4E16 4F16 5016 5116 5216 5316 5416 5516 5616 5716 5816 5916 5A16 5B16 5C16 5D16 5E16 5F16 6016 6116 6216 6316 6416 6516 6616 6716 6816 6916 6A16 6B16 6C16 6D16 6E16 6F16 7016 7116 7216 7316 7416 7516 7616 7716 7816 7916 7A16 7B16 7C16 7D16 7E16 7F16 Count start flag One-shot start flag Up-down flag AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA Timer A clock division select register Timer A0 register Timer A1 register Timer A2 register Timer A3 register Timer A4 register Timer B0 register Timer B1 register Timer B2 register Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Processor mode register 0 Processor mode register 1 Watchdog timer register Watchdog timer frequency select register Particular function select register 0 Particular function select register 1 Particular function select register 2 (Note 2) Debug control register 0 Debug control register 1 Address compare register 0 (Note 3) Address compare register 1 (Note 3) INT3 interrupt control register INT4 interrupt control register A-D conversion interrupt control register UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register INT2 interrupt control register Address 8016 CS0 control register L 8116 CS0 control register H 8216 CS1 control register L 8316 CS1 control register H 8416 CS2 control register L 8516 CS2 control register H 8616 CS3 control register L 8716 CS3 control register H 8816 8916 8A16 Area CS0 start address register 8B16 8C16 Area CS1 start address register 8D16 8E16 Area CS2 start address register 8F16 9016 Area CS3 start address register 9116 9216 Port function select register 9316 9416 External interrupt input control register 9516 External interrupt input read register 9616 D-A control register 9716 9816 D-A register 0 9916 D-A register 1 9A16 D-A register 2 9B16 9C16 (Note 2) 9D16 (Note 2) 9E16 Flash memory control register (Note 4) 9F16 A016 Realtime output control register A116 A216 Pulse output data register 0 A316 A416 Pulse output data register 1 A516 A616 A716 A816 A916 AA16 AB16 AC16 Serial I/O pin control register AD16 AE16 AF16 B016 B116 B216 B316 B416 B516 B616 B716 B816 B916 BA16 (Note 2) BB16 (Note 2) BC16 Clock control register BD16 (Note 2) BE16 (Note 2) BF16 (Note 2) Notes 1: Do not read out and write to. 2: Do not write to. 3: In order to access these registers, be sure to set the address compare register access enable bit (bit 2 at address 6716) to "1." (Refer to "CHAPTER 18. DEBUG FUNCTION.") 4: This register is assigned only in the flash memory version. (Refer to "CHAPTER 20. FLASH MEMORY VERSION.") Do no write to this register in the mask ROM version and external ROM version. Fig. 2.4.2 SFR area's memory map 7902 Group User's Manual 2-21 CENTRAL PROCESSING UNIT (CPU) 2.5 Processor modes 2.5 Processor modes The M37902 can operate in three processor modes: single-chip mode, memory expansion mode, and microprocessor mode (Note). Some pins' functions, memory assignment, and access space vary according to the processor mode. This section describes the differences according to the processor mode. Figure 2.5.1 shows the memory assignment in each processor mode. Note: The external ROM version can operate only in the microprocessor mode. Single-chip mode Memory expansion mode SFR area SFR area SFR area Internal RAM area (Note 1) Internal RAM area (Note 1) Microprocessor mode 016 FF16 Unused area Internal RAM area (Note 1) Unused area Internal ROM area (Note 2) Internal ROM area (Note 2) FEFFFF16 FF000016 FFFFFF16 Reserved area (Note 3) Reserved area (Note 3) : This is an external area. The access to this area enables the access to an externally-connected device. Notes 1: When the internal RAM area is followed by an unused area or an external area, do not assign a program to the last 8 bytes of the internal RAM area. 2: Do not assign a program to the last 8 bytes of the internal ROM area. 3: Do not access this area. 4: The memory assignment of the internal area varies according to the product type. Refer to section "Appendix 12. Memory assignment of 7902 Group," or the latest datasheets, catalogs. Fig. 2.5.1 Memory assignment in each processor mode 2-22 7902 Group User's Manual CENTRAL PROCESSING UNIT (CPU) 2.5 Processor modes Figure 2.5.2 shows the pin configuration in each processor mode. 2.5.1 Single-chip mode This mode is used when not connecting an external device with buses. In this mode, ports P0 to P8, P10, P11 serve as programmable I/O port pins. (When an internal peripheral device is used, they serve as corresponding I/O pins). In this mode, only the internal area (SFR, internal RAM, and internal ROM) can be accessed. 2.5.2 Memory expansion and Microprocessor modes Each of these modes is used when connecting an external device with buses. In these modes, an external device can be connected to any required location in the 15.9-Mbyte access space. Also, some programmable I/O port pins serve as the I/O pins of signals required for the access to the external devices. For the access to external devices, refer to "CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES." The memory expansion and microprocessor modes have the same functions except for the following: In the microprocessor mode, the access to the internal ROM area is forcedly disabled, and this internal ROM area is handled as an external area. If an external device is allocated to an area which overlaps with the internal area, the following are performed: When this overlapped area is read out, data in the internal area will be taken into the CPU, but data in the external area will not be taken in. When data is written to an overlapped area, the data will be written to the internal area, and the data will not be output to the external. For each pin's function, refer to section "1.3 Pin description," "CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES," "CHAPTER 5. CLOCK GENERATING CIRCUIT," "CHAPTER 6. INPUT/OUTPUT PINS," and each internal peripheral function's description (chapters 7 through 14). 7902 Group User's Manual 2-23 1 2-24 4 7902 Group User's Manual Fig. 2.5.2 Pin configuration in each processor mode (top view) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 NMI P80/CTS0/RTS0/DA2/INT3 P77/AN7/ADTRG/DA1/(INT2) P76/AN6/DA0 P75/AN5/(INT4) P74/AN4/(INT3) P73/AN3 5 P86/RXD1 P85/CTS1/CLK1 P84/CTS1/RTS1/INT4 P83/TXD0 P82/RXD0 P81/CTS0/CLK0 VCC AVCC VREF AVSS VSS 3 A0 P87/TXD1 2 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 A1 A2 A3 A4 A5 A6 A7 P110/A8 P111/A9 P112/A10 P113/A11 P114/A12 P115/A13 P116/A14 P117/A15 P00/A16 P01/A17 P02/A18 P03/A19 P04/A20 P05/A21 P06/A22 P07/A23 VSS MD1 D0/LA0 D1/LA1 D2/LA2 D3/LA3 D4/LA4 n P33/BHW BLW RD P72/AN2 P71/AN1 P70/AN0 P67/TB2IN P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/RTP13/KI3 P56/TA3OUT/RTP12/KI2 P55/TA2IN/RTP11/KI1 P54/TA2OUT/RTP10/KI0 P53/TA1IN/RTP03 P52/TA1OUT/RTP02 P51/TA0IN/RTP01 P50/TA0OUT/RTP00 P47/CS3 P46/CS2 P45/CS1 P44/CS0 P43/HOLD P42/HLDA P41/f 1 P40/ALE P40 P33 P32 P31 P72/AN2 P71/AN1 P70/AN0 P67/TB2IN P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/RTP13/KI3 P56/TA3OUT/RTP12/KI2 P55/TA2IN/RTP11/KI1 P54/TA2OUT/RTP10/KI0 P53/TA1IN/RTP03 P52/TA1OUT/RTP02 P51/TA0IN/RTP01 P50/TA0OUT/RTP00 P47 P46 P45 P44 P43 P42 P41/f 1 1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 P100 P87/TXD1 P86/RXD1 P85/CTS1/CLK1 P84/CTS1/RTS1/INT4 P83/TXD0 P82/RXD0 P81/CTS0/CLK0 VCC AVCC VREF AVSS VSS NMI P80/CTS0/RTS0/DA2/INT3 P77/AN7/ADTRG/DA1/(INT2) P76/AN6/DA0 P75/AN5/(INT4) P74/AN4/(INT3) P73/AN3 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 MD1 P10 P11 P12 P13 P14 P101 P102 P103 P104 P105 P106 P107 P110 P111 P112 P113 P114 P115 P116 P117 P00 P01 P02 P03 P04 P05 P06 P07 VSS n 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 CENTRAL PROCESSING UNIT (CPU) 2.5 Processor modes Single-chip mode P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 VCC XOUT XIN VSS MD0 RESET VCONT BYTE P30 Each function of these pins in the single-chip mode is different from that in the memory expansion or microprocessor mode. Memory expansion and Miocroprocessor modes D5/LA5 D6/LA6 D7/LA7 P20/D8 P21/D9 P22/D10 P23/D11 P24/D12 P25/D13 P26/D14 P27/D15 VCC XOUT XIN VSS MD0 RESET VCONT BYTE P30/RDY Each function of these pins in the single-chip mode is different from that in the memory expansion or microprocessor mode. Outline: 100P6S-A CENTRAL PROCESSING UNIT (CPU) 2.5 Processor modes 2.5.3 Setting of processor mode The processor mode is set by the following: * Voltage level applied to the MD0 pin * Processor mode bits (bits 1 and 0 at address 5E16 ) Note: While the microcomputer is operating, do not switch the voltage level applied to the MD0 pin. (1) When Vss level is applied to MD0 pin After reset, the microcomputer starts its operation in the single-chip mode. After the operation starts, the processor mode can be switched by the processor mode bits. When the processor mode bits = "012," the microcomputer enters the memory expansion mode; when these bits = "10 2," the microcomputer enters the microprocessor mode. When the processor mode has been switched during the program execution, the contents of the instruction queue buffer will not be initialized. (Refer to section "Appendix 8. 7902 Group Q & A.") (2) When Vcc level is applied to MD0 pin After reset, the microcomputer starts its operation in the microprocessor mode. In this case, the microcomputer cannot operate in any of the other modes. (Fix the processor mode bits = "10 2.") Table 2.5.1 lists the setting methods for processor modes. Figure 2.5.3 shows the structure of processor mode register 0 (address 5E 16). Table 2.5.1 Setting methods for setting processor mode Processor mode Single-chip mode Memory expansion mode Microprocessor mode Voltage level at MD0 pin Vss (Note 1) Vss (Note 1) Vss (Note 1) Processor mode bits b1 b0 0 0 0 1 1 0 Vcc (Note 2) Notes 1: After reset, the microcomputer starts its operation in the single-chip mode. The processor mode can be switched to another processor mode by the processor mode bits. 2: After reset, the microcomputer starts its operation in the microprocessor mode. The microcomputer cannot operate in any of the other processor modes, so be sure that the processor mode bits are fixed as follows: b1 = "1" and b0 = "0." 7902 Group User's Manual 2-25 CENTRAL PROCESSING UNIT (CPU) 2.5 Processor modes b7 b6 b5 b4 b3 b2 b1 b0 Processor mode register 0 (Address 5E16) Bit Bit name 0 Processor mode bits Function At reset R/W 0 RW (Note 1) RW 0 RW 1 RW Interrupt priority detection time b5 b4 0 0 : 7 cycles of fsys select bits 0 1 : 4 cycles of fsys 1 0 : 2 cycles of fsys 1 1 : Do not select. 0 RW 0 RW 6 Software reset bit The microcomputer is reset by writing "1" to this bit. The value is "0" at reading. 0 WO 7 Clock 1 output select bit 0 : 1 output is disabled. (P41 functions as a (Note 3) programmable I/O port pin.) 1 : 1 output is enabled. (P41 functions as a clock 1 output pin.) 1 2 External bus cycle select bit 0 (Note 2) 3 4 5 b1 b0 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode 1 1 : Do not select. (External bus cycle select (External bus cycle select bit 1 = 0) bit 1 = 1) b3 b2 b3 b2 0 0 : 1 + 1 0 1 : 1 + 2 1 0 : 1 + 3 1 1 : 2 + 2 0 0 : 2 + 3 0 1 : 2 + 4 1 0 : 3 + 3 1 1 : 3 + 4 RW Notes 1: When the Vss-level voltage is applied to pin MD0, this bit is "0"; when the Vcc-level voltage is applied to pin MD0, this bit is "1." (Fixed to "1.") 2: These bits are valid for the external area except for area CSi. Regardless of these bits' contents, the bus cycle of area CSi is decided by the corresponding area CSi bus cycle select bits 0, 1 (bits 0, 1 at addresses 8016, 82 16, 8416 , 8616 , and bit 3 at addresses 8116 , 8316 , 8516 , 8716). 3: When the Vss-level voltage is applied to pin MD0, this bit is "0"; when the Vcc-level voltage is applied to pin MD0, this bit is "1." Fig. 2.5.3 Structure of processor mode register 0 2-26 7902 Group User's Manual CENTRAL PROCESSING UNIT (CPU) [Precautions for setting of processor mode] [Precautions for setting of processor mode] Only the microprocessor mode is available for the external ROM version. Therefore, for the external ROM version, do as follows: * The MD0 pin must be connected to Vcc. * The processor mode bits (bits 0 and 1 at address 5E16 ) must be fixed to "10 2." 7902 Group User's Manual 2-27 CENTRAL PROCESSING UNIT (CPU) [Precautions for setting of processor mode] MEMORANDUM 2-28 7902 Group User's Manual CHAPTER 3 CONNECTION WITH EXTERNAL DEVICES 3.1 Signals required for accessing external devices 3.2 Chip select wait controller [Precautions for CSWC] 3.3 Ready function 3.4 Hold function CONNECTION WITH EXTERNAL DEVICES 3.1 Signals required for accessing external devices This chapter explains the functions for connection with external devices. The bus interface unit (BIU) controls the following. (Refer to section "2.2 Bus interface unit (BIU).": * Reading data from devices connected externally * Writing data to devices connected externally The bus cycle at access to external devices can be changed by the chip select wait controller (CSWC) and Ready function. Also, by Hold function, buses can be opened to the external. 3.1 Signals required for accessing external devices 52 51 53 54 55 56 57 59 58 61 60 63 62 64 65 67 66 68 69 70 71 72 73 75 25 24 23 22 21 20 19 17 18 16 15 14 P53/TA1IN/RTP03 P52/TA1OUT/RTP02 P51/TA0IN/RTP01 P50/TA0OUT/RTP00 P47/CS3 P46/CS2 P45/CS1 P44/CS0 P43/HOLD P42/HLDA P41/1 P40/ALE 13 12 11 10 9 8 7 6 5 4 3 2 P70/AN0 P67/TB2IN P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/RTP13/KI3 P56/TA3OUT/RTP12/KI2 P55/TA2IN/RTP11/KI1 P54/TA2OUT/RTP10/KI0 1 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A3 A2 A1 A0 P87/TXD1 P86/RXD1 P85/CTS1/CLK1 P84/CTS1/RTS1/INT4 P83/TXD0 P82/RXD0 P81/CTS0/CLK0 VCC AVCC VREF AVSS VSS NMI P80/CTS0/RTS0/DA2/INT3 P77/AN7/ADTRG/DA1/(INT2) P76/AN6/DA0 P75/AN5/(INT4) P74/AN4/(INT3) P73/AN3 P72/AN2 P71/AN1 74 A4 A5 A6 A7 P110/A8 P111/A9 P112/A10 P113/A11 P114/A12 P115/A13 P116/A14 P117/A15 P00/A16 P01/A17 P02/A18 P03/A19 P04/A20 P05/A21 P06/A22 P07/A23 VSS MD1 D0/LA0 D1/LA1 D2/LA2 When connecting devices externally, make sure that the microcomputer operates in the memory expansion or microprocessor mode. (Refer to section "2.5 Processor modes.") While the microcomputer operates in one of these modes, a part of programmable I/O port pins serve as I/O pins of signals required for accessing external devices. Figure 3.1.1 shows the pin configuration in the memory expansion and microprocessor modes, Figure 3.1.2 shows the external area, Table 3.1.1 lists the pins used for accessing external devices. D3/LA3 D4/LA4 D5/LA5 D6/LA6 D7/LA7 P20/D8 P21/D9 P22/D10 P23/D11 P24/D12 P25/D13 P26/D14 P27/D15 VCC XOUT XIN VSS MD0 RESET VCONT BYTE P30/RDY RD BLW P33/BHW When BYTE = VCC, P20 to P27 When BYTE = VSS, D8 to D15 When BYTE = VCC, P3 When BYTE = VSS, BHW Outline: 100P6Q-A Fig. 3.1.1 Pin configuration in memory expansion and microprocessor modes (Top view) 3-2 7902 Group User's Manual CONNECTION WITH EXTERNAL DEVICES 3.1 Signals required for accessing external devices Memory expansion mode Microprocessor mode 016 SFR area SFR area Internal RAM area (Note 1) Internal RAM area (Note 1) FF16 Internal ROM area (Note 2) FEFFFF16 FF000016 FFFFFF16 Reserved area Reserved area (Note 3) (Note 3) External area : Access to this area enables the access to the devices which are connected with the external. Notes 1: When the internal RAM area is followed by an external area, do not assign a program to the last 8 bytes of the internal RAM area. 2: Do not assign a program to the last 8 bytes of the internal ROM area. 3: Do not access this area. 4: The memory map of the internal area depends on the devices type. Therefore, for details, refer to section "Appendix 12. Memory assignment of 7902 Group," the latest datasheets, and catalogs. Fig. 3.1.2 External area 7902 Group User's Manual 3-3 CONNECTION WITH EXTERNAL DEVICES 3.1 Signals required for accessing external devices Table 3.1.1 Pins used for accessing external devices Pin A 0-A23 D0-D7 Access to external devices External data bus width = 16 bits (BYTE = Vss level) External data bus width = 8 bits (BYTE = Vcc level) Access to internal devices Address (A0-A23 ) output pins Undefined (Note 1). (Note 2) I/O pins for data (D0-D7) at an even- I/O pins for data (D0-D7) Floating. numbered address D8-D15 I/O pins for data (D8-D15) at an odd- Programmable I/O port pins (P2) Floating. numbered address (Note 4) (Note 3) RD Input pin for signals related to Ready function (Refer to section "3.3 Ready function.") Invalid. Output pin for read singnal ("L" level is output while data bus is read out.) "H" level is output. BLW Output pin for write signal ("L" level Output pin for write signal ("L" level is output while data is written to an is output while data is written to the even-numbered address.) external area.) Output pin for write signal ("L" level Programmable I/O port pin (P3 3) RDY BHW is output while data is written to an "H" level is output. "H" level is output. (Note 4) odd-numbered address.) (Note 5) ALE Output pin for address latch enable signal (This pin indicates address "L" level is output. stabilization and can be used to latch an address.) 1 Clock 1 output pin (This pin outputs a signal with the same period of fsys. Refer to "CHAPTER 5. CLOCK GENERATING CIRCUIT.") HOLD Input pin for signals related to Hold function (Refer to section "3.4 Hold function.") Invalid. Output pin for signals related to Hold function (Refer to section "3.4 Hold function.") "H" level is output. HLDA Chip select output pins (Refer to section "3.2 Chip select wait controller.") "H" level is output. (Note 6) External data bus width select input pin (When VSS level is input, 16-bit width is selected; When V CC level is input, 8-bit width is selected.) CS 0-CS3 BYTE Notes 1: Address outputs at access to internal areas can be fixed by software. (Refer to section "3.2.4 Address output selection.") 2: When area CS2 is accessed with the external data bus width = 8 bits, by software, the address output (LA0-LA 7) and the data input/output (D0-D7) can be performed with the time-sharing method. (Refer to section "3.2.2 External bus operations.") 3: When an area with the external data bus width = 8 bits is accessed by software, these pins are placesd in the floating state. (See Figure 2.2.6.) 4: This applies only when the external data bus width = 16 bits (BYTE = Vss level). 5: When an area with the external data bus width = 8 bits is accessed by software, "H" level is output. (See Figure 2.2.6.) 6: Do not change the input level to this pin while the microcomputer is operating. The data bus width selected by the input to pin BYTE is valid only for the external areas. (See Figure 3.1.2.) When an internal area is accessed, the data bus width is always fixed to 16 bits. When BYTE = Vss, the external data bus width of 8 bits can independently be selected by software for each of areas CS1-CS 3. (Refer to section "3.2 Chip select wait controller.") 7: For details of each signal and input/output timings, refer to each reference and section "Appendix 9. M37902FGCGP electrical characteristics" and "Appendix 10. M37902FGMHP electrical characteristics." 3-4 7902 Group User's Manual CONNECTION WITH EXTERNAL DEVICES 3.1 Signals required for accessing external devices The pins required for accessing external devices are explained below: (1) In order to switch the processor mode from the single-chip mode to memory expansion or microprocessor mode after reset with Vss applied to pin MD0, specify the function of the related pins by using the following bits. (Reset with MD0 = Vss makes these pins to be programmable I/O port pins). * Pin RDY: RDY input select bit (bit 2 at address 5F 16 ) * Pin ALE : ALE output select bit (bit 3 at address 5F 16 ) * Pin 1 : clock 1 output select bit (bit 7 at address 5E 16) * pins HOLD, HLDA : HOLD input, HLDA output select bit (bit 5 at address 5F 16 ) * Pins CS0-CS 3: CS 0 output select bit (bit 7 at address 80 16 ) CS 1 output select bit (bit 7 at address 82 16 ) CS 2 output select bit (bit 7 at address 84 16 ) CS 3 output select bit (bit 7 at address 86 16 ) (2) Switches between addresses and ports The address/port switch bits switch between addresses A8-A23 and ports P0, P11 (See Figure 3.1.3.), so that address output pins not needed can be used as programmable I/O port pins, according to the access space required. (Refer to section "2.3 Access space.") (3) Pullups of P44 (CS 0)-P47 (CS 3) While pin RESET = "L" level and after reset, pins P4 4 (CS 0)-P4 7 (CS 3) are pulled up. Therefore, external pullup resistors are not needed for these pins. Setting the pins P4 4-P4 7 pullup select bit to "1" removes the pullups. (See Figure 3.1.3.) Either of the following settings also removes the pullups regardless of the contents of the pins P4 4- P4 7 pullup select bit. (The bit's contents remain unchanged). * Setting the port direction register corresponding to P4 4-P47 to "1" (output mode). * Setting the CS0-CS 3 output select bits (bit 7 at addresses 8016 , 8216 , 8416 , and 86 16) corresponding to P44 (CS0)-P4 7 (CS 3) to "1" (CS 0-CS 3 outputs enabled). Note that P44-P4 7 in the flash memory parallel I/O mode (MD1 and MD0 = Vcc), and CS 0 (P44) in the microprocessor mode (MD1 = Vss and MD0 = Vcc) will not be pulled up regardless of the pins P44- P4 7 pullup select bit. For details of the flash memory parallel I/O mode, refer to section "20.4 Flash memory parallel I/O mode." 7902 Group User's Manual 3-5 CONNECTION WITH EXTERNAL DEVICES 3.1 Signals required for accessing external devices b7 b6 b5 b4 b3 b2 b1 b0 Port function control register (Address 9216) Bit Bit name 0 Address/Port switch select bits 1 2 3 Port P0 input level select bit 4 P44-P47 pullup select bit 6, 5 7 0 0 Function At reset R/W 0 0 0 : A0 to A23 (16 Mbytes) 0 0 1 : A0 to A21, P06, P07 (4 Mbytes) 0 1 0 : A0 to A19, P04 to P07 (1 Mbytes) 0 1 1 : A0 to A17, P02 to P07 (256 Kbytes) 1 0 0 : A0 to A15, P00 to P07 (64 Kbytes) 1 0 1 : Do not select. 1 1 0 : A0 to A11, P00 to P07, P114 to P117 (4 Kbytes) 1 1 1 : A0 to A7, P00 to P07, P110 to P117 (256 bytes) 0 : VIH = 0.7 VCC, VIL = 0.2 VCC 1 : VIH = 0.43 VCC (Note 1), VIL = 0.16 VCC 0 RW 0 RW 0 RW 0 RW 0 : P44 to P47 are pulled up. 1 : P44 to P47 are not pulled up. 0 RW 0 RW 0 RW b2 b1 b0 (Notes 2 and 3) Fix these bit s to "1." Pin NMI pullup connection select bit 0 : Pin NMI is pulled up. 1 : Pin NMI is not pulled up. (Note 2) Notes 1: For the M37902FxMHP (power source voltage = 3.3 V0.3 V), VIH = 0.5 VCC. 2: When MD1 = VCC and MD0 = VCC (flash memory parallel I/O mode), pins P44 to P47 and NMI are not pulled up, regardless of these bits' contents. 3: When MD1 = VSS and MD0 = VCC (microprocessor mode), pin CS0 (P44) is not pulled up, regardless of the bits' contents. Fig. 3.1.3 Structure of port function control register 3-6 7902 Group User's Manual CONNECTION WITH EXTERNAL DEVICES 3.2 Chip select wait controller 3.2 Chip select wait controller The chip select wait controller (CSWC) controls the bus cycle at access to the external areas. By CSWC, the chip select areas (CS 0-CS 3) of the maximum of 4 blocks can be set in the address space from banks 0 16 through FE16. (See Figures 3.2.10 to 3.2.12). For each chip select area, the functions listed in Table 3.2.1 can be specified. For the external areas except for areas CS 0-CS 3, the functions listed in Table 3.2.1 can also be specified. Table 3.2.1 Functions of areas CS 0 through CS 3 CS 0 Mode 0 Mode 1 Bank 016 Space where start Banks 2 16 address can be set to FE 16 Block size 128 Kbytes, 128 Kbytes, 256 Kbytes, 256 Kbytes, 512 Kbytes, 512 Kbytes, 1 Mbytes, 1 Mbytes, 2 Mbytes, 2 Mbytes, 4 Mbytes, 4 Mbytes, or 8 Mbytes or 8 Mbytes Bus cycle Bus cycle *1 + 1 *1 + 2 *1 + 3 *2 + 2 *2 + 3 *2 + 4 *3 + 3 *3 + 4 (Selected by bits 0, 1 at address 80 16 and bit 3 at address 81 16.) CS 1, CS 2 Mode 0 Mode 1 Banks 216 Bank 016 to FE16 128 Kbytes, 4 Kbytes, 256 Kbytes, or 8 Kbytes 512 Kbytes, 1 Mbytes, 2 Mbytes, 4 Mbytes, or 8 Mbytes Bus cycle *1 + 1 *1 + 2 *1 + 3 *2 + 2 *2 + 3 *2 + 4 *3 + 3 *3 + 4 (Selected by bits 0, 1 at addresses 8216, 84 16 and bit 3 at addresses 8316, 85 16.) CS 3 External area except for CS0 to CS3 RDY control Valid (Selected by bit 2 at address Valid (Selected by bit 2 at address 5F16 and bit 3 at address 8016 .) 5F16 and bit 3 at addresses 82 16 , 8416.) Burst ROM access (Notes 2, 3) Recovery cycle insertion Area multiplexed bus access (Note 3) Address output selection (Note 5) Available. Available. Banks 2 16 to FE16 128 Kbytes, 256 Kbytes, 512 Kbytes, 1 Mbytes, 2 Mbytes, 4 Mbytes, or 8 Mbytes Bus cycle *1 + 1 *1 + 2 *1 + 3 *2 + 2 *2 + 3 *2 + 4 *3 + 3 *3 + 4 (Selected by bits 0, 1 at address 8616 and bit 3 at address 8716.) When BYTE = VSS level, 8-bit width or 16-bit width can be selected arbitrary (Note 1). Valid (Selected by bit 2 at address 5F16 and bit 3 at address 8616.) Available. Available. Available. Available. Available. Not available. CS1: Not available. CS 2: Available. (Note 4) Available. Not available. Not available. Available. Available. External data bus Determined by pin BYTE's level. When BYTE = VSS level, 8-bit width or width 16-bit width can be selected arbitrary (Note 1). Notes 1: 2: 3: 4: 5: Available. Bus cycle *1 + 1 *1 + 2 *1 + 3 *2 + 2 *2 + 3 *2 + 4 *3 + 3 *3 + 4 (Selected by bits 2, 3 at address 5E16 and bit 0 at address 5F16.) Determined by pin BYTE's level. Valid (Selected by bit 2 at address 5F16.) Not available. When BYTE = Vcc level, the external data bus width is fixed to 8 bits. Burst ROM access is valid only when the external data bus width is 16 bits with instruction prefetched. Burst ROM access and area multiplexed bus access cannot be used at the same time. Valid only when area CS 2 is accessed with the 8-bit external data bus width. The address output selection cannot be specified for each area. (Refer to section "3.2.4 Address output selection.") 7902 Group User's Manual 3-7 CONNECTION WITH EXTERNAL DEVICES 3.2 Chip select wait controller 3.2.1 Related registers The related registers are explained below. (1) Processor mode register 0 Figure 3.2.1 shows the structure of the processor mode register 0. b7 b6 b5 b4 b3 b2 b1 b0 Processor mode register 0 (Address 5E16) Bit Bit name 0 Processor mode bits 1 2 External bus cycle select bit 0 (Note 2) 3 4 5 Function b1 b0 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode 1 1 : Do not select. (External bus cycle select (External bus cycle select bit 1 = 0) bit 1 = 1) b3 b2 b3 b2 0 0 : 1 + 1 0 1 : 1 + 2 1 0 : 1 + 3 1 1 : 2 + 2 0 0 : 2 + 3 0 1 : 2 + 4 1 0 : 3 + 3 1 1 : 3 + 4 Interrupt priority detection time b5 b4 0 0 : 7 cycles of fsys select bits 0 1 : 4 cycles of fsys 1 0 : 2 cycles of fsys 1 1 : Do not select. At reset R/W 0 RW (Note 1) RW 0 RW 1 RW 0 RW 0 RW 0 WO 6 Software reset bit The microcomputer is reset by writing "1" to this bit. The value is "0" at reading. 7 Clock 1 output select bit 0 : 1 output is disabled. (P41 functions as a (Note 3) programmable I/O port pin.) 1 : 1 output is enabled. (P41 functions as a clock 1 output pin.) RW Notes 1: When the Vss-level voltage is applied to pin MD0, this bit is "0"; when the Vcc-level voltage is applied to pin MD0, this bit is "1." (Fixed to "1.") 2: These bits are valid for the external area except for area CSi. Regardless of these bits' contents, the bus cycle of area CSi is decided by the corresponding area CSi bus cycle select bits 0, 1 (bits 0, 1 at addresses 8016, 82 16, 8416 , 8616 , and bit 3 at addresses 8116 , 8316 , 8516 , 8716). 3: When the Vss-level voltage is applied to pin MD0, this bit is "0"; when the Vcc-level voltage is applied to pin MD0, this bit is "1." Fig. 3.2.1 Structure of processor mode register 0 External bus cycle select bit 0 (bits 2, 3) The combination of this bit and the external bus cycle select bit 1 (bit 0 at address 5F 16 ) selects the bus cycle at access to the external areas except for areas CS 0-CS3. (Refer to section "3.2.2 External bus operations.") 3-8 7902 Group User's Manual CONNECTION WITH EXTERNAL DEVICES 3.2 Chip select wait controller (2) Processor mode register 1 Figure 3.2.2 shows the structure of the processor mode register 1. b7 b6 b5 b4 b3 b2 b1 b0 Processor mode register 1 (Address 5F16) Bit Bit name Function At reset R/W 0 External bus cycle select bit 1 (Note 1) The combination of this bit and the external bus cycle select bit 0 selects the bus cycle. 0 : 1 + 1, 1 + 2, 1 + 3, or 2 + 2 1 : 2 + 3, 2 + 4, 3 + 3, or 3 + 4 0 RW 1 Direct page register switch bit 0 : Only DPR0 is used. 1 : DPR0 through DPR3 are used. 0 RW (Note 2) 2 RDY input select bit (Note 3) (Note 4) RW 0 : RDY input is disabled. (Note 5) (P30 functions as a programmable I/O port pin.) 1 : RDY input is enabled. (P30 functions as pin RDY.) 3 ALE output select bit (Note 3) (Note 4) 0 : ALE output is disabled. (P40 functions as a programmable I/O port pin.) 1 : ALE output is enabled. (P40 functions as pin ALE.) 4 Recovery cycle insert select bit 0 : No recovery cycle is inserted at access to external area. (Note 4) RW 1 : Recovery cycle is inserted at access to external area. (Note 3) (Note 4) RW HOLD input, HLDA output select 0 : HOLD input and HLDA output are disabled. 3 and P42 function as programmable I/O port pins.) (Note 5) (P4 bit (Note 3) 1 : HOLD input and HLDA output are enabled. (P43 and P42 function as pins HOLD and HLDA.) 5 6 7 Recovery-cycle-insert number select bit (Note 6) Internal ROM bus cycle select bit (Note 7) RW 0 : 1 cycle 1 : 2 cycles 0 RW 0 : 3 1 : 2 0 RW Notes 1: This bit is valid for the external area except for area CSi. Regardless of these bits' contents, the bus cycle of area CSi is decided by the corresponding area CSi bus cycle select bits 0, 1 (bits 0, 1 at addresses 8016 , 8216, 84 16, 8616 , and bit 3 at addresses 8116 , 8316 , 8516 , 8716). 2: After reset, this bit can be set only once. (During the software execution, be sure not to change this bit's contents.) 3: In the single-chip mode, all of these bits' functions are disabled regardless of these bits' contents. 4: When the Vss-level voltage is applied to pin MD0, this bit is "0"; when the Vcc-level voltage is applied to pin MD0, this bit is "1." 5: After reset, this bit can be set to "1" only once. Once this bit has been cleared from "1" to "0," it cannot be back to "1" again. (Fixed to "0.") 6: Make sure that a program to be used to change this bit's contents is allocated in the internal area. 7: In the microprocessor mode, this bit is invalid. This bit is not assigned to the external ROM version. ("0" at reading.) To reprogram the internal flash memory by using the CPU reprogramming mode, clear this bit to "0." (Refer to section "20.2 Flash memory CPU reprogramming mode.") Fig. 3.2.2 Structure of processor mode register 1 7902 Group User's Manual 3-9 CONNECTION WITH EXTERNAL DEVICES 3.2 Chip select wait controller External bus cycle select bit 1 (bit 0) The combination of this bit and the external bus cycle select bit 0 (bits 2, 3 at address 5E16) selects the bus cycle at access to the external areas except for areas CS0 to CS 3. (Refer to section "3.2.2 External bus operations.") RDY input select bit (bit 2) This bit selects whether the RDY input is enabled or not. Setting this bit to "1" enables the RDY control at access to the external areas except for areas CS 0 to CS 3. To validate the RDY control at the access to any of areas CS 0 to CS3, set this bit to "1" and clear the corresponding RDY control bit for areas CS 0 to CS 3 (bit 3 at address 8016 , 8216 , 8416, or 86 16) to "0." Recovery cycle insert select bit (bit 4) This bit decides whether recovery cycles are inserted or not at access to the external areas except for areas CS0 to CS3. Setting this bit to "1" inserts such recovery cycles as 1 or 2 cycles of 1 after the bus cycle for access to an external area. The number of recovery cycles to be inserted is specified by the recovery-cycle-insert number select bit (bit 6). Insertion of recovery cycles allows devices with longer output disable time at read to be connected without using bus buffers. Since addresses are maintained throughout recovery cycles, devices requiring longer address hold time can easily be connected; on the other hand, by inserting 2 recovery cycles to extend the data hold time at write by 1 cycle of 1, devices requiring longer data hold time can also be connected. (Refer to section "3.2.2 External bus operations.") Recovery-cycle-insert number select bit (bit 6) This bit selects the number of recovery cycles to be inserted. 1 and 2 cycles are selectable. The number of recovery cycles selected by this bit is valid for all of the external areas including areas CS 0 to CS 3. To insert recovery cycles, each recovery cycle insert select bit for each area (bit 4 at address 5F 16 and bit 6 at address 8016 , 8216 , 8416 , or 86 16 ) must be set to "1." Make sure that a program to be used to change this bit's contents is allocated in the internal area. 3-10 7902 Group User's Manual CONNECTION WITH EXTERNAL DEVICES 3.2 Chip select wait controller (3) CS 0 control register L Figure 3.2.3 shows the structure of the CS0 control register L. b7 b6 b5 b4 b3 b2 b1 b0 CS0 control register L (Address 8016 ) Bit Bit name Function At reset R/W 0 Area CS0 bus cycle select bit 0 (Area CS 0 bus cycle select (Area CS0 bus cycle select bit 1 = 0) bit 1 = 1) 0 RW 1 RW (Note 1) RO 0 RW 1 b1 b0 b1 b0 0 0 : 1 + 1 0 1 : 1 + 2 1 0 : 1 + 3 1 1 : 2 + 2 0 0 : 2 + 3 0 1 : 2 + 4 1 0 : 3 + 3 1 1 : 3 + 4 2 External data bus width select bit The input level at pin BYTE is read out. 0 : 16-bit width 1 : 8-bit width 3 RDY control bit 4 The value is "0" at reading. 0 -- 5 Burst ROM access select bit 0 : Normal access (Note 3) 1 : Burst ROM access 0 RW 6 Recovery cycle insert select bit 1 RW 7 CS0 output select bit (Note 2) 0 : RDY control is valid. 1 : RDY control is invalid. 0 : No recovery cycle is inserted at access to area CS0. 1 : Recovery cycle is inserted at access to area CS0. (Note 4) 0 : CS 0 output is disabled. (P4 4 functions as a (Note 5) programmable I/O port pin.) 1 : CS0 output is enabled. (P44 functions as pin CS0.) RW Notes 1: This bit is "0" when Vss-level voltage is applied to pin BYTE; this bit is "1" when Vcc-level voltage is applied. 2: This bit is valid when the RDY input select bit (bit 2 at address 5F16 ) is "1." 3: When Vcc-level voltage is applied to pin BYTE, "normal access" is selected regardless of this bit's value. 4: This bit's contents are invalid in the single-chip mode. (CS0 output disabled) 5: This bit is "0" when Vss-level voltage is applied to pin MD0; this bit is "1" when Vcc-level voltage is applied. (Fixed to "1.") Fig. 3.2.3 Structure of CS 0 control register L 7902 Group User's Manual 3-11 CONNECTION WITH EXTERNAL DEVICES 3.2 Chip select wait controller Area CS0 bus cycle select bit 0 (bits 0, 1) The combination of this bit and the area CS 0 bus cycle select bit 1 (bit 3 at address 81 16) selects the bus cycle at access to area CS0. (Refer to section "3.2.2 External bus operations.") External data bus width select bit (bit 2) Reading this bit informs the input level at pin BYTE. The external data bus width at access to area CS 0 is decided by the input level at pin BYTE. (When BYTE = Vss level, 16-bit width; when BYTE = Vcc level, 8-bit width.) RDY control bit (bit 3) This bit decides whether the RDY control is valid or not at access to area CS0. While the RDY input select bit (bit 2 at address 5F 16) = "1," this bit is valid. (Refer to section "3.3 Ready function.") Burst ROM access select bit (bit 5) When ROM, etc., supporting burst access, is allocated to area CS 0, the burst access for the maximum of 8 bytes becomes available if this bit is set to "1." The burst ROM access is valid only when the external data bus width = 16 bits with instructions prefetched. When the external data bus width = 8 bits or when data is read or written, "normal access" is specified regardless of this bit's contents. (Refer to section "3.2.2 External bus operations.") Recovery cycle insert select bit (bit 6) This bit decides whether recovery cycles are inserted or not at access to area CS 0. Setting this bit to "1" inserts such recovery cycles as 1 or 2 cycles of 1 after the bus cycle for access to area CS 0. The number of recovery cycles to be inserted is selected by the recovery-cycle-insert number select bit (bit 6 at address 5F16 ). Insertion of recovery cycles allows devices with longer output disable time at read to be connected without using bus buffers. Since addresses are maintained throughout recovery cycles, devices requiring longer address hold time can easily be connected; on the other hand, by inserting 2 recovery cycles to extend the data hold time at write by 1 cycle of 1, devices requiring longer data hold time can also be connected. (Refer to section "3.2.2 External bus operations.") CS 0 output select bit (bit 7) Setting this bit to "1" outputs a chip select signal at access to area CS0. Even though this bit has been cleared to "0" in order to disable CS 0 output, setting for each function of area CS 0 (See Table 3.2.1.) is valid if the area CS 0 block size select bits (bits 2 to 0 at address 8116 ) are not "0002" (in other words, area CS0 is invalid.) Moreover, even when area CS 0 is invalid, setting this bit to "1" validates pin CS 0. ("H" level is output.) 3-12 7902 Group User's Manual CONNECTION WITH EXTERNAL DEVICES 3.2 Chip select wait controller (4) CS 0 control register H Figure 3.2.4 shows the structure of the CS0 control register H. b7 b6 b5 b4 b3 b2 b1 b0 CS0 control register H (Address 8116 ) Bit 0 At reset R/W 0 0 0 : 0 byte (Area CS0 is invalid.) 0 0 1 : 128 Kbytes 0 1 0 : 256 Kbytes 0 1 1 : 512 Kbytes 1 0 0 : 1 Mbytes 1 0 1 : 2 Mbytes 1 1 0 : 4 Mbytes 1 1 1 : 8 Mbytes 1 RW 0 RW 0 RW The combination of this bit and the area CS0 bus cycle select bit 0 selects the bus cycle. 0 : 1 + 1, 1 + 2, 1 + 3, or 2 + 2 1 : 2 + 3, 2 + 4, 3 + 3, or 3 + 4 0 RW The value is "0" at reading. 0 -- Area CS0 setting mode select bit 0: Mode 0 (A block can be set to 16-Mbyte space.) 1: Mode 1 (Area CS0 start address is set in bank 0.) 1 RW Ares CS0 block size select bits 1 2 3 6 to 4 7 Function Bit name Area CS0 bus cycle select bit 1 b2 b1 b0 Fig. 3.2.4 Structure of CS 0 control register H Area CS0 block size select bit (bits 2 to 0) These bits select the block size of area CS0. Clearing these bits to "0002" invalidates area CS 0. When the block size has been selected, area CS 0 becomes valid, and setting for each function of area CS0 is valid, regardless of the CS0 output select bit (bit 7 at address 8016). (See Table 3.2.1.) Area CS0 bus cycle select bit 1 (bit 3) The combination of this bit and the area CS 0 bus cycle select bit 0 (bits 0, 1 at address 80 16 ) selects the bus cycle at access to area CS 0. (Refer to section "3.2.2 External bus operations.") Area CS 0 setting mode select bit (bit 7) This bit selects the setting mode of the block size. For details of area CS0, see Figures 3.2.10 and 3.2.11. 7902 Group User's Manual 3-13 CONNECTION WITH EXTERNAL DEVICES 3.2 Chip select wait controller (5) CS j control register L Figure 3.2.5 shows the structure of the CS j (j = 1 to 3) control register L. CS1 control register L (Address 8216 ) CS2 control register L (Address 8416 ) CS3 control register L (Address 8616 ) Bit 0 Bit name Area CSj bus cycle select bit 0 (j = 1 to 3) 1 2 b7 b6 b5 b4 b3 b2 b1 b0 Function At reset R/W (Area CSj bus cycle select (Area CSj bus cycle select bit 1 = 0) bit 1 = 1) 0 RW 1 RW 0 RW 0 RW 0 -- b1 b0 b1 b0 0 0 : 1 + 1 0 1 : 1 + 2 1 0 : 1 + 3 1 1 : 2 + 2 0 0 : 2 + 3 0 1 : 2 + 4 1 0 : 3 + 3 1 1 : 3 + 4 External data bus width select bit 0 : 16-bit width 1 : 8-bit width (Note 1) 3 RDY control bit 4 The value is "0" at reading. 5 Burst ROM access select bit (Note 3) 0 : Normal access 1 : Burst ROM access 0 RW 6 Recovery cycle insert select bit 0 : No recovery cycle is inserted with area CSj selected. 1 : Recovery cycle is inserted with area CSj selected. 1 RW 7 CSj output select bit (j = 1 to 3) 0 : CS j output is disabled. (P4 5 to P47 function as programmable I/O port pins.) 1 : CSj output is enabled. (P45 to P47 function as pin CSj .) 0 RW (Note 2) (Note 4) 0 : RDY control is valid. 1 : RDY control is invalid. Notes 1: This bit is fixed to "1" (8-bit width) when Vcc-level voltage is applied to pin BYTE. 2: Valid when the RDY input select bit (bit 2 at 5F16 ) is "1." 3: When the external data bus width select bit (bit 2) is "1" or when Vcc-level voltage is applied to pin BYTE, "normal access" is selected regardless of this bit's value. 4: This bit's value is invalid in the single-chip mode. (CSj output is disabled.) Fig. 3.2.5 Structure of CSj (j = 1 to 3) control register L 3-14 7902 Group User's Manual CONNECTION WITH EXTERNAL DEVICES 3.2 Chip select wait controller Area CSj bus cycle select bit 0 (bits 0, 1) The combination of this bit and the area CS j bus cycle select bit 1 (bit 3 at addresses 8316 , 8516 , 8716) selects the bus cycle at access to area CSj. (Refer to section "3.2.2 External bus operations.") External data bus width select bit (bit 2) When the input level at pin BYTE = Vss level, this bit can arbitrarily select the external data bus width at access to area CS j. When the input level at pin BYTE = Vcc level, the external data bus width = 8 bits regardless of this bit's contents. RDY control bit (bit 3) This bit decides whether the RDY control is valid or not at access to area CSj. While the RDY input select bit (bit 2 at address 5F16 ) = "1," this bit is valid. (Refer to section "3.3 Ready function.") Burst ROM access select bit (bit 5) When ROM, etc., supporting burst access, is allocated to area CSj, the burst access for the maximum of 8 bytes becomes available if this bit is set to "1." The burst ROM access is valid only when the external data bus width = 16 bits with instructions prefetched. When the external data bus width = 8 bits or when data is read or written, "normal access" is specified regardless of this bit's contents. (Refer to section "3.2.2 External bus operations.") Recovery cycle insert select bit (bit 6) This bit decides whether recovery cycles are inserted or not at access to area CSj. Setting this bit to "1" inserts such recovery cycles as 1 or 2 cycles of 1 after the bus cycle for accessing area CS j. The number of recovery cycles to be inserted is selected by the recovery-cycle-insert number select bit (bit 6 at address 5F16 ). Insertion of recovery cycles allows devices with longer output disable time at read to be connected without using bus buffers. Since addresses are maintained throughout recovery cycles, devices requiring longer address hold time can easily be connected; on the other hand, by inserting 2 recovery cycles to extend the data hold time at write by 1 cycle of 1, devices requiring longer data hold time can also be connected. (Refer to section "3.2.2 External bus operations.") CS j output select bit (bit 7) Setting this bit to "1" outputs a chip select signal at access to area CSj. Even though clearing this bit to "0" in order to disable CSj output, setting for each function of area CS j (See Table 3.2.1.) is valid if the area CSj block size select bits (bits 2 to 0 at addresses 8316 , 8516 , 8716 ) are not "0002" (in other words, area CSj is invalid.) Moreover, even when area CS j is invalid, setting this bit to "1" validates pin CS j. ("H" level is output.) 7902 Group User's Manual 3-15 CONNECTION WITH EXTERNAL DEVICES 3.2 Chip select wait controller (6) CS 1 control register H Figure 3.2.6 shows the structure of the CS1 control register H. b7 b6 b5 b4 b3 b2 b1 b0 CS1 control register H (Address 8316) Bit 0 0 Bit name Area CS1 block size select bits 1 2 Function At reset R/W (Mode 1) (Mode 0) 0 0 0 : 0 byte (Area CS1 is invalid.) 0 byte (Area CS1 is invalid.) 0 0 1 : 128 Kbytes Do not select. 0 1 0 : 256 Kbytes Do not select. 0 1 1 : 512 Kbytes Do not select. 1 0 0 : 1 Mbytes 4 Kbytes 1 0 1 : 2 Mbytes 8 Kbytes 1 1 0 : 4 Mbytes Do not select. 1 1 1 : 8 Mbytes Do not select. 0 RW 0 RW 0 RW The combination of this bit and the area CS 1 bus cycle select bit 0 selects the bus cycle. 0 : 1 + 1, 1 + 2, 1 + 3, or 2 + 2 1 : 2 + 3, 2 + 4, 3 + 3, or 3 + 4 0 RW b2 b1 b0 3 Area CS1 bus cycle select bit 1 4 The value is "0" at reading. 0 -- 5 Fix this bit to "0." 0 RW 6 The value is "0" at reading. 0 -- 7 Area CS1 setting mode select bit 0 RW 0 : Mode 0 (A block can be set to 16-Mbyte space.) 1 : Mode 1 (A block can be set to bank 0.) Fig. 3.2.6 Structure of CS1 control register H Area CS1 block size select bit (bits 2 to 0) These bits select the block size of area CS 1. Clearing these bits to "000 2" invalidates area CS1. When the block size has been selected, area CS 1 becomes valid and setting for each function of area CS 1 becomes valid, regardless of the CS 1 output select bit (bit 7 at address 82 16). (See Table 3.2.1.) Area CS1 bus cycle select bit 1 (bit 3) The combination of this bit and the area CS 1 bus cycle select bit 0 (bits 0, 1 at address 8216 ) selects the bus cycle at access to area CS 1. (Refer to section "3.2.2 External bus operations.") Area CS 1 setting mode select bit (bit 7) This bit selects the setting mode of the block size. For details of area CS 1, see Figures 3.2.10 and 3.2.12. 3-16 7902 Group User's Manual CONNECTION WITH EXTERNAL DEVICES 3.2 Chip select wait controller (7) CS 2 control register H Figure 3.2.7 shows the structure of the CS2 control register H. b7 b6 b5 b4 b3 b2 b1 b0 CS2 control register H (Address 85 16) Bit 0 Bit name Area CS2 block size select bits 1 2 3 Area CS2 bus cycle select bit 1 4 The value is "0" at reading. 5 Multiplexed bus select bit 6 The value is "0" at reading. 7 Area CS2 setting mode select bit Function At reset R/W (Mode 1) (Mode 0) 0 0 0 : 0 byte (Area CS2 is invalid.) 0 byte (Area CS2 is invalid.) 0 0 1 : 128 Kbytes Do not select. 0 1 0 : 256 Kbytes Do not select. 0 1 1 : 512 Kbytes Do not select. 1 0 0 : 1 Mbytes 4 Kbytes 1 0 1 : 2 Mbytes 8 Kbytes 1 1 0 : 4 Mbytes Do not select. 1 1 1 : 8 Mbytes Do not select. 0 RW 0 RW 0 RW The combination of this bit and the area CS 2 bus cycle select bit 0 selects the bus cycle. 0 : 1 + 1, 1 + 2, 1 + 3, or 2 + 2 1 : 2 + 3, 2 + 4, 3 + 3, or 3 + 4 0 RW 0 -- 0 RW 0 -- 0 RW b2 b1 b0 0 : Separated bus. Input/Output for D0-D7. 1 : Multiplexed bus. LA0/D 0-LA7 /D7 are input/output when the external data bus = 8 bits (bit 2 at address 8416 = 1) with area CS2 accessed. 0 : Mode 0 (A block can be set to 16-Mbyte space.) 1 : Mode 1 (A block can be set to bank 0.) Fig. 3.2.7 Structure of CS 2 control register H Area CS2 block size select bit (bits 2 to 0) These bits select the block size of area CS2. Clearing these bits to "0002" invalidates area CS 2. When the block size has been selected, area CS 2 becomes valid and setting for each function of area CS 2 becomes valid, regardless of the CS 2 output select bit (bit 7 at address 8416 ). (See Table 3.2.1.) Area CS2 bus cycle select bit 1 (bit 3) The combination of this bit and the area CS 2 bus cycle select bit 0 (bits 0, 1 at address 84 16 ) selects the bus cycle at access to area CS 2. (Refer to section "3.2.2 External bus operations.") Multiplexed bus select bit (bit 5) Setting this bit to "1" performs the following with the time-sharing method only when area CS 2 is accessed with the external data bus width = 8 bits (Note): * Address (LA 0 to LA 7) output from pins D0-D 7 * Data (D 0 to D7) input/output Note: This applies when BYTE = Vcc level or when the external data bus width select bit (bit 2 at address 84 16) = 1 Area CS 2 setting mode select bit (bit 7) This bit selects the setting mode of the block size. For details of area CS2, see Figures 3.2.10 and 3.2.12. 7902 Group User's Manual 3-17 CONNECTION WITH EXTERNAL DEVICES 3.2 Chip select wait controller (8) CS 3 control register H Figure 3.2.8 shows the structure of the CS3 control register H. b7 b6 b5 b4 b3 b2 b1 b0 CS3 control register H (Address 8716 ) Bit 0 Bit name Area CS3 block size select bits 1 2 3 Area CS3 bus cycle select bit 1 Function b2 b1 b0 0 0 0 : 0 byte (Area CS3 is invalid.) 0 0 1 : 128 Kbytes 0 1 0 : 256 Kbytes 0 1 1 : 512 Kbytes 1 0 0 : 1 Mbytes 1 0 1 : 2 Mbytes 1 1 0 : 4 Mbytes 1 1 1 : 8 Mbytes The combination of this bit and the area CS 3 bus cycle select bit 0 selects the bus cycle. 0 : 1 + 1, 1 + 2, 1 + 3, or 2 + 2 1 : 2 + 3, 2 + 4, 3 + 3, or 3 + 4 7 to 4 The value is "0" at reading. At reset R/W 0 RW 0 RW 0 RW 0 RW 0 -- Fig. 3.2.8 Structure of CS3 control register H Area CS3 block size select bit (bits 2 to 0) These bits select the block size of area CS 3. Clearing these bits to "000 2" invalidates area CS3. When the block size has been selected, area CS 3 becomes valid and setting for each function of area CS 3 becomes valid, regardless of the CS 3 output select bit (bit 7 at address 86 16). (See Table 3.2.1.) Area CS3 bus cycle select bit 1 (bit 3) The combination of this bit and the area CS 3 bus cycle select bit 0 (bits 0, 1 at address 8616 ) selects the bus cycle at access to area CS 3. (Refer to section "3.2.2 External bus operations.") For details of area CS 3, see Figures 3.2.10. (9) Area CSi start address register Figure 3.2.9 shows the structure of area CS i (i = 0 to 3) start address register. Addresses which can be set into each register differ according to the block size, which is selected by the area CSi block size select bits. (See Figures 3.2.10 to 3.2.12.) 3-18 7902 Group User's Manual CONNECTION WITH EXTERNAL DEVICES 3.2 Chip select wait controller Area CS0 start address register (Address 8A16) Bit At reset R/W 0 -- 0 RW 0 RW 0 RW 1 RW 5 0 RW 6 0 RW 7 0 RW 0 1 Function b7 b6 b5 b4 b3 b2 b1 b0 Mode 0 A16-A23 of the start address are set. 3 Mode 1 A8-A15 of the start address are set. Any value of 1016, 2016, 4016, and 8016 can be set. 4 (Bit 0 is always "0" at reading.) 2 Note: Depending on the block size, which has been selected by the area CS0 block size select bits 0 to 2 at address 81 16), the start address which can be set is changed. (See Figures 3.2.10 and 3.2.11.) Area CS1 start address register (Address 8C16) Area CS2 start address register (Address 8E16) Bit At reset R/W Mode 0 A16-A23 of the start address are set. 0 -- 0 RW Mode 1 A8-A15 of the start address are set. 0 RW 0 RW 4 0 RW 5 0 RW 6 0 RW 7 0 RW 0 1 2 Function b7 b6 b5 b4 b3 b2 b1 b0 3 (Bit 0 is always "0" at reading.) Note: Depending on the block size, which has been selected by the area CS 1/CS2 block size select bits (bits 0 to 2 at address 83 16/ 8516), the start address which can be set is changed. (See Figures 3.2.10 and 3.2.12.) b7 b6 b5 b4 b3 b2 b1 b0 Area CS3 start address register (Address 9016) Function Bit At reset R/W 0 A16-A23 of the start address are set. 0 -- 1 (Bit 0 is always "0" at reading.) 0 RW 2 0 RW 3 0 RW 4 0 RW 5 0 RW 6 0 RW 7 0 RW Note: Depending on the block size, which has been selected by the area CS3 block size select bits (bits 0 to 2 at address 8716), the start address which can be set is changed. (See Figure 3.2.10.) Fig. 3.2.9 Structure of area CS i start address register 7902 Group User's Manual 3-19 3-20 Fig. 3.2.10 Area CS0/CS1/CS2 (mode 0) and area CS3 7902 Group User's Manual F0000016 (FF000016) (FFFFFF16) (FF000016) (FFFFFF16) FE000016 (FF000016) (FFFFFF16) Block size : 2 Mbytes E0000016 C0000016 A0000016 80000016 60000016 40000016 20000016 (016) Addresses which can be specified as start address (Note 1) (Addresses 016 and FF000016 to FFFFFF16 are not included.) Block size : 4 Mbytes (FF000016) (FFFFFF16) C0000016 80000016 40000016 (016) Addresses which can be specified as start address (Note 1) (Addresses 016 and FF000016 to FFFFFF16 are not included.) Block size : 8 Mbytes (FF000016) (FFFFFF16) 80000016 (016) Addresses which can be specified as start address (Note 1) (Addresses 016 and FF000016 to FFFFFF16 are not included.) Notes 1: Only A16 to A23 of each address can be set to the area CS0/CS1/CS2/CS3 start address register. Do not set another address not shown here. 2: When an area which overlaps with the internal area is accessed, the internal area will be accessed. In this case, pin CS0/CS1/CS2/CS3 outputs "H" level. : Reserved area. Do not access this area. : Area CS0/CS1/CS2/CS3 cannot be assigned here. (FF000016) (FFFFFF16) ,,, ,,,,,, ,,, ,,,,,, ,,, , E0000016 FC000016 FC000016 (FF000016) (FFFFFF16) D0000016 FA000016 C0000016 F8000016 F8000016 F8000016 B0000016 A0000016 90000016 F6000016 12000016 80000016 10000016 60000016 50000016 40000016 30000016 20000016 10000016 (016) 10000016 10000016 8000016 (016) Block size : 1 Mbytes Addresses which can be specified as start address (Note 1) (Addresses 016 and FF000016 to FFFFFF16 are not included.) 70000016 C000016 8000016 Block size : 512 Kbytes Addresses which can be specified as start address (Note 1) (Addresses 016 and FF000016 to FFFFFF16 are not included.) E000016 C000016 A000016 8000016 6000016 4000016 4000016 (016) (016) 2000016 Block size : 256 Kbytes Addresses which can be specified as start address (Note 1) (Addresses 016 and FF000016 to FFFFFF16 are not included.) Block size : 128 Kbytes Addresses which can be specified as start address (Note 1) (Addresses 016 and FF000016 to FFFFFF16 are not included.) CONNECTION WITH EXTERNAL DEVICES 3.2 Chip select wait controller Start address : 100016 7902 Group User's Manual 7FFFFF16 3FFFFF16 1FFFFF16 FFFFF16 7FFFF16 3FFFF16 1FFFF16 016 100016 256K bytes 512K bytes 1M bytes Block size 2M bytes 4M bytes Start address : 200016 8M bytes 200016 128K bytes 256K bytes Value to be set into area CS0 start address register = "2016" 512K bytes 1M bytes Block size 2M bytes 4M bytes Note: When an area which overlaps with the internal area is accessed, the internal area will be accessed. In this case, pin CS0 outputs "H" level. 128K bytes Value to be set into area CS0 start address register = "1016" Start address : 400016 8M bytes 400016 256K bytes 512K bytes 1M bytes Block size 2M bytes 4M bytes Start address : 800016 800016 128K bytes 256K bytes Value to be set into area CS0 start address register = "8016" 8M bytes Area CS0 cannot be assigned here. 128K bytes Value to be set into area CS0 start address register = "4016" 512K bytes 1M bytes Block size 2M bytes 4M bytes 8M bytes CONNECTION WITH EXTERNAL DEVICES 3.2 Chip select wait controller Fig. 3.2.11 Area CS 0 (mode 1) 3-21 CONNECTION WITH EXTERNAL DEVICES 3.2 Chip select wait controller Block size : 4 Kbytes Block size : 8 Kbytes Addresses which can be specified as start address (Note 1) (Address FFFF16 is not included.) Addresses which can be specified as start address (Note 1) (Address FFFF16 is not included.) 016 016 4 Kbytes 8 Kbytes 100016 200016 200016 300016 400016 400016 500016 600016 600016 700016 800016 800016 E00016 Notes 1: Only A8 to A15 of each address can be set to the area CS1/CS2 start address register. Do not set an address not shown here. 2: When an area which overlaps with the internal area is accessed, the internal area will be accessed. In this case, pin CS1/CS2 outputs "H" level. F00016 (FFFF16) (FFFF16) Fig. 3.2.12 Area CS1/CS 2 (mode 1) 3-22 7902 Group User's Manual CONNECTION WITH EXTERNAL DEVICES 3.2 Chip select wait controller 3.2.2 External bus operations By selecting the following functions by software, the external bus operation can be specified for each area CS i: * Bus cycle * Burst ROM access * Recovery cycle * Area CS 2 multiplexed bus access * RDY control The relationship between the external bus operations and the above functions are explained below. For details of RDY control, refer to section "3.3 Ready control." 7902 Group User's Manual 3-23 CONNECTION WITH EXTERNAL DEVICES 3.2 Chip select wait controller (1) Bus cycle For each area CS i, one of the following bus cycle types can be specified arbitrary. Table 3.2.2 lists the bus cycle types at normal access. Table 3.2.2 Bus cycle types at normal access Bus cycle select bit 0 (Note) Bus cycle select bit 1 = 1 (Note) Bus cycle select bit 1 = 0 (Note) Bus cycle 2 + 3 Bus cycle 1 + 1 1 bus cycle = 2 00 1 1 External address bus External address bus External data bus Address Data CSi CSi RD BLW,BHW RD BLW,BHW ALE ALE Data CSi RD BLW,BHW ALE ALE 1 bus cycle = 6 3 1 External address bus Address Data Address External data bus CSi CSi RD BLW,BHW RD BLW,BHW ALE ALE Data Bus cycle 3 + 4 Bus cycle 2 + 2 1 bus cycle = 4 1 bus cycle = 7 4 3 1 1 External address bus Address Data External data bus CSi CSi RD BLW,BHW RD BLW,BHW ALE ALE Note: The bus cycles type is determined by the following bits: * Areas except for area CSi : external bus cycle select bit 0 (bits 2 and 3 at address 5E16) external bus cycle select bit 1 (bit 0 at address 5F16) : area CSi bus cycle select bit 0 (bits 0 and 1 at addresses 8016, 8216, 8416, 8616) * Area CSi area CSi bus cycle select bit 1 (bit 3 at addresses 8116, 8316, 8516, 8716) 3-24 3 1 External data bus External data bus Data Bus cycle 3 + 3 1 bus cycle = 4 11 Address External data bus RD BLW,BHW External address bus 4 External address bus Address CSi External address bus 1 bus cycle = 6 1 Bus cycle 1 + 3 10 Data 2 1 External data bus Address Bus cycle 2 + 4 1 bus cycle = 3 External address bus 3 External data bus Bus cycle 1 + 2 01 1 bus cycle = 5 2 7902 Group User's Manual Address Data CONNECTION WITH EXTERNAL DEVICES 3.2 Chip select wait controller (2) Burst ROM access When ROM, etc., supporting burst access, is allocated to area CSi, the burst access for the maximum of 8 bytes becomes available if the burst ROM access is specified (the burst ROM access select bit = "1"). The burst ROM access is valid only when the external data bus width = 16 bits with instructions prefetched. In the other cases, normal access is specified regardless of the burst ROM access select bit. Figure 3.2.13 shows the operating waveform at burst ROM access. Also, for the instruction prefetch, refer to section "2.2.1 Instruction prefetch." At instruction prefetch with burst ROM access, 8 bytes are fetched from an 8-byte boundary. (See Figure 3.2.13 (a): quadruple consecutive access.) At branch, 4 bytes are fetched from a 4-byte boundary regardless of the low-order 2 bits (A1, A0) of the branch destination address. (See Figure 3.2.13 (b): double consecutive access.) In this case, the number of fetched bytes depends on the branch destination address. (See Table 2.2.3.) Also, the address of data (instruction) to be fetched next controls the following operations as below: * If this address is placed at an 8-byte boundary, data (instruction) will be fetched in a unit of 8 bytes. (See Figure 3.2.13 (a): quadruple consecutive access.) * If this address is placed at a 4-byte boundary, after 4-byte data is fetched (See Figure 3.2.13 (b): double consecutive access.), data will be fetched in a unit of 8 bytes. (See Figure 3.2.13 (a): quadruple consecutive access.) (a) 1 RD External address bus (A0 to A23) (b) Address Address Address Address External data bus (D0 to D7) (Instruction) External data bus (D8 to D15) Data Data Data Data (Instruction) (Instruction) (Instruction) (Instruction) Data Data Data Data (Instruction) (Instruction) (Instruction) 1 RD External address bus (A0 to A23) Address Address External data bus (D0 to D7) Data Data (Instruction) (Instruction) External data bus (D8 to D15) Data Data (Instruction) (Instruction) Note: The above is applied when 1 bus cycle = 1 + 1. For details of the bus cycle types, refer to section "(1) Bus cycle." Fig. 3.2.13 Operating waveform at burst ROM access 7902 Group User's Manual 3-25 CONNECTION WITH EXTERNAL DEVICES 3.2 Chip select wait controller Table 3.2.3 lists the waveform examples at burst ROM access for each bus cycle. Table 3.2.3 Waveform examples at burst ROM access for each bus cycle Area CSi bus cycle select bit 1 Area CSi bus cycle select bit 0 Burst ROM access select bit = 1 1 bus cycle = 5 2 1 1 1 1 External address bus 0 00 External data bus Address Address Address Address Data Data Data Data CSi RD ALE 1 bus cycle = 9 3 2 2 2 1 External address bus 01 Address External data bus Address Data Address Data Address Data Data CSi RD ALE 1 bus cycle = 13 4 3 3 3 1 External address bus 10 Address Address External data bus Address Data Data Address Data Data CSi RD ALE 11 Do not select. 1 bus cycle = 14 5 3 3 Address Address 3 1 External address bus 1 00 Address External data bus Data Data Address Data Data CSi RD ALE 1 bus cycle = 18 6 4 4 4 1 External address bus 01 External data bus Address Address Data Address Data CSi RD ALE 10 Do not select. 11 Do not select. Area CS i bus cycle select bit 0: Bits 1, 0 at addresses 80 16 , 8216, 84 16, 86 16 Area CS i bus cycle select bit 1: Bit 3 at addresses 81 16, 83 16, 8516 , 8716 Burst ROM access select bit: Bit 5 at addresses 8016 , 8216 , 8416 , 8616 3-26 7902 Group User's Manual Address Data Data CONNECTION WITH EXTERNAL DEVICES 3.2 Chip select wait controller (3) Recovery cycle As the recovery cycle, 1 or 2 cycles of 1 can be selected by both the recovery cycle insert select bit and the recovery-cycle-insert number select bit. (See Figures 3.2.2, 3.2.3, and 3.2.5). Insertion of recovery cycles allows devices with longer output disable time at read to be connected without using bus buffers. Since addresses are maintained throughout recovery cycles, devices requiring longer address hold time can easily be connected; on the other hand, by inserting 2 recovery cycles to extend the data hold time at write by 1 cycle of 1, devices requiring longer data hold time can also be connected. Figures 3.2.14 and 3.2.15 show operating waveforms at recovery cycle insertion. (a) At read/write of data <No recovery cycle inserted> <1 recovery cycle inserted> Recovery cycle 1 Recovery cycle Recovery (Next bus cycle cycle) 1 A0 to A23 A B A A0 to A23 A+1 CSi CSi RD BLW,BHW RD BLW,BHW ALE A B A A+1 ALE Data Write Data Access to area CSi Data Access to internal area Data Write Data Data 16-bit data is accessed starting from an odd-numbered address in area CSi. Data Access to area CSi Data Access to 16-bit data is accessed starting from an internal area odd-numbered address in area CSi. <2 recovery cycles inserted> Recovery cycle Recovery cycle Recovery (Next bus cycle cycle) 1 A0 to A23 A B A A+1 CSi RD BLW,BHW ALE Write Data Data Data Access to area CSi Access to internal area Data 16-bit data is accessed starting from an oddnumbered address in area CSi. If area CSi where recovery cycles have been inserted at the preceding bus cycle is accessed, the same recovery cycles will also be inserted here. (b) At instruction prefetch (Normal access; quadruple consecutive access) <No recovery cycle inserted> Recovery cycle (Next bus cycle) <1 recovery cycle inserted> 1 1 A0-A23 (Note 1) CSi (Note 2) A A+2 A+4 A+6 A0-A23 (Note 1) A A+2 A+4 A+6 CSi (Note 2) RD RD ALE ALE Recovery cycle <2 recovery cycles inserted> (Next bus cycle) 1 A0-A23 (Note 1) A A+2 A+4 A+6 CSi (Note 2) RD ALE If area CSi where recovery cycles have been inserted at the preceding bus cycle is accessed, the same recovery cycles will also be inserted here. Notes 1: This applies when the external data bus width = 16 bits. When 8 bits, each address is incremented by 1. 2: When the same area CSi is consecutively accessed, pin CSi outputs "L" level consecutively. Fig. 3.2.14 Operating waveforms at recovery cycle insertion (1) 7902 Group User's Manual 3-27 CONNECTION WITH EXTERNAL DEVICES 3.2 Chip select wait controller (C) At instruction prefetch (Normal access; double consecutive access) <No recovery cycle inserted> Recovery cycle (Next bus cycle) <1 recovery cycle inserted> 1 1 A0-A23 (Note 1) A A0-A23 (Note 1) A+2 A A+2 CSi (Note 2) CSi (Note 2) RD RD ALE ALE Recovery cycle <2 recovery cycles inserted> (Next bus cycle) 1 A0-A23 (Note 1) A A+2 CSi (Note 2) RD ALE If area CSi where recovery cycles have been inserted at the preceding bus cycle is accessed, the same recovery cycles will also be inserted here. Notes 1: This applies when the external data bus width = 16 bits. When 8 bits, each address is incremented by 1. 2: When the same area CSi is consecutively accessed, pin CSi outputs "L" level consecutively. (d) At instruction prefetch (Burst ROM access; quadruple consecutive access) <No recovery cycle inserted> Recovery cycle (Next bus cycle) <1 recovery cycle inserted> 1 1 A0-A23 A0-A23 A A+2 A+4 A+6 A A+2 A+4 A+6 CSi CSi RD RD ALE ALE Recovery cycle <2 recovery cycles inserted> (Next bus cycle) 1 A0-A23 A A+2 A+4 A+6 CSi RD ALE If area CSi where recovery cycles have been inserted at the preceding bus cycle is accessed, the same recovery cycles will also be inserted here. Note: This applies when the external data bus width = 16 bits. (e) At instruction prefetch (Burst ROM access; double consecutive access) <No recovery cycle inserted> Recovery cycle (Next bus cycle) <1 recovery cycle inserted> 1 1 A0-A23 CSi A A+2 A A0-A23 A+2 CSi RD RD ALE ALE <2 recovery cycles inserted> Recovery cycle (Next bus cycle) 1 A0-A23 A A+2 CSi RD ALE If area CSi where recovery cycles have been inserted at the preceding bus cycle is accessed, the same recovery cycles will also be inserted here. Note: This applies when the external data bus width = 16 bits. Fig. 3.2.15 Operating waveforms at recovery cycle insertion (2) 3-28 7902 Group User's Manual CONNECTION WITH EXTERNAL DEVICES 3.2 Chip select wait controller (4) Area CS 2 multiplexed bus access Setting the multiplexed bus select bit (bit 5 at address 85 16) to "1" performs the following with the timesharing method. This is performed only when area CS2 is accessed with the external data bus width = 8 bits (Note): * Address (LA 0 to LA7) output from pins D0 to D 7 * Data (D0 to D 7) input/output Table 3.2.4 lists the multiplexed bus access waveform examples at bus cycle type selection Note: This applies when BYTE = Vcc level or when the external data bus width select bit (bit 2 at address 8416 ) = 1 Table 3.2.4 Multiplexed bus access waveform examples at bus cycle type selection Area CS2 bus cycle select bit 1 Area CS2 bus cycle select bit 0 Multiplexed bus select bit = 1 0 00 Do not select. 01 Do not select. 10 Do not select. 1 bus cycle = 4 2 2 1 External address bus 11 Address LA0/D0 to LA7/D7 LA0 to LA7 LA0/D0 to LA7/D7 LA0 to LA7 RD WD CS2 RD BLW ALE 1 00 Do not select. 01 Do not select. 1 bus cycle = 6 3 3 1 External address bus 10 Address LA0/D0 to LA7/D7 LA0 to LA7 LA0/D0 to LA7/D7 LA0 to LA7 RD WD CS2 RD BLW ALE 1 bus cycle = 7 3 4 1 External address bus Address LA0/D0 to LA7/D7 LA0 to LA7 LA0/D0 to LA7/D7 LA0 to LA7 11 RD WD CS2 RD BLW ALE RD: Read Data, WD: Write Data Area CS 2 bus cycle select bit 0: Bits 1, 0 at address 84 16 Area CS 2 bus cycle select bit 1: Bit 3 at address 85 16 Multiplexed bus select bit: Bit 5 at address 85 16 7902 Group User's Manual 3-29 CONNECTION WITH EXTERNAL DEVICES 3.2 Chip select wait controller 3.2.3 Setting method Figure 3.2.16 shows an initial setting example of registers related to CSWC. AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA b7 b0 CS0 control register H (Address 8116) Area CS0 bus cycle select bit 1 See Table 3.2.2. b7 b0 CS1 control register H (Address 8316) 0 Area CS1 bus cycle select bit 1 See Table 3.2.2. b7 b0 CS2 control register H (Address 8516) Area CS2 bus cycle select bit 1 See Table 3.2.2. b7 b0 CS3 control register H (Address 8716) Area CS3 bus cycle select bit 1 See Table 3.2.2. b7 b0 CS0 control register L (Address 8016) Area CS0 bus cycle select bit 0 See Table 3.2.2. RDY control bit (Note 1) 0 : RDY control is valid. 1 : RDY control is invalid. Burst ROM access select bit (Note 2) 0 : Normal access 1 : Burst ROM access Recovery cycle insert select bit 0 : No recovery cycle is inserted. 1 : Recovery cycles are inserted. CS0 output select bit 0 : CS0 output is disabled. 1 : CS0 output is enabled. b7 b0 CS1 control register L (Address 8216) CS2 control register L (Address 8416) CS3 control register L (Address 8616) Area CSj bus cycle select bit 0 (j = 1 to 3) See Table 3.2.2. External data bus width select bit (Note 3) 0 : 16-bit width 1 : 8-bit width RDY control bit (Note 1) 0 : RDY control is valid. 1 : RDY control is invalid. Burst ROM access select bit (Note 2) 0 : Normal access 1 : Burst ROM access Recovery cycle insert select bit 0 : No recovery cycle is inserted. 1 : Recovery cycles are inserted. CSj output select bit 0 : CSj output is disabled. 1 : CSj output is enabled. Notes 1: Valid when the RDY input select bit (bit 2 at address 5F16) = "1." 2: Normal access is selected when the external data bus width = 8 bits, regardless of this bit's contents. 3: Fixed to "1" (8-bit width) while VCC-level voltage is applied to pin BYTE. AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA Setting of start address b7 b0 Area CS0 start address register (Address 8A16) See Figures 3.2.10 and 3.2.11. b7 b0 b7 b0 Area CS1 start address register (Address 8C16) Area CS2 start address register (Address 8E16) AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAA AAA AAA Setting of block size b7 b0 CS0 control register H (Address 8116) Area CS0 block size select bits b2 b1 b0 0 0 1 : 128 Kbytes 0 1 0 : 256 Kbytes 0 1 1 : 512 Kbytes 1 0 0 : 1 Mbytes 1 0 1 : 2 Mbytes 1 1 0 : 4 Mbytes 1 1 1 : 8 Mbytes Area CS0 setting mode select bit 0 : Mode 0 1 : Mode 1 b7 b0 CS1 control register H (Address 8316) 0 Area CS1 block size select bits (mode 0) (mode 1) b2 b1 b0 0 0 1 : 128 Kbytes 0 1 0 : 256 Kbytes 0 1 1 : 512 Kbytes 1 0 0 : 1 Mbytes 1 0 1 : 2 Mbytes 1 1 0 : 4 Mbytes 1 1 1 : 8 Mbytes 1 0 0 : 4 Mbytes 1 0 1 : 8 Mbytes Area CSj setting mode select bit 0 : Mode 0 1 : Mode 1 b7 b0 CS2 control register H (Address 8516) Area CS2 block size select bits (mode 0) (mode 1) b2 b1 b0 0 0 1 : 128 Kbytes 0 1 0 : 256 Kbytes 0 1 1 : 512 Kbytes 1 0 0 : 1 Mbytes 1 0 1 : 2 Mbytes 1 1 0 : 4 Mbytes 1 1 1 : 8 Mbytes b2 b1 b0 1 0 0 : 4 Mbytes 1 0 1 : 8 Mbytes Multiplexed bus select bit 0 : Separate bus 1 : Multiplexed bus Area CS2 setting mode select bit 0 : Mode 0 1 : Mode 1 b7 b0 CS3 control register H (Address 8716) Area CS3 block size select bits b2 b1 b0 0 0 1 : 128 Kbytes 0 1 0 : 256 Kbytes 0 1 1 : 512 Kbytes 1 0 0 : 1 Mbytes 1 0 1 : 2 Mbytes 1 1 0 : 4 Mbytes 1 1 1 : 8 Mbytes CSWC operation is started See Figures 3.2.10 and 3.2.12. Area CS3 start address register (Address 9016) See Figure 3.2.10. Fig. 3.2.16 Initial setting example of registers related to CSWC 3-30 b2 b1 b0 7902 Group User's Manual CONNECTION WITH EXTERNAL DEVICES 3.2 Chip select wait controller 3.2.4. Address output selection When internal areas are accessed, address outputs will be undefined. Setting the address output select bit (See Figure 3.2.17.) to "1" allows the address output at access to an internal area to be fixed. It is because the address output at access to an internal area will maintain the state at the preceding access to an external area, by this setting. Figure 3.2.17 shows the structure of the particular function select register 1, and Figure 3.2.18 shows the relationship between address output select bit and address output waveforms. b7 b6 b5 b4 b3 b2 b1 b0 Particular function select register 1 (Address 6316) Bit Bit name Function 0 STP-instruction-execution status 0 : Normal operation. bit 1 : STP instruction has been executed. 1 WIT-instruction-execution status 0 : Normal operation. bit 1 : WIT instruction has been executed. 2 Standby state select bit 3 System clock stop select bit at 0 : In wait mode, system clock fsys is active. 1 : In wait mode, system clock fsys is stopped. WIT (Note 3) 4 Address output select bit 5 The value is "0" at reading. 6 Timer B2 clock source select bit (Valid in event counter mode) 7 The value is "0" at reading. 0 : External bus 1 : Programmable I/O port 0 : Address output changes at access to the internal area and external area. 1 : Address output changes only at access to the external area. 0 : External signal input to the TB2IN pin is counted. 1 : fX32 is counted. At reset R/W RW (Note 2) (Note 1) RW (Note 2) (Note 1) 0 RW 0 RW 0 RW 0 - 0 RW 0 - Notes 1: At power-on reset, this bit becomes "0." At hardware reset or software reset, this bit retains the value just before reset. 2: Even when "1" is written, the bit status will not change. 3: Setting this bit to "1" must be performed just before execution of the WIT instruction. Also, after the wait state is terminated, this bit must be cleared to "0" immediately. Fig. 3.2.17 Structure of particular function select register 1 7902 Group User's Manual 3-31 CONNECTION WITH EXTERNAL DEVICES 3.2 Chip select wait controller Access to external area Normal access Access to internal area Access to external area 1 RD BLW,BHW Address output select bit = 0 A0 to A23 Address output select bit = 1 A0 to A23 Burst ROM access Address Undefined Undefined Address Address Address Access to external area Access to internal area Access to external area 1 RD Address output select bit = 0 A0 to A23 Address output select bit = 1 A0 to A23 Address Address Address Address Address Address Address Undefined Undefined Address Address Address Fig. 3.2.18 Relationship between address output select bit and address output waveforms 3-32 7902 Group User's Manual CONNECTION WITH EXTERNAL DEVICES [Precautions for CSWC] [Precautions for CSWC] 1. When an overlapping area of area CS i (i = 0 to 3) and the internal area is accessed, the internal area will be accessed. In this case, signal CS i is not output (CSi = "H" level output). Also, the data bus width, bus cycle, etc., are the same as those at access to internal areas. (See Table 2.2.4.) 2. Be sure that area CS i does not overlap each other. 7902 Group User's Manual 3-33 CONNECTION WITH EXTERNAL DEVICES 3.3 Ready function 3.3 Ready function Ready function facilitates access to external devices that require long access time. The microcomputer enters Ready state by input of "L" level to pin RDY and retains this state while the level of pin RDY = "L." Table 3.3.1 lists the microcomputer's state in Ready state. To use Ready function, set the following bits as below: * Area CSi (i = 0 to 3): RDY input select bit (bit 2 at address 5F 16 ) = 1, RDY control bit (bit 3 at addresses 80 16, 82 16, 84 16, 86 16) = 0 * External areas except for area CSi: RDY input select bit (bit 2 at address 5F 16) = 1 Table 3.3.1 Microcomputer's state in Ready state Item State Oscillation, fsys Operating. CPU, BIU Operating (Note 1). Pins A 0 to A 23, D0 to D7, D8 to D 15, RD, BLW, BHW, ALE, HLDA, Retain the state when Ready request was CS 0 to CS 3 accepted. Pin 1 Port pins P0, P2, P3 3, P4 to P8, P11 Outputs clock 1. (Note 2) Watchdog timer Operating. Operating. Notes 1: When access to the external areas (including the instruction prefetch) becomes necessary, both of CPU and BIU stop their operations. Until the access to the internal area stops, both of CPU and BIU continue to operate. 2: This applies when these pins serve as programmable I/O port pins or I/O pins of internal peripheral devices not shown in the above table. 3-34 7902 Group User's Manual CONNECTION WITH EXTERNAL DEVICES 3.3 Ready function 3.3.1 Operation description The input level of pin RDY is judged at the last falling edge of clock 1 for each bus cycle. (While buses are not in use, the input level at pin RDY is not judged.) When "L" level is detected at this point, the microcomputer enters Ready state. (This is called "Acceptance of Ready request.") In Ready state, the input level of pin RDY is judged at every falling edge of clock 1. When "H" level is detected at this time, the microcomputer terminates Ready state at the next rising edge of clock 1. Figure 3.3.1 shows the timing of acceptance of Ready request and termination of Ready state. Refer also to "CHAPTER 19. APPLICATIONS" for usage of Ready function. 1 bus cycle 1 CSi (Note 2) RD BLW BHW tsu(RDY-1) (Note 1) RDY tsu(RDY-1) (Note 1) th(1-RDY) (Note 1) : Extended by Ready function This applies when 1 bus cycle = 1 + 3. Notes 1: Be sure to input signal RDY which satisfies these timing conditions. 2: At the burst ROM access, until the quadruple/double consecutive access is completed, signal RD is not risen to "H." 3: Broken lines for CSi, RD, BLW, and BHW apply when the input level at pin RDY = "H" (no Ready request). Fig. 3.3.1 Timing of acceptance of Ready request and termination of Ready state 7902 Group User's Manual 3-35 CONNECTION WITH EXTERNAL DEVICES 3.4 Hold function 3.4 Hold function Hold function opens the external buses to external devices. In the memory expansion or microprocessor mode, the microcomputer enters Hold state when "L" level is input to pin HOLD. While the level at pin HOLD = "L," the microcomputer retains Hold state. Table 3.4.1 lists the microcomputer's state in Hold state. To use Hold function, be sure to set the HOLD input, HLDA output select bit (bit 5 at address 5F 16) to "1." Table 3.4.1 Microcomputer's state in Hold state Item State Oscillation, fsys Operating. CPU, BIU Operating (Note 1). Pins A 0 to A 23, D0 to D7, D8 to D 15, RD, BLW, BHW, ALE, Floating. CS 0 to CS 3 Pin HLDA Outputs "L" level. Pin 1 Outputs clock 1. Port pins P0, P2, P30, P3 3, P40 to P4 2, P5 to P8, P11 (Note 2) Operating. Watchdog timer Operating (Note 1). Notes 1: When access to the external areas (including the instruction prefetch) becomes necessary, all of CPU, BIU, and the watchdog timer stop their operations. Until the access to the internal area stops, all of CPU, BIU, and the watchdog timer continue to operate. 2: This applies when these pins serve as programmable I/O port pins or I/O pins of internal peripheral devices not shown in the above table. 3-36 7902 Group User's Manual CONNECTION WITH EXTERNAL DEVICES 3.4 Hold function 3.4.1 Operation description The judgement timing of the input level at pin HOLD depends on the usage state of buses. While buses are not in use, the input level at pin HOLD is judged at every rising edge of clock 1. While buses are in use, the input level is judged at the rising edge of clock 1, which precedes the end of the bus cycle by 1 cycle. When "L" level (Hold request) is detected at the judgement of the input level, the microcomputer will enter Hold state after completion of the present bus cycle. (This is called "Acceptance of Hold request.") When Hold request is accepted, pin HLDA's level changes from "H" to "L" at the next rising edge of clock 1. Simultaneously, pins RD, BLW, BHW, ALE, CSi (i = 0 to 3), and external buses enter the floating state. In Hold state, the input level at pin HOLD is judged every rising edge of clock 1. When "H" level is detected at this time, pin HLDA's level will change from "L" to "H" at the next rising edge of clock 1. When pin HLDA's level becomes "H," the microcomputer terminates Hold state after 1 cycle of clock 1 is elapsed. Figure 3.4.1 shows the timing of acceptance of Hold request and termination of Hold state. 1 A0 to A23 Address D0 to D15 Data Undefined Address Undefined Data CSi RD BLW BHW ALE HOLD HLDA Hold state Bus cycle (Bus in use) Bus cycle Input level at pin HOLD is judged. Hold request is sampled, and priority is determined (Acceptance of Hold request.) Input level at pin HOLD is judged. ( Request to terminate Hold state is generated.) Fig. 3.4.1 Timing of acceptance of Hold request and termination of Hold state 7902 Group User's Manual 3-37 CONNECTION WITH EXTERNAL DEVICES 3.4 Hold function MEMORANDUM 3-38 7902 Group User's Manual CHAPTER 4 RESET 4.1 4.2 4.3 4.4 Reset operation Pin state State of internal area Internal processing sequence after reset RESET 4.1 Reset operation There are 3 ways to reset the microcomputer: Hardware reset : Apply "L" level of voltage to pin RESET while the power source voltage (Vcc) meets the recommended operating conditions. Software reset : Write "1" to the software reset bit (bit 6 of address 5E 16) while the power source voltage (Vcc) meets the recommended operating conditions. Power-on reset : Apply "L" level of voltage to pin RESET until the voltage level at pin Vcc meets the recommended operating conditions after powered on. 4.1 Reset operation Operations of hardware, software, and power-on reset are described below. 4.1.1 Hardware reset Figure 4.1.1 shows an example of hardware reset timing. RESET (Note) 2 s or more 8 to 9 cycles of fsys Internal processing sequence after reset Program is executed. Note: The above is applied when the oscillator is stably oscillating or when an external clock is stably input from pin XIN. When the oscillator is not stably oscillating (including the case at the stop mode's termination; refer to section "16.3 Stop mode."), apply "L" level of voltage for 2 s or more after the oscillation becomes stable. Fig. 4.1.1 Example of hardware reset timing The following explains how the microcomputer operates in the above periods, to . After applying "L" level of voltage to pin RESET, the microcomputer initializes pins within a period of several ten cycles of fsys . (Refer to section "4.2 Pin state.") The microcomputer initializes the central processing unit (CPU) and SFR area in the following periods. (Refer to section "4.3 State of internal area.") * While pin RESET is at "L" level. * A period of 8 to 9 cycles of fsys after pin RESET goes from "L" to "H." After , the microcomputer performs "Internal processing sequence after reset." (Refer to section "4.4 Internal processing sequence after reset.") The microcomputer executes a program beginning with the address which has been set into the reset vector addresses (addresses FFFE 16 and FFFF16 ). 4-2 7902 Group User's Manual RESET 4.1 Reset operation 4.1.2 Software reset The microcomputer initializes pins, CPU, and SFR area just as in the case of hardware reset (Refer to sections "4.2 Pin state" and "4.3 State of internal area") by writing "1" to the software reset bit. (See Figure 4.1.2.) After initialization completed, the microcomputer performs "Internal processing sequence after reset." (Refer to section "4.4 Internal processing sequence after reset.") After that, it executes a program beginning with the address which has been set into the reset vector addresses (FFFE 16 and FFFF16 ). b7 b6 b5 b4 b3 b2 b1 b0 Processor mode register 0 (Address 5E16) Bit Bit name 0 Processor mode bits 1 2 External bus cycle select bit 0 (Note 2) 3 4 5 Function b1 b0 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode 1 1 : Do not select. (External bus cycle select (External bus cycle select bit 1 = 0) bit 1 = 1) b3 b2 b3 b2 0 0 : 1 + 1 0 1 : 1 + 2 1 0 : 1 + 3 1 1 : 2 + 2 0 0 : 2 + 3 0 1 : 2 + 4 1 0 : 3 + 3 1 1 : 3 + 4 Interrupt priority detection time b5 b4 0 0 : 7 cycles of fsys select bits 0 1 : 4 cycles of fsys 1 0 : 2 cycles of fsys 1 1 : Do not select. At reset R/W 0 RW (Note 1) RW 0 RW 1 RW 0 RW 0 RW 0 WO 6 Software reset bit The microcomputer is reset by writing "1" to this bit. The value is "0" at reading. 7 Clock 1 output select bit 0 : 1 output is disabled. (P4 1 functions as a (Note 3) programmable I/O port pin.) 1 : 1 output is enabled. (P4 1 functions as a clock 1 output pin.) RW Notes 1: When the Vss-level voltage is applied to pin MD0, this bit is "0"; when the Vcc-level voltage is applied to pin MD0, this bit is "1." (Fixed to "1.") 2: These bits are valid for the external area except for area CSi. Regardless of these bits' contents, the bus cycle of area CSi is decided by the corresponding area CSi bus cycle select bits 0, 1 (bits 0, 1 at addresses 8016 , 8216 , 8416 , 8616, and bit 3 at addresses 8116, 8316 , 8516 , 8716 ). 3: When the Vss-level voltage is applied to pin MD0, this bit is "0"; when the Vcc-level voltage is applied to pin MD0, this bit is "1." Fig. 4.1.2 Structure of processor mode register 0 7902 Group User's Manual 4-3 RESET 4.1 Reset operation 4.1.3 Power-on reset The following describes the operation of the microcomputer at power-on reset. After powered on, within the several ten cycles of f sys after the voltage level at pin Vcc meets the recommended operating conditions with the voltage level at pin RESET = "L," the microcomputer initializes pins: refer to section "4.2 Pin state." After the voltage level at pin RESET goes from "L" to "H," the microcomputer initializes the CPU and SFR area within a period of 8 to 9 cycles of fsys. (Contents of the internal RAM area become undefined: refer to section "4.3 State of internal area.") After , the microcomputer performs "Internal processing sequence after reset.": refer to section "4.4 Internal processing sequence after reset." The microcomputer executes a program beginning with the address which has been set into the reset vector addresses (addresses FFFE 16 and FFFF16 ). Figure 4.1.3 shows the power-on reset conditions. Figure 4.1.4 shows an example of a power-on reset circuit. After the voltage level at pin Vcc meets the recommended operating conditions and the oscillator's operation is stabilized (see Figure 4.1.3.), apply "L" level of voltage to pin RESET for 2 s or more. When an oscillator is used, the time required for stabilizing oscillation depends on the oscillator. For details, contact the oscillator manufacturer. VCC level VCC 0V RESET 0.2 V CC level 2 s 0V X IN 0V Oscillation stabilized Powered on there Fig. 4.1.3 Power-on reset conditions 5V M37902 1 M51957AL VCC VCC 27 k 2 IN OUT 5 RESET 47 4 Delay capacity 10 k GND 3 VSS Cd SW The delay time is about 11 ms when Cd = 0.033 F. td 0.34 Cd [s], Cd: [pF] GND Fig. 4.1.4 Example of power-on reset circuit 4-4 7902 Group User's Manual RESET 4.2 Pin state 4.2 Pin state Table 4.2.1 lists the microcomputer's pin state while the voltage level at pin RESET is "L." Table 4.2.1 Pin state while voltage level at pin RESET is "L" Pin MD1's level Pin MD0's level Pin (Bus, Port) name Pin state Vss or Vcc P0-P3, P4 0-P43, P5-P8, P10, P11 Floating. MASK ROM version, Vss Flash memory version P4 4-P47, NMI Pulled up. Vcc External ROM version A 0-A 23 Outputs "H" or "L" level. RDY, HOLD, D0-D 7, Floating. P2 0/D8-P27/D15, P5-P8 Flash memory version Vcc (Note 2) Vss P4 5-P47, NMI Pulled up. RD, BLW, BHW, HLDA, CS 0 Outputs "H" level (Note 1). ALE 1 Outputs "L" level. P0-P3, P4 0-P43, P5-P8, P10, P11 Floating. P4 4-P47, NMI Vcc Outputs 1. Pulled up. P0-P3, P4 0, P41, P4 3-P47, P5-P8, Floating (Note 3). P10, P11, NMI P4 2 Outputs "H" level. Notes 1: When BYTE = Vcc, pin BHW enters the floating state. 2: Refer to "CHAPTER 20. FLASH MEMORY VERSION." 3: When applying the voltage of "H" level to pin VCONT and "L" level to pins P54 and P55, P1 and P2 output "H" or "L" level. 7902 Group User's Manual 4-5 RESET 4.3 State of internal area 4.3 State of internal area Figure 4.3.1 shows the state of CPU registers immediately after reset. Figures 4.3.2 to 4.3.7 show the state of the SFR and internal RAM areas immediately after reset. 0 : "0" immediately after reset. 1 : "1" immediately after reset. ? : Undefined immediately after reset. : "0" immediately after reset. Fix this bit to "0." 0 Register name State immediately after reset b15 b8 Accumulator A (A) b7 b0 ? ? b15 b8 Accumulator B (B) b7 b0 ? ? b15 b8 Index register X (X) b7 b0 ? ? b15 b8 Index register Y (Y) b7 b0 ? ? b15 b8 Stack pointer (S) b7 b0 0F16 FF16 b7 b0 Data bank register (DT) 0016 b7 b0 Program bank register (PG) 0016 b15 Program counter (PC) b8 Contents at address FFFF16 b15 b0 0016 b15 b8 b7 b0 ? ? b15 0 0 0 0 0 0 0 b8 b7 0 ? ? 0 0 0 1 ? ? N V m x D I Z C IPL Fig. 4.3.1 State of CPU registers immediately after reset 4-6 b7 0016 Direct page register i (DPRi) (i = 1 to 3) Processor status register (PS) b0 Contents at address FFFE16 b8 Direct page register 0 (DPR0) b7 7902 Group User's Manual b0 RESET 4.3 State of internal area SFR area (Addresses 016 to FF16) Access characteristics RW : It is possible to read the bit state at reading. The written value becomes valid. RO : It is possible to read the bit state at reading. The written value becomes invalid. WO : The written value becomes valid. It is impossible to read the bit state. : Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid. State immediately after reset 0 : "0" immediately after reset. 1 : "1" immediately after reset. ? : Undefined immediately after reset. Address 0 16 1 16 2 16 3 16 4 16 5 16 6 16 7 16 8 16 9 16 A 16 B 16 C16 D16 E 16 F 16 10 16 11 16 12 16 13 16 14 16 15 16 16 16 17 16 18 16 19 16 1A 16 1B 16 1C16 1D16 1E 16 1F 16 Register name Port P0 register Port P1 register Port P0 direction register Port P1 direction register Port P2 register 0 : Always "0" at reading. 1 : Always "1" at reading. ? : Always undefined at reading. 0 : "0" immediately after reset. Fix this bit to "0." b7 Access characteristics Port P3 direction register Port P4 register Port P5 register Port P4 direction register Port P5 direction register Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register Port P8 direction register Port P10 register Port P11 register Port P10 direction register Port P11 direction register A-D control register 0 A-D control register 1 b7 State immediately after reset (Note 1) (Note 1) RW RW RW RW RW Port P3 register Port P2 direction register b0 RW 0 0 0 RW 0 0 0 0 ?0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ? ? ? ? 0016 0016 ? 0 0016 0 0 ? ? 0016 0016 ? ? 0016 0016 ? ? 0016 ? ? ? 0016 0016 ? ? ? ? 0 0 0 0 b0 ? 0 0 0 ? 0 ? 1 ? 1 Notes 1: Do not read and write. Fig. 4.3.2 State of SFR and internal RAM areas immediately after reset (1) 7902 Group User's Manual 4-7 RESET 4.3 State of internal area Address Register name A-D register 0 2016 2116 A-D register 1 2216 2316 A-D register 2 2416 2516 A-D register 3 2616 2716 A-D register 4 2816 2916 2A16 A-D register 5 2B16 2C16 A-D register 6 2D16 A-D register 7 2E16 2F16 3016 UART0 transmit/receive mode register UART0 baud rate register 3116 3216 UART0 transmit buffer register 3316 3416 UART0 transmit/receive control register 0 3516 UART0 transmit/receive control register 1 3616 UART0 receive buffer register 3716 3816 UART1 transmit/receive mode register UART1 baud rate register 3916 3A16 UART1 transmit buffer register 3B16 3C16 UART1 transmit/receive control register 0 3D16 UART1 transmit/receive control register 1 3E16 UART1 receive buffer register 3F16 b7 Access characteristics b0 State immediately after reset b7 RO RO RO 0 0 0 0 ? 0 0 ? 0 0 ? 0 0 ? 0 0 ? 0 0 ? 0 0 ? 0 0 0016 ? ? ? 0 1 0 0 ? 0 0 0016 ? ? ? 0 1 0 0 ? 0 0 0 ? 0 ? RO RO 0 0 0 0 RO ? RO RO 0 0 0 0 RO ? RO RO 0 0 0 0 ? RO RO RO 0 0 0 0 ? RO RO RO 0 0 0 0 RO ? RO RO 0 0 0 RO RO 0 0 0 WO RW RW RO RW 0 0 0 0 0 0 RO 0 0 0 WO RW RW RO RW 0 0 0 0 0 0 RO 0 0 0 RW WO WO RO RO RW WO WO RW RO RO 0 ? RO RO Fig. 4.3.3 State of SFR and internal RAM areas immediately after reset (2) 4-8 0 RO RW RO b0 ? 7902 Group User's Manual 0 0 0 1 0 0 0 0 ? 0 0 0 1 0 0 0 0 ? RESET 4.3 State of internal area Address Access characteristics Register name State immediately after reset b0 b7 RW Count start register 4 0 16 4 1 16 RW WO One-shot start register 4 2 16 4 3 16 Up-down register WO RW 4 4 16 RW RW 4 5 16 Timer A clock division select register (Note 2) 4 6 16 Timer A0 register (Note 2) 4 7 16 (Note 2) 4 8 16 Timer A1 register 4 9 16 (Note 2) 4A16 (Note 2) Timer A2 register (Note 2) 4B16 4C16 (Note 2) Timer A3 register (Note 2) 4D16 4E16 (Note 2) Timer A4 register (Note 2) 4F 16 5 0 16 (Note 3) Timer B0 register 5 1 16 (Note 3) (Note 3) 5 2 16 Timer B1 register (Note 3) 5 3 16 (Note 3) 5 4 16 Timer B2 register (Note 3) 5 5 16 Timer A0 mode register RW 5 6 16 Timer A1 mode register RW 5 7 16 Timer A2 mode register RW 5 8 16 Timer A3 mode register RW 5 9 16 Timer A4 mode register 5A16 RW Timer B0 mode register RW (Note 4) 5B16 RW Timer B1 mode register RW (Note 4) 5C16 RW Timer B2 mode register RW (Note 4) 5D16 RW RW RW WO 5E16 Processor mode register 0 (Note 6) 5F 16 Processor mode register 1 (Note 7) RWRW RW RW (Note 6) RW RW b0 b7 0 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? 0 (Note 5) 0 0016 ? 0 0 ? 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0016 0016 0016 0016 0016 ? 0 ? 0 ? 0 0 1 (Note 5) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Note 5) 0 Notes 2: The access characteristics at addresses 4616 to 4F16 vary according to the timer A's operating mode. (Refer to "CHAPTER 9. TIMER A.") 3: The access characteristics at addresses 5016 to 5516 vary according to the timer B's operating mode. (Refer to "CHAPTER 10. TIMER B.") 4: The access characteristics for bit 5 at addresses 5B16 and 5D16 vary according to the timer B's operating mode. (Refer to "CHAPTER 10. TIMER B.") 5: This bit is "0" when Vss-level voltage is applied to pin MD0; this bit is "1" when Vcc-level voltage is applied. 6: After reset, this bit can be set to "1" only once. Once this bit goes from "1" to "0," it cannot be set to "1" again. (This bit is fixed to "0.") 7: In the external ROM version, for bit 7, nothing is assigned. This bit is "0" at reading. Fig. 4.3.4 State of SFR and internal RAM areas immediately after reset (3) 7902 Group User's Manual 4-9 RESET 4.3 State of internal area Address Access characteristics Register name 60 16 61 16 62 16 63 16 64 16 65 16 66 16 67 16 68 16 69 16 6A 16 6B 16 6C16 6D16 6E 16 6F 16 70 16 71 16 72 16 73 16 74 16 75 16 76 16 77 16 78 16 79 16 7A 16 7B 16 7C16 7D16 7E 16 7F 16 Watchdog timer register Watchdog timer frequency select register RW RW Particular function select register 0 Particular function select register 1 State immediately after reset b0 b7 RW (Note 8) RW RW (Note 10) RW RW RW RW (Note 11) Particular function select register 2 Debug control register 0 Debug control register 1 Address comparison register 0 Address comparison register 1 INT3 interrupt control register INT4 interrupt control register A-D conversion interrupt control register UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register INT2 interrupt control register (Note 13) RW RO RO RW RW RW RO RW RW (Note 14) RW (Note 14) RW (Note 14) RW (Note 14) RW (Note 14) RW (Note 14) RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW b7 Notes 8 : By writing dummy data to address 6016, a value of "FFF16" is set to the watchdog timer. The dummy data is not retained anywhere. 9 : A value of "FFF16" is set to the watchdog timer. (Refer to "CHAPTER 15. WATCHDOG TIMER.") 10 : After writing "5516" to address 6216, each bit must be set. 11 : It is possible to read the bit state at reading. By writing "0" to this bit, this bit becomes "0." But when writing "1" to this bit, this bit will not change. 12 : This bit becomes "0" at power-on reset. This bit retains the state immediately before reset in the case of hardware reset and software reset. 13 : Do not write. 14 : When these registers are accessed, set the address comparison register access enable bit (bit 2 at address 6716) to "1." (Refer to "CHAPTER 18. DEBUG FUNCTION.") Fig. 4.3.5 State of SFR and internal RAM areas immediately after reset (4) 4-10 7902 Group User's Manual b0 ? (Note 9) 0 0 0 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Note 12) ? ? (Note 12) 0 0 (Note 12) 1 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 ? ? ? 0 0 0 0 0 0 0 ? 0 0 0 0 ? 0 0 0 0 ? 0 0 0 0 ? 0 0 0 0 ? 0 0 0 0 ? 0 0 0 0 ? 0 0 0 0 ? 0 0 0 0 ? 0 0 0 0 ? 0 0 0 0 ? 0 0 0 0 ? 0 0 0 0 0 0 ? 0 0 0 0 0 0 ? 0 0 0 0 0 0 ? RESET 4.3 State of internal area Address Access characteristics Register name b7 State immediately after reset b0 CS0 control register L 80 16 RW RW RO RW RW RW CS0 control register H 81 16 RW CS1 control register L 82 16 RW RW RW CS 1 control register H 83 16 RW RW CS2 control register L 84 16 RW RW CS2 control register H 85 16 RW RW RW RW RW 86 16 CS3 control register L 87 16 RW CS3 control register H 88 16 89 16 8A16 Area CS0 start address register RW 8B16 8C16 Area CS1 start address register RW 8D16 8E16 Area CS2 start address register RW 8F 16 RW 90 16 Area CS3 start address register 91 16 Port function control register 92 16 RW 93 16 94 16 External interrupt input control register RW RO 95 16 External interrupt input read-out register D-A control register 96 16 RW RW RW 97 16 98 16 RW D-A register 0 99 16 D-A register 1 RW RW 9A16 D-A register 2 9B16 (Note 17) 9C16 9D16 (Note 17) 9E16 Flash memory control register (Note 18) RW RO 9F 16 Notes 15 : 16 : 17 : 18 : b0 b7 (Note 15) 1 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Note 16) 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ? ? 0 0 0 1 ? 0 0 0 0 0 0 0 0 ? ? 0 0 0 0 ? 0 0 0 0 ? 0 0 0 0 ? ? 0 0 0 ? 0016 0016 0016 ? ? ? 0 0 ? This bit is "0" when Vss-level voltage is applied to pin MD0; this bit is "1" when Vcc-level voltage is applied. This bit is "0" when Vss-level voltage is applied to pin BYTE; this bit is "1" when Vcc-level voltage is applied. Do not write. This register is allocated only to the flash memory version. (Refer to "CHAPTER 20. FLASH MEMORY VERSION.") Do not write to this register in the mask ROM and external ROM versions. Fig. 4.3.6 State of SFR and internal RAM areas immediately after reset (5) 7902 Group User's Manual 4-11 RESET 4.3 State of internal area Address A0 16 A1 16 A2 16 A3 16 A4 16 A5 16 A6 16 A7 16 A8 16 A9 16 AA 16 AB 16 AC 16 AD 16 AE 16 AF 16 B0 16 B1 16 B2 16 B3 16 B4 16 B5 16 B6 16 B7 16 B8 16 B9 16 BA 16 BB 16 BC 16 BD 16 BE 16 BF 16 Register name b7 Access characteristics RW Real-time output control register Serial I/O pin control register Clock control register State immediately after reset b7 0 0 0 0 WO RW RW RW RW (Note 19) (Note 19) RW RW RW RW (Note 20) RW RW (Note 19) (Note 19) (Note 19) b0 0 0 0 0 0 0 0 0 0 1 1 1 ? ? ? ? ? ? ? ? ? ? ? WO Pulse output data register 0 Pulse output data register 1 b0 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 ? ? ? Notes 19 : Do not write to this register. 20 : After reset, these bits are allowed to be changed only once. Internal RAM area At hardware reset ................................................................................. Retains the state immediately before reset (Note 21). At software reset.................................................................................................... Retains the state immediately before reset. At termination of the stop or wait mode (when hardware reset is used for the termination.)....................................Retains the state immediately before the STP or WIT instruction is executed. At power-on reset..................................................................................................................................................... Undefined. Notes 21 : When a reset operation starts while writing to the internal RAM area is in process, the microcomputer will be reset before the completion of writing. Accordingly, the contents of the area where the writing was in process will become undefined. Fig. 4.3.7 State of SFR and internal RAM areas immediately after reset (6) 4-12 7902 Group User's Manual RESET 4.4 Internal processing sequence after reset 4.4 Internal processing sequence after reset Figure 4.4.1 shows the internal processing sequence after reset. (1) At MD0 = VSS (single-chip mode) fsys AH(CPU) 0016 0016 0016 000016 FFFE16 ALAM(CPU) DATA(CPU) Undefined IPL, Vector addresses of reset AD15 to AD 0 AD15 to AD 0 Next op-code fsys : System clock (See Figure 5.2.1.) AD0 to AD 15 : Internal address bus IPL : Processor interrupt priority level This is an internal signal and is not output to the external. (2) At MD0 = VCC (microprocessor mode) 1 A23 to A16 0016 0016 A15 to A 0 000016 FFFE16 DATA(CPU) Undefined IPL, Vector addresses of reset AD15 to AD0 0016 AD15 to AD0 next op-code Floating D0 to D15 RD BLW BHW H ALE CS0 AD0 to AD 15 : Internal address bus IPL : Processor interrupt priority level This is an internal signal and is not output to the external. Note : When the stack area is in the internal area, the above signals are not output to the external. When the stack area is in the external area, A0 to A23, RD, BLW, and BHW are output to the external. The above waveforms are applied when the external data bus has a width of 16 bits. When the external data bus has a width of 8 bits, D8 to D15 and BHW enter the floating state. Fig. 4.4.1 Internal processing sequence after reset 7902 Group User's Manual 4-13 RESET 4.4 Internal processing sequence after reset MEMORANDUM 4-14 7902 Group User's Manual CHAPTER 5 CLOCK GENERATING CIRCUIT 5.1 Oscillation circuit examples 5.2 Clocks [Precautions for clcok generating circuit] CLOCK GENERATING CIRCUIT 5.1 Oscillation circuit examples 5.1 Oscillation circuit examples To the oscillation circuit, a ceramic resonator or a quartz-crystal oscillator can be connected, or the clock which is externally generated can be input. Oscillation circuit examples are shown below. 5.1.1 Connection example with resonator/oscillator Figure 5.1.1 shows an example where pins XIN and X OUT connect across a ceramic resonator/quartz-crystal oscillator. The circuit constants such as Rf, R d, C IN, and C OUT (shown in "Figure 5.1.1") depend on the resonator/ oscillator. These values shall be set to the values recommended by the resonator/oscillator manufacturer. M37902 XIN XOUT Rf Rd CIN COUT Fig. 5.1.1 Connection example of resonator/oscillator 5.1.2 Externally generated clock input example Figure 5.1.2 shows an input example of a clock which is externally generated. An external clock must be input from pin XIN , and pin XOUT must be left open. When an externally generated clock is input, the power source current consumption can be saved by the stop of internal circuit's operation between pins XIN and XOUT. (Refer to "CHAPTER 17. POWER SAVING FUNCTION.") M37902 XIN XOUT Open Externally generated clock Vcc Vss Fig. 5.1.2 Externally generated clock input example 5-2 7902 Group User's Manual CLOCK GENERATING CIRCUIT 5.1 Oscillation circuit examples 5.1.3 Connection example of filter circuit In the usage of the PLL frequency multiplier, be sure to connect a filter circuit with pin VCONT . Figure 5.1.3 shows a connection example of the filter circuit. M37902 VCONT 1 k 220pF 0.1 F Note: Connect the elements of the filter circuit as close as possible and enclose the whole circuit with a Vss pattern. Fig. 5.1.3 Connection example of filter circuit 7902 Group User's Manual 5-3 5-4 R S Q WIT instruction Interrupt request R S Q External clock input select bit STP instruction Interrupt request Wait mode XIN XOUT fXIN f/n Fig. 5.2.1 Clock generating circuit block diagram 7902 Group User's Manual STP instruction R S Q 0 1 1 0 System clock frequency select bit Wait mode fsys 1/2 1/2 BIU : Bus interface Unit CPU : Central Processing Unit : Signal generated when the watchdog timer's most significant bit becomes "0." : bit 0 at address 6116 : bits 6, 7 at address 6116 : bit 1 at address 6216 : bit 3 at address 6316 : bit 1 at address BC16 : bits 2, 3 at address BC16 : bit 5 at address BC16 : bits 6, 7 at address BC16 CPU wait request 1 0 Peripheral device's clock select bit 0 Access to Wait mode external area HLDA 1 0 Peripheral device's clock select bit 1 * Watchdog timer frequency select bit * Watchdog timer clock source select bits at STP termination * External clock input select bit * System clock stop select bit at WIT * PLL circuit operation enable bit * PLL multiplication ratio select bits * System clock select bit * Peripheral device's clock select bit 0, 1 Reset VCONT fX16 fX32 fX64 fX128 fPLL PLL circuit operation enable bit PLL frequency multiplier PLL multiplication ratio select bits System clock stop select bi at WIT Wait mode 1 f4096 1/16 0 1 Wf512 Wf32 Watchdog timer frequency select bit 1/8 fX16 fX32 fX64 fX128 External clock input select bit (Clock for CPU) CPU (Clock for BIU) BIU 1/8 Watchdog timer clock source select bits at STP termination 1/16 1/4 System clock frequency select bit 1/8 f1 f2 f16 f64 f512 0 1 Watchdog timer Interrupt request Operating clock for timer A Operating clock for serial I/O, timer B A-D conversion frequency (AD) clock source Peripheral device's clocks CLOCK GENERATING CIRCUIT 5.2 Clocks 5.2 Clocks Figure 5.2.1 shows the clock generating circuit block diagram. CLOCK GENERATING CIRCUIT 5.2 Clocks 5.2.1 Clocks generated in clock generating circuit (1) fX IN It is the input clock from pin X IN . (2) f PLL It is the output clock from the PLL frequency multiplier. (3) f sys It is the system clock which becomes the clock source of CPU, BIU, and internal peripheral devices. Whether fXIN = f sys or f PLL = fsys can be selected by software. (4) CPU It is the operating clock of CPU. (5) BIU It is the operating clock of BIU. (6) Clock 1 It has the same period as f sys and is output to the external from pin P4 1/1. (7) f1, f 2, f 16, f 64 , f 512 , f4096 Each of them is the internal peripheral device's operating clock. (8) Wf 32, Wf 512 These are the operating clocks of the watchdog timer, and their clock source is f 2. (9) fX16 , fX 32, fX 64 , fX 128 These are the divide clocks of fX IN and become the watchdog timer's clock source at STP termination. 7902 Group User's Manual 5-5 CLOCK GENERATING CIRCUIT 5.2 Clocks 5.2.2 Clock control register Figure 5.2.2 shows the structure of the clock control register, and Figure 5.2.3 shows the setting procedure for the clock control register when using the PLL frequency multiplier. b7 b6 b5 b4 b3 b2 b1 b0 Clock control register (Address BC16) 1 0 At reset R/W Fix this bit to "1." PLL circuit operation enable bit 0 : PLL frequency muliplier is inactive, and pin VCONT is invalid. (Floating) (Note 1) 1 : PLL frequency muliplier is active, and pin VCONT is valid. 1 RW 1 RW PLL multiplication ratio select bits b3 b2 0 0 : Do not select. (Note 2) 0 1 : Double 1 0 : Triple 1 1 : Quadruple 1 RW 0 RW 4 Fix this bit to "0." 0 RW 5 System clock select bit 0 RW 6 Peripheral device's clock select bit 0 See Table 5.2.2. 0 RW 7 Peripheral device's clock select bit 1 0 RW Bit 0 1 2 3 Function Bit name 0 : fXIN (Note 3) 1 : fPLL Notes 1: Clear this bit to "0" if the PLL frequency multiplier need not to be active. In the stop and flash memory parallel I/O modes, the PLL frequency multiplier is inactive and pin VCONT is invalid regardless of the contents of this bit. 2: Rewriting of these bits must be performed simultaneously with clearance of the system clock select bit (bit 5). Then, set bit 5 to "1" 2 ms after the rewriting of these bits. (After reset, these bits are allowed to be changed only once.) 3: Clearing the PLL circuit operation enable bit (bit 1) to "0" clears the system clock select bit to "0." Also, while the PLL circuit operation enable bit = "0," nothing can be written to the system clock select bit. (Fixed to be "0.") In order to set the system clock select bit to "1" after reset, it is necessary to wait 2 ms after the stabilization of f(XIN). Fig. 5.2.2 Structure of clock control register (1) PLL circuit operation enable bit (bit 1) Setting this bit to "1" enables the PLL frequency multiplier to be active and pin V CONT to be valid. This bit = "1" while pin RESET = "L" level and after reset, so that, in this case, the PLL frequency multiplier is active. Clear this bit to "0" if the PLL frequency multiplier need not to be active. Note that, in the stop and flash memory parallel I/O modes, the PLL frequency multiplier is in active and pin V CONT is invalid regardless of the contents of this bit. (Refer to sections "16.3 Stop mode" and "20.4 Flash memory parallel I/O mode.") (2) PLL multiplication ratio select bits (bits 2, 3) These bits select the multiplication ratio of the PLL frequency multiplier. (See Table 5.2.1.) To rewrite these bits, clear the system clock select bit (bit 5) to "0" simultaneously. Then, set the system clock select bit to "1" 2 ms after the rewriting of this bit. (See Figure 5.2.3.) Note that, after reset, these bits are allowed to be changed only once. 5-6 7902 Group User's Manual CLOCK GENERATING CIRCUIT 5.2 Clocks (3) System clock select bit (bit 5) This bit selects a clock source of fsys. When this bit = "0," fX IN is selected as fsys ; and when this bit = "1," fPLL as the one. (See Table 5.2.1.) Clearing the PLL circuit operation enable bit (bit 1) to "0" clears the system clock select bit to "0." Also, while the PLL circuit operation enable bit = "0," nothing can be written to the system clock select bit. (Fixed to be "0.") In order to set the system clock select bit to "1" after reset, it is necessary to wait 2 ms after the stabilization of f(XIN ). To rewrite the PLL multiplication ratio select bits (bits 2 and 3), clear the system clock select bit to "0" simultaneously. Then, set this bit to "1" 2 ms after the rewriting of the PLL multiplication ratio select bits. (See Figure 5.2.3.) Table 5.2.1 fsys selection System clock select bit (bit 5) fsys PLL circuit operation enable bit PLL multiplication ratio select bits (bit 1) (bits 3, 2) (Note 1) Clock source Frequency (Note 2) 0 - - fX IN f(XIN) 1 1 01 (double) fPLL f(XIN ) 2 10 (triple) fPLL f(XIN ) 3 11 (quadruple) fPLL f(XIN ) 4 Notes 1: The PLL multiplication ratio select bits must be set so that fsys is in the range from 10 MHz to 26 MHz. After reset, these bits are allowed to be changed only once. 2: Be sure that fsys does not exceed 26 MHz. (4) Peripheral device's clock select bits 1, 0 (bits 7, 6) These bits select the internal peripheral device's operation clock frequency listed in Table 5.2.2. Table 5.2.2 Internal peripheral device's operation clock frequency Peripheral device's clock select bits 1, 0 Internal peripheral device's operation clock 00 01 (Note) 10 f1 fsys fsys fsys/2 f2 fsys/2 fsys fsys/4 f16 fsys/16 fsys/8 fsys/32 f64 fsys/64 fsys/32 fsys/128 f512 fsys/512 fsys/256 fsys/1024 f4096 fsys/4096 fsys/2048 fsys/8192 11 Do not select. Note: To set the peripheral device's clock select bits 1, 0 to "012," be sure that a frequency of fsys must be 13 MHz or less. 7902 Group User's Manual 5-7 CLOCK GENERATING CIRCUIT 5.2 Clocks AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA b7 b0 0 0 1 1 Clock control register (Address BC16) PLL frequency multiplier is active, and pin VCONT is valid. PLL multiplication ratio select bits (Note 1) b3 b2 0 1 : Double 1 0 : Triple 1 1 : Quadruple System clock select bit 0 : fXIN (Note 2) 2 ms elapsed ? N AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA Y Setting of system clock select bit to "1." b7 b0 1 0 1 1 Clock control register (Address BC16) System clock select bit 0 : fPLL Notes 1: After reset, these bits are allowed to be changed only once. If it is necessary to write a certain value to these bits, be sure to write the same value that has been written after the latest reset. 2: This decision is unnecessary If double is selected and the period of RESET = "L" is "the oscillation stabilizing time of an oscillator + 2 ms" or more. Fig. 5.2.3 Setting procedure for clock control register when using PLL frequency multiplier 5-8 7902 Group User's Manual CLOCK GENERATING CIRCUIT 5.2 Clocks 5.2.3 Particular function select register 0 Figure 5.2.4 shows the structure of the particular function select register 0, and Figure 5.2.5 shows the writing procedure for the particular function select register 0. b7 b6 b5 b4 b3 b2 b1 b0 Particular function select register 0 (Address 6216) Bit Bit name 0 0 0 0 0 0 Function 0 STP instruction invalidity select bit 0 : STP instruction is valid. 1 : STP instruction is invalid. 1 External clcok input select bit 0 : Oscillation circuit is active. (Oscillator is connected.) Watchdog timer is used at stop mode termination. 1 : Oscillation circuit is inactive. (External clock is input.) At reset R/W 0 RW (Note) RW (Note) 0 When the system clock select bit (bit 5 at address BC16) = "0," watchdog timer is not used at stop mode termination. When the system clock select bit = "1," watchdog timer is used at stop mode termination. 7 to 2 Fix this bit to "0." 0 RW Note: Writing to these bits requires the following procedure: * Write "5516" to this register. (The bit status does not change only by this writing.) * Succeedingly, write "0" or "1" to each bit. Also, use the MOVMB (MOVM when m = 1) instruction or STAB (STA when m = 1) instruction. If an interrupt occurs between writing of "5516" and next writing of "0" or "1," latter writing may be ignored. When there is a possibility that an interrupt occurs at the above timing, be sure to read this bit's contents after writing of "0" or "1," and verify whether "0" or "1" has correctly been written or not. Fig. 5.2.4 Structure of particular function select register 0 7902 Group User's Manual 5-9 CLOCK GENERATING CIRCUIT 5.2 Clocks (1) External clock input select bit (bit 1) Setting this bit to "1" stops the oscillation driver circuit between pins X IN and XOUT and keeps the output level at pin XOUT being "H." (Refer to section "17.4 Stop of oscillation circuit.") At the stop mode termination owing to an interrupt occurrence, the watchdog timer is not used if the system clock select bit (bit 5 at address BC 16 ) = "0," where as the watchdog timer is used if the system clock select bit = "1." To rewrite this bit, write "0" or "1" just after writing of "5516 " to address 6216. (See Figure 5.2.5.) Note that if an interrupt occurs between writing of "5516 " and next writing of "0" or "1," latter writing may be ignored. When there is a possibility that an interrupt occurs at the above timing, be sure to read this bit's contents after writing of "0" or "1," and verify whether "0" or "1" has correctly been written or not. In addition, even when the watchdog timer is disabled by the particular function select register 2 (address 64 16 ), the watchdog timer can be active only at the stop mode termination if this bit = "0." (Refer to section "16.3 Stop mode.") AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAA AAA AAA Writing of "5516" b7 0 b0 1 0 1 0 1 0 1 Particular function select register 0 (Address 6216) Note: Bits' state does not change only by writing of "5516." Writing to bits 0, 1 b7 0 0 b0 0 0 0 0 Particular function select register 0 (Address 6216) STP instruction invalidity select bit 0 : STP instruction is valid. 1 : STP instruction is invalid. External clock input select bit 0 : Oscillation circuit is active. (Oscillator is connected.) Watchdog timer is used at stop mode termination. 1 : Oscillation circuit is inactive. (External clock is input.) When the system clock select bit (bit 5 at address BC16) = "0," watchdog timer is not used at stop mode termination. When the system clock select bit = "1," watchdog timer is used at stop mode termination. Setting completed Fig. 5.2.5 Writing procedure for particular function select register 0 5-10 7902 Group User's Manual Next instruction CLOCK GENERATING CIRCUIT [Precautions for clock generating circuit] [Precautions for clock generating circuit] 1. While pin RESET = "L" level and after reset, the PLL frequency multiplier is inactive. Clear the PLL circuit operation enable bit (bit 1 at address BC16) to "0" if the PLL frequency multiplier need not to be active. 2. To select f PLL as f sys after reset, set the system clock select bit (bit 5 at address BC 16 ) to "1" 2 ms after f(XIN) has been stabilized. (See Figure 5.2.3.) 3. To rewrite the PLL multiplication ratio for the PLL frequency multiplier, clear the system clock select bit (bit 5 at address BC16 ) to "0" simultaneously. Then, set the system clock select bit to "1" 2 ms after the rewriting of the PLL multiplication ratio select bits (bits 2, 3 at address BC16). (See Figure 5.2.3.) After reset, the PLL multiplication ratio select bits are allowed to be changed only once. If it is necessary to write a certain value to these bits, be sure to write the same value that has been written after the latest reset. 7902 Group User's Manual 5-11 CLOCK GENERATING CIRCUIT [Precautions for clock generating circuit] MEMORANDUM 5-12 7902 Group User's Manual CHAPTER 6 INPUT/OUTPUT PINS 6.1 Overview 6.2 Programmable I/O ports 6.3 Examples of handling unused pins INPUT/OUTPUT PINS 6.1 Overview, 6.2 Programmable I/O ports 6.1 Overview Input/output pins (hereafter called I/O pins) have functions as programmable I/O port pins, internal peripheral devices's I/O pins, external buses, etc. For the basic functions of each I/O pin, refer to section "1.3 Pin description." For the I/O functions of the internal peripheral devices, refer to relevant sections of each internal peripheral device. For the external address bus, external data bus, bus control signals, etc., refer to "CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES." This chapter describes the programmable I/O ports and examples of handling unused pins. 6.2 Programmable I/O ports The programmable I/O ports have direction registers and port registers in the SFR area. Figure 6.2.1 shows the memory map of direction registers and port registers. Addresses 216 Port P0 register 316 Port P1 register 416 Port P0 direction register 516 Port P1 direction register 616 Port P2 register 716 Port P3 register 816 Port P2 direction register 916 Port P3 direction register A16 Port P4 register B16 Port P5 register C16 Port P4 direction register D16 Port P5 direction register E16 Port P6 register F16 Port P7 register 1016 Port P6 direction register 1116 Port P7 direction register 1216 Port P8 register 1316 1416 Port P8 direction register 1516 1616 Port P10 register 1716 Port P11 register 1816 Port P10 direction register 1916 Port P11 direction register Fig. 6.2.1 Memory map of direction registers and port registers 6-2 7902 Group User's Manual INPUT/OUTPUT PINS 6.2 Programmable I/O ports 6.2.1 Direction register This register determines the I/O direction of programmable I/O ports. One bit of this register corresponds to one pin of the microcomputer, and this is the one-to-one relationship. Figure 6.2.2 shows the structure of port Pi (i = 0 to 8, 10, 11) direction register. b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (i = 0 to 8, 10, 11) (Addresses 416, 516, 816, 916, C16, D16, 1016, 1116, 1416, 1816, 1916) Bit Bit name Function At reset R/W 0 RW 0 RW 0 RW 0 Port Pi0 direction bit 1 Port Pi1 direction bit 2 Port Pi2 direction bit 3 Port Pi3 direction bit 0 RW 4 Port Pi4 direction bit 0 RW 5 Port Pi5 direction bit 0 RW 6 Port Pi6 direction bit 0 RW 7 Port Pi7 direction bit 0 RW 0 : Input mode (The port functions as an input port) 1 : Output mode (The port functions as an output port) Note: Nothing is assigned for bits 4 to 7 of the port P3 direction register. These bits are "0" at reading. Fig. 6.2.2 Structure of port Pi (i = 0 to 8, 10, 11) direction register 7902 Group User's Manual 6-3 INPUT/OUTPUT PINS 6.2 Programmable I/O ports 6.2.2 Port register Data is input from or output to the external by writing/reading data to/from a port register. A port register consists of a port latch which holds the output data and a circuit which reads the pin state. One bit of the port register corresponds to one pin of the microcomputer. (This is the one-to-one relationship.) Figure 6.2.3 shows the structure of the port Pi (i = 0 to 8, 10, 11) register. When outputting data from programmable I/O port which has been set to output mode By writing data to the corresponding bit of the port register, the data is written into the port latch. The data is output from the pin according to the contents of the port latch. By reading the port register of a port which has been set to the output mode, the contents of the port latch is read out, instead of the pin state. Accordingly, the output data can be correctly read out without being affected by an external load, etc. (Refer to "Figures 6.2.4 and 6.2.5.") When inputting data from programmable I/O port which has been set to input mode A pin which has been set to the input mode enters the floating state. By reading the corresponding bit of the port register, the data which has been input from the pin can be read out. By writing data to a port register of a programmable I/O port which has been set to the input mode, the data is written only into the port latch and is not output to the external (Note). This pin remains floating state. Note: When executing a read-modify-write instruction to a port register of a programmable I/O port which has been set to the input mode, the instruction will be executed to the data which has been input from the pin and the result will be written into the port register. b7 b6 b5 b4 b3 b2 b1 b0 Port Pi register (i = 0 to 8, 10, 11) (Addresses 216, 316, 616, 716, A16, B16, E16, F16, 1216, 1616, 1716) Bit Funtion Bit name R/W Undefined RW Undefined RW Undefined RW Undefined RW 0 Pin port Pi0 1 Pin port Pi1 2 Pin port Pi2 3 Pin port Pi3 4 Pin port Pi4 Undefined RW 5 Pin port Pi5 Undefined RW 6 Pin port Pi6 Undefined RW 7 Pin port Pi7 Undefined RW Data is input from or output to a pin by reading from or writing to the corresponding bit. 0 : "L" level 1 : "H" level Note: Nothing is assigned for bits 4 to 7 of the port P3 register. These bits are "0" at reading. Fig. 6.2.3 Structure of port Pi (i = 0 to 8, 10, 11) register 6-4 At reset 7902 Group User's Manual INPUT/OUTPUT PINS 6.2 Programmable I/O ports Figures 6.2.4 and 6.2.5 show the port peripheral circuits. [Inside dotted-line not included] P00 to P07, P10 to P17, P20 to P27, P31 to P33, P100 to P107, P110 to P117 Direction register Data bus Port latch [Inside dotted-line included] P30 /RDY, P4 3/HOLD, P6 1/TA4IN, P6 2/INT0, P6 3/INT1, P64 /INT2, P6 5/TB0IN, P6 6/TB1IN, P67 /TB2IN, P8 2/RXD0, P8 6/RXD1 [Inside dotted-line not included] P40/ALE, P41/1, P42/HLDA, P83/TXD0, P87/TXD1 Pullup selection Pullup transistor Direction register 1 [Inside dotted-line included] P60 /TA4OUT Output (Internal peripheral devices) Data bus Port latch [Shaded area included] P44 /CS0, P45/CS1, P46 /CS2, P47 /CS3 [Shaded area not included] P5 1/TA0IN/RTP01, P5 3/TA1IN/RTP03 [Shaded area included] P5 5/TA2IN/RTP11/KI1, P57 /TA3IN/RTP13/KI3 Pullup selection Data bus Port latch Latch Timer underflow signal [Shaded area not included] P5 0/TA0OUT/RTP00, P5 2/TA1OUT/RTP02 [Shaded area included] P5 4/TA2OUT/RTP10/KI0, P5 6/TA3OUT/RTP12/KI2 Pullup transistor Direction register T Q CK Pullup selection Pullup transistor Direction register 1 Output (Internal peripheral devices) Data bus Port latch Latch Timer underflow signal T Q CK Fig. 6.2.4 Port peripheral circuits (1) 7902 Group User's Manual 6-5 INPUT/OUTPUT PINS 6.2 Programmable I/O ports [Inside dotted-line not included] P70/AN0, P71/AN1, P72/AN2, P73/AN3 [Inside dotted-line included] P74/AN4/(INT3), P75/AN5/(INT4) Direction register Data bus Port latch Analog input P81/CTS0/CLK0, P84/CTS1/RTS1/INT4, P85/CTS1/CLK1 1 0 Direction register Output (Internal peripheral devices) Data bus Port latch [Inside dotted-line not included] P76/AN6/DA0 [Inside dotted-line included] P7 7/AN7/ADTRG/DA1/(INT2) Direction register Data bus Port latch Analog input Analog output Enable D-A output 1 P80/CTS0/RTS0/DA2/INT3 0 Direction register Output (Internal peripheral devices) Data bus Port latch Analog output Enable D-A output NMI Pullup selection Fig. 6.2.5 Port peripheral circuits (2) 6-6 7902 Group User's Manual Pullup transistor INPUT/OUTPUT PINS 6.2 Programmable I/O ports 6.2.3 Selectable functions In the usage of programmable I/O ports, the following items are selectable: Port P0 input level Port pins P44-P4 7 pullup function b7 b6 b5 b4 b3 b2 b1 b0 Port function control register (Address 9216) Bit 0 Bit name Address/Port switch bits 1 2 3 Port P0 input level select bit 4 Pins P44-P47 pullup select bit 6, 5 7 0 0 Function At reset R/W 0 0 0 : A0 to A23 (16 Mbytes) 0 0 1 : A0 to A21, P06, P07 (4 Mbytes) 0 1 0 : A0 to A19, P04 to P07 (1 Mbytes) 0 1 1 : A0 to A17, P02 to P07 (256 Kbytes) 1 0 0 : A0 to A15, P00 to P07 (64 Kbytes) 1 0 1 : Do not select. 1 1 0 : A0 to A11, P00 to P07, P114 to P117 (4 Kbytes) 1 1 1 : A0 to A7, P00 to P07, P110 to P117 (256 bytes) 0 : VIH = 0.7 Vcc, VIL = 0.2 Vcc 1 : VIH = 0.43 Vcc (Note 1), VIL = 0.16 Vcc 0 RW 0 RW 0 RW 0 RW 0 : Pins P44-P47 are pulled up. 1 : Pins P44-P47 are not pulled up (Notes 2, 3). 0 RW 0 RW 0 RW b2 b1b0 Fix these bits to "0". Pin NMI pullup select bit 0 : Pin NMI is pulled up. 1 : Pin NMI is not pulled up (Note 2). Notes 1: For the M37902FxM (power source voltage = 3.3 V0.3 V), VIH = 0.5Vcc. 2: When MD1 = Vcc and MD0 = Vcc (flash memory parallel I/O mode), pins P44 to P47 and NMI are not pulled up, regardless of these bits' contents. 3: When MD1 = Vss and MD0 = Vcc (microprocessor mode), pin CS0 (P44) is not pulled up regardless of this bit's contents. Fig. 6.2.6 Structure of port function control register (1) Port P0 input level select bit (bit 3) This bit allows the user to select the input level to port P0 (VIH, V IL). According to the external devices to be connected with port P0, set this bit's contents. (2) Pins P4 4-P47 pullup select bit (bit 4) While the voltage level at pin RESET = "L" and after reset, this bit = "0" and pins P44-P47 are pulled up. Accordingly, no external pullup resistor is necessary. By setting this bit to "1," the pullup state is removed. When one of the following settings is selected, the pullup state is removed regardless of this bit's contents. (The bit's contents do not change.) * The P44-P4 7 direction registers are set to "1" (output mode). * The CS0 to CS 3 output select bits (bit 7 at addresses 80 16 , 82 16 , 84 16, 86 16 ) are set to "1". (By this setting, the CS 0/CS 1/CS 2/CS 3 outputs become enabled.) Regardless of this bit's contents; * Pins P4 4-P47 are not pulled up in the flash memory parallel I/O mode (MD1 = Vcc, MD0 = Vcc). * Pin CS0 (P4 4) is not pulled up in the microprocessor mode (MD1 = Vss, MD 0 = Vcc). For the flash memory parallel I/O mode, refer to the section on "20.4 Flash memory parallel I/O mode". 7902 Group User's Manual 6-7 INPUT/OUTPUT PINS 6.3 Examples of handling unused pins 6.3 Examples of handling unused pins When unusing an I/O pin, some handling is necessary for this pin. Examples of handling unused pins are described below. The following are just examples. In actual use, the user shall modify them according to the user's application and properly evaluate their performance. 6.3.1 In the single-chip mode Table 6.3.1 Example of handling unused pins in single-chip mode Pin name P0 to P3, P4 0 to P4 3, P5 to P8, P10, P11 P4 4 to P4 7 NMI (Notes 2, 4), XOUT (Note 5), V CONT (Note 6) AV CC AV SS, V REF, BYTE Handling example Set these pins to the input mode and connect each pin to Vcc or Vss via a resistor; or set these pins to the output mode and leave them open (Note 1). Set these pins to the input mode and leave them open (Notes 2, 3) Leave these pins open. Connect this pin to Vcc. Connect these pins to Vss. Notes 1: When leaving these pins open after they have been set to the output mode, note the following: these port pins are placed in the input mode from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these port pins are placed in the input mode. Software reliability can be enhanced by setting the contents of the above ports' direction registers periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer's pins). 2: Do not connect these pins to Vss. 3: Be sure that the pins P44-P47 pullup select bit (bit 4 at address 9216) = 0. 4: Be sure that the pin NMI pullup select bit (bit 7 at address 9216) = 0. 5: This applies when a clock externally generated is input to pin XIN. 6: Be sure that the PLL circuit operation enable bit (bit 1 at address BC16) = 0. When setting port pins to input mode P0-P3, P40-P43, P5-P8, P10, P11 P0-P8, P10, P11 Left open NMI XOUT VCONT Left open Left open M37902 M37902 P44-P47 NMI XOUT VCONT When setting port pins to output mode (Note) VCC AVCC AVSS VREF BYTE VCC AVCC AVSS VREF BYTE VSS VSS Note: Be sure to set P44-P47 to the input mode. Fig. 6.3.1 Example of handling unused pins in single-chip mode 6-8 7902 Group User's Manual INPUT/OUTPUT PINS 6.3 Examples of handling unused pins 6.3.2 In memory expansion and microprocessor modes Table 6.3.2 Example of handling unused pins in memory expansion and microprocessor modes Pin name Handling example P2 (Note 1), P30, P33 (Note 1), P40 to P43, P5 to P8 Set these pins to the input mode and connect each pin to Vcc or Vss via a resistor; or set these pins to the output mode and leave them open (Note 2). P4 4 to P47 NMI (Notes 3, 5), X OUT (Note 6), V CONT (Note 7) AV CC AV SS, V REF Set these pins to the input mode and leave them open (Notes 3,4) Leave these pins open. Connect this pin to Vcc. Connect these pins to Vss. Leave these pins open. 1 (Note 8), ALE (Note 8), HLDA (Note 8) RDY (Note 8), HOLD (Note 8) Connect these pins to Vcc via a resistor. Notes 1: This applies when the V CC level voltage is applied to pin BYTE. 2: When leaving these pins open after they have been set to the output mode, note the following: these port pins are placed in the input mode from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins are placed in the input mode. Software reliability can be enhanced by setting the contents of the above ports' direction registers periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. 3: Do not connect these pins to Vss. 4: Be sure that the pins P44-P47 pullup select bit (bit 4 at address 92 16) = 0. 5: Be sure that the pin NMI pullup select bit (bit 7 at address 9216) = 0. 6: This applies when a clock externally generated is input to pin X IN. 7: Be sure that the PLL circuit operation enable bit (bit 1 at address BC16) = 0. 8: This applies when the Vcc-level voltage is applied to pin MD0. (It is also possible to disable these functions by software and use these pins as programmable I/O port pins.) When setting port pins to output mode When setting port pins to input mode P2, P30, P33, P40-P43, P5-P8 Left open 1 ALE HLDA RDY HOLD Left open Left open VCC 1 ALE HLDA M37902 M37902 VCC P44-P47 NMI XOUT VCONT P2, P30, P33, P4-P8 VCC AVCC AVSS VREF RDY HOLD NMI XOUT VCONT Left open Left open VCC AVCC AVSS VREF VSS VSS Note: Be sure to set P44-P47 to the input mode. Fig. 6.3.2 Example of handling unused pins in memory expansion and microprocessor modes 7902 Group User's Manual 6-9 INPUT/OUTPUT PINS 6.3 Examples of handling unused pins MEMORANDUM 6-10 7902 Group User's Manual CHAPTER 7 INTERRUPTS 7.1 7.2 7.3 7.4 7.5 Overview Interrupt sources Interrupt control Interrupt priority level Interrupt priority level detection circuit 7.6 Interrupt priority level detection time 7.7 Sequence from acceptance of interrupt request until execution of interrupt routine 7.8 Return from interrupt routine 7.9 Multiple interrupts 7.10 External interrupts [Precautions for interrupts] INTERRUPTS 7.1 Overview 7.1 Overview The M37902 provides 23 (including the reset) interrupt sources to generate interrupt requests. Figure 7.1.1 shows the interrupt processing sequence. When an interrupt request is accepted, a branch is made to the start address of the interrupt routine set in the interrupt vector table (addresses FFC0 16 to FFFF 16 ). Set the start address of each interrupt routine to the corresponding interrupt vector address in the interrupt vector table. Routine in progress ress add art . t s o e es t utin nch rupt ro a r B ter of in Interrupt request is accepted. Interrupt routine Interrupt processing Processing is suspended. Retu rns t Processing is resumed. o ori ginal routi Fig. 7.1.1 Interrupt processing sequence 7-2 7902 Group User's Manual ne. RTI instruction INTERRUPTS 7.1 Overview When an interrupt request is accepted, the following registers' contents just before acceptance of an interrupt request are automatically pushed onto the stack area in ascending sequence from to . For other registers of which contents are necessary, be sure to push and pop them by software. Program bank register (PG) Program counter (PC L, PC H) Processor status register (PS L, PSH ) Figure 7.1.2 shows the state of the stack area just before entering an interrupt routine. Execute the RTI instruction at the end of this interrupt routine in order to return to the routine that the microcomputer was executing just before the interrupt request was accepted. By executing the RTI instruction, the register contents pushed onto the stack area are pulled in descending sequence from to . Then, the suspended processing is resumed from where it left off. Stack area Address [S] - 5 [S] - 4 Processor status register's low-order byte (PSL) [S] - 3 Processor status register's high-order byte (PSH) [S] - 2 Program counter's low-order byte (PCL) [S] - 1 Program counter's high-order byte (PCH) [S] Program bank register (PG) [S] is an initial address that the stack pointer (S) indicates when an interrupt request is accepted. The S's contents become "[S] - 5" after all of the above registers are pushed. Fig. 7.1.2 State of stack area just before entering interrupt routine 7902 Group User's Manual 7-3 INTERRUPTS 7.2 Interrupt sources 7.2 Interrupt sources Table 7.2.1 lists the interrupt sources and the interrupt vector addresses. When programming, set the start address of each interrupt routine to the vector addresses listed in this table. Table 7.2.1 Interrupt sources and interrupt vector addresses Interrupt vector addresses Remarks Reference High-order Low-order address address FFFE16 Non-maskable Reset FFFF16 4. RESET Non-maskable software interrupt FFFC 16 Zero division FFFD16 7900 Series Software Manual FFFA16 Do not use. BRK instruction (Note) FFFB16 ____ FFF816 DBC (Note) FFF916 FFF616 Non-maskable internal interrupt 15. WATCHDOG TIMER Watchdog timer FFF716 ____ FFF416 Non-maskable external interrupt 7.10 External interrupts NMI FFF516 ____ FFF216 Maskable external interrupts INT 0 FFF316 Interrupt source ____ INT 1 INT 2 Timer A0 Timer A1 Timer A2 FFF116 FFEF16 FFED 16 FFEB16 FFE916 FFF016 FFEE16 FFEC 16 FFEA16 FFE816 Maskable internal interrupts 9. TIMER A Timer Timer Timer Timer Timer A3 A4 B0 B1 B2 FFE716 FFE516 FFE316 FFE116 FFDF16 FFE616 FFE416 FFE216 FFE016 FFDE 16 Maskable internal interrupts 10. TIMER B UART0 receive UART0 transmit UART1 receive UART1 transmit A-D conversion FFDD16 FFDB 16 FFD916 FFD716 FFD516 FFDC16 FFDA 16 FFD816 FFD616 FFD416 Maskable internal interrupts 12. SERIAL I/O FFD216 FFD016 FFCE 16 FFCC16 FFCA 16 13. A-D CONVERTER 7.10 External interrupts Address matching detection FFD316 FFD116 FFCF16 FFCD16 FFCB 16 Maskable internal interrupt Maskable external interrupts Reserved Reserved Reserved Reserved Reserved FFC916 FFC716 FFC516 FFC316 FFC116 FFC816 FFC616 FFC416 FFC216 FFC016 ____ ____ INT 3 INT 4 Reserved area Reserved area ____ area area area area area Do not use. Non-maskable software interrupt 18. DEBUG FUNCTION Do not use. ____ Note: The BRK instruction and the DBC interrupt are used exclusively for a debugger. Maskable interrupt: An interrupt of which request's acceptance can be disabled by software. ____ Non-maskable interrupt (including zero division, watchdog timer, NMI, and address matching detection interrupts): An interrupt which is certain to be accepted when its request occurs. These interrupts do not have their interrupt control registers and are not affected by the interrupt disable flag (I). 7-4 7902 Group User's Manual INTERRUPTS 7.3 Interrupt control 7.3 Interrupt control The maskable interrupts are controlled by the following : *Interrupt request bit Assigned to an interrupt control register of each interrupt. *Interrupt priority level select bits *Processor interrupt priority level (IPL) Assigned to the processor status register (PS). *Interrupt disable flag (I) } } Figure 7.3.1 shows the memory assignment of the interrupt control registers, and Figures 7.3.2 and 7.3.3 show their structures. Address 6E16 INT3 interrupt control register 6F16 INT4 interrupt control register 7016 A-D conversion interrupt control register 7116 UART0 transmit interrupt control register 7216 UART0 receive interrupt control register 7316 UART1 transmit interrupt control register 7416 UART1 receive interrupt control register 7516 Timer A0 interrupt control register 7616 Timer A1 interrupt control register 7716 Timer A2 interrupt control register 7816 Timer A3 interrupt control register 7916 Timer A4 interrupt control register 7A16 Timer B0 interrupt control register 7B16 Timer B1 interrupt control register 7C16 Timer B2 interrupt control register 7D16 INT0 interrupt control register 7E16 INT1 interrupt control register 7F16 INT2 interrupt control register Fig. 7.3.1 Memory assignment of interrupt control registers 7902 Group User's Manual 7-5 INTERRUPTS 7.3 Interrupt control A-D conversion, UART0 and 1 transmit, UART0 and 1 receive, timers A0 to A4, timers B0 to B2 interrupt control registers (Addresses 7016 to 7C 16) Bit 0 Bit name Interrupt priority level select bits 1 2 3 Interrupt request bit 7 to 4 Nothing is assigned. Function b2 b1 b0 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0 : No interrupt requested 1 : Interrupt requested At reset R/W 0 RW 0 RW 0 RW 0 RW (Note 1) (Note 2) Undefined Notes 1: The A-D conversion interrupt request bit is undefined after reset. 2: When writing to this bit, use the MOVM (MOVMB) or STA (STAB, STAD) instruction. Fig. 7.3.2 Structure of interrupt control register (1) 7-6 b7 b6 b5 b4 b3 b2 b1 b0 7902 Group User's Manual -- INTERRUPTS 7.3 Interrupt control b7 b6 b5 b4 b3 b2 b1 b0 INT0 to INT2 interrupt control registers (Addresses 7D16 to 7F 16) Bit 0 Function Bit name Interrupt priority level select bits 1 2 b2 b1 b0 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 At reset R/W 0 RW 0 RW 0 RW 3 Interrupt request bit (Note 1) 0 : No interrupt requested 1 : Interrupt requested 0 RW (Note 2) 4 Polarity select bit 0 : The interrupt request bit is set to "1" at "H" level when level sense is selected; this bit is set to "1" at falling edge when edge sense is selected. 1 : The interrupt request bit is set to "1" at "L" level when level sense is selected; this bit is set to "1" at rising edge when edge sense is selected. 0 RW 5 Level sense/Edge sense select bit 0 : Edge sense 1 : Level sense 0 RW Undefined -- 7, 6 Nothing is assigned. Notes 1: The interrupt request bits of INT0 to INT2 interrupts are invalid when the level sense is selected. 2: When writing to this bit, use the MOVM (MOVMB) or STA (STAB, STAD) instruction. b7 b6 b5 b4 b3 b2 b1 b0 INT3, INT4 interrupt control registers (Addresses 6E16, 6F16) Bit 0 Bit name Interrupt priority level select bits 1 2 3 Interrupt request bit 4 Polarity select bit 7 to 5 Function b2 b1 b0 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0 : No interrupt requested 1 : Interrupt requested 0 : The interrupt request bit is set to "1" at the falling edge. 1 : The interrupt request bit is set to "1" at the rising edge. Nothing is assigned. At reset R/W 0 RW 0 RW 0 RW 0 RW (Note) 0 RW Undefined -- Note: When writing to this bit, use the MOVM (MOVMB) or STA (STAB, STAD) instruction. Fig. 7.3.3 Structure of interrupt control register (2) 7902 Group User's Manual 7-7 INTERRUPTS 7.3 Interrupt control 7.3.1 Interrupt disable flag (I) All maskable interrupts can be disabled by this flag. When this flag is set to "1," all maskable interrupts are disabled; when this flag is cleared to "0," those interrupts are enabled. Because this flag is set to "1" at reset, clear this flag to "0" when enabling interrupts. 7.3.2 Interrupt request bit When an interrupt request occurs, this bit is set to "1." This bit remains set to "1" until the interrupt request is accepted; it is cleared to "0" when the interrupt request is accepted. This bit can also be set to "0" or "1" by software. The INT i interrupt request bit (i = 0 to 2) is ignored when the corresponding INTi interrupt is used with the level sense. 7.3.3 Interrupt priority level select bits and Processor interrupt priority level (IPL) The interrupt priority level select bits are used to determine the priority level of each interrupt. When an interrupt request occurs, its interrupt priority level is compared with the processor interrupt priority level (IPL). The requested interrupt is enabled only when the comparison result meets the following condition. Accordingly, any interrupt can be disabled by setting its interrupt priority level to 0. Each interrupt priority level > Processor interrupt priority level (IPL) Table 7.3.1 lists the setting of interrupt priority levels, and Table 7.3.2 lists the enabled interrupt's levels according to the IPL contents. The interrupt disable flag (I), interrupt request bit, interrupt priority level select bits, and processor interrupt priority level (IPL) are independent of one another; they do not affect one another. Interrupt requests are accepted only when all of the following conditions are satisfied. *Interrupt disable flag (I) = "0" *Interrupt request bit = "1" *Interrupt priority level > Processor interrupt priority level (IPL) 7-8 7902 Group User's Manual INTERRUPTS 7.3 Interrupt control Table 7.3.1 Setting of interrupt priority level Interrupt priority level select bits b1 b0 b2 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 1 1 1 1 Interrupt priority level Level 0 (Interrupt disabled) Level 1 Level Level Level Level Level Priority -- Low 2 3 4 5 6 Level 7 High Table 7.3.2 Enabled interrupt's levels according to IPL contents IPL2 0 0 IPL 1 0 0 IPL 0 0 1 0 0 1 1 1 1 1 0 0 1 0 1 0 1 0 Enabled interrupt's level Level 1 and above are enabled. Level 2 and above are enabled. Level 3 and above are enabled. Level 4 and above are enabled. Level 5 and above are enabled. Levels 6 and 7 are enabled. Only level 7 is enabled. 1 1 1 All maskable interrupts are disabled. IPL0: Bit 8 in processor status register (PS) IPL1: Bit 9 in processor status register (PS) IPL2: Bit 10 in processor status register (PS) 7902 Group User's Manual 7-9 INTERRUPTS 7.4 Interrupt priority level 7.4 Interrupt priority level When the interrupt disable flag (I) = "0" (interrupts enabled) and more than one interrupt request is detected at the same sampling timing, which means a timing to check whether an interrupt request exists or not, they are accepted in descending sequence from the highest priority level. A maskable interrupt can be set to the desired priority level by using the interrupt priority level select bits. The priority levels of reset, a watchdog timer interrupt, and an NMI interrupt are set by hardware. Figure 7.4.1 shows the interrupt priority levels set by hardware. Note that software interrupts are not affected by the interrupt priority levels. Whenever an instruction is executed, a branch is certainly made to the interrupt routine. Reset Watchdog timer NMI ****************** Maskable interrupts Priority levels determined by hardware The user can set the desired priority level to a maskable interrupt. Low Priority level Fig. 7.4.1 Interrupt priority levels set by hardware 7-10 7902 Group User's Manual High INTERRUPTS 7.5 Interrupt priority level detection circuit 7.5 Interrupt priority level detection circuit The interrupt priority level detection circuit is used to select the interrupt with the highest priority level from multiple interrupt requests sampled at the same timing. Figure 7.5.1 shows the interrupt priority level detection circuit. Interrupt priority level Level 0 (Initial value) INT4 INT3 Interrupt priority level A-D conversion Timer A4 UART1 transmit Timer A3 UART1 receive Timer A2 UART0 transmit Timer A1 UART0 receive Timer A0 Timer B2 INT2 Timer B1 INT1 Timer B0 INT0 Interrupt with the highest priority level IPL Processor interrupt priority level Interrupt disable flag (I) NMI interrupt Watchdog timer interrupt Reset Accepting of interrupt request Fig. 7.5.1 Interrupt priority level detection circuit 7902 Group User's Manual 7-11 INTERRUPTS 7.5 Interrupt priority level detection circuit The following explains the operation of the interrupt priority level detection circuit using Figure 7.5.2. The interrupt priority level of a requested interrupt (Y in Figure 7.5.2) is compared with the resultant priority level which is sent from the preceding comparator (X in Figure 7.5.2); the interrupt with the higher priority level will be sent to the next comparator (Z in Figure 7.5.2). (The initial value of the comparison level is "0.") For an interrupt which is not requested, the comparison is not performed, and the priority level which is sent from the preceding comparator is sent to the next comparator as it is. When the two priority levels are found the same, as a resultant of the comparison, the priority level which is sent from the preceding comparator will be sent to the next comparator. Accordingly, when the same priority level is set to multiple interrupts by software, their interrupt priority levels are handled as follows: ____ ____ INT4 > INT3 > A-D conversion > UART1 transmit > UART1 receive > UART0 transmit > UART0 receive > ____ ____ Timer B2 > Timer B1 > Timer B0 > Timer A4 > Timer A3 > Timer A2 > Timer A1 > Timer A0 > INT 2 > INT 1 ____ > INT0 Among the multiple interrupt requests sampled at the same timing, one request with the highest priority level is detected by the above comparison. Then, this highest interrupt priority level is compared with the processor interrupt priority level (IPL). When this interrupt priority level is higher than IPL and the interrupt disable flag (I) is "0," the interrupt request is accepted. An interrupt request which is not accepted here is retained until it is accepted or its interrupt request bit is cleared to "0" by software. The interrupt priority level is detected when the CPU fetches an op code, which is called the CPU's op-code fetch cycle. However, when an op-code fetch cycle starts during detection of an interrupt priority, a new interrupt priority detection does not start. (See Figure 7.6.2.) Since the state of the interrupt request bit and interrupt priority levels are latched during the interrupt priority detection, even if they change, the interrupt priority detection is performed for the state just before the change occurs. The interrupt priority level is detected when the CPU fetches an op code. Therefore, in the following case, no interrupt request is accepted until the CPU fetches the op code of the next instruction after the following operation is completed: *Execution of an instruction which requires many cycles, such as the MVN and MVP instructions X Time Y Interrupt source Y Comparator (Priority level comparison) Z X : Priority level sent from the preceding comparator (Highest priority level at this point) Y : Priority level of interrupt source Y Z : Highest priority level at this point When X Y then Z = X When X < Y then Z = Y Fig. 7.5.2 Interrupt priority level detection model 7-12 7902 Group User's Manual INTERRUPTS 7.6 Interrupt priority level detection time 7.6 Interrupt priority level detection time When the interrupt priority level detection time has passed after sampling starts, an interrupt request is accepted. The interrupt priority level detection time can be selected by software. (See Figure 7.6.1.) Usually, select "2 cycles of fsys " as the interrupt priority level detection time. Figure 7.6.2 shows the interrupt priority level detection time. b7 b6 b5 b4 b3 b2 b1 b0 Processor mode register 0 (Address 5E16) Bit Bit name 0 Processor mode bits Function At reset R/W 0 RW (Note 1) RW 0 RW 1 RW Interrupt priority level detection b5 b4 0 0 : 7 cycles of fsys time select bits 0 1 : 4 cycles of fsys 1 0 : 2 cycles of fsys 1 1 : Do not select. 0 RW 0 RW 6 Software reset bit The microcomputer is reset by writing "1" to this bit. The value is "0" at reading. 0 WO 7 Clock 1 output select bit 0 : 1 output is disabled. (P4 1 functions as a (Note 3) programmable I/O port pin.) 1 : 1 output is enabled. (P4 1 functions as a clock 1 output pin.) b1 b0 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode 1 1 : Do not select. 1 2 External bus cycle select bit 0 (Note 2) 3 4 5 (External bus cycle select (External bus cycle select bit 1 = 0) bit 1 = 1) b3 b2 b3 b2 0 0 : 1 + 1 0 1 : 1 + 2 1 0 : 1 + 3 1 1 : 2 + 2 0 0 : 2 + 3 0 1 : 2 + 4 1 0 : 3 + 3 1 1 : 3 + 4 RW Notes 1: When the Vss-level voltage is applied to pin MD0, this bit is "0"; when the Vcc-level voltage is applied to pin MD0, this bit is "1." (Fixed to "1.") 2: These bits are valid for the external area except for area CSi. Regardless of these bits' contents, the bus cycle of area CSi is decided by the corresponding area CSi bus cycle select bits 0, 1 (bits 0, 1 at addresses 8016 , 8216 , 8416 , 8616, and bit 3 at addresses 8116, 8316 , 8516 , 8716 ). 3: When the Vss-level voltage is applied to pin MD0, this bit is "0"; when the Vcc-level voltage is applied to pin MD0, this bit is "1." Fig. 7.6.1 Structure of processor mode register 0 fsys Op-code fetch cycle Sampling pulse (Note) (a) 7 cycles of fsys Interrupt priority level detection time (b) 4 cycles of fsys (c) 2 cycles of fsys Note: The pulse resides when "2 cycles of fsys" is selected. Fig. 7.6.2 Interrupt priority level detection time 7902 Group User's Manual 7-13 INTERRUPTS 7.7 Sequence from acceptance of interrupt request until execution of interrupt routine 7.7 Sequence from acceptance of interrupt request until execution of interrupt routine The sequence from acceptance of an interrupt request until execution of the interrupt routine is described below. When an interrupt request is accepted, the interrupt request bit of the accepted interrupt is cleared to "0." And then, the interrupt processing starts from the cycle just after completion of the instruction execution which was executed at acceptance of the interrupt request. Figure 7.7.1 shows the sequence from acceptance of an interrupt request until execution of the interrupt routine. After execution of an instruction at acceptance of the interrupt request is completed, an INTACK (Interrupt Acknowledge) sequence is executed, and a branch is made to the start address of the interrupt routine allocated in addresses 0 16 to FFFF 16. In the INTACK sequence, the following are automatically performed in ascending sequence from to . The contents of the program bank register (PG) just before performing the INTACK sequence are pushed onto stack. The contents of the program counter (PC) just before performing the INTACK sequence are pushed onto stack. The contents of the processor status register (PS) just before performing the INTACK sequence is pushed onto stack. The interrupt disable flag (I) is set to "1." The interrupt priority level of the accepted interrupt is set into the processor interrupt priority level (IPL). The contents of the program bank register (PG) are cleared to "0016 ," and the contents of the interrupt vector address are set into the program counter (PC). Performing the INTACK sequence requires at least 15 cycles of fsys. Figure 7.7.2 shows the INTACK sequence timing. After the INTACK sequence is completed, the instruction execution starts from the start address of the interrupt routine. Interrupt request is accepted. Interrupt request occurs. @ @ Instruction Instruction 1 2 INTACK sequence Time Instructions in interrupt routine Interrupt response time @ : Interrupt priority level detection time Time from occurrence of an interrupt request until comparison of an instruction execution which is in progress at that time. Time from execution start of an instruction next to until completion of execution of the instruction which was in progress at detection completed. Time required to perform the INTACK sequence (15 cycles of at minimum) Fig. 7.7.1 Sequence from acceptance of interrupt request until execution of interrupt routine 7-14 7902 Group User's Manual INTERRUPTS 7.7 Sequence from acceptance of interrupt request until execution of interrupt routine When stack pointer (S)'s contents are even at acceptance of an interrupt request with bus cycle = 1 + 1 fsys CPU AD23-AD16 Undefined 00 00 00 00 00 00 AD15-AD0 Undefined 0000 [S] [S] - 2 [S] - 4 FFXX16 AD15-AD0 DB15-DB8 Undefined DB7-DB0 Undefined RD IPL -- PCH PSH AD15-AD8 Next instruction PG PCL PSL AD7-AD0 Next instruction Vector address (low-order) BLW BHW INTACK sequence [S]: Contents of stack pointer (S) FFXX16: Vector address fsys, CPU: Internal clock (See Figure 5.2.1.) AD23-AD0: Internal address bus DB15-DB0: Internal data bus Note: When the stack area is in the internal area, above signals are not output to the external. When the stack area is in the external area, AD23-AD0(A23-A0),DB15-DB0(D15-D0), RD, BLW, and BHW are output to the external. (fsys can always be output as 1). Fig. 7.7.2 INTACK sequence timing (at minimum) 7.7.1 Change in IPL at acceptance of interrupt request When an interrupt request is accepted, the processor interrupt priority level (IPL) is replaced with the interrupt priority level of the accepted interrupt. This results in easy control of the processing for multiple interrupts. (Refer to section "7.9 Multiple interrupts.") At acceptance of a watch dog timer interrupt request, an NMI interrupt request, a zero division request, or address matching detection interrupt request or at reset, a value in Table 7.7.1 is set into the IPL. Table 7.7.1 Change in IPL at acceptance of interrupt request Interrupts Change in IPL Reset Watchdog timer NMI Zero division Address matching detection Level 0 ("000 2") is set. Level 7 ("111 2") is set. Level 7 ("111 2") is set. Not changed. Not changed. Other interrupts Accepted interrupt's priority level is set. 7902 Group User's Manual 7-15 INTERRUPTS 7.7 Sequence from acceptance of interrupt request until execution of interrupt routine 7.7.2 Push operation for registers The push operation for registers performed in the INTACK sequence depends on whether the contents of the stack pointer (S) at acceptance of an interrupt request are even or odd. When the contents of the stack pointer (S) are even, the contents of the program counter (PC) and the processor status register (PS) are simultaneously pushed in a unit of 16 bits. When the contents of the stack pointer (S) are odd, each of PC and PS is pushed in a unit of 8 bits. Figure 7.7.3 shows the push operation for registers. In the INTACK sequence, only the contents of the program bank register (PG), program counter (PC), and processor status register (PS) are pushed onto the stack area. Other necessary registers must be pushed by software at the start of the interrupt routine. By using the PSH instruction, all CPU registers, except the stack pointer (S), can be pushed with 1 instruction. (1) When contents of stack pointer (S) are even Address [S] - 5 (odd) Order for push [S] - 4 (even) Low-order byte of processor status register (PSL) [S] - 3 (odd) High-order byte of processor status register (PSH) Pushed in a unit of 16 bits. [S] - 2 (even) Low-order byte of program counter (PCL) [S] - 1 (odd) High-order byte of program counter (PCH) [S] (even) Pushed in a unit of 16 bits. Program bank register (PG) Pushed in 3 times. (2) When contents of stack pointer (S) are odd Address Order for push [S] - 5 (even) [S] - 4 (odd) Low-order byte of processor status register (PSL) [S] - 3 (even) High-order byte of processor status register (PSH) [S] - 2 (odd) Low-order byte of program counter (PCL) [S] - 1 (even) High-order byte of program counter (PCH) Program bank register (PG) [S] (odd) Pushed in a unit of 8 bits. Pushed in 5 times. [S] is the initial address that the stack pointer (S) indicates at acceptance of an interrupt request. The S's contents become "[S] - 5" after all of the above registers are pushed. Fig. 7.7.3 Push operation for registers 7-16 7902 Group User's Manual INTERRUPTS 7.8 Return from interrupt routine, 7.9 Multiple interrupts 7.8 Return from interrupt routine When the RTI instruction is executed at the end of the interrupt routine, the contents of the program bank register (PG), program counter (PC), and processor status register (PS) which were pushed onto the stack area just before the INTACK sequence are automatically pulled. After this, the control returns to the original routine. And then, the suspended processing, which was in progress before acceptance of the interrupt request, is resumed. Before the RTI instruction is executed, registers which were pushed by software in the interrupt routine must be pulled in the same data length and register length as those in pushing, using the PUL instruction, etc. 7.9 Multiple interrupts Just after a branch is made to an interrupt routine, the following occur: *Interrupt disable flag (I) = "1" (Interrupts are disabled.) *Interrupt request bit of accepted interrupt = "0" *Processor interrupt priority level (IPL) = Interrupt priority level of accepted interrupt Accordingly, as long as the IPL remains unchanged, an interrupt request, whose priority level is higher than that of the interrupt which is in progress, can be accepted by clearing the interrupt disable flag (I) to "0" in an interrupt routine. In this way, multiple interrupts are processed. Figure 7.9.1 shows the processing for multiple interrupts. An interrupt request which has not been accepted because its priority level is lower is retained. When the RTI instruction is executed, the interrupt priority level of the routine which was in progress just before acceptance of an interrupt request is pulled into the IPL. Therefore, if the following relationship is satisfied when interrupt priority level detection is performed next, the retained interrupt request will be accepted. Retained interrupt request's priority level > Processor interrupt priority level (IPL) Note: When any of the following interrupt request is generated while an interrupt routine is in progress, this interrupt request is accepted at once: zero division, watchdog timer, NMI, and address matching detection. 7902 Group User's Manual 7-17 INTERRUPTS 7.9 Multiple interrupts Interrupt request generated Time Reset Nesting Main routine I=1 IPL = 0 Interrupt 1 I=0 Interrupt priority level = 3 Interrupt 1 I=1 IPL = 3 Multiple interrupts Interrupt 2 I=0 Interrupt priority level = 5 Interrupt 2 I=1 IPL = 5 Interrupt 3 RTI Interrupt priority level = 2 I=0 IPL = 3 Interrupt 3 RTI This request cannot be accepted because its priority level is lower than the interrupt 1's one. I=0 IPL = 0 The instruction in the main routine is not executed. Interrupt 3 I=1 IPL = 2 RTI I=0 I : Interrupt disable flag IPL = 0 IPL : Processor interrupt priority level : They are automatically executed. : They must be set by software. Fig. 7.9.1 Processing for multiple interrupts 7-18 7902 Group User's Manual INTERRUPTS 7.10 External interrupts 7.10 External interrupts The external interrupts consist of NMI interrupts and INT i interrupts. 7.10.1 NMI interrupt An NMI interrupt request occurs at the falling edge of an input signal to pin NMI. Regardless of flag I, the NMI interrupt request is always accepted when this interrupt occurs, because the NMI interrupt is a nonmaskable interrupt. When the NMI interrupt request occurs again while the NMI interrupt processing is in progress, this new NMI interrupt request is accepted, too (multiple interrupts). There is the possibility of the many times NMI interrupt request occurrence when the noise or the chattering is input to pin NMI. In this case, take care not to destroy the necessary data by the increment of the multiple interrupt nesting and the stack area. By reading out the NMI read bit (See Figure 7.10.3.), the state of pin NMI can be read out. Also, while the level at pin RESET = "L" or after reset, pin NMI is pulled up. Therefore, it is not necessary to connect a pullup resistor externally. When the pin NMI pullup select bit is set to "1" (See Figure 7.10.1.), the pullup state is removed. The signal input to pin NMI requires the "L" level width of 250 ns or more, independent of f(X IN ). 7.10.2 INTi interrupt An INTi (i = 0 to 4) interrupt request occurs by an input signal to pin INTi (i = 0 to 4) pin. Table 7.10.1 lists the occurrence factor of the INT i interrupt request. The each allocation of pins INT2 to INT4 can be changed by the pin INT k (k = 2 to 4) select bit. (See Figure 7.10.2.) When using pins P6 0/INT0 to P63/INT 1, P6 4(P77)/INT 2, P80(P7 4)/INT 3, and P8 4(P7 5)/INT 4 as input pins of external interrupts, clear the port direction registers' bits corresponding to the above pins. (See Figure 7.10.4.) The signal input to pin INT i requires "H" or "L" level width of 250 ns or more, independent of f(XIN) (Note). By reading out the INTi read bit (See Figure 7.10.3.), the state of pin INT i can be read out. Note: Selection of the interrupt occurrence factor requires the following conditions: * when an input signal's falling edge or "L" level is selected, be sure that "L" level width 250 ns. * when an input signal's rising edge or "H" level is selected, be sure that "H" level width 250 ns. Table 7.10.1 Occurrence factor of INTi interrupt request 7D16 to 7F 16) 6F16, 7D 16 to 7F 16 ) 0 0 1 0 1 Occurrence factor of interrupt request (An interrupt request occurs when the input signal of pin INTi is as follows.) Falling edge (Edge sense) Rising edge (Edge sense) 0 1 0 1 "H" level (Level sense) "L" level (Level sense) Falling edge (Edge sense) Rising edge (Edge sense) Polarity select bit Level sense/Edge sense select bit (bit 5 at addresses (bit 4 at addresses 6E 16, INT 0 to INT2 1 INT3, INT4 The INT i interrupt request occurs by detecting the state of pin INT i all the time. Therefore, when the user does not use an INT i interrupt, be sure to set the INTi interrupt's priority level to 0. 7902 Group User's Manual 7-19 INTERRUPTS 7.10 External interrupts b7 b6 b5 b4 b3 b2 b1 b0 Port function control register (Address 9216) Bit 0 Bit name Address/Port switch bits 1 2 3 Port P0 input level select bit 4 Pins P44-P47 pullup select bit 6, 5 7 0 0 Function At reset R/W 0 0 0 : A0 to A23 (16 Mbytes) 0 0 1 : A0 to A21, P06, P07 (4 Mbytes) 0 1 0 : A0 to A19, P04 to P07 (1 Mbytes) 0 1 1 : A0 to A17, P02 to P07 (256 Kbytes) 1 0 0 : A0 to A15, P0 0 to P07 (64 Kbytes) 1 0 1 : Do not select. 1 1 0 : A0 to A11, P00 to P07, P114 to P117 (4 Kbytes) 1 1 1 : A0 to A7, P00 to P07, P110 to P117 (256 bytes) 0 : VIH = 0.7 Vcc, V IL = 0.2 Vcc 1 : VIH = 0.43 Vcc (Note 1), VIL = 0.16 Vcc 0 RW 0 RW 0 RW 0 RW 0 : Pins P44-P47 are pulled up. 1 : Pins P44-P47 are not pulled up (Notes 2, 3). 0 RW 0 RW 0 RW b2 b1 b0 Fix these bits to "0." Pin NMI pullup select bit 0 : Pin NMI is pulled up. 1 : Pin NMI is not pulled up (Note 2). Notes 1: For the M37902FxM (power source voltage = 3.3 V0.3 V), VIH = 0.5Vcc. 2: When MD1 = Vcc and MD0 = Vcc (flash memory parallel I/O mode), pins P44 to P47 and NMI are not pulled up, regardless of these bits' contents. 3: When MD1 = Vss and MD0 = Vcc (microprocessor mode), pin CS0 (P44 ) is not pulled up regardless of this bit's contents. Fig. 7.10.1 Structure of port function control register b7 b6 b5 b4 b3 b2 b1 b0 External interrupt input control register (Address 9416) Bit 0 Function Bit name At reset R/W 0 Key input interrupt select bit 0 : INT3 interrupt 1 : Key input interrupt 0 RW 1 Key input interrupt pin pullup select bit Key input interrupt pin select bits 0 : Pins KI0 to KI3 are not pulled up. 1 : Pins KI0 to KI3 are pulled up. 0 RW b3 b2 0 RW 0 RW 0 RW 2 3 0 0 : Pins KI0 to KI3 0 1 : Pins KI0 to KI2 1 0 : Pins KI0 and KI1 1 1 : Pin KI0 (Note 1) 0 : Allocate pin INT2 to P64. 1 : Allocate pin INT2 to P77. 4 Pin INT2 select bit 5 Pin INT3 select bit 0 : Allocate pin INT3 to P80. 1 : Allocate pin INT3 to P74. (Note 3) 0 RW 6 Pin INT4 select bit 0 : Allocate pin INT4 to P84. 1 : Allocate pin INT4 to P75. (Note 4) 0 RW 7 Fix this bit to "0." 0 RW (Note 2) Notes 1: When using pin KIi, do not select timer A's output pins and pulse output pins which are multiplexed with pin KIi. Refer to "CHAPTER 9. TIMER A" and "CHAPTER 11. REAL-TIME OUTPUT." 2: When allocating pin INT2 to P7 7, do not use pin AN7/ADTRG. Additionally, clear the D-A1 output enable bit (bit 1 at address 9616 ) to "0" (output disabled). 3: When allocating pin INT3 to P8 0, clear the D-A2 output enable bit (bit 2 at address 96 16) to "0" (output disabled). When allocating pin INT3 to P74, do not use pin AN 4. 4: When allocating pin INT4 to P75, do not use pin AN5 . Fig. 7.10.2 Structure of external interrupt input control register 7-20 7902 Group User's Manual INTERRUPTS 7.10 External interrupts b7 b6 b5 b4 b3 b2 b1 b0 External interrupt input read register (Address 9516) Bit Bit name Function R/W Undefined RO Undefined RO Undefined RO 0 INT0 read out bit 1 INT1 read out bit 2 INT2 read out bit 3 INT3 read out bit (Note) Undefined RO 4 INT4 read out bit Undefined RO 5 NMI read out bit Undefined RO The value is undefined at reading. Undefined RO 7, 6 The input level at the corresponding pin is read out. 0 : "L" level 1 : "H" level At reset Note : When the key input interrupt select bit (bit 0 at address 9416) = "1," the input level at pin INT3 cannot be read out. Fig. 7.10.3 Structure of external interrupt input read register 7902 Group User's Manual 7-21 INTERRUPTS 7.10 External interrupts b7 b6 b5 b4 b3 b2 b1 b0 Port P6 direction register (Address 1016 ) Bit Function Corresponding pin 0 : Input mode 1 : Output mode At reset R/W 0 RW 0 RW 0 RW 0 RW 0 RW 0 Pin TA4OUT 1 Pin TA4IN 2 Pin INT0 3 Pin INT1 4 Pin INT2 (Note) 5 Pin TB0IN 0 RW 6 Pin TB1IN 0 RW 7 Pin TB2IN 0 RW When using this pin as an external interrupt's input pin, be sure to clear the corresponding bit to "0." Note: This applies when the pin INT2 select bit (bit 4 at address 9416) = "0." b7 b6 b5 b4 b3 b2 b1 b0 Port P7 direction register (Address 1116 ) Bit Corresponding pin Function 0 : Input mode 1 : Output mode At reset R/W 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Pin AN0 1 Pin AN1 2 Pin AN2 3 Pin AN3 4 Pin INT3 (Pin AN4) (Note 1) 5 Pin INT4 (Pin AN5) (Note 1) 6 Pin AN6/DA0 0 RW 7 Pin INT2 (Pin AN7/ADTRG/DA1) (Note 1) 0 RW When using this pin as an external interrupt's input pin, be sure to clear the corresponding bit to "0." Notes 1: This applies when the pin INTk (k = 2 to 4) select bit (bits 4 to 6 at address 94 16) = "1." 2: ( ) shows the I/O pin of the other internal peripheral devices which are multiplexed. b7 b6 b5 b4 b3 b2 b1 b0 Port P8 direction register (Address 1416) Bit At reset R/W 0 RW 0 RW 0 RW 3 Pin INT3 (Pin CTS0/RTS0/DA2) (Note 1) 0 : Input mode 1 : Output mode Pin CTS0/CLK0 When using this pin as an external interrupt's Pin RxD0 input pin, be sure to clear the corresponding bit Pin TxD0 to "0." 0 RW 4 Pin INT3 (Pin CTS1/RTS1) (Note 1) 0 RW 5 Pin CTS1/CLK1 0 RW 6 Pin RxD1 0 RW 7 Pin TxD1 0 RW 0 1 2 Corresponding pin Function Notes 1: This applies when the pins INT3 and INT4 select bit (bits 5, 6 at address 9416) = "0." 2: ( ) shows the I/O pin of the other internal peripheral devices which are multiplexed. Fig. 7.10.4 Relationship between port P6/P7P8 direction register and external interrupt's input pins 7-22 7902 Group User's Manual INTERRUPTS 7.10 External interrupts 7.10.3 Functions of INT i interrupt request bit Figure 7.10.5 shows an INT i interrupt request. (1) Functions when edge sense is selected (INT0 to INT4) In this case, the interrupt request bit has the same function as that of an internal interrupt. That is, when an interrupt request occurs, the interrupt request bit is set to "1" and retains this state until the interrupt request is accepted. When this bit is cleared to "0" by software, the interrupt request is cancelled; when this bit is set to "1" by software, the interrupt request can occur. (2) Functions when level sense is selected (INT 0 to INT 2) In this case, the interrupt request bit is ignored. INT k (k = 0 to 2) interrupt requests continuously occur while the level at pin INTk is the valid level1; when the level at pin INT k changes from the valid level to the invalid level2 before the corresponding INTk interrupt request is accepted, this interrupt request is not retained. (See Figure 7.10.6.) Valid level 1: This means the level selected by the polarity select bit (bit 4 at addresses 7D 16 to 7F 16) Invalid level 2: This means the reversed level of "valid level" Data bus Pins INT3 and INT4 Edge detection circuit Pins INT0 to INT2 Edge detection circuit Interrupt request bit Interrupt request Interrupt request bit "0" Interrupt request "1" Fig. 7.10.5 INT i Interrupt request Interrupt request is accepted. When the level at pin INTk changes to the invalid level before the INTk interrupt request is accepted, this interrupt request is not retained. Return to main routine. Valid Level at pin INTk (k = 0 to 2) Invalid Main routine Main routine First interrupt routine Second interrupt routine Third interrupt routine Fig. 7.10.6 Occurrence of INT k interrupt request when level sense is selected (k = 0 to 2) 7902 Group User's Manual 7-23 INTERRUPTS 7.10 External interrupts 7.10.4 Switching of INT k to (k = 0 to 2) interrupt request occurrence factor When the INT k interrupt request occurrence factor is switched in one of the following ways, there is a possibility that the corresponding interrupt request bit is set to "1": * Switching the factor from the level sense to the edge sense * Switching the polarity Therefore, after this switching, make sure to clear the corresponding interrupt request bit to "0." Figure 7.10.7 shows an example of the switching procedure for the INTk interrupt request's occurrence factor. (1) Switching the factor from the level sense to the edge sense Set the interrupt priority level to 0 or set the interrupt disable flag (I) to "1." (INT0 to INT2 interrupts are disabled.) (2) Switching the polarity Set the interrupt priority level to 0 or set the interrupt disable flag (I) to "1." (INT0 to INT2 interrupts are disabled.) Set the polarity select bit. Clear the level sense/Edge sense select bit to "0." (Edge sense is selected.) Clear the interrupt request bit to "0." Clear the interrupt request bit to "0." Set the interrupt priority level to one of levels 1-7 or clear the interrupt disable flag (I) to "0." (INT0 to INT2 interrupt requests are acceptable.) Set the interrupt priority level to one of levels 1-7 or clear the interrupt disable flag (I) to "0." (INT0 to INT2 interrupt requests are acceptable.) Note: The above settings must be done separately. Multiple settings must not be done at the same time, in other words, they must not be done only by 1 instruction. Fig. 7.10.7 Example of switching procedure for INT k (k = 0 to 2) interrupt request occurrence factor 7-24 7902 Group User's Manual INTERRUPTS [Precautions for interrupts] [Precautions for interrupts] 1. In order to change the interrupt priority level select bits (bits 0 to 2 at addresses 6E 16 to 7F 16), 2 to 7 cycles of fsys are required after execution of a write instruction until change of the interrupt priority level. Therefore, when the interrupt priority level of a certain interrupt source is repeatedly changed in a very short time, which consists of a few instructions, it is necessary to reserve the time required for the change by software. Figure 7.10.8 shows a program example to reserve the time required for the change. Note that the time required for the change depends on the contents of the interrupt priority detection time select bits (bits 4 and 5 at address 5E 16). Table 7.10.2 lists the correspondence between the number of instructions inserted in Figure 7.10.8 and the interrupt priority detection time select bits. : MOVMB 00XXH, #0XH NOP NOP NOP MOVMB 00XXH, #0XH : ; Write instruction for the interrupt priority level select bits ; Inserted NOP instruction (Note) ; ; ; Write instruction for the interrupt priority level select bits Note: Except a write instruction for address XX16, any instruction which has the same cycles as the NOP instruction can also be inserted, instead of the NOP instruction. For the number of inserted NOP instructions, see Table 7.10.2. XX: any of 6C to 7F Fig. 7.10.8 Program example to reserve time required for change of interrupt priority level Table 7.10.2 Correspondence between number of instructions to be inserted in Figure 7.10.8 and interrupt priority detection time select bits Interrupt priority level Interrupt priority detection time select bits (Note) b5 b4 detection time 0 0 7 cycles of f sys 1 0 4 cycles of f sys 1 0 2 cycles of f sys 1 1 Do not select. Note: We recommend [b5 = "1", b4 = "0"]. Number of inserted NOP instructions 7 or more 4 or more 2 or more 2. When allocating pin INT 2 to pin P77, be sure not use pin AN 7/AD TRG. Additionally, be sure that the D-A 1 output enabled bit (bit 1 at address 9616 ) = 0 (output disabled). When allocating pin INT 3 to pin P80, be sure that the D-A 2 output enabled bit (bit 2 at address 96 16) = 0 (output disabled). When allocating pin INT 3 to pin P7 4, be sure not to use pin AN 4. When allocating pin INT4 to pin P7 5, be sure not use pin AN 5. 7902 Group User's Manual 7-25 INTERRUPTS [Precautions for interrupts] MEMORANDUM 7-26 7902 Group User's Manual CHAPTER 8 KEY INPUT INTERRUPT 8.1 Overview 8.2 Block description 8.3 Initial setting example for related registers KEY INPUT INTERRUPT 8.1 Overview The key input interrupt function is used to generate an interrupt request at the falling edge of the signal which is input to one pin, selected from four pins. When terminating the stop or wait mode by using this function, the key-on wakeup function can be realized. For details, refer to "CHAPTER 16. STOP AND WAIT MODES." 8.1 Overview The key input interrupt request is generated at the falling edge of the signal input to one pin selected from the following: KI 0 to KI 3. By composing an external key matrix as shown in Figure 8.1.1, an interrupt request can occur simply by pressing the key. Any of the KI0 to KI 3 pins can be programmed as a key input interrupt pin. Also, each pin programmed as a key input pin can be pulled up by software. The Interrupt vector addresses and interrupt control register are common to the key input interrupt and the INT3 interrupt. When the key input interrupt is selected, the INT 3 interrupt cannot be used. M37902 Key matrix KI3 KI2 KI1 KI0 P67 P66 P65 P64 Fig. 8.1.1 Key matrix example using key input interrupt function 8-2 7902 Group User's Manual KEY INPUT INTERRUPT 8.2 Block description 8.2 Block description Figure 8.2.1 shows the block diagram of the key input interrupt function. P80/INT3 Pin INT3 select bit Key input interrupt select bit 0 0 Interrupt control circuit P74/(INT3) INT3 interrupt request 1 1 Port P57 direction register Pullup transistor Key input interrupt pin pullup select bit KI3 enable signal (Note) INT3 interrupt control register P57/KI3 Port P56 direction register Pullup transistor Key input interrupt pin pullup select bit KI2 enable signal (Note) P56/KI2 Port P55 direction register Pullup transistor Key input interrupt pin pullup select bit KI1 enable signal (Note) Note: KIi enable signal (i = 0 to 3) means a signal which becomes "1" when the key input interrupt select bit = "1" and pin KIi is selected by the key input interrupt pin select bits. P55/KI1 Port P54 direction register Pullup transistor Key input interrupt pin pullup select bit KI0 enable signal (Note) * Port P5j direction register : bit j (j = 4 to 7) at address D16 * INT3 interrupt control register : address 6E16 * Key input interrupt select bit : bit 0 at address 9416 * Key input interrupt pin pullup select bit : bit 1 at address 9416 * Pin INT3 select bit : bit 5 at address 9416 P54/KI0 Fig. 8.2.1 Block diagram of key input interrupt function 7902 Group User's Manual 8-3 KEY INPUT INTERRUPT 8.2 Block description 8.2.1 External interrupt input control register Figure 8.2.2 shows the structure of the external interrupt input control register. b7 b6 b5 b4 b3 b2 b1 b0 External interrupt input control register (Address 9416) Bit Bit name 0 Function At reset R/W 0 Key input interrupt select bit 0 : INT3 interrupt 1 : Key input interrupt 0 RW 1 Key input interrupt pin pullup select bit Key input interrupt pin select bits 0 : Pins KI0 to KI3 are not pulled up. 1 : Pins KI0 to KI3 are pulled up. 0 RW b3 b2 0 RW 0 RW 0 RW 2 3 0 0 : Pins KI0 to KI3 0 1 : Pins KI0 to KI2 1 0 : Pins KI0 and KI1 1 1 : Pin KI0 (Note 1) 0 : Allocate pin INT2 to P64. 1 : Allocate pin INT2 to P77. 4 Pin INT2 select bit 5 Pin INT3 select bit 0 : Allocate pin INT3 to P80. 1 : Allocate pin INT3 to P74. (Note 3) 0 RW 6 Pin INT4 select bit 0 : Allocate pin INT4 to P84. 1 : Allocate pin INT4 to P75. (Note 4) 0 RW 7 Fix this bit to "0." 0 RW (Note 2) Notes 1: When using pin KIi, do not select timer A's output pins and pulse output pins which are multiplexed with pin KIi. Refer to "CHAPTER 9. TIMER A" and "CHAPTER 11. REAL-TIME OUTPUT." 2: When allocating pin INT2 to P77, do not use pin AN7 /ADTRG. Additionally, clear the D-A1 output enable bit (bit 1 at address 9616 ) to "0" (output disabled). 3: When allocating pin INT3 to P8 0, clear the D-A2 output enable bit (bit 2 at address 9616) to "0" (output disabled). When allocating pin INT3 to P74 , do not use pin AN4. 4: When allocating pin INT4 to P75, do not use pin AN 5. Fig. 8.2.2 Structure of external interrupt input control register (1) Key input interrupt select bit (bit 0) The interrupt vector addresses and interrupt control register are common to the key input interrupt and the INT 3 interrupt. When setting this bit to "1," the key input interrupt is selected. When the key input interrupt is selected, the INT3 interrupt cannot be used. (2) Key input interrupt pin pullup select bit (bit 1) When setting this bit to "1," the KI i pin programmed as a key input interrupt pin is pulled up. When composing a key matrix, it is unnecessary to connect the KIi pin with an external pullup transistor. Also, when the KI i pin serves as a programmable I/O port pin, this pin is not pulled up regardless of this bit's contents. (3) Key input interrupt pin select bit (bit 2, 3) These bits are used to select pins to be used as key input interrupt pins. (These pins are selected from the KI0 to KI3 pins.) Some pins not to be used as key input interrupt pins can serve as programmable I/O port pins. The signal input to the KIi pin requires the low-level pulse width of 250 ns or more, regardless of f(XIN). 8-4 7902 Group User's Manual KEY INPUT INTERRUPT 8.2 Block description 8.2.2 INT 3 interrupt control register The interrupt vector addresses and interrupt control register are common to the key input interrupt and the INT 3 interrupt, so set as follows: * Interrupt vector addresses: addresses FFD216 and FFD316 (INT 3 interrupt's vector addresses) * Interrupt control register: address 6E 16 (INT3 interrupt control register) When the key input interrupt is selected, the INT3 interrupt cannot be used. When a key input interrupt request is accepted, the microcomputer operates in the same way as when an INT 3 interrupt request is accepted. (Refer to "CHAPTER 7. INTERRUPTS.") Figure 8.2.3 shows the structure of the INT3 interrupt control register when selecting the key input interrupt function. For details of each bit, refer to "CHAPTER 7. INTERRUPTS." b7 b6 b5 b4 b3 b2 b1 b0 INT 3 interrupt control register (Address 6E 16) Bit Bit name 0 Interrupt priority level select bits 1 2 3 Interrupt request bit 4 Polarity select bit 7 to 5 0 Function b2 b1 b0 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0 : No interrupt requested 1 : Interrupt requested 0 : The interrupt request bit is set to "1" at the falling edge. Nothing is assigned. At reset R/W 0 RW 0 RW 0 RW 0 RW (Note) 0 RW Undefined -- Note: When writing to this bit, use the MOVM (MOVMB) or STA (STAB, STAD) instruction. Fig. 8.2.3 Structure of INT 3 interrupt control register when selecting key input interrupt function 7902 Group User's Manual 8-5 KEY INPUT INTERRUPT 8.2 Block description 8.2.3 Port P5 direction register The key input interrupt pins are multiplexed with port P5 pins. When using these pins as key input interrupt pins, clear the corresponding bits of the port P5 direction register to "0" in order to set these port pins for the input mode. Figure 8.2.4 shows the relationship between the port P5 direction register and the key input interrupt pins. By reading out bits 4 to 7 of the port P5 register (address B16 ) when the key input interrupt is selected, the corresponding KIi pin's state can be read out. b7 b6 b5 b4 b3 b2 b1 b0 Port P5 direction register (Address D16) Bit Functions Corresponding pin 0 Pin TA0OUT/RTP00 1 Pin TA0IN/RTP01 2 Pin TA1OUT/RTP02 0 : Input mode 1 : Output mode When using this pin as key input interrupt pin, be sure to clear the corresponding bit to "0." At reset R/W 0 RW 0 RW 0 RW 0 RW 3 Pin TA1IN/RTP03 4 Pin KI0 (Pin TA2OUT/RTP10) 0 RW 5 Pin KI1 (Pin TA2IN/RTP11) 0 RW 6 Pin KI2 (Pin TA3OUT/RTP12) 0 RW 7 Pin KI3 (Pin TA3IN/RTP13) 0 RW Note: ( ) shows the I/O pin of another internal peripheral device which is multiplexed. Fig. 8.2.4 Relationship between port P5 direction register and key input interrupt pins 8-6 7902 Group User's Manual KEY INPUT INTERRUPT 8.3 Initial setting example for related registers 8.3 Initial setting example for related registers Figure 8.3.1 shows an initial setting example for related registers of the key input interrupt function. AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA Setting of key input interrupt b7 b0 0 1 External interrupt input control register (Address 9416) Selection of key input Key input interrupt pin pullup select bit 0 : Pins KI0 to KI3 are not pulled up. 1 : Pins KI0 to KI3 are pulled up (Note). Key input interrupt pin select bits b3 b2 0 0 : Pins KI0 to KI3 0 1 : Pins KI0 to KI2 1 0 : Pins KI0 and KI1 1 1 : Pin KI0 Note: When the polarity select bit (bit 4 at address 6E16) = "1," be sure to set this bit to "1." Setting of port P5 direction register b7 b0 Port P5 direction register (Address D16) Pin KI0 Pin KI1 Pin KI2 Pin KI3 When using this pin as key input interrupt pin, be sure to clear the corresponding bit to "0." Setting of interrupt priority level b7 b0 0 0 INT3 interrupt control register (Address 6E16) Interrupt priority level select bits Set the level to one of 1 through 7 when using this interrupt. Interrupt request bit Polaruty select bit 0 : The interrupt request bit is set to "1" at falling edge. Fig. 8.3.1 Initial setting example for related registers of key input interrupt function 7902 Group User's Manual 8-7 KEY INPUT INTERRUPT 8.3 Initial setting example for related registers MEMORANDUM 8-8 7902 Group User's Manual CHAPTER 9 TIMER A 9.1 Overview 9.2 Block description 9.3 Timer mode [Precautions for timer mode] 9.4 Event counter mode [Precautions for event counter mode] 9.5 One-shot pulse mode [Precautions for one-shot pulse mode] 9.6 Pulse width modulation (PWM) mode [Precautions for pulse width modulation (PWM) mode] TIMER A 9.1 Overview 9.1 Overview Timer to A4 Timer to A4 A consists of five counters, Timers A0 to A4, each equipped with a 16-bit reload function. Timers A0 operate independently of one other. Ai (i = 0 to 4) has four operating modes listed below. Except for the event counter mode, Timers A0 all have the same functions. (1) Timer mode In this mode, the timer counts an internally generated count source. Following functions can be used in this mode: * Gate function * Pulse output function (2) Event counter mode In this mode, the timer counts an external signal. Following functions can be used in this mode: * Pulse output function * Two-phase pulse signal processing function (Timers A2, A3, and A4) (3) One-shot pulse mode In this mode, the timer outputs a pulse which has an arbitrary width once. (4) Pulse width modulation (PWM) mode In this mode, the timer outputs pulses which have an arbitrary width in succession. In this mode, the timer serves as one of the following pulse width modulators: * 16-bit pulse width modulator * 8-bit pulse width modulator 9-2 7902 Group User's Manual TIMER A 9.2 Block description 9.2 Block description Figure 9.2.1 shows the block diagram of timer A. Explanation of registers relevant to timer A is described below. Timer A clock division select bits f2 f1 Count source select bit Data bus (odd) f16 f64 Data bus (even) f512 (Low-order 8 bits) (High-order 8 bits) f4096 Timer mode One-shot pulse mode PWM mode Timer Ai reload register (16) Timer mode (Gate function) TAiIN Polarity switching Timer Ai counter (16) Event counter mode Count start bit Trigger Timer Ai interrupt request bit Countup/Countdown switching (Always "countdown" except for in the event counter mode) Countdown Up-down bit Pulse output function select bit TAiOUT Toggle F.F. i = 0 to 4 Fig. 9.2.1 Block diagram of timer A 7902 Group User's Manual 9-3 TIMER A 9.2 Block description 9.2.1 Counter and Reload register (timer Ai register) Each of timer Ai counter and reload register consists of 16 bits. Countdown in the counter is performed each time the count source is input. In the event counter mode, it can also function as an up-counter. The reload register is used to store the initial value of the counter. When a counter underflow or overflow occurs, the reload register's contents are reloaded into the counter. A value is set to the counter and reload register by writing the value to the timer Ai register. Table 9.2.1 lists the memory assignment of the timer Ai register. The value written into the timer Ai register while counting is not in progress is set to the counter and reload register. The value written into the timer Ai register while counting is in progress is set only to the reload register. In this case, the reload register's updated contents are transferred to the counter at the next reload time. The value obtained when reading out the timer Ai register varies according to the operating mode. Table 9.2.2 lists reading from and writing to the timer Ai register. Table 9.2.1 Memory assignment of timer Ai register Timer Ai register High-order byte Low-order byte Timer A0 register Address 4716 Address 4616 Timer A1 register Address 4916 Address 4816 Timer A2 register Address 4B 16 Address 4A 16 Timer A3 register Address 4D 16 Address 4C 16 Timer A4 register Address 4F 16 Address 4E 16 Note: At reset, the contents of the timer Ai register are undefined. Table 9.2.2 Reading from and writing to timer Ai register Operating mode Timer mode Event counter mode One-shot pulse mode Pulse width modulation (PWM) mode Read Counter value is read out. (Note 1) Undefined value is read out. Write <While counting> Written only to reload register. <While not counting> Written to both of the counter and reload register. Notes 1: Also refer to sections "[Precautions for timer mode]" and "[Precautions for event counter mode]." 2: When reading from and writing to the timer Ai register, perform it in a unit of 16 bits. 9-4 7902 Group User's Manual TIMER A 9.2 Block description 9.2.2 Timer A clock division select register In the timer mode, one-shot pulse mode, and pulse width modulation (PWM) mode, the count source select bits (bits 6 and 7 at addresses 56 16 to 5A 16), and timer A clock division select bits (bits 0 and 1 at addresses 45 16) select the count source. Figure 9.2.2 shows the structures of the timer A clock division select register. Table 9.2.3 lists the count source (in the timer mode, one-shot pulse mode, and pulse width modulation (PWM) mode). b7 b6 b5 b4 b3 b2 b1 b0 Timer A clock division select register (Address 4516) Bit 0 Bit name Function Timer A clock division select bits See Table 9.2.3. 1 7 to 2 The value is "0" at reading. At reset R/W 0 RW 0 RW 0 - Fig. 9.2.2 Structures of timer A clock division select register Table 9.2.3 Count source (in timer mode, one-shot pulse mode, and pulse width modulation (PWM) mode) Count source select bits (bits 6 and 7 at addresses 5616 to 5A16) 00 01 10 11 7902 Group User's Manual Timer A clock division select bits (bits 0 and 1 at address 45 16) 00 01 10 11 f2 f1 f1 f16 f 16 f 64 Do not f64 f 64 f512 select. f 512 f4096 f4096 9-5 TIMER A 9.2 Block description 9.2.3 Count start register This register is used to start and stop counting. One bit of this registar corresponds to one timer. (This is the one-to-one relationship.) Figure 9.2.3 shows the structure of the count start register. b7 b6 b5 b4 b3 b2 b1 b0 Count start register (Address 4016 ) Bit Bit name Function 0 : Stop counting 1 : Start counting At reset R/W 0 RW 0 RW 0 Timer A0 count start bit 1 Timer A1 count start bit 2 Timer A2 count start bit 0 RW 3 Timer A3 count start bit 0 RW 4 Timer A4 count start bit 0 RW 5 Timer B0 count start bit 0 RW 6 Timer B1 count start bit 0 RW 7 Timer B2 count start bit 0 RW Fig. 9.2.3 Structure of count start register 9.2.4 Timer Ai mode register Figure 9.2.4 shows the structure of the timer Ai mode register. The operating mode select bits are used to select the operating mode of timer Ai. Bits 2 to 7 have different functions according to the operating mode. These bits are described in the paragraph of each operating mode. b7 b6 b5 b4 b3 b2 b1 b0 Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A 16) Bit At reset R/W 0 RW 0 RW 0 RW 3 0 RW 4 0 RW 5 0 RW 6 0 RW 7 0 RW 0 1 2 Bit name Operating mode select bits Function b1 b0 0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot pulse mode 1 1 : Pulse width modulation (PWM) mode. These bits have different functions according to the operating mode. Fig. 9.2.4 Structure of timer Ai mode register 9-6 7902 Group User's Manual TIMER A 9.2 Block description 9.2.5 Timer Ai interrupt control register Figure 9.2.5 shows the structure of the timer Ai interrupt control register. For details about interrupts, refer to "CHAPTER 7. INTERRUPTS." Timer Ai interrupt control register (i = 0 to 4) (Addresses 7516 to 7916) Bit 0 Bit name Interrupt priority level select bits 1 2 3 Interrupt request bit 7 to 4 Nothing is assigned. b7 b6 b5 b4 b3 b2 b1 b0 Function At reset R/W 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0 RW 0 RW 0 RW 0 : No interrupt requested 1 : Interrupt requested 0 RW (Note) Undefined -- b2 b1b0 Note: When writing to this bit, use the MOVM (MOVMB) instruction or STA (STAB, STAD) instruction. Fig. 9.2.5 Structure of timer Ai interrupt control register (1) Interrupt priority level select bits (bits 2 to 0) These bits are used to select a timer Ai interrupt's priority level. When using timer Ai interrupts, select the priority level from levels 1 through 7. When a timer Ai interrupt request occurs, its priority level is compared with the processor interrupt priority level (IPL), so that the requested interrupt is enabled only when its priority level is higher than the IPL. (However, this applies when the interrupt disable flag (I) = "0.") To disable timer Ai interrupts, set these bits to "000 2" (level 0). (2) Interrupt request bit (bit 3) This bit is set to "1" when a timer Ai interrupt request occurs. This bit is automatically cleared to "0" when the timer Ai interrupt request is accepted. This bit can be set to "1" or cleared to "0" by software. 7902 Group User's Manual 9-7 TIMER A 9.2 Block description 9.2.6 Port P5 and port P6 direction registers The I/O pins of timers A0 and A3 are multiplexed with port P5 pins, and the I/O pins of timer A4 are multiplexed with port P6 pins. When using these pins as timer Ai's input pins, clear the corresponding bits of the port P5 and port P6 direction registers to "0" in order to set these port pins for the input mode. When used as timer Ai's output pins, these pins are forcibly set to the output pins of timer Ai regardless of the direction registers's contents. Figure 9.2.6 shows the relationship between the port P5 and port P6 direction registers and the timer Ai's I/O pins. b7 b6 b5 b4 b3 b2 b1 b0 Port P5 direction register (Address D16) Bit Functions Corresponding pin 0 Pin TA0OUT (Pin RTP00) 1 Pin TA0IN (Pin RTP01) 2 Pin TA1OUT (Pin RTP02) 0 : Input mode 1 : Output mode When using this pin as timer Ai's input pin, be sure to clear the corresponding bit to "0." At reset R/W 0 RW 0 RW 0 RW 0 RW 3 Pin TA1IN (Pin RTP03) 4 Pin TA2OUT (Pin RTP10/KI0) 0 RW 5 Pin TA2IN (Pin RTP11/KI1) 0 RW 6 Pin TA3OUT (Pin RTP12/KI2) 0 RW 7 Pin TA3IN (Pin RTP13/KI3) 0 RW Note: ( ) shows the I/O pin of another internal peripheral device which is multiplexed. b7 b6 b5 b4 b3 b2 b1 b0 Port P6 direction register (Address 1016) Bit Corresponding pin 0 Pin TA4OUT 1 Pin TA4IN 2 Pin INT0 Functions 0 : Input mode 1 : Output mode When using this pin as timer Ai's input pin, be sure to clear the corresponding bit to "0." At reset R/W 0 RW 0 RW 0 RW 0 RW 3 Pin INT1 4 Pin INT2 (Note) 0 RW 5 Pin TB0IN 0 RW 6 Pin TB1IN 0 RW 7 Pin TB2IN 0 -- Note: This applies when the pin INT2 select bit (bit 4 at address 9416) = "0." Fig. 9.2.6 Relationship between port P5 and port P6 direction registers and timer Ai's I/O pins 9-8 7902 Group User's Manual TIMER A 9.3 Timer mode 9.3 Timer mode In this mode, the timer counts an internally generated count source. Table 9.3.1 lists the specifications of the timer mode. Figure 9.3.1 shows the structures of the timer Ai register and timer Ai mode register in the timer mode. Table 9.3.1 Specifications of timer mode Item Specifications Count source fi Count operation f1, f 2, f16 , f 64 , f 512, or f 4096 * Countdown * When a counter underflow occurs, reload register's contents are reloaded, and counting continues. Division ratio 1 n : Timer Ai register setting value (n + 1) When count start bit is set to "1." When count start bit is cleared to "0." When a counter underflow occurs. Programmable I/O port pin or gate input pin Programmable I/O port pin or pulse output pin Counter value can be read out. While counting is stopped When a value is written to the timer Ai register, it is written to both reload register and counter. While counting is in progress When a value is written to the timer Ai register, it is written to only reload register. (Transferred to the counter at the next reload timing.) Count start condition Count stop condition Interrupt request occurrence timing TAi IN pin function TAi OUT pin function Read from timer Ai register Write to timer Ai register 7902 Group User's Manual 9-9 TIMER A 9.3 Timer mode Timer A0 register (Addresses 4716 , 4616) Timer A1 register (Addresses 4916 , 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16 ) Bit (b15) b7 (b8) b0 b7 b0 Function At reset R/W 15 to 0 These bits to can be set to "000016" to "FFFF16." Undefined Assuming that the set value = n, the counter divides the count source frequency by (n + 1). When reading, the register indicates the counter value. RW Note: Reading from or writing to this register must be performed in a unit of 16 bits. b7 b6 b5 b4 b3 b2 b1 b0 Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A 16) Bit 0 Function Bit name 0 0 At reset R/W 0 RW Operating mode select bits b1 b0 0 RW 2 Pulse output function select bit 0 : No pulse output (TAiOUT pin functions as a programmable I/O port pin.) 1 : Pulse output (TAi OUT pin functions as a pulse output pin.) (Note) 0 RW 3 Gate function select bits b4 b3 0 RW 0 RW 0 RW 0 RW 0 RW 0 0 0 : Timer mode 1 00: 01: 10: 4 11: 5 Fix this bit to "0" in timer mode. 6 Count source select bits No gate function (TAiIN pin functions as a programmable I/O port pin.) Gate function (Counter counts only while TAiIN pin's input signal is at "L" level.) Gate function (Counter counts only while TAiIN pin's input signal is at "H" level.) See Table 9.2.3. 7 Note: In order to make the TA2OUT and TA3 OUT pins serve as pulse output pins, be sure not to select the key input interrupt pins (KI0 and KI2 pins), which are multiplexed with the above pins. (Refer to "CHAPTER 8. KEY INPUT INTERRUPT.") Fig. 9.3.1 Structures of timer Ai register and timer Ai mode register in timer mode 9-10 7902 Group User's Manual TIMER A 9.3 Timer mode 9.3.1 Setting for timer mode Figure 9.3.2 shows an initial setting example for registers related to the timer mode. Note that when using interrupts, set up to enable the interrupts. For details, refer to section "CHAPTER 7. INTERRUPTS." AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAA AAAA AAAA Selecting timer mode and each function b7 b0 0 0 0 Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16) Selection of timer mode Pulse output function select bit 0 : No pulse output 1 : Pulses output Gate function select bits b4 b3 0 0 1 1 0: No Gate function 1: 0 : Gate function (Counter counts only while TAiIN pin's input signal level is "L.") 1 : Gate function (Counter counts only while TAiIN pin's input signal level is "H.") Count source select bits See Table 9.2.3. Setting division ratio (b15) b7 (b8) b0 b7 b0 Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Can be set to "000016" to "FFFF16" (n). Note: Counter divides the count source frequency by (n + 1). Setting interrupt priority level b7 b0 Timer Ai interrupt control register (i = 0 to 4) (Addresses 7516 to 7916) Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. Setting count start bit to "1." Setting port P5 and port P6 direction registers b7 b7 b0 Port P5 direction register (Address D16) Count start register (Address 4016) Timer A0 count start bit Pin TA0IN Pin TA1IN b7 b0 Timer A1 count start bit Pin TA2IN Timer A2 count start bit Pin TA3IN Timer A3 count start bit Timer A4 count start bit b0 Port P6 direction register (Address 1016) Pin TA1IN When gate function is selected, clear the bit corresponding to the TAiIN pin to "0." Count starts. Fig. 9.3.2 Initial setting example for registers relevant to timer mode 7902 Group User's Manual 9-11 TIMER A 9.3 Timer mode 9.3.2 Operation in timer mode When the count start bit is set to "1," the counter starts counting of the count source. When a counter underflow occurs, the reload register's contents are reloaded, and counting continues. The timer Ai interrupt request bit is set to "1" at the underflow in . The interrupt request bit remains set to "1" until the interrupt request is accepted or until the interrupt request bit is cleared to "0" by software. Figure 9.3.3 shows an example of operation in the timer mode. Counter contents (Hex.) FFFF16 Starts counting. (1 / fi) (n+1) Stops counting. n Restarts counting. 000016 Time Set to "1" by software. Cleared to "0" by software. Set to "1" by software. Count start bit Timer Ai interrupt request bit Cleared to "0" when interrupt request is accepted or cleared by software. fi : Frequency of count source n : Reload register's contents Fig. 9.3.3 Example of operation in timer mode (without pulse output and gate functions) 9-12 7902 Group User's Manual TIMER A 9.3 Timer mode 9.3.3 Select function The following describes the gate and pulse output functions. (1) Gate function The gate function is selected by setting the gate function select bits (bits 4 and 3 at addresses 5616 to 5A 16 ) to "102" or "11 2." The gate function makes it possible to start or stop counting depending on the TAiIN pin's input signal. Table 9.3.2 lists the count valid levels. Figure 9.3.4 shows an example of operation with the gate function selected. When selecting the gate function, set the port P5 and port P6 direction registers' bits which correspond to the TAi IN pin for the input mode. Additionally, make sure that the TAiIN pin's input signal has a pulse width equal to or more than two cycles of the count source. Table 9.3.2 Count valid levels Gate function select bits Count valid level (Duration while counter counts) b4 b3 1 0 While TAi IN pin's input signal level is at "L" level 1 1 While TAi IN pin's input signal level is at "H" level Note: The counter does not count while the TAiIN pin's input signal is not at the count valid level. FFFF16 Starts counting. Counter contents (Hex.) n Stops counting. 000016 Set to "1" by software. Time Count start bit Count valid TAiIN pin's level input signal Invalid level Timer Ai interrupt request bit The counter counts while the count start bit = "1" and the TAiIN pin's input signal is at the count valid level. The counter stops counting while the TAiIN pin's input signal is not at the count valid level, and the counter value is retained. Cleared to "0" when interrupt request is accepted or cleared by software. n : Reload register's contents Fig. 9.3.4 Example of operation with gate function selected 7902 Group User's Manual 9-13 TIMER A 9.3 Timer mode (2) Pulse output function The pulse output function is selected by setting the pulse output function select bit (bit 2 at addresses 56 16 to 5A 16 ) to "1." When this function is selected, the TAi OUT pin is forcibly set for the pulse output pin regardless of the corresponding bits of the port P5 and port P6 direction registers. The TAi OUT pin outputs pulse of which polarity is inverted each time a counter underflow occurs. When the count start bit (bits 0 to 4 at address 40 16 ) is "0" (count stopped), the TAiOUT pin outputs "L" level. Figure 9.3.5 shows an example of operation with the pulse output function selected. Note that in order to make the TA2 OUT and TA3OUT pins serve as pulse output pins, be sure not to select the key input interrupt pins (KI 0 and KI 2 pins), which are multiplexed with the above pins. (Refer to "CHAPTER 8. KEY INPUT INTERRUPT.") FFFF16 Counter contents (Hex.) Starts counting. Starts counting. n Restarts counting. 000016 Time Set to "1" by software. Cleared to "0" by software. Set to "1" by software. Count start bit Pulse output from TAiOUT pin Timer Ai interrupt request bit Cleared to "0" when interrupt request is accepted or cleared by software. n : Reload register's contents Fig. 9.3.5 Example of operation with pulse output function selected 9-14 7902 Group User's Manual TIMER A [Precautions for timer mode] [Precautions for timer mode] 1. By reading the timer Ai register, the counter value can be read out at any timing. However, if the timer Ai register is read at the reload timing shown in Figure 9.3.6, the value "FFFF16 " is read out. If reading is performed in the period from when a value is set into the timer Ai register with the counter stopped until the counter starts counting, the set value is correctly read out. Reload Counter value (Hex.) 2 1 0 Read value (Hex.) 2 1 0 n n-1 FFFF n - 1 n : Reload register's contents Time Fig. 9.3.6 Reading timer Ai register 2. In order to make the TA2 OUT and TA3 OUT pins serve as pulse output pins, be sure not to select the key input interrupt pins (KI 0 and KI2 pins), which are multiplexed with the above pins. (Refer to "CHAPTER 8. KEY INPUT INTERRUPT.") 7902 Group User's Manual 9-15 TIMER A 9.4 Event counter mode 9.4 Event counter mode In this mode, the timer counts an external signal. Tables 9.4.1 and 9.4.2 list the specifications of the event counter mode. Figure 9.4.1 shows the structures of the timer Ai register and timer Ai mode register in the event counter mode. Table 9.4.1 Specifications of event counter mode (when not using two-phase pulse signal processing function) Item Count source Count operation Division ratio Specifications External signal input to the TAiIN pin The count source's valid edge can be selected from the falling edge and the rising edge by software. Countup or countdown can be switched by external signal or software. When a counter overflow or underflow occurs, reload register's contents are reloaded, and counting continues. For countdown 1 (n + 1) For countup Count start condition Count stop condition Interrupt request occurrence timing TAi IN pin's function TAi OUT pin's function Read from timer Ai register Write to timer Ai register 9-16 n: Timer Ai register's set value 1 (FFFF16 - n + 1) When the count start bit is set to "1." When the count start bit is cleared to "0." When a counter overflow or underflow occurs. Count source input Programmable I/O port pin, pulse output pin, or countup/countdown switch signal input pin Counter value can be read out. While counting is stopped When a value is written to timer Ai register, it is written to both of the reload register and counter. While counting is in progress When a value is written to timer Ai register, it is written only to the reload register. (Transferred to the counter at the next reload timing.) 7902 Group User's Manual TIMER A 9.4 Event counter mode Table 9.4.2 Specifications of event counter mode (when using two-phase pulse signal processing function in timers A2 and A4) Item Count source Count operation Division ratio Specifications External signal (two-phase pulse) input to the TAj IN or TAjOUT pin (j = 2 to 4) Countup or countdown can be switched by external signal (twophase pulse). When a counter overflow or underflow occurs, reload register's contents are reloaded, and counting continues. For countdown 1 (n + 1) n: Timer Aj register's set value For countup 1 (FFFF 16 - n + 1) Count start condition Count stop condition Interrupt request occurrence timing TAj IN, TAjOUT (j = 2 to 4) pin function Read from timer Aj register Write to timer Aj register When the count start bit is set to "1." When the count start bit is cleared to "0." When a counter overflow or underflow occurs. Two-phase pulse input Counter value can be read out by reading timer Aj register. While counting is stopped When a value is written to timer Aj register, it is written to both of the reload register and counter. While counting is in progress When a value is written to timer Aj register, it is written only to the reload register. (Transferred to the counter at the next reload timing.) 7902 Group User's Manual 9-17 TIMER A 9.4 Event counter mode Timer A0 register (Addresses 4716 , 4616) Timer A1 register (Addresses 4916 , 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Bit (b15) b7 (b8) b0 b7 Function b0 At reset R/W 15 to 0 These bits to can be set to "000016" to "FFFF16." Undefined Assuming that the set value = n, the counter divides the count source frequency by (n + 1) during countdown, or by (FFFF16 - n + 1) during countup. When reading, the register indicates the counter value. RW Note: Reading from or writing to this register must be performed in a unit of 16 bits. b7 b6 b5 b4 b3 b2 b1 b0 Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16) Bit Bit name X X 0 Function 0 1 At reset R/W 0 RW 0 RW 0 RW Operating mode select bits b1 b0 2 Pulse output function select bit 0 : No pulse output (TAi OUT pin functions as a programmable I/O port pin.) 1 : Pulse output (TAiOUT pin functions as a pulse output pin.) (Note) 3 Count polarity select bit 0 : Counts at falling edge of external signal 1 : Counts at rising edge of external signal 0 RW 4 Up-down switching factor select bit 0 : Contents of up-down register 1 : Input signal to TAiOUT pin 0 RW 5 Fix this bit to "0" in event counter mode. 0 RW 6 These bits are invalid in event counter mode. 0 RW 0 RW 0 0 1 : Event counter mode 1 7 X : It may be either "0" or "1." Note: In order to make the TA2OUT and TA3OUT pins serve as pulse output pins, be sure not to select the key input interrupt pins (KI0 and KI2 pins), which are multiplexed with the above pins. (Refer to "CHAPTER 8. KEY INPUT INTERRUPT.") Fig. 9.4.1 Structures of timer Ai register and timer Ai mode register in event counter mode 9-18 7902 Group User's Manual TIMER A 9.4 Event counter mode 9.4.1 Setting for event counter mode Figures 9.4.2 and 9.4.3 show an initial setting example for registers related to the event counter mode. Note that when using interrupts, set up to enable the interrupts. For details, refer to "CHAPTER 7. INTERRUPTS." Selecting event counter mode and each function b7 b0 0 0 1 Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16) Selection of event counter mode Pulse output function select bit 0: No pulse output 1: Pulse output Count polarity select bit 0: Counts at falling edge of external signal. 1: Counts at rising edge of external signal. Up-down switching factor select bit 0: Contents of up-down register 1: Input signal to TAiOUT pin X: It may be either "0" or "1." Setting up-down register b7 b0 Up-down register (Address 4416) Timer A0 up-down bit Timer A1 up-down bit Timer A2 up-down bit Timer A3 up-down bit Timer A4 up-down bit Set to the corresponding up-down bit when the contents of the up-down register are selected as the up-down switching factor. 0: Countdown 1: Countup Timer A2 two-phase pulse signal processing select bit Timer A3 two-phase pulse signal processing select bit Timer A4 two-phase pulse signal processing select bit Set the corresponding bit to "1" when the two-phase pulse signal processing function is selected for timers A2 to A4. 0: Two-phase pulse signal processing function disabled 1: Two-phase pulse signal processing function enabled Setting divide ratio (b15) b7 (b8) b0 b7 b0 Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Can be set to "000016" to "FFFF16" (n). The counter divides the count source frequency by (n + 1) when counting down, or by (FFFF16 - n + 1) when counting up. Continued to Figure 9.4.3 on the next page Fig. 9.4.2 Initial setting example for registers related to event counter mode (1) 7902 Group User's Manual 9-19 TIMER A 9.4 Event counter mode From preceding Figure 9.4.2 Setting interrupt priority level b7 b0 Timer Ai interrupt control register (i = 0 to 4) (Addresses 7516 to 7916) Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. Setting port P5 and port P6 direction registers b7 b0 Port P5 direction register (Address D16) Pin TA0OUT Pin TA0IN Pin TA1OUT Pin TA1IN Pin TA2OUT Pin TA2IN Pin TA3OUT Pin TA3IN b7 b0 Port P6 direction register (Address 1016) Pin TA4OUT Pin TA4IN Clear the bit corresponding to the TAiIN pin to "0." When selecting the TAiOUT pin's input signal as up-down switching factor, clear the bit corresponding to the TAiOUT pin to "0." When selecting the two-phase pulse signal processing function, clear the bit corresponding to the TAjOUT (j = 2 to 4) pin to "0." AAAAAA Setting the count start bit to "1" b7 b0 Count start register (Address 4016) Timer A0 count start bit Timer A1 count start bit Timer A2 count start bit Timer A3 count start bit AAA AAA AAA Timer A4 count start bit Count starts. Fig. 9.4.3 Initial setting example for registers relevant to event counter mode (2) 9-20 7902 Group User's Manual TIMER A 9.4 Event counter mode 9.4.2 Operation in event counter mode When the count start bit is set to "1," the counter starts counting of the count source's valid edge. When a counter underflow or overflow occurs, the reload register's contents are reloaded, and counting continues. The timer Ai interrupt request bit is set to "1" at the underflow or overflow in . The interrupt request bit remains set to "1" until the interrupt request is accepted or until the interrupt request bit is cleared to "0" by software. Figure 9.4.4 shows an example of operation in the event counter mode. FFFF16 Counter contents (Hex.) Starts counting. n 000016 Time Set to "1" by software. Count start bit Set to "1" by software. Up-down bit Timer Ai interrupt request bit Cleared to "0" when interrupt request is accepted or cleared by software. n : Reload register's contents Note: The above applies when the up-down bit's contents are selected as the up-down switching factor (i.e., up-down switching factor select bit = "0" ). Fig. 9.4.4 Example of operation in event counter mode (without pulse output and two-phase pulse signal processing functions) 7902 Group User's Manual 9-21 TIMER A 9.4 Event counter mode 9.4.3 Switching between countup and countdown Figure 9.4.5 shows structure of the up-down register. The up-down register or the input signal from the TAi OUT pin is used to switch countup from and to countdown. This switching is performed by the up-down bit when the up-down switching factor select bit (bit 4 at addresses 5616 to 5A 16 ) is "0," and by the input signal from the TAiOUT pin when the up-down switching factor select bit is "1." When the switching between countup and countdown is set while counting is in progress, this switching is actually performed when the count source's next valid edge is input. (1) Switching by up-down bit Countdown is performed when the up-down bit is "0," and countup is performed when the up-down bit is "1." Figure 9.4.5 shows the structure of the up-down register. (2) Switching by TAi OUT pin's input signal Countdown is performed when the TAiOUT pin's input signal is at "L" level, and countup is performed when the TAi OUT pin's input signal is at "H" level. When using the TAiOUT pin's input signal to switch countup from and to countdown, set the port P5 and port P6 direction registers' bits which correspond to the TAi OUT pin for the input mode. b7 b6 b5 b4 b3 b2 b1 b0 Up-down register (Address 4416) Bit Bit name 0 Timer A0 up-down bit 1 Timer A1 up-down bit At reset R/W 0 : Countdown 1 : Countup Function 0 RW 0 RW This function is valid when the contents of the updown register is selected as the up-down switching factor. 0 RW 0 RW 2 Timer A2 up-down bit 3 Timer A3 up-down bit 4 Timer A4 up-down bit 0 RW 5 Timer A2 two-phase pulse signal 0 : Two-phase pulse signal processing function disabled 1 : Two-phase pulse signal processing function enabled processing select bit 0 WO (Note) 6 Timer A3 two-phase pulse signal When not using the two-phase pulse signal processing processing select bit function, clear the bit to "0." Timer A4 two-phase pulse signal The value is "0" at reading. processing select bit 0 WO (Note) 0 WO (Note) 7 Note: Use the MOVM(MOVMB) or STA(STAB, STAD) instruction for writing to bits 5 to 7. Fig. 9.4.5 Structure of up-down register 9-22 7902 Group User's Manual TIMER A 9.4 Event counter mode 9.4.4 Selectable functions The following describes the selectable pulse output, and two-phase pulse signal processing functions. (1) Pulse output function The pulse output function is selected by setting the pulse output function select bit (bit 2 at addresses 56 16 to 5A 16 ) to "1." When this function is selected, the TAiOUT pin is forcibly set for the pulse output pin regardless of the corresponding bits of the port P5 and port P6 direction registers. The TAi OUT pin outputs pulses of which polarity is inverted each time a counter underflow or overflow occurs. (Refer to Figure 9.3.5). When the count start bit (address 40 16) is "0" (count stopped), the TAi OUT pin outputs "L" level. In order to make the TA2OUT and TA3OUT pins serve as pulse output pins, be sure not to select the key input interrupt pins (KI 0 and KI2 pins), which are multiplexed with the above pins. (Refer to "CHAPTER 8. KEY INPUT INTERRUPT.") (2) Two-phase pulse signal processing function (Timers A2 to A4) For timers A2 to A4, the two-phase pulse signal processing function is selected by setting the twophase pulse signal processing select bits (bits 5 to 7 at address 44 16 ) to "1." (See Figure 9.4.5.) Figure 9.4.6 shows the timer A2/A3/A4 mode registers when the two-phase pulse signal processing function is selected. For timers with two-phase pulse signal processing function selected, the timer counts two kinds of pulses of which phases differ by 90 degrees. There are two types of the two-phase pulse signal processing: normal processing and quadruple processing. In timer A2 and A3, normal processing is performed; in timer A4, quadruple processing is performed. For the port P5 and P6 direction registers' bits corresponding to the pins used for two-phase pulse input, be sure to set these bits for the input mode. b7 b6 b5 b4 b3 b2 b1 b0 0 1 0 0 0 1 Timer A2 mode register (Address 5816) Timer A3 mode register (Address 5916) Timer A4 mode register (Address 5A16) : It may be either "0" or "1." Fig. 9.4.6 Timer A2/A3/A4 mode registers when two-phase pulse signal processing function is selected 7902 Group User's Manual 9-23 TIMER A 9.4 Event counter mode <Normal processing> Countup is performed at the rising edges input to the TAk IN pin when the TAk IN and TAk OUT have the relationship that the TAkIN pin's input signal goes from "L" to "H" while the TAk OUT (k = 2 and 3) pin's input signal is at "H" level. Countdown is performed at the falling edges input to the TAk IN pin when the TAk IN and TAk OUT have the relationship that the TAkIN pin's input signal goes from "H" to "L" while the TAk OUT pin's input signal is "H." (See Figure 9.4.7.) "H" TAkOUT "L" "H" TAkIN (k=2, 3) "L" Countup Countup +1 Countup Countdown Countdown +1 +1 -1 Countdown -1 -1 Fig. 9.4.7 Normal processing "H" <Quadruple processing> Countup is performed at all rising and falling edges input to the TA4 OUT and TA4 IN pins when the TAk IN and TAk OUT have the relationship that the TA4 IN pin's input signal level goes from "L" to "H" while the TA4 OUT pin's input signal is at "H" level. Countdown is performed at all rising and falling edges input to the TA4 OUT and TA4IN pins when the TAk IN and TAk OUT have the relationship that the TA4 IN pin's input signal level goes from "H" to "L" while the TA4 OUT pin's input signal is at "H" level. (See Figure 9.4.8.) Table 9.4.3 lists the input signals on the TA4 OUT and TA4 IN pins when the quadruple processing is selected. TA4OUT "L" Counted up at all edges. +1 TA4IN +1 +1 +1 Counted down at all edges. -1 +1 -1 -1 -1 "H" "L" Counted up at all edges. +1 +1 +1 +1 +1 Counted down at all edges. -1 -1 -1 -1 Fig. 9.4.8 Quadruple processing Table 9.4.3 TA4 OUT and TA4 IN pin's input signals when quadruple processing is selected Input signal to TA4 OUT pin Countup Countdown 9-24 -1 "H" level "L" level Rising edge Falling edge "H" level "L" level Rising edge Falling edge 7902 Group User's Manual Input signal to TA4IN pin Rising edge Falling edge "L" level "H" level Falling edge Rising edge "H" level "L" level -1 TIMER A [Precautions for event counter mode] [Precautions for event counter mode] 1. While counting is in progress, by reading the timer Ai register, the counter value can be read out at any timing. However, if the timer Ai register is read at the reload timing shown in Figure 9.4.9, the value "FFFF16" (at an underflow) or "0000 16 " (at the overflow) is read out. If reading is performed in the period from when a value is set into the timer Ai register with the counter stopped until the counter starts counting, the set value is correctly read out. (1) For countdown (2) For countup Reload Reload Counter value (Hex.) 2 1 0 Read value (Hex.) 2 1 0 n n-1 FFFF n - 1 Counter value (Hex.) Read value (Hex.) FFFD FFFE FFFF n+1 FFFD FFFE FFFF 0000 n + 1 Time Time n : reload register's contents n n : reload register's contents Fig. 9.4.9 Reading timer Ai register 2. The TAi OUT pin is used for all functions listed below. Accordingly, only one of these functions can be selected for each timer. Switching between countup and countdown by TAi OUT pin's input signal Pulse output function Two-phase pulse signal processing function (Timers A2 to A4) 3. In order to make the TA2OUT and TA3OUT pins serve as pulse output pins, be sure not to select the key input interrupt pins (KI0 and KI 2 pins), which are multiplexed with the above pins. (Refer to "CHAPTER 8. KEY INPUT INTERRUPT.") 7902 Group User's Manual 9-25 TIMER A 9.5 One-shot pulse mode 9.5 One-shot pulse mode In this mode, the timer outputs a pulse which has an arbitrary width once. When a trigger occurs, the timer outputs "H" level from the TAiOUT pin for an arbitrary time. Table 9.5.1 lists the specifications of the one-shot pulse mode. Figure 9.5.1 shows the structures of the timer Ai register and timer Ai mode register in the oneshot pulse mode. Table 9.5.1 Specifications of one-shot pulse mode Item Specifications Count source fi Count operation f1, f 2, f 16 , f64 , f 512 , or f4096 Countdown When the counter value becomes "000016 ," reload register's contents are reloaded, and counting stops. If a trigger occurs during counting, reload register's contents are reloaded, and counting continues. Output pulse width ("H") n [s] n : Timer Ai register's set value fi When a trigger occurs. (Note) Internal or external trigger can be selected by software. When the counter value becomes "000016 " When the count start bit is cleared to "0" When counting stops. Programmable I/O port pin or trigger input pin One-shot pulse output An undefined value is read out. While counting is stopped When a value is written to timer Ai register, it is written to both of the reload register and counter. While counting is in progress When a value is written to timer Ai register, it is written only to the reload register. (Transferred to counter at the next reload timing.) Count start condition Count stop condition Interrupt request occurrence timing TAiIN pin's function TAiOUT pin's function Read from timer Ai register Write to timer Ai register Note: The trigger is generated with the count start bit = "1." 9-26 7902 Group User's Manual TIMER A 9.5 One-shot pulse mode Timer A0 register (Addresses 4716, 4616 ) Timer A1 register (Addresses 4916 , 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Bit (b8) b0 b7 (b15) b7 b0 Function At reset R/W 15 to 0 These bits can be set to "000016" to "FFFF16." Undefined Assuming that the set value = n, the "H" level width of the one-shot pulse which is output from the TAiOUT pin is expressed as follows : n fi. WO fi: Frequency of count source Note: Use the MOVM or STA(STAD) instruction for writing to this register. Writing to this register must be performed in a unit of 16 bits. b7 b6 b5 b4 b3 b2 b1 b0 Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16 ) Bit 0 Bit name Operating mode select bits 0 Function b1 b0 1 0 : One-shot pulse mode 1 2 3 Fix this bit to "1" in one-shot pulse mode. Trigger select bits 4 5 6 b4 b3 00: 01: Writing "1" to one-shot start bit (TAiIN pin functions as a programmable I/O port pin.) 1 0 : Falling edge of TAiIN pin's input signal 1 1 : Rising edge of TAiIN pin's input signal Fix this bit to "0" in one-shot pulse mode. Count source select bits See Table 9.2.3. 7 1 1 0 At reset R/W 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW Fig. 9.5.1 Structures of timer Ai register and timer Ai mode register in one-shot pulse mode 7902 Group User's Manual 9-27 TIMER A 9.5 One-shot pulse mode 9.5.1 Setting for one-shot pulse mode Figures 9.5.2 and 9.5.3 show an initial setting example for registers related to the one-shot pulse mode. Note that when using interrupts, set up to enable the interrupts. For details, refer to "CHAPTER 7. INTERRUPTS." Selecting one-shot pulse mode and each function b7 b0 0 1 1 0 Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16) Selection of one-shot pulse mode Trigger select bits b4 b3 00: 0 1 : Writing "1" to one-shot start bit: Internal trigger 1 0 : Falling of TAiIN pin's input signal: External trigger 1 1 : Rising of TAiIN pin's input signal: External trigger Count source select bits See Table 9.2.3. Setting "H" level width of one-shot pulse (b15) b7 (b8) b0 b7 b0 Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Can be set to "000016" to "FFFF16" (n). n fi fi = Frequency of count source However, if n = "000016", the counter does not operate and the TAiOUT pin outputs "L" level. At this time, no timer Ai interrupt request occurs. Note. "H" level width = Setting interrupt priority level b7 b0 Timer Ai interrupt control register (i = 0 to 4) (Addresses 7516 to 7916) Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. Continue to Figure 9.5.3. Fig. 9.5.2 Initial setting example for registers related to one-shot pulse mode (1) 9-28 7902 Group User's Manual TIMER A 9.5 One-shot pulse mode From preceding Figure 9.5.2 When external trigger is selected When internal trigger is selected Setting count start bit to "1" Setting port P5 and port P6 direction registers b7 b0 Port P5 direction register (Address D16) b7 b0 Count start register (Address 4016) Timer A0 count start bit Pin TA0IN Pin TA1IN Pin TA2IN Timer A1 count start bit Timer A2 count start bit Pin TA3IN b7 Timer A3 count start bit b0 Timer A4 count start bit Port P6 direction register (Address 1016) Pin TA1IN Clear the corresponding bit to "0." Setting count start bit to "1" Setting one-shot start bit to "1" b7 b7 b0 Count start register (Address 4016) Timer A0 count start bit b0 One-shot start register (Address 4216) Timer A0 one-shot start bit Timer A1 one-shot start bit Timer A2 one-shot start bit Timer A3 one-shot start bit Timer A4 one-shot start bit Timer A1 count start bit Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit Trigger input to TAiIN pin AAA AAA AAA AAA Trigger generated Count starts. Fig. 9.5.3 Initial setting example for registers related to one-shot pulse mode (2) 7902 Group User's Manual 9-29 TIMER A 9.5 One-shot pulse mode 9.5.2 Trigger The counter is enabled for counting when the count start bit (address 4016) has been set to "1." The counter starts counting when a trigger is generated after counting has been enabled. An internal or external trigger can be selected as that trigger. An internal trigger is selected when the trigger select bits (bits 4 and 3 at addresses 5616 to 5A 16) are "002" or "012"; an external trigger is selected when the bits are "102" or "11 2." If a trigger is generated during counting, the reload register's contents are reloaded and the counter continues counting. If a trigger generated during counting, make sure that a certain time which is equivalent to one cycle of the timer's count source or more has passed between the previously trigger occurrence and a new trigger occurrence. (1) When selecting internal trigger A trigger is generated when writing "1" to the one-shot start bit (bits 0 to 4 at address 4216 ). Figure 9.5.4 shows the structure of the one-shot start register. (2) When selecting external trigger A trigger is generated at the falling edge of the TAi IN pin's input signal when bit 3 at addresses 56 16 to 5A 16 is "0," or at its rising edge when bit 3 is "1." When using an external trigger, set the port P5 and port P6 direction registers' bits which correspond to the TAi IN pins for the input mode. b7 b6 b5 b4 b3 b2 b1 b0 One-shot start register (Address 4216 ) Bit 0 Bit name 0 Timer A0 one-shot start bit 1 Timer A1 one-shot start bit Function 1 : Start outputting one-shot pulse. (Valid when an internal trigger is selected.) The value is "0" at reading. R/W 0 WO 0 WO 0 WO 2 Timer A2 one-shot start bit 3 Timer A3 one-shot start bit 0 WO 4 Timer A4 one-shot start bit 0 WO Undefined - 0 RW 6, 5 7 Nothing is assigned. Fix this bit to "0." Fig. 9.5.4 Structure of one-shot start register 9-30 At reset 7902 Group User's Manual TIMER A 9.5 One-shot pulse mode 9.5.3 Operation in one-shot pulse mode When the one-shot pulse mode is selected with the operating mode select bits, the TAi OUT pin outputs "L" level. When the count start bit is set to "1," the counter is enabled for counting. After that, counting starts when a trigger is generated. When the counter starts counting, the TAi OUT pin outputs "H" level. (When a value of "000016 " is set to the timer Ai register, the counter stops operating, the output level at pin TAiOUT remains "L," and no timer Ai interrupt request does not occur.) When the counter value becomes "0000 16," the output from the TAiOUT pin becomes "L" level. Additionally, the reload register's contents are reloaded and the counter stops counting there. Simultaneously with , the timer Ai interrupt request bit is set to "1." This interrupt request bit remains set to "1" until the interrupt request is accepted or until the interrupt request bit is cleared to "0" by software. Figure 9.5.5 shows an example of operation in the one-shot pulse mode. When a trigger is generated after above, the counter and TAiOUT pin perform the same operations beginning from again. Furthermore, if a trigger is generated during counting, the counter performs countdown once after this new trigger is generated, and then, it continues counting with the reload register's contents reloaded. If generating a trigger during counting, make sure that a certain time which is equivalent to one cycle of the timer's count source or more has passed between the previously trigger occurrence and a new trigger occurrence. The one-shot pulse output from the TAi OUT pin can be disabled by clearing the timer Ai mode register's bit 2 to "0." Accordingly, timer Ai can also be used as an internal one-shot timer that does not perform the pulse output. In this case, the TAi OUT pin functions as a programmable I/O port pin. In order to make the TA2OUT and TA3OUT pins serve as pulse output pins, be sure not to select the key input interrupt pins (KI 0 and KI2 pins), which are multiplexed with the above pins. (Refer to "CHAPTER 8. KEY INPUT INTERRUPT.") 7902 Group User's Manual 9-31 TIMER A 9.5 One-shot pulse mode Counter contents (Hex.) FFFF16 n = Reload register's contents Starts counting. Stops counting. Stops counting. Starts counting. n Reloaded Reloaded 000116 Time Set to "1" by software. Count start bit Trigger during counting TAiIN pin input signal (1 / fi) (n) (1 / fi) (n+1) One-shot pulse output from TAiOUT pin Timer Ai interrupt request bit fi : Frequency of count source n : Reload register's contents Cleared to "0" when interrupt request is accepted or cleared by software. When the count start bit = "0" (counting stopped), the TAiOUT pin outputs "L" level. When a trigger is generated during counting, the counter counts the count source (n + 1) times after a new trigger is generated. Note: The above applies when an external trigger (rising edge of TAiIN pin's input signal) is selected. Fig. 9.5.5 Example of operation in one-shot pulse mode (selecting external trigger) 9-32 7902 Group User's Manual TIMER A [Precautions for one-shot pulse mode] [Precautions for one-shot pulse mode] 1. If the count start bit is cleared to "0" during counting, the counter becomes as follows: *The counter stops counting, and the reload register's contents are reloaded into the counter. *The TAi OUT pin's output level becomes "L." *The timer Ai interrupt request bit is set to "1." 2. A one-shot pulse is output synchronously with an internally generated count source. Accordingly, when selecting an external trigger, there will be a delay equivalent to one cycle of the count source at maximum, in a period from when a trigger is input to the TAi IN pin until a one-shot pulse is output. Trigger input TAiIN pin's input signal Count source One-shot pulse output from TAiOUT pin Starts outputting of one-shot pulse Note: The above applies when an external trigger (falling edge of TAiIN pin's input signal) is selected. Fig. 9.5.6 Output delay in one-shot pulse output 3. When the timer's operating mode has been set by one of the following procedures, the timer Ai interrupt request bit will be set to "1." When the one-shot pulse mode is selected after reset When the operating mode is switched from the timer mode to the one-shot pulse mode When the operating mode is switched from the event counter mode to the one-shot pulse mode Accordingly, when using a timer Ai interrupt (interrupt request bit), be sure to clear the timer Ai interrupt request bit to "0" after the above setting. 4. In order to make the TA2 OUT and TA3OUT pins serve as pulse output pins, be sure not to select the key input interrupt pins (KI0 and KI 2 pins), which are multiplexed with the above pins. (Refer to "CHAPTER 8. KEY INPUT INTERRUPT.") 7902 Group User's Manual 9-33 TIMER A 9.6 Pulse width modulation (PWM) mode 9.6 Pulse width modulation (PWM) mode In this mode, the timer continuously outputs pulses which have an arbitrary width. Table 9.6.1 lists the specifications of the PWM mode. Figure 9.6.1 shows the structures of the timer Ai register and timer Ai mode register in the PWM mode. Table 9.6.1 Specifications of PWM mode Item Specifications Count source f i f 1, f 2, f 16 , f 64 , f512 , or f 4096 Count operation Countdown (operating as an 8-bit or 16-bit pulse width modulator) Reload register's contents are reloaded at rising edge of PWM pulse, and counting continues. A trigger generated during counting does not affect the counting. PWM period/"H" level width <16-bit pulse width modulator> (2 16 -1) Period = [s] fi n : Timer Ai register's set value n "H" level width = fi [s] Count start condition <8-bit pulse width modulator> m : Timer Ai register's low-order 8 (m + 1)(2 8-1) bits' set value Period = [s] fi n : Timer Ai register's high-order n(m + 1) "H" level width = [s] 8 bits' set value fi When a trigger is generated. (Note) Internal or external trigger can be selected by software. When the count start bit is cleared to "0." Count stop condition Interrupt request occurrence timing At falling edge of PWM pulse TA iIN pin's function Programmable I/O port pin or trigger input pin TA iOUT pin's function PWM pulse output Read from timer Ai register An undefined value is read out. Write to timer Ai register While counting is stopped When a value is written to the timer Ai register, it is written to both of the reload register and counter. While counting is in progress When a value is written to the timer Ai register, it is written only to the reload register. (Transferred to the counter at the next reload time.) Note: The trigger is generated with the count start bit = "1." 9-34 7902 Group User's Manual TIMER A 9.6 Pulse width modulation (PWM) mode <When operating as a 16-bit pulse width modulator> Timer A0 register (Addresses 4716 , 4616) Timer A1 register (Addresses 4916 , 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Bit (b15) b7 (b8) b0 b7 Function b0 At reset R/W 15 to 0 These bits can be set to "000016" to "FFFE16." Undefined Assuming that the set value = n, the "H" level width of the PWM pulse which is output n from the TAiOUT pin is expressed as follows : fi (PWM pulse period = 216-1 ) fi WO fi: Frequency of count source Note: Use the MOVM or STA(STAD) instruction for writing to this register. Writing to this register must be performed in a unit of 16 bits. <When operating as an 8-bit pulse width modulator> Timer A0 register (Addresses 4716, 46 16) Timer A1 register (Addresses 4916, 48 16) Timer A2 register (Addresses 4B16 , 4A16) Timer A3 register (Addresses 4D16 , 4C16 ) Timer A4 register (Addresses 4F16, 4E16) Bit (b15) b7 (b8) b0 b7 Function b0 At reset R/W Undefined These bits can be set to "0016" to "FF16." Assuming that the set value = m, the period of the PWM pulse which is output from the TAiOUT pin is expressed as follows: (m + 1) (28 - 1) fi Undefined 15 to 8 These bits can be set to "0016" to "FF16." Assuming that the set value = n, the "H" level width of the PWM pulse which is output from the TAiOUT pin is expressed as follows: n(m + 1) fi WO 7 to 0 WO f i: Frequency of count source Note: Use the MOVM or STA(STAD) instruction for writing to this register. Writing to this register must be performed in a unit of 16 bits. b7 b6 b5 b4 b3 b2 b1 b0 Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16 ) Bit 0 Bit name Operating mode select bits 1 1 1 Function At reset R/W 0 RW 0 RW 0 RW Writing "1" to count start bit (TAiIN pin functions as a programmable I/O port pin.) 1 0 : Falling edge of TAiIN pin's input signal 1 1 : Rising edge of TAiIN pin's input signal 0 RW 0 RW b1 b0 1 1 : PWM mode 1 2 3 Fix this bit to "1" in PWM mode. Trigger select bits 4 b4 b3 00: 01: 5 16/8-bit PWM mode select bit 0 : 16-bit pulse width modulator 1 : 8-bit pulse width modulator 0 RW 6 Count source select bits See Table 9.2.3. 0 RW 0 RW 7 Fig. 9.6.1 Structures of timer Ai registers and timer Ai mode registers in PWM mode. 7902 Group User's Manual 9-35 TIMER A 9.6 Pulse width modulation (PWM) mode 9.6.1 Setting for PWM mode Figures 9.6.2 and 9.6.3 show an initial setting example for registers relevant to the PWM mode. Note that when using interrupts, set up to enable the interrupts. For details, refer to "CHAPTER 7. INTERRUPTS." Selecting PWM mode and each function b7 b0 1 1 1 Timer Ai mode register (i=0 to 4) (Addresses 5616 to 5A16) Selection of PWM mode Trigger select bits b4 b3 00: Writing "1" to count start bit: Internal trigger 01: 1 0 : Falling edge of TAiIN pin's input signal: External trigger 1 1 : Rising edge of TAiIN pin's input signal: External trigger 16/8-bit PWM mode select bit 0 : Operates as 16-bit pulse width modulator 1 : Operates as 8-bit pulse width modulator Count source select bits See Table 9.2.3. Setting PWM pulse's period and "H" level width When operating as 16-bit pulse width modulator (b15) b7 (b8) b0 b7 b0 Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Can be set to "000016" to "FFFE16" (n) When operating as 8-bit pulse width modulator (b15) b7 (b8) b0 b7 b0 Timer A0 register (Addresses 4716, 4616) Timer A1 register (Addresses 4916, 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) Can be set to "0016" to "FF16" (m) Can be set to "0016" to "FE16" (n) Note. When operating as 8-bit pulse width modulator (m+1) (2 8 - 1) (fi : Frequency of Period = fi count source) "H" level width = Note. When operating as 16-bit pulse width modulator (216 - 1) (fi : Frequency of count source) Period = fi n(m+1) "H" level width = fi However, if n = "0016", the pulse width modulator does not operate and the TAiOUT pin outputs "L" level. At this time, no timer Ai interrupt request occurs. n fi However, if n = "000016", the pulse width modulator does not operate and the TAiOUT pin outputs "L" level. At this time, no timer Ai interrupt request occurs. Continue to Figure 9.6.3. Fig. 9.6.2 Initial setting example for registers related to PWM mode (1) 9-36 7902 Group User's Manual TIMER A 9.6 Pulse width modulation (PWM) mode AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAA AAAAA AAA AA AAAAAAAAAAAA AAAA AAA AA A AAAAA AAA AA AAAAAAAAAAAA AAAAAA AA AAAAAAAAAAAA AAAA AAA A AAAAAA AAAAA AAA AAA AA AAAAAAAAAAAA AAAAAAAAAAAA AAAA AAAAAAAAAAAA AAAAAA AAAAAAAAAAAA AAAA AAA AA AAAAAAAAAAAA AAAAAAAAAAAA AAAA AAAAAAAAAAAA AA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAA AAA AA AAAAAAAAAAAA AAAA AAA AA AAAAAAAAAAAA AAAA AAA AAAAAAAAAAAA AAAA AAAAAA AAAAAA AAAA AAAA AAAA From preceding Figure 9.6.2 Setting interrupt priority level b7 b0 Timer Ai interrupt control register (i = 0 to 4) (Addresses 7516 to 7916) Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. When internal trigger is selected When external trigger is selected Setting port P5 and port P6 direction registers Setting count start bit to "1" b7 b7 b0 Port P5 direction register (Address D16) b7 b0 b0 Count start register (Address 4016) Pin TA0IN Timer A0 count start bit Pin TA1IN Timer A1 count start bit Pin TA2IN Timer A2 count start bit Pin TA3IN Timer A3 count start bit Port P6 direction register (Address 1016) Timer A4 count start bit Pin TA4IN Clear the corresponding bit to "0." Setting count start bit to "1" b7 b0 Count start register (Address 4016) Timer A0 count start bit Timer A1 count start bit Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit Trigger input to TAiIN pin Trigger generated Count starts. Fig. 9.6.3 Initial setting example for registers related to PWM mode (2) 7902 Group User's Manual 9-37 TIMER A 9.6 Pulse width modulation (PWM) mode 9.6.2 Trigger When a trigger is generated, the TAiOUT pin starts to output PWM pulses. An internal or an external trigger can be selected as that trigger. An internal trigger is selected when the trigger select bits (bits 4 and 3 at addresses 56 16 to 5A16 ) are "002" or "012"; an external trigger is selected when these bits are "10 2" or "11 2." A trigger generated during PWM pulse output is invalid, and it does not affect the pulse output operation. (1) When selecting internal trigger A trigger is generated when "1" is written to the count start bit (address 40 16 ). (2) When selecting external trigger A trigger is generated at the falling edge of the TAiIN pin's input signal when bit 3 at addresses 5616 to 5A16 is "0," or at its rising edge when bit 3 is "1." However, the trigger input is acceptable only when the count start bit is "1." When using an external trigger, set the port P5 and port P6 direction registers' bits which correspond to the TAiIN pins for the input mode. 9-38 7902 Group User's Manual TIMER A 9.6 Pulse width modulation (PWM) mode 9.6.3 Operation in PWM mode When the PWM mode is selected with the operating mode select bits, the TAi OUT pin outputs "L" level. When a trigger is generated, the counter (pulse width modulator) starts counting and the TAi OUT pin outputs a PWM pulse (Notes 1 and 2). The timer Ai interrupt request bit is set to "1" each time the PWM pulse level goes from "H" to "L." The interrupt request bit remains set to "1" until the interrupt request is accepted or until the interrupt request bit is cleared to "0" by software. Each time a PWM pulse has been output for one period, the reload register's contents are reloaded and the counter continues counting. The following explains operations of the pulse width modulator. (1) 16-bit pulse width modulator When the 16/8-bit PWM mode select bit is cleared to "0," the counter operates as a 16-bit pulse width modulator. Figures 9.6.4 and 9.6.5 show operation examples of the 16-bit pulse width modulator. (2) 8-bit pulse width modulator When the 16/8-bit PWM mode select bit is set to "1," the counter is divided into 8-bit halves. Then, the high-order 8 bits operate as an 8-bit pulse width modulator, and the low-order 8 bits operate as an 8-bit prescaler. Figures 9.6.6 and 9.6.7 show operation examples of the 8-bit pulse width modulator. Notes 1: If a value "0000 16" is set into the timer Ai register when the counter operates as a 16-bit pulse width modulator, the pulse width modulator does not operate and the output from the TAi OUT pin remains "L" level. The timer Ai interrupt request does not occur. Similarly, if a value "00 16 " is set into the high-order 8 bits of the timer Ai register when the counter operates as an 8-bit pulse width modulator, the same is performed. 2: When the counter operates as an 8-bit pulse width modulator, after a trigger is generated, the TAiOUT pin outputs "L" level for a period of (1 / f i ) (m + 1) (n + 1). After that, the PWM pulse output will start. In order to make the TA2OUT and TA3 OUT pins serve as pulse output pins, be sure not to select the key input interrupt pins (KI0 and KI 2 pins), which are multiplexed with the above pins. (Refer to "CHAPTER 8. KEY INPUT INTERRUPT.") 7902 Group User's Manual 9-39 TIMER A 9.6 Pulse width modulation (PWM) mode (1 / fi) (216 - 1) Count source TAiIN pin's input signal Trigger is not generated by this signal. (1 / fi) (n) PWM pulse output from TAiOUT pin Timer Ai interrupt request bit fi: Frequency of count source Cleared to "0" when interrupt request is accepted or cleared by software. n: Reload register Note: The above applies when n = "000316" and an external trigger (rising edge of TAiIN pin's input signal) is selected. Fig. 9.6.4 Operation example of 16-bit pulse width modulator n = Reload register's contents Counter contents (Hex.) (1 / fi) (216 -1) (1 / fi) (216 -1) (1 / fi) (216 -1) FFFE16 200016 (216 -1) - n n 000116 Stops counting. TAiIN pin's input signal Restarts counting. Time PWM pulse output from TAiOUT pin fi: Frequency of count source n: Reload register's contents "FFFE16" is set to timer Ai register. "000016" is set to timer Ai register. "200016" is set to timer Ai register. When an arbitrary value is set to the timer Ai register after setting "000016" to it, the timing when the PWM pulse goes "H" depends on the timing when the new value is set. Note: The above applies when an external trigger (rising edge of TAiIN pin's input signal) is selected. Fig. 9.6.5 Operation example of 16-bit pulse width modulator (when counter value is updated during pulse output) 9-40 7902 Group User's Manual TIMER A 9.6 Pulse width modulation (PWM) mode (1 / fi) (m + 1) (28 - 1) Count source TAiIN pin's input signal (1 / fi) (m + 1) 8-bit prescaler's underflow signal (1 / fi) (m + 1) (n) PWM pulse output from TAiOUT pin Timer Ai interrupt request bit Cleared to "0" when interrupt request is accepted or cleared by software. fi: Frequency of count source n: Reload register's high-order 8 bits m: Reload register's low-order 8 bits The 8-bit prescaler counts the count source. The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. Note: The above applies when n = "0216", m = "0216", and an external trigger (falling edge of TAiIN pin's input signal) is selected. Fig. 9.6.6 Operation example of 8-bit pulse width modulator 7902 Group User's Manual 9-41 Prescaler's contents (Hex.) 7902 Group User's Manual 0116 0416 0A16 0016 0216 "040216" is set to timer Ai register. "000216" is set to timer Ai register. (1 / fi) (m+1) (28 -1) Restarts counting. "0A0216" is set to timer Ai register. Stops counting. (1 / fi) (m + 1) (28 -1) Note: The above applies when an external trigger (falling edge of TAiIN pin's input signal) is selected. When an arbitrary value is set to the timer Ai register after setting "0016" to it, the timing when the PWM pulse level goes "H" depends on the timing when the new value is set. fi: Frequency of count source m: Reload register's low-order 8 bits PWM pulse output from TAiOUT pin Counter's contents (Hex.) 9-42 TAiIN pin's input signal Count source (1 / fi) (m+1) (28 -1) Time Time TIMER A 9.6 Pulse width modulation (PWM) mode Fig. 9.6.7 Operation example of 8-bit pulse width modulator (when counter value is updated during pulse output) TIMER A [Precautions for pulse width modulation PWM mode] [Precautions for pulse width modulation (PWM) mode] 1. If the count start bit is cleared to "0" during PWM pulse output, the counter stops counting. If the TAiOUT pin outputs "H" level at that time, the output level will become "L" and the timer Ai interrupt request bit will be set to "1." When the TAiOUT pin outputs "L" level at that time, the output level will not change and no timer Ai interrupt request will occur. 2. When the timer's operating mode is set by one of the following procedures, the timer Ai interrupt request bit is set to "1." When the PWM mode is selected after reset When the operating mode is switched from the timer mode to the PWM mode When the operating mode is switched from the event counter mode to the PWM mode Accordingly, when using a timer Ai interrupt (interrupt request bit), be sure to clear the timer Ai interrupt request bit to "0" after the above setting. 3. When using timers A2 and A3 in the PWM mode, the TA2 OUT and TA3 OUT pins serve as pulse output pins. Therefore, be sure not to select the key input interrupt pins (KI 0 and KI 2 pins), which are multiplexed with the above pins. (Refer to "CHAPTER 8. KEY INPUT INTERRUPT.") 7902 Group User's Manual 9-43 TIMER A [Precautions for pulse width modulation PWM mode] MEMORANDUM 9-44 7902 Group User's Manual CHAPTER 10 TIMER B 10.1 Overview 10.2 Block description 10.3 Timer mode [Precautions for timer mode] 10.4 Event counter mode [Precautions for event counter mode] 10.5 Pulse period/Pulse width measurement mode [Precautions for pulse period/pulse width measurement mode] TIMER B 10.1 Overview, 10.2 Block description 10.1 Overview Timer B consists of three counters (timers B0 to B2) each equipped with a 16-bit reload function. Timers B0 to B2 have identical functions and operate independently of one other. Timer Bi (i = 0 to 2) has three operating modes listed below. (1) Timer mode The timer counts an internally generated count source. (2) Event counter mode The timer counts an external signal. (3) Pulse period/Pulse width measurement mode The timer measures an external signal's pulse period or pulse width. 10.2 Block description Figure 10.2.1 shows the block diagram of timer B. Explanation of registers relevant to timer B is described below. Data bus (odd) Count source select bits f2 f16 f64 Data bus (even) (Low-order 8 bits) f512 *Timer *Pulse period measurement/pulse width measurement TBiIN Polarity selection and edge pulse generator Timer Bi reload register (16) Event counter mode Timer Bi counter (16) Timer B2 clock source select bit (Note) Count start register Counter reset circuit Timer B2 clock source select bit : Bit 6 at address 6316 Note: Only for timer B2, a count source in the event counter mode can be selected. Fig. 10.2.1 Block diagram of timer B 10-2 (High-order 8 bits) 7902 Group User's Manual Timer Bi interrupt request bit Timer Bi overflow flag (Valid in the pulse period/pulse width measurement mode.) TIMER B 10.2 Block description 10.2.1 Counter and Reload register (timer Bi register) Each of timer Bi counter and reload register consists of 16 bits and has the following functions. (1) Functions in timer mode and event counter mode Countdown in the counter is performed each time the count source is input. The reload register is used to store the initial value of the counter. When a counter underflow occurs, the reload register's contents are reloaded into the counter. A value is set to the counter and reload register by writing the value to the timer Bi register. Table 10.2.1 lists the memory assignment of the timer Bi register. The value written into the timer Bi register while counting is not in progress is set to the counter and reload register. The value written into the timer Bi register while counting is in progress is set only to the reload register. In this case, the reload register's updated contents are transferred to the counter at the next underflow. The counter value is read out by reading out the timer Bi register. Note: When reading from or writing to the timer Bi register, perform it in a unit of 16 bits. For more information about the value obtained by reading the timer Bi register, refer to sections "[Precautions for timer mode]" and "[Precautions for event counter mode]." (2) Functions in pulse period/pulse width measurement mode Countup in the counter is performed each time the count source is input. The reload register is used to retain the pulse period or pulse width measurement result. When a valid edge is input to the TBiIN pin, the counter value is transferred to the reload register. In this mode, the value obtained by reading the timer Bi register is the reload register's contents, so that the measurement result is obtained. Note: When reading from the timer Bi register, perform it in a unit of 16 bits. Table 10.2.1 Memory assignment of timer Bi registers Timer Bi register Timer B0 register Timer B1 register Timer B2 register High-order byte Address 5116 Address 5316 Address 5516 Low-order byte Address 5016 Address 5216 Address 5416 Note: At reset, the contents of the timer Bi register are undefined. 7902 Group User's Manual 10-3 TIMER B 10.2 Block description 10.2.2 Count start register This register is used to start and stop counting. One bit of this register corresponds to one timer. (This is the one-to-one relationship.) Figure 10.2.2 shows the structure of the count start register. b7 b6 b5 b4 b3 b2 b1 b0 Count start register (Address 4016) Bit Bit name Function 0 : Stop counting 1 : Start counting At reset R/W 0 RW 0 RW 0 Timer A0 count start bit 1 Timer A1 count start bit 2 Timer A2 count start bit 0 RW 3 Timer A3 count start bit 0 RW 4 Timer A4 count start bit 0 RW 5 Timer B0 count start bit 0 RW 6 Timer B1 count start bit 0 RW 7 Timer B2 count start bit 0 RW Fig. 10.2.2 Structure of count start register 10.2.3 Timer Bi mode register Figure 10.2.3 shows the structure of the timer Bi mode register. The operating mode select bits are used to select the operating mode of timer Bi. Bits 2, 3, and bits 5 to 7 have different functions according to the operating mode. These bits are described in the paragraph of each operating mode. b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16) Bit 0 Operating mode select bits 1 2 Function Bit name b1 b0 0 0 : Timer mode 0 1 : Event counter mode 1 0 : Pulse period/Pulse width measurement mode 1 1 : Do not select. These bits have different functions according to the operating mode. 3 R/W 0 RW 0 RW 0 RW 0 RW 4 Nothing is assigned. Undefined - 5 These bits have different functions according to the operating mode. Undefined RO (Note) 6 0 RW 7 0 RW Note: Bit 5 is invalid in the timer and event counter modes; its value is undefined at reading. Fig. 10.2.3 Structure of timer Bi mode register 10-4 At reset 7902 Group User's Manual TIMER B 10.2 Block description 10.2.4 Timer Bi interrupt control register Figure 10.2.4 shows the structure of the timer Bi interrupt control register. For details about interrupts, refer to "CHAPTER 7. INTERRUPTS." b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi interrupt control register (i = 0 to 2) (Addresses 7A16 to 7C 16) Bit Bit name 0 Interrupt priority level select bits 1 2 3 Interrupt request bit 7 to 4 Nothing is assigned. Function b2 b1b0 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0 : No interrupt requested 1 : Interrupt requested At reset R/W 0 RW 0 RW 0 RW 0 RW (Note) Undefined -- Note: When writing to this bit, use the MOVM (MOVMB) or STA (STAB, STAD) instruction. Fig. 10.2.4 Structure of timer Bi interrupt control register (1) Interrupt priority level select bits (bits 2 to 0) These bits are used to select a timer Bi interrupt's priority level. When using timer Bi interrupts, select the priority level from levels 1 through 7. When a timer Bi interrupt request occurs, its priority level is compared with the processor interrupt priority level (IPL), so that the requested interrupt is enabled only when its priority level is higher than the IPL. (However, this applies when the interrupt disable bit (I) = "0.") To disable timer Bi interrupts, set these bits to "0002" (level 0). (2) Interrupt request bit (bit 3) This bit is set to "1" when a timer Bi interrupt request occurs. This bit is automatically cleared to "0" when the timer Bi interrupt request is accepted. This bit can be set to "1" or cleared to "0" by software. 7902 Group User's Manual 10-5 TIMER B 10.2 Block description 10.2.5 Port P6 direction register The input pins of timer Bi are multiplexed with port P6 pins. When using these pins as timer Bi's input pins, clear the corresponding bits of the port P6 direction register to "0" in order to set these port pins for the input mode. Figure 10.2.5 shows the relationship between port P6 direction register and the timer Bi's input pins. b7 b6 b5 b4 b3 b2 b1 b0 Port P6 direction register (Address 1016) Bit Corresponding pin 0 Pin TA4OUT 1 Pin TA4IN 2 Pin INT0 Functions 0 : Input mode 1 : Output mode When using this pin as timer Bi's input pin, be sure to clear the corresponding bit to "0." At reset R/W 0 RW 0 RW 0 RW 0 RW 3 Pin INT1 4 Pin INT2 (Note) 0 RW 5 Pin TB0IN 0 RW 6 Pin TB1IN 0 RW 7 Pin TB2IN 0 -- Note: This applies when the pin INT2 select bit (bit 4 at address 9416) = "0." Fig. 10.2.5 Relationship between port P6 direction register and timer Bi's input pins 10.2.6 Count source (in timer mode and pulse period/pulse width measurement mode) In the timer mode and pulse period/pulse width measurement mode, the count source select bits (bits 6 and 7 at addresses 5B 16 to 5D16 ) are used to select the count source (f2, f16, f 64, or f512). (See Figures 10.3.1 and 10.5.1.) 10-6 7902 Group User's Manual TIMER B 10.3 Timer mode 10.3 Timer mode In this mode, the timer counts an internally generated count source. Table 10.3.1 lists the specification of the timer mode. Figure 10.3.1 shows the structures of the timer Bi register and timer Bi mode register in the timer mode. Table 10.3.1 Specifications of timer mode Item Specifications Count source fi f2, f 16 , f64 , or f 512 Count operation *Countdown *When a counter underflow occurs, reload register's contents are reloaded, and counting continues. Division ratio 1 n: Timer Bi register's set value (n + 1) Count start condition Count stop condition Interrupt request occurrence timing TBi IN pin's function Read from timer Bi register Write to timer Bi register When the count start bit is set to "1." When the count start bit is cleared to "0." When a counter underflow occurs. Programmable I/O port pin Counter value can be read out. While counting is stopped When a value is written to the timer Bi register, it is written to both of the reload register and counter. While counting is in progress When a value is written to the timer Bi register, it is written only to the reload register. (Transferred to the counter at the next reload timing.) 7902 Group User's Manual 10-7 TIMER B 10.3 Timer mode Timer B0 register (Addresses 5116, 50 16) Timer B1 register (Addresses 5316, 52 16) Timer B2 register (Addresses 5516, 54 16) Bit (b8) b0 b7 (b15) b7 b0 Function At reset R/W 15 to 0 These bits can be set to "000016" to "FFFF16." Undefined Assuming that the set value = n, the counter divides the count source frequency by (n + 1). When reading, the register indicates the counter value. RW Note: Reading from or writing to this register must be performed in a unit of 16 bits. b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi mode register (i = 0 to 2) (Addresses 5B 16 to 5D16 ) Bit 0 Bit name Operating mode select bits Function b1 b0 0 0 : Timer mode 1 2 These bits are invalid in timer mode. 3 X X X 0 0 At reset R/W 0 RW 0 RW 0 RW 0 RW 4 Nothing is assigned. Undefined -- 5 This bit is invalid in timer mode; its value is undefined at reading. Undefined RO 6 Count source select bits 0 RW 0 RW 7 b7 b6 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 X : It may be either "0" or "1." Fig. 10.3.1 Structures of timer Bi register and timer Bi mode register in timer mode 10-8 7902 Group User's Manual TIMER B 10.3 Timer mode 10.3.1 Setting for timer mode Figure 10.3.2 shows an initial setting example for registers relevant to the timer mode. Note that when using interrupts, set up registers to enable the interrupts. For details, refer to "CHAPTER 7. INTERRUPTS." Selecting timer mode and count source b7 b0 0 0 Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16) Selection of timer mode Count source select bits b7 b6 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 : It may be either "0" or "1." Setting division ratio (b15) b7 (b8) b0 b7 b0 Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) Timer B2 register (Addresses 5516, 5416) Can be set to "000016" to "FFFF16" (n). Note: The counter divides the count source by (n + 1). Setting interrupt priority level b7 b0 Timer Bi interrupt control register (i = 0 to 2) (Addresses 7A16 to 7C16) Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. Setting count start bit to "1" b7 b0 Count start register (Address 4016) Timer B0 count start bit Timer B1 count start bit Timer B2 count start bit AAAA AAAA AAAA Count starts. Fig. 10.3.2 Initial setting example for registers relevant to timer mode 7902 Group User's Manual 10-9 TIMER B 10.3 Timer mode 10.3.2 Operation in timer mode When the count start bit is set to "1," the counter starts counting of the count source. When a counter underflow occurs, the reload register's contents are reloaded and counting continues. The timer Bi interrupt request bit is set to "1" at the counter underflow in . The interrupt request bit remains set to "1" until the interrupt request is accepted or until the interrupt request bit is cleared to "0" by software. Figure 10.3.3 shows an example of operation in the timer mode. Counter contents (Hex.) FFFF16 Starts counting. 1 / fi (n+1) Stops counting. n Restarts counting. 000016 Time Set to "1" by software. Cleared to "0" by software. Count start bit Timer Bi interrupt request bit fi : Frequency of count source n : Reload register's contents Cleared to "0" when interrupt request is accepted or cleared by software. Fig. 10.3.3 Example of operation in timer mode 10-10 7902 Group User's Manual Set to "1" by software. TIMER B [Precautions for timer mode] [Precautions for timer mode] While counting is in progress, by reading the timer Bi register, the counter value can be read out at any timing. However, if the timer Bi register is read at the reload timing shown in Figure 10.3.4, the value "FFFF16 " is read out. If reading is performed in the period from when a value is set into the timer Bi register with the counter stopped until the counter starts counting, the set value is correctly read out. Reload Counter value (Hex.) 2 1 0 Read value (Hex.) 2 1 0 n n-1 FFFF n - 1 n = Reload register's contents Time Fig. 10.3.4 Reading timer Bi register 7902 Group User's Manual 10-11 TIMER B 10.4 Event counter mode 10.4 Event counter mode In this mode, the timer counts an external signal. Table 10.4.1 lists the specifications of the event counter mode. Figure 10.4.1 shows the structures of the timer Bi register and the timer Bi mode register in the event counter mode. Table 10.4.1 Specifications of event counter mode Item Specifications Count source *External signal input to the TBi IN pin, fX 32 (Note 1) *The count source's valid edge can be selected from the falling edge, the rising edge, and both of the falling and rising edges by software. Count operation *Countdown *When a counter underflow occurs, reload register's contents are reloaded, and counting continues. Division ratio 1 n: Timer Bi register's set value (n + 1) Count start condition Count stop condition Interrupt request occurrence timing TBi IN pin's function Read from timer Bi register Write to timer Bi register When the count start bit is set to "1." When the count start bit is cleared to "0." When the counter underflow occurs. Count source input pin (Note 2) Counter value can be read out. While counting is stopped When a value is written to the timer Bi register, it is written to both of the reload register and counter. While counting is in progress When a value is written to the timer Bi register, it is written only to the reload register. (Transferred to the counter at the next reload timing.) Notes 1 :Only for timer B2, fX 32 can be selected. 2 :When fX 32 is selected as the count source in timer B2, the TB2IN pin can be used as a programmable I/O port pin. 10-12 7902 Group User's Manual TIMER B 10.4 Event counter mode Timer B0 register (Addresses 5116, 5016 ) Timer B1 register (Addresses 5316, 5216 ) Timer B2 register (Addresses 5516, 5416 ) Bit (b15) b7 (b8) b0 b7 Function b0 At reset R/W 15 to 0 These bits can be set to "000016" to "FFFF16." Undefined Assuming that the set value = n, the counter divides the count source frequency by (n + 1). When reading, the register indicates the counter value. RW Note: Reading from or writing to this register must be performed in a unit of 16 bits. b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16) Bit 0 Bit name Operating mode select bits X X X Function b1 b0 0 1 : Event counter mode 1 2 Count polarity select bits 3 b3 b2 0 0 : Count at falling edge of external signal 0 1 : Count at rising edge of external signal 1 0 : Count at both falling and rising edges of external signal 1 1 : Do not select. (Note) 4 Nothing is assigned. 5 This bit is invalid in event counter mode; its value is undefined at reading. 6 These bits are invalid in event counter mode. 7 0 1 At reset R/W 0 RW 0 RW 0 RW 0 RW Undefined -- Undefined RO 0 RW 0 RW X : It may be either "0" or "1." Note: When the timer B2 clock source select bit (bit 6 at address 6316) = "1," be sure to fix these bits to "012" (count at the rising edge of the external signal). Fig. 10.4.1 Structures of timer Bi register and timer Bi mode register in event counter mode 7902 Group User's Manual 10-13 TIMER B 10.4 Event counter mode 10.4.1 Count source For timer B2 in the event counter mode, a count source (an external signal into the TB2IN pin, or fX32 ) can be selected by using the timer B2 clock source select bit. (See Figure 10.4.2.) Timers B0 and B1 count the external signals input to the TB0 IN and TB1 IN pins, respectively. When fX32 is selected as the count source, the TB2 IN pin serves as a programmable I/O port pin. b7 b6 b5 b4 b3 b2 b1 b0 Particular function select register 1 (Address 6316) Bit Bit name Function At reset R/W 0 STP-instruction-execution status bit 0 : Normal operation. 1 : STP instruction has been executed. (Note 1) RW (Note 2) 1 WIT-instruction-execution status bit Standby state select bit 0 : Normal operation. 1 : WIT instruction has been executed. (Note 1) RW (Note 2) 0 : External bus 1 : Programmable I/O port 0 RW 0 : In the wait mode, system clock fsys is active. 1 : In the wait mode, system clock fsys is stopped. 0 RW 4 System clock stop select bit at WIT (Note 3) Address output select bit 0 : Address output changes at access to the internal area and external area. 1 : Address output changes only at access to the external area. 0 RW 5 The value is "0" at reading. 0 -- 6 Timer B2 clock source select bit 0 : External signal input to the TB2IN pin is counted. (Valid in event counter mode.) 1 : fX32 is counted. 0 RW 7 The value is "0" at reading. 0 -- 2 3 Notes 1: At power-on reset, this bit becomes "0." At hardware reset or software reset, this bit retains the value just before reset. 2: Even when "1" is written, the bit status will not change. 3: Setting this bit to "1" must be performed just before execution of the WIT instruction. Also, after the wait state is terminated, this bit must be cleared to "0" immediately. Fig. 10.4.2 Structures of particular function select register 1 10-14 7902 Group User's Manual TIMER B 10.4 Event counter mode 10.4.2 Setting for event counter mode Figure 10.4.3 shows an initial setting example for registers relevant to the event counter mode. Note that when using interrupts, set up to enable the interrupts. For details, refer to section "CHAPTER 7. INTERRUPTS." Selecting event counter mode and count polarity b7 b0 0 1 Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16) Selection of event counter mode Count polarity select bits b3 b2 0 0 : Count at falling edge of external signal. 0 1 : Count at rising edge of external signal. 1 0 : Count at both of falling and rising edges of external signal. 1 1 : Do not selected. : It may be either "0" or "1." Timers B0 and B1 Timer B2 Selecting clock source b7 b0 Particular function select register 1 (Address 6316) Timer B2 clock source select bit 0 : Count an external signal input to the TB2IN pin 1 : Count fX32 Setting division ratio (b15) b7 (b8) b0 b7 b0 Timer B0 register (Addresses 5116, 5016) Timer B1 register (Addresses 5316, 5216) Timer B2 register (Addresses 5516, 5416) Can be set to "000016" to "FFFF16" (n). Note: The counter divides the count source by (n + 1). Setting interrupt priority level b7 b0 Timer Bi interrupt control register (i = 0 to 2) (Addresses 7A16 to 7C16) Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. AAAA AAAA Setting port P6 direction register b7 b0 Port P6 direction register (Address 1016) Pin TB0IN Pin TB1IN Clear the corresponding bit to "0." Pin TB2IN (Note) Note: When fX32 is selected as the count source of timer B2 (bit 6 at address 6316 = "1"), this setting is unnecessary. Setting count start bit to "1" b7 b0 Count start register (Address 4016) Timer B0 count start bit Timer B1 count start bit Timer B2 count start bit AAA AAA AAA Count starts. Fig. 10.4.3 Initial setting example for registers relevant to event counter mode 7902 Group User's Manual 10-15 TIMER B 10.4 Event counter mode 10.4.3 Operation in event counter mode When the count start bit is set to "1," the counter starts counting of the count source. When a counter underflow occurs, the reload register's contents are reloaded, and counting continues. The timer Bi interrupt request bit is set to "1" at the counter underflow in . The interrupt request bit remains set to "1" until the interrupt request is accepted or until the interrupt request bit is cleared to "0" by software. Figure 10.4.4 shows an example of operation in the event counter mode. Counter contents (Hex.) FFFF16 Starts counting. Stops counting. n Restarts counting . 000016 Time Set to "1" by software. Cleared to "0" by software. Set to "1" by software. Count start bit Timer Bi interrupt request bit n : Reload ragister's contents Cleared to "0" when interrupt request is accepted or cleared to "0" by software. Fig. 10.4.4 Example of operation in event counter mode 10-16 7902 Group User's Manual TIMER B [Precautions for event counter mode] [Precautions for event counter mode] While counting is in progress, by reading the timer Bi register, the counter value can be timing. However, if the timer Bi register is read at the reload timing shown in Figure "FFFF 16" is read out. If reading is performed in the period from when a value is set into the with the counter stopped until the counter start counting, the set value is correctly read read out at any 10.4.5, a value timer Bi register out. Reload Counter value (Hex.) 2 1 0 Read value (Hex.) 2 1 0 n = Reload register's contents n n-1 FFFF n - 1 Time Fig. 10.4.5 Reading timer Bi register 7902 Group User's Manual 10-17 TIMER B 10.5 Pulse period/Pulse width measurement mode 10.5 Pulse period/Pulse width measurement mode In this mode, the timer measures an external signal's pulse period or pulse width. Table 10.5.1 lists the specifications of the pulse period/pulse width measurement mode. Figure 10.5.1 shows the structures of the timer Bi register and timer Bi mode register in the pulse period/pulse width measurement mode. (1) Pulse period measurement The timer measures the pulse period of the external signal that is input to the TBi IN pin. (2) Pulse width measurement The timer measures the pulse width ("L" level and "H" level widths) of the external signal that is input to the TBi IN pin. Table 10.5.1 Specifications of pulse period/pulse width measurement mode Item Specifications Count source fi f2, f 16 , f 64 , or f512 Count operation Countup Counter value is transferred to the reload register at valid edge of measurement pulse, and counting continues after clearing the counter value to "0000 16." Count start condition When the count start bit is set to "1." Count stop condition When the count start bit is cleared to "0." Interrupt request occurrence timing When a valid edge of measurement pulse is input (Note 1). When a counter overflow occurs (The timer Bi overflow flag is set to "1" simultaneously.) TBiIN pin's function Measurement pulse input pin Read from timer Bi register The value obtained by reading the timer Bi register is the reload register's contents (Measurement result) (Note 2). Write to timer Bi register Invalid Timer Bi overflow flag: This bit is used to identify the source of an interrupt request occurrence. Notes 1: No interrupt request occurs when the first valid edge is input after the counter starts counting. 2: The value read out from the timer Bi register is undefined in the period after the counter starts counting until the second valid edge is input. 10-18 7902 Group User's Manual TIMER B 10.5 Pulse period/Pulse width measurement mode Timer B0 register (Addresses 5116, 50 16) Timer B1 register (Addresses 5316, 52 16) Timer B2 register (Addresses 5516, 54 16) Bit (b8) b0 b7 (b15) b7 Function 15 to 0 The measurement result of pulse period or pulse width is read out. b0 At reset R/W Undefined RO Note: Reading from this register must be performed in a unit of 16 bits. b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16 ) Bit 0 1 0 Function Bit name Operating mode select bits b1 b0 1 0 : Pulse period/Pulse width measurement mode 1 2 Measurement mode select bits 3 4 Nothing is assigned. 5 Timer Bi overflow flag 6 Count source select bits 7 b3 b2 0 0 : Pulse period measurement (Interval between falling edges of measurement pulse) 0 1 : Pulse period measurement (Interval between rising edges of measurement pulse) 1 0 : Pulse width measurement (Interval from a falling edge to a rising edge, and from a rising edge to a falling edge of measurement pulse) 1 1 : Do not select. 0 : No overflow (Note) 1 : Overflowed b7 b6 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 At reset R/W 0 RW 0 RW 0 RW 0 RW Undefined -- Undefined RO 0 RW 0 RW Note: The timer Bi overflow flag is cleared to "0" when a value is written to the timer Bi mode register with the count start bit = "1." This flag cannot be set to "1" by software. Fig. 10.5.1 Structures of timer Bi register and timer Bi mode register in pulse period/pulse width measurement mode 7902 Group User's Manual 10-19 TIMER B 10.5 Pulse period/Pulse width measurement mode 10.5.1 Setting for pulse period/pulse width measurement mode Figure 10.5.2 shows an initial setting example for registers relevant to the pulse period/pulse width measurement mode. Note that when using interrupts, set up to enable the interrupts. For details, refer to "CHAPTER 7. INTERRUPTS." Selecting pulse period/pulse width measurement mode and each function b7 b0 Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16) (Note 1) 1 0 Selection of pulse period/pulse width measurement mode Measurement mode select bits b3 b2 0 0 : Pulse period measurement (Interval between falling edges of measurement pulse) 0 1 : Pulse period measurement (Interval between rising edges of measurement pulse) 1 0 : Pulse width measurement 1 1 : Do not select. Timer Bi overflow flag (Note 2) 0: No overflow 1: Overflowed Count source select bits b7b6 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 Setting interrupt priority level b7 b0 Timer Bi interrupt control register (i = 0 to 2) (Addresses 7A16 to 7C16) Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. Setting port P6 direction register b7 b0 Port P6 direction register (Address 1016) Pin TB0IN Pin TB1IN Clear the corresponding bit to "0." Pin TB2IN Setting count start bit to "1" b7 b0 Count start register (Address 4016) Timer B0 count start bit Timer B1 count start bit Timer B2 count start bit AAA AAA AAA Count starts. Notes 1: When using timer B2, be sure to clear the timer B2 clock source select bit (See Figure 10.4.2.) to "0." 2: The timer Bi overflow flag is a read-only bit. This bit is undefined after reset. When a value is written to the timer Bi mode register with the count start bit = "1," this bit will be cleared to "0." Fig. 10.5.2 Initial setting example for registers relevant to pulse period/pulse width measurement mode 10-20 7902 Group User's Manual TIMER B 10.5 Pulse period/pulse width measurement mode 10.5.2 Operation in pulse period/pulse width measurement mode When the count start bit is set to "1," the counter starts counting of the count source. The counter value is transferred to the reload register when an valid edge of the measurement pulse is detected. (Refer to section "(1) Pulse period/Pulse width measurement.") The counter value is cleared to "0000 16 " after the transfer in , and the counter continues counting. The timer Bi interrupt request bit is set to "1" when the counter value is cleared to "0000 16 " in (Note). The interrupt request bit remains set to "1" until the interrupt request is accepted or until the interrupt request bit is cleared to "0" by software. The timer repeats operations to above. Note: No timer Bi interrupt request occurs when the first valid edge is input after the counter starts counting. (1) Pulse period/pulse width measurement The measurement mode select bits (bits 3 and 2 at addresses 5B16 and 5D 16 ) specify whether the pulse period of an external signal is measured or its pulse width is done. Table 10.5.2 lists the relationship between the measurement mode select bits and the pulse period/pulse width measurements. Make sure that the measurement pulse interval from the falling edge to the rising edge, and vice versa are two cycles of the count source or more. Additionally, use software to identify whether the measurement result indicates the "H" level width or the "L" level width. Table 10.5.2 Relationship between measurement mode select bits and pulse period/pulse width measurements b3 b2 Pulse period/Pulse width measurement 0 0 1 0 1 0 Pulse period measurement Pulse width measurement Measurement interval (Valid edges) From falling edge to falling edge (Falling edges) From rising edge to rising edge (Rising edges) From falling edge to rising edge, and vice versa (Falling and rising edges) (2) Timer Bi overflow flag A timer Bi interrupt request occurs when a measurement pulse's valid edge is input or when a counter overflow occurs. The timer Bi overflow flag is used to identify the source of the interrupt request occurrence, that is, whether it is an overflow occurrence or a valid edge input. The timer Bi overflow flag is set to "1" at an overflow occurrence. Accordingly, the source of the interrupt request occurrence is identified by checking the timer Bi overflow flag in the interrupt routine. When a value is written to the timer Bi mode register with the count source start bit = "1," the timer Bi overflow flag will be cleared to "0" at the next count timing of the count source. The timer Bi overflow flag is a read-only bit. Use the timer Bi interrupt request bit to detect the overflow timing. Do not use the timer Bi overflow flag for this detection. Figure 10.5.3 shows the operation example during the pulse period measurement, and Figure 10.5.4 shows the operation example during the pulse width measurement. 7902 Group User's Manual 10-21 TIMER B 10.5 Pulse period/pulse width measurement mode Count source Measurement pulse Transferred (undefined value) Reload register Counter Transfer timing Transferred (measured value) Timing at which counter is cleared to "000016" Count start bit Timer Bi interrupt request bit Cleared to "0" when interrupt request is accepted or cleared to "0" by software. Timer Bi overflow flag Counter is initialized by completion of measurement. Counter overflow. Note: The above applies when measurement is performed for an interval from one falling edge to the next falling edge of the measurement pulse. Fig. 10.5.3 Operation example during pulse period measurement Count source Measurement pulse Reload register Counter Transfer timing Transferred (undefined value) Transferred Transferred (measured (measured value) value) Transferred (measured value) Timing at which counter is cleared to "000016" Count start bit Timer Bi interrupt request bit Timer Bi overflow flag Cleared to "0" when interrupt request is accepted or cleared to "0" by software. Counter is initialized by completion of measurement. Counter overflow. Fig. 10.5.4 Operation example during pulse width measurement 10-22 7902 Group User's Manual TIMER B [Precautions for pulse period/pulse width measurement mode] [Precautions for pulse period/pulse width measurement mode] 1. A timer Bi interrupt request is generated by one of the following sources: Valid edge input of measured pulse Counter overflow When an overflow generates an interrupt request, the timer Bi overflow flag will be set to "1." 2. After reset, the timer Bi overflow flag is undefined. When a value is written to the timer Bi mode register with the count start bit = "1," this flag will be cleared to "0" at the next count timing of the count source. 3. An undefined value is transferred to the reload register at the first valid edge input after the count start. In this case, no timer Bi interrupt request will occur. 4. The counter value at count start is undefined. Accordingly, there is a possibility that a timer Bi interrupt request occurs by an overflow immediately after the count start. 5. If the contents of the measurement mode select bits are changed after the count start, the timer Bi interrupt request bit is set to "1." When the value, which has been set in these bits before, are written again, the timer Bi interrupt request bit will not change, that is to say, this bit retains this state. 6. When using timer B2, be sure to clear the timer B2 clock source select bit (bit 6 at address 63 16 ) to "0." 7. If the input signal to the TBiIN pin is affected by noise, etc., there is a possibility that the counter cannot perform the exact measurement. We recommend to verify, by software, that the measurement values are within a constant range. 7902 Group User's Manual 10-23 TIMER B [Precautions for pulse period/pulse width measurement mode] MEMORANDUM 10-24 7902 Group User's Manual CHAPTER 11 REAL-TIME OUTPUT 11.1 11.2 11.3 11.4 Overview Block description Setting of real-time output Real-time output operation REAL-TIME OUTPUT 11.1 Overview 11.1 Overview The real-time output function is used to change the output levels of several pins simultaneously at every period of the timer. Figure 11.1.1 shows the block diagram of real-time output per bit. The real-time output function has two operating modes described below. (1) Pulse mode 0 The 8-bit pulse output pins serve as two independent 4-bit outputs. Figure 11.1.2 shows the configuration of real-time output in the pulse mode 0. (2) Pulse mode 1 The 8-bit pulse output pins serve as a 2-bit and a 6-bit outputs. Figure 11.1.3 shows the configuration of real-time output in the pulse mode 1. Data bus AA AA AA AA AA AA AA Timer Aj underflow signal Pulse output data register j Bit i of port P5 direction register T D Q 1 Flip-flop P5i/RTP0k, P5i/RTP1k Port P5i latch 0 Waveform output select bit j * i = 0 to 7 * j = 0, 2 * k = 0 to 3 Fig. 11.1.1 Block diagram of real-time output per bit 11-2 7902 Group User's Manual REAL-TIME OUTPUT 11.1 Overview AA AA AAAA AA AA AAAA AA AA AA AA AA AA AAAA AA AA AAAA Pulse output data register 0 Data bus (even) b7 b0 Timer A0 a 1 a a a a DTQ T DQ T DQ DTQ Port P5i direction register P50/RTP00 P51/RTP01 P52/RTP02 P53/RTP03 Port P5i latch (i = 0 to 7) 0 Bit 0 of waveform output select bits Pulse output data register 1 b7 b0 Timer A2 T DQ DTQ P54/RTP10 P55/RTP11 P56/RTP12 P57/RTP13 a a a a T DQ T DQ Bit 1 of waveform output select bits Fig. 11.1.2 Configuration of real-time output in pulse mode 0 AA AA AA AA AA AA AAAA AA AA AAAA AA AA AA AA AA AA AAAA Pulse output data register 0 Data bus (even) b7 b0 Timer A0 T DQ T DQ a a P50/RTP00 P51/RTP01 Bit 0 of waveform output select bits Pulse output data register 1 b7 b0 Timer A1 a T DQ T DQ T DQ T DQ T DQ T DQ a a a a a a P52/RTP02 P53/RTP03 P54/RTP10 P55/RTP11 P56/RTP12 P57/RTP13 Port P5i direction register 1 Port P5i latch (i = 0 to 7) 0 Bit 1 of waveform output select bits Fig. 11.1.3 Configuration of real-time output in pulse mode 1 7902 Group User's Manual 11-3 REAL-TIME OUTPUT 11.2 Block description 11.2 Block description Registers relevant to the real-time output function are described below. 11.2.1 Real-time output control register Figure 11.2.1 shows the structure of the real-time output control register. b7 b6 b5 b4 b3 b2 b1 b0 Real-time output control register (Address A016) Bit 0 Bit name Function Waveform output select bits See the table below. 1 2 7 to 3 0 : Pulse mode 0 1 : Pulse mode 1 Pulse output mode select bit The value is "0" at reading. At reset R/W 0 RW 0 RW 0 RW 0 -- Note: When using pins P50 to P57 as pulse output pins of the real-time output function, be sure to set the corresponding bits of the port P5 direction register (address D 16) to "1." When using pins RTP1 0 to RTP13 , do not select the key input interrupt pins (KI0 to KI3 ) multiplexed with pins RTP10 to RTP13. (Refer to "CHAPTER 8. KEY INPUT INTERRUPT.") b1 b0 Pulse mode 0 P57/RTP13 P56/RTP12 P55/RTP11 P54/RTP10 Port P57/RTP13 P56/RTP12 P55/RTP11 P54/RTP10 Port P53/RTP03 P52/RTP02 P51/RTP01 P50/RTP00 P57/RTP13 P56/RTP12 P55/RTP11 P54/RTP10 P53/RTP03 P52/RTP02 P51/RTP01 P50/RTP00 P53/RTP03 P52/RTP02 P51/RTP01 P50/RTP00 Pulse mode 1 01 00 RTP P57/RTP13 P56/RTP12 P55/RTP11 P54/RTP10 RTP Port P53/RTP03 P52/RTP02 P51/RTP01 P50/RTP00 RTP RTP RTP Port P57/RTP13 P56/RTP12 P55/RTP11 P54/RTP10 RTP P53/RTP03 P52/RTP02 P51/RTP01 P50/RTP00 Port P57/RTP13 P56/RTP12 P55/RTP11 P54/RTP10 P53/RTP03 P52/RTP02 Port P57/RTP13 P56/RTP12 P55/RTP11 P54/RTP10 P53/RTP03 P52/RTP02 RTP P57/RTP13 P56/RTP12 P55/RTP11 P54/RTP10 P53/RTP03 P52/RTP02 Port P51/RTP01 P50/RTP00 RTP P51/RTP01 P50/RTP00 Port P51/RTP01 P50/RTP00 Port : This functions as a programmable I/O port pin. RTP : This functions as a pulse output pin. Fig. 11.2.1 Structure of real-time output control register 11-4 11 10 7902 Group User's Manual REAL-TIME OUTPUT 11.2 Block description 11.2.2 Pulse output data registers 0 and 1 Figure 11.2.2 shows the structures of the pulse output data registers 0 and 1. Each of data written into the pulse output data registers 0 and 1 is output from the corresponding pulse output pins at each underflow of timers A0 and A2. The bit position of the RTP02 and RTP03 pulse output data bits depends on the pulse mode. Before setting the pulse output data registers 0 and 1, be sure to set the pulse output mode select bit (bit 2 at address A016 ). b7 b6 b5 b4 b3 b2 b1 b0 Pulse output data register 0 (Address A216) Bit Bit name Function R/W Undefined WO Undefined WO 0 RTP00 pulse output data bit 1 RTP01 pulse output data bit 2 RTP02 pulse output data bit (Valid in pulse mode 0.) Undefined WO 3 RTP03 pulse output data bit (Valid in pulse mode 0.) Undefined WO Nothing is assigned. Undefined - 7 to 4 0 : "L" level output 1 : "H" level output At reset Note: When writing to this register, use the MOVM (MOVMB) instruction or STA (STAB, STAD) instruction. b7 b6 b5 b4 b3 b2 b1 b0 Pulse output data register 1 (Address A416) Bit Bit name 1, 0 Nothing is assigned. Function At reset R/W Undefined - Undefined WO 2 RTP02 pulse output data bit (Valid in pulse mode 1.) 3 RTP03 pulse output data bit (Valid in pulse mode 1.) Undefined WO 4 RTP10 pulse output data bit Undefined WO 5 RTP11 pulse output data bit Undefined WO 6 RTP12 pulse output data bit Undefined WO 7 RTP13 pulse output data bit Undefined WO 0 : "L" level output 1 : "H" level output Note: When writing to this register, use the MOVM (MOVMB) instruction or STA (STAB, STAD) instruction. Fig. 11.2.2 Structures of pulse output data registers 0 and 1 7902 Group User's Manual 11-5 REAL-TIME OUTPUT 11.2 Block description 11.2.3 Port P5 direction register The pulse output pins are multiplexed with port P5 pins. When using these pins as pulse output pins of the real-time output, be sure to set the corresponding bits of the port P5 direction register to "1" in order to set these port pins for the output mode. Figure 11.2.3 shows the relationship between the port P5 direction register and pulse output pins. b7 b6 b5 b4 b3 b2 b1 b0 Port P5 direction register (Address D16) Bit Functions Corresponding pin 0 Pin RTP00 (Pin TA0OUT) 1 Pin RTP01 (Pin TA0IN) 2 Pin RTP02 (Pin TA1OUT) At reset R/W 0 RW 0 RW 0 RW 0 RW 0 : Input mode 1 : Output mode When using this pin as a pulse output pin, be sure to set the corresponding bit to "1." 3 Pin RTP03 (Pin TA1IN) 4 Pin RTP10 (Pin TA2OUT/KI0) 0 RW 5 Pin RTP11 (Pin TA2IN/KI1) 0 RW 6 Pin RTP12 (Pin TA3OUT/KI2) 0 RW 7 Pin RTP13 (Pin TA3IN/KI3) 0 RW Notes 1: When any of these bits becomes "0," the corresponding pin becomes an input port pin (floating state), regardless of the waveform output select bits (bits 0 and 1 at address A016). 2: ( ) shows the I/O pin of another internal peripheral device which is multiplexed. Fig. 11.2.3 Relationship between port P5 direction register and pulse output pins After reset, the port P5 pins are floated since these pins are placed in the input mode. The output levels of the pulse output pins are undefined until timer A0 or A2 underflows first after data for the timer is written. It is because the pulse output data registers 0 and 1 are undefined after reset. When avoiding these states, be sure to follow the procedure "Processing of avoiding undefined output before starting pulse output" in Figures 11.3.1 and 11.3.2. When reading the port P5 register (address B 16), the output values of the pulse output pins can be read out. 11.2.4 Timers A0 and A2 Data written into the pulse output registers 0 and 1 is output from the corresponding pulse output pins at each underflow of timer A0 or A2. Refer to section "9.3 Timer mode" for the setting of timers A0 and A2. 11-6 7902 Group User's Manual REAL-TIME OUTPUT 11.3 Setting of real-time output 11.3 Setting of real-time output Figures 11.3.1 to 11.3.3 show an initial setting example for registers relevant to the real-time output function. Note that when using interrupts, set up to enable the interrupts. For details, refer to "CHAPTER 7. INTERRUPTS." Processing of avoiding undefined output before starting pulse output (Note) b7 b0 Port P5 register (Address B16) RTP00 RTP01 RTP02 RTP03 RTP10 RTP11 RTP12 RTP13 Note: This processing can be neglected when the system is not affected by the undefined output. Set the initial output level of real-time output. 0 : "L" level 1 : "H" level AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA Setting of port P5 direction register b7 b0 Port P5 direction register (Address D16) RTP00 RTP01 RTP02 RTP03 RTP10 RTP11 RTP12 RTP13 Set the bits corresponding to the selected pulse output pins to "1." Setting of pulse output mode b7 b0 Real-time output control register (Address A016) 0 0 P50-P57 pins serve as programmable I/O port pins. Pulse output mode select bit 0 : Pulse mode 0 1 : Pulse mode 1 AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA When pulse mode 0 is selected When pulse mode 1 is selected Setting of output data b7 Setting of output data b0 b7 Pulse output data register 0 (Address A216) RTP00 RTP01 RTP02 RTP03 b0 0 : "L" level 1 : "H" level Pulse output data register 1 (Address A416) RTP10 RTP11 RTP12 RTP13 Pulse output data register 0 (Address A216) RTP00 RTP01 b7 b7 b0 0 : "L" level 1 : "H" level : It may be either "0" or "1." 0 : "L" level 1 : "H" level : It may be either "0" or "1." b0 Pulse output data register 1 (Address A416) RTP02 RTP03 0 : "L" level RTP10 1 : "H" level RTP11 RTP12 RTP13 Continue to "Figure 11.3.2" Fig. 11.3.1 Initial setting example for registers relevant to real-time output (1) 7902 Group User's Manual 11-7 REAL-TIME OUTPUT 11.3 Setting of real-time output From preceding "Figure 11.3.1" A AAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA Processing of avoiding undefined output before starting pulse output (Note) b7 b0 0 b7 0 0 0 Timer A clock division select register (Address 4516) b0 0 0 0 0 0 0 Timer A0 mode register (Address 5616) Timer A2 mode register (Address 5816) Selection of count source f2 (b15) b7 (b8) b0 b7 0016 b0 Timer A0 register (Addresses 4716, 4616) Timer A2 register (Addresses 4B16, 4A16) 0016 Set to "000016." b7 b0 0 0 0 0 Timer A0 interrupt control register (Address 7516) Timer A2 interrupt control register (Address 7716) Interrupt disabled Interrupt request bit b7 b0 Count start register (Address 4016) Timer A0 count start bit 1 : Start counting Timer A2 count start bit When timer A0 or A2 underflows, the contents of the pulse output data register 0 or 1 are output from the flip-flop. b7 b0 Count start register (Address 4016) Timer A0 count start bit 0 : Stop counting Timer A2 count start bit Note: This processing can be neglected when the system is not affected by the undefined output. Setting of timers A0 and A2 b7 b0 Timer A clock division select register (Address 4516) Timer A clock division select bits See Table 9.2.3. b7 b0 0 0 0 0 0 0 Timer A0 mode register (Address 5616) Timer A2 mode register (Address 5816) Count source select bits See Table 9.2.3. (b15) b7 (b8) b0 b7 b0 Timer A0 register (Addresses 4716, 4616) Timer A2 register (Addresses 4B6, 4A16) Can be set to "000016" to "FFFF16" (n) b7 b0 0 Timer A0 interrupt control register (Address 7516) Timer A2 interrupt control register (Address 7716) Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. Interruput request bit Continue to "Figure 11.3.3" Fig. 11.3.2 Initial setting example for registers relevant to real-time output (2) 11-8 7902 Group User's Manual REAL-TIME OUTPUT 11.3 Setting of real-time output Continue to "Figure 11.3.2" When pulse mode 0 is selected When pulse mode 1 is selected AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAA AAA AAA Selecting real-time output port b7 Selecting real-time output port b0 0 b7 Real-time output control register (Address A016) b0 1 Waveform output select bits Real-time output control register (Address A016) Waveform output select bits b1 b0 b1 b0 0 1 : RTP00-RTP03 1 0 : RTP10-RTP13 1 1 : RTP00-RTP03 and RTP10-RTP13 0 1 : RTP00, RTP01 1 0 : RTP02, RTP03 and RTP10-RTP13 1 1 : RTP00-RTP03 and RTP10-RTP13 Pulse mode 0 Pulse mode 1 Setting count start bit to "1" b7 b0 Count start register (Address 4016) Timer A0 count start bit Timer A2 count start bit Pulse output starts after overflow of timer A0 or A2. Fig. 11.3.3 Initial setting example for registers relevant to real-time output (3) 7902 Group User's Manual 11-9 REAL-TIME OUTPUT 11.4 Real-time output operation 11.4 Real-time output operation When the timer Ai (i = 0, 2) count start bit is set to "1," the counter starts counting of a count source. The contents of pulse output data register i are output from the corresponding pulse output pins at each underflow of timer Ai. The timer is reloaded with the contents of the reload register and continues counting. The timer Ai interrupt request bit is set to "1" when the counter underflows in . The interrupt request bit retains "1" until the interrupt request is accepted or it is cleared by software. Write the next output data into the pulse output data register i during a timer Ai interrupt routine (or after the recognition of a timer Ai interrupt request occurrence.) Figure 11.4.1 shows an example of real-time output operation. Counter contents (Hex.) 1 Starts counting Starts pulse outputting 000316 000016 Contents of bits 3 to 0 of pulse output data register 0 1 Undefined 1 00112 RTP03 output Undefined 2 RTP02 output Undefined 2 RTP01 output Undefined 2 RTP00 output Undefined 2 Timer A0 interrupt request bit 1 01102 3 1 11002 3 1 10012 3 1 00112 3 3 1 : Written by software 2 : When avoiding undefined output in these terms (in other words, when stabilizing these output level), be sure to follow the procedure "Processing of avoiding undefined output before starting pulse output" in Figures 11.3.1 and 11.3.2. 3 : Cleared to "0" by an interrupt request acceptance or cleared by software. The above applies when the following conditions are satisfied: *Pulse mode 0 selected *RTP00 to RTP03 selected *Timer A0 register set value (n) = 000316 Fig. 11.4.1 Example of real-time output operation 11-10 7902 Group User's Manual CHAPTER 12 SERIAL I/O 12.1 Overview 12.2 Block description 12.3 Clock synchronous serial I/O mode [Precautions for clock synchronous serial I/O mode] 12.4 Clock asynchronous serial I/O (UART) mode [Precautions for clock asynchronous serial I/O (UART) mode] SERIAL I/O 12.1 Overview 12.1 Overview Serial I/O consists of 2 channels: UART0 and UART1. They each have a transfer clock generating timer for the exclusive use of them and can operate independently. UARTi (i = 0 and 1) has the following 2 operating modes: (1) Clock synchronous serial I/O mode Transmitter and receiver use the same clock as the transfer clock. Transfer data has a length of 8 bits. (2) Clock asynchronous serial I/O (UART) mode Transfer rate and transfer data format can arbitrarily be set. The user can select one transfer data length from the following: 7 bits, 8 bits, and 9 bits. Figure 12.1.1 shows the transfer data formats in each operating mode. Clock synchronous serial I/O mode Transfer data length of 8 bits (LSB first) Transfer data length of 8 bits (MSB first) UART mode Transfer data length of 7 bits Transfer data length of 8 bits Transfer data length of 9 bits Fig. 12.1.1 Transfer data formats in each operating mode 12-2 7902 Group User's Manual SERIAL I/O 12.2 Block description 12.2 Block description Figure 12.2.1 shows the block diagram of serial I/O. Registers relevant to serial I/O are described below. AA AA 0 0 0 0 0 0 Data bus (odd) AA AA AA AA Data bus (even) Bit converter 0 D8 RxDi D7 D6 D5 D4 D3 D2 D1 D0 UARTi receive buffer register UARTi receive register f2 BRGi 1 / (n+1) f16 f64 f512 UART 1/16 BRG count source select bits Clock synchronous Clock synchronous Clock synchronous (internal clock selected) Transfer clock Transmit control circuit Transfer clock UART 1/16 1/2 Receive control circuit Clock synchronous (internal clock selected) UARTi transmit register Clock synchronous (external clock selected) D8 AA AA AA TxDi UARTi transmit buffer register D7 D6 D5 D4 D3 D2 D1 D0 Bit converter CLKi CTSi/CLKi Data bus (odd) CTSi CTSi/RTSi Data bus (even) n: Values set in UARTi baud rate register (BRGi) Fig. 12.2.1 Block diagram of serial I/O 7902 Group User's Manual 12-3 SERIAL I/O 12.2 Block description 12.2.1 UARTi transmit/receive mode register Figure 12.2.2 shows the structure of UARTi transmit/receive mode register. b7 b6 b5 b4 b3 b2 b1 b0 UART0 transmit/receive mode register (Address 3016) UART1 transmit/receive mode register (Address 3816) Bit 0 Bit name Function Serial I/O mode select bits 1 2 At reset R/W 0 0 0 : Serial I/O is invalid. (P8 functions as programmable I/O port pins.) 0 0 1 : Clock synchronous serial I/O mode 010: 0 1 1 : Do not select. 1 0 0 : UART mode (Transfer data length = 7 bits) 1 0 1 : UART mode (Transfer data length = 8 bits) 1 1 0 : UART mode (Transfer data length = 9 bits) 1 1 1 : Do not select. 0 RW 0 RW 0 RW b2 b1 b0 3 Internal/External clock select bit 0 : Internal clock 1 : External clock 0 RW 4 Stop bit length select bit (Valid in UART mode) (Note) Odd/Even parity select bit (Valid in UART mode when parity enable bit = "1.") (Note) Parity enable bit (Valid in UART mode) (Note) 0 : One stop bit 1 : Two stop bits 0 RW 0 : Odd parity 1 : Even parity 0 RW 0 : Parity disabled 1 : Parity enabled 0 RW Sleep select bit (Valid in UART mode) 0 : Sleep mode terminated (Invalid) 1 : Sleep mode selected 0 RW 5 6 7 (Note) Note: Bits 4 to 6 are invalid in the clock synchronous serial I/O mode. (They may be either "0" or "1.") Additionally, fix bit 7 to "0." Fig. 12.2.2 Structure of UARTi transmit/receive mode register 12-4 7902 Group User's Manual SERIAL I/O 12.2 Block description (1) Serial I/O mode select bits (bits 0 to 2) These bits select a UARTi's operating mode. (2) Internal/External clock select bit (bit 3) Clock synchronous serial I/O mode By clearing this bit to "0" in order to select an internal clock, the clock which is selected with the BRG count source select bits (bits 0 and 1 at addresses 34 16 , 3C16) becomes the count source of the BRGi. (Refer to section "12.2.6 UARTi baud rate register (BRGi).") The BRGi's output divided by 2 becomes the transfer clock. Additionally, the transfer clock is output from the CLK i pin. By setting this bit to "1" in order to select an external clock, the clock input to the CLK i pin becomes the transfer clock. UART mode By clearing this bit to "0" in order to select an internal clock, the clock which is selected with the BRG count source select bits (bits 0 and 1 at addresses 34 16 , 3C16) becomes the count source of the BRGi. (Refer to section "12.2.6 UARTi baud rate register (BRGi).") Then, the CLK i pin functions as a programmable I/O port pin. By setting this bit to "1" in order to select an external clock, the clock input to the CLK i pin becomes the count source of BRGi. Always in the UART mode, the BRGi's output divided by 16 becomes the transfer clock. (3) Stop bit length select bit, Odd/Even parity select bit, Parity enable bit (bits 4 to 6) Refer to section "12.4.2 Transfer data format." (4) Sleep select bit (bit 7) Refer to section "12.4.8 Sleep mode." 7902 Group User's Manual 12-5 SERIAL I/O 12.2 Block description 12.2.2 UARTi transmit/receive control register 0 Figure 12.2.3 shows the structure of UARTi transmit/receive control register 0. b7 b6 b5 b4 b3 b2 b1 b0 UART0 transmit/receive control register (Address 3416) UART1 transmit/receive control register (Address 3C16) Bit 0 Bit name BRG count source select bits 1 Function At reset R/W 0 0 : Clock f2 0 1 : Clock f16 1 0 : Clock f64 1 1 : Clock f512 0 RW 0 RW b1 b0 2 CTS/RTS function select bit (Note 1) 0 : The CTS function is selected. 1 : The RTS function is selected. 0 RW 3 Transmit register empty flag 0 : Data is present in the transmit register. (Transmission is in progress.) 1 : No data is present in the transmit register. (Transmission is completed.) 1 RO 4 CTS/RTS enable bit 0 : The CTS/RTS function is enabled. 1 : The CTS/RTS function is disabled. 0 RW 5 UARTi receive interrupt mode 0 : Reception interrupt 1 : Reception error interrupt select bit CLK polarity select bit 0 : At the falling edge of the transfer clock, transmit (This bit is used in the clock data is output; at the rising edge of the transfer clock, receive data is input. synchronous serial I/O mode.) When not in transferring, pin CLKi's level is "H." (Note 2) 1 : At the falling edge of the transfer clock, transmit data is output; at the falling edge of the transfer clock, receive data is input. When not in transferring, pin CLKi's level is "L." 0 RW 0 RW 0 : LSB (Least Significant Bit) first Transfer format select bit (This bit is used in the clock 1 : MSB (Most Significant Bit) first synchronous serial I/O mode.) (Note 2) 0 RW 6 7 Notes 1: Valid when the CTS/RTS enable bit (bit 4) is "0" and CTSi/RTS i separate select bit (bit 0 or 1 at address AC16) is "0." 2: Fix these bits to "0" in the UART mode or when serial I/O is disabled. Fig. 12.2.3 Structure of UARTi transmit/receive control register 0 12-6 7902 Group User's Manual SERIAL I/O 12.2 Block description (1) BGR count source select bit (bits 0 and 1) Refer to section "12.2.1 (2) Internal/External clock select bit." ____ ____ (2) CTS/RTS function select ____ bit (bit 2) ____ Refer to section "12.2.10 CTS/RTS function." (3) Transmit register empty flag (bit 3) This flag is cleared to "0" when the UARTi transmit buffer register's contents have been transferred to the UARTi transmit register. When transmission has been completed and the UARTi transmit register becomes empty, this flag is set to "1." ____ ____ (4) CTS/RTS enable bit (bit 4) ____ ____ Refer to section "12.2.10 CTS/RTS function." (5) UARTi receive interrupt mode select bit (bit 5) Refer to section "12.2.7 (2) Interrupt request bit." (6) CLK polarity select bit (bit 6) Refer to section "12.3.1 (3) Polarity of transfer clock." (7) Transfer format select bit (bit 7) Refer to section "12.3.2 Transfer data format." 7902 Group User's Manual 12-7 SERIAL I/O 12.2 Block description 12.2.3 UARTi transmit/receive control register 1 Figure 12.2.4 shows the structure of UARTi transmit/receive control register 1. b7 b6 b5 b4 b3 b2 b1 b0 UART0 transmit/receive control register 1 (Address 3516 ) UART1 transmit/receive control register 1 (Address 3D16) Bit Bit name Function R/W 0 Transmit enable bit 0 : Transmission disabled 1 : Transmission enabled 0 RW 1 Transmit buffer empty flag 0 : Data is present in the transmit buffer register 1 : No data is present in the transmit buffer register 1 RO 2 Receive enable bit 0 : Reception disabled 1 : Reception enabled 0 RW 3 Receive complete flag 0 : No data is present in the receive buffer register 1 : Data is present in the receive buffer register 0 RO 4 Overrun error flag 0 : No overrun error 1 : Overrun error detected 0 RO 5 Framing error flag (Valid in UART mode) (Note) 0 : No framing error 1 : Framing error detected 0 RO 6 Parity error flag (Valid in UART mode) (Note) 0 : No parity error 1 : Parity error detected 0 RO 7 Error sum flag (Valid in UART mode) (Note) 0 : No error 1 : Error detected 0 RO Note: Bits 5 to 7 are invalid in the clock synchronous serial I/O mode. Fig. 12.2.4 Structure of UARTi transmit/receive control register 1 12-8 At reset 7902 Group User's Manual SERIAL I/O 12.2 Block description (1) Transmit enable bit (bit 0) By setting this bit to "1," UARTi enters the transmission-enabled state. By clearing this bit to "0" during transmission, UARTi enters the transmission-disabled state after the transmission which was in progress at that time is completed. (2) Transmit buffer empty flag (bit 1) This flag is set to "1" when data set in the UARTi transmit buffer register has been transferred from the UARTi transmit buffer register to the UARTi transmit register. This flag is cleared to "0" when data has been set in the UARTi transmit buffer register. (3) Receive enable bit (bit 2) By setting this bit to "1," UARTi enters the reception-enabled state. By clearing this bit to "0" during reception, UARTi quits the reception immediately and enters the reception-disabled state. (4) Receive complete flag (bit 3) This flag is set to "1" when data has been ready in the UARTi receive register and that has been transferred to the UARTi receive buffer register (i.e., when reception is completed). This flag is cleared to "0" in one of the following cases: * When the low-order byte of the UARTi receive buffer register has been read out * When the receive enable bit (bit 2) has been cleared to "0" (5) Overrun error flag (bit 4) Refer to section "12.3.7 Processing on detecting overrun error" and "12.4.7 Processing on detecting error." (6) Framing error flag, Parity error flag, Error sum flag (bits 5 to 7) Refer to section "12.4.7 Processing on detecting error." 7902 Group User's Manual 12-9 SERIAL I/O 12.2 Block description 12.2.4 UARTi transmit register and UARTi transmit buffer register Figure 12.2.5 shows the block diagram for the transmitter; Figure 12.2.6 shows the structure of UARTi transmit buffer register. Data bus (odd) AA AA AA Data bus (even) D8 D7 D6 D5 D4 D3 D2 D1 SP : Stop bit PAR : Parity bit Parity enabled 2SP SP SP 7-bit UART 9-bit UART Clock sync. D0 UARTi transmit buffer register 8-bit UART 9-bit UART Clock sync. UART TxDi PAR 1SP Parity disabled Clock sync. 8-bit UART 7-bit UART UARTi transmit register 0 Fig. 12.2.5 Block diagram for transmitter (b15) b7 UART0 transmit buffer register (Addresses 3316, 3216) UART1 transmit buffer register (Addresses 3B16, 3A16) (b8) b0 b7 Function Bit At reset R/W Transmit data is set. Undefined WO 15 to 9 Nothing is assigned. Undefined -- 8 to 0 Note: Use the MOVM (MOVMB) or STA (STAB, STAD) instruction for writing to this register. Fig. 12.2.6 Structure of UARTi transmit buffer register 12-10 b0 7902 Group User's Manual SERIAL I/O 12.2 Block description Transmit data is set into the UARTi transmit buffer register. Set the transmit data into the low-order byte of this register when the microcomputer operates in the clock synchronous serial I/O mode or when a 7bit or 8-bit length of transfer data is selected in the UART mode. When a 9-bit length of transfer data is selected in the UART mode, set the transmit data into the UARTi transmit buffer register as follows: *Bit 8 of the transmit data into bit 0 of high-order byte of this register. *Bits 7 to 0 of the transmit data into the low-order byte of this register. The transmit data which has been set in the UARTi transmit buffer register is transferred to the UARTi transmit register when the transmission conditions are satisfied, and then it is output from the TxDi pin synchronously with the transfer clock. The UARTi transmit buffer register becomes empty when the data set in the UARTi transmit buffer register has been transferred to the UARTi transmit register. Accordingly, the user can set the next transmit data. When the "MSB first" is selected in the clock synchronous serial I/O mode, bit position of set data is reversed, and then the data of which bit position was reversed will be written, as a transmit data, into the UARTi transmit buffer register. (Refer to section "12.3.2 Transfer data format.") Transmit operation itself is the same whichever format is selected, "LSB first" or "MSB first." When quitting the transmission which is in progress and setting the UARTi transmit buffer register again, follow the procedure described bellow: Clear the serial I/O mode select bits (bits 2 to 0 at addresses 30 16, 3816 ) to "000 2" (serial I/O disabled). Set the serial I/O mode select bits again. Set the transmit enable bit (bit 0 at addresses 35 16 , 3D16 ) to "1" (transmission enabled) and set transmit data in the UARTi transmit buffer register. 7902 Group User's Manual 12-11 SERIAL I/O 12.2 Block description 12.2.5 UARTi receive register and UARTi receive buffer register Figure 12.2.7 shows the block diagram of the receiver; Figure 12.2.8 shows the structure of UARTi receive buffer register. 0 0 0 SP : Stop bit PAR : Parity bit SP SP 1SP 0 Parity enabled 2SP RxDi AA AA A A A A Data bus (odd) Data bus (even) 0 0 UART 0 D8 9-bit UART D7 D6 D5 AA AA AA AA D4 D3 D2 D1 UARTi receive buffer register D0 8-bit UART 9-bit UART Clock sync. PAR Parity disabled Clock sync. 7-bit UART 8-bit UART Clock sync. 7-bit UART UARTi receive register Fig. 12.2.7 Block diagram of receiver UART0 transmit buffer register (Addresses 3716, 3616) UART1 transmit buffer register (Addresses 3F16, 3E16) Function Bit 8 to 0 (b15) b7 Receive data is read out from here. 15 to 9 The value is "0" at reading. Fig. 12.2.8 Structure of UARTi receive buffer register 12-12 7902 Group User's Manual (b8) b0 b7 b0 At reset R/W Undefined RO 0 -- SERIAL I/O 12.2 Block description The UARTi receive register is used to convert serial data, which is input to the RxDi pin, into parallel data. This register takes in the signal input to the RxD i pin, bit by bit, synchronously with the transfer clock. The UARTi receive buffer register is used to read out receive data. When reception has been completed, the receive data taken in the UARTi receive register is automatically transferred to the UARTi receive buffer register. Note that the contents of the UARTi receive buffer register is updated when the next data has been ready in the UARTi receive register before the data transferred to the UARTi receive buffer register is read out. (i.e., an overrun error occurs.) When "MSB first" is selected in the clock synchronous serial I/O mode, bit position of data in the UARTi receive buffer register is reversed, and then the data of which bit position was reversed will be read out as transmit data. (Refer to section "12.3.2 Transfer data format.") Receive operation itself is the same whichever format is selected, "LSB first" or "MSB first." The UARTi receive buffer register is initialized by setting the receive enable bit (bit 2 at addresses 3516 , 3D 16 ) to "1" after clearing it to "0." Figure 12.2.9 shows the contents of the UARTi receive buffer register at reception completed. Low-order byte (addresses 3616, 3E16) High-order byte (addresses 3716, 3F16) b7 UART mode (Transfer data length : 9 bits) Clock synchronous serial I/O mode, UART mode (Transfer data length : 8 bits) UART mode (Transfer data length : 7 bits) 0 b0 0 0 0 0 0 b7 b0 0 Receive data (9 bits) 0 0 0 0 0 0 0 Same value as bit 7 in low-order byte 0 0 0 0 0 0 Receive data (8 bits) 0 Same value as bit 6 in low-order byte Receive data (7 bits) Fig. 12.2.9 Contents of UARTi receive buffer register at reception completed 7902 Group User's Manual 12-13 SERIAL I/O 12.2 Block description 12.2.6 UARTi baud rate register (BRGi) The UARTi baud rate register (BRGi) is an 8-bit timer exclusively used for UARTi to generate a transfer clock. It has a reload register. Assuming that the value set in the BRGi is "n" (n = "0016 " to "FF16 "), the BRGi divides the count source frequency by (n + 1). In the clock synchronous serial I/O mode, the BRGi is valid when an internal clock is selected, and the BRGi's output divided by 2 becomes the transfer clock. In the UART mode, the BRGi is always valid, and the BRGi's output divided by 16 becomes the transfer clock. The data written to the BRGi is written to both the timer and the reload register whichever transmission/ reception is in progress or not. Accordingly, writing to these register must be performed while transmission/ reception halts. Figure 12.2.10 shows the structure of the UARTi baud rate register (BRGi); Figure 12.2.11 shows the block diagram of transfer clock generating section. b7 UART0 baud rate register (BRG0) (Address 3116) UART1 baud rate register (BRG1) (Address 3916) b0 Bit Function At reset R/W 7 to 0 Can be set to "0016" to "FF16." Assuming that the set value = n, BRGi divides the count source frequency by (n + 1). Undefined WO Note: Writing to this register must be performed while the transmission/reception halts. Use the MOVM (MOVMB) or STA (STAB, STAD) instruction for writing to this register. Fig. 12.2.10 Structure of UARTi baud rate register (BRGi) <Clock synchronous serial I/O mode> fi 1/2 BRGi fEXT Transmit control circuit Transfer clock for transmit operation Receive control circuit Transfer clock for receive operation <UART mode> fi fEXT 1/16 Transmit control circuit Transfer clock for transmit operation 1/16 Receive control circuit Transfer clock for receive operation BRGi fi : Clock selected by BRG count source select bits (f2, f16, f64, or f512) fEXT : Clock input to CLKi pin (external clock) Fig. 12.2.11 Block diagram of transfer clock generating section 12-14 7902 Group User's Manual SERIAL I/O 12.2 Block description 12.2.7 UARTi transmit interrupt control and UARTi receive interrupt control registers When using UARTi, 2 types of interrupts (UARTi transmit and UARTi receive interrupts) can be used. Each interrupt has its corresponding interrupt control register. Figure 12.2.12 shows the structure of UARTi transmit interrupt control and UARTi receive interrupt control registers. For details about these interrupts, refer to "CHAPTER 7. INTERRUPTS." For the UARTi receive interrupt, a receive or receive error interrupt can be selected by the UARTi receive interrupt mode selected bit (bit 5 at addresses 34 16 , 3C16 ). UART0 transmit interrupt control registers (Address 71 16) UART0 receive interrupt control registers (Address 7216) UART1 transmit interrupt control registers (Address 73 16) UART1 receive interrupt control registers (Address 7416) Bit Bit name 0 Interrupt priority level select bits 1 2 3 Interrupt request bit 7 to 4 Nothing is assigned. b7 b6 b5 b4 b3 b2 b1 b0 Function b2 b1b0 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0 : No interrupt requested 1 : Interrupt requested At reset R/W 0 RW 0 RW 0 RW 0 RW (Note) Undefined -- Note: When writing to this bit, use the MOVM (MOVMB) or STA (STAB, STAD) instruction. Fig. 12.2.12 Structure of UARTi transmit interrupt control and UARTi receive interrupt control registers 7902 Group User's Manual 12-15 SERIAL I/O 12.2 Block description (1) Interrupt priority level select bits (bits 0 to 2) These bits select a priority level of the UARTi transmit interrupt or UARTi receive interrupt. When using UARTi transmit/receive interrupts, select one of the priority levels (1 to 7). When a UARTi transmit/receive interrupt request occurs, its priority level is compared with the processor interrupt priority level (IPL). The requested interrupt is enabled only when its priority level is higher than the IPL. (However, this applies when the interrupt disable flag (I) = "0.") To disable UARTi transmit/ receive interrupts, be sure to set these bits to "000 2" (level 0). (2) Interrupt request bit (bit 3) The UARTi transmit interrupt request bit is set to "1" when data has been transferred from the UARTi transmit buffer register to the UARTi transmit register. The UARTi receive interrupt request bit functions as below: When receive interrupt is selected (bit 5 = 0 at addresses 3416 , 3C16 ) The UARTi receive interrupt request bit is set to "1" when data has been transferred from the UARTi receive register to the UARTi receive buffer register. (However, the UARTi receive interrupt request bit does not change when an overrun error has occurred.) When receive error interrupt is selected (bit 5 = 1 at addresses 3416 , 3C 16) The UARTi receive interrupt request bit is set to "1" when an error (an overrun error in the clock synchronous serial I/O mode; an overrun error, framing error, or parity error in UART mode) has occurred. Each interrupt request bit is automatically cleared to "0" when its corresponding interrupt request has been accepted. This bit can be set to "1" or cleared to "0" by software. 12-16 7902 Group User's Manual SERIAL I/O 12.2 Block description 12.2.8 Serial I/O pin control register Figure 12.2.13 shows the structure of the seral I/O pin control register. b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O pin control register (Address AC16) Bit Function Bit name At reset R/W 0 CTS0/RTS0 separate select bit (Note) 0 : CTS0/RTS0 are used together. 1 : CTS0/RTS0 are separated. 0 RW 1 CTS1/RTS1 separate select bit 0 : CTS1/RTS1 are used together. 1 : CTS1/RTS1 are separated. 0 RW (Note) 2 TxD0/P83 switch bit 0 : Functions as TxD0. 1 : Functions as P83. 0 RW 3 TxD1/P87 switch bit 0 : Functions as TxD1. 1 : Functions as P87. 0 RW 0 -- 7 to 4 The value is "0" at reading. Note: Valid when the CTS/RTS enable bit (bit 4 at addresses 3416 and 3C16) is "0." Fig. 12.2.13 Structure of serial I/O pin control register (1) CTS 0/RTS0 separate select bit (bit 0) Refer to section "12.2.10 CTS/RTS function." (2) CTS 1/RTS1 separate select bit (bit 1) Refer to section "12.2.10 CTS/RTS function." (3) TxD 0/P8 3 switch bit (bit 2) When this bit is set to "1," the TxD 0 pin functions as a programmable I/O port pin (P8 3). When only reception is performed in the clock synchronous serial I/O mode, the TxD 0 pin can be used as the P8 3 pin. When performing transmission, be sure to clear this bit to "0." (4) TxD 1/P8 7 switch bit (bit 3) When this bit is set to "1," the TxD 1 pin functions as a programmable I/O port pin (P8 7). When only reception is performed in the clock asynchronous serial I/O mode, the TxD1 pin can be used as the P8 7 pin. When preforming transmission, be sure to clear this bit to "0." 7902 Group User's Manual 12-17 SERIAL I/O 12.2 Block description 12.2.9 Port P8 direction register I/O pins for serial I/O are multiplexed with port P8 pins. When using pins P8 1, P8 2, P85, and P86 as serial I/O's input pins (CTSi, RxD i), clear the corresponding bits of the port P8 direction register to "0" in order to set these pins for the input mode. When using these pins as other serial I/O's pins (CTSi/RTSi, CLKi, TxD i), these pins are forcibly set as I/O pins for serial I/O regardless of the port P8 direction register's contents. Figure 12.2.14 shows the relationship between the port P8 direction register and serial I/O's I/O pins. For details, refer to the description of each operating mode. b7 b6 b5 b4 b3 b2 b1 b0 Port P8 direction register (Address 1416) Bit Corresponding pin name Function At reset R/W 0 RW 0 RW 0 RW 0 RW 0 RW 0 Pin CTS0/RTS0 (Pin DA2/INT3) 1 Pin CTS0/CLK0 2 Pin RxD0 3 Pin TxD0 4 Pin CTS1/RTS1 (Pin INT4) 5 Pin CTS1/CLK1 0 RW 6 Pin RxD1 0 RW 7 Pin TxD1 0 RW 0 : Input mode 1 : Output mode When using pins P8 1, P82, P85, and P86 as serial I/O's input pins (CTS 0, RxD 0, CTS1, RxD 1), clear the corresponding bits to "0." Note: ( ) shows the I/O pin of another internal peripheral device which is multiplexed. Fig. 12.2.14 Relationship between port P8 direction register and serial I/O's I/O pins 12-18 7902 Group User's Manual SERIAL I/O 12.2 Block description 12.2.10 CTS/RTS function When the CTS function is selected, the signal input to the CTS i pin must be at "L" level. (This is one of the transmit conditions.) When the RTS function is selected, the RTS i pin outputs the following signals: (1) Clock synchronous serial I/O mode When the receive enable bit (bit 2 at addresses 35 16 , 3D 16) = "0" (reception disabled), the RTS i pin outputs "H" level. When the receive enable bit = "0" (reception disabled), the RTS i pin outputs "L" level by setting the receive enable bit to "1," or by reading the low-order byte of the UARTi receive buffer register. When the receive enable bit = "1" (continuously reception), the RTSi pin outputs "L" level by reading the low-order byte of the UARTi receive buffer register. When reception has started, the RTS i pin outputs "H" level. When an internal clock is selected (bit 3 at addresses 3016, 3816 = "0"), do not select the RTS function because the RTS output is undefined. (2) UART mode When the receive enable bit (bit 2 at addresses 35 16 , 3D 16) = "0" (reception disabled), the RTS i pin outputs "H" level. When the receive enable bit = "0" (reception disabled), the RTS i pin outputs "L" level by setting the receive enable bit to "1," or by reading the low-order byte of the UARTi receive buffer register. When the receive enable bit = "1" (continuously reception), the RTSi pin outputs "L" level by reading the low-order byte of the UARTi receive buffer register. When reception has started, the RTS i pin outputs "H" level. Selection of the CTS/RTS function depends on the following bits. *CTS/RTS function select bit (bit 2 at addresses 34 16 , 3C16 : see Figure 12.2.3.) *CTS/RTS enable bit (bit 4 at addresses 34 16, 3C 16: see Figure 12.2.3.) *CTS 0/RTS0 separate select bit (bit 0 at address AC 16: see Figure 12.2.13.) *CTS 1/RTS1 separate select bit (bit 1 at address AC 16: see Figure 12.2.13.) Table 12.2.1 lists the selection of the CTS/RTS function. Table 12.2.1 Selection of CTS/RTS function Functions CTS/RTS CTSi/RTS i CTS/RTS enable bit separate select bit function select bit P80/CTS0/RTS0 pin (Note 1) P81/CTS0/CLK0 pin P84/CTS1/RTS1 pin P85/CTS1/CLK1 pin P81 or CLK0 P85 or CLK1 0 CTS 0 CTS 1 0 0 P81 or CLK0 P85 or CLK1 1 RTS 0 RTS 1 1 CTS0 (Notes 2, 3) CTS1 (Notes 2, 3) RTS 0 RTS 1 1 P81 or CLK0 P85 or CLK1 P8 0 P8 4 : It may be either "0" or "1." Notes 1: When using the CTS0/RTS0 pin, be sure that the D-A 2 output enable bit (bit 2 at address 96 16 ) = "0" (output disabled). 2: When using the P8 1 or P85 pin as the CTS pin, be sure to clear the corresponding bit of the port P8 direction register to "0." 3: When CTSi/RTS i separation is selected, the CLKi pin cannot be used. Accordingly, CTS i/RTS i cannot be separated in the clock synchronous serial I/O mode. When separating CTS i/RTS i in UART mode, be sure to select an internal clock. 7902 Group User's Manual 12-19 SERIAL I/O 12.3 Clock synchronous serial I/O mode 12.3 Clock synchronous serial I/O mode Table 12.3.1 lists the performance overview in the clock synchronous serial I/O mode, and Table 12.3.2 lists the functions of I/O pins in this mode. Table 12.3.1 Performance overview in clock synchronous serial I/O mode Item Functions Transfer data format Transfer data has a length of 8 bits. LSB first or MSB first can be selected by software. Transfer rate When selecting internal clock BRGi's output divided by 2 When selecting external clock Transmit/Receive control Maximum 5 Mbps CTS function or RTS function can be selected by software. Table 12.3.2 Functions of I/O pins in clock synchronous serial I/O mode Pin name TxD i (P83, P87) Method of selection Functions Serial data output pin -- (Dummy data is output when performing only reception.) (Note) Programmable I/O port pin TxD 0/P83 or TxD 1/P87 switch bit = "1" RxD i (P82, P86) Serial data input pin Port P8 direction register's corresponding bit = "0" (Can be used as an I/O port pin when performing only transmission.) CLK i (P81, P85) Transfer clock output pin Internal/External clock select bit = "0" Transfer clock input pin Internal/External clock select bit = "1" CTS i, RTSi CTS input pin See Table 12.2.1. (P80, P81, P84, P85) RTS output pin Programmable I/O port pin Port P8 direction register: address 14 16 Internal/External clock select bit: bit 3 at addresses 30 16, 38 16 TxD0/P83 switch bit: bit 2 at address AC16 TxD1/P87 switch bit: bit 3 at address AC16 Note: The TxDi pin outputs "H" level until transmission starts after UARTi's operating mode is selected. 12.3.1 Transfer clock (Synchronizing clock) Data transfer is performed synchronously with a transfer clock. For the transfer clock, the following selection is possible: Whether to generate a transfer clock internally or to input it from the external. Polarity of transfer clock. The transfer clock is generated by operation of the transmit control circuit. Accordingly, even when performing only reception, set the transmit enable bit to "1," and set dummy data in the UARTi transmit buffer register in order to make the transmit control circuit active. (1) Internal generation of transfer clock The count source selected with the BRG count source select bits is divided by the BRGi, and the BRGi output is further divided by 2. This divided output is the transfer clock. The transfer clock is output from the CLK i pin. Transfer clock's frequency = 12-20 fi 2 (n+1) fi: Frequency of BRGi's count source (f 2, f 16, f64 , or f512) n: Setting value of BRGi 7902 Group User's Manual SERIAL I/O 12.3 Clock synchronous serial I/O mode (2) Input of transfer clock from the external A clock input from the CLK i pin becomes the transfer clock. (3) Porarity of transfer clock As shown in Figure 12.3.1, the polarity of the transfer clock can be selected by the CLK polarity select bit (bit 6 at addresses 34 16, 3C 16 ). CLK polarity select bit = 0 CLKi TxDi D0 D1 D2 D3 D4 D5 D6 D7 RxDi D0 D1 D2 D3 D4 D5 D6 D7 The transmit data is output to the TxDi pin at the falling edge of a transfer clock, and the receive data is input from the RxDi pin at the rising edge of the transfer clock. The level at the CLKi pin is "H" when the transfer is not performed. CLK polarity select bit = 1 CLKi TxDi D0 D1 D2 D3 D4 D5 D6 D7 RxDi D0 D1 D2 D3 D4 D5 D6 D7 The transmit data is output to the TxDi pin at the rising edge of a transfer clock, and the receive data is input from the RxDi pin at the falling edge of the transfer clock. The level at the CLKi pin is "L" when the transfer is not performed. Fig. 12.3.1 Polarity of transfer clock 7902 Group User's Manual 12-21 SERIAL I/O 12.3 Clock synchronous serial I/O mode 12.3.2 Transfer data format LSB first or MSB first can be selected as the transfer data format. Table 12.3.3 lists the relationship between the transfer data format and writing/reading to and from the UARTi transmit/receive buffer register. The transfer format select bit (bit 7 at addresses 3416, 3C16 ) selects the transfer data format. When this bit is cleared to "0," the set data is written to the UARTi transmit buffer register as the transmit data, as it is. Similarly, the data in the UARTi receive buffer register is read out as the receive data, as it is. (See the upper row in Table 12.3.3.) When this bit is set to "1," each bit's position of set data is reversed, and the resultant data will be written to the UARTi transmit buffer register as the transmit data. Similarly, each bit's position of data in the UARTi receive buffer register is reversed, and the resultant data will be read out as the receive data. (See the lower row in Table 12.3.3.) Note that only the method of writing/reading to and from the UARTi transmit/receive buffer register is affected by selection of the transfer data format, and that the transmit/receive operation is unaffected by it. Table 12.3.3 Relationship between transfer data format and writing/reading to and from UARTi transmit/ receive buffer register Transfer format select bit Transfer data format Writing to UARTi transmit buffer register Data bus 0 LSB (Least Significant Bit) first 1 12-22 Data bus UARTi receive buffer register DB7 D7 DB7 D7 DB6 D6 DB6 D6 DB5 D5 DB5 D5 DB4 D4 DB4 D4 DB3 D3 DB3 D3 DB2 D2 DB2 D2 DB1 D1 DB1 D1 DB0 D0 DB0 D0 Data bus MSB (Most Significant Bit) first UARTi transmit buffer register Reading from UARTi receive buffer register UARTi transmit buffer register Data bus UARTi receive buffer register DB7 D7 DB7 D7 DB6 D6 DB6 D6 DB5 D5 DB5 D5 DB4 D4 DB4 D4 DB3 D3 DB3 D3 DB2 D2 DB2 D2 DB1 D1 DB1 D1 DB0 D0 DB0 D0 7902 Group User's Manual SERIAL I/O 12.3 Clock synchronous serial I/O mode 12.3.3 Method of transmission Figure 12.3.2 shows an initial setting example for relevant registers when transmitting. Transmission is started when all of the following conditions ( to ) has been satisfied. When an external clock is selected, satisfy conditions to with the following preconditions satisfied. <Preconditions> The CLKi pin's input is at "H" level (External clock selected, when the CLK polarity select bit = "0") The CLKi pin's input is at "L" level (External clock selected, when the CLK polarity select bit = "1") Note: When an internal clock is selected, the above preconditions are ignored. Transmit data is present in the UARTi transmit buffer register (transmit buffer empty flag = "0") Transmission is enabled (transmit enable bit = "1"). The CTSi pin's input is at "L" level (when the CTS function selected). Note: When the CTS function is not selected, condition is ignored. By connecting the RTSi pin (receiver side) and CTSi pin (transmitter side), the timing of transmission and that of reception can be matched. For details, refer to section "12.3.6 Receive operation." When using interrupts, it is necessary to set the relevant registers to enable interrupts. For details, refer to "CHAPTER 7. INTERRUPTS." Figure 12.3.3 shows the write operation of data after transmission start, and Figure 12.3.4 shows the detect operation of transmit completion. 7902 Group User's Manual 12-23 SERIAL I/O 12.3 Clock synchronous serial I/O mode AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AA AA A AA AAAAAAAAAAAAA AA AA A AA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AA A AA AAAA A AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA UART0 transmit/receive mode register (Address 3016) UART1 transmit/receive mode register (Address 3816) b7 0 b0 0 0 1 Selection of clock synchronous serial I/O mode Internal/External clock select bit 0: Internal clock 1: External clock : It may be either "0" or "1." UART0 transmit/receive control register 0 (Address 3416) UART1 transmit/receive control register 0 (Address 3C16) b7 b0 BRG count source select bits b1 b0 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 CTS/RTS function select bit 0: CTS function selected 1: RTS function selected CTS/RTS enable bit 0: CTS/RTS function is enabled. 1: CTS/RTS function is disabled. CLK polarity select bit 0: At the falling edge of the transfer clock, transmit data is output. 1: At the rising edge of the transfer clock, transmit data is output. Transfer format select bit 0: LSB first 1: MSB first Serial I/O pin control register (Address AC16) b7 b0 CTS0/RTS0 separate select bit 0: CTS0/RTS0 are used together (Note). CTS1/RTS1 separate select bit 0: CTS1/RTS1 are used together (Note). TxD0/P83 switch bit 0: Functions as TxD0. AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAA AAAA AAAA UART0 transmit interrupt control register (Address 7116) UART1 transmit interrupt control register (Address 7316) b7 b0 Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. UART0 transmit buffer register (Address 3216) UART1 transmit buffer register (Address 3A16) b7 b0 Transmit data is set. UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) b7 b0 1 Transmit enable bit 1: Transmission is enabled. Transmission starts. (In the case of selecting the CTS function, transmission starts when the CTS0 pin's input level is "L.") TxD1/P87 switch bit 0: Functions as TxD1. When extenal clock is selected Note: In the clock synchronous serial I/O mode, CTSi/RTSi separation cannot be selected. (Refer to section "[Precautions for clock synchronous serial I/O mode].") When internal clock is selected UART0 baud rate register (BRG0) (Address 3116) UART1 baud rate register (BRG1) (Address 3916) b7 b0 Can be set to "0016" to "FF16." Fig. 12.3.2 Initial setting example for relevant registers when transmitting 12-24 7902 Group User's Manual SERIAL I/O 12.3 Clock synchronous serial I/O mode [When using interrupts] [When not using interrupts] A UARTi transmit interrupt request occurs when the transbission starts (when the UARTi transmit buffer register becomes empty). AAA AAA AAA Checking state of UARTi transmit buffer register UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) b7 b0 UARTi transmit interrupt b0 1 Transmit buffer empty flag 0: Data is present in transmit buffer register. 1: No data is present in transmit buffer register. (Writing of next transmit data is possible.) Writing of next transmit data UART0 transmit buffer register (Address 3216) UART1 transmit buffer register (Address 3A16) b7 Note: This figure shows the bits and registers required for processing. See Figures 12.3.6 and 12.3.7 for the change of flag state and the occurrence timing of an interrupt request. b0 Transmit data is set. Fig. 12.3.3 Write operation of data after transmission start [When using interrupts] [When not using interrupts] AAA AAA AAA A UARTi transmit interrupt request occurs when the transmission starts. Checking start of transmission UART0 transmit interrupt control register (Address 7116) UART1 transmit interrupt control register (Address 7316) b7 UARTi transmit interrupt b0 Interrupt request bit 0: No interrupt requested 1: Interrupt requested (Transmission has started.) Checking completion of transmission A A UART0 transmit/receive control register 0 (Address 3416) UART1 transmit/receive control register 0 (Address 3C16) b7 b0 Note: This figure shows the bits and registers required for processing. See Figures 12.3.6 and 12.3.7 for the change of flag state and the occurrence timing of an interrupt request. Transmit register empty flag 0: Transmission is in progress. 1: Transmission is completed. Processing at completion of transmission Fig. 12.3.4 Detect operation of transmit completion 7902 Group User's Manual 12-25 SERIAL I/O 12.3 Clock synchronous serial I/O mode 12.3.4 Transmit operation When the transmit conditions described in section "12.3.3 Method of transmission" have been satisfied in the case of an internal clock selected, a transfer clock is generated and the following operations are automatically performed after 1 cycle of the transfer clock or less has passed. In the case of an external clock selected, when the transmit conditions have been satisfied and then an external clock is input to the CLK i pin, the following operations are automatically performed: *The UARTi transmit buffer register's contents are transferred to the UARTi transmit register. *The transmit buffer empty flag is set to "1." *The transmit register empty flag is cleared to "0." *8 transfer clocks are generated (in the case of an internal clock selected). *A UARTi transmit interrupt request occurs, and the interrupt request bit is set to "1." The transmit operations are described below: Data in the UARTi transmit register is transmitted from the TxD i pin synchronously with the valid edge of the clock output from or input to the CLK i pin. This data is transmitted, bit by bit, sequentially beginning with the least significant bit. When 1-byte data has been transmitted, the transmit register empty flag is set to "1." This indicates the completion of transmission. Valid edge : A falling edge is selected when the CLK polarity select bit = "0." A rising edge is selected when the CLK polarity select bit = "1." Figure 12.3.5 shows the transmit operation. When an internal clock is selected, if the transmit conditions for the next data are satisfied at completion of the transmission, the transfer clock is generated continuously. Accordingly, when performing transmission continuously, set the next transmit data to the UARTi transmit buffer register during transmission (when the transmit register empty flag = "0"). When the transmit conditions for the next data are not satisfied, the transfer clock stops at "H" level (when the CLK polarity select bit = "0"), or "L" level (when the CLK polarity select bit = "1"). Figures 12.3.6 and 12.3.7 show examples of transmit timing. b7 b0 UARTi transmit buffer register Transfer clock output from or input to the CLKi pin (Note) Transmit data LSB MSB UARTi transmit register D7 D6 D5 D4 D3 D 2 D7 D6 D1 D 0 D5 D4 D 3 D2 D7 D6 D5 D 4 D1 D0 D3 D 2 D1 D7 D 6 D5 D4 ** * D3 D2 ** * D7 Note: This applies when the CLK polarity select bit = "0." When the CLK polarity select bit = "1," data is shifted at the rising edge of the transfer clock. Fig. 12.3.5 Transmit operation 12-26 7902 Group User's Manual SERIAL I/O 12.3 Clock synchronous serial I/O mode Tc Transfer clock Transmit enable bit Data is set in UARTi transmit buffer register. Transmit buffer empty flag UARTi transmit register UARTi transmit buffer register. TCLK CTSi Stopped because transmit enable bit = "0." Stopped because CTSi = "H." CLKi TENDi D0 D1 D2 D 3 D4 D 5 D 6 D7 TxDi D0 D1 D2 D3 D4 D 5 D 6 D7 D 0 D1 D2 D3 D4 D5 D 6 D7 Transmit register empty flag UARTi transmit interrupt request bit Cleared to "0" when interrupt request is accepted or cleared to "0" by software. The above timing diagram applies when the following conditions are satisfied: Internal clock selected CTS function selected CLK polarity select bit = 0 TENDi: Next transmit conditions are examined when this signal level is "H." (TENDi is an internal signal. Accordingly, it cannot be read from the external.) Tc = TCLK = 2(n+1) /fi fi: BRGi count source frequency n: Value set in BRGi Fig. 12.3.6 Example of transmit timing (when internal clock and CTS function selected) Tc Transfer clock Transmit enable bit Data is set in UARTi transmit buffer register. Transmit buffer empty flag UARTi transmit registerUARTi transmit buffer register. TCLK Stopped because transmit enable bit = "0." CLKi TENDi TxDi D0 D1 D2 D3 D4 D5 D 6 D7 D0 D 1 D2 D3 D4 D5 D6 D7 D 0 D1 D2 D3 D4 D 5 D 6 D7 Transmit register empty flag UARTi transmit interrupt request bit Cleared to "0" when interrupt request is accepted or cleared to "0" by software. The above timing diagram applies when the following conditions are satisfied: Internal clock selected CTS function not selected CLK polarity select bit = 0 TENDi: Next transmit conditions are examined when this signal level is "H." (TENDi is an internal signal. Accordingly, it cannot be read from the external.) Tc = TCLK = 2(n+1) /fi fi: BRGi count source frequency n: Value set in BRGi Fig. 12.3.7 Example of transmit timing (when internal clock selected and CTS function not selected) 7902 Group User's Manual 12-27 SERIAL I/O 12.3 Clock synchronous serial I/O mode 12.3.5 Method of reception Figure 12.3.8 shows an initial setting example for relevant registers when receiving. Reception is started when all of the following conditions ( to ) have been satisfied. When an external clock is selected, satisfy conditions to with the following preconditions satisfied. <Preconditions> The CLK i pin's input is at "H" level (External clock selected, when the CLK polarity select bit = "0" ). The CLK i pin's input is at "L" level (External clock selected, when the CLK polarity select bit = "1"). Note: When an internal clock is selected, the above preconditions are ignored. Dummy data is present in the UARTi transmit buffer register (transmit buffer empty flag = "0") Reception is enabled (receive enable bit = "1"). Transmission is enabled (transmit enable bit = "1"). By connecting the RTSi pin (receiver side) and CTSi pin (transmitter side), the timing of transmission and that of reception can be matched. For details, refer to section "12.3.6 Receive operation." When using interrupts, it is necessary to set the relevant registers to enable interrupts. For details, refer to "CHAPTER 7. INTERRUPTS." Figure 12.3.9 shows processing after reception is completed. 12-28 7902 Group User's Manual SERIAL I/O 12.3 Clock synchronous serial I/O mode AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA AA A AA A AAAAAAAAAAA AAAAAAAAAAAA AA A AA A AAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAAA AA A A AAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA AAAA AAAA UART0 transmit/receive mode register (Address 3016) UART1 transmit/receive mode register (Address 3816) b7 0 b0 When extenal clock is selected 0 0 1 When internal clock is selected Selection of clock synchronous serial I/O mode Internal/External clock select bit 0: Internal clock 1: External clock UART0 baud rate register (BRG0) (Address 3116) UART1 baud rate register (BRG1) (Address 3916) b7 b0 : It may be either "0" or "1." Can be set to "0016" to "FF16." UART0 transmit/receive control register 0 (Address 3416) UART1 transmit/receive control register 0 (Address 3C16) b7 b0 Port P8 direction register (Address 1416) b7 b0 BRG count source select bits 0 b1 b0 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 Pin RxD0 Pin RxD1 CTS/RTS function select bit 0: CTS function selected 1: RTS function selected CTS/RTS enable bit 0: CTS/RTS function is enabled. 1: CTS/RTS function is disabled. UART0 receive interrupt control register (Address 7216) UART1 receive interrupt control register (Address 7416) b7 b0 UARTi receive interrupt mode select bit 0: Reception interrupt 1: Reception error interrupt Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. CLK polarity select bit 0: At the rising edge of the transfer clock, receive data is input. 1: At the falling edge of the transfer clock, receive data is input. Transfer format select bit 0: LSB first 1: MSB first UART0 transmit buffer register (Address 3216) UART1 transmit buffer register (Address 3A16) b7 b0 Serial I/O pin control register (Address AC16) b7 b0 Dummy data is set. CTS0/RTS0 separate select bit 0: CTS0/RTS0 are used together (Note 1). CTS1/RTS1 separate select bit 0: CTS1/RTS1 are used together (Note 1). TxD0/P83 switch bit (Note 2) 0: Functions as TxD0. 1: Functions as P83. TxD1/P87 switch bit (Note 2) 0: Functions as TxD1. 1: Functions as P87. UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) b7 b0 1 1 Transmit enable bit 1: Transmission enabled Notes 1: In the clock synchronous serial I/O mode, CTSi/RTSi separation cannot be selected. (Refer to section "[Precautions for clock synchronous serial I/O mode].") 2: When only reception is performed, if these bits = "1," the TxDi pin can be used as a programmable I/O port pin. Reception enable bit 1: Reception enabled Note: Set the receive enable bit and the transmit enable bit to "1" simultaneously. Reception starts. Fig. 12.3.8 Initial setting example for relevant registers when receiving 7902 Group User's Manual 12-29 SERIAL I/O 12.3 Clock synchronous serial I/O mode [When not using interrupts] [When using interrupts] (Note 1) AAA AAA AAA A UARTi receive interrupt request occurs when reception is completed. Checking completion of reception UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) b7 b0 1 UARTi receive interrupt 1 Receive complete flag 0 : Reception not completed 1 : Reception completed Reading of receive data (Note 2) UART0 receive buffer register (Address 3616) UART1 receive buffer register (Address 3E16) b0 b7 Read out receive data. Checking error UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) b0 b7 1 1 Overrun error flag 0 : No overrun error 1 : Overrun error detected Processing after reading out receive data Notes 1: When performing the processing after reception is completed, using an interrupt, be sure to select a receive interrupt (UARTi receive interrupt mode select bit = "0.") 2: In the case of an external clock and the RTS function selected, the RTSi output level becomes "L" when the UARTi receive buffer register is read out. Accordingly, when performing reception continuously, be sure to write the dummy data to the UARTi transmit buffer register before reading out the UARTi receive buffer register. 3: This figure shows the bits and registers required for the processing. See Figure 12.3.12 for the change of flag state and the occurrence timing of an interrupt request. Fig. 12.3.9 Processing after reception is completed 12-30 7902 Group User's Manual SERIAL I/O 12.3 Clock synchronous serial I/O mode 12.3.6 Receive operation In the case of an internal clock selected, when the receive conditions described in section "12.3.5 Method of reception" have been satisfied, a transfer clock is generated and the reception is started after 1 cycle of the transfer clock or less has passed. In the case of an external clock selected, when the receive conditions have been satisfied, the UARTi enters the receive-enabled state, and then reception will be started when an external clock is input to the CLKi pin. In the case of an external clock selected, when connecting the RTS i pin to the CTS i pin of the transmitter side, the timing of transmission and that of reception can be matched. In the case of an internal clock selected, do not use the RTS function. It is because the RTS output is undefined in the case of an internal clock selected. In the case of an external clock and the RTS function selected, the RTS i pin's output level becomes as described below. When the receive enable bit = "0," if one of the following is performed, the RTSi pin's output level becomes "L" and informs of the transmitter side that reception has become enabled: * The receive enable bit is set to "1." * The low-order byte of the UARTi receive buffer register is read out. When the receive enable bit = "1," if the low-order byte of the UARTi receive buffer register is read out, the RTS i pin's output level becomes "L." Accordingly, when performing reception continuously, an overrun occurrence can be avoided because the RTS output level does not become "L" until the receive data is read out. When reception has started, the RTSi pin's output level becomes "H." Figure 12.3.10 shows a connection example. Transmitter side Receiver side TxDi TxDi RxDi RxDi CLKi CLKi CTSi RTSi Fig. 12.3.10 Connection example 7902 Group User's Manual 12-31 SERIAL I/O 12.3 Clock synchronous serial I/O mode The receive operations are described below: The signal input to the RxD i pin is taken into the most significant bit of the UARTi receive register synchronously with the valid edge of the clock output from the CLKi pin or input to the CLK i pin. The contents of the UARTi receive register are shifted, bit by bit, to the right. Steps and are repeated at each valid edge of the clock output from the CLK i pin or input to the CLK i pin. When 1-byte data has been prepared in the UARTi receive register, the contents of this register are transferred to the UARTi receive buffer register. Simultaneously with step , the receive complete flag is set to "1." Additionally, when the receive interrupt is selected (UARTi receive interrupt mode select bit = "0"), a UARTi receive interrupt request occurs and its interrupt request bit is set to "1." Valid edge : A rising edge is selected when the CLK polarity select bit = "0." A falling edge is selected when the CLK polarity select bit = "1." The receive complete flag is cleared to "0" when the low-order byte of the UARTi receive buffer register is read out. Figure 12.3.11 shows the receive operation, and Figure 12.3.12 shows an example of receive timing (when an external clock is selected). When the transfer format select bit is "1" (MSB first), each bit's position of this register's contents is reversed, and then the resultant data is read out. 12-32 7902 Group User's Manual SERIAL I/O 12.3 Clock synchronous serial I/O mode LSB MSB Transfer clock output from or input to CLKi pin (Note). UARTi receive register D0 D1 D0 D2 D1 D0 * ** * * * D7 D6 D 5 D 4 D3 D2 b7 D1 D0 b0 UARTi receive buffer register Receive data Note: This applies when the CLK polarity select bit = "0." When the CLK polarity select bit = "1," data is shifted at the rising edge of the transfer clock. Fig. 12.3.11 Receive operation Receive enable bit Transmit enable bit Dummy data is set to UARTi transmit buffer register. Transmit buffer empty flag UARTi transmit registerUARTi transmit buffer register RTSi 1/fEXT CLKi Receive data is taken in. RxDi D0 D 1 D 2 D 3 D4 D 5 D6 D 7 D0 UARTi receive registerUARTi receive buffer register D1 D2 D3 D 4 D5 UARTi receive buffer register is read out. Receive complete flag UARTi receive interrupt request bit Cleared to "0" when interrupt request is accepted or cleared to "0" by software. The above timing diagram applies when the following conditions are satisfied: External clock selected RTS function selected CLK polarity select bit = "0" When the CLKi pin's input level is "H," be sure to satisfy the following conditions: Writing of dummy data to UARTi transmit buffer register Transmit enable bit = "1" Receive enable bit = "1" fEXT: Frequency of external clock Fig. 12.3.12 Example of receive timing (when external clock selected) 7902 Group User's Manual 12-33 SERIAL I/O 12.3 Clock synchronous serial I/O mode 12.3.7 Processing on detecting overrun error In the clock synchronous serial I/O mode, an overrun error can be detected. An overrun error occurs when the next data has been prepared in the UARTi receive register with the receive complete flag = "1" (i.e. data is present in the UARTi receive buffer register) and next data is transferred to the UARTi receive buffer register. In other words, an overrun error occurs when the next data has been prepared before reading out the contents of the UARTi receive buffer register. When an overrun error has occurred, the next receive data is written into the UARTi receive buffer register. Additionally, when the receive error interrupt is selected (UARTi receive interrupt mode select bit = "1"), a UARTi receive interrupt request occurs and its interrupt request bit is set to "1." When the receive interrupt is selected (UARTi receive interrupt mode select bit = "0"), the UARTi receive interrupt request bit does not change. An overrun error is detected when data is transferred from the UARTi receive register to the UARTi receive buffer register, and the overrun error flag is set to "1." The overrun error flag is cleared to "0" by clearing the receive enable bit to "0." When an overrun error occurs during reception, be sure to initialize the overrun error flag and UARTi receive buffer register, and then perform reception again. When it is necessary to perform retransmission owing to a receiver-side overrun error which has occurred during transmission, be sure to set the UARTi transmit buffer register again, and start transmission again. The methods of initializing the UARTi receive buffer register and that of setting the UARTi transmit buffer register again are described below. (1) Method of initializing UARTi receive buffer register Clear the receive enable bit to "0" (reception disabled). Set the receive enable bit to "1" again (reception enabled). (2) Method of setting UARTi transmit buffer register again Clear the serial I/O mode select bits to "000 2" (serial I/O invalidated). Set the serial I/O mode select bits to "0012" again. Set the transmit enable bit to "1" (transmission enabled), and set the transmit data to the UARTi transmit buffer register. 12-34 7902 Group User's Manual SERIAL I/O 12.3 Clock synchronous serial I/O mode [Precautions for clock synchronous serial I/O mode] 1. A transfer clock is generated by operation of the transmit control circuit. Accordingly, even when performing only reception, the transmit operation (in other words, setting for transmission) must be performed. In this case, be sure to set as follows. Additionally, in this case, dummy data is output from the TxD i pin to the external: * When performing reception, be sure to enable the reception after dummy data is set to the low-order byte of the UARTi transmit buffer register. Also, be sure to set dummy data at each 1-byte data reception. * At reception, be sure to set the receive enable bit and transmit enable bit to "1" simultaneously. When performing only reception, if any of the TxD0/P8 3 and TxD 1/P8 7 switch bits (bits 2 and 3 at address AC16 ) is set to "1," the corresponding TxDi pin can be used as a programmable I/O port pin. 2. When an external clock is selected, with the input level at the CLKi pin = "H" (the CLK polarity select bit = "0") or "L" (the CLK polarity select bit = "1"), be sure to satisfy all of the following three conditions: <At transmission> Transmit data is written to the UARTi transmit buffer register. The transmit enable bit is set to "1." "L" level is input to the CTS i pin (when the CTS function selected). <At reception> Dummy data is written to the UARTi transmit buffer register. The receive enable bit is set to "1." The transmit enable bit is set to "1." 3. When using the CTS0/RTS0 pin, be sure that the D-A 2 output enable bit (bit 2 at address 9616 ) = "0" (output disabled). 4. While the CTS i/RTS i separation is selected, the CLK i pin cannot be used. Accordingly, in the clock synchronous serial I/O mode, the CTS i/RTSi separation cannot be selected. 5. Writing to the UARTi baud rate register (BRGi) must be performed while transmission/reception halts. 6. When an internal clock is selected, do not use the RTS function because the RTS output is undefined. 7. When performing transmission, be sure to clear both of the TxD0/P83 and TxD 1/P87 switch bits to "0" (bits 2 and 3 at address AC 16). 7902 Group User's Manual 12-35 SERIAL I/O 12.4 Clock asynchronous serial I/O (UART) mode 12.4 Clock asynchronous serial I/O (UART) mode Table 12.4.1 lists the performance overview in the UART mode, and Table 12.4.2 lists the functions of I/O pins in this mode. Table 12.4.1 Performance overview in UART mode Item Functions Transfer data 1 bit Start bit format Character bit (Transfer data) 7 bits, 8 bits, or 9 bits 0 bit or 1 bit (Odd or Even can be selected.) Parity bit Transfer rate Stop bit When selecting internal clock When selecting external clock Error detection 1 bit or 2 bits BRGi's output divided by 16 Maximum 312.5 kbps 4 types (overrun, framing, parity, and summing): presence of an error can be detected only by check of the error sum flag. Table 12.4.2 Functions of I/O pins in UART mode Pin name Functions Method of selection TxD i (P8 3, P87) Serial data output pin (Note) Programmable I/O port pin TxD 0/P8 3 or TxD1/P8 7 switch bit = "1." RxD i (P82, P86) Serial data input pin Port P8 direction register's corresponding bit = "0" (Can be used as a programmable I/O port pin when performing only transmission.) BRGi's count source input pin Internal/External clock select bit = "1" Programmable I/O port pin Internal/External clock select bit = "0" See Table 12.2.1. CTS i/ RTS i (P8 0 , P8 1 , CTS input pin P8 4, P8 5) RTS output pin Programmable I/O port pin CLK i (P81, P85) Port P8 direction register: address 1416 Internal/External clock select bit: bit 3 at addresses 30 16, 3816 TxD0/P83 switch bit: bit 2 at address AC 16 TxD1/P87 switch bit: bit 3 at address AC 16 Note: The TxDi pin outputs "H" level while transmission is not performed after the UARTi's operating mode is selected. 12-36 7902 Group User's Manual SERIAL I/O 12.4 Clock asynchronous serial I/O (UART) mode 12.4.1 Transfer rate (Frequency of transfer clock) The transfer rate is determined by the BRGi (addresses 31 16 , 39 16 ). When "n" is set into BRGi, BRGi divides the count source frequency by (n + 1). The BRGi's output is further divided by 16, and the resultant clock becomes the transfer clock. Accordingly, "n" is expressed by the following formula. F n = 16 B n: Value set in BRGi (00 16 to FF16 ) F: BRGi's count source frequency (Hz) B: Transfer rate (bps) -- 1 An internal clock or an external clock can be selected as the BRGi's count source with the internal/external clock select bit (bit 3 at addresses 30 16 , 3816 ). When an internal clock is selected, the clock selected with the BRG count source select bits (bits 0 and 1 at addresses 34 16 , 3C16) becomes the BRGi's count source. When an external clock is selected, the clock input to the CLK i pin becomes the BRGi's count source. Be sure to set the same transfer rate for both transmitter and receiver sides. Tables 12.4.3 and 12.4.4 list the setting examples of transfer rate. Each of the values, listed in these tables, realizes the actual transfer rate of which error toward an ideal transfer rate is within 1 %. Table 12.4.3 Setting examples of transfer rate (1) fsys = 19.6608 MHz Transfer Actual time BRGi's BRGi's set rate (bps) (bps) count source value: n (Note) 63 (3F 16 ) 300.00 300 f64 127 (7F16 ) 600.00 600 f16 63 (3F 16 ) 1200.00 1200 f16 31 (1F 16 ) 2400.00 2400 f16 4800 9600 14400 19200 31250 38400 f2 f2 f2 f2 f2 127 63 41 31 (7F16 ) (3F 16 ) (2916 ) (1F16 ) 15 (0F16 ) f sys = 20 MHz BRGi's set BRGi's value: n (Note) count source 64 (40 16) f 64 129 (81 16) f 16 64 (40 16) f 16 64 (40 16) f8 4800.00 9600.00 14628.57 19200.00 Actual time (bps) 300.48 600.96 1201.92 2403.85 f2 f2 f2 f2 129 (81 16) 64 (40 16) 42 (2A 16) 4807.69 9615.38 14534.88 f2 19 (13 16) 31250.00 38400.00 Table 12.4.4 Setting examples of transfer rate (2) fsys = 11.0592 MHz Transfer BRGi's set BRGi's Actual time rate (bps) count source value: n (Note) (bps) 35 (23 16 ) f64 300.00 300 71 (47 16 ) 600.00 600 f16 35 (23 16 ) 1200.00 1200 f16 18 (12 16 ) f16 2400.00 2400 4800 9600 14400 19200 28800 31250 38400 57600 115200 f2 f2 f2 f2 f2 f2 f2 f2 f2 71 35 23 17 11 (47 16 ) (23 16 ) (18 16 ) (11 16 ) (0B 16 ) 10 8 5 3 (0A 16 ) (08 16 ) (05 16 ) (03 16 ) 4800.00 9600.00 14400.00 19200.00 28800.00 31418.18 38400.00 57600.00 115200.00 Note: This applies when the peripheral device's clock select bits 1, 0 (bits 7, 6 at address BC16 ) = "002." 7902 Group User's Manual 12-37 SERIAL I/O 12.4 Clock asynchronous serial I/O (UART) mode Error-permitted range of transfer baud During reception, the receive data input to the RxDi pin is taken at the rising edge of the transfer clock. (Refer to section "12.4.6 Receive operation.") Accordingly, in order to receive data correctly, the stop bit must be input when the transfer clock of one-set receive data rises last. Figure 12.4.1 shows the relationship between the transfer clock and receive data. <1ST-8DATA-1SP> RxDi (Receive data) When the transfer rate of the receive data is faster than the rate of the transfer clock on the receiver side ST When the transfer rate of the receive data is slower than the rate of the transfer clock on the receiver side D0 ST SP D7 D7 D0 SP SP must be detected at this last rising edge of the transfer clock. At the falling edge of ST, the transfer clock is generated, and reception starts. Transfer clock (Receiver side) 1 clock 8 clocks 1 clock 9.5 clocks 1 period of BRGi's count source (Maximum) According to the condition of the input timing, a maximum of this period () can be omitted. ST : Start bit SP : Stop bit Fig. 12.4.1 Relationship between transfer clock and receive data Accordingly, the transfer rate of the receiver and transmitter sides must satisfy the following formula in order to receive data correctly. 1 1 (b - 1) + Bt F Br: Bt: F : b : < 1 1 (b - 0.5) + F Br < 1 b Bt Transfer rate on receiver side (bps) Transfer rate on transmitter side (bps) BRGi's count source frequency on receiver side (Hz) Entire bit number of one-set data (ex: 12 bits in the case of 1ST-8DATA-1PAR-2SP; See Figure 12.4.2.) Be sure to satisfy the above formula, and set the timing with enough margin. Also, the user shall make sufficient evaluation before actually using it. 12-38 7902 Group User's Manual SERIAL I/O 12.4 Clock asynchronous serial I/O (UART) mode 12.4.2 Transfer data format The transfer data format can be selected from formats shown in Figure 12.4.2. Bits 4 to 6 at addresses 3016 and 3816 select the transfer data format. (See Figure 12.2.2.) Set the same transfer data format for both transmitter and receiver sides. Figure 12.4.3 shows an example of transfer data format. Table 12.4.5 lists each bit in transmit data. Transfer data length of 7 bits 1ST--7DATA 1SP 1ST--7DATA 2SP 1ST--7DATA--1PAR-- 1SP 1ST--7DATA--1PAR-- 2SP Transfer data length of 8 bits 1ST--8DATA 1SP 1ST--8DATA 2SP 1ST--8DATA--1PAR-- 1SP 1ST--8DATA--1PAR-- 2SP Transfer data length of 9 bits 1ST--9DATA 1SP 1ST--9DATA 2SP 1ST--9DATA--1PAR-- 1SP 1ST--9DATA--1PAR-- 2SP ST DATA PAR SP : Start bit : Character bit (Transfer data) : Parity bit : Stop bit Fig. 12.4.2 Transfer data format * 1ST-8DATA-1PAR-1SP Time Transmit/Receive data Next transmit/receive data (When continuously transferred) DATA (8 bits) ST LSB MSB PAR SP ST Fig. 12.4.3 Example of transfer data format Table 12.4.5 Each bit in transmit data Name Functions ST "L" signal equivalent to 1 character bit. This is added immediately before the character Start bit bits. It indicates start of data transmission. DATA Transmit data which is set in the UARTi transmit buffer register. Character bit PAR A signal that is added immediately after the character bits in order to improve data Parity bit reliability. The level of this signal changes according to selection of odd/even parity SP Stop bit in such a way that the sum of "1"s in the sum of this bit and character bits is always an odd or even number. "H" level signal equivalent to 1 or 2 character bits. This is added immediately after the character bits (or parity bit when parity is enabled). It indicates completion of data transmission. 7902 Group User's Manual 12-39 SERIAL I/O 12.4 Clock asynchronous serial I/O (UART) mode 12.4.3 Method of transmission Figure 12.4.4 shows an initial setting example for relevant registers when transmitting. The difference depending on the transfer data length (7 bits, 8 bits, or 9 bits) is the transmit data's length only. When selecting a 7- or 8-bit data length, be sure to set the transmit data into the low-order byte of the UARTi transmit buffer register. When selecting a 9-bit data length, be sure to set the transmit data into the low-order byte and bit 0 of the high-order byte. Transmission is started when all of the following conditions ( to ) are satisfied: Transmit data is present in the UARTi transmit buffer register (transmit buffer empty flag = "0"). Transmit is enabled (transmit enable bit = "1"). The CTSi pin's input level is "L" (when the CTS function selected). Note: When the CTS function is not selected, condition is ignored. By connecting the RTSi pin (receiver side) and CTSi pin (transmitter side), the timing of transmission and that of reception can be matched. For details, refer to section "12.4.6 Receive operation." When using interrupts, it is necessary to set the relevant registers to enable interrupts. For details, refer to "CHAPTER 7. INTERRUPTS." Figure 12.4.5 shows writing data after transmission is started, and Figure 12.4.6 shows detection of transmit completion. 12-40 7902 Group User's Manual SERIAL I/O 12.4 Clock asynchronous serial I/O (UART) mode AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AA AAAAAAAAAAA AAAAAAAAAAA AA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA UART0 transmit/receive mode register (Address 3016) UART1 transmit/receive mode register (Address 3816) b7 b0 1 Serial I/O mode select bit b2 b1 b0 1 0 0: UART mode (7 bits) 1 0 1: UART mode (8 bits) 1 1 0: UART mode (9 bits) Internal/External clock select bit 0: Internal clock 1: External clock Stop bit length select bit 0: 1 stop bit 1: 2 stop bits Odd/Even parity select bit 0: Odd parity 1: Even parity Parity enable bit 0: Parity is disabled. 1: Parity is enabled. Sleep select bit 0: Sleep mode cleared (invalid) 1: Sleep mode selected UART0 transmit/receive control register 0 (Address 3416) UART1 transmit/receive control register 0 (Address 3C16) b7 b0 0 0 BRG count source select bits b1 b0 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 CTS/RTS function is select bit 0: CTS function selected 1: RTS function selected CTS/RTS enable bit 0: CTS/RTS function is enabled. 1: CTS/RTS function is disabled. Serial I/O pin control register (Address AC16) b7 b0 CTS0/RTS0 separate select bit 0: CTS0/RTS0 are used together. 1: CTS0/RTS0 are separated (Note). CTS1/RTS1 separate select bit 0: CTS1/RTS1 are used together. 1: CTS1/RTS1 are separated (Note). TxD0/P83 switch bit 0: Functions as TxD0. TxD1/P87 switch bit 0: Functions as TxD1. Note: The CLKi pin cannot be used when the CTSi/RTSi separation is selected. (Refer to "[Precaution for clock asynchronous serial I/O (UART) mode].") AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAA AAA AAA AAA UART0 baud rate register (BRG0) (Address 3116) UART1 baud rate register (BRG1) (Address 3916) b7 b0 Can be set to "0016" to "FF16." CTSi/RTSi are used together. CTSi/RTSi are separated. Port P8 direction register (Address 1416) b7 b0 0 0 Pin CTS0 Pin CTS1 UART0 transmit interrupt control register (Address 7116) UART1 transmit interrupt control register (Address 7316) b0 b7 Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. UART0 transmit buffer register (Addresses 3316, 3216) UART1 transmit buffer register (Addresses 3B16, 3A16) b15 b8 b7 b0 Transmit data is set. UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) b7 b0 1 Transmit enable bit 1: Transmission enabled Transmission starts. (If the CTS function selected, transmission starts when the CTSi pin's input level becomes "L.") Fig. 12.4.4 Initial setting example for relevant registers when transmitting 7902 Group User's Manual 12-41 SERIAL I/O 12.4 Clock asynchronous serial I/O (UART) mode [When using interrupts] [When not using interrupts] A UARTi transmit interrupt request occurs when the transmission starts. (when the UARTi transmit buffer register becomes empty.) AAA AAA AAA Checking state of UARTi transmit buffer register UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) b7 b0 UARTi transmit interrupt b0 1 Transmit buffer empty flag 0: Data is present in transmit buffer register. 1: No data is present in transmit buffer register. (Writing of next transmit data is possible.) Writing of next transmit data UART0 transmit buffer register (Addresses 3316, 3216) UART1 transmit buffer register (Addresses 3B16, 3A16) b15 b8 b7 Note: This figure shows the bits and registers required for processing. See Figures 12.4.7 to 12.4.9 for the change of flag state and the occurrence timing of an interrupt request. b0 Transmit data is set. Fig. 12.4.5 Write operation of data after transmission start 12-42 7902 Group User's Manual SERIAL I/O 12.4 Clock asynchronous serial I/O (UART) mode [When not using interrupts] [When using interrupts] A UARTi transmit interrupt request occurs when the transmission starts. AAAA AAAA AAAA Checking start of transmission UART0 transmit interrupt control register (Address 7116) UART1 transmit interrupt control register (Address 7316) b7 UARTi transmit interrupt b0 Interrupt request bit 0: No interrupt requested 1: Interrupt requested (Transmission has started.) Checking completion of transmission. AAA AA A AAAA AA UART0 transmit/receive control register 0 (Address 3416) UART1 transmit/receive control register 0 (Address 3C16) b7 0 b0 Note: This figure shows the bits and registers required for processing. See Figures 12.4.7 to 12.4.9 for the change of flag state and the occurrence timing of an interrupt request. 0 Transmit register empty flag 0: Transmission is in progress. 1: Transmission is completed. Processing at completion of transmission Fig. 12.4.6 Detect operation of transmit completion 7902 Group User's Manual 12-43 SERIAL I/O 12.4 Clock asynchronous serial I/O (UART) mode 12.4.4 Transmit operation When the receive conditions described in section "12.4.3 Method of transmission" have been satisfied, a transfer clock is generated, and the following operations are automatically performed after 1 cycle of the transfer clock or less has passed. *The UARTi transmit buffer register's contents are transferred to the UARTi transmit register. *The transmit buffer empty flag is set to "1." *The transmit register empty flag is cleared to "0." *A UARTi transmit interrupt request occurs, and the interrupt request bit is set to "1." The transmit operations are described below: Data in the UARTi transmit register is transmitted from the TxD i pin. This data is transmitted bit by bit sequentially in order of STDATA (LSB)***DATA (MSB)PAR SP according to the transfer data format. The transmit register empty flag is set to "1" at the center of the stop bit (or the second stop bit if 2 stop bits selected). This indicates completion of transmission. Additionally, whether the transmit conditions for the next data are satisfied or not is examined. When the transmit conditions for the next data are satisfied in step , the start bit is generated following the stop bit, and the next data is transmitted. When performing transmission continuously, be sure to set the next transmit data in the UARTi transmit buffer register during transmission (i.e. when the transmit register empty flag = "0"). When the transmit conditions for the next data are not satisfied, the TxD i pin outputs "H" level and the transfer clock stops. Figures 12.4.7 and 12.4.8 show examples of transmit timing when the transfer data length = 8 bits, and Figure 12.4.9 shows an example of transmit timing when the transfer data length = 9 bits. 12-44 7902 Group User's Manual SERIAL I/O 12.4 Clock asynchronous serial I/O (UART) mode Tc Transfer clock Transmit enable bit Data is set in UARTi transmit buffer register. Transmit buffer empty flag UARTi transmit register UARTi transmit buffer register TENDi Stopped because transmit enable bit = "0" TxDi ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P ST D0 D1 SP Transmit register empty flag UARTi transmit interrupt request bit Cleared to "0" when interrupt request is accepted or cleared to "0" by software. The above timing diagram applies when the following conditions are satisfied: Parity enabled 1 stop bit CTS function not selected ST: Start bit D0 to D7: Transfer data P: Parity bit ST: Stop bit TENDi: Next transmit conditions are examined when this signal level becomes "H." (TENDi is an internal signal. Accordingly, it cannot be read from the external.) Tc: 16 (n + 1)/fi or 16 (n + 1)/fEXT fi: BRGi's count source frequency (internal clock) fEXT: BRGi's count source frequency (external clock) n: Value set in BRGi Fig. 12.4.7 Example of transmit timing when transfer data length = 8 bits (when parity enabled, 1 stop bit selected, CTS function not selected) Tc Transfer clock Transmit enable bit Data is set in UARTi transmit buffer register. Transmit buffer empty flag UARTi transmit register UARTi transmit buffer register CTSi TENDi Stopped because transmit enable bit = "0" Stopped because CTSi = "H" TxDi ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 Transmit register empty flag UARTi transmit interrupt request bit Cleared to "0" when interrupt request is accepted or cleared to "0" by software. The above timing diagram applies when the following conditions are satisfied: Parity enabled 1 stop bit CTS function selected TENDi: Next transmit conditions are examined when this signal level becomes "H." (TENDi is an internal signal. Accordingly, it cannot be read from the external.) ST: Start bit D0 to D7: Transfer data P: Parity bit ST: Stop bit Tc = 16 (n + 1)/fi or 16 (n + 1)/fEXT fi: BRGi's count source frequency (internal clock) fEXT: BRGi's count source frequency (external clock) n: Value set in BRGi Fig. 12.4.8 Example of transmit timing when transfer data length = 8 bits (when parity enabled, 1 stop bit and selecting CTS function selected) 7902 Group User's Manual 12-45 SERIAL I/O 12.4 Clock asynchronous serial I/O (UART) mode Tc Transfer clock Transmit enable bit Data is set in UARTi transmit buffer register. Transmit buffer empty flag UARTi transmit register UARTi transmit buffer register TENDi Stopped because transmit enable bit = "0" TxDi ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 Transmit register empty flag UARTi transmit interrupt request bit Cleared to "0" when interrupt request is accepted or cleared to "0" by software. The above timing diagram applies when the following conditions are satisfied: Parity disabled 2 stop bits CTS function not selected TENDi: Next transmit conditions are examined when this signal level becomes "H." (TENDi is an internal signal. Accordingly, it cannot be read from the external.) ST: Start bit D0 to D7: Transfer data P: Parity bit ST: Stop bit Tc = 16 (n + 1)/fi or 16 (n + 1)/fEXT fi: BRGi count source frequency (internal clock) fEXT: BRGi count source frequency (external clock) n: Value set in BRGi Fig. 12.4.9 Example of transmit timing when transfer data length = 9 bits (when parity disabled, 2 stop bits selected, CTS function not selected) 12-46 7902 Group User's Manual SERIAL I/O 12.4 Clock asynchronous serial I/O (UART) mode 12.4.5 Method of reception Figure 12.4.10 shows an initial setting example for relevant registers when receiving. Reception is started when all of the following conditions ( and ) have been satisfied: Reception is enabled (receive enable bit = "1"). The start bit (its falling edge) is detected. By connecting the RTSi pin (receiver side) and CTSi pin (transmitter side), the timing of transmission and that of reception can be matched. For details, refer to section "12.4.6 Receive operation." When using interrupts, it is necessary to set the relevant registers to enable interrupts. For details, refer to "CHAPTER 7. INTERRUPTS." Figure 12.4.11 shows processing after reception is completed. 7902 Group User's Manual 12-47 SERIAL I/O 12.4 Clock asynchronous serial I/O (UART) mode AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AA AAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAA AAAA AAAAAAAAAAAA AAAA AAAAAAAAAAAA AAAA AAAAAAAAAAAA AAAAAAAAAAAA A A A AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA UART0 transmit/receive mode register (Address 3016) UART1 transmit/receive mode register (Address 3816) b7 b0 1 Serial I/O mode select bit b2 b1 b0 1 0 0: UART mode (7 bits) 1 0 1: UART mode (8 bits) 1 1 0: UART mode (9 bits) UART0 baud rate register (BRG0) (Address 3116) UART1 baud rate register (BRG1) (Address 3916) b7 b0 Internal/External clock select bit 0: Internal clock 1: External clock Stop bit length select bit 0: 1 stop bit 1: 2 stop bits Odd/Even parity select bit 0: Odd parity 1: Even parity Can be set to "0016" to "FF16." Port P8 direction register (Address 1416) b7 b0 0 0 Pin RxD0 Parity enable bit 0: Parity is disabled. 1: Parity is enabled. Sleep select bit 0: Sleep mode cleared (invalid) 1: Sleep mode selected Set the same transfer data format as that of the transmitter side. Pin RxD1 UART0 receive interrupt control register (Address 7216) UART1 receive interrupt control register (Address 7416) b7 b0 UART0 transmit/receive control register 0 (Address 3416) UART1 transmit/receive control register 0 (Address 3C16) b7 Interrupt priority level select bits When using interrupts, set these bits to one of levels 1 to 7. When disabling interrupts, set these bits to level 0. b0 0 0 BRG count source select bits b1 b0 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) b7 b0 1 CTS/RTS function select bit 0: CTS function selected 1: RTS function selected Receive enable bit 1: Reception enabled CTS/RTS enable bit 0: CTS/RTS function is enabled. 1: CTS/RTS function is disabled. UARTi receive interrupt mode select bit 0: Reception interrupt 1: Reception error interrupt Reception will start when the start bit ('s falling edge) is detected. Serial I/O pin control register (Address AC16) b7 b0 CTS0/RTS0 separate select bit 0: CTS0/RTS0 are used together. 1: CTS0/RTS0 are separated (Note 1). CTS1/RTS1 separate select bit 0: CTS1/RTS1 are used together. 1: CTS1/RTS1 are separated (Note 1). TxD0/P83 switch bit (Note 2) 0: Functions as TxD0. 1: Functions as P83. TxD1/P87 switch bit (Note 2) 0: Functions as TxD1. 1: Functions as P87. Notes 1: The CLKi pin cannot be used when the CTSi/RTSi separation is selected. (Refer to "[Precaution for clock asynchronous serial I/O (UART) mode].") 2: When performing reception only, if these bits are set to "1," the TxDi pin can be used as a programmable I/O port pin. Fig. 12.4.10 Initial setting example for relevant registers when receiving 12-48 7902 Group User's Manual SERIAL I/O 12.4 Clock asynchronous serial I/O (UART) mode [When using interrupts] [When not using interrupts] (Note 1) AAA AAA AAA A UARTi receive interrupt request occurs when reception is completed. Checking completion of reception UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) b7 b0 UARTi receive interrupt 1 Receive complete flag 0 : Reception not completed 1 : Reception completed Checking error UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) b0 b7 1 Framing error flag Parity error flag Error sum flag 0 : No error 1 : Error detected Reading of receive data UART0 receive buffer register (Addresses 3716, 3616) UART1 receive buffer register (Addresses 3F16, 3E16) b15 b8 b7 b0 0 0 0 0 0 0 0 Read out receive data. Checking error UART0 transmit/receive control register 1 (Address 3516) UART1 transmit/receive control register 1 (Address 3D16) b0 b7 1 Overrun error flag 0 : No overrun error 1 : Overrun error detected Processing after reading out receive data Notes 1: When performing the processing after the reception is completed, using an interrupt, be sure to select the receive interrupt (UARTi receive interrupt mode select bit = "0"). 2: This figure shows the bits and registers required for the processing. See Figure 12.4.13 for the change of flag state and the occurrence timing of an interrupt request. Fig. 12.4.11 Processing after reception is completed 7902 Group User's Manual 12-49 SERIAL I/O 12.4 Clock asynchronous serial I/O (UART) mode 12.4.6 Receive operation When the receive enable bit is set to "1," the UARTi enters the receive-enabled state. Then, reception will start when ST ('s falling edge) is detected and a transfer clock is generated. If the RTS function selected, when connecting the RTSi pin to the CTS i pin of the transmitter side, the timing of transmission and that of reception can be matched. If the RTS function selected, the RTSi pin's output level becomes as described below. When the receive enable bit = "0," if one of the following is performed, the RTSi pin's output level becomes "L" and informs of the transmitter side that reception has become enabled: * The receive enable bit is set to "1." * The low-order byte of the UARTi receive buffer register is read out. When the receive enable bit = "1," if the low-order byte of the UARTi receive buffer register is read out, the RTS i pin's output level becomes "L." Accordingly, when performing reception continuously, an overrun occurrence can be avoided because the RTS output level does not become "L" until the receive data is read out. When reception has started, the RTSi pin's output level becomes "H." Figure 12.4.12 shows a connection example. Transmitter side Receiver side TxDi TxDi RxDi RxDi CTSi RTSi Fig. 12.4.12 Connection example The receive operation is described below. The signal input to the RxDi pin is taken into the most significant bit of the UARTi receive register, synchronously with the transfer clock's rising edge. The contents of the UARTi receive register are shifted, bit by bit, to the right. Steps and are repeated at each rising edge of the transfer clock. When one set of data has been prepared, in other words, when the shift operation has been performed several times according to the selected data format, the UARTi receive register's contents are transferred to the UARTi receive buffer register. Simultaneously with step , the receive complete flag is set to "1." Additionally, when the receive interrupt is selected (UARTi receive interrupt mode select bit = "0"), a UARTi receive interrupt request occurs and its interrupt request bit is set to "1." The receive complete flag is cleared to "0" when the low-order byte of the UARTi receive buffer register has been read out. Figure 12.4.13 shows an example of receive timing when the transfer data length = 8 bits. 12-50 7902 Group User's Manual SERIAL I/O 12.4 Clock asynchronous serial I/O (UART) mode BRGi's count source Receive enable bit Stop bit RxDi Start bit D0 D1 D7 Received data taken in Sampled "L" Transfer clock Receive complete flag At falling edge of start bit, the transfer clock is generated and reception started. UARTi receive register UARTi receive buffer register RTSi UARTi receive buffer register's reading out UARTi receive interrupt request bit The above timing diagram applies when the following conditions are satisfied: Parity disabled 1 stop bit RTS function selected Cleared to "0" when interrupt request is accepted or cleared to "0" by software. Fig. 12.4.13 Example of receive timing when transfer data length = 8 bits (when parity disabled, 1 stop bit and RTS function selected) 7902 Group User's Manual 12-51 SERIAL I/O 12.4 Clock asynchronous serial I/O (UART) mode 12.4.7 Processing on detecting error In the UART mode, 3 types of errors can be detected. Each error can be detected when the data in the UARTi receive register is transferred to the UARTi receive buffer register, and the corresponding error flag is set to "1." When any error occurs, the error sum flag is set to "1." Accordingly, presence of errors can be judged by using the error sum flag. Table 12.4.6 lists the conditions for setting each error flag to "1" and method to clear it to "0." Additionally, when the receive error interrupt is selected (UARTi receive interrupt mode select bit = "1"), the UARTi receive interrupt request bit is set to "1" only when each error has occurred. When the receive interrupt is selected (UARTi receive interrupt mode select bit = "0"), the UARTi receive interrupt request bit is set to "1" when reception has been completed or when a framing or parity error has occurred. (Even when an overrun error has occurred, this bit does not change). Table 12.4.6 Conditions for setting each error flag to "1" and method to clear it to "0" Error flag Overrun error flag Framing error flag Parity error flag Error sum flag Conditions for setting Method to clear When the next data is prepared in the * Clear the receive enable bit to "0." UARTi receive register with the receive complete flag = "1" (i.e. data is present in the UARTi receive buffer register). In other words, when the next data is prepared before the contents of the UARTi receive buffer register are read out (Note). When the number of detected stop bits * Clear the receive enable bit to "0." does not match the set number of stop * Read out the low-order byte of the UARTi bits. receive buffer register. When the sum of "1"s in the sum of the * Clear the receive enable bit to "0." parity bit and character bits does not match * Read out the low-order byte of the UARTi the set number of "1"s. receive buffer register. When any error listed above has occurred. * Clear the all error flags, which are overrun, framing and parity error flags. Note: The next data is written into the UARTi receive buffer register. When an error occurs during reception, be sure to initialize the error flag and the UARTi receive buffer register, and then perform reception again. When it is necessary to perform retransmission owing to an error which has occurred on the receiver side during transmission, be sure to set the UARTi transmit buffer register again, and then perform the retransmission. The method to initialize the UARTi receive buffer register and that to set the UARTi transmit buffer register again are described below. (1) Method to initialize UARTi receive buffer register Clear the receive enable bit to "0" (reception disabled). Set the receive enable bit to "1" again (reception enabled). (2) Method to set UARTi transmit buffer register again Clear the serial I/O mode select bits to "000 2" (serial I/O invalid). Set the serial I/O mode select bits again. Set the transmit enable bit to "1" (transmission enabled), and set the transmit data to the UARTi transmit buffer register. 12-52 7902 Group User's Manual SERIAL I/O 12.4 Clock asynchronous serial I/O (UART) mode 12.4.8 Sleep mode This mode is used to transfer data between the specified microcomputers, which are connected by using UARTi. The sleep mode is selected by setting the sleep select bit (bit 7 at addresses 3016 , 3816) to "1" when receiving. In the sleep mode, receive operation is performed when the MSB (D8 when the transfer data = 9-bit length, D 7 when it is 8-bit length, D 6 when it is 7-bit length) of the receive data is "1." Receive operation is not performed when the MSB is "0." (The UARTi receive register's contents are not transferred to the UARTi receive buffer register. Additionally, the receive complete flag and each error flag do not change, and no UARTi receive interrupt request occurs.) The following shows an usage example of the sleep mode when the transfer data = 8-bit length. Be sure to set the same transfer data format for the master and slave microcomputers. Additionally, be sure to select the sleep mode for the slave microcomputers. Then, transmit the data, of which structure is as follows, from the master microcomputer: * Bit 7 = "1" * Bits 6 to 0 indicate the address of the slave microcomputer to be communicated Each slave microcomputer receives the data described in step . (At this time, a UARTi receive interrupt request occurs.) Be sure to check for each slave microcomputer, in the interrupt routine, whether bits 6 to 0 of the receive data match its own address. For the slave microcomputer of which address matches bits 6 to 0 of the receive data, terminate the sleep mode. (Do not terminate the sleep mode for the other slave microcomputers.) By performing steps to , "the microcomputer which performs transfer" is specified. Transmit the data of which bit 7 = "0" from the master microcomputer. (Only one slave microcomputer specified in steps to can receive this data. The other microcomputers do not receive this data.) By repeating step , continuous transfer can be performed between two specific microcomputers. When communicating with another slave microcomputer, perform steps to in order to specify the new slave microcomputer. Master Slave A Slave B Data is transferred between the master microcomputer and one specific slave microcomputer selected from multiple slave microcomputers. Slave C Slave D Fig. 12.4.14 Sleep mode 7902 Group User's Manual 12-53 SERIAL I/O [Precautions for clock asynchronous serial I/O (UART) mode] [Precautions for clock asynchronous serial I/O (UART) mode] 1. When using the CTS0/RTS0 pin, be sure that the D-A2 output enable bit (bit 2 at address 9616 ) = "0" (output disabled). 2. When separating CTSi/RTSi, the CLK i pin cannot be used. Accordingly, when separating CTS i/RTSi in UART mode, be sure to select an internal clock. 3. Writing to the UARTi baud rate register (BRGi) must be performed while transmission/reception halts. 4. When transmitting, be sure to clear the TxD0/P8 3 or TxD1/P8 7 switch bit (bits 2, 3 at address AC16 ) to "0." 12-54 7902 Group User's Manual CHAPTER 13 A-D CONVERTER 13.1 13.2 13.3 13.4 Overview Block description A-D conversion method Absolute accuracy and Differential non-linearity error 13.5 Comparison voltage in 8-bit resolution mode 13.6 One-shot mode 13.7 Repeat mode 13.8 Single sweep mode 13.9 Repeat sweep mode [Precautions for A-D converter] A-D CONVERTER 13.1 Overview 13.1 Overview The A-D conversion is performed in the 8-bit resolution mode or the 10-bit resolution mode. Table 13.1.1 lists the performance specifications of the A-D converter. Table 13.1.1 Performance specifications of A-D converter Item Performance specifications A-D conversion method Successive approximation conversion method Resolution Either of 8-bit or 10-bit resolution can be selected by software. Absolute accuracy 8-bit resolution mode : 2 LSB 10-bit resolution mode : 3 LSB Analog input pin 8 pins (AN0 to AN7) Conversion rate per analog input pin 8-bit resolution mode : 49 AD cycles 10-bit resolution mode : 59 AD cycles AD : A-D converter's operation clock (1) 8-bit resolution mode The input voltage from pin ANi (i = 0 to 7) is A-D converted, and the 8-bit A-D conversion result is stored in A-D register i. (Refer to sections "13.3 A-D conversion method" and "13.5 Comparison voltage in 8-bit resolution mode.") (2) 10-bit resolution mode The input voltage from pin ANi is A-D converted, and the 10-bit A-D conversion result is stored in A-D register i. (Refer to section "13.3 A-D conversion method.") (3) Operation modes The A-D converter is equipped with the following 4 modes. One-shot mode This mode is used to perform the A-D conversion once for a voltage input from one selected analog input pin. Repeat mode This mode is used to perform the A-D conversion repeatedly for a voltage input from one selected analog input pin. Single sweep mode This mode is used to perform the A-D conversion for voltages input from multiple selected analog input pins, one at a time. Repeat sweep mode This mode is used to perform the A-D conversion repeatedly for voltages input from multiple selected analog input pins. 13-2 7902 Group User's Manual A-D CONVERTER 13.2 Block description 13.2 Block description Figure 13.2.1 shows the block diagram of the A-D converter. Registers relevant to the A-D converter are described below. Selection of A-D conversion frequency (1,1) f1 (1,0) (0,1) 1/2 f2 (0,0) 1/2 A-D conversion frequency (AD) select bits 1, 0 VREF connection select bit VREF AVSS AD 0 Resistor ladder network 1 Vref Successive approximation register A-D control register 1 A-D control register 0 A-D register 0 A-D register 1 Comparator A-D register 2 A-D register 3 Decoder A-D register 4 A-D register 5 A-D register 6 A-D register 7 Data bus (odd) Data bus (even) AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7/ADTRG Selector Fig. 13.2.1 Block diagram of A-D converter 7902 Group User's Manual 13-3 A-D CONVERTER 13.2 Block description 13.2.1 A-D control register 0, 1 Figure 13.2.2 shows the structures of the A-D control registers 0 and 1. b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 0 (Address 1E16 ) Bit 0 1 2 3 Function Bit name b2 b1b0 Analog input select bits 0 0 0 : AN0 is selected. (Valid in the one-shot and repeat 0 0 1 : AN1 is selected. 0 1 0 : AN2 is selected. modes.) (Note 1) 0 1 1 : AN3 is selected. 1 0 0 : AN4 is selected. 1 0 1 : AN5 is selected. 1 1 0 : AN6 is selected. 1 1 1 : AN7 is selected. b4 b3 A-D operation mode select bits 4 0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode (Note 2) (Note 3) (Note 4) (Note 5) At reset R/W Undefined RW Undefined RW Undefined RW 0 RW 0 RW RW 5 Trigger select bit 0 : Internal trigger 1 : External trigger (Note 6) 0 6 A-D conversion start bit 0 : A-D conversion halts. 1 : A-D conversion starts. 0 7 A-D conversion frequency ( AD ) See Table 13.2.1. select bit 0 RW (Note 7) 0 RW Notes 1: These bits are invalid in the single sweep and repeat sweep modes. (They may be either "0" or "1.") 2: When using pin AN4, be sure that the pin INT3 select bit (bit 5 at address 9416) = "0." 3: When using pin AN5, be sure that the pin INT4 select bit (bit 6 at address 9416) = "0." 4: When using pin AN6, be sure that the D-A0 output enable bit (bit 0 at address 9616) = "0" (output disabled). 5: When using pin AN 7, be sure that the pin INT2 select bit (bit 4 at address 9416) = "0" and the D-A 1 output enable bit (bit 1 at address 9616) = "0." When using an external trigger, pin AN7 cannot be used as an analog input pin. 6: When using an external trigger, be sure that the pin INT2 select bit (bit 4 at address 94 16) = "0" and the D-A1 output enable bit (bit 1 at address 9616) = "0." 7: When writing to this bit, use the MOVM (MOVMB) or STA (STAB, STAD) instruction. 8: Writing to each bit (except bit 6) of the A-D control register 0 must be performed while the A-D converter halts. Fig. 13.2.2 Structure of A-D control register 0 13-4 7902 Group User's Manual A-D CONVERTER 13.2 Block description A-D control register 1 (Address 1F16) b7 b6 b5 b4 b3 b2 b1 b0 0 Bit Bit name Function At reset R/W 1 RW 1 RW 0 RW 0 RW 1 A-D sweep pin select bits (Valid in the single sweep and repeat sweep modes.) (Note 1) 2 Fix this bit to "0." 3 Resolution select bit 4 A-D conversion frequency (AD) select See Table 13.2.1. bit 1 0 RW 5 0 : Falling edge of the pin ADTRG's input signal External trigger polarity select bit (Valid when external trigger selected.) 1 : Rising edge of the pin ADTRG's input signal 0 RW 6 VREF connection select bit (Note 6) 0 RW 7 The value is "0" at reading. 0 -- 0 b1 b0 0 0 : Pins AN0 and AN1 (2 pins) 0 1 : Pins AN0 to AN3 (4 pins) 1 0 : Pins AN0 to AN5 (6 pins) (Notes 2, 3) 1 1 : Pins AN0 to AN7 (8 pins) (Notes 2 to 5) 0 : 8-bit resolution mode 1 : 10-bit resolution mode 0 : Pin VREF is connected. 1 : Pin VREF is disconnected. Notes 1: These bits are invalid in the one-shot and repeat modes. (They may be either "0" or "1.") 2: When using pin AN4 , be sure that the pin INT3 select bit (bit 5 at address 9416) = "0." 3: When using pin AN5 , be sure that the pin INT4 select bit (bit 6 at address 9416) = "0." 4: When using pin AN6 , be sure that the D-A0 output enable bit (bit 0 at address 9616) = "0" (output disabled). 5: When using pin AN7 , be sure that the pin INT2 select bit (bit 4 at address 94 16) = "0" and the D-A1 output enable bit (bit 1 at address 9616) = "0." When an external trigger is selected, pin AN7 cannot be used as an analog input pin. 6: When this bit is cleared from "1" to "0," be sure to start the A-D conversion or D-A conversion after an interval of 1 s or more has elapsed. 7: Writing to each bit of the A-D control register 1 must be performed while the A-D conversion halts. Fig. 13.2.3 Structure of A-D control register 1 7902 Group User's Manual 13-5 A-D CONVERTER 13.2 Block description (1) Analog input pin select bits (bits 0 to 2 at address 1E 16) These bits are used to select an analog input pin in the one-shot mode or repeat mode. Pins which are not selected as analog input pins serve as programmable I/O port pins. Also, these bits must be specified again if the user switches the operation mode to the one-shot mode or repeat mode after the A-D conversion is performed in the single sweep mode or repeat sweep mode. (2) A-D operation mode select bit (bits 3 and 4 at address 1E 16) These bits are used to select the operation mode of the A-D converter. (3) Trigger select bit (bit 5 at address 1E16 ) This bit is used to select the source of trigger occurrence. (Refer to section "(4) A-D conversion start bit.") (4) A-D conversion start bit (bit 6 at address 1E 16 ) When internal trigger is selected Setting this bit to "1" generates a trigger, causing the A-D converter to start its operation. Clearing this bit to "0" causes the A-D converter to halt its operation. In the one-shot mode or single sweep mode, this bit is cleared to "0" when the A-D conversion is completed. In the repeat mode or repeat sweep mode, the A-D converter continues its operation until this bit is cleared to "0" by software. When external trigger is selected When pin ADTRG 's level changes from "H" to "L" (when the external trigger polarity select bit = "0") or from "L" to "H" (when the external trigger polarity select bit = "1") with this bit = "1," a trigger is generated, causing the A-D converter to start its operation. The A-D converter halts when this bit is cleared to "0." In the one-shot mode or single sweep mode, this bit remains set to "1" even after the A-D conversion is completed. In the repeat mode or repeat sweep mode, the A-D converter continues its operation until this bit is cleared to "0" by software. (5) A-D conversion frequency ( AD ) select bit 0 (bit 7 at address 1E16 ), A-D conversion frequency (AD ) select bit 1 (bit 4 at address 1F16 ) These bits are used to select the operation clock (AD) of the A-D converter. Table 13.2.1 lists the conversion time per one analog input pin. Since the A-D converter's comparator consists of capacity coupling amplifiers, be sure to keep that AD 250 kHz during A-D conversion. Table 13.2.1 Conversion time per one analog input pin A-D conversion frequency (AD) select bit 1 A-D conversion frequency (AD) select bit 0 AD 0 0 1 1 0 1 0 1 f2 divided by 4 f2 divided by 2 f2 f1 Conversion time (s) (Note) fsys = 26 MHz 8-bit resolution mode 10-bit resolution mode 15.08 18.15 7.54 9.07 3.77 4.54 Do not select. 1.88 Note: This applies when the peripheral devices' clock select bit 0, 1 (bits 6, 7 at address BC16 ) = "002." 13-6 7902 Group User's Manual A-D CONVERTER 13.2 Block description (6) A-D sweep pin select bit (bits 0 and 1 at address 1E16 ) These bits are used to select analog input pins in the single sweep mode or repeat sweep mode. Pins which are not selected as analog input pins serve as programmable I/O port pins. (7) Resolution select bit (bit 3 at address 1F16 ) This bit is used to select a resolution. (8) External trigger polarity select bit (bit 5 at address 1F 16 ) When an external trigger is selected, this bit is used to select the polarity of the trigger. (Refer to section "(4) A-D conversion start bit.") (9) V REF connection select bit (bit 6 at address 1F 16 ) When the A-D converter and D-A converter are not used, this bit is used to disconnect the resistor ladder network of the A-D converter from the reference voltage input pin (V REF ). When the resistor ladder network and pin VREF is disconnected, the current is not flowed from pin V REF to resistor ladder network. Accordingly, the power dissipation can be saved. After this bit changes from "1" (V REF disconnect) to "0" (VREF connected), start of the A-D conversion must be 1 s or more later. 7902 Group User's Manual 13-7 A-D CONVERTER 13.2 Block description 13.2.2 A-D register i (i = 0 to 7) Figure 13.2.4 shows the structure of the A-D register i. When the A-D conversion is completed, the conversion result (contents of the successive approximation register) is stored into this register. Each A-D register i corresponds to an analog input pin (ANi). When 8-bit resolution mode is selected A-D register 0 (Addresses 2116, 2016) A-D register 1 (Addresses 2316, 2216) A-D register 2 (Addresses 2516, 2416) A-D register 3 (Addresses 2716, 2616) A-D register 4 (Addresses 2916, 2816) A-D register 5 (Addresses 2B16, 2A16) A-D register 6 (Addresses 2D16, 2C16) A-D register 7 (Addresses 2F16, 2E16) Bit 7 to 0 (b15) b7 (b8) b0 b7 Function Reads an A-D conversion result. 15 to 8 The value is "0" at reading. b0 At reset R/W Undefined RO 0 - When 10-bit resolution mode is selected A-D register 0 (Addresses 2116, 2016) A-D register 1 (Addresses 2316, 2216) A-D register 2 (Addresses 2516, 2416) A-D register 3 (Addresses 2716, 2616) A-D register 4 (Addresses 2916, 2816) A-D register 5 (Addresses 2B16, 2A16) A-D register 6 (Addresses 2D16, 2C16) A-D register 7 (Addresses 2F16, 2E16) Bit 9 to 0 (b15) b7 Function Reads an A-D conversion result. 15 to 10 The value is "0" at reading. Fig. 13.2.4 Structure of A-D register i 13-8 7902 Group User's Manual (b8) b0 b7 b0 At reset R/W Undefined RO 0 - A-D CONVERTER 13.2 Block description 13.2.3 A-D conversion interrupt control register Figure 13.2.5 shows the structure of the A-D conversion interrupt control register. For details about interrupts, refer to "CHAPTER 7. INTERRUPTS." A-D conversion interrupt control register (Address 7016) Bit 0 Bit name Interrupt priority level select bits 1 2 3 Interrupt request bit 7 to 4 Nothing is assigned. b7 b6 b5 b4 b3 b2 b1 b0 Function b2 b1b0 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0 : No interrupt requested 1 : Interrupt requested At reset R/W 0 RW 0 RW 0 RW Undefined RW (Note 1) (Note 2) Undefined -- Notes 1: Clear this bit "0" by software before using an A-D conversion interrupt. 2: When writing to this bit, use the MOVM (MOVMB) or STA (STAB, STAD) instruction. Fig. 13.2.5 Structure of A-D conversion interrupt control register (1) Interrupt priority level select bits (bits 2 to 0) These bits are used to select an A-D conversion interrupt's priority level. When using an A-D conversion interrupt, be sure to select one of the priority levels (1 to 7). When an A-D conversion interrupt request occurs, its priority level is compared with the processor interrupt priority level (IPL). The requested interrupt is enabled only when its priority level is higher than the IPL. (However, this applies when the interrupt disable flag (I) = "0.") To disable an A-D conversion interrupt, set these bits to "000 2" (level 0). (2) Interrupt request bit (bit 3) This bit is set to "1" when an A-D conversion interrupt request has occurred. This bit is automatically cleared to "0" when the A-D conversion interrupt request has accepted. This bit can be set to "1" or cleared to "0" by software. 7902 Group User's Manual 13-9 A-D CONVERTER 13.2 Block description 13.2.4 Port P7 direction register The A-D converter's input pins are multiplexed with the port P7 pins. When using these pins as A-D converter's input pins, be sure to clear the corresponding bits of the port P7 direction register to "0" in order to set these pins to the input mode. Figure 13.2.6 shows the correspondence between the port P7 direction register and the A-D converter's input pins. b7 b6 b5 b4 b3 b2 b1 b0 Port P7 direction register (Address 1116) Bit Function Bit name 0 Pin AN0 1 Pin AN1 0 : Input mode 1 : Output mode When using any of these pins as A-D converter's input pin, be sure to set its corresponding bit to "0." At reset R/W 0 RW 0 RW 0 RW 2 Pin AN2 3 Pin AN3 0 RW 4 Pin AN4 (Pin INT3) 0 RW 5 Pin AN5 (Pin INT4) 0 RW 6 Pin AN6 (Pin DA0) 0 RW 7 Pin AN7/ADTRG (Pin DA1/INT2) 0 RW Note: The pin in ( ) is an I/O pin of another internal peripheral device and is multiplexed with the corresponding port P7 pins. Fig. 13.2.6 Correspondence between port P7 direction register and A-D converter's input pins 13-10 7902 Group User's Manual A-D CONVERTER 13.3 A-D conversion method 13.3 A-D conversion method The A-D converter compares the comparison voltage (V ref), which is internally generated according to the contents of the successive approximation register, with the analog input voltage (VIN ), which is input from the analog input pin (AN i). By reflecting the comparison result on the successive approximation register, V IN is converted into a digital value. When a trigger is generated, the A-D converter performs the following processing: Determining bit 9 of the successive approximation register The A-D converter compares V ref with V IN. At this time, the contents of the successive approximation register is "1000000000 2" (initial value). Bit 9 of the successive approximation register depends on the comparison result as follows: When V ref < V IN , bit 9 = "1" When V ref > V IN, bit 9 = "0" Determining bit 8 of the successive approximation register After setting bit 8 of the successive approximation register to "1," the A-D converter compares Vref with V IN. Bit 8 depends on the comparison result as follows: When V ref < V IN, bit 8 = "1" When V ref > V IN, bit 8 = "0" Determining bits 7 to LSB of the successive approximation register Operation is performed for each of bits 7 to 0 in the 10-bit resolution mode. Operation is performed for each of bits 7 to 2 in the 8-bit resolution mode. When the LSB is determined, the contents of the successive approximation register (in order words, conversion result) are transferred to the A-D register i. V ref is generated according to the latest contents of the successive approximation register. Table 13.3.1 lists the relationship between the successive approximation register's contents and V ref . Tables 13.3.2 and 13.3.3 list the changes of the successive approximation register and V ref during the A-D conversion, respectively. Figure 13.3.1 shows the ideal A-D conversion characteristics in the 10-bit resolution mode. Table 13.3.1 Relationship between successive approximation register's contents and V ref Successive approximation register's contents: n 0 1 to 1023 V ref (V) 0 V REF 1024 x (n - 0.5) V REF: Reference voltage 7902 Group User's Manual 13-11 A-D CONVERTER 13.3 A-D conversion method Table 13.3.2 Change of successive approximation register and Vref during A-D conversion (8-bit resolution) Successive approximation register b9 Change of Vref b0 A-D converter halt 1 0 0 0 0 0 0 0 0 0 VREF [V] 2 1st comparison 1 0 0 0 0 0 0 0 0 0 VREF - VREF [V] 2 2048 2nd comparison n9 1 0 0 0 0 0 0 0 0 3rd comparison n 9 n8 1 0 0 0 0 0 0 0 1st comparison result 2nd comparison result : : *n9 = 1 + VREF 4 VREF VREF - VREF [V] VREF 2 2048 4 *n9 = 0 - 4 + VREF VREF VREF VREF - VREF [V] *n8 = 1 8 VREF 2048 8 4 2 - *n8 = 0 8 : : : : 8th comparison n9 n8 n7 n6 n5 n4 n3 1 0 0 Conversion completed n9 n8 n7 n6 n5 n4 n3 n2 0 0 VREF VREF VREF ...... VREF - VREF [V] 4 8 256 2048 2 Table 13.3.3 Change of successive approximation register and V ref during A-D conversion (10-bit resolution) Successive approximation register b9 Change of Vref b0 A-D converter halt 1 0 0 0 0 0 0 0 0 0 VREF [V] 2 1st comparison 1 0 0 0 0 0 0 0 0 0 VREF - VREF [V] 2048 2 2nd comparison n9 1 0 0 0 0 0 0 0 0 *n9 = 1 1st comparison result 3rd comparison n9 n8 1 0 0 0 0 0 0 0 2nd comparison result : : : : 10th comparison n9 n8 n7 n6 n5 n4 n3 n2 n1 1 Conversion completed n9 n8 n7 n6 n5 n4 n3 n2 n1 n0 13-12 + VREF 4 VREF VREF - VREF [V] 2048 2 4 *n9 = 0 - VREF 4 VREF *n8 = 1 + VREF VREF VREF REF V 8 [V] - 8 2 4 2048 VREF *n8 = 0 - : : 8 VREF VREF VREF ...... VREF VREF [V] - 8 2 4 1024 2048 7902 Group User's Manual A-D CONVERTER 13.3 A-D conversion method A-D conversion result ldeal A-D conversion characteristics 3FF16 3FE16 3FD16 00316 00216 00116 00016 0 VREF 1 1024 VREF 2 1024 VREF 3 1024 VREF VREF VREF 1021 1022 1023 1024 1024 1024 VREF 1024 0.5 VREF Analog input voltage Fig. 13.3.1 Ideal A-D conversion characteristics in 10-bit resolution mode 7902 Group User's Manual 13-13 A-D CONVERTER 13.4 Absolute accuracy and Differential non-linearity error 13.4 Absolute accuracy and Differential non-linearity error The A-D converter's accuracy is described below. Refer to section "Appendix 10.4 A-D converter standard characteristics," also. 13.4.1 Absolute accuracy The absolute accuracy is the difference expressed in the LSB between the actual A-D conversion result and the output code of an A-D converter with ideal characteristics. (See Figure 13.4.1 for more details.) The analog input voltage at measurement of the absolute accuracy is assumed to be the mid point of the analog input voltage width that outputs the same output code from an A-D converter with ideal characteristics. For example, in the case of the 10-bit resolution mode, when VREF = 5.12 V, 1 LSB width is 5 mV, and 0 mV, 5 mV, 10 mV, 15 mV, 20 mV, ... are selected as the analog input voltages. The absolute accuracy = 3 LSB indicates that when the analog input voltage is 25 mV, the output code expected from an ideal A-D conversion characteristics is "00516 ," but the actual A-D conversion result is between "00216" to "008 16." The absolute accuracy includes the zero error and the full-scale error. The absolute accuracy degrades when VREF is lowered. Any of the output codes for analog input voltages in the range from VREF to AVcc is "3FF 16 ." Output code (A-D conversion result) 00B16 00A16 00916 +3 LSB 00816 Ideal A-D conversion characteristics 00716 00616 00516 00416 00316 00216 -3 LSB 00116 00016 0 5 10 15 20 25 30 35 40 45 50 Analog input voltage (mV) Fig. 13.4.1 Absolute accuracy of A-D converter (10-bit resolution mode) 13-14 7902 Group User's Manual 55 A-D CONVERTER 13.4 Absolute accuracy and Differential non-linearity error 13.4.2 Differential non-linearity error The differential non-linearity error indicates the difference between the 1 LSB step width (the ideal analog input voltage width while the same output code is expected to output) of an A-D converter with ideal characteristics and the actual measured step width (the actual analog input voltage width while the same output code is output). (See Figure 13.4.2 for more details.) For example, in the case of the 10-bit resolution mode and VREF = 5.12 V, the 1 LSB width of an A-D converter with ideal characteristics is 5 mV; but if the differential non-linearity error is 1 LSB, the actual measured 1 LSB width is in the range from 0 to 10 mV. Output code (A-D conversion result) 00916 1 LSB width with ideal A-D conversion characteristics 00816 00716 00616 00516 00416 00316 00216 00116 Differential non-linearity error 00016 0 5 10 15 20 25 30 35 40 45 Analog input voltage (mV) Fig. 13.4.2 Differential non-linearity error (10-bit resolution mode) 7902 Group User's Manual 13-15 A-D CONVERTER 13.5 Comparison voltage in 8-bit resolution mode 13.5 Comparison voltage in 8-bit resolution mode In the 8-bit resolution mode, which is selected by the resolution select bit, the high-order 8 bits of the 10bit successive approximation register are treated as the A-D conversion result. Accordingly, when compared with the 8-bit A-D converter, a comparison reference voltage is different by 3V REF /2048. (Refer to the underlined portions in Table 13.5.1). The difference of the output code change point is generated as shown in Figure 13.5.1. Table 13.5.1 Comparison voltage M37902's 8-bit resolution mode 8-bit A-D converter V REF V REF n- 0.5 8 2 2 10 V REF V REF n- 0.5 8 2 28 Comparison voltage Vref V REF : Reference voltage n : Contents of successive approximation register 8-bit A-D converter's ideal characteristics (when VREF = 5.12 V) Output code (A-D conversion result) 02 01 00 10 30 Analog input voltage (mV) M37902's A-D converter's ideal characteristics (when VREF = 5.12 V) Output code (A-D conversion result) 10-bit 8-bit resolution resolution mode mode 09 08 02 07 06 05 04 01 03 02 01 00 00 10-bit resolution mode 8-bit resolution mode (Note) (Note) 17.5 37.5 Note: Difference of output code change point VREF: Reference voltage Fig. 13.5.1 Difference of output code change point 13-16 7902 Group User's Manual Analog input voltage (mV) A-D CONVERTER 13.6 One-shot mode 13.6 One-shot mode In the one-shot mode, the A-D conversion for an input voltage from one selected analog input pin is performed once, and an A-D conversion interrupt request occurs at completion of A-D conversion. 13.6.1 Settings for one-shot mode Figure 13.6.1 shows an initial setting example for related registers in the one-shot mode. When using an interrupt, it is necessary to set the related registers to enable an interrupt. Refer to "CHAPTER 7. INTERRUPTS" for more details. A-D control registers 0 and 1 b7 b0 b7 0 0 0 A-D control register 0 (Address 1E16) b0 0 0 Analog input pin select bits A-D control register 1 (Address 1F16) Resolution select bit 0 : 8-bit resolution mode 1 : 10-bit resolution mode b2 b1b0 0 0 0 : AN0 selected 0 0 1 : AN1 selected 0 1 0 : AN2 selected 0 1 1 : AN3 selected 1 0 0 : AN4 selected 1 0 1 : AN5 selected 1 1 0 : AN6 selected 1 1 1 : AN7 selected A-D conversion frequency (AD) select bit 1 See Table 13.2.1. External trigger polarity select bit 0 : Falling edge of pin ADTRG's input signal 1 : Rising edge of pin ADTRG's input signal One-shot mode VREF connection select bit 0 : Pin VREF is connected. Trigger select bit 0 : Internal trigger 1 : External trigger A-D conversion start bit 0 : A-D conversion halts. A-D conversion frequency (AD) select bit 0 See Table 13.2.1. X : It may be either "0" or "1." Interrupt priority level b7 b0 A-D conversion interrupt control register (Address 7016) 0 Interrupt priority level select bits Set the level to one of 1 through 7 when using this interrupt. Set the level 0 when disabling interrupts. Interrupt request bit "0" : No interrupt requested Port P7 direction register b7 b0 Port P7 direction register (Address 1116) AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Set A-D conversion start bit to "1." b7 b0 A-D control register 0 (Address 1E16) 1 A-D conversion start bit Selecting external trigger Input an external trigger to pin ADTRG (falling edge/ rising edge). Setting internal trigger Clear the bits corresponding to analog input pins to "0." Clear bit 7 to "0" when selecting an external trigger. Trigger generated Operation starts. Note: Writing to the following must be performed during the A-D conversion halts (berore an trigger is generated). * Each bit of the A-D control register 0 (except bit 6) * Each bit of the A-D control register 1 Fig. 13.6.1 Initial setting example for related registers in one-shot mode 7902 Group User's Manual 13-17 A-D CONVERTER 13.6 One-shot mode 13.6.2 One-shot mode operation (1) When an internal trigger is selected The A-D converter starts its operation when the A-D conversion start bit is set to "1." The A-D conversion is completed after 49 cycles of AD in the 8-bit resolution mode, or 59 cycles of AD in the 10-bit resolution mode. Then, the contents of the successive approximation register (conversion result) are transferred to the A-D register i. At the same time as step , the A-D conversion interrupt request bit is set to "1." The A-D conversion start bit is cleared to "0," and the A-D converter halts. (2) When an external trigger is selected The A-D converter starts its operation when the input level to pin AD TRG changes from "H" to "L" (when the external trigger polarity select bit = "0") or from "L" to "H" (when the external trigger polarity select bit = "1") while the A-D conversion start bit = "1." The A-D conversion is completed after 49 cycles of AD in the 8-bit resolution mode, or 59 cycles of AD in the 10-bit resolution mode. Then, the contents of the successive approximation register (conversion result) are transferred to the A-D register i. At the same time as step , the A-D conversion interrupt request bit is set to "1." The A-D converter halts. The A-D conversion start bit remains set to "1" after step . Accordingly, the operation of the A-D converter can be performed again from step if an trigger is generated (the level at pin AD TRG changes from "H" to "L" or from "L" to "H.") Also, if an trigger is generated during the operation of A-D converter, the operation at that point is cancelled and is restarted from step . Figure 13.6.2 shows the conversion operation in the one-shot mode. Trigger generated Conversion result Convert input voltage at pin ANi. A-D register i A-D conversion interrupt request occurs. A-D converter halts. Fig. 13.6.2 Conversion operation in one-shot mode 13-18 7902 Group User's Manual A-D CONVERTER 13.7 Repeat mode 13.7 Repeat mode In the repeat mode, the A-D conversion for an input voltage from one selected analog input pin is performed repeatedly. In this mode, no A-D conversion interrupt request occurs. Additionally, the A-D conversion start bit (bit 6 at address 1E 16 ) remains set to "1" until it is cleared to "0" by software, and the A-D converter repeates its operation while the A-D conversion start bit = "1." 13.7.1 Settings for repeat mode Figure 13.7.1 shows an initial setting example for related registers in the repeat mode. A-D control registers 0 and 1 b7 b7 b0 0 0 1 A-D control register 0 (Address 1E16) b0 0 0 Analog input pin select bits A-D control register 1 (Address 1F16) Resolution mode select bit 0 : 8-bit resolution mode 1 : 10-bit resolution mode b2 b1 b0 0 0 0 : AN0 selected 0 0 1 : AN1 selected 0 1 0 : AN2 selected 0 1 1 : AN3 selected 1 0 0 : AN4 selected 1 0 1 : AN5 selected 1 1 0 : AN6 selected 1 1 1 : AN7 selected A-D conversion frequency (AD) select bit 1 See Table 13.2.1. External trigger polarity select bit 0 : Falling edge of pin ADTRG's input signal 1 : Rising edge of pin ADTRG's input signal Repeat mode VREF connection select bit 0 : Pin VREF is connected. Trigger select bit 0 : Internal trigger 1 : External trigger : It may be either "0" or "1." A-D conversion start bit 0 : A-D conversion halts. A-D conversion frequency (AD) select bit 0 See Table 13.2.1. Port P7 direction register b7 b0 Port P7 direction register (Address 1116) AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Set A-D conversion start bit to "1." b7 b0 A-D control register 0 (Address 1E16) 1 Clear the bits corresponding to analog input pins to "0." Clear bit 7 to "0" when selecting an external trigger. A-D conversion start bit Selecting external trigger Input an external trigger to pin ADTRG (falling edge/ rising edge). Note: Writing to the following must be performed during the A-D conversion halts (berore an trigger is generated). * Each bit of the A-D control register 0 (except bit 6) * Each bit of the A-D control register 1 Setting internal trigger Trigger generated Operation starts. Fig. 13.7.1 Initial setting example for related registers in repeat mode 7902 Group User's Manual 13-19 A-D CONVERTER 13.7 Repeat mode 13.7.2 Repeat mode operation (1) When an internal trigger is selected The A-D converter starts its operation when the A-D conversion start bit is set to "1." The 1st A-D conversion is completed after 49 cycles of AD in the 8-bit resolution mode, or 59 cycles of AD in the 10-bit resolution mode. Then, the contents of the successive approximation register (conversion result) are transferred to the A-D register i. The A-D converter repeats its operation until the A-D conversion start bit is cleared to "0" by software. The conversion result is transferred to the A-D register i each time the conversion is completed. (2) When an external trigger is selected The A-D converter starts its operation when the input level at pin ADTRG changes from "H" to "L" (when the external trigger polarity select bit = "0") or from "L" to "H" (when the external trigger polarity select bit = "1") while the A-D conversion start bit = "1." The 1st A-D conversion is completed after 49 cycles of AD in the 8-bit resolution mode, or 59 cycles of AD in the 10-bit resolution mode. Then, the contents of the successive approximation register (conversion result) are transferred to the A-D register i. The A-D converter repeates its operation until the A-D conversion start bit is cleared to "0" by software. The conversion result is transferred to the A-D register i each time the conversion is completed. If an trigger is generated (the level at pin AD TRG changes from "H" to "L" or from "L" to "H.") during the operation of the A-D converter, the operation at that point is cancelled and is restarted from step . Figure 13.7.2 shows the conversion operation in the repeat mode. Trigger generated Conversion result Convert input voltage at pin ANi. Fig. 13.7.2 Conversion operation in repeat mode 13-20 7902 Group User's Manual A-D register i A-D CONVERTER 13.8 Single sweep mode 13.8 Single sweep mode In the single sweep mode, the A-D conversions for the input voltages from multiple selected analog input pins are performed, one at a time. The A-D conversion is performed in ascending sequence from pin AN 0 to pin AN7. An A-D conversion interrupt request occurs when the A-D conversions for all selected input pins are completed. 13.8.1 Settings for single sweep mode Figure 13.8.1 shows an initial setting example for related registers in the single sweep mode. When using an interrupt, it is necessary to set the related registers to enable an interrupt. Refer to "CHAPTER 7. INTERRUPTS" for more details. A-D control registers 0 and 1 b7 b0 0 1 0 b7 A-D control register 0 (Address 1E16) b0 0 0 A-D control register 1 (Address 1F16) A-D sweep pin select bits 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) Single sweep mode Trigger select bit 0 : Internal trigger 1 : External trigger A-D conversion start bit 0 : A-D conversion halts. Resolution select bit 0 : 8-bit resolution mode 1 : 10-bit resolution mode A-D conversion frequency (AD) select bit 0 See Table 13.2.1. A-D conversion frequency (AD) select bit 1 See Table 13.2.1. External trigger polarity select bit 0 : Falling edge of pin ADTRG's input signal 1 : Rising edge of pin ADTRG's input signal VREF connection select bit 0 : Pin VREF is connected. : It may be either "0" or "1." Interrupt priority level b7 b0 A-D conversion interrupt control register 0 (Address 7016) 0 Interrupt priority level select bits Set the level to one of 1 through 7 when using this interrupt. Set the level 0 when disabling interrupts. Interrupt request bit "0" : No interrupt requested. Port P7 direction register b7 b0 Port P7 direction register (Address 1116) AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Set A-D conversion start bit to "1." b7 b0 A-D control register 0 (Address 1E16) 1 A-D conversion start bit Selecting external trigger Input an external trigger to pin ADTRG (falling edge/ rising edge). Setting internal trigger Clear the bits corresponding to analog input pins to "0." Clear bit 7 to "0" when selecting an external trigger. Trigger generated Operation starts. Note: Writing to the following must be performed during the A-D conversion halts (berore an trigger is generated). * Each bit of the A-D control register 0 (except bit 6) * Each bit of the A-D control register 1 Fig. 13.8.1 Initial setting example for related registers in single sweep mode 7902 Group User's Manual 13-21 A-D CONVERTER 13.8 Single sweep mode 13.8.2 Single sweep mode operation (1) When an internal trigger is selected The A-D converter starts its operation for the input voltage at pin AN0 when the A-D conversion start bit is set to "1." The A-D conversion for the input voltage at pin AN 0 is completed after 49 cycles of AD in the 8bit resolution mode, or 59 cycles of AD in the 10-bit resolution mode. Then, the contents of the successive approximation register (conversion result) are transferred to the A-D register 0. The A-D conversions for all selected analog input pins are performed. The conversion result is transferred to the corresponding A-D register i each time when the A-D conversion per one pin is completed. When step is completed, the A-D conversion interrupt request bit is set to "1." The A-D conversion start bit is cleared to "0," and the A-D converter halts. (2) When an external trigger is selected The A-D converter starts its operation for the input voltage at pin AN0 when the input level at pin ADTRG changes from "H" to "L" (when the external trigger polarity select bit = "0") or from "L" to "H" (when the external trigger polarity select bit = "1") while the A-D conversion start bit = "1." The A-D conversion for the input voltage at pin AN 0 is completed after 49 cycles of AD in the 8bit resolution mode, or 59 cycles of AD in the 10-bit resolution mode. Then, the contents of the successive approximation register (conversion result) are transferred to the A-D register 0. The A-D conversion for all selected analog input pins are performed. The conversion result is transferred to the A-D register i each time each when the A-D conversion per one pin is completed. When step is completed, the A-D conversion interrupt request bit is set to "1." The A-D conversion halts. The A-D conversion start bit remains set to "1" after step . Accordingly, the operation of the A-D converter can be performed again from step if an trigger is generated (the level at pin ADTRG changes from "H" to "L" or from "L" to "H.") If an trigger is generated during the operation of the A-D converter, the operation at that point is cancelled and is restarted from step . Figure 13.8.2 shows the conversion operation in the single sweep mode. Trigger generated Convert input voltage at pin AN0. Conversion result Convert input voltage at pin AN1. Conversion result Convert input voltage at pin ANi. Conversion result A-D register 0 A-D register 1 A-D register i A-D converter interrupt request occurs. A-D converter halts. Fig. 13.8.2 Conversion operation in single sweep mode 13-22 7902 Group User's Manual A-D CONVERTER 13.9 Repeat sweep mode 13.9 Repeat sweep mode In the repeat sweep mode, the A-D conversions for input voltages from multiple selected analog input pins are performed repeatedly. The A-D conversion is performed in ascending sequence from pin AN0 to pin AN7. In this mode, no A-D conversion interrupt request occurs. Additionally, the A-D conversion start bit (bit 6 at address 1E16 ) remains set to "1" until it is cleared to "0" by software, and the A-D converter repeates its operation while the A-D conversion start bit = "1." 13.9.1 Settings for repeat sweep mode Figure 13.9.1 shows an initial setting example for related registers in the repeat sweep mode. A-D control registers 0 and 1 b7 b0 0 1 1 b7 A-D control register 0 (Address 1E16) b0 0 0 A-D control register 1 (Address 1F16) A-D sweep pin select bits 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) Repeat sweep mode Trigger select bit 0 : Internal trigger 1 : External trigger Resolution select bit 0 : 8-bit resolution mode 1 : 10-bit resolution mode A-D conversion start bit 0 : A-D conversion halts. A-D conversion frequency (AD) select bit 0 See Table 13.2.1. A-D conversion frequency (AD) select bit 1 See Table 13.2.1. External trigger polarity select bit 0 : Falling edge of pin ADTRG's input signal 1 : Rising edge of pin ADTRG's input signal VREF connection select bit 0 : Pin VREF is connected. : It may be either "0" or "1." Port P7 direction register b7 b0 Set A-D conversion start bit to "1." Port P7 direction register (Address 1116) AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Clear the bits corresponding to analog input pins to "0." Clear bit 7 to "0" when selecting an external trigger. b7 b0 A-D control register 0 (Address 1E16) 1 A-D conversion start bit Selecting external trigger Input an external trigger to pin ADTRG (falling edge/ rising edge) Setting internal trigger Note: Writing to the following must be performed during the A-D conversion halts (berore an trigger is generated). * Each bit of the A-D control register 0 (except bit 6) * Each bit of the A-D control register 1 Trigger generated Operation starts. Fig. 13.9.1 Initial setting example for related registers in repeat sweep mode 7902 Group User's Manual 13-23 A-D CONVERTER 13.9 Repeat sweep mode 13.9.2 Repeat sweep mode operation (1) When an internal trigger is selected The A-D converter starts its operation for the input voltage at pin AN 0 when the A-D conversion start bit is set to "1." The A-D conversion for the input voltage at pin AN 0 is completed after 49 cycles of AD in the 8bit resolution mode, or 59 cycles of AD in the 10-bit resolution mode. Then, the contents of the successive approximation register (conversion result) are transferred to the A-D register 0. The A-D conversions for all selected analog input pins are performed. The conversion result is transferred to the correponding A-D register i each time when the A-D conversion per one pin is completed. The A-D conversions for all selected analog input pins are performed again. The A-D converter repeates its operation until the A-D conversion start bit is cleared to "0" by software. (2) When an external trigger is selected The A-D converter starts its operation for the input voltage at pin AN 0 when the input level at pin ADTRG changes from "H" to "L" (when the external trigger polarity select bit = "0") or from "L" to "H" (when the external trigger polarity select bit = "1") while the A-D conversion start bit = "1." The A-D conversion for the input voltage at pin AN 0 is completed after 49 cycles of AD in the 8bit resolution mode, or 59 cycles of AD in the 10-bit resolution mode. Then, the contents of the successive approximation register (conversion result) are transferred to the A-D register 0. The A-D conversions for all selected analog input pins is performed. The conversion result is transferred to the correponding A-D register i each time when the A-D conversion per one pin is completed. The A-D conversion for all selected analog input pins are performed again. The A-D converter repeates its operation until the A-D conversion start bit is cleared to "0" by software. When the level at pin AD TRG changes from "H" to "L" or from "L" to "H" during the operation of the A-D converter, the operation at that point is cancelled and is restarted from step . Figure 13.9.2 shows the conversion operation in the repeat sweep mode. Trigger generated Conversion result Convert input voltage at pin AN0. Convert input voltage at pin AN1. Conversion result Conversion result Convert input voltage at pin ANi. Fig. 13.9.2 Conversion operation in repeat sweep mode 13-24 7902 Group User's Manual A-D register 0 A-D register 1 A-D register i A-D CONVERTER [Precautions for A-D converter] [Precautions for A-D converter] 1. Be sure to clear the VREF connection select bit to "0." 2. Writing to the following must be performed before a trigger is generated (in other words, while the A-D converter halts). * Each bit of the A-D control register 0, except bit 6 * Each bit of the A-D control register 1 Especially, when any instruction which clears the V REF connection select bit from "1" to "0" has been executed (in other words, the resistor ladder network is connected with pin VREF by this instruction), the occurrence of an trigger must be performed after an interval of 1 s or more has elapsed. 3. When an external trigger is selected, pin AN 7/AD TRG is disconnected from the comparator. Accordingly, pin AN 7/AD TRG cannot serve as an analog input pin. When pin AN 7 is selected as analog input pin while an external trigger is selected, an undefined value is stored into the A-D register 7 even though the A-D converter operates. 4. When using pin AN 4, be sure that the pin INT 3 select bit (bit 5 at address 9416 ) = "0." When using pin AN 5, be sure that the pin INT 4 select bit (bit 6 at address 94 16) = "0." When using pin AN 6, be sure that the D-A 0 output enable bit (bit 0 at address 9616 ) = "0" (output disabled). When using pin AN 7/AD TRG, be sure that the pin INT 2 select bit (bit 4 at address 9416 ) = "0" and the D-A 1 output enable bit (bit 1 at address 96 16) = "0." 5. Refer to section "Appendix. 7 Countermeasures against noise" when using the A-D converter. 7902 Group User's Manual 13-25 A-D CONVERTER [Precautions for A-D converter] MEMORANDUM 13-26 7902 Group User's Manual CHAPTER 14 D-A CONVERTER 14.1 Overview 14.2 Block description 14.3 D-A conversion method 14.4 Setting method 14.5 Operation description [Precautions for D-A converter] D-A CONVERTER 14.1 Overview, 14.2 Block description 14.1 Overview The M37902 is provided with three independent D-A converters of the R-2R type with 8-bit resolution. These D-A converters convert the values loaded in the D-A registers i (i = 0 to 2) to analog voltages and output them from pin DA i. 14.2 Block description Figure 14.2.1 shows the block diagram of the D-A converter. The registers related to the D-A converter are described below. AA AA Data bus VREF connection select bit VREF 0 1 AVSS D-A register i (i = 0 to 2) (Addresses 9816 to 9A16 ) R-2R ladder network D-Ai output enable bit DAi Fig. 14.2.1 D-A converter block diagram 14-2 7902 Group User's Manual D-A CONVERTER 14.2 Block description 14.2.1 D-A control register Figure 14.2.2 shows the structure of the D-A control register. Pin DAi (i = 0 to 2) serves as the analog voltage output pin of the D-A converter. Since pin DA i is equipped with no internal buffer amplifier, it is necessary to connect a buffer amplifier externally to pin DA i, if this pin is needed to be connected with a low-impedance load. Pin DA i is multiplexed with an analog input, serial I/O, or external interrupt input pin. When any of the D-A i output enable bits is set to "1" (output enabled), the corresponding pin is used only as pin DA i, not as any other multiplexed input/output pin (including programmable I/O port pin). b7 b6 b5 b4 b3 b2 b1 b0 D-A control register (Address 9616 ) Bit Function Bit name At reset R/W 0 D-A0 output enable bit 0: Output is disabled. 1: Output is enabled. (Notes 1, 2) 0 RW 1 D-A1 output enable bit 0: Output is disabled. 1: Output is enabled. (Notes 1, 2) 0 RW 2 D-A2 output enable bit 0: Output is disabled. 1: Output is enabled. (Notes 1, 2) 0 RW Undefined -- 7 to 3 Nothing is assigned. Notes 1: Pin DAi is multiplexed with analog input pin, serial I/O pin, and external interrupt input pin. When a D-Ai output enable bit = "1" (in other words, output is enabled.), however, the corresponding pin cannot function as any other multiplexed input/ output pin (including programmable I/O port pin). 2: When not using the D-A converter, be sure to clear the contents of this bit to "0." Fig. 14.2.2 Structure of D-A control register (1) D-Ai output enable bits (Bits 0 to 2) Setting any of the D-Ai output enable bits to "1" (output enabled) allows the corresponding pin DA i to output D-A converted analog voltage, regardless of the contents of the corresponding bits of the port P7 and P8 registers. 14.2.2 D-A Register i (i = 0 to 2) Each pin DAi outputs the analog voltage corresponding to the value loaded in the D-A register i. Figure 14.2.3 shows the structure of the D-A register i. b7 b0 D-A register i (i = 0 to 2) (Addresses 98 16 to 9A 16) Function At reset R/W Any value from 0016 through FF 16 can be set (Note), and this value is D-A converted and is output. 0 RW Bit 7 to 0 Note: When not using the D-A converter, be sure to clear the contents of these bits to "0016." Fig. 14.2.3 Structure of the D-A register i 7902 Group User's Manual 14-3 D-A CONVERTER 14.2 Block description 14.2.3 A-D control register 1 Figure 14.2.4 shows the structure of the A-D control register 1. b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 1 (Address 1F16 ) Bit 0 At reset R/W A-D sweep pin select bits (Valid in the single sweep and repeat 0 0 : Pins AN0 and AN1 (2 pins) 0 1 : Pins AN0 to AN3 (4 pins) sweep modes.) (Note 1) 1 0 : Pins AN0 to AN5 (6 pins) (Notes 2, 3) 1 1 : Pins AN0 to AN7 (8 pins) (Notes 2 to 5) 1 RW 1 RW 2 Fix this bit to "0." 0 RW 3 Resolution select bit 0 RW 4 A-D convertion frequency (AD) select bit 1 See Table 13.2.1. 0 RW 5 0 : Falling edge of the pin ADTRG's input signal External trigger polarity select bit 1 : Rising edge of the pin ADTRG's input signal (Valid when external trigger is selected.) 0 : Pin VREF is connected. VREF connection select bit (Note 6) 1 : Pin VREF is not connected. 0 RW 0 RW The value is "0" at reading. 0 -- 0 1 6 7 Bit name Function b1 b0 0 : 8-bit resolution mode 1 : 10-bit resolution mode Notes 1: These bits are invalid in the one-shot and repeat modes. (They may be either "0" or "1.") 2: When using pin AN4, be sure that the pin INT3 select bit (bit 5 at address 9416) = "0." 3: When using pin AN5, be sure that the pin INT4 select bit (bit 6 at address 9416) = "0." 4: When using pin AN6, be sure that the D-A0 output enable bit (bit 0 at address 9616) = "0" (output disabled). 5: When using pin AN7 , be sure that the pin INT2 select bit (bit 4 at address 9416) = "0" and the D-A1 output enable bit (bit 1 at address 9616) = "0." When an external trigger is selected, pin AN7 cannot be used as an analog input pin. 6: When this bit is cleared from "1" to "0," be sure to start the A-D conversion or D-A conversion after an interval of 1 s or more has elapsed. 7: Writing to each bit of the A-D control register 1 must be performed while the A-D conversion halts. Fig.14.2.4 Structure of A-D control register 1 (1) V REF connection select bit (Bit 6) This bit is used to disconnect the ladder network of the D-A converters from the reference voltage input pin (V REF) when A-D and D-A converters are not used. Disconnecting the ladder network from pin VREF prevents the current flow from pin V REF to the network to save the current consumption. When this bit is cleared from "1" (VREF disconnected) to "0" (VREF connected), start D-A conversion after 1 s or more has elapsed. 14-4 7902 Group User's Manual D-A CONVERTER 14.3 D-A conversion method 14.3 D-A conversion method The reference voltage VREF is divided according to the value loaded in the D-A register i, and it is output as an analog voltage from pin DA i. Figure 14.3.1 shows the equivalent circuit diagram of the D-A converter. D-Ai output enable bit 0 DAi R 1 2R R 2R R 2R R 2R MSB D-A register i AVSS VREF 0 R 2R R 2R R 2R 2R 2R LSB 1 0 1 VREF connection select bit Note: In this case, the value of D-A register is "2A16." Fig. 14.3.1 Equivalent circuit diagram of D-A converter 7902 Group User's Manual 14-5 D-A CONVERTER 14.4 Setting method, 14.5 Operation description 14.4 Setting method Figure 14.4.1 shows an initial setting example of registers related to the D-A converter. AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAA AAA Setting of a value to D-A register i b7 b0 D-A register 0 (Address 9816) D-A register 1 (Address 9916) D-A register 2 (Address 9A16) A value (0016 to FF16) to be D-A converted is set. Connection with VREF b7 b0 0 A-D control register1 (Address 1F16) 0 VREF connection select bit Setting of the D-Ai output enable bit to "1". b7 b0 D-A control register (Address 9616) D-A0 output enable bit D-A1 output enable bit D-A2 output enable bit Analog voltage output started Fig. 14.4.1 Initial setting example of registers related to D-A converter 14.5 Operation description When any of the D-Ai output enable bits is set to "1," the value loaded in the D-A register i is converted to an analog voltage, and the analog voltage is output from pin DA i. The relationship between the analog output voltage V and value n, which has been loaded in the D-A register i, can be expressed as follows : V = V REF n (n = 0 to 255) 256 V REF : Reference voltage 14-6 7902 Group User's Manual D-A CONVERTER [Precautions for D-A converter] [Precautions for D-A converter] 1. Be sure to clear the V REF connection select bit to "0." 2. When the instruction of clearing the V REF connection select bit from "1" to "0" is executed (i.e., a ladder network is connected with pin VREF), be sure to enable the D-A i output after 1 s or more has elapsed. 3. Pin DA i is multiplexed with an analog input, serial I/O, or external interrupt input pin. When any of the D-Ai output enable bits is set to "1" (output enabled), the corresponding pin is used as pin DAi , not as any other multiplexed input/output pin (including programmable I/O port pin). 4. When not using the D-A converter, be sure to do as follows: * Clear the D-Ai (i = 0 to 2) output enable bit (bits 0 to 2 at address 96 16 ) to "0." * Clear the contents of the D-A register i (addresses 9816 to 9A16 ) to "00 16 ." 7902 Group User's Manual 14-7 D-A CONVERTER [Precautions for D-A converter] MEMORANDUM 14-8 7902 Group User's Manual CHAPTER 15 WATCHDOG TIMER 15.1 Block description 15.2 Operation description [Precautions for watchdog timer] WATCHDOG TIMER 15.1 Block description The watchdog timer functions as follows: Detects a program runaway. At stop mode termination, measures a certain time after oscillation starts. (Refer to section "5.3 Stop mode.") 15.1 Block description Figure 15.1.1 shows the block diagram of the watchdog timer, and registers relevant to the watchdog timer are described below. Access to external area HLDA f2 Wf32 1 1/16 Wait mode 1/16 Watchdog timer frequency select bit Wf512 Divided f(XIN) 0 fX16 fX32 fX64 fX128 Watchdog timer interrupt request Watchdog timer Stop mode "FFF16" is set. Disables watchdog timer (Note). Watchdog timer clock source select bits at STP termination Writing to watchdog timer register RESET STP instruction * Watchdog timer register: address 6016 * Watchdog timer frequency select register: bit 0 at address 6116 * Watchdog timer clock source select bits at STP termination: bits 7, 6 at address 6116 When the most significant bit of the watchdog timer becomes "0," this signal will be generated. Note: During the stop mode and until the stop mode is terminated, setting for disabling the watchdog timer is ignored. (Refer to section "15.1.3 Particular function select register 2.") Fig. 15.1.1 Block diagram of watchdog timer 15-2 7902 Group User's Manual WATCHDOG TIMER 15.1 Block description 15.1.1 Watchdog timer The watchdog timer is a 12-bit counter where the count source which is selected with the watchdog timer frequency select bit (bit 0 at address 61 16 ) is counted down. A value of "FFF16" is automatically set in the watchdog timer if any of the following conditions is satisfied. An arbitrary value cannot be set to the watchdog timer. When dummy data is written to the watchdog timer register. (See Figure 15.1.2.) When the most significant bit of watchdog timer becomes "0." When the STP instruction is executed. (Refer to section "16.3 Stop mode.") At reset b7 b0 Watchdog timer register (Address 6016 ) Bit 7 to 0 Function At reset Initializes the watchdog timer. Undefined When dummy data has been written to this register, the watchdog timer's value is initialized to "FFF16" (dummy data: 0016 to FF16). R/W -- Fig. 15.1.2 Structure of watchdog timer register 15.1.2 Watchdog timer frequency select register Figure 15.1.3 shows the structure of the watchdog timer frequency select register. b7 b6 b5 b4 b3 b2 b1 b0 Watchdog timer frequency select register (Address 6116) Bit 0 5 to 1 6 7 Bit name Watchdog timer frequency select bit Nothing is assigned. Function 0 : Wf512 1 : Wf32 Watchdog timer clock source 0 0 : fX32 select bits at STP termination 0 1 : fX16 1 0 : fX128 1 1 : fX64 b7 b6 At reset R/W 0 RW Undefined -- 0 RW 0 RW Fig. 15.1.3 Structure of watchdog timer frequency select register (1) Watchdog timer frequency select bit (bit 0) This bit is used to select a count source of the watchdog timer. (2) Watchdog timer clock source select bits at STP termination (bits 7, 6) These bits are used to select a count source at stop mode termination. For details of the operation at stop mode termination, refer to section "16.3 Stop mode." 7902 Group User's Manual 15-3 WATCHDOG TIMER 15.1 Block description 15.1.3 Particular function select register 2 When not using the watchdog timer, this register can be used to disable the watchdog timer. Figure 15.1.4 shows the structure of the particular function select register 2. Particular function select register 2 (Address 6416) Bit 7 to 0 Function b7 b0 At reset Disables the watchdog timer. Undefined When values of "7916" and "50 16" succeedingly in this order, the watchdog timer will stop its operation. R/W -- Note: After reset, this register can be set only once. Writing to this register requires the following procedure: * Write values of "7916 " and "5016" to this register succeedingly in this order. * For the above writing, be sure to use the MOVMB (MOVM when m = 1) instruction or the STAB (STA when m = 1). Note that the following: if an interrupt occurs between writing of "7916 " and next writing of "5016," the watchdog timer does not stop its operation. If any of the following has been performed after reset, writing to this register is disabled from that time: * If this register is read out. * If writing to this register is performed by the procedure other than the above procedure. Fig. 15.1.4 Structure of particular function select register 2 In addition, even when the watchdog timer is disabled by this register, the watchdog timer can be active only at the stop mode termination if the external clock input select bit (bit 1 at address 62 16 ) = "0." (Refer to section "16.3 Stop mode.") 15-4 7902 Group User's Manual WATCHDOG TIMER 15.2 Operation description 15.2 Operation description The operations of the watchdog timer are described below. 15.2.1 Basic operation Watchdog timer starts counting down from "FFF 16." When the watchdog timer's most significant bit becomes "0" (counted 2048 times), a watchdog timer interrupt request occurs. (See Table 15.2.1.) When the interrupt request occurs in above , a value of "FFF 16" is set to the watchdog timer. A watchdog timer interrupt is a non-maskable interrupt. When a watchdog timer interrupt request is accepted, the processor interrupt priority level (IPL) is set to "111 2." Table 15.2.1 Occurrence interval of watchdog timer interrupt request Watchdog timer f(f sys ) = 26 MHz frequency select bit Count source Occurrence interval (Note) 0 Wf512 40.33 ms 1 Wf32 2.52 ms Note: This applies when the peripheral device's clock select bits 1, 0 (bits 7, 6 at address BC16) = "002." 7902 Group User's Manual 15-5 WATCHDOG TIMER 15.2 Operation description Be sure to write dummy data to the watchdog timer register (address 6016 ) before the most significant bit of the watchdog timer becomes "0." When writing to the watchdog timer is not performed owing to a program runaway and the watchdog timer's most significant bit becomes "0," a watchdog timer interrupt request occurs. This informs that a program runaway has occurred. In order to reset the microcomputer when a program runaway has been detected, write "1" to the software reset bit (bit 6 at address 5E16 ) in the watchdog timer interrupt routine. Figure 15.2.1 shows an example of a program runaway detected by the watchdog timer. Main routine Watchdog timer register (Address 6016) 8-bit dummy data Watchdog timer initialized (Value of watchdog timer : "FFF16") (Note 1) Watchdog timer interrupt request occurrence (In other words, program runaway is detected.) Watchdog timer interrupt routine Software reset bit (bit 6 at address 5E16) "1" (Note 2) Reset microcomputer RTI Notes 1: Be sure to initialize the watchdog timer before the most significant bit of the watchdog timer becomes "0." (In other words, be sure to write dummy data to address 6016 before a watchdog timer interrupt request occurs). 2: When a program runaway occurs, values of the data bank register (DT), direct page register (DPRi), etc., may be changed. When "1" is written to the software reset bit by an addressing mode using DT, DPRi, etc., be sure to set values to DT and DPRi, etc. again. Fig. 15.2.1 Example of program runaway detection by watchdog timer 15-6 7902 Group User's Manual WATCHDOG TIMER 15.2 Operation description 15.2.2 Stop period The watchdog timer stops its operation in any of the following cases: Hold state with an external area accessed (Refer to section "3.4 Hold function.") During Wait mode (Refer to section "16.4 Wait mode.") Stop mode (Refer to section "16.3 Stop mode.") When state or has been terminated, the watchdog timer restarts counting from the state immediately before it stops its operation. For the watchdog timer's operation at termination of state , refer to section "15.2.3 Operation in stop mode." 15.2.3 Operations in stop mode When the STP instruction has been executed, a value of "FFF 16" is set to the watchdog timer, and the watchdog timer stops its operation in the stop mode. Immediately after the stop mode termination, the watchdog timer operates as follows. (1) When stop mode is terminated by hardware reset Supply of CPU and BIU starts immediately after the stop mode termination, and the microcomputer performs "operation after reset." (Refer to "CHAPTER 4. RESET.") The watchdog timer frequency select bit becomes "0," and the watchdog timer starts counting of Wf512 from "FFF16 ." (2) When stop mode is terminated by interrupt occurrence (with watchdog timer used) (Note) Immediately after the stop mode termination, the watchdog timer starts counting the count source selected by the watchdog timer clock source select bits at STP termination (bits 6, 7 at address 6116), starting from "FFF 16." It is independent of the watchdog timer frequency select bit (bit 0 at address 6116 ). When the most significant bit of the watchdog timer becomes "0," supply of CPU and BIU starts. (At this time, no watchdog timer interrupt request occurs.) When supply of CPU and BIU starts, the routine of the interrupt which the microcomputer used to terminate the stop mode is executed. The watchdog timer restarts counting of the count source (Wf 32 or Wf512), which was counted immediately before execution of the STP instruction, starting from "FFF16." Note: For the setting of the usage of the watchdog timer, refer to section "16.3 Stop mode." (3) When stop mode is terminated by interrupt occurrence (with watchdog timer not used) (Note) Supply of CPU and BIU starts immediately after the stop mode termination, and the routine of the interrupt which the microcomputer used to terminate the stop mode is executed. The watchdog timer restarts counting of the count source (Wf 32 or Wf512), which was counted immediately before execution of the STP instruction, starting from "FFF 16 ." Note: For the setting of the usage of the watchdog timer, refer to section "16.3 Stop mode." 7902 Group User's Manual 15-7 WATCHDOG TIMER [Precautions for watchdog timer] [Precautions for watchdog timer] 1. When dummy data has been written to address 6016 with the 16-bit data length, writing to address 6116 is simultaneously performed. Accordingly, when the user does not want to change the contents of the watchdog timer frequency select bit (bit 0 at address 61 16) and watchdog timer clock source select bits at STP termination (bits 6, 7 at address 6116), be sure to write the previous value to the bit simultaneously with writing to address 6016 . 2. When the STP instruction is executed, the watchdog timer stops its operation. If the STP instruction's code (3116 , 3016) has accidentally been executed owing to a program runaway, the watchdog timer stops its operation. Therefore, in the system where the watchdog timer is used to detect a program runaway, we recommend that the STP instruction invalidity select bit (bit 0 at address 6216) = "1." (STP instruction is invalid.) Refer to section "16.3 Stop mode." 15-8 7902 Group User's Manual CHAPTER 16 STOP AND WAIT MODES 16.1 16.2 16.3 16.4 Overview Block description Stop mode Wait mode STOP AND WAIT MODES 16.1 Overview 16.1 Overview When there is no need for operation of the central processing unit (CPU), the stop and wait modes are used to stop oscillation or internal clock. As a result, the power consumption can be saved. The microcomputer enters the stop mode when the STP instruction has been executed; the microcomputer enters the wait mode when the WIT instruction has been executed. The stop and wait modes are terminated by an interrupt request occurrence or hardware reset. Table 16.1.1 lists the states in the stop and wait modes and operations after these modes are terminated. Table 16.1.1 States in stop and wait modes and operations after these modes are terminated Item Oscillation Wait mode Stop mode System clock is inactive. When watchdog timer is used at When watchdog timer is not used System clock is active. termination (See Figure 16.3.1.) at termination (See Figure 16.3.1.) (Bit 3 at address 6316 = "0") (Bit 3 at address 6316 = "1") Active. Inactive. PLL frequency multiplier Stopped. Operates (Note 1). CPU, BIU Inactive. Inactive. fsys, clock 1, Inactive. Active. Inactive. f1 to f 4096 Inactive. Wf 32, Wf 512 Inactive. Timers A, B Can operate only in the event counter mode. Operates. Can operate only when an external clock is Operates. event counter mode. Can operate only when an selected. external clock is selected. A-D converter Stopped. Operates. Stopped. D-A converter Stopped. Operates. Stopped. Watchdog timer Stopped. Stopped. A 0 to A23 Retains the state at the STP instruction execution (Note 2). Retains the state at the WIT instruction execution (Note 2). D0 to D15 Floating (Note 2). RD, BLW, Outputs "H" level (Note 2). Pins States Operation after termination Internal peripheral devices Serial I/O Can operate only in the Floating (Note 2). Outputs "H" level (Note 2). BHW, HLDA, CS0 to CS3 ALE Outputs "L" level (Note 2). Outputs "L" level (Note 2). 1 Outputs "L" level (Note 2). Outputs clock 1 (Note 2). Outputs "L" level (Note 2). The others Retains the state at the STP instruction execution. Retains the state at the WIT instruction execution. Termination due Supply of CPU, BIU starts after a Supply of CPU, BIU starts Supply of CPU , BIU starts immediately after to interrupt request certain time has been measured immediately after termi- termination. occurrence by using the watchdog timer. nation (Note 3). Termination due Operation after hardware reset Operation after hardware reset to hardware reset Notes 1: This applies when the PLL circuit operation enable bit (bit 1 at address BC16) = "1." 2: The I/O pins of the external buses and bus control signals can be switched to programmable I/O port pins by software. (Refer to section "17.2 Bus fixation in stop and wait modes.") 3: See Table 16.3.2. 16-2 7902 Group User's Manual R S Q 7902 Group User's Manual WIT instruction Interrupt request R S Q External clock input select bit STP instruction Interrupt request Wait mode XIN XOUT fXIN f/n STP instruction R S Q 0 1 1 0 System clock frequency select bit Wait mode fsys 1/2 1/2 BIU : Bus interface Unit CPU : Central Processing Unit : Signal generated when the watchdog timer's most significant bit becomes "0." : bit 0 at address 6116 : bits 6, 7 at address 6116 : bit 1 at address 6216 : bit 3 at address 6316 : bit 1 at address BC16 : bits 2, 3 at address BC16 : bit 5 at address BC16 : bits 6, 7 at address BC16 CPU wait request 1 0 Peripheral device's clock select bit 0 Access to Wait mode external area HLDA 1 0 Peripheral device's clock select bit 1 * Watchdog timer frequency select bit * Watchdog timer clock source select bits at STP termination * External clock input select bit * System clock stop select bit at WIT * PLL circuit operation enable bit * PLL multiplication ratio select bits * System clock select bit * Peripheral device's clock select bit 0, 1 Reset VCONT fX16 fX32 fX64 fX128 fPLL PLL circuit operation enable bit PLL frequency multiplier PLL multiplication ratio select bits System clock stop select bi at WIT Wait mode 1 f4096 1/16 0 1 Wf512 Wf32 Watchdog timer frequency select bit 1/8 fX16 fX32 fX64 fX128 External clock input select bit (Clock for CPU) CPU (Clock for BIU) BIU 1/8 Watchdog timer clock source select bits at STP termination 1/16 1/4 System clock frequency select bit 1/8 f1 f2 f16 f64 f512 0 1 Watchdog timer Interrupt request Operating clock for timer A Operating clock for serial I/O, timer B A-D conversion frequency (AD) clock source Peripheral device's clocks STOP AND WAIT MODES 16.2 Block description 16.2 Block description Figure 16.2.1 shows the block diagram of the clock generating circuit with the STP and WIT instructions. Also, registers relevant to these modes are described below. Fig. 16.2.1 Block diagram of clock generating circuit with STP and WIT instructions 16-3 STOP AND WAIT MODES 16.2 Block description 16.2.1 Particular function select register 0 Figure 16.2.2 shows the structure of the particular function select register 0, and Figure 16.2.3 shows the writing procedure for the particular function select register 0. b7 b6 b5 b4 b3 b2 b1 b0 Particular function select register 0 (Address 6216) Bit Bit name 0 0 0 0 0 0 Function 0 STP instruction invalidity select bit 0 : STP instruction is valid. 1 : STP instruction is invalid. 1 External clcok input select bit 0 : Oscillation circuit is active. (Oscillator is connected.) Watchdog timer is used at stop mode termination. 1 : Oscillation circuit is inactive. (External clock is input.) At reset R/W 0 RW (Note) RW (Note) 0 When the system clock select bit (bit 5 at address BC 16) = "0," watchdog timer is not used at stop mode termination. When the system clock select bit = "1," watchdog timer is used at stop mode termination. 7 to 2 Fix this bit to "0." 0 RW Note: Writing to these bits requires the following procedure: * Write "5516" to this register. (The bit status does not change only by this writing.) * Succeedingly, write "0" or "1" to each bit. Also, use the MOVMB (MOVM when m = 1) instruction or STAB (STA when m = 1) instruction. If an interrupt occurs between writing of "5516 " and next writing of "0" or "1," latter writing may be ignored. When there is a possibility that an interrupt occurs at the above timing, be sure to read this bit's contents after writing of "0" or "1," and verify whether "0" or "1" has correctly been written or not. Fig. 16.2.2 Structure of particular function select register 0 (1) STP instruction invalidity select bit (bit 0) Setting this bit to "1" invalidates the STP instruction. When using the stop mode, be sure to clear this bit to "0." Writing to this bit requires the following procedure: * Write "5516 " to address 62 16 . * Succeedingly, write "0" or "1" to this bit. (See Figure 16.2.3.) If an interrupt occurs between writing of "55 16 " and next writing of "0" or "1," latter writing may be ignored. When there is a possibility that an interrupt occurs at the above timing, be sure to read this bit's contents after writing of "0" or "1," and verify whether "0" or "1" has correctly been written or not. 16-4 7902 Group User's Manual STOP AND WAIT MODES 16.2 Block description (2) External clock input select bit (bit 1) Setting this bit to "1" stops the oscillation driver circuit between pins XIN and X OUT and keeps the output level at pin XOUT being "H." (Refer to section "17.4 Stop of oscillation circuit.") At the stop mode termination owing to an interrupt occurrence, the watchdog timer is not used if the system clock select bit (bit 5 at address BC 16) = "0," where as the watchdog timer is used if the system clock select bit = "1." To rewrite this bit, write "0" or "1" just after writing of "55 16" to address 62 16 . (See Figure 16.2.3.) Note that if an interrupt occurs between writing of "5516" and next writing of "0" or "1," latter writing may be ignored. When there is a possibility that an interrupt occurs at the above timing, be sure to read this bit's contents after writing of "0" or "1," and verify whether "0" or "1" has correctly been written or not. In addition, even when the watchdog timer is disabled by the particular function select register 2 (address 64 16), the watchdog timer can be active only at the stop mode termination if this bit = "0." (Refer to section "16.3 Stop mode.") AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAA AAA AAA Writing of "5516" b7 0 b0 1 0 1 0 1 0 1 Particular function select register 0 (Address 6216) Note: Bits' state does not change only by writing of "5516." Next instruction Writing to bits 0, 1 b7 0 0 b0 0 0 0 0 Particular function select register 0 (Address 6216) STP instruction invalidity select bit 0 : STP instruction is valid. 1 : STP instruction is invalid. External clock input select bit 0 : Oscillation circuit is active. (Oscillator is connected.) Watchdog timer is used at stop mode termination. 1 : Oscillation circuit is inactive. (External clock is input.) When the system clock select bit (bit 5 at address BC16) = "0," watchdog timer is not used at stop mode termination. When the system clock select bit = "1," watchdog timer is used at stop mode termination. Setting completed Fig. 16.2.3 Writing procedure for particular function select register 0 7902 Group User's Manual 16-5 STOP AND WAIT MODES 16.2 Block description 16.2.2 Particular function select register 1 Figure 16.2.4 shows the structure of the particular function select register 1. b7 b6 b5 b4 b3 b2 b1 b0 Particular function select register 1 (Address 6316) Bit Bit name Function 0 STP-instruction-execution status 0 : Normal operation. bit 1 : STP instruction has been executed. 1 WIT-instruction-execution status 0 : Normal operation. 1 : WIT instruction has been executed. bit 2 Standby state select bit 3 System clock stop select bit at 0 : In wait mode, system clock fsys is active. 1 : In wait mode, system clock fsys is stopped. WIT (Note 3) 4 Address output select bit 5 The value is "0" at reading. 6 Timer B2 clock source select bit (Valid in event counter mode) 7 The value is "0" at reading. 0 : External bus 1 : Programmable I/O port 0 : Address output changes at access to the internal area and external area. 1 : Address output changes only at access to the external area. 0 : External signal input to the TB2 IN pin is counted. 1 : fX32 is counted. At reset R/W RW (Note 2) (Note 1) RW (Note 2) (Note 1) 0 RW 0 RW 0 RW 0 -- 0 RW 0 -- Notes 1: At power-on rest, this bit becomes "0." At hardware reset or software reset, this bit retains the value just before reset. 2: Even when "1" is written, the bit status will not change. 3: Setting this bit to "1" must be performed just before execution of the WIT instruction. Also, after the wait state is terminated, this bit must be cleared to "0" immediately. Fig. 16.2.4 Structure of particular function select register 1 (1) STP-instruction-execution status bit (bit 0) When the microcomputer enters the stop mode, this bit becomes "1," indicating that the STP instruction has been executed. This bit becomes "0" at power-on reset. At hardware reset and software reset, this bit retains the value immediately before reset. Therefore, this bit is used for the following verification: * Which of the power-on reset and hardware reset has been used to reset the system? * Has the hardware reset been used for the stop mode termination? This bit is cleared to "0" by writing "0" to this bit. Although, even when "1" is written to this bit, this bit does not change. At the stop mode termination, be sure to clear this bit to "0" by software. (2) WIT-instruction-execution status bit (bit 1) When the microcomputer enters the wait mode, this bit becomes "1," indicating that the WIT instruction has been executed. This bit becomes "0" at power-on reset. At hardware reset and software reset, this bit retains the value immediately before reset. Therefore, this bit is used for the following verification: * Which of the power-on reset and hardware reset has been used to reset the system? * Has the hardware reset been used for the wait mode termination? This bit is cleared to "0" by writing "0" to this bit. Although, even when "1" is written to this bit, this bit does not change. At the wait mode termination, be sure to clear this bit to "0" by software. 16-6 7902 Group User's Manual STOP AND WAIT MODES 16.2 Block description 16.2.3 Watchdog timer frequency select register Figure 16.2.5 shows the structure of the watchdog timer frequency select register. b7 b6 b5 b4 b3 b2 b1 b0 Watchdog timer frequency select register (Address 6116) Bit 0 5 to 1 6 7 Function Bit name Watchdog timer frequency select bit Nothing is assigned. 0 : Wf512 1 : Wf32 Watchdog timer clock source b7 b6 0 0 : fX32 select bits at STP termination 0 1 : fX16 1 0 : fX128 1 1 : fX64 At reset R/W 0 RW Undefined -- 0 RW 0 RW Fig. 16.2.5 Structure of watchdog timer frequency select register (1) Watchdog timer frequency select bit (bit 0) This bit is used to select a count source of the watchdog timer. (2) Watchdog timer clock source select bits at STP termination (bits 7, 6) These bits are used to select a count source at stop mode termination. For details of the operation at stop mode termination, refer to section "16.3 Stop mode." 7902 Group User's Manual 16-7 STOP AND WAIT MODES 16.3 Stop mode 16.3 Stop mode When the STP instruction has been executed, each of the oscillation and the PLL frequency multiplier's operation stops. This state is called "stop mode." In the stop mode, even when oscillation becomes inactive, the contents of the internal RAM can be retained if Vcc (the power source voltage) V RAM (RAM hold voltage). Furthermore, since the CPU and internal peripheral devices which use any of clocks f 1 to f4096, Wf32, Wf 512 stop their operations, the power consumption can be saved. Also, in the stop mode, the state of each I/O pin of the external buses and bus control signals can be set arbitrarily, the power consumption of the whole system can be saved. (Refer to section "17.2 Bus fixation in stop and wait modes.") The stop mode is terminated owing to an interrupt request occurrence or hardware reset. When terminated owing to an interrupt request occurrence, an instruction can be executed immediately after termination if all of the following conditions are satisfied. (Refer to section "16.3.2 Terminate operation at interrupt request occurrence (when not using watchdog timer)."): * An stable clock is input from the external. The external clock input select bit (bit 1 at address 62 16) = "1." * The PLL frequency multiplier is not used. The system clock select bit (bit 5 at address BC16 ) = "0." When terminated owing to an interrupt request occurrence, an instruction will be executed after the oscillation stabilizing time has been measured by using the watchdog timer if any of the following conditions is satisfied. (Refer to section "16.3.1 Terminate operation at interrupt request occurrence (when using watchdog timer)."): * An oscillator is used. The external clock input select bit (bit 1 at address 62 16) = "0." * The PLL frequency multiplier is used. The system clock select bit (bit 5 at address BC 16) = "1." 16.3.1 Terminate operation at interrupt request occurrence (when using watchdog timer) At the stop mode termination, execution of an instruction is started after a certain time has been measured by using the watchdog timer. (See Figure 16.3.1.) When an interrupt request occurs, an oscillator starts its operation. Also, when the PLL circuit operation enable bit (bit 1 at address BC 16) = "1," the PLL frequency multiplier starts its operation. Simultaneously with this, each supply of clocks f sys, 1, f 1 to f4096 , Wf32 , Wf512 starts. By start of oscillation in , the watchdog timer starts its operation. Regardless of the watchdog timer frequency select bit (bit 0 at address 61 16 ), the watchdog timer counts a count source (fX16 to fX128 ), which is selected by the watchdog timer clock source select bits at STP termination (bits 6, 7 at address 61 16 ). This counting is started from a value of "FFF16." When the most significant bit (MSB) of the watchdog timer becomes "0," each supply of CPU , BIU starts. (At this time, no watchdog timer interrupt request occurs.) Also, the count source of the watchdog timer returns to the count source selected by the watchdog timer frequency select bit (Wf 32 or Wf 512). The interrupt request which occurred in is accepted. For the watchdog timer, refer to "CHAPTER 15. WATCHDOG TIMER." Table 16.3.1 lists the interrupts which can be used to terminate the stop mode. Table 16.3.1 Interrupts which can be used to terminate stop mode Interrupt NMI interrupt INT i interrupt (i = 0 to 4) Key input interrupt Timer Ai interrupt (i = 0 to 4) Timer Bi interrupt (i = 0 to 2) Usage condition for interrupt request occurrence INT3 interrupt: when the key input interrupt is invalid. When the key input interrupt is selected. In event counter mode UARTi transmit interrupt (i = 0, 1) When an external clock is selected. UARTi receive interrupt (i = 0, 1) Notes 1: When multiple interrupts are enabled, the stop mode is terminated owing to the interrupt request which occurs first. 2: For interrupts, refer to "CHAPTER 7. INTERRUPTS" and each peripheral device's chapter. 16-8 7902 Group User's Manual STOP AND WAIT MODES 16.3 Stop mode Before executing the STP instruction, be sure to enable an interrupt which is to be used for the stop mode termination. Also, make sure that the interrupt priority level of an interrupt to be used for the termination is higher than the processor interrupt priority level (IPL) of a routine where the STP instruction is executed. After oscillation starts (), there is a possibility that each interrupt request occurs until the supply of CPU, BIU starts (). The interrupt requests which occurred during this period are accepted in order of priority after the watchdog timer's MSB becomes "0." (When the level sense of an INT i interrupt is used, however, no interrupt request is retained. Therefore, if pin INT i is at the invalid level when the watchdog timer's MSB becomes "0," no interrupt request is accepted.) For an interrupt which has no need to be accepted, be sure to set its interrupt priority level to "0" (Interrupt disabled) before executing the STP instruction. 16.3.2 Terminate operation at interrupt request occurrence (when not using watchdog timer) At the stop mode termination, an instruction is executed without use of the watchdog timer. (See Figure 16.3.1.) When an interrupt request occurs, clock input from pin XIN starts. Simultaneously, supply of clocks f sys, 1, f 1 to f4096 , Wf32 , Wf512 starts. Supply of CPU , BIU starts after the time listed in Table 16.3.2 has elapsed. The interrupt request which occurred in is accepted. Table 16.3.2 Time after stop mode is terminated until supply of CPU , BIU starts Watchdog timer clock source select bit at STP termination (bits 7, 6 at address 6116) Time until supply of CPU and BIU starts 00 fX IN 19 cycles fX IN 11 cycles fX IN 67 cycles 01 10 11 fX IN 35 cycles Before executing the STP instruction, be sure to set as follows: Enable an interrupt which is to be used for the stop mode termination. Also, make sure that the interrupt priority level of an interrupt to be used for the termination is higher than the processor interrupt priority level (IPL) of a routine where the STP instruction is executed. The external clock input select bit (bit 1 at address 62 16 ) = "1" (Note) The system clock select bit (bit 5 at address BC 16 ) = "0" (Note) Note: Simultaneously, the oscillation driver circuit between pins X IN and X OUT stops, and the output level at pin XOUT is kept "H." (Refer to section "17.4 Stop of oscillation circuit.") 7902 Group User's Manual 16-9 STOP AND WAIT MODES 16.3 Stop mode When using watchdog timer Stop mode fXIN fPLL (Note) 1 BIU Interrupt request to be used for stop mode termination (Interrupt request bit) fXi 2048 counts FFF16 Value of watchdog timer 7FF16 CPU Operating Stopped Stopped Operating Internal peripheral devices Operating Stopped Operating Operating STP instru- Interrupt request to be used for ction is termination occurs. executed. Oscillation starts. (When an external clock is input from pin XIN, clock input starts.) PLL frequency multiplier starts its operation. Watchdog timer starts counting. Watchdog timer's MSB = "0" (However, watchdog timer interrupt request does not occur.) Each supply of CPU, BIU starts. Interrupt request which was used for termination is accepted. Note: This applies when the PLL circuit operation enable bit (bit 1 at address BC16) = "1." fXi : fX16, fX32, fX64, fX128. These are clocks selected by the watchdog timer clock source select bits at STP termination (bits 7, 6 at address 6116.) When not using watchdog timer Stop mode fXIN 1 BIU Interrupt request to be used for stop mode termination (Interrupt request bit) (Note) FFF16 Value of watchdog timer 7FF16 CPU Operating Stopped Stopped Operating Internal peripheral devices Operating Stopped Operating Operating STP instru- Interrupt Each supply of CPU, BIU starts. ction is request to Interrupt request which was used executed. be used for for termination is accepted. termination occurs. Clock input from pin XIN starts. Watchdog timer starts counting. Note: Time listed in Table 16.3.2. Fig. 16.3.1 Stop mode terminate sequence owing to interrupt request occurrence 16-10 7902 Group User's Manual STOP AND WAIT MODES 16.3 Stop mode 16.3.3 Terminate operation at hardware reset Although each of the CPU and SFR area is initialized, the contents of the internal RAM immediately before the STP instruction execution are retained. The terminate sequence is the same as the internal processing sequence after reset. For reset, refer to "CHAPTER 4. RESET." Also, the STP-instruction-execution status bit is used for the following verification: * Which of the power-on reset and hardware reset has been used to reset the system? * Has the hardware reset been used for the stop mode termination? 7902 Group User's Manual 16-11 STOP AND WAIT MODES 16.4 Wait mode 16.4 Wait mode When the WIT instruction is executed, both of CPU and BIU become inactive. (The oscillation does not become inactive.) This state is called "wait mode." (See Table 16.1.1.) In the wait mode, the power consumption can be saved with Vcc (the power source voltage) retained. When using no internal peripheral device in the wait mode, the power consumption can be saved furthermore since each of f sys and internal peripheral device's operation clock can be inactive. (Refer to section "17.3 Stop of system clock in wait mode.") Also, in the wait mode, the state of each I/O pin of the external buses and bus control signals can be set arbitrarily. Therefore, the power consumption of the whole system can be saved. (Refer to section "17.2 Bus fixation in stop and wait modes.") The wait mode is terminated owing to an interrupt request occurrence or hardware reset. The wait mode terminate operation is described below. 16.4.1 Terminate operation at interrupt request occurrence When an interrupt request occurs, each supply of CPU and BIU starts. The interrupt request which occurred in is accepted. Table 16.4.1 lists the interrupts which can be used for the wait mode termination. Table 16.4.1 Interrupts which can be used for wait mode termination Usage conditions for interrupt request occurrences Interrupt System clock in active System clock stopped NMI interrupt INT i interrupt (i = 0 to 4) INT 3 interrupt: when the key input interrupt is invalid. Key input interrupt When the key input interrupt is selected. Timer Ai interrupt (i = 0 to 4) In event counter mode Timer Bi interrupt (i = 0 to 2) UARTi transmit interrupt (i = 0, 1) When an external clock is selected. UARTi receive interrupt (i = 0, 1) A-D conversion interrupt Do not use. Notes 1: When multiple interrupts are enabled, the wait mode is terminated owing to the interrupt request which occurs first. 2: For interrupts, refer to "CHAPTER 7. INTERRUPTS" and each peripheral device's chapter. Before executing the WIT instruction, be sure to enable an interrupt which is to be used for the wait mode termination. Also, make sure that the interrupt priority level of an interrupt to be used for termination is higher than the processor interrupt priority level (IPL) of a routine where the WIT instruction is executed. Also, when multiple interrupts in Table 16.4.1 are enabled, the wait mode is terminated owing to the interrupt request which occurs first. 16.4.2 Terminate operation at hardware reset Although each of the CPU and SFR area is initialized, the contents of the internal RAM immediately before the WIT instruction execution are retained. The terminate sequence is the same as the internal processing sequence after reset. For reset, refer to "CHAPTER 4. RESET." Also, the WIT-instruction-execution status bit is used for the following verification: * Which of the power-on reset and hardware reset has been used to reset the system? * Has the hardware reset been used for the wait mode termination? 16-12 7902 Group User's Manual CHAPTER 17 POWER SAVING FUNCTION 17.1 Overview 17.2 Bus fixation in stop and wait modes 17.3 Stop of system clock in wait mode 17.4 Stop of oscillation circuit 17.5 Pin V REF disconnection POWER SAVING FUNCTIONS 17.1 Overview This chapter explains the functions to save the power consumption of the microcomputer and the total system including the microcomputer. 17.1 Overview Table 17.1.1 lists the overview of the power saving functions. Each of these functions saves the power consumption of the total system. The registers related to the power saving functions are explained in the following. Table 17.1.1 Overview of power saving functions Item Function Bus fixation in stop and In the stop and wait modes, by switching I/O pins of the wait modes external bus and bus control signals to programmable I/O port pins, the states of the I/O pins can arbitrary be set. Stop of system clock in In the wait mode, operating clocks for the internal peripheral wait mode devices and fsys can be stopped. Stop of oscillation circuit When a stable clock externally generated is used, the drive circuit for oscillation between pins X IN and XOUT can be stopped. (The output level at pin XOUT is fixed to "H.") When terminating the stop mode, the watchdog timer is not used. Pin VREF disconnection The VREF input can be disconnected when the A-D converter and D-A converter are not used. 17-2 7902 Group User's Manual Reference CHAPTER 16. STOP AND WAIT MODES CHAPTER 5. CLOCK GENERATING CIRCUIT, Section 16.3 Stop mode CHAPTER 13. A-D CONVERTER CHAPTER 14. D-A CONVERTER POWER SAVING FUNCTIONS 17.1 Overview 17.1.1 Particular function select register 0 Figure 17.1.1 shows the structure of the particular function select register 0, and Figure 17.1.2 shows the writing procedure for the particular function select register 0. b7 b6 b5 b4 b3 b2 b1 b0 Particular function select register 0 (Address 6216) Bit Bit name 0 0 0 0 0 0 Function 0 STP instruction invalidity select bit 0 : STP instruction is valid. 1 : STP instruction is invalid. 1 External clcok input select bit 0 : Oscillation circuit is active. (Oscillator is connected.) Watchdog timer is used at stop mode termination. 1 : Oscillation circuit is inactive. (External clock is input.) At reset R/W 0 RW (Note) RW (Note) 0 When the system clock select bit (bit 5 at address BC16) = "0," watchdog timer is not used at stop mode termination. When the system clock select bit = "1," watchdog timer is used at stop mode termination. 7 to 2 Fix this bit to "0." 0 RW Note: Writing to these bits requires the following procedure: * Write "5516" to this register. (The bit status does not change only by this writing.) * Succeedingly, write "0" or "1" to each bit. Also, use the MOVMB (MOVM when m = 1) instruction or STAB (STA when m = 1) instruction. If an interrupt occurs between writing of "5516" and next writing of "0" or "1," latter writing may be ignored. When there is a possibility that an interrupt occurs at the above timing, be sure to read this bit's contents after writing of "0" or "1," and verify whether "0" or "1" has correctly been written or not. Fig. 17.1.1 Structure of particular function select register 0 7902 Group User's Manual 17-3 POWER SAVING FUNCTIONS 17.1 Overview (1) External clock input select bit (bit 1) Setting this bit to "1" stops the oscillation driver circuit between pins X IN and XOUT and keeps the output level of pin XOUT being "H." (Refer to section "17.4 Stop of oscillation circuit." At the stop mode termination owing to an interrupt occurrence, the watchdog timer is not used if the system clock select bit (bit 5 at address BC16 ) = "0," whereas the watchdog timer is used if the system clock select bit = "1." To rewrite this bit, write "0" or "1" just after writing of "55 16 " to address 62 16. (See Figure 17.1.2.) Note that if an interrupt occurs between writing of "5516 " and next writing of "0" or "1," latter writing may be ignored. When there is a possibility that an interrupt occurs at the above timing, be sure to read this bit's contents after writing of "0" or "1," and verify whether "0" or "1" has correctly been written or not. In addition, even when the watchdog timer is disabled by the particular function select register 2 (address 64 16 ), the watchdog timer can be active only at the stop mode termination if this bit = "0." (Refer to section "16.3 Stop mode.") AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAA AAA AAA Writing of "5516" b7 0 b0 1 0 1 0 1 0 1 Particular function select register 0 (Address 6216) Note: Bits' state does not change only by writing of "5516." Writing to bits 0, 1 b7 0 0 b0 0 0 0 0 Particular function select register 0 (Address 6216) STP instruction invalidity select bit 0 : STP instruction is valid. 1 : STP instruction is invalid. External clock input select bit 0 : Oscillation circuit is active. (Oscillator is connected.) Watchdog timer is used at stop mode termination. 1 : Oscillation circuit is inactive. (External clock is input.) When the system clock select bit (bit 5 at address BC16) = "0," watchdog timer is not used at stop mode termination. When the system clock select bit = "1," watchdog timer is used at stop mode termination. Setting completed Fig. 17.1.2 Writing procedure for particular function select register 0 17-4 7902 Group User's Manual Next instruction POWER SAVING FUNCTIONS 17.1 Overview 17.1.2 Particular function select register 1 Figure 17.1.3 shows the structure of the particular function select register 1. b7 b6 b5 b4 b3 b2 b1 b0 Particular function select register 1 (Address 6316) Bit Bit name Function At reset R/W 0 STP-instruction-execution status bit 0 : Normal operation. 1 : STP instruction has been executed. (Note 1) RW (Note 2) 1 WIT-instruction-execution status bit Standby state select bit 0 : Normal operation. 1 : WIT instruction has been executed. (Note 1) RW (Note 2) 0 : External bus 1 : Programmable I/O port 0 RW 0 : In the wait mode, system clock fsys is active. 1 : In the wait mode, system clock f sys is stopped. 0 RW 4 System clock stop select bit at WIT (Note 3) Address output select bit 0 : Address output changes at access to the internal area and external area. 1 : Address output changes only at access to the external area. 0 RW 5 The value is "0" at reading. 0 -- 6 Timer B2 clock source select bit 0 : External signal input to the TB2IN pin is counted. 1 : fX32 is counted. (Valid in event counter mode.) 0 RW 7 The value is "0" at reading. 0 -- 2 3 Notes 1: At power-on reset, this bit becomes "0." At hardware reset or software reset, this bit retains the value just before reset. 2: Even when "1" is written, the bit status will not change. 3: Setting this bit to "1" must be performed just before execution of the WIT instruction. Also, after the wait state is terminated, this bit must be cleared to "0" immediately. Fig. 17.1.3 Structure of particular function select register 1 (1) Standby state select bit (bit 2) Setting this bit to "1" allows the I/O pins of the external bus and bus control signals to be switched to the programmable I/O port pins in the stop and wait modes. (Refer to section "17.2 Bus fixation in stop and wait modes.") (2) Internal clock stop select bit at WIT (bit 3) Setting this bit to "1" stops operating clocks for the internal peripheral devices and f sys in the wait mode. (Refer to section "17.3 Stop of system clock in wait mode.") 7902 Group User's Manual 17-5 POWER SAVING FUNCTIONS 17.2 Bus fixation in stop and wait modes 17.2 Bus fixation in stop and wait modes Setting the standby state select bit (See Figure 17.1.3.) to "1" allows the I/O pins of the external bus and bus control signals to be switched to the programmable I/O port pins in stop and wait modes. By setting the pins' state not to generate unnecessary currents between the microcomputer and external devices, the power consumption of the total system can be saved. (This pin's state can be realized by setting the corresponding port register and port direction register.) Table 17.2.1 lists the correspondences between I/O pins of the external bus, bus control signals and programmable I/O port pins, and Figure 17.2.1 shows a setting example of bus fixation. Table 17.2.1 Correspondences between I/O pins of external bus, bus control signals and programmable I/O port pins Standby state select bit External bus and Bus control signals 0 1 A 0 to A7, A 0 to A7, P100 to P10 7, A 8 to A15, A 8 to A 15, P110 to P11 7, A 16 to A 23, A 16 to A23, P0 0 to P07 D0 to D7, D0 to D7, P1 0 to P17, D8 to D15, D8 to D15 (Note 1) P2 0 to P27 RD, BLW, RD, BLW, P3 1, P32, BHW BHW (Note 1) P3 3 CS 0 CS 0 (Note 2) P4 4 Notes 1: When the external data bus width = 8 bits (BYTE = Vcc level), these pins are forcibly switched to be programmable I/O port pins, regardless of the standby state select bit. 2: Only in the microprocessor mode, this pin can be switched to a programmable I/O port pin by using the standby state select bit. In the memory expansion mode, be sure to switch this pin to a programmable I/O port pin by clearing the CS0 output select bit (bit 7 at address 80 16). Also, pins ALE, 1, CS1 to CS 3 must be switched to programmable I/O port pins by clearing the following bits to "0": * ALE : ALE output select bit (bit 3 at address 5F 16 ) * 1 : Clock 1 output select bit (bit 7 at address 5E16 ) * CS1 to CS 3: Each of CS 1 to CS 3 output select bits (each of bit 7s at addresses 82 16 , 8416 and 8616 ) 17-6 7902 Group User's Manual POWER SAVING FUNCTIONS 17.2 Bus fixation in stop and wait modes AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAA AAAAAAAAAAAA AAAA AAAAAAAAAAAA AAAA AAAAAAAAAAAA AAAAAAAAAAAA Setting the I/O pins' output level of external bus and bus control signals. Set the standby state select bit to "1." b7 b0 1 Particular function select register 1 (Address 6316) Standby state select bit 1 : Programmable I/O port Port P11 Port P10 Port P0 register register register (Address 216) (Address 1716) (Address 1616) b7 b0 b7 b0 b7 A23 to A0 0: "L" level output 1: "H" level output Setting the I/O pins' state of external bus and bus control signals. Port P2 Port P1 register register (Address 616) (Address 316) Port P0 direction Port P11 direction Port P10 direction register register register (Address 1916) (Address 416) (Address 1816) b7 b0 b7 b0 b7 b0 b7 b0 b7 b0 D15 to D0 0: "L" level output 1: "H" level output A23 to A0 0: Input mode (Note 1) 1: Output mode Port P2 direction Port P1 direction register register (Address 816) (Address 516) b7 b0 b7 b0 b7 b0 RD BLW BHW b7 0: "L" level output 1: "H" level output b0 Port P4 register (Address A16) CS0 (Note 2) 0: "L" level output 1: "H" level output Port P3 direction register (Address 916) RD BLW BHW b7 b0 Port P3 register (Address 716) D15 to D0 0: Input mode (Note 1) 1: Output mode b7 b0 0: Input mode (Note 1) 1: Output mode b0 Port P4 direction register (Address C16) CS0 (Note 2) 0: Input mode (Note 1) 1: Output mode STP or WIT instruction executed. Notes 1: Each of pins which have been set for the input mode must be connected to Vcc or Vss via a resistor; otherwise they are placed in the floting state. 2: This pin can be switched to a programmable I/O port pin by the standby state select bit only in the microprocessor mode. In the memory expansion mode, be sure to switch this pin to a programmable I/O port pin by clearing the CS0 output select bit (bit 7 at address 8016). Fig. 17.2.1 Setting example of bus fixation 7902 Group User's Manual 17-7 POWER SAVING FUNCTIONS 17.3 Stop of system clock in wait mode 17.3 Stop of system clock in wait mode In the wait mode, if there is not need to operate the internal peripheral devices, setting the system clock stop select bit at WIT (See Figure 17.1.3.) to "1" stops the operating clocks for the internal peripheral devices and fsys . This saves the power consumption of the microcomputer. Table 17.3.1 lists the states and operations in the wait mode and after this mode is terminated. Table 17.3.1 States and operations in wait mode and after this mode is terminated Item System clock is active. (bit 3 at address 6316 = 0) System clock is inactive. (bit 3 at address 6316 = 1) Oscillation Active. PLL frequency multiplier Operates (Note 1). CPU, BIU Inactive. fsys, Clock 1, Active. Inactive. f1 to f 4096 Inactive. Operates. Can operate only in the event counter mode. Serial I/O Operates. Can operate only when an external clock is selected. A-D converter Operates. Stopped. D-A converter Operates. Stopped. Watchdog timer Stopped. A 0 to A 23 Retains the state at the WIT instruction execution (Note 2). D0 to D15 Floating (Note 2). _____ ________ RD, BLW, BHW, HLDA, ______ ______ CS0 to CS3 ALE Outputs "L" level (Note 2). 1 Outputs clock 1 (Note 2). The others Operation after termination Outputs "H" level (Note 2). ________ __________ Pins States Internal peripheral devices Wf 32, Wf 512 Timers A, B Outputs "L" level (Note 2). Retains the state at the WIT instruction execution. Termination due to i n t e r r u p t r e q u e s t Supply of CPU, BIU starts immediately after termination. occurrence Termination due to hardware reset Operation after hardware reset Notes 1: This applies when the PLL circuit operation enable bit (bit 1 at address BC16) = "1." 2: The I/O pins of the external buses and bus control signals can be switched to programmable I/O port pins by software. (Refer to section "17.2 Bus fixation in stop and wait modes.") 17-8 7902 Group User's Manual POWER SAVING FUNCTIONS 17.4 Stop of oscillation circuit, 17.5 Pin VREF disconnection 17.4 Stop of oscillation circuit When a stable clock externally generated is input to pin X IN , power consumption can be saved by setting the external clock input select bit to "1" to stop the drive circuit for oscillation between pins X IN and XOUT . (See Figure 17.1.1.) At this time, the output level at pin X OUT is fixed to "H." Also, if the system clock select bit (bit 5 at address BC 16) = "0," the watchdog timer is not used when the stop mode is terminated owing to an interrupt request occurrence; therefore, the microcomputer can start instruction execution just after termination of the stop mode. When the system clock select bit = "1," in this case, the watchdog timer is used. 17.5 Pin VREF disconnection When the A-D converter and D-A converter are not used, power consumption can be saved by setting the V REF connection select bit to "1." It is because the reference voltage input pin (VREF) is disconnected from the ladder resistors of the A-D converter and D-A converter (See Figure 17.5.1.), and there is no current flow between them. When the V REF connection select bit has been cleared from "1" (VREF disconnected) to "0" (V REF connected), be sure to start the A-D conversion or D-A conversion after an interval of 1 s or more has elapsed. b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 1 (Address 1F16) Bit 0 Bit name Function At reset R/W 1 RW 1 RW 0 RW 0 RW 1 A-D sweep pin select bits (Valid in the single sweep and repeat sweep modes.) (Note 1) 2 Fix this bit to "0." 3 Resolution select bit 4 A-D conversion frequency (AD) select See Table 13.2.1. bit 1 0 RW 5 0 : Falling edge of the pin ADTRG's input signal External trigger polarity select bit (Valid when external trigger selected.) 1 : Rising edge of the pin ADTRG's input signal 0 RW 6 VREF connection select bit (Note 6) 0 RW 7 The value is "0" at reading. 0 - 0 b1 b0 0 0 : Pins AN0 and AN1 (2 pins) 0 1 : Pins AN0 to AN3 (4 pins) 1 0 : Pins AN0 to AN5 (6 pins) (Notes 2, 3) 1 1 : Pins AN0 to AN7 (8 pins) (Notes 2 to 5) 0 : 8-bit resolution mode 1 : 10-bit resolution mode 0 : Pin VREF is connected. 1 : Pin VREF is disconnected. Notes 1: These bits are invalid in the one-shot and repeat modes. (They may be either "0" or "1.") 2: When using pin AN4 , be sure that the pin INT3 select bit (bit 5 at address 9416) = "0." 3: When using pin AN5 , be sure that the pin INT4 select bit (bit 6 at address 9416) = "0." 4: When using pin AN6 , be sure that the D-A0 output enable bit (bit 0 at address 9616) = "0" (output disabled). 5: When using pin AN7 , be sure that the pin INT2 select bit (bit 4 at address 94 16) = "0" and the D-A1 output enable bit (bit 1 at address 9616) = "0." When an external trigger is selected, pin AN7 cannot be used as an analog input pin. 6: When this bit is cleared from "1" to "0," be sure to start the A-D conversion or D-A conversion after an interval of 1 s or more has elapsed. 7: Writing to each bit of the A-D control register 1 must be performed while the A-D conversion halts. Fig. 17.5.1 Structure of A-D control register 1 7902 Group User's Manual 17-9 POWER SAVING FUNCTIONS 17.5 Pin VREF disconnection MEMORANDUM 17-10 7902 Group User's Manual CHAPTER 18 DEBUG FUNCTION 18.1 Overview 18.2 Block description 18.3 Address matching detection mode 18.4 Out-of-address-area detection mode [Precautions for debug function] DEBUG FUNCTION 18.1 Overview, 18.2 Block description 18.1 Overview When the CPU fetches an op code (op-code fetch), the debug function generates an address matching detection interrupt request if a selected condition is satisfied as a result of comparison between the address where the op code to be fetched is stored (in other words, the contents of PG and PC) and the specified address. The debug function provides the following 2 modes: (1) Address matching detection mode When the contents of PG and PC match with the specified address, an address matching detection interrupt request occurs. This mode can be used for avoiding or modifying a portion of a program. (2) Out-of-address-area detection mode When the contents of PG and PC go out of the specified area, an address matching detection interrupt request occurs. This mode can be used for the program runaway detection by specifying the area where a program exists. Note that an address matching detection interrupt is a non-maskable software interrupt. For details of this interrupt, refer to "CHAPTER 7. INTERRUPTS." In addition, the debug function cannot be evaluated by a debugger. Therefore, do not use a debugger when using the debug function. 18.2 Block description Figure 18.2.1 shows the block diagram of the debug function, and the registers relevant to this function are described in the following. Internal data bus (DB0 to DB15) Debug control register 0 Address compare register 0 Address compare register 1 Debug control register 1 Matching * Compare register Matching * Compare register CPU bus (Address) Fig. 18.2.1 Block diagram of debug function 18-2 7902 Group User's Manual Address matching detect circuit Address matching detection interrupt DEBUG FUNCTION 18.2 Block description 18.2.1 Debug control register 0 Figure 18.2.2 shows the structure of the debug control register 0. b7 b6 b5 b4 b3 b2 b1 b0 Debug control register 0 (Address 6616) Bit 0 Bit name Detect condition select bits 1 2 3 0 Function b2 b1 b0 0 0 0 : Do not select. 0 0 1 : Address matching detection 0 0 1 0 : Address matching detection 1 0 1 1 : Address matching detection 2 1 0 0 : Do not select. 1 0 1 : Out-of-address-area detection 110: Do not select. 111: Fix these bits to "0." 4 5 Detect enable bit 6 Fix this bit to "0." 7 The value is "1" at reading. 0 : Detection disabled. 1 : Detection enabled. 0 0 At reset R/W (Note) RW (Note) RW (Note) RW (Note) RW (Note) RW (Note) RW (Note) RW 1 -- Note: At power-on reset, these bits become "0"; at hardware reset or software reset, these bits retain the value immediately before reset. Fig. 18.2.2 Structure of debug control register 0 (1) Detect condition select bits (bits 0 to 2) These bits are used to select an occurrence condition for an address matching detection interrupt request. This condition can be selected from the following: Address matching detection 0 An address matching detection interrupt request occurs when the contents of PG and PC match with the address being set in the address compare register 0 (addresses 6816 to 6A 16); (Refer to section "18.3 Address matching detection mode.") Address matching detection 1 An address matching detection interrupt request occurs when the contents of PG and PC match with the address being set in the address compare register 1 (addresses 6B16 to 6D16 ); (Refer to section "18.3 Address matching detection mode.") Address matching detection 2 An address matching detection interrupt request occurs when the contents of PG and PC match with the address being set in the address compare register 0 (addresses 68 16 to 6A 16 ) or address compare register 1 (addresses 6B16 to 6D 16); (Refer to section "18.3 Address matching detection mode.") Out-of-address-area detection An address matching detection interrupt request occurs when the contents of PG and PC are less than the address being set in the address compare register 0 (addresses 68 16 to 6A 16) or larger than the address compare register 1 (addresses 6B16 to 6D 16 ); (Refer to section "18.4 Out-ofaddress-area detection mode.") (2) Detect enable bit (bit 5) If any selected condition is satisfied when this bit = "1," an address matching detection interrupt request occurs. 7902 Group User's Manual 18-3 DEBUG FUNCTION 18.2 Block description 18.2.2 Debug control register 1 Figure 18.2.3 shows the structure of the debug control register 1. b7 b6 b5 b4 b3 b2 b1 b0 Debug control register 1 (Address 6716) Bit 0 1 Bit name Function 0 At reset R/W 0 Fix this bit to "0." (Note 1) RW 1 The value is "0" at reading. (Note 1) RO 2 Address compare register access enable bit (Note 2) 0 RW 3 Fix this bit to "1" when using the debug function. 0 RW 4 Fix this bit to "0." (Note 1) RW 5 While a debugger is not used, the value is "0" at reading. While a debugger is used, the value is "1" at reading. 0 RO 6 Address-matching-detection 2 decision bit (Valid when the address matching detection 2 is selected.) 0 RO 7 The value is "0" at reading. 0 -- 0 : Disabled. 1 : Enabled. 0 : Matches with the contents of the address compare register 0. 1 : Matches with the contents of the address compare register 1. Notes 1: At power-on reset, these bits become "0"; at hardware reset or software reset, these bits retain the value immediately before reset. 2: Be sure to set this bit to "1" immediately before the access to the address compare registers 0 and 1 (addresses 68 16 to 6D16). Then, be sure to clear this bit to "0" immediately after this access. Fig. 18.2.3 Structure of debug control register 1 (1) Address compare register access enable bit (bit 2) Setting this bit to "1" enables reading from or writing to the contents of address compare registers 0 and 1 (addresses 6816 to 6D 16), while clearing this bit to "0" disables this reading or writing. Be sure to set this bit to "1" immediately before reading from or writing to the address compare registers 0 and 1, and then clear it to "0" immediately after this reading or writing. (2) Address-matching-detection 2 decision bit (bit 6) When the address matching detection 2 is selected, this bit is used to decide which of the addresses being set in the address compare registers 0 and 1 matches with the contents of PG and PC. This bit is cleared to "0" when the contents of PG and PC matches with the address being set in address compare register 0 and set to "1" when the contents of PG and PC match with the one being set in the address compare register 1. This bit is invalid when the address matching detection 0 and 1 are selected. 18-4 7902 Group User's Manual DEBUG FUNCTION 18.2 Block description 18.2.3 Address compare registers 0 and 1 Each of the address compare registers 0 and 1 consists of 24 bits, and the address to be detected is set here. Figure 18.2.4 shows the structures of the address compare registers 0 and 1. Address compare register 0 (Addresses 6A16 to 6816 ) Address compare register 1 (Addresses 6D16 to 6B16) Bit 23 to 0 Function (b23) (b16) (b15) (b8) b7 b0 b7 b0 b7 b0 At reset R/W The address to be detected (in other words, the start address of instructions) is set here. Undefined RW Note: When accessing to these registers, be sure to set the address compare register access enable bit (bit 2 at address 6716) to "1" immediately before the access. Then, be sure to clear this bit to "0" immediately after this access. Fig. 18.2.4 Structures of address compare registers 0 and 1 At op-code fetch, the contents of PG and PC are compared with the addresses being set in the address compare register 0 or 1. Therefore, be sure to set the start address of an instruction into the address compare register 0 or 1. If such an address as in the middle of instructions or in the data table is set into the address compare register 0 or 1, no address matching detection interrupt request occurs because this address does not match with the contents of PG and PC. Note that, before the instruction at the address being set in the address compare register 0 or 1 is executed, an address matching detection interrupt request occurs and is accepted. 7902 Group User's Manual 18-5 DEBUG FUNCTION 18.3 Address matching detection mode 18.3 Address matching detection mode When the contents of PG and PC match with the specified address, an address matching detection interrupt request occurs. 18.3.1 Setting procedure for address matching detection mode Figure 18.3.1 shows an initial setting example for registers relevant to the address matching detection mode. Disables interrupts. The interrupt disable flag (I) is set to "1." Selection of detect condition b7 b7 b0 b0 0 0 0 0 0 Debug control register 1 (Address 6716) Debug control register 0 (Address 6616) Address compare register access enable bit (Note 1) 0 : Disabled. Detect condition select bits b2 b1 b0 0 0 1 : Address matching detection 0 0 1 0 : Address matching detection 1 0 1 1 : Address matching detection 2 Set the detect enable bit to "1." Detect enable bit 0 : Detection disabled. b7 b0 Debug control register 0 (Address 6616) 1 Detect enable bit 1 : Detection enabled. Processing for setting of address compare registers b7 b0 0 1 1 0 Debug control register 1 (Address 6716) Address compare register access enable bit (Note 1) 1 : Enabled. AAA AAA Clear the interrupt disable flag (I) to "0" (Note 2). Setting of address compare registers b23 b0 Detection starts. Address compare register 0 (Addresses 6A16 to 6816) Address compare register 1 (Addresses 6D16 to 6B16) The address to be detected is set here. Notes 1: Be sure to set this bit to "1" immediately before reading from or writing to the address compare registers 0, 1. Then, be sure to clear this bit to "0" immediately after this reading or writing. 2: This processing is unnecessary when no maskable interrupt is used. Fig. 18.3.1 Initial setting example for registers relevant to address matching detection mode 18-6 7902 Group User's Manual DEBUG FUNCTION 18.3 Address matching detection mode 18.3.2 Operations in address matching detection mode Setting the detect enable bit to "1" initiate to compare the contents of PG and PC with one of the contents of the following registers. This comparison is performed at each op-code fetch: * When the address matching detection 0 is selected, the contents of the address compare register 0 are used for the above comparison. * When the address matching detection 1 is selected, the contents of the address compare register 1 are used for the above comparison. * When the address matching detection 2 is selected, the contents of the address compare register 0 or 1 are used for the above comparison. When the address which matches with the above register's contents is detected, an address matching detection interrupt request occurs, and then, this request will be accepted. Perform the necessary processing with an address matching detection interrupt routine. The contents of PG, PC, and PS at acceptance of the address matching detection interrupt request are saved onto the stack area. Therefore, be sure to rewrite the above contents of PG and PC to a certain return address, and return to the address by using the RTI instruction. When an address matching detection interrupt request has been accepted, the interrupt disable flag (I) is set to "1"; the processor interrupt priority level (IPL) does not change. Figures 18.3.2 and 18.3.3 show the examples of the ROM correct processing using the address matching detection mode. 7902 Group User's Manual 18-7 DEBUG FUNCTION 18.3 Address matching detection mode Address matching detection 0 or 1 selected Address matching detection interrupt routine Main routine The interrupt disable flag (I) is cleared to "0" (Note 1) TOP_BUG Defective or Former program Modified or Updated program TOP_RTN The contents of PG and PC saved onto the stack area (address TOP_BUG) are rewritten to address TOP_RTN (Note 2). STAB A, LG : 0h (Note 3) RTI TOP_BUG : The start address of defective or former program. This address is to be set in the address compare register 0 or 1, in advance. TOP_RTN : The address next to the defective or former program. Notes 1: When an address matching detection interrupt request has been accepted, the interrupt disable flag (I) is set to "1." If another interrupt requests is required to be accepted under the same conditions as those of the defective or former program, be sure to clear the interrupt disable flag (I) to "0" at the start of an address matching detection interrupt routine. 2: Each status of PG, PC, and PS immediately before acceptance of an address matching detection interrupt request is saved onto the stack area. (The contents of PG, PC, and PS are saved onto the stack area in this order.) Refer to section "7.7 Sequence from acceptance of interrupt request until execution of interrupt routine." 3: Make sure that this instruction is executed in the absolute long addressing mode. The above is just an example. In an actual programming, be sure to refer to the format of the assembler description to be used. Fig. 18.3.2 Example of ROM correct processing using address matching detection mode (1) 18-8 7902 Group User's Manual DEBUG FUNCTION 18.3 Address matching detection mode Address matching detection 2 selected Main routine Address matching detection interrupt routine The interrupt disable flag (I) is cleared to "0" (Note 1) TOP_BUG1 Defective or Former program Address-matchingdetection 2 decision bit? 1 0 TOP_RTN1 TOP_BUG2 Modified or Updated program Modified or Updated program The contents of PG and PC saved onto the stack area (address TOP_BUG1) are rewritten to address TOP_RTN1 (Note 2). The contents of PG and PC saved onto the stack area (address TOP_BUG2) are rewritten to address TOP_RTN2 (Note 2). Defective or Former program STAB A, LG : 0h (Note 3) TOP_RTN2 RTI TOP_BUG1 : The start address of defective or former program . This address is to be set in the address compare register 0, in advance. TOP_RTN1 : The address next to the defective or former program . TOP_BUG2 : The start address of defective or former program . This address is to be set in the address compare register 1, in advance. TOP_RTN2 : The address next to the defective or former program . Notes 1: When an address matching detection interrupt request has been accepted, the interrupt disable flag (I) is set to "1." If another interrupt requests is required to be accepted under the same conditions as those of the defective or former program, be sure to clear the interrupt disable flag (I) to "0" at the start of an address matching detection interrupt routine. 2: Each status of PG, PC, and PS immediately before acceptance of an address matching detection interrupt request is saved onto the stack area. (The contents of PG, PC, and PS are saved onto the stack area in this order.) Refer to section "7.7 Sequence from acceptance of interrupt request until execution of interrupt routine." 3: Make sure that this instruction is executed in the absolute long addressing mode. The above is just an example. In an actual programming, be sure to refer to the format of the assembler description to be used. Fig. 18.3.3 Example of ROM correct processing using address matching detection mode (2) 7902 Group User's Manual 18-9 DEBUG FUNCTION 18.4 Out-of-address-area detection mode 18.4 Out-of-address-area detection mode When the contents of PG and PC go out of the range of the specified area, an address matching detection interrupt request occurs. 18.4.1 Setting procedure for out-of-address-area detection mode Figure 18.4.1 shows an initial setting example for registers relevant to the out-of-address-area detection mode. Disables interrupts. The interrupt disable flag (I) is set to "1." Selection of detect condition b7 b7 b0 b0 Debug control register 1 (Address 6716) 0 0 0 0 0 1 0 1 Debug control register 0 (Address 6616) Address compare register access enable bit (Note 1) 0 : Disabled. Selection of out-of-address-area detection Detect enable bit 0 : Detection disabled. Set the detect enable bit to "1." b7 Processing for setting of address compare registers b7 b0 1 Debug control register 0 (Address 6616) b0 0 1 1 0 Debug control register 1 (Address 6716) Detect enable bit 1 : Detection enabled. Address compare register access enable bit (Note 1) 1 : Enabled. AAA AAA Clear the interrupt disable flag (I) to "0" (Note 2). Setting of address compare registers b23 b0 Address compare register 0 (Addresses 6A16 to 6816) Detection starts. The start address of the programming area is set here. b23 b0 Address compare register 1 (Addresses 6D16 to 6B16) The last address of the programming area is set here. Notes 1: Be sure to set this bit to "1" immediately before reading from or writing to the address compare registers 0, 1. Then, be sure to clear this bit to "0" immediately after this reading or writing. 2: This processing is unnecessary when no maskable interrupt is used. Fig. 18.4.1 Initial setting example for registers relevant to out-of-address-area detection mode 18-10 7902 Group User's Manual DEBUG FUNCTION 18.4 Out-of-address-area detection mode 18.4.2 Operations in out-of-address-area detection mode Setting the detect enable bit to "1" initiate to compare the contents of PG and PC with the contents of the address compare registers 0 and 1. When an address less than the contents of the address compare registers 0 or larger than the one of the address compare register 1 is detected, an address matching detection interrupt request occurs, and then, this request will be accepted. Perform the necessary processing with an address matching detection interrupt routine. The contents of PG, PC, and PS at acceptance of the address matching detection interrupt request are saved onto the stack area. Therefore, be sure to rewrite the above contents of PG and PC to a certain return address, and return there by using the RTI instruction. When an address matching detection interrupt request has been accepted, the interrupt disable flag (I) is set to "1"; the processor interrupt priority level (IPL) does not change. By setting the start address of the programming area into the address compare register 0 and the last address of the programming area into the address compare register 1, a program runaway (in other words, fetching op codes from the area out of the programming area) can be detected. If any program runaway is detected and reset of the microcomputer is required, be sure to write "1" into the software reset bit (bit 6 at address 5E 16) within an address matching detection interrupt routine. Figure 18.4.2 shows an example of program runaway detection using the out-of-address-area detection mode. 00000016 Access to the area out of the programming area TOP_PRG AAAA AAAA AAAA AAAA Software reset bit 1 (bit 6 at address 5E16) Programming area END_PRG Address matching detection interrupt routine Access to the area out of the programming area The microcomputer is reset. RTI FFFFFF16 TOP_PRG : Start address of programming area This address is to be set into the address compare register 0, in advance. END_PRG : Last address of programming area This address is to be set into the address compare register 1, in advance. Note: A program runaway may affect the contents of the data bank register (DT), the direct page registers (DPRi) etc. Therefore, the contents of these registers must be rewritten in order to write "1" to the software reset bit with an addressing mode using DT, DPRi, etc. Fig. 18.4.2 Example of program runaway detection using out-of-address-area detection mode 7902 Group User's Manual 18-11 DEBUG FUNCTION [Precautions for debug function] [Precautions for debug function] 1. The debug function cannot be evaluated by a debugger. Therefore, do not use a debugger when using the debug function. 2. When returning from an address matching detection interrupt routine, be sure to rewrite the saved contents of PG and PC to a certain return address, and then return there by using the RTI instruction. However, this is unnecessary processing when the software reset is performed within an address matching detection interrupt routine for program runaway detection, etc. 3. Be sure to set the start address of an instruction into the address compare register 0 or 1. 18-12 7902 Group User's Manual CHAPTER 19 APPLICATIONS 19.1 Connection examples with external devices 19.2 Examples of handling control pins in flash memory serial I/O mode APPLICATIONS 19.1 Connection examples with external devices Some application examples are described below. Each application described here is just an example. Therefore, before actual using it, be sure to properly modify it according to the user's system and sufficiently evaluate it. 19.1 Connection examples with external devices Connection examples with the ready function used and those with memories and I/O devices are described below. For the functions and operations of pins used in these connection examples, refer to "CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES." Also for timing requirements, refer to sections "Appendix 9. M37902FGCGP electrical characteristics" and "Appendix 10. M37902FGMHP electrical characteristics." 19-2 7902 Group User's Manual APPLICATIONS 19.1 Connection examples with external devices 19.1.1 Examples with ready function used (1) Example with ready function used when bus cycle = 1 + 3 Figures 19.1.1 and 19.1.2 show examples with the ready function used when bus cycle = 1 + 3. M37902 D-TYPE FLIP FLOP 1 RD 3 BLW BHW 2 PR 1D 1Q PR 2D 2Q PR 3D 1CK 2CK 3CK 3Q 1 4 CSi RDY Circuit conditions: f(fsys) = 26MHz, bus cycle = 1 + 3 Bus cycle = 1 + 3 Ready A tc = 1/f(fsys) B C 1 1 CSi td(1-RDL) = -18 to 0 ns td(1-RDH) = -18 to 0 ns RD BLW BHW 1Q 2Q 3Q RDY tsu(RDY-1) tsu(RDY-1) tsu(RDY-1) < tc = 38 ns Insufficient Sum of propagation delay time of 2, 3, and 4 <Operations> * A ready request is accepted at pin RDY's input-level detection timing A . * A ready-state-termination request is accepted at pin RDY's input-level detection timing C . When f(fsys) = 26 MHz, the ready-state-termination request is accepted at the next detection timing C because tsu(RDY-1) (the setup time for ready state termination) for detection timing B is insufficient. <Device conditions: f(fsys) = 26 MHz> When the ready function is required to be used as shown above, be sure to satisfy all of the following conditions: * (Propagation delay time of 1 (Max.) - Propagation delay time of 2 (Min.) + Setup time of 3) 19 ns (Note) * (Propagation delay time of 1 (Min.) - Propagation delay time of 2 (Max.) + Setup time of 3) > 1 ns * Sum of propagation delay time of 2, 3, and 4 (Max.) 36 ns Note: If the above conditions are not satisfied, the rising edge of signal RDY shown above is delayed by 1 cycle of 1. Therefore, each of the rising edges of signals CSi, RD, BLW, BHW is delayed by 1 cycle of 1. Fig. 19.1.1 Example with ready function used when bus cycle = 1 + 3 (1) 7902 Group User's Manual 19-3 APPLICATIONS 19.1 Connection examples with external devices M37902 D-TYPE FLIP FLOP 1 RD 3 BLW BHW 2 PR 1D 1Q PR 2D 2Q PR 3D 1CK 2CK 3CK 3Q 4 1 CSi RDY Circuit condition: Bus cycle = 1 + 3 Bus cycle = 1 + 3 Ready A tc = 1/f(fsys) B 1 1 CSi td(1-RDL) = -18 to 0 ns td(1-RDH) = -18 to 0 ns RD BLW BHW 1Q 2Q 3Q RDY tsu(RDY-1) tsu(RDY-1) Sum of propagation delay time of 2, 3, and 4 <Operations> * A ready request is accepted at pin RDY's input-level detection timing A . * A ready-state-termination request is accepted at pin RDY's input-level detection timing B . <Device conditions> When the ready function is required to be used as shown above, be sure to satisfy all of the following conditions with adjusting f(fsys): 1 ns 2 f(fsys) 1 * (Propagation delay time of 1 (Min.) - Propagation delay time of 2 (Max.) + Setup time of 3) > -18 ns 2 f(fsys) 1 * Sum of propagation delay time of 2, 3, and 4 (Max.) -40 ns f(fsys) * (Propagation delay time of 1 (Max.) - Propagation delay time of 2 (Min.) + Setup time of 3) Fig. 19.1.2 Example with ready function used when bus cycle = 1 + 3 (2) 19-4 7902 Group User's Manual APPLICATIONS 19.1 Connection examples with external devices (2) Example with ready function used when bus cycle = 2 + 2 Figures 19.1.3 shows an example with the ready function used when bus cycle = 2 + 2. M37902 1 D-TYPE FLIP FLOP RD 3 BLW BHW 2 PR 1D 1Q PR 2D 1CK 2CK 2Q 1 4 CSi RDY Circuit condition: Bus cycle = 2 + 2 Bus cycle = 2 + 2 Ready A tc = 1/f(fsys) B 1 1 CSi td(1-RDL) = -18 to 0 ns td(1-RDH) = -18 to 0 ns RD BLW BHW 1Q 2Q RDY tsu(RDY-1) tsu(RDY-1) Sum of propagation delay time of 2, 3, and 4 <Operations> * A ready request is accepted at pin RDY's input-level detection timing A . * A ready-state-termination request is accepted at pin RDY's input-level detection timing B . <Device conditions> When the ready function is required to be used as shown above, be sure to satisfy all of the following conditions with adjusting f(fsys): 1 ns 2 f(fsys) 1 * (Propagation delay time of 1 (Min.) - Propagation delay time of 2 (Max.) + Setup time of 3) > -18 ns 2 f(fsys) 1 * Sum of propagation delay time of 2, 3, and 4 (Max.) -40 ns f(fsys) 3 * Sum of propagation delay time of 1 and 4 (Max.) -40 ns 2 f(fsys) * (Propagation delay time of 1 (Max.) - Propagation delay time of 2 (Min.) + Setup time of 3) Fig. 19.1.3 Example with ready function used when bus cycle = 2 + 2 7902 Group User's Manual 19-5 APPLICATIONS 19.1 Connection examples with external devices 19.1.2 Connection examples with memories Figures 19.1.4 and 19.1.5 show connection examples with memories, and Tables 19.1.1 to 19.1.5 list the timing requirements of memories. For timing requirements not listed in these tables, be sure to refer to the latest datasheet of each memory, also. M37902 MD0 MD1 Flash memory ( 16) BYTE CS0 CE RD OE BLW WE BHW A1 to A23 A1 to D0 to D15 D0 to D15 A0 to D0 to D15 SRAM ( 16) CS1 CE OE 1 W BC1 2 A1 to D0 to D15 Circuit condition: f(fsys) = 26 MHz 1, 2 : See Table 19.1.3. Fig. 19.1.4 Connection example with memories (1) 19-6 7902 Group User's Manual BC2 A0 to DQ1 to DQ16 APPLICATIONS 19.1 Connection examples with external devices M37902 MD0 MD1 MASK ROM ( 16) BYTE CS0 CE RD OE BLW BHW A0 to A23 A1 to D0/LA0 to D7/LA7 A0 to D8 to D15 D0 to D15 D0 to D15 SRAM ( 8) CE CS1 OE W A1 to A0 to D0 to D7 DQ1 to DQ8 SRAM ( 8) CE OE W A1 to D8 to D15 A0 to DQ1 to DQ8 CD-ROM decorder (Multiplexed-bus-type device) CE CS2 OE A8 to D0/LA0 to D7/LA7 WE A8 to DA0 to DA7 ALE AS RDY MRDY Circuit condition: f(fsys) = 26 MHz For access to area CS2, the 8-bit external data bus and multiplexed bus are selected. Fig. 19.1.5 Connection example with memories (2) 7902 Group User's Manual 19-7 APPLICATIONS 19.1 Connection examples with external devices Table 19.1.1 Timing requirements of flash memory (f(fsys ) = 26 MHz) Conditions Item Bus cycle = 2 + 2 Bus cycle = 2 + 3 Reading Address access time 107 ns or less (Note 1) 145 ns or less (Note 1) OE access time 46 ns or less 84 ns or less CE access time 98 ns or less 136 ns or less Writing Output disable time Data setup time Data hold time CE setup time before write 0ns or more 56 ns or less 9 ns or less (Note 2) 38 ns or less 0ns or more 94 ns or less 9 ns or less (Note 2) 38 ns or less Notes 1: This applies when the address output select bit (bit 4 at address 63 16) = "0." 2: Recovery insertion of 2 cycles allows "the data hold time" to be extended by 38 ns, moreover. Table 19.1.2 Timing requirements of mask ROM (f(fsys ) = 26 MHz) Conditions Bus cycle = 1 + 3 Bus cycle = 2 + 4 107 ns or less (Note) 183 ns or less (Note) 84 ns or less 122 ns or less Item Reading Address access time OE access time CE access time Output disable time 98 ns or less 0 ns or more 174 ns or less 0 ns or more Note: This applies when the address output select bit (bit 4 at address 63 16) = "0." Table 19.1.3 Timing requirements of SRAM ( 16) (f(f sys ) = 26 MHz) Item Reading Address access time OE access time CE access time BC 1/BC 2 access time Output enable time after OE enabled Conditions Bus cycle = 1 + 1 Bus cycle = 1 + 2 31 ns or less (Note 1) 69 ns or less (Note 1) 8 ns or less 46 ns or less 22 ns or less 60 ns or less (8 ns - propagation delay time of 2) or less (46 ns - propagation delay time of 2) or less 6 ns or more (Note 2) Output disable time 0 ns or more 0 ns or more (18 ns + propagation delay time of 1) or less (56 ns + propagation delay time of 1) or less Writing Data setup time (9 ns - propagation delay time of 1) or less (Note 3) (9 ns - propagation delay time of 1) or less (Note 3) Data hold time Notes 1: This applies when the address output select bit (bit 4 at address 63 16) = "0." 2: Recovery insertion of 1 cycle allows "the output enable time after OE enabled" to be set to "0 ns or more." 3: Recovery insertion of 2 cycles allows "the data hold time" to be extended by 38 ns, moreover. 19-8 6 ns or more (Note 2) 7902 Group User's Manual APPLICATIONS 19.1 Connection examples with external devices Table 19.1.4 Timing requirements of SRAM ( 8) (f(f sys ) = 26 MHz) Item Reading Writing Address access time OE access time CE access time Output enable time after OE enabled Output disable time Data setup time Data hold time Conditions Bus cycle = 1 + 1 Bus cycle = 1 + 2 31 ns or less (Note 1) 69 ns or less (Note 1) 8 ns or less 46 ns or less 22 ns or less 60 ns or less 6 ns or more (Note 2) 6 ns or more (Note 2) 0 ns or more 18 ns or less 9 ns or less (Note 3) 0 ns or more 18 ns or less 9 ns or less (Note 3) Notes 1: This applies when the address output select bit (bit 4 at address 6316) = "0." 2: Recovery insertion of 1 cycle allows "the output enabled time after OE enabled" to be set to "0 ns or more." 3: Recovery insertion of 2 cycles allows "the data hold time" to be extended by 38 ns, moreover. Table 19.1.5 Timing requirements of CD-ROM decoder (f(f sys) = 26 MHz) Conditions Bus cycle = 2 + 2 Bus cycle 18 ns or less 37 ns or 38 ns or less 53 ns or 18 ns or less 37 ns or Item Reading /Writing Reading Writing AS pulse width CE setup time for AS Address setup time for AS Address hold time for AS Ready-input setup time Ready-termination setup time OE access time WE pulse width Data setup time Data hold time 0 ns or less 40 ns or more 40 ns or more 5 ns or more and 46 ns or less 61 ns or less = 3 + 3 less less less 23 ns or less 40 ns or more 40 ns or more 5 ns or more and 84 ns or less 99 ns or less 56 ns or less 9 ns or less (Note) 94 ns or less 9 ns or less (Note) Note: Recovery insertion of 2 cycles allows "the data hold time" to be extended by 38 ns, moreover. 7902 Group User's Manual 19-9 APPLICATIONS 19.1 Connection examples with external devices 19.1.3 I/O expansion examples Figure 19.1.6 shows a port expansion example with the M66010FP used. The frequency of a transfer clock for serial I/O must be 1.923 MHz or less in order to satisfy the requirements of the M66010FP's CLK pulse width. Serial I/O control in this expansion example is described below. In this expansion example, 8-bit data transmission/reception is performed three times by using UART0, and so the port pins are expanded up to 24 bits. Clock synchronous serial I/O mode is selected. Transmission/Reception is enabled. An internal clock is selected. The frequency of a transfer clock = 1.85 MHz. LSB first is selected. The control procedure is as follows: "L" level is output from port P51. (This signal makes the expanded I/O port pins of the M66010FP floating.) "H" level is output from port P5 1. "L" level is output from port P5 0. 24-bit data is transmitted/received by using UART0. "H" level is output from port P50. Figure 19.1.7 shows the serial transfer timing between the M37902 and M66010FP. 19-10 7902 Group User's Manual APPLICATIONS 19.1 Connection examples with external devices M37902 M66010FP TXD0 DI RXD0 DO CLK0 CLK P50 CS P51 S RTS0 Left open CSi A0 to A23 VCC D0 to D15 RD BLW GND BHW 1 MD0 MD1 BYTE D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 Expanded I/O port pins Circuit conditions: f(fsys) = 26 MHz * UART0 is used in the clock synchronous serial I/O mode. * An internal clock is selected. f2 = 1.85 MHz. 6+1 * The applies when the peripheral devices' clock select bits 1, 0 * The frequency of a transfer clock = (bits 7, 6 at address BC16) = "002." Fig. 19.1.6 Port expansion example with M66010FP used 7902 Group User's Manual 19-11 19-12 CS P50 Fig. 19.1.7 Serial transfer timing between M37902 and M66010FP 7902 Group User's Manual D1 D2 Expanded I/O port pin Expanded I/O port pin Expanded I/O port pin D24 to DI1 DO RXD0 DO2 DO3 DO4 DO5 DO6 DI3 DI4 DI5 DI6 DI7 DO7 DI8 DO8 Output structure of an expanded I/O port pin is the N-channel open drain. DI24 DI2 DI1 DI2 Data of the shift register 1 is output in serial. DI DO1 AAA AAA Serial data is input to the shift register 2. Data of expanded I/O port pins is input to the shift register 1. Expanded I/O port pins are released from the floating state. TXD0 CLK0 CLK S P51 DI21 DI22 DI23 DI24 DO24 DO2 DO1 : This indicates a pin name of the M37902. The others are pins' names or operations of the M66010FP. DI20 AAA AAA DO20 DO21 DO22 DO23 DO24 Data of the shift register 2 is output to expanded I/O port pins. APPLICATIONS 19.1 Connection examples with external devices APPLICATIONS 19.2 Examples of handling control pins in flash memory serial I/O mode 19.2 Examples of handling control pins in flash memory serial I/O mode Each of pins P4 1 to P4 3, MD0, and MD1 serves as an input/output pin for a control signal in the flash memory serial I/O mode. Also, be sure to handle pin NMI for avoiding the interrupt occurrence in the flash memory serial I/O mode. Examples of handling these pins and pin RESET on the board are described below. 19.2.1 With control signals not affecting user system circuit When control signals in the flash memory serial I/O mode are not used in the user system circuit, or when these signals do not affect that circuit, the connections shown in Figure 19.2.1 are available. When pin NMI, however, is used in the user system circuit, see Figures 19.2.2 and 19.2.3. User system board Not used, or Connected to the user system circuit. M37902F SDA (P42) Connected to serial programmer. BUSY (P43) VCC SCLK (P41) NMI Left open. MD0 MD1 RESET VSS XIN XOUT User reset signal (Note) Note: When there is a possibility that the user reset signal becomes "L" level in the flash memory serial I/O mode, be sure to cut the current flow between the user reset pin and pin RESET by using a jumper switch, etc. : The flash memory version of the 7902 Group Fig. 19.2.1 Example of handing control pins when control signals do not affect user system circuit 7902 Group User's Manual 19-13 APPLICATIONS 19.2 Examples of handling control pins in flash memory serial I/O mode 19.2.2 With control signals affecting user system circuit In the flash memory serial I/O mode, be sure to cut the current flow toward the user system circuit if control signals for this mode are also used in the user system circuit. Figure 19.2.2 shows an example of handling pins with jumper switches used, and Figure 19.2.3 shows an example of handling pins with analog switches used. User system board Connected to the user system circuit. M37902F SDA (P42) BUSY (P43) VCC SCLK (P41) Connected to serial programmer. NMI MD0 MD1 VSS RESET XIN XOUT User reset signal (Note) Note: When there is a possibility that the user reset signal becomes "L" level in the flash memory serial I/O mode, be sure to cut the current flow between the user reset pin and pin RESET by using a jumper switch, etc. : The flash memory version of the 7902 Group Fig. 19.2.2 Example of handling pins with jumper switches used User system board 74HC4066 Connected to the user system circuit. M37902F SDA (P42) BUSY (P43) SCLK (P41) Connected to serial programmer. VCC MD0 NMI VSS MD1 RESET XIN XOUT User reset signal (Note) Note: When there is a possibility that the user reset signal becomes "L" level in the flash memory serial I/O mode, be sure to cut the current flow between the user reset pin and pin RESET by using a jumper switch, etc. : The flash memory version of the 7902 Group Fig. 19.2.3 Example of handling pins with analog switches used 19-14 7902 Group User's Manual CHAPTER 20 FLASH MEMORY VERSION 20.1 Overview 20.2 Flash memory CPU reprogramming mode [Precautions for flash memory CPU reprogramming mode] 20.3 Flash memory serial I/O mode [Precautions for flash memory serial I/O mode] 20.4 Flash memory parallel I/O mode [Precautions for flash memory parallel I/O mode] FLASH MEMORY VERSION 20.1 Overview 20.1 Overview The flash memory version is provided with the same function as that of the mask ROM version except that the former includes the flash memory. Note that, however, part of the SFR area of the flash memory version differs from that of the mask ROM or external ROM version. (Refer to section "20.1.1 Memory assignment.") In the flash memory version, its internal flash memory can be handled in the following three reprogramming modes: flash memory CPU reprogramming mode, flash memory serial I/O mode, and flash memory parallel I/O mode. Table 20.1.1 lists the performance overview of the flash memory version. (For the items not listed in Table 20.1.1, see Table 1.1.1.) Table 20.1.1 Performance overview of flash memory version Item Power source voltage M37902FGCGP M37902FGMHP Programming/Erase voltage M37902FGCGP M37902FGMHP Programming Erase method Flash memory reprogramming modes Performance 5 V 0.5 V 3.3 V 0.3 V 5 V 0.5 V(3.3 V 0.3 V only in flash memory parallel I/O mode) 3.3 V 0.3 V Programmed in a unit of 128 ward (256 bytes) Block erase or Total erase Flash memory CPU reprogramming mode Flash memory serial I/O mode Flash memory parallel I/O mode Maximum number of reprograms (programming 100 and erasure) For the flash memory version, in addition to the same three processor modes as those of the mask ROM version, any of the four operating modes listed in Table 20.1.2 can further be selected by the voltage level applied to pin MD1. Table 20.1.3 also lists the overview of flash memory reprogramming modes. Note: Do not switch the voltages applied to pins MD0 and MD1 while the microcomputer is active. Table 20.1.2 Operating mode selection according to voltages applied to pins MD0 and MD1 MD1 VSS VSS VCC VCC MD0 VSS VCC VSS VCC Operating modes Single-chip mode, Memory expansion mode, Microprocessor mode (Note 1) Microprocessor mode (Note 1) Boot mode (Note 2) Flash memory parallel I/O mode (Note 3) Notes 1: Refer to section "2.5 Processor modes." 2: Refer to section "20.1.2 Boot mode." 3: Refer to section "20.4 Flash memory parallel I/O mode." 20-2 7902 Group User's Manual FLASH MEMORY VERSION 20.1 Overview Table 20.1.3 Overview of flash memory reprogramming modes Flash memory Flash memory CPU reprogramming mode reprogramming mode Functional overview User ROM area is reprogrammed by the CPU executing software commands. Reprogrammable User ROM area area Operating mode Single-chip mode, available Memory expansion mode, Boot mode ROM programmer (Unnecessary) available Flash memory serial I/O mode Flash memory parallel I/O mode User ROM area is reprogram- Boot ROM area and User ROM med by using a dedicated serial area are reprogrammed by using programmer. a dedicated parallel programmer. User ROM area User ROM area, Boot mode Boot ROM area Flash memory parallel I/O mode Serial programmer Parallel programmer (For the serial programmer, re- (For the parallel programmer, refer to the latest catalog.) fer to the latest catalog.) 7902 Group User's Manual 20-3 FLASH MEMORY VERSION 20.1 Overview 20.1.1 Memory assignment The flash memory version is provided with the internal flash memory as shown below: * M37902FJCGP/HP, M37902FJMHP (hereafter referred to M37902FJ): 498 Kbytes * M37902FHCGP/HP, M37902FHMHP (hereafter referred to M37902FH): 370 Kbytes * M37902FGCGP/HP, M37902FGMHP (hereafter referred to M37902FG): 248 Kbytes * M37902FECGP/HP, M37902FEMHP (hereafter referred to M37902FE): 184 Kbytes * M37902FCCGP/HP, M37902FCMHP (hereafter referred to M37902FC): 120 Kbytes * M37902F8CGP/HP, M37902F8MHP (hereafter referred to M37902F8): 60 Kbytes Figures 20.1.1 to 20.1.6 show the memory assignments of the flash memory version. Also, for the flash memory versions other than above, refer to the latest datasheets or catalogs. Single-chip mode Memory expansion mode Microprocessor mode SFR area SFR area SFR area Internal RAM area (12 Kbytes) Internal RAM area (12 Kbytes) Internal RAM area (12 Kbytes) (Note 1) Internal flash memory area Internal flash memory area (User ROM area) (User ROM area) (498 Kbytes) (Note 2) (498 Kbytes) (Note 2) 016 FF16 10016 7FF16 80016 Unused area 37FF16 380016 7FFFF16 8000016 FEFFFF16 FF000016 Reserved area (Note 3) Reserved area (Note 3) FFFFFF16 : This is an external area. The access to this area enables the access to an externally-connected device. Notes 1: When the internal RAM area is followed by an external area, do not assign a program to the last 8 bytes of the internal RAM area. 2: Do not assign a program to the last 8 bytes of the internal ROM area. 3: Do not access this area. Fig. 20.1.1 Memory assignment of flash memory version (M37902FJ) 20-4 7902 Group User's Manual FLASH MEMORY VERSION 20.1 Overview Single-chip mode Memory expansion mode Microprocessor mode SFR area SFR area SFR area Internal RAM area (12 Kbytes) Internal RAM area (12 Kbytes) Internal RAM area (12 Kbytes) (Note 1) Internal flash memory area Internal flash memory area (User ROM area) (User ROM area) (370 Kbytes) (Note 2) (370 Kbytes) (Note 2) 016 FF16 10016 7FF16 80016 Unused area 37FF16 380016 5FFFF16 6000016 FEFFFF16 FF000016 Reserved area (Note 3) Reserved area (Note 3) FFFFFF16 : This is an external area. The access to this area enables the access to an externally-connected device. Notes 1: When the internal RAM area is followed by an external area, do not assign a program to the last 8 bytes of the internal RAM area. 2: Do not assign a program to the last 8 bytes of the internal ROM area. 3: Do not access this area. Fig. 20.1.2 Memory assignment of flash memory version (M37902FH) 7902 Group User's Manual 20-5 FLASH MEMORY VERSION 20.1 Overview Single-chip mode Memory expansion mode Microprocessor mode 016 FF16 10016 7FF16 80016 1FFF16 200016 SFR area SFR area Internal RAM area (6 Kbytes) Internal RAM area (6 Kbytes) Internal RAM area Internal flash memory area Internal flash memory area (User ROM area) (User ROM area) (248 Kbytes) (Note 2) (248 Kbytes) (Note 2) SFR area Unused area (6 Kbytes) (Note 1) 3FFFF16 4000016 FEFFFF16 FF000016 Reserved area (Note 3) Reserved area (Note 3) FFFFFF16 : This is an external area. The access to this area enables the access to an externally-connected device. Notes 1: When the internal RAM area is followed by an external area, do not assign a program to the last 8 bytes of the internal RAM area. 2: Do not assign a program to the last 8 bytes of the internal ROM area. 3: Do not access this area. Fig. 20.1.3 Memory assignment of flash memory version (M37902FG) 20-6 7902 Group User's Manual FLASH MEMORY VERSION 20.1 Overview Single-chip mode Memory expansion mode Microprocessor mode 016 FF16 10016 7FF16 80016 1FFF16 200016 2FFFF16 SFR area SFR area Internal RAM area (6 Kbytes) Internal RAM area (6 Kbytes) Internal RAM area Internal flash memory area Internal flash memory area (User ROM area) (User ROM area) (184 Kbytes) (Note 2) (184 Kbytes) (Note 2) SFR area Unused area (6 Kbytes) (Note 1) 3000016 FEFFFF16 FF000016 FFFFFF16 Reserved area (Note 3) Reserved area (Note 3) : This is an external area. The access to this area enables the access to an externally-connected device. Notes 1: When the internal RAM area is followed by an external area, do not assign a program to the last 8 bytes of the internal RAM area. 2: Do not assign a program to the last 8 bytes of the internal ROM area. 3: Do not access this area. Fig. 20.1.4 Memory assignment of flash memory version (M37902FE) 7902 Group User's Manual 20-7 FLASH MEMORY VERSION 20.1 Overview Single-chip mode Memory expansion mode Microprocessor mode 016 FF16 10016 SFR area Unused area 7FF16 80016 Internal RAM area 17FF16 (4 Kbytes)(Note 1) 180016 1FFF16 Unused area 200016 Internal flash memory area 1FFFF16 SFR area SFR area Internal RAM area (4 Kbytes)(Note 1) Internal RAM area (4 Kbytes)(Note 1) Internal flash memory area (User ROM area) (User ROM area) (120 Kbytes) (Note 2) (120 Kbytes) (Note 2) 2000016 FEFFFF16 FF000016 Reserved area (Note 3) Reserved area (Note 3) FFFFFF16 : This is an external area. The access to this area enables the access to an externally-connected device. Notes 1: When the internal RAM area is followed by an unused area or an external area, do not assign a program to the last 8 bytes of the internal RAM area. 2: Do not assign a program to the last 8 bytes of the internal ROM area. 3: Do not access this area. Fig. 20.1.5 Memory assignment of flash memory version (M37902FC) 20-8 7902 Group User's Manual FLASH MEMORY VERSION 20.1 Overview Single-chip mode Memory expansion mode SFR area SFR area SFR area Internal RAM area (2 Kbytes) Internal RAM area (2 Kbytes)(Note 1) Microprocessor mode 016 FF16 10016 Unused area 7FF16 80016 Internal RAM area (2 Kbytes) FFF16 100016 Internal flash memory area Internal flash memory area (User ROM area) FFFF16 (User ROM area) (60 Kbytes) (Note 2) (60 Kbytes) (Note 2) 1000016 FEFFFF16 FF000016 FFFFFF16 Reserved area (Note 3) Reserved area (Note 3) : This is an external area. The access to this area enables the access to an externally-connected device. Notes 1: When the internal RAM area is followed by an external area, do not assign a program to the last 8 bytes of the internal RAM area. 2: Do not assign a program to the last 8 bytes of the internal ROM area. 3: Do not access this area. Fig. 20.1.6 Memory assignment of flash memory version (M37902F8) 7902 Group User's Manual 20-9 FLASH MEMORY VERSION 20.1 Overview In addition to the internal flash memory area (in other words, user ROM area) shown in Figures 20.1.1 to 20.1.6, the flash memory version has the boot ROM area of 16 Kbytes. Figure 20.1.7 shows the internal flash memory assignment. The user ROM area is divided into several blocks, and each block can individually be inhibited from being programmed or erased (i.e. be locked). The user ROM area is reprogrammed in the flash memory CPU reprogramming mode, serial I/O mode, and parallel I/O mode. The boot ROM area is located at addresses where a part of the user ROM area resides and can be reprogrammed only in the flash memory parallel I/O mode. (Refer to section "20.4 Flash memory parallel I/O mode."). When being reset with pin MD1 tied to Vcc level and pin MD0 to Vss level, the software in the boot ROM area is executed after reset. (Refer to section "20.1.2 Boot mode.") When pin MD1 = Vss level, however, the contents of the boot ROM area cannot be read out. 20-10 7902 Group User's Manual FLASH MEMORY VERSION 20.1 Overview User ROM area User ROM area Word Byte addresses addresses 1C0016 1FFF16 200016 2FFF16 300016 3FFF16 400016 380016 3FFF16 400016 5FFF16 600016 7FFF16 800016 100016 1FFF16 200016 2FFF16 300016 3FFF16 400016 2 Kbytes 8 Kbytes 8 Kbytes 200016 3FFF16 400016 5FFF16 600016 7FFF16 800016 32 Kbytes (Note 1) 7FFF16 800016 User ROM area Word Byte addresses addresses 100016 80016 Word Byte addresses addresses 8 Kbytes 1FFF16 200016 2FFF16 300016 3FFF16 400016 8 Kbytes 8 Kbytes 3FFF16 400016 5FFF16 600016 7FFF16 800016 7FFF16 800016 8 Kbytes 8 Kbytes M37902F8 32 Kbytes (Note 1) 32 Kbytes (Note 1) FFFF16 1000016 12 Kbytes FFFF16 1000016 7FFF16 (Note 2) FFFF16 M37902FC 64 Kbytes 64 Kbytes FFFF16 1FFFF16 1000016 2000016 (Note 2) FFFF16 1FFFF16 1000016 2000016 M37902FH M37902FE Boot ROM area 64 Kbytes 64 Kbytes (In flash memory parallel I/O mode) Word addresses (In boot mode) Byte addresses 016 C00016 17FFF16 2FFFF16 1800016 3000016 (Note 2) 17FFF16 2FFFF16 1800016 3000016 16 Kbytes FFFF16 1FFF16 M37902FG 64 Kbytes 64 Kbytes 1FFFF16 3FFFF16 2000016 4000016 1FFFF16 3FFFF16 (Note 2) 64 Kbytes Notes 1: The area from addresses FFB016 to FFBF16 is the reserved area for a serial programmer. Therefore, in the flash memory serial I/O mode, do not program to this area. 2: Do not program to the last 8 bytes of the user ROM area. 27FFF16 4FFFF16 2800016 5000016 64 Kbytes (Note 2) 2FFFF16 5FFFF16 3000016 6000016 M37902FJ 64 Kbytes 37FFF16 6FFFF16 3800016 7000016 64 Kbytes 3FFFF16 7FFFF16 (Note 2) Fig. 20.1.7 Internal flash memory assignment 7902 Group User's Manual 20-11 FLASH MEMORY VERSION 20.1 Overview 20.1.2 Boot mode When being reset with pin MD1 tied to Vcc level and pin MD0 to Vss level, the flash memory version enters the boot mode. In the boot mode, the software in the boot ROM area is executed after reset. In the boot mode, either the boot ROM area or the user ROM area can be selected with the user ROM area select bit (bit 5 at address 9E 16). The boot ROM area is located at addresses C00016 to FFFF 16 (byte addresses) in the boot mode. A reprogramming control firmware used in the flash memory serial I/O mode has been stored in the boot ROM area on shipment. (Refer to section "20.3 Flash memory serial I/O mode.") Therefore, when being reset in the boot mode, the flash memory version enters the flash memory serial I/O mode, allowing the user ROM area to be reprogrammed with a dedicated serial programmer. Also the boot ROM area can be reprogrammed in the flash memory parallel I/O mode. If an appropriate reprogramming control software using the CPU reprogramming mode has been stored in the boot ROM area, reprogramming suitable for the user's system is enabled. Note that if the boot ROM area has been reprogrammed in the flash memory parallel I/O mode, the flash memory serial I/O mode cannot be used. 20-12 7902 Group User's Manual FLASH MEMORY VERSION 20.2 Flash memory CPU reprogramming mode 20.2 Flash memory CPU reprogramming mode In this mode, the user ROM area can be reprogrammed by the central processing unit (CPU) executing software commands. Therefore, this mode allows the user to reprogram the contents of the user ROM area with the microcomputer mounted on the final printed circuit board, without using any ROM programmer. Be sure to store the reprogramming control software into the user ROM area or the boot ROM area in advance. In the flash memory CPU reprogramming mode, however, opcodes cannot be fetched for the internal flash memory. Accordingly, be sure to transfer the reprogramming control software to an area other than the internal flash memory area (e.g. the internal RAM area) and then execute the software in this area. The flash memory CPU reprogramming mode is available in any of the single-chip, memory expansion, and boot modes. The software commands listed in Table 20.2.1 can be used in the flash memory CPU reprogramming mode. For details of each command, refer to section "20.2.5 Software commands." Note that commands and data must be read from and written into even-numbered addresses within the user ROM area, 16 bits at a time. At writing of command codes, the high-order 8 bits (D 8 to D 15) are ignored. Table 20.2.1 Software commands 2nd cycle 1st cycle Commands Read Array Read Status Register Clear Status Register Page Programming Block Erase Erase All Unlocked Block Lock Bit Programming Read Lock Bit Status Data Mode Address (D0 to D7) FF 16 Write Write 7016 Write 5016 Write 4116 Write 2016 Write A7 16 Write 7716 Write 7116 Mode Address 3rd cycle Data Read SRD Write Write Write Write Read WA BA BA BA WD D016 D016 D016 D6 Mode Address Write WA + 2 Data WD SRD : Status register data (D0 to D7) WA : Write address (A7 to A0 to be incremented by 2 from "0016" to "FE16") WD : Write data (16 bits) BA : The highest address of a block (Note that A 0 = 0.) D6 : Indicates the lock bit status. (Unlocked state when D6 = 1; Locked state when D6 = 0.) : Arbitrary even-numbered address in user ROM area (A0 = 0) 7902 Group User's Manual 20-13 FLASH MEMORY VERSION 20.2 Flash memory CPU reprogramming mode 20.2.1 Flash memory control register Figure 20.2.1 shows the structure of the flash memory control register. b7 b6 b5 b4 b3 b2 b1 b0 Flash memory control register (Address 9E16) Bit Bit name 0 Function At reset R/W RO 0 RY/BY status bit 0 : BUSY (Automatic programming or erase operation is active.) 1 : READY (Automatic programming or erase operation has been completed.) 1 1 CPU reprogramming mode select bit 0 : Flash memory CPU reprogramming mode is invalid. 1 : Flash memory CPU reprogramming mode is valid. 0 2 Lock bit invalidity select bit RW (Notes 1, 2) 0 : Lock bit is valid. 1 : Lock bit is invalid (Note 3). 0 Writing "1" followed with "0" into this bit discontinues the access to the internal flash memory. This causes the built-in flash memory circuit being reset. 0 RW (Note 6) RW (Notes 1, 4) 3 Flash memory reset bit (Note 5) 4 Fix this bit to "0." 0 RW 5 User ROM area select bit 0 : Access to boot ROM area (Valid in boot mode) (Note 7) 1 : Access to user ROM area 0 RW (Note 2) The value is "0" at reading. 0 -- 7, 6 Notes 1: In order to set this bit to "1," write "0" followed with "1" successively; while in order to clear this bit "0," write "0." 2: Writing to this bit must be performed in an area other than the internal flash memory. 3: Simultaneously with the CPU reprogramming mode select bit (bit 1) cleared "0," this bit is also cleared to "0." 4: Only when the CPU reprogramming mode select bit (bit 1) = "1," writing to this bit is available. 5: This bit is valid only when the CPU reprogramming mode select bit = "1": on the other hand, when the CPU reprogramming mode select bit = "0," be sure to fix this bit to "0." 6: After writing of "1" to this bit, be sure to write "0" successively. 7: When MD1 = Vss level, this bit is invalid. (It may be either "0" or "1.") Fig. 20.2.1 Structure of flash memory control register (1) RY/BY status bit (bit 0) This bit is used to indicate the operating status of the write state machine (hereafter referred to WSM) as well as the WSM status bit (SR.7 of the status register; refer to section "20.2.2 Status register."). This bit is "0" during the automatic programming or erase operation is active and becomes "1" upon completion of them. This bit also changes during the execution of the page programming, block erase, erase all unlocked block, or the lock bit programming command, but does not change owing to the execution of another command. (2) CPU reprogramming mode select bit (bit 1) Setting this bit to "1" allows the microcomputer to enter the flash memory CPU reprogramming mode to accept commands. In order to set this bit to "1," write "1" followed with "0" successively; while to clear this bit to "0," write "0." Since the microcomputer enters the flash memory CPU reprogramming mode after setting this bit to "1," opcodes cannot be fetched for the internal flash memory. Accordingly, be sure to execute the instruction to be used for writing to this bit in an area other than the internal flash memory area (e.g. the internal RAM area). When executing commands of the flash memory CPU reprogramming mode in the boot mode, be sure to set the user ROM area select bit (bit 5) to "1." 20-14 7902 Group User's Manual FLASH MEMORY VERSION 20.2 Flash memory CPU reprogramming mode (3) Lock bit invalidity select bit (bit 2) Setting this bit to "1" invalidates each lock bit for each block. (Refer to section "20.2.3 Data protect function.") and clearing it to "0" validates the lock bit. Writing to this bit is valid when the CPU reprogramming mode select bit (bit 1) = "1." In order to set the lock bit invalidity select bit to "1," write "1" followed with "0" successively; while in order to clear this bit "0," write "0." (4) Flash memory reset bit (bit 3) Writing "1" followed with "0" to this bit discontinues the access to the user ROM area and causes the built-in flash memory control circuit to be reset. After this reset, the microcomputer enters the read array mode to set the RY/BY status bit (bit 0) to "1" and the status register to "8016 ." (Refer to section "20.2.2 Status register.") When this flash memory control circuit is reset with the flash memory reset bit during programming (automatic programming) or erase (automatic erase) operation, that programming or erase operation is discontinued to invalidate the data in the working block. In order to write to this bit, write "1" followed with "0" using successive instructions. (5) User ROM area select bit (bit 5) This bit is used to select either the boot ROM area or the user ROM area in the boot mode. In order to access the boot ROM area (read out), clear this bit to "0." On the other hand, in order to access the user ROM area (reading out, programming, or erase), set it to "1." Instructions for writing into this bit must be executed in an area other than the internal flash memory (e.g. the internal RAM area). Note that when MD1 = Vss level, the user ROM area is accessed (being read out) regardless of the contents of this bit. 7902 Group User's Manual 20-15 FLASH MEMORY VERSION 20.2 Flash memory CPU reprogramming mode 20.2.2 Status register The programming and erase operations for the internal flash memory are controlled by the write state machine in the internal flash memory (hereafter referred to WSM). The status register indicates the operating status of the WSM and the completion states (normal or abnormal) of the programming and erase operations. For details of abnormal endings (errors), refer to section "20.2.6 Full status check." Table 20.2.2 lists the bit definition of the status register. The contents of the status register can be read out by the read status register command. (Refer to section "20.2.5 Software commands.") Table 20.2.2 Bit definition of status register Symbol (Data bus) SR.0 SR.1 SR.2 SR.3 SR.4 (D0) (D1) (D2) (D3) (D4) SR.5 (D5) SR.6 (D6) SR.7 (D7) Definition Status "1" "0" -- -- -- Block Status After Programming Block Status Erase Status -- Write State Machine (WSM) Status -- -- -- -- -- Terminated normally. Terminated normally. Terminated normally. -- -- BUSY Error <Excessive programming error> Error<Programming error> Error<Erase error> -- READY Data bus: Indicates the data bus to be read out when the read status register command has been executed. (1) Block status after programming bit (SR.3) When an excessive programming error has occurred, this bit is set to "1" upon completion of the page programming. Additionally, this bit is cleared to "0" by executing the clear status register command. This bit is also cleared to "0" at reset. (2) Programming status bit (SR.4) This bit is set to "1" if a programming error has occurred during the automatic programming (the page programming or lock bit programming) operation and cleared to "0" by executing the clear status register command. This bit is also cleared to "0" at reset. (3) Erase status bit (SR.5) This bit is set to "1" if an erase error has occurred during the automatic erase (the block erase or erase all unlocked block) operation and cleared to "0" by executing the clear status register command. This bit is also cleared to "0" at reset. (4) Write state machine (WSM) bit (SR.7) This bit is used to indicate the operating status of the WSM. It is "0" during the automatic programming or erase operation and set to "1" upon completion of these operations. This bit also changes during the execution of the page programming, block erase, erase all unlocked block, or the lock bit programming command, but this bit does not change by another command. This bit is set to "1" at reset. 20-16 7902 Group User's Manual FLASH MEMORY VERSION 20.2 Flash memory CPU reprogramming mode 20.2.3 Data protect function Each block of the internal flash memory is provided with a nonvolatile lock bit and can individually be inhibited from being programmed or erased (i.e. be locked) according to the state of the corresponding lock bit. Thus, this function prevents data from being inadvertently programmed or erased. The block states are described below according to the contents of their lock bits: * When lock bit = "0" Locked state. The corresponding block cannot be programmed or erased. * When lock bit = "1" Unlocked state. The corresponding block can be programmed or erased. Each lock bit is cleared to "0" (locked state) by executing the lock bit programming command and set to "1" (unlocked state) by erasing the corresponding block. The lock bit cannot be set to "1" by any software command. The state of a lock bit can be read out with the read lock bit status command. Setting the lock bit invalidity select bit (bit 2 at address 9E16 ) to "1" invalidates the functions of each lock bit to put all the blocks into the unlocked state. (The contents of all lock bits do not change.) On the other hand, clearing the lock bit invalidity select bit to "0" validates the functions of each lock bit. (The contents of all lock bits are maintained.) When the block erase or the erase all unlocked block command is executed with the lock bit invalidity select bit = "1," the corresponding block or all the blocks are erased regardless of the contents of their lock bits. Upon completion of this erasure, the corresponding lock bit is set to "1" (unlocked state). For details of each command, refer to section "20.2.5 Software commands." 20.2.4 Setting and Terminate procedure for flash memory CPU reprogramming mode Figure 20.2.2 shows the setting and terminate procedures for the flash memory CPU reprogramming mode. In the flash memory CPU reprogramming mode, opcodes cannot be fetched for the internal flash memory. Therefore, be sure to transfer the reprogramming control software to an area other than the internal flash memory and then execute the software in that area. Moreover, in order to prevent any interrupt occurrence during the flash memory CPU reprogramming mode, the following procedures must be taken before selecting this mode: * Set the interrupt disable flag (I) to "1" or set the interrupt priority level to "0002" (interrupts disabled) * Apply the Vcc level voltage to pin NMI; or open pin NMI with the pin NMI pullup select bit (bit 7 at address 92 16 ) = "0." Even in the flash memory CPU reprogramming mode, periodically writing to the watchdog timer is required in order to prevent the watchdog timer interrupt occurrence. At the same time, it is necessary to write to the watchdog timer before executing the page programming, block erase, erase all unlocked block, or lock bit programming command in order to prevent the watchdog timer interrupt occurrence during the automatic programming and erase operation. Interrupt requests or resets generated in the flash memory CPU reprogramming mode bring about the following results: * Maskable interrupts make program runaway. If a program runaway has occurred, be sure to push the microcomputer into the power-on reset state. * Each of NMI and watchdog timer interrupts pushes the built-in flash memory control circuit and flash memory control register into the reset state. This enables any of these interrupt requests to be accepted. * Each of hardware and software resets pushes the built-in flash memory control circuit and flash memory control register into the reset state. Additionally, this causes the microcomputer to be reset. (Refer to "CHAPTER 4. RESET.") When the above interrupts or resets are generated during the programming or erase operation, the contents of the corresponding block becomes invalidated. 7902 Group User's Manual 20-17 FLASH MEMORY VERSION 20.2 Flash memory CPU reprogramming mode Reprogramming control software Single-chip mode, Memory expansion mode, or Boot mode User ROM area select bit "1" (Only in the boot mode) Internal ROM bus cycle select bit "0" (bit 7 at address 5F16) Interrupt disable flag (I) = "1" or Interrupt priority level of each interrupt = "0002" CPU reprogramming mode select bit "0" CPU reprogramming mode select bit "1" Software command is executed. Pin NMI pullup select bit "0" (bit 7 at address 9216) The reprogramming control software for the flash memory CPU reprogramming mode is transferred to an area other than the internal flash memory. Jump to the control software transferred in the above procedure. (The subsequent procedures will be executed by the reprogramming control software transferred in the above procedure.) Read array command is executed, or Flash memory reset bit "1" Flash memory reset bit "0" (Note 1) CPU reprogramming mode select bit "0" User ROM area select bit "0" (Only in the boot mode ) (Note 2) Jump to an arbitrary address in the internal flash memory area. Notes 1: Before termination of the flash memory CPU reprogramming mode, be sure to execute the read array command or flash memory reset. 2: When the flash memory CPU reprogramming mode has been terminated with the user ROM area select bit = "1," the access to the user ROM area is selected. Fig. 20.2.2 Setting and Terminate procedures for flash memory CPU reprogramming mode 20.2.5 Software commands Software commands are described below. Software commands and data must be read from and written into even-numbered addresses in the user ROM area, 16 bits at a time. At writing of a command code, the high-order 8 bits (D8 to D 15) are ignored. (1) Read array command Writing command code "FF16" at the 1st bus cycle pushes the microcomputer into the read array mode. When an address to be read is input at the next and the following bus cycles, the contents at the specified address are output to the data bus (D0 to D 15 ), 16 bits at a time. The read array mode is maintained until another software command is written. (2) Read status register command Writing command code "7016 " at the 1st bus cycle outputs the contents of the status register to the data bus (D0 to D 7) by a read at the 2nd bus cycle. (See Table 20.2.2.) (3) Clear status register command Writing command code "50 16" at the 1st bus cycle clears three bits (SR.3 to SR.5) of the status register to "0." (See Table 20.2.2.) 20-18 7902 Group User's Manual FLASH MEMORY VERSION 20.2 Flash memory CPU reprogramming mode (4) Page programming command This command executes programming, 128 Start words (256 bytes) at a time. Write command code "4116" at the 1st bus cycle and then write data from the 2nd to the 129th bus cycles, 16 Command code "4116" is written. bits at a time. Additionally, increment the loworder 8 bits (A7 to A 0) of the write addresses (in other words, addresses to which data will n=0 be written) by 2 from "0016" to "FE16." After writing of 128 words has been completed, the automatic Write address Data is written to an programming (programming and verification of Write address + 2, arbitrary write address. data) operation is initiated. The completion of nn+2 the automatic programming can be recognized by the WSM status bit (SR.7 of the status n = FE16 NO register) or the RY/BY status bit (bit 0 at address YES 9E16 ). Simultaneously with the start of the automatic programming operation, the microcomputer RY/BY status bit = "1"? enters the read status register mode, allowing (bit 0 at address 9E16) NO the contents of the status register to be read. The read status register mode is maintained YES until the read array command (FF16) or read *** See Figure 20.2.8. Full status check lock bit status command (7116) is written or until the flash memory reset bit is set to "1." After the automatic programming operation has Page programming been completed, the result of it can be operation is completed. recognized by reading out the status register. (Refer to section "20.2.6 Full status check.") Fig. 20.2.3 Page programming operation flowchart Figure 20.2.3 shows the page programming operation flowchart. Note that, for the pages having already been programmed, be sure to program after an erase (block erase) operation. If the page programming command is executed for the pages having already been programmed, no programming error will occur, but the contents of the pages become undefined. 7902 Group User's Manual 20-19 FLASH MEMORY VERSION 20.2 Flash memory CPU reprogramming mode (5) Block erase command Writing of command code "2016 " at the 1st bus cycle and "D016 " to the highest address (here, A 0 = 0) of the block to be erased at the 2nd bus cycle initiate the automatic erase (erase and erase-verify) operation for the specified block. The completion of the automatic erase operation can be recognized by the WSM status bit (SR.7 of the status register) or the RY/BY status bit (bit 0 at address 9E 16). Simultaneously with the start of the automatic erase operation, the microcomputer enters the read status register mode, allowing the contents of the status register to be read. The read status register mode is maintained until the read array command (FF 16) or the read lock bit status command (71 16) is written or until the flash memory reset bit is set to "1." After the automatic erase operation is completed, the result of it can be recognized by reading out the status register. (Refer to section "20.2.6 Full status check.") Figure 20.2.4 shows the block erase operation flowchart. (6) Erase-all-unlocked-blocks command When the lock bit invalidity select bit = "0," writing of command code "A7 16" at the 1st bus cycle and "D016 " at the 2nd bus cycle initiate the automatic erase (erase and erase-verify) operation for all the blocks whose lock bits are "1" (unlocked state). The completion of the automatic erase operation can be recognized by the WSM status bit (SR.7 of the status register) or the RY/BY status bit (bit 0 at address 9E 16). Simultaneously with the start of the automatic erase operation, the microcomputer enters the read status register mode, allowing the contents of the status register to be read. The read status register mode is maintained until the read array command (FF 16) or the read lock bit status command (71 16) is written or until the flash memory reset bit is set to "1." After the automatic erase operation is completed, the result of it can be recognized by reading out the status register. (Refer to section "20.2.6 Full status check.") Figure 20.2.5 shows the erase-all-unlockedblocks operation flowchart. Start Blocks in locked state are erased. Blocks in unlocked state are erased. Lock bit invalidity select bit "0" Lock bit invalidity select bit "1" Lock bit invalidity select bit "0" (Note) Command code "2016" is written. "D016" is written to the highest address of the block. RY/BY status bit = "1"? (bit 0 at address 9E16) NO YES Blocks in locked state are erased. Blocks in unlocked state are erased. Lock bit invalidity select bit "0" Full status check *** See Figure 20.2.8. Block erase operation is completed. Note: When the erase operation is performed with the lock bits invalidated (the lock bit invalidity select bit = "1"), the lock bits of the blocks to be erased become "1" (unlocked state) after the automatic erase operation is completed. Fig. 20.2.4 Block erase operation flowchart Start All blocks are erased. Lock bit invalidity select bit "0" Lock bit invalidity select bit "1" Only blocks in unlocked state are erased. Lock bit invalidity select bit "0" (Note) Command code "A716" is written. "D016" is written. RY/BY status bit = "1"? (bit 0 at address 9E16) All blocks are erased. NO YES Only blocks in unlocked state are erased. Lock bit invalidity select bit "0" Full status check *** See Figure 20.2.8. Erase-all-unlocked-blocks operation is completed. Note: When the erase operation is performed with the lock bits invalidated (the lock bit invalidity select bit = "1"), the lock bits of all the blocks become "1" (unlocked state) after the automatic erase operation is completed. Fig. 20.2.5 Erase-all-unlocked-blocks operation flowchart 20-20 7902 Group User's Manual FLASH MEMORY VERSION 20.2 Flash memory CPU reprogramming mode (7) Lock bit programming command Writing of command code "7716 " at the 1st bus cycle and "D016" to the highest address (here, A 0 = 0) of a block at the 2nd bus cycle initiate writing "0" to the lock bit of the specified block (locked state). The completion of this writing can be recognized by the WSM status bit (SR.7 of the status register) or the RY/BY status bit (bit 0 at address 9E16 ). Simultaneously with writing to the lock bit, the microcomputer enters the read status register mode, allowing the contents of the status register to be read. The read status register mode is maintained until the read array command (FF16) or the read lock bit status command (7116 ) is written or until the flash memory reset bit is set to "1." After writing is completed, the result of it can be recognized by reading out the status register. (Refer to section "20.2.6 Full status check.") Figure 20.2.6 shows the lock bit programming operation flowchart. Start Command code "7716" is written. "D016" is written to the highest address of a block. RY/BY status bit = "1"? (bit 0 at address 9E16) NO YES SR.4 = 0? NO Lock bit programming error YES Lock bit programming operation is completed. Fig. 20.2.6 Lock bit programming operation flowchart (8) Read lock bit status command Writing of command code "7116 " at the 1st bus cycle and reading of the highest address of a block (here, A0 = 0) at the 2nd bus cycle allow the state of the lock bit of the specified block to be read onto the data bus (D6). Figure 20.2.7 shows the read lock bit status operation flowchart. Start Command code "7116" is written. The highest address of the block is read out. D6 = 0? NO YES Locked state Unlocked state Fig. 20.2.7 Read lock bit status operation flowchart 7902 Group User's Manual 20-21 FLASH MEMORY VERSION 20.2 Flash memory CPU reprogramming mode 20.2.6 Full status check If an error has occurred, bits SR.3 to SR.5 of the status register are set to "1" upon completion of the programming or erase operation. Therefore, the result of the programming or erase operation can be recognized by checking these status (in other words, full status check). Table 20.2.3 lists the errors and the states of bits SR.3 to SR.5, and Figure 20.2.8 shows the full status check flowchart and the action to be taken if any error has occurred. Table 20.2.3 Errors and States of bits SR.3 to SR.5 Status register Error Error occurrence conditions SR.5 SR.4 SR.3 0 Command sequen- * Commands are not correctly written. 1 1 ce error * Data other than "D016" and "FF16" is written at the 2nd bus cycle of the lock bit programming, block erase, or erase-all-unlocked-blocks command (Note 1). 1 0 0 Erase error * The block erase command is executed for locked blocks (Note 2). * Although the block erase or erase-all-unlocked-blocks command is 0 1 0 executed for unlocked blocks, these blocks are not correctly erased. Programming error * The page programming command is executed for pages in locked blocks (Note 2). * Although the programming command is executed for pages in unlocked blocks, these pages are not correctly programmed. * Although the lock bit programming command is executed, programming is not correctly performed. 0 0 1 Excessive progra- * Excessive programming has occurred upon completion of the page programming operation. mming error Notes 1: When "FF16" is written at the 2nd bus cycle of any of these commands, the microcomputer enters the read array mode. Simultaneously with this, the command code written at the 1st bus cycle is cancelled. 2: While the lock bit is invalid (the lock bit invalidity select bit = "1"), no error will occur even if one of these conditions is satisfied. 20-22 7902 Group User's Manual FLASH MEMORY VERSION 20.2 Flash memory CPU reprogramming mode Read status register SR.4 = 1 and SR.5 = 1 ? NO YES Command sequence * * * * Execute the clear status command to clear SR.4 and SR.5 to "0." error Execute the correct command again. Note: If the same error occurs, however, the block cannot be used. SR.5 = 0? NO Erase error **** YES Execute the clear status command to clear SR.5 to "0." Execute the read lock bit status command. If the lock bit of the block where an error has occurred, be sure to set the lock bit invalidity select bit (bit 2 at address 9E16) to "1." Execute the block erase or erase-all-unlocked-blocks command again. Note: If the same error occurs, however, the block cannot be used. Also, when the lock bit in = "1," the block cannot be used. Programming error * * * * [At page programming command execution] SR.4 = 0? NO Execute the clear status command to clear SR.4 to "0." Execute the read lock bit status command. If the lock bit of the block where an error has occurred, be sure to set the lock bit invalidity select bit (bit 2 at address 9E16) to "1." Execute the page programming command again. Note: If the same error occurs, however, the block cannot be used. Also, when the lock bit in = "1," the block cannot be used. YES [At lock bit programming command execution] Execute the clear status command to clear SR.4 to "0." Set the lock bit invalidity select bit (bit 2 at address 9E16) to "1." Execute the block erase command to erase the block where an error has occurred. Execute the lock bit programming command again. Note: If the same error occurs, however, the block cannot be used. SR.3 = 0? YES NO Excessive programming error * * * * Execute the clear status command to clear SR.3 to "0." Execute the block erase command to erase the block where an error has occurred. Execute the page programming command again. Note: If the same error occurs, however, the block cannot be used. Completed. Note: Under the condition that any of SR.5, SR.4, and SR.3 = "1," none of the page programming, block erase, erase-all-unlocked-blocks, and lock bit programming commands can be accepted. To execute any of these commands, in advance, execute the clear status register command. Fig. 20.2.8 Full status check flowchart and actions to be taken if any error has ocurred 7902 Group User's Manual 20-23 FLASH MEMORY VERSION 20.2 Flash memory CPU reprogramming mode 20.2.7 Electrical characteristics (1) M37902FGCGP DC Electrical Characteristics (V CC = 5 V 0.5 V, Ta = 0 to 60 C, f(fsys) = 26 MHz) Limits Symbol Parameter Min. Typ. ICC1 V CC power source current (at read) 30 ICC2 V CC power source current (at write) ICC3 V CC power source current (at programming) ICC4 V CC power source current (at erasing) Max. 48 48 54 54 AC Electrical Characteristics (V CC = 5 V 0.5 V, Ta = 0 to 60 C, f(fsys) = 26 MHz) Limits Parameter Min. Typ. Page programming time 8 Block erase time 50 Erase all unlocked blocks time 50 n Lock bit programming time 8 Max. 120 600 600 n 120 Unit mA mA mA mA Unit ms ms ms ms n = Number of blocks to be erased For the limits of parameters other than the above, refer to section "Appendix 9. M37902FGCGP electrical characteristics." (2) M37902FGMHP DC Electrical Characteristics (V CC = 3.3 V 0.3 V, Ta = 0 to 60 C, f(fsys) = 26 MHz) Limits Symbol Parameter Min. Typ. ICC1 V CC power source current (at read) 19 ICC2 V CC power source current (at write) ICC3 V CC power source current (at programming) ICC4 V CC power source current (at erasing) Max. 40 40 48 48 AC Electrical Characteristics (V CC = 3.3 V 0.3 V, Ta = 0 to 60 C, f(fsys) = 26 MHz) Limits Parameter Min. Typ. 8 Page programming time Block erase time 50 Erase all unlocked blocks time 50 n Lock bit programming time 8 Max. 120 600 600 n 120 Unit mA mA mA mA Unit ms ms ms ms n = Number of blocks to be erased For the limits of parameters other than the above, refer to section "Appendix 10. M37902FGMHP electrical characteristics." 20-24 7902 Group User's Manual FLASH MEMORY VERSION [Precautions for flash memory CPU reprogramming mode] [Precautions for flash memory CPU reprogramming mode] 1. In the flash memory CPU reprogramming mode, an opcode cannot be fetched for the internal flash memory. Accordingly, be sure to transfer the reprogramming control software to an area other than the internal flash memory area, and then execute it in this area. (See Figure 20.2.2.) Also, take consideration for instruction description (such as specified addresses, addressing modes) in the reprogramming control software since this software is to be executed in an area other than the internal flash memory area. 2. In order to prevent any interrupt occurrence during the flash memory CPU reprogramming mode, the following procedures must be taken before selecting this mode: * Set the interrupt disable flag (I) to "1"; or set the interrupt priority level to "0002" (interrupts disabled) * Apply the Vcc level voltage to pin NMI; or open pin NMI with the pin NMI pullup select bit (bit 7 at address 9216) = "0." Even in the flash memory CPU reprogramming mode, periodically writing to the watchdog timer is required. 3. Commands and data must be read from and written into even-numbered addresses in the user ROM area, 16 bits at a time. 4. Addresses FFB016 to FFBF16 (the user ROM area) are reserved for serial programmers. Therefore, when there is a possibility that the flash memory serial I/O mode is used, be sure not to program to this area. 7902 Group User's Manual 20-25 FLASH MEMORY VERSION 20.3 Flash memory serial I/O mode 20.3 Flash memory serial I/O mode In the flash memory serial I/O mode, by using a dedicated serial programmer, the contents of the user ROM area can be reprogrammed with the microcomputer mounted on the final printed circuit board. About the serial programmer concerned, consult its manufacturer, and for more information on using it, refer to the user's manual of the serial programmer. Note that if the boot ROM area has been reprogrammed in the flash memory parallel I/O mode, the flash memory serial I/O mode cannot be used. (Refer to section "20.4 Flash memory parallel I/O mode.") Addresses FFB016 to FFBF 16 (the user ROM area) are reserved for serial programmers. Therefore, be sure not to program to this area. 20.3.1 Pin description Table 20.3.1 lists the pin description in the flash memory serial I/O mode, and Figures 20.3.1 and 20.3.2 show the pin configuration in this mode. 20-26 7902 Group User's Manual FLASH MEMORY VERSION 20.3 Flash memory serial I/O mode Table 20.3.1 Pin description in flash memory serial I/O mode Pin Name V CC V SS Power supply input MD0 MD1 BYTE MD0 MD1 External data bus width select input Reset input Clock input RESET X IN X OUT NMI V CONT AV CC AVSS V REF P00 to P07 P10 to P17 P20 to P27 P30 to P33 P40, P44 to P47 Functions Supply V CC level voltage to pin Vcc. Supply V SS level voltage to pin Vss. Input Input Input Connect this pin to VSS . Connect this pin to VSS via a resistor (about 10 k to 100 k). The BYTE pin. (Not used in this mode.) Input The reset input pin (Note 1). Input Connect a ceramic resonator or quartz-crystal oscillator between Clock output Output X IN and X OUT pins. When using an external clock, the clcok source must be input to X IN pin and X OUT pin must be left open. NMI interrupt input Input Connect this pin to VCC, or leave it open. Filter circuit connection -- The V CONT pin. (Not used in this mode.) Analog supply input Connect this pin to VCC. Connect this pin to VSS . Reference voltage input Input port P0 Input port P1 Input port P2 Input port P3 Input port P4 P41 P42 SCLK input P43 P50 to P57 BUSY output Input port P5 Input port P6 P60 to P67 P70 to P77 P80 to P87 P100 to P107 P110 to P117 Input/Output SDA I/O Input Input Input Input port port port port P7 P8 P10 P11 Input Input Input The V REF pin. (Not used in this mode.) Input port pins. (Not used in this mode.) Input Input Input Input I/O The input pin for a serial clock. The I/O pin for serial data. This pin must be connected to an external pullup resistor (about 1 k). Output The BUSY signal output pin. Input Input port pins. (Not used in this mode.) Input Input Input Input Input Notes 1: When there is a possibility that the user reset signal becomes "L" level in the flash memory serial I/O mode, be sure to cut off the current flow between the user reset signal and pin RESET by using a jumper switch, etc. (Refer to section "19.2 Examples of handling control pins in flash memory serial I/O mode.") 2: For pins not used in the flash memory serial I/O mode, properly connect to somewhere in the user system. For pins not used in the user system, handle them with reference to section "6.3 Examples of handling unused pins." For pins used in the flash memory serial I/O mode, handle them with reference to section "19.2 Examples of handling control pins in flash memory serial I/O mode." 7902 Group User's Manual 20-27 20-28 BUSY SDA SCLK 1 7902 Group User's Manual 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 VCC P86/RXD1 P85/CTS1/CLK1 P84/CTS1/RTS1/INT4 P83/TXD0 P82/RXD0 P81/CTS0/CLK0 VCC AVCC VREF AVSS VSS NMI P80/CTS0/RTS0/DA2/INT3 P77/AN7/ADTRG/DA1/(INT2) P76/AN6/DA0 P75/AN5/(INT4) P74/AN4/(INT3) P73/AN3 P47/CS3 P46/CS2 P45/CS1 P44/CS0 P43/HOLD P42/HLDA P41/1 P40/ALE P33/BHW P32/BLW P31/RD P72/AN2 P71/AN1 P70/AN0 P67/TB2IN P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/RTP13/KI3 P56/TA3OUT/RTP12/KI2 P55/TA2IN/RTP11/KI1 P54/TA2OUT/RTP10/KI0 P53/TA1IN/RTP03 P52/TA1OUT/RTP02 P51/TA0IN/RTP01 P50/TA0OUT/RTP00 P100/A0 P87/TxD1 M37902FGCGP 31 32 33 34 35 36 37 38 39 40 41 42 43 44 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 VSS MD1 P10/D0/LA0 P11/D1/LA1 P12/D2/LA2 P13/D3/LA3 P14/D4/LA4 P101/A1 P102/A2 P103/A3 P104/A4 P105/A5 P106/A6 P107/A7 P110/A8 P111/A9 P112/A10 P113/A11 P114/A12 P115/A13 P116/A14 P117/A15 P00/A16 P01/A17 P02/A18 P03/A19 P04/A20 P05/A21 P06/A22 P07/A23 MD1 FLASH MEMORY VERSION 20.3 Flash memory serial I/O mode P15/D5/LA5 P16/D6/LA6 P17/D7/LA7 P20/D8 P21/D9 P22/D10 P23/D11 P24/D12 P25/D13 P26/D14 P27/D15 VCC XOUT XIN VSS MD0 RESET VCONT BYTE P30/RDY Outline 100P6S-A Fig. 20.3.1 Pin connection in flash memory serial I/O mode (Outline: 100P6S-A) RESET VSS : Connected to the oscillation circuit. : Connected to VCC or kept open. : Connected to a serial programmer. BUSY SDA SCLK P70/AN0 P67/TB2IN P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/RTP13/KI3 P56/TA3OUT/RTP12/KI2 P55/TA2IN/RTP11/KI1 P54/TA2OUT/RTP10/KI0 P53/TA1IN/RTP03 P52/TA1OUT/RTP02 P51/TA0IN/RTP01 P50/TA0OUT/RTP00 P47/CS3 P46/CS2 P45/CS1 P44/CS0 P43/HOLD P42/HLDA P41/1 P40/ALE 7902 Group User's Manual 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 AVSS VSS NMI P80/CTS0/RTS0/DA2/INT3 P77/AN7/ADTRG/DA1/(INT2) P76/AN6/DA0 P75/AN5/(INT4) P74/AN4/(INT3) P73/AN3 P72/AN2 P71/AN1 2 1 VCC P103/A3 P102/A2 P101/A1 P100/A0 P87/TXD1 P86/RXD1 P85/CTS1/CLK1 P84/CTS1/RTS1/INT4 P83/TXD0 P82/RXD0 P81/CTS0/CLK0 VCC AVCC VREF 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 M37902FGMHP 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 P104/A4 P105/A5 P106/A6 P107/A7 P110/A8 P111/A9 P112/A10 P113/A11 P114/A12 P115/A13 P116/A14 P117/A15 P00/A16 P01/A17 P02/A18 P03/A19 P04/A20 P05/A21 P06/A22 P07/A23 VSS MD1 P10/D0/LA0 P11/D1/LA1 P12/D2/LA2 MD1 FLASH MEMORY VERSION 20.3 Flash memory serial I/O mode P13/D3/LA3 P14/D4/LA4 P15/D5/LA5 P16/D6/LA6 P17/D7/LA7 P20/D8 P21/D9 P22/D10 P23/D11 P24/D12 P25/D13 P26/D14 P27/D15 VCC XOUT XIN VSS MD0 RESET VCONT BYTE P30/RDY P31/RD P32/BLW P33/BHW RESET VSS : Connected to the oscillation circuit. : Connected to VCC or kept open. : Connected to a serial programmer. Outline 100P6Q-A Fig. 20.3.2 Pin connection in flash memory serial I/O mode (Outline: 100P6Q-A) 20-29 FLASH MEMORY VERSION [Precautions for flash memory serial I/O mode] [Precautions for flash memory serial I/O mode] 1. If the boot ROM area has been reprogrammed in the flash memory parallel I/O mode, the flash memory serial I/O mode cannot be used. 2. In order to prevent any interrupt occurrence during the flash memory serial I/O mode, one of the following proce dures must be taken: * Connect pin NMI to Vcc. * Leave pin NMI open. (Refer to section "19.2 Examples of handling control pins in flash memory serial I/O mode.") 3. When there is a possibility that the user reset signal becomes "L" level in the flash memory serial I/O mode, be sure to cut the current flow between the user reset pin and pin RESET by using a jumper switch, etc. (Refer to section "19.2 Examples of handling control pins in flash memory serial I/O mode.") 4. Addresses FFB016 to FFBF16 (the user ROM area) are reserved for serial programmers. Therefore, be sure not to program to this area. 20-30 7902 Group User's Manual FLASH MEMORY VERSION 20.4 Flash memory parallel I/O mode 20.4 Flash memory parallel I/O mode In the flash memory parallel I/O mode, the contents of the user ROM area and boot ROM area can be reprogrammed by using a dedicated parallel programmer. (See Figure 20.1.7.) About the parallel programmer concerned, consult its manufacturer, and for more information on using it, refer to the user's manual of the parallel programmer. In the flash memory parallel I/O mode, the boot ROM area is assigned to addresses 0 16 to 1FFFF 16 (word addresses). Note that if the boot ROM area has been reprogrammed in the flash memory parallel I/O mode, the flash memory serial I/O mode cannot be used. (Refer to section "20.3 Flash memory serial I/O mode.") In the flash memory parallel I/O mode, the programming and erase voltages = 3.3 V0.3 V regardless of the type of microcomputer. For details of functions, refer to the corresponding latest datasheets. 7902 Group User's Manual 20-31 FLASH MEMORY VERSION [Precautions for flash memory parallel I/O mode] [Precautions for flash memory parallel I/O mode] 1. If the boot ROM area has been reprogrammed in the flash memory parallel I/O mode, the flash memory serial I/O mode cannot be used. (Refer to section "20.3 Flash memory serial I/O mode.") 2. In the flash memory parallel I/O mode, only the word addresses are available. 3. Addresses FFB016 to FFBF16 (the user ROM area; byte addresses) are reserved for serial programmers. Therefore, when there is a possibility that the flash memory serial I/O mode is used, be sure not to program to this area. 20-32 7902 Group User's Manual APPENDIX Appendix 1. Memory assignment in SFR area Appendix 2. Control registers Appendix 3. Package outline Appendix 4. E x a m p l e s o f h a n d l i n g unused pins Appendix 5. Hexadecimal instruction code table Appendix 6. Machine instructions Appendix 7. Countermeasure against noise Appendix 8. 7902 Group Q & A Appendix 9. M37902FGCGP electrical characteristics Appendix 10. M37902FGMHP electrical characteristics Appendix 11. Standard characteristics Appendix 12. Memory assignment of 7902 Group APPENDIX Appendix 1. Memory assigment in SFR area Appendix 1. Memory assigment in SFR area Access characteristics RW : It is possible to read the bit state at reading. The written value becomes valid. RO : It is possible to read the bit state at reading. The written value becomes invalid. WO : The written value becomes valid. It is impossible to read the bit state. : Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid. State immediately after reset 0 : "0" immediately after reset. 1 : "1" immediately after reset. ? : Undefined immediately after reset. Address 0 16 1 16 2 16 3 16 4 16 5 16 6 16 7 16 8 16 9 16 A 16 B 16 C16 D16 E 16 F 16 10 16 11 16 12 16 13 16 14 16 15 16 16 16 17 16 18 16 19 16 1A 16 1B 16 1C16 1D16 1E 16 1F 16 Register name Port P0 register Port P1 register Port P0 direction register Port P1 direction register Port P2 register 0 : Always "0" at reading. 1 : Always "1" at reading. ? : Always undefined at reading. 0 : "0" immediately after reset. Fix this bit to "0." b7 Access characteristics Port P3 direction register Port P4 register Port P5 register Port P4 direction register Port P5 direction register Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register Port P8 direction register Port P10 register Port P11 register Port P10 direction register Port P11 direction register A-D control register 0 A-D control register 1 State immediately after reset RW 0 0 0 RW 0 0 0 0 ?0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Notes 1: Do not read and write. 21-2 b7 (Note 1) (Note 1) RW RW RW RW RW Port P3 register Port P2 direction register b0 7902 Group User's Manual ? ? ? ? 0016 0016 ? 0 0016 0 0 ? ? 0016 0016 ? ? 0016 0016 ? ? 0016 ? ? ? 0016 0016 ? ? ? ? 0 0 0 0 b0 ? 0 0 0 ? 0 ? 1 ? 1 APPENDIX Appendix 1. Memory assigment in SFR area Access characteristics RW : It is possible to read the bit state at reading. The written value becomes valid. RO : It is possible to read the bit state at reading. The written value becomes invalid. WO : The written value becomes valid. It is impossible to read the bit state. : Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid. State immediately after reset 0 : "0" immediately after reset. 1 : "1" immediately after reset. ? : Undefined immediately after reset. Address 0 : Always "0" at reading. 1 : Always "1" at reading. ? : Always undefined at reading. 0 : "0" immediately after reset. Fix this bit to "0." Register name A-D register 0 2016 2116 A-D register 1 2216 2316 A-D register 2 2416 2516 A-D register 3 2616 2716 A-D register 4 2816 2916 2A16 A-D register 5 2B16 2C16 A-D register 6 2D16 A-D register 7 2E16 2F16 3016 UART0 transmit/receive mode register UART0 baud rate register 3116 3216 UART0 transmit buffer register 3316 3416 UART0 transmit/receive control register 0 3516 UART0 transmit/receive control register 1 3616 UART0 receive buffer register 3716 3816 UART1 transmit/receive mode register UART1 baud rate register 3916 3A16 UART1 transmit buffer register 3B16 3C16 UART1 transmit/receive control register 0 3D16 UART1 transmit/receive control register 1 3E16 UART1 receive buffer register 3F16 b7 Access characteristics b0 State immediately after reset b7 RO RO RO 0 0 0 0 0 ? 0 0 ? 0 0 ? 0 0 ? 0 0 ? 0 0 ? 0 0 ? 0 0 0016 ? ? ? 0 1 0 0 ? 0 0 0016 ? ? ? 0 1 0 0 ? 0 0 0 ? 0 RO ? RO RO 0 0 0 0 RO ? RO RO 0 0 0 0 RO ? RO RO 0 0 0 0 ? RO RO RO 0 0 0 0 ? RO RO RO 0 0 0 0 RO ? RO RO 0 0 0 RO RO 0 0 0 WO RW RW RO RW 0 0 0 0 0 0 RO 0 0 0 WO RW RW RO RW 0 0 0 0 0 0 RO 0 0 0 RW WO WO RO RO RW WO WO RW RO RO 0 ? RO RW RO b0 ? RO 7902 Group User's Manual 0 0 0 1 0 0 0 0 ? 0 0 0 1 0 0 0 0 ? 21-3 APPENDIX Appendix 1. Memory assigment in SFR area Access characteristics RW : It is possible to read the bit state at reading. The written value becomes valid. RO : It is possible to read the bit state at reading. The written value becomes invalid. WO : The written value becomes valid. It is impossible to read the bit state. : Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid. State immediately after reset 0 : "0" immediately after reset. 1 : "1" immediately after reset. ? : Undefined immediately after reset. Address 0 : Always "0" at reading. 1 : Always "1" at reading. ? : Always undefined at reading. 0 : "0" immediately after reset. Fix this bit to "0." Access characteristics Register name State immediately after reset b0 b7 RW Count start register 4 0 16 4 1 16 RW WO One-shot start register 4 2 16 4 3 16 Up-down register WO RW 4 4 16 RW RW 4 5 16 Timer A clock division select register (Note 2) 4 6 16 Timer A0 register (Note 2) 4 7 16 (Note 2) 4 8 16 Timer A1 register 4 9 16 (Note 2) 4A16 (Note 2) Timer A2 register (Note 2) 4B16 4C16 (Note 2) Timer A3 register (Note 2) 4D16 4E16 (Note 2) Timer A4 register (Note 2) 4F 16 5 0 16 (Note 3) Timer B0 register 5 1 16 (Note 3) (Note 3) 5 2 16 Timer B1 register (Note 3) 5 3 16 (Note 3) 5 4 16 Timer B2 register (Note 3) 5 5 16 Timer A0 mode register RW 5 6 16 Timer A1 mode register RW 5 7 16 Timer A2 mode register RW 5 8 16 Timer A3 mode register RW 5 9 16 Timer A4 mode register 5A16 RW Timer B0 mode register RW (Note 4) 5B16 RW Timer B1 mode register RW (Note 4) 5C16 RW Timer B2 mode register RW (Note 4) 5D16 RW RW RW WO 5E16 Processor mode register 0 5F 16 Processor mode register 1 (Note 7) RWRW (Note 6) RW RW (Note 6) RW RW b0 b7 0 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? 0 (Note 5) 0 0016 ? 0 0 ? 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0016 0016 0016 0016 0016 ? 0 ? 0 ? 0 0 1 (Note 5) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Note 5) 0 Notes 2: The access characteristics at addresses 4616 to 4F16 vary according to the timer A's operating mode. (Refer to "CHAPTER 9. TIMER A.") 3: The access characteristics at addresses 5016 to 5516 vary according to the timer B's operating mode. (Refer to "CHAPTER 10. TIMER B.") 4: The access characteristics for bit 5 at addresses 5B16 and 5D16 vary according to the timer B's operating mode. (Refer to "CHAPTER 10. TIMER B.") 5: This bit is "0" when Vss-level voltage is applied to pin MD0; this bit is "1" when Vcc-level voltage is applied. 6: After reset, this bit can be set to "1" only once. Once this bit goes from "1" to "0," it cannot be set to "1" again. (This bit is fixed to "0.") 7: In the external ROM version, for bit 7, nothing is assigned. This bit is "0" at reading. 21-4 7902 Group User's Manual APPENDIX Appendix 1. Memory assigment in SFR area Access characteristics RW : It is possible to read the bit state at reading. The written value becomes valid. RO : It is possible to read the bit state at reading. The written value becomes invalid. WO : The written value becomes valid. It is impossible to read the bit state. : Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid. State immediately after reset 0 : "0" immediately after reset. 1 : "1" immediately after reset. ? : Undefined immediately after reset. Address 0 : Always "0" at reading. 1 : Always "1" at reading. ? : Always undefined at reading. 0 : "0" immediately after reset. Fix this bit to "0." Access characteristics Register name 60 16 61 16 62 16 63 16 64 16 65 16 66 16 67 16 68 16 69 16 6A 16 6B 16 6C16 6D16 6E 16 6F 16 70 16 71 16 72 16 73 16 74 16 75 16 76 16 77 16 78 16 79 16 7A 16 7B 16 7C16 7D16 7E 16 7F 16 Watchdog timer register Watchdog timer frequency select register RW RW Particular function select register 0 Particular function select register 1 State immediately after reset b0 b7 RW (Note 8) RW RW (Note 10) RW RW RW RW (Note 11) Particular function select register 2 Debug control register 0 Debug control register 1 Address comparison register 0 Address comparison register 1 INT3 interrupt control register INT4 interrupt control register A-D conversion interrupt control register UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register INT2 interrupt control register (Note 13) RW RO RO RW RW RW RO RW RW (Note 14) RW (Note 14) RW (Note 14) RW (Note 14) RW (Note 14) RW (Note 14) RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW b7 b0 ? (Note 9) 0 0 0 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Note 12) ? ? 1 0 (Note 12) 0 0 (Note 12) 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 ? ? ? 0 0 0 0 0 0 0 ? 0 0 0 0 ? 0 0 0 0 ? 0 0 0 0 ? 0 0 0 0 ? 0 0 0 0 ? 0 0 0 0 ? 0 0 0 0 ? 0 0 0 0 ? 0 0 0 0 ? 0 0 0 0 ? 0 0 0 0 ? 0 0 0 0 0 0 ? 0 0 0 0 0 0 ? 0 0 0 0 0 0 ? Notes 8 : By writing dummy data to address 6016, a value of "FFF16" is set to the watchdog timer. The dummy data is not retained anywhere. 9 : A value of "FFF16" is set to the watchdog timer. (Refer to "CHAPTER 15. WATCHDOG TIMER.") 10 : After writing "5516" to address 6216, each bit must be set. 11 : It is possible to read the bit state at reading. By writing "0" to this bit, this bit becomes "0." But when writing "1" to this bit, this bit will not change. 12 : This bit becomes "0" at power-on reset. This bit retains the state immediately before reset in the case of hardware reset and software reset. 13 : Do not write. 14 : When these registers are accessed, set the address comparison register access enable bit (bit 2 at address 6716) to "1." (Refer to "CHAPTER 18. DEBUG FUNCTION.") 7902 Group User's Manual 21-5 APPENDIX Appendix 1. Memory assigment in SFR area Access characteristics RW : It is possible to read the bit state at reading. The written value becomes valid. RO : It is possible to read the bit state at reading. The written value becomes invalid. WO : The written value becomes valid. It is impossible to read the bit state. : Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid. State immediately after reset 0 : "0" immediately after reset. 1 : "1" immediately after reset. ? : Undefined immediately after reset. Address 0 : Always "0" at reading. 1 : Always "1" at reading. ? : Always undefined at reading. 0 : "0" immediately after reset. Fix this bit to "0." Access characteristics Register name State immediately after reset b0 b7 CS0 control register L 80 16 RW RW RO RW RW RW CS0 control register H 81 16 RW CS1 control register L 82 16 RW RW RW CS 1 control register H 83 16 RW RW CS2 control register L 84 16 RW RW CS2 control register H 85 16 RW RW RW RW RW 86 16 CS3 control register L 87 16 RW CS3 control register H 88 16 89 16 8A16 Area CS0 start address register RW 8B16 8C16 Area CS1 start address register RW 8D16 8E16 Area CS2 start address register RW 8F 16 RW 90 16 Area CS3 start address register 91 16 Port function control register 92 16 RW 93 16 94 16 External interrupt input control register RW RO 95 16 External interrupt input read-out register D-A control register 96 16 RW RW RW 97 16 98 16 RW D-A register 0 99 16 D-A register 1 RW RW 9A16 D-A register 2 9B16 (Note 17) 9C16 9D16 (Note 17) 9E16 Flash memory control register (Note 18) RW RO 9F 16 Notes 15 : 16 : 17 : 18 : 21-6 b0 b7 (Note 15) 1 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Note 16) 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ? ? 0 0 0 1 0 0 0 0 ? ? 0 0 0 0 ? 0 0 0 0 0 0 0 0 ? ? 0 0 0 0 ? ? 0 0 0 ? 0016 0016 0016 ? ? ? 0 0 ? This bit is "0" when Vss-level voltage is applied to pin MD0; this bit is "1" when Vcc-level voltage is applied. This bit is "0" when Vss-level voltage is applied to pin BYTE; this bit is "1" when Vcc-level voltage is applied. Do not write. This register is allocated only to the flash memory version. (Refer to "CHAPTER 20. FLASH MEMORY VERSION.") Do not write to this register in the mask ROM and external ROM versions. 7902 Group User's Manual APPENDIX Appendix 1. Memory assigment in SFR area Access characteristics RW : It is possible to read the bit state at reading. The written value becomes valid. RO : It is possible to read the bit state at reading. The written value becomes invalid. WO : The written value becomes valid. It is impossible to read the bit state. : Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid. State immediately after reset 0 : "0" immediately after reset. 1 : "1" immediately after reset. ? : Undefined immediately after reset. Address A0 16 A1 16 A2 16 A3 16 A4 16 A5 16 A6 16 A7 16 A8 16 A9 16 AA 16 AB 16 AC 16 AD 16 AE 16 AF 16 B0 16 B1 16 B2 16 B3 16 B4 16 B5 16 B6 16 B7 16 B8 16 B9 16 BA 16 BB 16 BC 16 BD 16 BE 16 BF 16 0 : Always "0" at reading. 1 : Always "1" at reading. ? : Always undefined at reading. 0 : "0" immediately after reset. Fix this bit to "0." Register name b7 Access characteristics RW Real-time output control register Serial I/O pin control register State immediately after reset b7 0 0 0 0 WO RW RW RW RW 0 0 0 0 RW RW RW RW (Note 20) RW RW (Note 19) (Note 19) (Note 19) 0 0 0 0 0 0 0 0 1 1 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (Note 19) (Note 19) Clock control register b0 0 ? ? ? ? ? ? ? ? ? ? ? WO Pulse output data register 0 Pulse output data register 1 b0 0 0 0 0 ? ? ? Notes 19 : Do not write to this register. 20 : After reset, these bits are allowed to be changed only once. 7902 Group User's Manual 21-7 APPENDIX Appendix 2. Control registers Appendix 2. Control registers The control registers allocated in the SFR area are shown on the following pages. Below is the structure diagram for all registers. 3 2 XXX register (address XX16) Bit 1 b7 b6 b5 b4 b3 b2 b1 b0 5 Bit name Function 0 * * * select bit 0:... 1:... The value is "0" at reading. 1 * * * select bit b2 b1 00:... 01:... 10:... 11:... 2 0:... 1:... At reset R/W Reference Undefined WO 3-10 0 RW 3-11 0 RW 0 RO 3 * * * flag 4 Fix this bit to "0." 0 RW 5 This bit is invalid in ... mode. 0 RW 6 Nothing is assigned. Undefined - 7 The value is "0" at reading. 0 - 6 1 Blank 0 1 : Set to "0" or "1" according to the usage. : Set to "0" at writing. : Set to "1" at writing. : Invalid depending on the mode or state. It may be "0" or "1." : Nothing is assigned. 2 0 1 Undefined : "0" immediately after reset. : "1" immediately after reset. : Undefined immediately after reset. 3 RW RO WO -- 4 21-8 4 X 0 : It is possible to read the bit state at reading. The written value becomes valid. : It is possible to read the bit state at reading. The written value becomes invalid. Accordingly, the written value may be "0" or "1." : The written value becomes valid. It is impossible to read the bit state. The value is undefined at reading. However, when ["0" at reading"] is indicated in the "Function" or "Note" column, the bit is always "0" at reading. (See 5 above.) : It is impossible to read the bit state. The value is undefined at reading. However, when ["0" at reading"] is indicated in the "Function" or "Note" column, the bit is always "0" at reading. (See 6 above.) The written value becomes invalid. Accordingly, the written value may be "0" or "1." Reference page for each bit. 7902 Group User's Manual 2-6 APPENDIX Appendix 2. Control registers b7 b6 b5 b4 b3 b2 b1 b0 Port Pi register (i = 0 to 8, 10, 11) (Addresses 216, 316, 616, 716, A16, B16, E16, F16, 1216, 1616, 1716) Bit Funtion Bit name At reset R/W Reference Undefined RW 6-4 Undefined RW Undefined RW Undefined RW 0 Pin port Pi0 1 Pin port Pi1 2 Pin port Pi2 3 Pin port Pi3 4 Pin port Pi4 Undefined RW 5 Pin port Pi5 Undefined RW 6 Pin port Pi6 Undefined RW 7 Pin port Pi7 Undefined RW Data is input from or output to a pin by reading from or writing to the corresponding bit. 0 : "L" level 1 : "H" level Note: Nothing is assigned for bits 4 to 7 of the port P3 register. These bits are "0" at reading. b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (i = 0 to 8, 10, 11) (Addresses 416, 516, 816, 916, C16, D16, 1016, 1116, 1416, 1816, 1916) Bit 0 Bit name Port Pi0 direction bit 1 Port Pi1 direction bit 2 Port Pi2 direction bit 3 Function 0 : Input mode (The port functions as an input port) 1 : Output mode (The port functions as an output port) At reset R/W 0 RW 0 RW 0 RW Port Pi3 direction bit 0 RW 4 Port Pi4 direction bit 0 RW 5 Port Pi5 direction bit 0 RW 6 Port Pi6 direction bit 0 RW 7 Port Pi7 direction bit 0 RW Reference 6-3 Port P5 8-6 9-8 11-6 Port P6 7-19 9-8 10-6 Port P7 7-19 13-10 Port P8 7-19 12-18 Note: Nothing is assigned for bits 4 to 7 of the port P3 direction register. These bits are "0" at reading. 7902 Group User's Manual 21-9 APPENDIX Appendix 2. Control registers b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 0 (Address 1E16) Bit 0 1 2 3 Bit name Function b2 b1 b0 Analog input select bits 0 0 0 : AN0 is selected. (Valid in the one-shot and repeat 0 0 1 : AN1 is selected. 0 1 0 : AN2 is selected. modes.) (Note 1) 0 1 1 : AN3 is selected. 1 0 0 : AN4 is selected. 1 0 1 : AN5 is selected. 1 1 0 : AN6 is selected. 1 1 1 : AN7 is selected. A-D operation mode select bits 4 b4 b3 0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode (Note 2) (Note 3) (Note 4) (Note 5) At reset R/W Reference Undefined RW 13-6 Undefined RW Undefined RW 0 RW 0 RW RW 5 Trigger select bit 0 : Internal trigger 1 : External trigger (Note 6) 0 6 A-D conversion start bit 0 : A-D conversion halts. 1 : A-D conversion starts. 0 7 A-D conversion frequency ( AD) See Table 13.2.1. select bit 0 RW (Note 7) 0 RW Notes 1: These bits are invalid in the single sweep and repeat sweep modes. (They may be either "0" or "1.") 2: When using pin AN4 , be sure that the pin INT3 select bit (bit 5 at address 9416) = "0." 3: When using pin AN5 , be sure that the pin INT4 select bit (bit 6 at address 9416) = "0." 4: When using pin AN6 , be sure that the D-A0 output enable bit (bit 0 at address 9616) = "0" (output disabled). 5: When using pin AN 7, be sure that the pin INT2 select bit (bit 4 at address 9416) = "0" and the D-A1 output enable bit (bit 1 at address 9616) = "0." When using an external trigger, pin AN7 cannot be used as an analog input pin. 6: When using an external trigger, be sure that the pin INT2 select bit (bit 4 at address 9416) = "0" and the D-A1 output enable bit (bit 1 at address 96 16) = "0." 7: When writing to this bit, use the MOVM (MOVMB) or STA (STAB, STAD) instruction. 8: Writing to each bit (except bit 6) of the A-D control register 0 must be performed while the A-D converter halts. 21-10 7902 Group User's Manual APPENDIX Appendix 2. Control registers b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 1 (Address 1F16) Bit 0 Function Bit name At reset R/W Reference 1 RW 13-6 13-7 1 RW 0 RW 0 RW 1 A-D sweep pin select bits (Valid in the single sweep and repeat sweep modes.) (Note 1) 2 Fix this bit to "0." 3 Resolution select bit 4 A-D conversion frequency (AD) select See Table 13.2.1. bit 1 0 RW 5 External trigger polarity select bit 0 : Falling edge of the pin AD TRG's input signal (Valid when external trigger selected.) 1 : Rising edge of the pin AD TRG's input signal 0 RW 6 VREF connection select bit (Note 6) 0 RW 7 The value is "0" at reading. 0 - 0 b1 b0 0 0 : Pins AN0 and AN1 (2 pins) 0 1 : Pins AN0 to AN3 (4 pins) 1 0 : Pins AN0 to AN5 (6 pins) (Notes 2, 3) 1 1 : Pins AN0 to AN7 (8 pins) (Notes 2 to 5) 0 : 8-bit resolution mode 1 : 10-bit resolution mode 0 : Pin VREF is connected. 1 : Pin VREF is disconnected. 13-7 14-4 17-9 Notes 1: These bits are invalid in the one-shot and repeat modes. (They may be either "0" or "1.") 2: When using pin AN4 , be sure that the pin INT3 select bit (bit 5 at address 9416) = "0." 3: When using pin AN5 , be sure that the pin INT4 select bit (bit 6 at address 9416) = "0." 4: When using pin AN6 , be sure that the D-A0 output enable bit (bit 0 at address 9616) = "0" (output disabled). 5: When using pin AN 7, be sure that the pin INT2 select bit (bit 4 at address 9416) = "0" and the D-A 1 output enable bit (bit 1 at address 9616) = "0." When an external trigger is selected, pin AN 7 cannot be used as an analog input pin. 6: When this bit is cleared from "1" to "0," be sure to start the A-D conversion or D-A conversion after an interval of 1 s or more has elapsed. 7: Writing to each bit of the A-D control register 1 must be performed while the A-D conversion halts. 7902 Group User's Manual 21-11 APPENDIX Appendix 2. Control registers When 8-bit resolution mode is selected A-D register 0 (Addresses 2116, 2016) A-D register 1 (Addresses 2316, 2216) A-D register 2 (Addresses 2516, 2416) A-D register 3 (Addresses 2716, 2616) A-D register 4 (Addresses 2916, 2816) A-D register 5 (Addresses 2B16, 2A16) A-D register 6 (Addresses 2D16, 2C16) A-D register 7 (Addresses 2F16, 2E16) (b8) b0 b7 Function Bit 7 to 0 (b15) b7 Reads an A-D conversion result. 15 to 8 The value is "0" at reading. b0 At reset R/W Reference Undefined RO 13-8 0 - When 10-bit resolution mode is selected A-D register 0 (Addresses 2116, A-D register 1 (Addresses 2316, A-D register 2 (Addresses 2516, A-D register 3 (Addresses 2716, A-D register 4 (Addresses 2916, A-D register 5 (Addresses 2B16, A-D register 6 (Addresses 2D16, A-D register 7 (Addresses 2F16, 2016) 2216) 2416) 2616) 2816) 2A16) 2C16) 2E16) Function Bit 9 to 0 (b15) b7 Reads an A-D conversion result. 15 to 10 The value is "0" at reading. 21-12 7902 Group User's Manual (b8) b0 b7 b0 At reset R/W Reference Undefined RO 13-8 0 - APPENDIX Appendix 2. Control registers b7 b6 b5 b4 b3 b2 b1 b0 UART0 transmit/receive mode register (Address 3016) UART1 transmit/receive mode register (Address 3816) Bit 0 Bit name Function Serial I/O mode select bits 1 2 At reset R/W Reference 0 0 0 : Serial I/O is invalid. (P8 functions as programmable I/O port pins.) 0 0 1 : Clock synchronous serial I/O mode 010: 0 1 1 : Do not select. 1 0 0 : UART mode (Transfer data length = 7 bits) 1 0 1 : UART mode (Transfer data length = 8 bits) 1 1 0 : UART mode (Transfer data length = 9 bits) 1 1 1 : Do not select. 0 RW 12-5 0 RW 0 RW b2 b1b0 3 Internal/External clock select bit 0 : Internal clock 1 : External clock 0 RW 4 Stop bit length select bit (Valid in UART mode) (Note) Odd/Even parity select bit (Valid in UART mode when parity enable bit = "1.") (Note) Parity enable bit (Valid in UART mode) (Note) 0 : One stop bit 1 : Two stop bits 0 RW 0 : Odd parity 1 : Even parity 0 RW 0 : Parity disabled 1 : Parity enabled 0 RW Sleep select bit (Valid in UART mode) 0 : Sleep mode terminated (Invalid) 1 : Sleep mode selected 0 RW 5 6 7 (Note) Note: Bits 4 to 6 are invalid in the clock synchronous serial I/O mode. (They may be either "0" or "1.") Additionally, fix bit 7 to "0." b7 UART0 baud rate register (BRG0) (Address 3116) UART1 baud rate register (BRG1) (Address 3916) b0 Bit Function At reset R/W Reference 7 to 0 Can be set to "00 16" to "FF16." Assuming that the set value = n, BRGi divides the count source frequency by (n + 1). Undefined WO 12-14 Note: Writing to this register must be performed while the transmission/reception halts. Use the MOVM (MOVMB) or STA (STAB, STAD) instruction for writing to this register. (b15) b7 UART0 transmit buffer register (Addresses 3316, 3216) UART1 transmit buffer register (Addresses 3B16, 3A16) Bit (b8) b0 b7 At reset R/W Reference Transmit data is set. Undefined WO 12-11 15 to 9 Nothing is assigned. Undefined - 8 to 0 Function b0 Note: Use the MOVM (MOVMB) or STA (STAB, STAD) instruction for writing to this register. 7902 Group User's Manual 21-13 APPENDIX Appendix 2. Control registers b7 b6 b5 b4 b3 b2 b1 b0 UART0 transmit/receive control register 0 (Address 3416) UART1 transmit/receive control register 0 (Address 3C16) Bit 0 Function Bit name BRG count source select bits 1 At reset R/W Reference 0 0 : Clock f2 0 1 : Clock f16 1 0 : Clock f64 1 1 : Clock f512 0 RW 12-7 0 RW b1 b0 2 CTS/RTS function select bit (Note 1) 0 : The CTS function is selected. 1 : The RTS function is selected. 0 RW 3 Transmit register empty flag 0 : Data is present in the transmit register. (Transmission is in progress.) 1 : No data is present in the transmit register. (Transmission is completed.) 1 RO 4 CTS/RTS enable bit 0 : The CTS/RTS function is enabled. 1 : The CTS/RTS function is disabled. 0 RW 5 UARTi receive interrupt mode 0 : Reception interrupt 1 : Reception error interrupt select bit CLK polarity select bit 0 : At the falling edge of the transfer clock, transmit data is output; at the rising edge of the transfer (This bit is used in the clock clock, receive data is input. synchronous serial I/O mode.) When not in transferring, pin CLKi's level is "H." (Note 2) 1 : At the falling edge of the transfer clock, transmit data is output; at the falling edge of the transfer clock, receive data is input. When not in transferring, pin CLKi's level is "L." 0 RW 0 RW 0 : LSB (Least Significant Bit) first Transfer format select bit (This bit is used in the clock 1 : MSB (Most Significant Bit) first synchronous serial I/O mode.) (Note 2) 0 RW 6 7 Notes 1: Valid when the CTS/RTS enable bit (bit 4) is "0" and CTSi/RTS i separate select bit (bit 0 or 1 at address AC16) is "0." 2: Fix these bits to "0" in the UART mode or when serial I/O is disabled. b7 b6 b5 b4 b3 b2 b1 b0 UART0 transmit/receive control register 1 (Address 3516 ) UART1 transmit/receive control register 1 (Address 3D16) Bit Bit name Function R/W Reference 12-9 0 Transmit enable bit 0 : Transmission disabled 1 : Transmission enabled 0 RW 1 Transmit buffer empty flag 0 : Data is present in the transmit buffer register 1 : No data is present in the transmit buffer register 1 RO 2 Receive enable bit 0 : Reception disabled 1 : Reception enabled 0 RW 3 Receive complete flag 0 : No data is present in the receive buffer register 1 : Data is present in the receive buffer register 0 RO 4 Overrun error flag 0 : No overrun error 1 : Overrun error detected 0 RO 5 Framing error flag (Valid in UART mode) (Note) 0 : No framing error 1 : Framing error detected 0 RO 6 Parity error flag (Valid in UART mode) (Note) 0 : No parity error 1 : Parity error detected 0 RO 7 Error sum flag (Valid in UART mode) (Note) 0 : No error 1 : Error detected 0 RO Note: Bits 5 to 7 are invalid in the clock synchronous serial I/O mode. 21-14 At reset 7902 Group User's Manual APPENDIX Appendix 2. Control registers UART0 transmit buffer register (Addresses 3716, 3616) UART1 transmit buffer register (Addresses 3F16, 3E16) Bit 8 to 0 (b8) b0 b7 (b15) b7 Function Receive data is read out from here. 15 to 9 The value is "0" at reading. b0 At reset R/W Reference Undefined RO 12-13 0 - b7 b6 b5 b4 b3 b2 b1 b0 Count start register (Address 4016) Bit Function Bit name 0 : Stop counting 1 : Start counting At reset R/W Reference 0 RW 9-6 0 RW 0 Timer A0 count start bit 1 Timer A1 count start bit 2 Timer A2 count start bit 0 RW 3 Timer A3 count start bit 0 RW 4 Timer A4 count start bit 0 RW 5 Timer B0 count start bit 0 RW 6 Timer B1 count start bit 0 RW 7 Timer B2 count start bit 0 RW 10-4 b7 b6 b5 b4 b3 b2 b1 b0 One-shot start register (Address 4216 ) Bit 0 Bit name 0 Timer A0 one-shot start bit 1 Timer A1 one-shot start bit Function 1 : Start outputting one-shot pulse. (Valid when an internal trigger is selected.) The value is "0" at reading. At reset R/W Reference 0 WO 9-30 0 WO 0 WO 2 Timer A2 one-shot start bit 3 Timer A3 one-shot start bit 0 WO 4 Timer A4 one-shot start bit 0 WO Undefined - 0 RW 6, 5 7 Nothing is assigned. Fix this bit to "0." b7 b6 b5 b4 b3 b2 b1 b0 Up-down register (Address 4416) Bit At reset R/W Reference 0 RW 9-22 0 RW 0 RW 0 RW 0 RW 0 : Two-phase pulse signal processing function disabled 1 : Two-phase pulse signal processing function enabled 0 WO (Note) When not using the two-phase pulse signal processing function, clear the bit to "0." Timer A4 two-phase pulse signal The value is "0" at reading. processing select bit 0 WO (Note) 0 WO (Note) 0 Timer A0 up-down bit 1 Timer A1 up-down bit 2 Timer A2 up-down bit 3 Timer A3 up-down bit 4 Timer A4 up-down bit 5 Timer A2 two-phase pulse signal processing select bit Timer A3 two-phase pulse signal processing select bit 6 7 Function Bit name 0 : Countdown 1 : Countup This function is valid when the contents of the updown register is selected as the up-down switching factor. 9-23 Note: Use the MOVM(MOVMB) or STA(STAB, STAD) instruction for writing to bits 5 to 7. 7902 Group User's Manual 21-15 APPENDIX Appendix 2. Control registers b7 b6 b5 b4 b3 b2 b1 b0 Timer A clock division select register (Address 4516) Bit 0 Bit name Function Timer A clock division select bits See Table 9.2.3. 1 7 to 2 The value is "0" at reading. Timer A0 register (Addresses 4716 , 4616) Timer A1 register (Addresses 4916 , 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16 ) (b15) b7 Bit At reset R/W Reference 0 RW 9-5 0 RW 0 - (b8) b0 b7 Function 15 to 0 These bits have different functions according to the operating mode. b0 At reset R/W Reference Undefined RW 9-4 Note: Reading from or writing to this register must be performed in a unit of 16 bits. b7 b6 b5 b4 b3 b2 b1 b0 Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A 16) Bit At reset R/W Reference 0 RW 9-6 0 RW 0 RW 3 0 RW 4 0 RW 5 0 RW 6 0 RW 7 0 RW 0 1 2 21-16 Bit name Operating mode select bits Function b1 b0 0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot pulse mode 1 1 : Pulse width modulation (PWM) mode. These bits have different functions according to the operating mode. 7902 Group User's Manual APPENDIX Appendix 2. Control registers Timer mode Timer A0 register (Addresses 4716 , 4616) Timer A1 register (Addresses 4916 , 4816) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16 ) (b15) b7 Bit (b8) b0 b7 b0 Function At reset R/W Reference Undefined 15 to 0 These bits to can be set to "000016" to "FFFF16." Assuming that the set value = n, the counter divides the count source frequency by (n + 1). When reading, the register indicates the counter value. RW 9-10 Note: Reading from or writing to this register must be performed in a unit of 16 bits. b7 b6 b5 b4 b3 b2 b1 b0 Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A 16) Bit 0 Bit name Operating mode select bits 0 Function b1 b0 0 0 : Timer mode 1 0 0 At reset R/W Reference 0 RW 9-10 0 RW 2 Pulse output function select bit 0 : No pulse output (TAiOUT pin functions as a programmable I/O port pin.) 1 : Pulse output (TAi OUT pin functions as a pulse output pin.) (Note) 0 RW 9-14 3 Gate function select bits b4 b3 0 RW 9-13 0 RW 0 RW 0 RW 0 RW 00: 01: 10: 4 11: 5 Fix this bit to "0" in timer mode. 6 Count source select bits No gate function (TAiIN pin functions as a programmable I/O port pin.) Gate function (Counter counts only while TAiIN pin's input signal is at "L" level.) Gate function (Counter counts only while TAiIN pin's input signal is at "H" level.) See Table 9.2.3. 7 9-5 Note: In order to make the TA2OUT and TA3 OUT pins serve as pulse output pins, be sure not to select the key input interrupt pins (KI0 and KI2 pins), which are multiplexed with the above pins. (Refer to "CHAPTER 8. KEY INPUT INTERRUPT.") 7902 Group User's Manual 21-17 APPENDIX Appendix 2. Control registers Event counter mode Timer A0 register (Addresses 4716, 46 16) Timer A1 register (Addresses 4916, 48 16) Timer A2 register (Addresses 4B16 , 4A16) Timer A3 register (Addresses 4D16 , 4C16 ) Timer A4 register (Addresses 4F16, 4E16) (b15) b7 (b8) b0 b7 Function Bit b0 At reset R/W Reference Undefined 15 to 0 These bits to can be set to "000016" to "FFFF16." Assuming that the set value = n, the counter divides the count source frequency by (n + 1) during countdown, or by (FFFF16 - n + 1) during countup. When reading, the register indicates the counter value. RW 9-18 Note: Reading from or writing to this register must be performed in a unit of 16 bits. b7 b6 b5 b4 b3 b2 b1 b0 Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A 16) Bit Bit name X X 0 Function 0 1 At reset R/W Reference 0 RW 9-18 0 RW 0 RW 9-23 9-18 Operating mode select bits b1 b0 2 Pulse output function select bit 0 : No pulse output (TAi OUT pin functions as a programmable I/O port pin.) 1 : Pulse output (TAiOUT pin functions as a pulse output pin.) (Note) 3 Count polarity select bit 0 : Counts at falling edge of external signal 1 : Counts at rising edge of external signal 0 RW 4 Up-down switching factor select bit 0 : Contents of up-down register 1 : Input signal to TAiOUT pin 0 RW 5 Fix this bit to "0" in event counter mode. 0 RW 6 These bits are invalid in event counter mode. 0 RW 0 RW 0 0 1 : Event counter mode 1 7 X : It may be either "0" or "1." Note: In order to make the TA2OUT and TA3 OUT pins serve as pulse output pins, be sure not to select the key input interrupt pins (KI0 and KI2 pins), which are multiplexed with the above pins. (Refer to "CHAPTER 8. KEY INPUT INTERRUPT.") 21-18 7902 Group User's Manual 9-22 APPENDIX Appendix 2. Control registers One-shot pulse mode Timer A0 register (Addresses 4716, 46 16) Timer A1 register (Addresses 4916, 48 16) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16 , 4C16 ) Timer A4 register (Addresses 4F16, 4E16) (b15) b7 Bit (b8) b0 b7 b0 Function At reset R/W Reference Undefined 15 to 0 These bits can be set to "0000 16" to "FFFF16." Assuming that the set value = n, the "H" level width of the one-shot pulse which is output from the TAi OUT pin is expressed as follows : n fi. WO 9-27 fi: Frequency of count source Note: Use the MOVM or STA(STAD) instruction for writing to this register. Writing to this register must be performed in a unit of 16 bits. b7 b6 b5 b4 b3 b2 b1 b0 Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A 16) Bit 0 Function Bit name Operating mode select bits 0 b1 b0 1 0 : One-shot pulse mode 1 2 3 Fix this bit to "1" in one-shot pulse mode. Trigger select bits 4 b4 b3 00: 01: Writing "1" to one-shot start bit (TAiIN pin functions as a programmable I/O port pin.) 1 0 : Falling edge of TAiIN pin's input signal 1 1 : Rising edge of TAiIN pin's input signal 5 Fix this bit to "0" in one-shot pulse mode. 6 Count source select bits See Table 9.2.3. 7 7902 Group User's Manual 1 1 0 At reset R/W Reference 0 RW 9-27 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 9-30 9-5 21-19 APPENDIX Appendix 2. Control registers Pulse width modulator (PWM) mode <When operating as a 16-bit pulse width modulator> Timer A0 register (Addresses 4716, 46 16) Timer A1 register (Addresses 4916, 48 16) Timer A2 register (Addresses 4B16, 4A16) Timer A3 register (Addresses 4D16, 4C16) Timer A4 register (Addresses 4F16, 4E16) (b8) b0 b7 (b15) b7 Bit Function b0 At reset R/W Reference 15 to 0 These bits can be set to "0000 16" to "FFFE16." Undefined Assuming that the set value = n, the "H" level width of the PWM pulse which is output n from the TAiOUT pin is expressed as follows : fi (PWM pulse period = 216-1 ) fi WO 9-35 fi: Frequency of count source Note: Use the MOVM or STA(STAD) instruction for writing to this register. Writing to this register must be performed in a unit of 16 bits. <When operating as an 8-bit pulse width modulator> Timer A0 register (Addresses 4716 , 4616) Timer A1 register (Addresses 4916 , 4816) Timer A2 register (Addresses 4B 16, 4A16 ) Timer A3 register (Addresses 4D 16, 4C16) Timer A4 register (Addresses 4F16 , 4E16 ) (b8) b0 b7 (b15) b7 Bit At reset R/W Reference Undefined These bits can be set to "0016" to "FF16." Assuming that the set value = m, the period of the PWM pulse which is output from the TAiOUT pin is expressed as follows: (m + 1) (28 - 1) fi WO 9-35 15 to 8 These bits can be set to "0016" to "FF16." Undefined Assuming that the set value = n, the "H" level width of the PWM pulse which is output from the TAiOUT pin is expressed as follows: n(m + 1) fi WO 7 to 0 Function b0 fi: Frequency of count source Note: Use the MOVM or STA(STAD) instruction for writing to this register. Writing to this register must be performed in a unit of 16 bits. b7 b6 b5 b4 b3 b2 b1 b0 Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16 ) Bit 0 Function Bit name Operating mode select bits 1 1 1 At reset R/W Reference 0 RW 9-35 0 RW 0 RW Writing "1" to count start bit (TAiIN pin functions as a programmable I/O port pin.) 1 0 : Falling edge of TAiIN pin's input signal 1 1 : Rising edge of TAiIN pin's input signal 0 RW 0 RW b1 b0 1 1 : PWM mode 1 2 3 Fix this bit to "1" in PWM mode. Trigger select bits 4 b4 b3 00: 01: 5 16/8-bit PWM mode select bit 0 : 16-bit pulse width modulator 1 : 8-bit pulse width modulator 0 RW 9-39 6 Count source select bits See Table 9.2.3. 0 RW 9-5 0 RW 7 21-20 9-38 7902 Group User's Manual APPENDIX Appendix 2. Control registers (b15) b7 Timer B0 register (Addresses 5116, 50 16) Timer B1 register (Addresses 5316, 52 16) Timer B2 register (Addresses 5516, 54 16) (b8) b0 b7 Function Bit 15 to 0 These bits have different functions according to the operating mode. b0 At reset R/W Reference Undefined RW 10-3 Note: Reading from or writing to this register must be performed in a unit of 16 bits. b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16 ) Bit 0 Bit name Operating mode select bits 1 2 Function b1 b0 0 0 : Timer mode 0 1 : Event counter mode 1 0 : Pulse period/Pulse width measurement mode 1 1 : Do not select. These bits have different functions according to the operating mode. 3 At reset R/W Reference 0 RW 10-4 0 RW 0 RW 0 RW 4 Nothing is assigned. Undefined -- 5 These bits have different functions according to the operating mode. Undefined RO (Note) 6 0 RW 7 0 RW Note: Bit 5 is invalid in the timer and event counter modes; its value is undefined at reading. 7902 Group User's Manual 21-21 APPENDIX Appendix 2. Control registers Timer mode (b15) b7 Timer B0 register (Addresses 5116, 50 16) Timer B1 register (Addresses 5316, 52 16) Timer B2 register (Addresses 5516, 54 16) (b8) b0 b7 b0 Function Bit At reset R/W Reference 15 to 0 These bits can be set to "000016" to "FFFF16." Undefined Assuming that the set value = n, the counter divides the count source frequency by (n + 1). When reading, the register indicates the counter value. RW 10-8 Note: Reading from or writing to this register must be performed in a unit of 16 bits. b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16 ) Bit 0 Function Bit name Operating mode select bits b1 b0 0 0 : Timer mode 1 2 These bits are invalid in timer mode. 3 X X 0 0 At reset R/W Reference 0 RW 10-8 0 RW 0 RW 0 RW 4 Nothing is assigned. Undefined -- 5 This bit is invalid in timer mode; its value is undefined at reading. Undefined RO 6 Count source select bits 0 RW 0 RW 7 b7 b6 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 X : It may be either "0" or "1." 21-22 X 7902 Group User's Manual 10-6 APPENDIX Appendix 2. Control registers Event counter mode Timer B0 register (Addresses 5116, 50 16) Timer B1 register (Addresses 5316, 52 16) Timer B2 register (Addresses 5516, 54 16) (b15) b7 Bit (b8) b0 b7 Function b0 At reset R/W Reference 15 to 0 These bits can be set to "000016" to "FFFF16." Undefined Assuming that the set value = n, the counter divides the count source frequency by (n + 1). When reading, the register indicates the counter value. RW 10-13 Note: Reading from or writing to this register must be performed in a unit of 16 bits. b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D 16) Bit 0 Bit name X X X Function Operating mode select bits b1 b0 Count polarity select bits b3 b2 0 1 : Event counter mode 1 2 3 0 0 : Count at falling edge of external signal 0 1 : Count at rising edge of external signal 1 0 : Count at both falling and rising edges of external signal 1 1 : Do not select. (Note) 4 Nothing is assigned. 5 This bit is invalid in event counter mode; its value is undefined at reading. 6 These bits are invalid in event counter mode. 7 0 1 At reset R/W Reference 0 RW 10-13 0 RW 0 RW 0 RW Undefined -- Undefined RO 0 RW 0 RW X : It may be either "0" or "1." Note: When the timer B2 clock source select bit (bit 6 at address 63 16) = "1," be sure to fix these bits to "012 " (count at the rising edge of the external signal). 7902 Group User's Manual 21-23 APPENDIX Appendix 2. Control registers Pulse period/Pulse width measurement mode Timer B0 register (Addresses 5116, 5016 ) Timer B1 register (Addresses 5316, 5216 ) Timer B2 register (Addresses 5516, 5416 ) (b8) b0 b7 (b15) b7 Bit Function 15 to 0 The measurement result of pulse period or pulse width is read out. b0 At reset R/W Reference Undefined RO 10-19 Note: Reading from this register must be performed in a unit of 16 bits. b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D 16) Bit 0 Function At reset R/W Reference 1 0 : Pulse period/Pulse width measurement mode 0 RW 10-19 0 RW 0 RW 0 RW Undefined -- Undefined RO 10-21 0 RW 10-6 0 RW Bit name Operating mode select bits b1 b0 Measurement mode select bits b3 b2 1 2 3 4 Nothing is assigned. 5 Timer Bi overflow flag 6 Count source select bits 7 1 0 0 0 : Pulse period measurement (Interval between falling edges of measurement pulse) 0 1 : Pulse period measurement (Interval between rising edges of measurement pulse) 1 0 : Pulse width measurement (Interval from a falling edge to a rising edge, and from a rising edge to a falling edge of measurement pulse) 1 1 : Do not select. 0 : No overflow (Note) 1 : Overflowed b7 b6 0 0 : f2 0 1 : f16 1 0 : f64 1 1 : f512 Note: The timer Bi overflow flag is cleared to "0" when a value is written to the timer Bi mode register with the count start bit = "1." This flag cannot be set to "1" by software. 21-24 7902 Group User's Manual 10-21 APPENDIX Appendix 2. Control registers b7 b6 b5 b4 b3 b2 b1 b0 Processor mode register 0 (Address 5E16) Bit Bit name 0 Processor mode bits At reset R/W Reference 0 RW 2-25 (Note 1) RW 0 RW 1 RW Interrupt priority detection time b5 b4 0 0 : 7 cycles of fsys select bits 0 1 : 4 cycles of fsys 1 0 : 2 cycles of fsys 1 1 : Do not select. 0 RW 0 RW 6 Software reset bit The microcomputer is reset by writing "1" to this bit. The value is "0" at reading. 0 WO 4-3 7 Clock 1 output select bit 0 : 1 output is disabled. (P41 functions as a (Note 3) programmable I/O port pin.) 1 : 1 output is enabled. (P41 functions as a clock 1 output pin.) RW 3-5 1 2 External bus cycle select bit 0 (Note 2) 3 4 5 Function b1 b0 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode 1 1 : Do not select. (External bus cycle select (External bus cycle select bit 1 = 0) bit 1 = 1) b3 b2 b3 b2 0 0 : 1 + 1 0 1 : 1 + 2 1 0 : 1 + 3 1 1 : 2 + 2 0 0 : 2 + 3 0 1 : 2 + 4 1 0 : 3 + 3 1 1 : 3 + 4 3-8 7-13 Notes 1: When the Vss-level voltage is applied to pin MD0, this bit is "0"; when the Vcc-level voltage is applied to pin MD0, this bit is "1." (Fixed to "1.") 2: These bits are valid for the external area except for area CSi. Regardless of these bits' contents, the bus cycle of area CSi is decided by the corresponding area CS i bus cycle select bits 0, 1 (bits 0, 1 at addresses 8016, 82 16, 84 16, 8616 , and bit 3 at addresses 8116 , 8316 , 8516, 8716). 3: When the Vss-level voltage is applied to pin MD0, this bit is "0"; when the Vcc-level voltage is applied to pin MD0, this bit is "1." 7902 Group User's Manual 21-25 APPENDIX Appendix 2. Control registers b7 b6 b5 b4 b3 b2 b1 b0 Processor mode register 1 (Address 5F16) Bit name Function At reset R/W Reference 0 External bus cycle select bit 1 (Note 1) The combination of this bit and the external bus cycle select bit 0 selects the bus cycle. 0 : 1 + 1, 1 + 2, 1 + 3, or 2 + 2 1 : 2 + 3, 2 + 4, 3 + 3, or 3 + 4 0 RW 3-9 1 Direct page register switch bit 0 : Only DPR0 is used. 1 : DPR0 through DPR3 are used. 0 RW (Note 2) 2-6 2 RDY input select bit (Note 3) 0 : RDY input is disabled. (Note 4) RW (P30 functions as a programmable I/O port pin.) (Note 5) 1 : RDY input is enabled. (P3 0 functions as pin RDY.) 3-5 3-9 3 ALE output select bit (Note 3) 0 : ALE output is disabled. (Note 4) (P40 functions as a programmable I/O port pin.) 1 : ALE output is enabled. (P40 functions as pin ALE.) 3-5 4 Recovery cycle insert select bit 0 : No recovery cycle is inserted at access to external area. (Note 4) RW 1 : Recovery cycle is inserted at access to external area. (Note 3) (Note 4) RW HOLD input, HLDA output select 0 : HOLD input and HLDA output are disabled. (Note 5) (P43 and P42 function as programmable I/O port pins.) bit (Note 3) 1 : HOLD input and HLDA output are enabled. (P43 and P42 function as pins HOLD and HLDA.) Bit 5 6 7 Recovery-cycle-insert number select bit (Note 6) Internal ROM bus cycle select bit (Note 7) RW 3-5 0 : 1 cycle 1 : 2 cycles 0 RW 3-9 0 : 3 1 : 2 0 RW 2-14 Notes 1: This bit is valid for the external area except for area CSi. Regardless of these bits' contents, the bus cycle of area CS i is decided by the corresponding area CSi bus cycle select bits 0, 1 (bits 0, 1 at addresses 8016, 82 16, 8416 , 8616, and bit 3 at addresses 8116 , 8316 , 8516 , 8716 ). 2: After reset, this bit can be set only once. (During the software execution, be sure not to change this bit's contents.) 3: In the single-chip mode, all of these bits' functions are disabled regardless of these bits' contents. 4: When the Vss-level voltage is applied to pin MD0, this bit is "0"; when the Vcc-level voltage is applied to pin MD0, this bit is "1." 5: After reset, this bit can be set to "0" only once. Once this bit has been cleared from "1" to "0," it cannot be back to "1" again. (Fixed to "0.") 6: Make sure that a program to be used to change this bit's contents is allocated in the internal area. 7: In the microprocessor mode, this bit is invalid. This bit is not assigned to the external ROM version. ("0" at reading.) To reprogram the internal flash memory by using the CPU reprogramming mode, clear this bit to "0." (Refer to section "20.2 Flash memory CPU reprogramming mode.") 21-26 3-9 7902 Group User's Manual APPENDIX Appendix 2. Control registers b7 b0 Watchdog timer register (Address 6016) Bit 7 to 0 Function At reset Initializes the watchdog timer. Undefined When dummy data has been written to this register, the watchdog timer's value is initialized to "FFF16" (dummy data: 0016 to FF16). R/W Reference -- 15-3 b7 b6 b5 b4 b3 b2 b1 b0 Watchdog timer frequency select register (Address 6116) Bit 0 5 to 1 6 7 Bit name Watchdog timer frequency select bit Nothing is assigned. Function 0 : Wf512 1 : Wf32 Watchdog timer clock source b7 b6 0 0 : fX32 select bits at STP termination 0 1 : fX16 1 0 : fX128 1 1 : fX64 7902 Group User's Manual At reset R/W Reference 0 RW 15-3 16-7 Undefined -- 0 RW 0 RW 21-27 APPENDIX Appendix 2. Control registers b7 b6 b5 b4 b3 b2 b1 b0 Particular function select register 0 (Address 6216) Bit Bit name 0 0 0 0 0 0 Function 0 STP instruction invalidity select bit 0 : STP instruction is valid. 1 : STP instruction is invalid. 1 External clcok input select bit 0 : Oscillation circuit is active. (Oscillator is connected.) Watchdog timer is used at stop mode termination. 1 : Oscillation circuit is inactive. (External clock is input.) At reset R/W Reference 0 RW (Note) RW (Note) 16-4 0 5-10 16-5 17-4 When the system clock select bit (bit 5 at address BC16) = "0," watchdog timer is not used at stop mode termination. When the system clock select bit = "1," watchdog timer is used at stop mode termination. 7 to 2 Fix this bit to "0." 0 RW Note: Writing to these bits requires the following procedure: * Write "5516" to this register. (The bit status does not change only by this writing.) * Succeedingly, write "0" or "1" to each bit. Also, use the MOVMB (MOVM when m = 1) instruction or STAB (STA when m = 1) instruction. If an interrupt occurs between writing of "5516" and next writing of "0" or "1," latter writing may be ignored. When there is a possibility that an interrupt occurs at the above timing, be sure to read this bit's contents after writing of "0" or "1," and verify whether "0" or "1" has correctly been written or not. b7 b6 b5 b4 b3 b2 b1 b0 Particular function select register 1 (Address 6316) Bit Bit name Function At reset R/W Reference 16-6 0 STP-instruction-execution status bit 0 : Normal operation. 1 : STP instruction has been executed. (Note 1) RW (Note 2) 1 WIT-instruction-execution status bit Standby state select bit 0 : Normal operation. 1 : WIT instruction has been executed. (Note 1) RW (Note 2) 0 : External bus 1 : Programmable I/O port 0 RW 0 : In the wait mode, system clock fsys is active. 1 : In the wait mode, system clock fsys is stopped. 0 RW 4 System clock stop select bit at WIT (Note 3) Address output select bit 0 : Address output changes at access to the internal area and external area. 1 : Address output changes only at access to the external area. 0 RW 5 The value is "0" at reading. 0 -- 6 Timer B2 clock source select bit 0 : External signal input to the TB2IN pin is counted. (Valid in event counter mode.) 1 : fX32 is counted. 0 RW 7 The value is "0" at reading. 0 -- 2 3 Notes 1: At power-on reset, this bit becomes "0." At hardware reset or software reset, this bit retains the value just before reset. 2: Even when "1" is written, the bit status will not change. 3: Setting this bit to "1" must be performed just before execution of the WIT instruction. Also, after the wait state is terminated, this bit must be cleared to "0" immediately. 21-28 7902 Group User's Manual 17-5 3-31 10-14 APPENDIX Appendix 2. Control registers Particular function select register 2 (Address 6416) Bit 7 to 0 Function b7 b0 At reset Disables the watchdog timer. Undefined When values of "7916" and "5016" succeedingly in this order, the watchdog timer will stop its operation. R/W Reference -- 15-4 Note: After reset, this register can be set only once. Writing to this register requires the following procedure: * Write values of "79 16" and "5016 " to this register succeedingly in this order. * For the above writing, be sure to use the MOVMB (MOVM when m = 1) instruction or the STAB (STA when m = 1). Note that the following: if an interrupt occurs between writing of "79 16" and next writing of "5016," the watchdog timer does not stop its operation. If any of the following has been performed after reset, writing to this register is disabled from that time: * If this register is read out. * If writing to this register is performed by the procedure other than the above procedure. 7902 Group User's Manual 21-29 APPENDIX Appendix 2. Control registers b7 b6 b5 b4 b3 b2 b1 b0 Debug control register 0 (Address 6616) Bit 0 Bit name Detect condition select bits 1 2 3 0 Function b2 b1 b0 0 0 0 : Do not select. 0 0 1 : Address matching detection 0 0 1 0 : Address matching detection 1 0 1 1 : Address matching detection 2 1 0 0 : Do not select. 1 0 1 : Out-of-address-area detection 110: Do not select. 111: Fix these bits to "0." 4 5 Detect enable bit 6 Fix this bit to "0." 7 The value is "1" at reading. 0 : Detection disabled. 1 : Detection enabled. 0 0 At reset R/W Reference (Note) RW 18-3 (Note) RW (Note) RW (Note) RW (Note) RW (Note) RW (Note) RW 1 -- Note: At power-on reset, these bits become "0"; at hardware reset or software reset, these bits retain the value immediately before reset. b7 b6 b5 b4 b3 b2 b1 b0 Debug control register 1 (Address 6716) Bit 0 1 Bit name Function 0 At reset R/W Reference 18-4 0 Fix this bit to "0." (Note 1) RW 1 The value is "0" at reading. (Note 1) RO 2 Address compare register access enable bit (Note 2) 0 RW 3 Fix this bit to "1" when using the debug function. 0 RW 4 Fix this bit to "0." (Note 1) RW 5 While a debugger is not used, the value is "0" at reading. While a debugger is used, the value is "1" at reading. 0 RO 6 Address-matching-detection 2 decision bit (Valid when the address matching detection 2 is selected.) 0 RO 7 The value is "0" at reading. 0 -- 0 : Disabled. 1 : Enabled. 0 : Matches with the contents of the address compare register 0. 1 : Matches with the contents of the address compare register 1. Notes 1: At power-on reset, these bits become "0"; at hardware reset or software reset, these bits retain the value immediately before reset. 2: Be sure to set this bit to "1" immediately before the access to the address compare registers 0 and 1 (addresses 68 16 to 6D16). Then, be sure to clear this bit to "0" immediately after this access. Address compare register 0 (Addresses 6A16 to 6816) Address compare register 1 (Addresses 6D16 to 6B16) Bit 23 to 0 Function (b23) (b16) (b15) (b8) b7 b0 b7 b0 b7 b0 At reset R/W Reference The address to be detected (in other words, the start address of instructions) is set here. Undefined RW 18-5 Note: When accessing to these registers, be sure to set the address compare register access enable bit (bit 2 at address 6716) to "1" immediately before the access. Then, be sure to clear this bit to "0" immediately after this access. 21-30 7902 Group User's Manual APPENDIX Appendix 2. Control registers b7 b6 b5 b4 b3 b2 b1 b0 INT3, INT4 interrupt control registers (Addresses 6E16, 6F16) Bit 0 Bit name Interrupt priority level select bits 1 2 3 Interrupt request bit 4 Polarity select bit 7 to 5 Function b2 b1 b0 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0 : No interrupt requested 1 : Interrupt requested 0 : The interrupt request bit is set to "1" at the falling edge. 1 : The interrupt request bit is set to "1" at the rising edge. Nothing is assigned. At reset R/W Reference 0 RW 7-8 7-9 0 RW INT 3 8-5 0 RW 0 RW (Note) 0 RW Undefined -- 7-19 Note: When writing to this bit, use the MOVM (MOVMB) or STA (STAB, STAD) instruction. A-D conversion, UART0 and 1 transmit, UART0 and 1 receive, timers A0 to A4, timers B0 to B2 interrupt control registers (Addresses 7016 to 7C 16) Bit 0 Bit name Interrupt priority level select bits 1 2 3 Interrupt request bit 7 to 4 Nothing is assigned. Function b2 b1b0 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0 : No interrupt requested 1 : Interrupt requested b7 b6 b5 b4 b3 b2 b1 b0 At reset R/W Reference 0 RW 0 RW 7-8 7-9 Timer Ai 9-7 Timer Bi 0 RW RW 0 (Note 1) (Note 2) Undefined -- 10-5 UART0 UART1 12-16 A-D 13-9 Notes 1: The A-D conversion interrupt request bit is undefined after reset. 2: When writing to this bit, use the MOVM (MOVMB) or STA (STAB, STAD) instruction. 7902 Group User's Manual 21-31 APPENDIX Appendix 2. Control registers b7 b6 b5 b4 b3 b2 b1 b0 INT0 to INT2 interrupt control registers (Addresses 7D16 to 7F16) Bit Bit name 0 Interrupt priority level select bits 1 2 Function b2 b1 b0 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0 : No interrupt requested 1 : Interrupt requested R/W Reference 0 RW 7-8 7-9 0 RW 0 RW 0 RW (Note 2) 3 Interrupt request bit (Note 1) 4 Polarity select bit 0 : The interrupt request bit is set to "1" at "H" level when level sense is selected; this bit is set to "1" at falling edge when edge sense is selected. 1 : The interrupt request bit is set to "1" at "L" level when level sense is selected; this bit is set to "1" at rising edge when edge sense is selected. 0 RW 5 Level sense/Edge sense select bit 0 : Edge sense 1 : Level sense 0 RW Undefined -- 7, 6 Nothing is assigned. Notes 1: The interrupt request bits of INT0 to INT2 interrupts are invalid when the level sense is selected. 2: When writing to this bit, use the MOVM (MOVMB) or STA (STAB, STAD) instruction. 21-32 At reset 7902 Group User's Manual 7-19 APPENDIX Appendix 2. Control registers b7 b6 b5 b4 b3 b2 b1 b0 CS0 control register L (Address 8016) Bit Bit name Function At reset R/W Reference 0 Area CS0 bus cycle select bit 0 (Area CS0 bus cycle select (Area CS0 bus cycle select bit 1 = 0) bit 1 = 1) 0 RW 3-12 1 RW (Note 1) RO 0 RW 1 b1 b0 b1 b0 0 0 : 1 + 1 0 1 : 1 + 2 1 0 : 1 + 3 1 1 : 2 + 2 0 0 : 2 + 3 0 1 : 2 + 4 1 0 : 3 + 3 1 1 : 3 + 4 2 External data bus width select bit The input level at pin BYTE is read out. 0 : 16-bit width 1 : 8-bit width 3 RDY control bit 4 The value is "0" at reading. 0 -- 5 Burst ROM access select bit 0 : Normal access (Note 3) 1 : Burst ROM access 0 RW 6 Recovery cycle insert select bit 1 RW 7 CS0 output select bit (Note 2) 0 : RDY control is valid. 1 : RDY control is invalid. 0 : No recovery cycle is inserted at access to area CS0. 1 : Recovery cycle is inserted at access to area CS0. (Note 4) 0 : CS0 output is disabled. (P44 functions as a (Note 5) programmable I/O port pin.) 1 : CS0 output is enabled. (P4 4 functions as pin CS0.) RW 3-5 3-12 Notes 1: This bit is "0" when Vss-level voltage is applied to pin BYTE; this bit is "1" when Vcc-level voltage is applied. 2: This bit is valid when the RDY input select bit (bit 2 at address 5F 16) is "1." 3: When Vcc-level voltage is applied to pin BYTE, "normal access" is selected regardless of this bit's value. 4: This bit's contents are invalid in the single-chip mode. (CS 0 output disabled) 5: This bit is "0" when Vss-level voltage is applied to pin MD0; this bit is "1" when Vcc-level voltage is applied. (Fixed to "1.") b7 b6 b5 b4 b3 b2 b1 b0 CS0 control register H (Address 8116) Bit 0 Bit name At reset R/W Reference 0 0 0 : 0 byte (Area CS0 is invalid.) 0 0 1 : 128 Kbytes 0 1 0 : 256 Kbytes 0 1 1 : 512 Kbytes 1 0 0 : 1 Mbytes 1 0 1 : 2 Mbytes 1 1 0 : 4 Mbytes 1 1 1 : 8 Mbytes 1 RW 3-13 0 RW 0 RW The combination of this bit and the area CS 0 bus cycle select bit 0 selects the bus cycle. 0 : 1 + 1, 1 + 2, 1 + 3, or 2 + 2 1 : 2 + 3, 2 + 4, 3 + 3, or 3 + 4 0 RW The value is "0" at reading. 0 -- Area CS0 setting mode select bit 0: Mode 0 (A block can be set to 16-Mbyte space.) 1: Mode 1 (Area CS0 start address is set in bank 0.) 1 RW Area CS0 block size select bits 1 2 3 6 to 4 7 Area CS0 bus cycle select bit 1 Function b2 b1 b0 7902 Group User's Manual 21-33 APPENDIX Appendix 2. Control registers CS1 control register L (Address 8216 ) CS2 control register L (Address 8416 ) CS3 control register L (Address 8616 ) Bit 0 Bit name Area CSj bus cycle select bit 0 (j = 1 to 3) 1 2 b7 b6 b5 b4 b3 b2 b1 b0 Function At reset R/W Reference (Area CS j bus cycle select (Area CSj bus cycle select bit 1 = 0) bit 1 = 1) 0 RW 3-15 1 RW 0 RW 0 RW 0 -- b1 b0 b1 b0 0 0 : 1 + 1 0 1 : 1 + 2 1 0 : 1 + 3 1 1 : 2 + 2 0 0 : 2 + 3 0 1 : 2 + 4 1 0 : 3 + 3 1 1 : 3 + 4 External data bus width select bit 0 : 16-bit width 1 : 8-bit width (Note 1) 3 RDY control bit 4 The value is "0" at reading. 5 Burst ROM access select bit (Note 3) 0 : Normal access 1 : Burst ROM access 0 RW 6 Recovery cycle insert select bit 0 : No recovery cycle is inserted with area CSj selected. 1 : Recovery cycle is inserted with area CSj selected. 1 RW 7 CSj output select bit (j = 1 to 3) 0 : CSj output is disabled. (P45 to P4 7 function as programmable I/O port pins.) 1 : CSj output is enabled. (P45 to P47 function as pin CSj.) 0 RW (Note 2) (Note 4) 0 : RDY control is valid. 1 : RDY control is invalid. 3-5 3-15 Notes 1: This bit is fixed to "1" (8-bit width) when Vcc-level voltage is applied to pin BYTE. 2: Valid when the RDY input select bit (bit 2 at 5F16) is "1." 3: When the external data bus width select bit (bit 2) is "1" or when Vcc-level voltage is applied to pin BYTE, "normal access" is selected regardless of this bit's value. 4: This bit's value is invalid in the single-chip mode. (CSj output is disabled.) b7 b6 b5 b4 b3 b2 b1 b0 CS1 control register H (Address 8316) Bit 0 Bit name Area CS1 block size select bits 1 2 21-34 0 Function At reset R/W Reference (Mode 1) (Mode 0) 0 0 0 : 0 byte (Area CS1 is invalid.) 0 byte (Area CS1 is invalid.) 0 0 1 : 128 Kbytes Do not select. 0 1 0 : 256 Kbytes Do not select. 0 1 1 : 512 Kbytes Do not select. 1 0 0 : 1 Mbytes 4 Kbytes 1 0 1 : 2 Mbytes 8 Kbytes 1 1 0 : 4 Mbytes Do not select. 1 1 1 : 8 Mbytes Do not select. 0 RW 3-16 0 RW 0 RW The combination of this bit and the area CS 1 bus cycle select bit 0 selects the bus cycle. 0 : 1 + 1, 1 + 2, 1 + 3, or 2 + 2 1 : 2 + 3, 2 + 4, 3 + 3, or 3 + 4 0 RW b2 b1 b0 3 Area CS1 bus cycle select bit 1 4 The value is "0" at reading. 0 -- 5 Fix this bit to "0." 0 RW 6 The value is "0" at reading. 0 -- 7 Area CS1 setting mode select bit 0 RW 0 : Mode 0 (A block can be set to 16-Mbyte space.) 1 : Mode 1 (A block can be set to bank 0.) 7902 Group User's Manual APPENDIX Appendix 2. Control registers b7 b6 b5 b4 b3 b2 b1 b0 CS2 control register H (Address 8516) Bit 0 Bit name Area CS2 block size select bits 1 2 3 Area CS2 bus cycle select bit 1 4 The value is "0" at reading. 5 Multiplexed bus select bit 6 The value is "0" at reading. 7 Area CS2 setting mode select bit Function At reset R/W Reference (Mode 1) (Mode 0) 0 0 0 : 0 byte (Area CS2 is invalid.) 0 byte (Area CS2 is invalid.) 0 0 1 : 128 Kbytes Do not select. 0 1 0 : 256 Kbytes Do not select. 0 1 1 : 512 Kbytes Do not select. 1 0 0 : 1 Mbytes 4 Kbytes 1 0 1 : 2 Mbytes 8 Kbytes 1 1 0 : 4 Mbytes Do not select. 1 1 1 : 8 Mbytes Do not select. 0 RW 3-17 0 RW 0 RW The combination of this bit and the area CS 2 bus cycle select bit 0 selects the bus cycle. 0 : 1 + 1, 1 + 2, 1 + 3, or 2 + 2 1 : 2 + 3, 2 + 4, 3 + 3, or 3 + 4 0 RW 0 -- 0 RW 0 -- 0 RW b2 b1 b0 0 : Separated bus. Input/Output for D 0-D7. 1 : Multiplexed bus. LA0 /D0-LA 7/D7 are input/output when the external data bus = 8 bits (bit 2 at address 8416 = 1) with area CS2 accessed. 0 : Mode 0 (A block can be set to 16-Mbyte space.) 1 : Mode 1 (A block can be set to bank 0.) b7 b6 b5 b4 b3 b2 b1 b0 CS3 control register H (Address 87 16) Bit 0 Bit name Area CS3 block size select bits 1 2 3 Area CS3 bus cycle select bit 1 Function b2 b1 b0 0 0 0 : 0 byte (Area CS3 is invalid.) 0 0 1 : 128 Kbytes 0 1 0 : 256 Kbytes 0 1 1 : 512 Kbytes 1 0 0 : 1 Mbytes 1 0 1 : 2 Mbytes 1 1 0 : 4 Mbytes 1 1 1 : 8 Mbytes The combination of this bit and the area CS 3 bus cycle select bit 0 selects the bus cycle. 0 : 1 + 1, 1 + 2, 1 + 3, or 2 + 2 1 : 2 + 3, 2 + 4, 3 + 3, or 3 + 4 7 to 4 The value is "0" at reading. 7902 Group User's Manual At reset R/W Reference 0 RW 3-18 0 RW 0 RW 0 RW 0 -- 21-35 APPENDIX Appendix 2. Control registers b7 b6 b5 b4 b3 b2 b1 b0 Area CS0 start address register (Address 8A16) Function Bit At reset R/W Reference 0 - 3-18 0 RW 0 RW 0 RW 1 RW 5 0 RW 6 0 RW 7 0 RW 0 1 Mode 0 A16-A23 of the start address are set. 3 Mode 1 A8-A15 of the start address are set. Any value of 1016, 2016, 4016, and 8016 can be set. 4 (Bit 0 is always "0" at reading.) 2 Note: Depending on the block size, which has been selected by the area CS 0 block size select bits 0 to 2 at address 8116 ), the start address which can be set is changed. (See Figures 3.2.10 and 3.2.11.) Area CS1 start address register (Address 8C16) Area CS2 start address register (Address 8E16) Bit At reset R/W Reference Mode 0 A16-A23 of the start address are set. 0 - 3-18 0 RW Mode 1 A8-A15 of the start address are set. 0 RW 0 RW 4 0 RW 5 0 RW 6 0 RW 7 0 RW 0 1 2 Function b7 b6 b5 b4 b3 b2 b1 b0 3 (Bit 0 is always "0" at reading.) Note: Depending on the block size, which has been selected by the area CS 1/CS 2 block size select bits (bits 0 to 2 at address 8316 / 8516 ), the start address which can be set is changed. (See Figures 3.2.10 and 3.2.12.) b7 b6 b5 b4 b3 b2 b1 b0 Area CS3 start address register (Address 9016) Bit Function At reset R/W Reference 3-18 0 A16-A23 of the start address are set. 0 - 1 (Bit 0 is always "0" at reading.) 0 RW 2 0 RW 3 0 RW 4 0 RW 5 0 RW 6 0 RW 7 0 RW Note: Depending on the block size, which has been selected by the area CS3 block size select bits (bits 0 to 2 at address 8716), the start address which can be set is changed. (See Figure 3.2.10.) 21-36 7902 Group User's Manual APPENDIX Appendix 2. Control registers b7 b6 b5 b4 b3 b2 b1 b0 Port function control register (Address 9216) Bit 0 Bit name Address/Port switch bits 1 2 3 Port P0 input level select bit 4 Pins P44-P47 pullup select bit 6, 5 7 0 0 Function At reset R/W Reference 0 0 0 : A0 to A23 (16 Mbytes) 0 0 1 : A0 to A21, P06, P07 (4 Mbytes) 0 1 0 : A0 to A19, P04 to P07 (1 Mbytes) 0 1 1 : A0 to A17, P02 to P07 (256 Kbytes) 1 0 0 : A0 to A15, P00 to P07 (64 Kbytes) 1 0 1 : Do not select. 1 1 0 : A0 to A11, P00 to P07, P114 to P117 (4 Kbytes) 1 1 1 : A0 to A7, P00 to P07, P110 to P117 (256 bytes) 0 : VIH = 0.7 VCC, VIL = 0.2 VCC 1 : VIH = 0.43 VCC (Note 1), VIL = 0.16 VCC 0 RW 3-5 0 RW 0 RW 0 RW 6-7 0 : Pins P44-P47 are pulled up. 1 : Pins P44-P47 are not pulled up (Notes 2, 3). 0 RW 3-5 6-7 0 RW 0 RW b2 b1 b0 Fix these bit s to "0." Pin NMI pullup select bit 0 : Pin NMI is pulled up. 1 : Pin NMI is not pulled up. 7-19 (Note 2) Notes 1: For the M37902FxMHP (power source voltage = 3.3 V0.3 V), VIH = 0.5 VCC. 2: When MD1 = VCC and MD0 = VCC (flash memory parallel I/O mode), pins P44 to P47 and NMI are not pulled up, regardless of these bits' contents. 3: When MD1 = VSS and MD0 = VCC (microprocessor mode), pin CS0 (P44) is not pulled up, regardless of the bits' contents. b7 b6 b5 b4 b3 b2 b1 b0 External interrupt input control register (Address 9416) Bit Bit name 0 Function At reset R/W Reference 8-4 0 Key input interrupt select bit 0 : INT3 interrupt 1 : Key input interrupt 0 RW 1 Key input interrupt pin pullup select bit Key input interrupt pin select bits 0 : Pins KI0 to KI 3 are not pulled up. 1 : Pins KI0 to KI 3 are pulled up. 0 RW b3 b2 0 RW 0 RW 0 RW 2 3 0 0 : Pins KI0 to KI3 0 1 : Pins KI0 to KI2 1 0 : Pins KI0 and KI1 1 1 : Pin KI0 (Note 1) 0 : Allocate pin INT2 to P64. 1 : Allocate pin INT2 to P77. 4 Pin INT2 select bit 5 Pin INT3 select bit 0 : Allocate pin INT3 to P80. 1 : Allocate pin INT3 to P74. (Note 3) 0 RW 6 Pin INT4 select bit 0 : Allocate pin INT4 to P84. 1 : Allocate pin INT4 to P75. (Note 4) 0 RW 7 Fix this bit to "0". 0 RW 7-19 (Note 2) Notes 1: When using pin KIi, do not select timer A's output pins and pulse output pins which are multiplexed with pin KIi. Refer to "CHAPTER 9. TIMER A" and "CHAPTER 11. REAL-TIME OUTPUT." 2: When allocating pin INT2 to P7 7, do not use pin AN7/ADTRG. Additionally, clear the D-A1 output enable bit (bit 1 at address 9616 ) to "0" (output disabled). 3: When allocating pin INT3 to P8 0, clear the D-A2 output enable bit (bit 2 at address 9616) to "0" (output disabled). When allocating pin INT3 to P74 , do not use pin AN 4. 4: When allocating pin INT4 to P75, do not use pin AN5 . 7902 Group User's Manual 21-37 APPENDIX Appendix 2. Control registers b7 b6 b5 b4 b3 b2 b1 b0 External interrupt input read register (Address 9516) Bit Bit name Function R/W Reference Undefined RO 7-19 Undefined RO Undefined RO 0 INT0 read out bit 1 INT1 read out bit 2 INT2 read out bit 3 INT3 read out bit (Note) Undefined RO 4 INT4 read out bit Undefined RO 5 NMI read out bit Undefined RO The value is undefined at reading. Undefined RO 7, 6 The input level at the corresponding pin is read out. 0 : "L" level 1 : "H" level At reset Note : When the key input interrupt select bit (bit 0 at address 9416) = "1," the input level at pin INT3 cannot be read out. b7 b6 b5 b4 b3 b2 b1 b0 D-A control register (Address 9616) Bit Bit name Function At reset R/W Reference 14-3 0 D-A 0 output enable bit 0: Output is disabled. 1: Output is enabled. (Notes 1, 2) 0 RW 1 D-A 1 output enable bit 0: Output is disabled. 1: Output is enabled. (Notes 1, 2) 0 RW 2 D-A 2 output enable bit 0: Output is disabled. 1: Output is enabled. (Notes 1, 2) 0 RW Undefined -- 7 to 3 Nothing is assigned. Notes 1: Pin DAi is multiplexed with analog input pin, serial I/O pin, and external interrupt input pin. When a D-Ai output enable bit = "1" (in other words, output is enabled.), however, the corresponding pin cannot function as any other multiplexed input/ output pin (including programmable I/O port pin). 2: When not using the D-A converter, be sure to clear the contents of this bit to "0." b7 b0 D-A register i (i = 0 to 2) (Addresses 98 16 to 9A16 ) Bit Function At reset R/W Reference 7 to 0 Any value from 00 16 through FF 16 can be set (Note), and this value is D-A converted and is output. 0 RW 14-3 Note: When not using the D-A converter, be sure to clear the contents of these bits to "0016." 21-38 7902 Group User's Manual APPENDIX Appendix 2. Control registers b7 b6 b5 b4 b3 b2 b1 b0 Flash memory control register (Address 9E16) Bit Bit name 0 Function At reset R/W Reference RO 20-14 20-15 0 RY/BY status bit 0 : BUSY (Automatic programming or erase operation is active.) 1 : READY (Automatic programming or erase operation has been completed.) 1 1 CPU reprogramming mode select bit 0 : Flash memory CPU reprogramming mode is invalid. 1 : Flash memory CPU reprogramming mode is valid. 0 2 Lock bit invalidity select bit RW (Notes 1, 2) 0 : Lock bit is valid. 1 : Lock bit is invalid (Note 3). 0 RW Writing "1" followed with "0" into this bit discontinues the access to the internal flash memory. This causes the built-in flash memory circuit being reset. 0 RW (Note 6) (Notes 1, 4) 3 Flash memory reset bit (Note 5) 4 Fix this bit to "0." 0 RW 5 User ROM area select bit 0 : Access to boot ROM area (Valid in boot mode) (Note 7) 1 : Access to user ROM area 0 RW (Note 2) The value is "0" at reading. 0 -- 7, 6 Notes 1: In order to set this bit to "1," write "0" followed with "1" successively; while in order to clear this bit "0," write "0." 2: Writing to this bit must be performed in an area other than the internal flash memory. 3: Simultaneously with the CPU reprogramming mode select bit (bit 1) cleared "0," this bit is also cleared to "0." 4: Only when the CPU reprogramming mode select bit (bit 1) = "1," writing to this bit is available. 5: This bit is valid only when the CPU reprogramming mode select bit = "1": on the other hand, when the CPU reprogramming mode select bit = "0," be sure to fix this bit to "0." 6: After writing of "1" to this bit, be sure to write "0" successively. 7: When MD1 = Vss level, this bit is invalid. (It may be either "0" or "1.") 7902 Group User's Manual 21-39 APPENDIX Appendix 2. Control registers b7 b6 b5 b4 b3 b2 b1 b0 Real-time output control register (Address A016) Bit 0 Function Bit name Waveform output select bits See the table below. 1 2 7 to 3 0 : Pulse mode 0 1 : Pulse mode 1 Pulse output mode select bit The value is "0" at reading. At reset R/W Reference 0 RW 11-4 0 RW 0 RW 0 -- Note: When using pins P50 to P57 as pulse output pins of the real-time output function, be sure to set the corresponding bits of the port P5 direction register (address D 16) to "1." When using pins RTP1 0 to RTP13 , do not select the key input interrupt pins (KI0 to KI3 ) multiplexed with pins RTP10 to RTP13. (Refer to "CHAPTER 8. KEY INPUT INTERRUPT.") b1 b0 Pulse mode 0 P57/RTP13 P56/RTP12 P55/RTP11 P54/RTP10 Port P57/RTP13 P56/RTP12 P55/RTP11 P54/RTP10 Port P53/RTP03 P52/RTP02 P51/RTP01 P50/RTP00 P57/RTP13 P56/RTP12 P55/RTP11 P54/RTP10 P53/RTP03 P52/RTP02 P51/RTP01 P50/RTP00 P53/RTP03 P52/RTP02 P51/RTP01 P50/RTP00 Pulse mode 1 01 00 RTP P57/RTP13 P56/RTP12 P55/RTP11 P54/RTP10 RTP Port P53/RTP03 P52/RTP02 P51/RTP01 P50/RTP00 RTP Port P57/RTP13 P56/RTP12 P55/RTP11 P54/RTP10 P53/RTP03 P52/RTP02 RTP P57/RTP13 P56/RTP12 P55/RTP11 P54/RTP10 P53/RTP03 P52/RTP02 RTP RTP P51/RTP01 P50/RTP00 Port P51/RTP01 P50/RTP00 RTP Port P57/RTP13 P56/RTP12 P55/RTP11 P54/RTP10 RTP P53/RTP03 P52/RTP02 P51/RTP01 P50/RTP00 Port P57/RTP13 P56/RTP12 P55/RTP11 P54/RTP10 P53/RTP03 P52/RTP02 Port P51/RTP01 P50/RTP00 Port : This functions as a programmable I/O port pin. RTP : This functions as a pulse output pin. 21-40 11 10 7902 Group User's Manual APPENDIX Appendix 2. Control registers b7 b6 b5 b4 b3 b2 b1 b0 Pulse output data register 0 (Address A216) Bit Function Bit name R/W Reference Undefined WO 11-5 Undefined WO 0 RTP00 pulse output data bit 1 RTP01 pulse output data bit 2 RTP02 pulse output data bit (Valid in pulse mode 0.) Undefined WO 3 RTP03 pulse output data bit (Valid in pulse mode 0.) Undefined WO Nothing is assigned. Undefined -- 7 to 4 0 : "L" level output 1 : "H" level output At reset Note: When writing to this register, use the MOVM (MOVMB) instruction or STA (STAB, STAD) instruction. b7 b6 b5 b4 b3 b2 b1 b0 Pulse output data register 1 (Address A416) Bit Bit name 1, 0 Nothing is assigned. Function At reset R/W Reference Undefined -- 11-5 Undefined WO 2 RTP02 pulse output data bit (Valid in pulse mode 1.) 3 RTP03 pulse output data bit (Valid in pulse mode 1.) Undefined WO 4 RTP10 pulse output data bit Undefined WO 5 RTP11 pulse output data bit Undefined WO 6 RTP12 pulse output data bit Undefined WO 7 RTP13 pulse output data bit Undefined WO 0 : "L" level output 1 : "H" level output Note: When writing to this register, use the MOVM (MOVMB) instruction or STA (STAB, STAD) instruction. 7902 Group User's Manual 21-41 APPENDIX Appendix 2. Control registers b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O pin control register (Address AC16) Bit Function Bit name At reset R/W Reference 12-17 0 CTS0/RTS0 separate select bit (Note) 0 : CTS0/RTS0 are used together. 1 : CTS0/RTS0 are separated. 0 RW 1 CTS1/RTS1 separate select bit 0 : CTS1/RTS1 are used together. 1 : CTS1/RTS1 are separated. 0 RW (Note) 2 TxD0/P83 switch bit 0 : Functions as TxD0. 1 : Functions as P83. 0 RW 3 TxD1/P87 switch bit 0 : Functions as TxD1. 1 : Functions as P87. 0 RW 0 -- 7 to 4 The value is "0" at reading. Note: Valid when the CTS/RTS enable bit (bit 4 at addresses 3416 and 3C16) is "0." b7 b6 b5 b4 b3 b2 b1 b0 Clock control register (Address BC16) 0 Function 1 At reset R/W Reference Fix this bit to "1." PLL circuit operation enable bit 0 : PLL frequency muliplier is inactive, and pin VCONT is invalid. (Floating) (Note 1) 1 : PLL frequency muliplier is active, and pin VCONT is valid. 1 RW 5-6 5-7 1 RW PLL multiplication ratio select bits b3 b2 0 0 : Do not select. (Note 2) 0 1 : Double 1 0 : Triple 1 1 : Quadruple 1 RW 0 RW 4 Fix this bit to "0." 0 RW 5 System clock select bit 0 RW 6 Peripheral device's clock select bit 0 See Table 5.2.2. 0 RW 7 Peripheral device's clock select bit 1 0 RW Bit 0 1 2 3 Bit name 0 : fXIN (Note 3) 1 : fPLL Notes 1: Clear this bit to "0" if the PLL frequency multiplier need not to be active. In the stop and flash memory parallel I/O modes, the PLL frequency multiplier is inactive and pin VCONT is invalid regardless of the contents of this bit. 2: Rewriting of these bits must be performed simultaneously with clearance of the system clock select bit (bit 5). Then, set bit 5 to "1" 2 ms after the rewriting of these bits. (After reset, these bits are allowed to be changed only once.) 3: Clearing the PLL circuit operation enable bit (bit 1) to "0" clears the system clock select bit to "0." Also, while the PLL circuit operation enable bit = "0," nothing can be written to the system clock select bit. (Fixed to be "0.") In order to set the system clock select bit to "1" after reset, it is necessary to wait 2 ms after the stabilization of f(XIN ). 21-42 7902 Group User's Manual APPENDIX Appendix 3. Package outline Appendix 3. Package outline 100P6S-A Plastic 100pin 1420mm body QFP EIAJ Package Code QFP100-P-1420-0.65 Weight(g) 1.58 Lead Material Alloy 42 MD e JEDEC Code - ME HD D 81 b2 100 1 80 I2 E HE Recommended Mount Pad Symbol A A1 A2 b c D E e HD HE L L1 y 51 30 50 A L1 c A2 31 F b A1 e b2 I2 MD ME L Detail F y 100P6Q-A Dimension in Millimeters Min Nom Max 3.05 - - 0.1 0.2 0 2.8 - - 0.25 0.3 0.4 0.13 0.15 0.2 13.8 14.0 14.2 19.8 20.0 20.2 0.65 - - 16.5 16.8 17.1 22.5 22.8 23.1 0.4 0.6 0.8 1.4 - - 0.1 - - 0 10 - 0.35 - - - - 1.3 14.6 - - - - 20.6 Plastic 100pin 1414mm body LQFP EIAJ Package Code LQFP100-P-1414-0.50 Weight(g) Lead Material Cu Alloy MD e JEDEC Code - b2 ME HD D 76 100 I2 75 1 Symbol HE E Recommended Mount Pad 51 25 50 26 A L1 F b y A1 c A2 e L Detail F 7902 Group User's Manual A A1 A2 b c D E e HD HE L L1 y b2 I2 MD ME Dimension in Millimeters Min Nom Max 1.7 - - 0.1 0.2 0 1.4 - - 0.13 0.18 0.28 0.105 0.125 0.175 13.9 14.0 14.1 13.9 14.0 14.1 0.5 - - 15.8 16.0 16.2 15.8 16.0 16.2 0.3 0.5 0.7 1.0 - - 0.1 - - 0 10 - 0.225 - - - - 1.0 14.4 - - - - 14.4 21-43 APPENDIX Appendix 4. Examples of handling unused pins Appendix 4. Examples of handling unused pins When unusing an I/O pin, some handling is necessary for this pin. Examples of handling unused pins are described below. The following are just examples. In actual use, the user shall modify them according to the user's application and properly evaluate their performance. 1. In the single-chip mode Table 1 Example of handling unused pins in single-chip mode Pin name P0 to P3, P4 0 to P4 3, P5 to P8, P10, P11 P4 4 to P4 7 NMI (Notes 2, 4), XOUT (Note 5), V CONT (Note 6) AV CC AV SS, V REF, BYTE Handling example Set these pins to the input mode and connect each pin to Vcc or Vss via a resistor; or set these pins to the output mode and leave them open (Note 1). Set these pins to the input mode and leave them open (Notes 2, 3) Leave these pins open. Connect this pin to Vcc. Connect these pins to Vss. Notes 1: When leaving these pins open after they have been set to the output mode, note the following: these port pins are placed in the input mode from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these port pins are placed in the input mode. Software reliability can be enhanced by setting the contents of the above ports' direction registers periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer's pins). 2: Do not connect these pins to Vss. 3: Be sure that the pins P44-P47 pullup select bit (bit 4 at address 9216) = 0. 4: Be sure that the pin NMI pullup select bit (bit 7 at address 9216) = 0. 5: This applies when a clock externally generated is input to pin XIN. 6: Be sure that the PLL circuit operation enable bit (bit 1 at address BC16) = 0. When setting port pins to input mode P0-P3, P40-P43, P5-P8, P10, P11 P0-P8, P10, P11 Left open NMI XOUT VCONT Left open Left open M37902 M37902 P44-P47 NMI XOUT VCONT When setting port pins to output mode (Note) VCC AVCC AVSS VREF BYTE VCC AVCC AVSS VREF BYTE VSS VSS Note: Be sure to set P44-P47 to the input mode. Fig. 1 Example of handling unused pins in single-chip mode 21-44 7902 Group User's Manual APPENDIX Appendix 4. Examples of handling unused pins 2. In memory expansion and microprocessor modes Table 2 Example of handling unused pins in memory expansion and microprocessor modes Pin name Handling example P2 (Note 1), P30, P33 (Note 1), P40 to P43, P5 to P8 Set these pins to the input mode and connect each pin to Vcc or Vss via a resistor; or set these pins to the output mode and leave them open (Note 2). P4 4 to P47 NMI (Notes 3, 5), X OUT (Note 6), V CONT (Note 7) AV CC AV SS, V REF Set these pins to the input mode and leave them open (Notes 3,4) Leave these pins open. Connect this pin to Vcc. Connect these pins to Vss. Leave these pins open. 1 (Note 8), ALE (Note 8), HLDA (Note 8) RDY (Note 8), HOLD (Note 8) Connect these pins to Vcc via a resistor. Notes 1: This applies when the V CC level voltage is applied to pin BYTE. 2: When leaving these pins open after they have been set to the output mode, note the following: these port pins are placed in the input mode from reset until they are switched to the output mode by software. Therefore, voltage levels of these pins are undefined and the power source current may increase while these pins are placed in the input mode. Software reliability can be enhanced by setting the contents of the above ports' direction registers periodically. This is because these contents may be changed by noise, a program runaway which occurs owing to noise, etc. 3: Do not connect these pins to Vss. 4: Be sure that the pins P44-P47 pullup select bit (bit 4 at address 92 16) = 0. 5: Be sure that the pin NMI pullup select bit (bit 7 at address 9216) = 0. 6: This applies when a clock externally generated is input to pin X IN. 7: Be sure that the PLL circuit operation enable bit (bit 1 at address BC16) = 0. 8: This applies when the Vcc-level voltage is applied to pin MD0. (It is also possible to disable these functions by software and use these pins as programmable I/O port pins.) When setting port pins to output mode When setting port pins to input mode P2, P30, P33, P40-P43, P5-P8 Left open 1 ALE HLDA RDY HOLD Left open Left open VCC 1 ALE HLDA M37902 M37902 VCC P44-P47 NMI XOUT VCONT P2, P30, P33, P4-P8 VCC AVCC AVSS VREF RDY HOLD NMI XOUT VCONT Left open Left open VCC AVCC AVSS VREF VSS VSS Note: Be sure to set P44-P47 to the input mode. Fig. 2 Example of handling unused pins in memory expansion and microprocessor modes 7902 Group User's Manual 21-45 APPENDIX Appendix 5. Hexadecimal instruction code table Appendix 5. Hexadecimal instruction code table INSTRUCTION CODE TABLE 0 D3-D0 Hexadecimal D7-D4 notation 0000 0001 0010 0011 0100 0101 0110 6 0 1 2 3 4 5 Table 1 LDX DIR ASL A SEC IMP SEI IMP 0111 1000 1001 1010 1011 1100 1101 1110 1111 7 8 9 A B C D E F LDX ABS LDAB A,(DIR),Y LDAB A,L(DIR),Y LDAB A,DIR LDAB A,DIR,X LDAB A,ABL LDAB A,ABL,X LDAB A,ABS LDAB A,ABS,X 0000 0 BRK IMP 0001 1 BPL REL Table 2 LDY DIR ROL A CLC IMP CLI IMP LDA A,IMM LDY ABS LDA A,(DIR),Y LDA A,L(DIR),Y LDA A,DIR LDA A,DIR,X LDA A,ABL LDA A,ABL,X LDA A,ABS LDA A,ABS,X 0010 2 BRA REL Table 3 CPX DIR ANDB A,IMM NEG A SEM IMP ADD A,IMM LDXB IMM LDAB A,IMM ADDB A,IMM ADD A,DIR ADD A,DIR,X LDAD E,IMM ADDD E,IMM ADD A,ABS ADD A,ABS,X 0011 3 BMI REL Table 4 CPY DIR EORB A,IMM EXTZ A EXTS A SUB A,IMM LDYB IMM CMPB A,IMM SUBB A,IMM SUB A,DIR SUB A,DIR,X CMPD E,IMM SUBD E,IMM SUB A,ABS SUB A,ABS,X 0100 4 BGTU REL Table 5 BBSB DIR,b,REL LSR A CLRB A CLM IMP CMP A,IMM BBSB ABS,b,REL MOVMB DIR/DIR CMP A,DIR CMP A,DIR,X MOVMB DIR/ABS MOVMB DIR/ABS,X CMP A,ABS CMP A,ABS,X 0101 5 BVC REL Table 6 BBCB DIR,b,REL ROR A CLR A XAB IMP ORA A,IMM BBCB ABS,b,REL MOVM DIR/DIR ORA A,DIR ORA A,DIR,X MOVM DIR/ABS MOVM DIR/ABS,X ORA A,ABS ORA A,ABS,X 0110 6 BLEU REL Table 7 CBEQB ORAB A,IMM ASR A CLV IMP AND A,IMM PUL STK MOVMB ABS/DIR MOVMB ABS/DIR,X AND A,DIR AND A,DIR,X MOVMB ABS/ABS AND A,ABS AND A,ABS,X 0111 7 BVS REL Table 8 E OR A,IMM PLD n /RTLD n /RTSD n ST K MOVM ABS/DIR MOVM ABS/DIR,X E OR A,DIR E OR A,DIR,X MOVM ABS/ABS E OR A,ABS E OR A,ABS,X 1000 8 BGT REL Table 9 INC DIR PHD STK RTS IMP PHA STK MOVM DIR/IMM INC ABS LDAD E,(DIR),Y LDAD E,L(DIR),Y LDAD E,DIR LDAD E,DIR,X LDAD E,ABL LDAD E,ABL,X LDAD E,ABS LDAD E,ABS,X 1001 9 BCC REL Table 10 DEC DIR PLD STK RTL IMP PLA STK MOVM ABS/IMM DEC ABS CLP IMM SEP IMM ADDD E,DIR ADDD E,DIR,X JMP ABS JSR ABS ADDD E,ABS ADDD E,ABS,X 1010 A BLE REL Table 11 A/IMM,REL CBEQB INC A TXA IMP PHP STK CBEQ A/IMM,REL BRAL REL PSH STK MOVMB DIR/IMM SUBD E,DIR SUBD E,DIR,X JMPL ABL JSRL ABL SUBD E,ABS SUBD E,ABS,X 1011 B BCS REL Table 12 A/IMM,REL CBNEB DEC A TYA IMP PLP STK CBNE A/IMM,REL LDD n /PHD n /PHLD n STK/IMM MOVMB ABS/IMM CMPD E,DIR CMPD E,DIR,X JMP (ABS,X) JSR (ABS,X) CMPD E,ABS CMPD E,ABS,X 1100 C BGE REL Table 13 CLRMB DIR INX IMP TAX IMP PHX STK LDX IMM CLRMB ABS STAB A,(DIR),Y STAB A,L(DIR),Y STAB A,DIR STAB A,DIR,X STAB A,ABL STAB A,ABL,X STAB A,ABS STAB A,ABS,X 1101 D BNE REL Table 14 CLRM DIR INY IMP TAY IMP PLX STK LDY IMM CLRM ABS STA A,(DIR),Y STA A,L(DIR),Y STA A,DIR STA A,DIR,X STA A,ABL STA A,ABL,X STA A,ABS STA A,ABS,X 1110 E BLT REL ABS A STX DIR DEX IMP CLRX IMP PHY STK CPX IMM STX ABS STAD E,(DIR),Y STAD E,L(DIR),Y STAD E,DIR STAD E,DIR,X STAD E,ABL STAD E,ABL,X STAD E,ABS STAD E,ABS,X 1111 F BEQ REL RTI IMP STY DIR DEY IMP CLRY IMP PLY STK CPY IMM STY ABS DIR/IMM,REL CBNEB NOP IMP DIR/IMM,REL Note: Tables 1 through 14 specifies the contents of the INSTRUCTION CODE TABLE 1 through 14. About the second word's codes, refer to the INSTRUCTION CODE TABLE 1 through 14. 21-46 7902 Group User's Manual BSR REL APPENDIX Appendix 5. Hexadecimal instruction code table INSTRUCTION CODE TABLE 1 (The first word's code of each instruction is 0116) D3-D0 Hexadecimal D7-D4 notation 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 A 1011 B 1100 C 1101 D 1110 E 1111 F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F ADDX IMM ADDY IMM SUBX IMM SUBY IMM BSS A,b,REL BSC A,b,REL DXBNE IMM,REL DYBNE IMM,REL INSTRUCTION CODE TABLE 2 (The first word's code of each instruction is 1116) D3-D0 Hexadecimal D7-D4 notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F LDAB A,(DIR,X) LDAB A,L(DIR) LDAB A,SR LDAB A,(SR),Y LDAB A,ABS,Y 0000 0 LDAB A,(DIR) 0001 1 LDA A,(DIR) LDA A,(DIR,X) LDA A,L(DIR) LDA A,SR LDA A,(SR),Y LDA A,ABS,Y 0010 2 ADD A,(DIR) ADD A,(DIR,X) ADD A,L(DIR) ADD A,SR ADD A,(SR),Y ADD A,ABS,Y ADD ADD A,(DIR),Y A,L(DIR),Y ADD A,ABL ADD A,ABL,X 0011 3 SUB A,(DIR) SUB A,(DIR,X) SUB A,L(DIR) SUB A,SR SUB A,(SR),Y SUB A,ABS,Y SUB SUB A,(DIR),Y A,L(DIR),Y SUB A,ABL SUB A,ABL,X 0100 4 CMP A,(DIR) CMP A,(DIR,X) CMP A,L(DIR) CMP A,SR CMP A,(SR),Y CMP A,ABS,Y CMP CMP A,(DIR),Y A,L(DIR),Y CMP A,ABL CMP A,ABL,X 0101 5 ORA A,(DIR) ORA A,(DIR,X) ORA A,L(DIR) ORA A,SR ORA A,(SR),Y ORA A,ABS,Y ORA ORA A,(DIR),Y A,L(DIR),Y ORA A,ABL ORA A,ABL,X 0110 6 AND A,(DIR) AND A,(DIR,X) AND A,L(DIR) AND A,SR AND A,(SR),Y AND A,ABS,Y AND AND A,(DIR),Y A,L(DIR),Y AND A,ABL AND A,ABL,X 0111 7 E OR A,(DIR) E OR A,(DIR,X) E OR A,L(DIR) E OR A,SR E OR A,(SR),Y E OR A,ABS,Y E OR E OR A,(DIR),Y A,L(DIR),Y E OR A,ABL E OR A,ABL,X 1000 8 LDAD E,(DIR) LDAD E,(DIR,X) LDAD E,L(DIR) LDAD E,SR LDAD E,(SR),Y LDAD E,ABS,Y 1001 9 ADDD E,(DIR) ADDD E,(DIR,X) ADDD E,L(DIR) ADDD E,SR ADDD E,(SR),Y ADDD E,ABS,Y ADDD ADDD E,(DIR),Y E,L(DIR),Y ADDD E,ABL ADDD E,ABL,X 1010 A SUBD E,(DIR) SUBD E,(DIR,X) SUBD E,L(DIR) SUBD E,SR SUBD E,(SR),Y SUBD E,ABS,Y SUBD SUBD E,(DIR),Y E,L(DIR),Y SUBD E,ABL SUBD E,ABL,X 1011 B CMPD E,(DIR) CMPD E,(DIR,X) CMPD E,L(DIR) CMPD E,SR CMPD E,(SR),Y CMPD E,ABS,Y CMPD CMPD E,(DIR),Y E,L(DIR),Y CMPD E,ABL CMPD E,ABL,X 1100 C STAB A,(DIR) STAB A,(DIR,X) STAB A,L(DIR) STAB A,SR STAB A,(SR),Y STAB A,ABS,Y 1101 D STA A,(DIR) STA A,(DIR,X) STA A,L(DIR) STA A,SR STA A,(SR),Y STA A,ABS,Y 1110 E STAD E,(DIR) STAD E,(DIR,X) STAD E,L(DIR) STAD E,SR STAD E,(SR),Y STAD E,ABS,Y 1111 F 7902 Group User's Manual 21-47 APPENDIX Appendix 5. Hexadecimal instruction code table INSTRUCTION CODE TABLE 3 (The first word's code of each instruction is 2116) D3-D0 Hexadecimal D7-D4 notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 0 1 2 3 4 5 6 7 8 9 1010 1011 1100 1101 C D 1110 1111 A B E F ASL DIR,X ASL ABS ASL ABS,X 0000 0 ASL DIR 0001 1 ROL DIR ROL DIR,X ROL ABS ROL ABS,X 0010 2 LSR DIR LSR DIR,X LSR ABS LSR ABS,X 0011 3 ROR DIR ROR DIR,X ROR ABS ROR ABS,X 0100 4 ASR DIR ASR DIR,X ASR ABS ASR ABS,X 0101 5 0110 6 0111 7 1000 8 ADC A,(DIR) ADC A,(DIR,X) ADC A,L(DIR) ADC A,SR ADC A,(SR),Y ADC A,ABS,Y ADC ADC A,(DIR),Y A,L(DIR),Y ADC A,DIR ADC A,DIR,X ADC A,ABL ADC A,ABL,X ADC A,ABS ADC A,ABS,X 1001 9 ADCD E,(DIR) ADCD E,(DIR,X) ADCD E,L(DIR) ADCD E,SR ADCD E,(SR),Y ADCD E,ABS,Y ADCD ADCD E,(DIR),Y E,L(DIR),Y ADCD E,DIR ADCD E,DIR,X ADCD E,ABL ADCD E,ABL,X ADCD E,ABS ADCD E,ABS,X 1010 A SBC A,(DIR) SBC A,(DIR,X) SBC A,L(DIR) SBC A,SR SBC A,(SR),Y SBC A,ABS,Y SBC SBC A,(DIR),Y A,L(DIR),Y SBC A,DIR SBC A,DIR,X SBC A,ABL SBC A,ABL,X SBC A,ABS SBC A,ABS,X 1011 B SBCD E,(DIR) SBCD E,(DIR,X) SBCD E,L(DIR) SBCD E,SR SBCD E,(SR),Y SBCD E,ABS,Y SBCD SBCD E,(DIR),Y E,L(DIR),Y SBCD E,DIR SBCD E,DIR,X SBCD E,ABL SBCD E,ABL,X SBCD E,ABS SBCD E,ABS,X 1100 C MPY (DIR) MPY (DIR,X) MPY L(DIR) MPY SR MPY (SR),Y MPY ABS,Y MPY (DIR),Y MPY L(DIR),Y MPY DIR MPY DIR,X MPY ABL MPY ABL,X MPY ABS MPY ABS,X 1101 D MPYS (DIR) MPYS (DIR,X) MPYS L(DIR) MPYS SR MPYS (SR),Y MPYS ABS,Y MPYS (DIR),Y MPYS L(DIR),Y MPYS DIR MPYS DIR,X MPYS ABL MPYS ABL,X MPYS ABS MPYS ABS,X 1110 E DIV (DIR) DIV (DIR,X) DIV L(DIR) DIV SR DIV (SR),Y DIV ABS,Y DIV (DIR),Y DIV L(DIR),Y DIV DIR DIV DIR,X DIV ABL DIV ABL,X DIV ABS DIV ABS,X 1111 F DIVS (DIR) DIVS (DIR,X) DIVS L(DIR) DIVS SR DIVS (SR),Y DIVS ABS,Y DIVS (DIR),Y DIVS L(DIR),Y DIVS DIR DIVS DIR,X DIVS ABL DIVS ABL,X DIVS ABS DIVS ABS,X INSTRUCTION CODE TABLE 4 (The first word's code of each instruction is 3116) D3-D0 Hexadecimal D7-D4 notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F ADDS IMM SUBS IMM TAD,1 IMP ADCB A,IMM SBCB A,IMM ADCD E,IMM SBCD E,IMM TAD,2 IMP MVP BLK MVN BLK PEA STK PER STK JMP (ABS) JMPL L(ABS) RLA A TAD,0 IMP 0000 0 0001 1 0010 2 0011 3 STP IMP TAD,3 IMP 0100 4 PHT STK TDA,0 IMP WIT IMP MOVMB MOVMB DIR,X/IMM ABS,X/IMM MOVM DIR,X/IMM LDT IMM MOVM ABS,X/IMM RMPA 0101 5 PLT STK TDA,1 IMP 0110 6 PHG STK TDA,2 IMP 0111 7 TSD IMP TDA,3 IMP 1000 8 NEGD E TAS IMP 1001 9 ABSD E TSA IMP 1010 A EXTZD E 1011 B EXTSD E 1100 C TXY IMP MPY IMM 1101 D TYX IMP MPYS IMM 1110 E TXS IMP DIV IMM 1111 F TSX IMP DIVS IMM 21-48 TDS IMP ADC A,IMM SBC A,IMM 7902 Group User's Manual Multiplied accumulation PEI STK APPENDIX Appendix 5. Hexadecimal instruction code table INSTRUCTION CODE TABLE 5 (The first word's code of each instruction is 4116) D3-D0 Hexadecimal D7-D4 notation 0000 0001 0010 0011 0100 0 1 2 3 4 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 5 6 7 8 9 A B C D E F LDX DIR,Y LDX ABS,Y 0000 0 0001 1 0010 2 CPX ABS 0011 3 CPY ABS 0100 4 BBS DIR,b,REL BBS ABS,b,REL 0101 5 BBC DIR,b,REL BBC ABS,b,REL 0110 6 DIR/IMM,REL 0111 7 DIR/IMM,REL 1000 8 INC DIR,X INC ABS,X 1001 9 DEC DIR,X DEC ABS,X 1010 A 1011 B 1100 C 1101 D 1110 E 1111 F LDY DIR,X LDY ABS,X CBEQ CBNE STX DIR,Y STY DIR,X INSTRUCTION CODE TABLE 6 (The first word's code of each instruction is 5116) D3-D0 Hexadecimal D7-D4 notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F ADDM DIR/IMM ADDMB ABS/IMM ADDM ABS/IMM 0000 0 ADDMB DIR/IMM 0001 1 SUBMB DIR/IMM SUBM DIR/IMM SUBMB ABS/IMM SUBM ABS/IMM 0010 2 CMPMB DIR/IMM CMPM DIR/IMM CMPMB ABS/IMM CMPM ABS/IMM 0011 3 ORAMB DIR/IMM ORAM DIR/IMM ORAMB ABS/IMM ORAM ABS/IMM 0100 4 0101 5 0110 6 ANDMB DIR/IMM ANDM DIR/IMM ANDMB ABS/IMM ANDM ABS/IMM 0111 7 EORMB DIR/IMM EORM DIR/IMM EORMB ABS/IMM EORM ABS/IMM 1000 8 ADDMD DIR/IMM ADDMD ABS/IMM 1001 9 SUBMD DIR/IMM SUBMD ABS/IMM 1010 A CMPMD DIR/IMM CMPMD ABS/IMM 1011 B ORAMD DIR/IMM ORAMD ABS/IMM 1100 C 1101 D 1110 E ANDMD DIR/IMM ANDMD ABS/IMM 1111 F EORMD DIR/IMM EORMD ABS/IMM 7902 Group User's Manual 21-49 APPENDIX Appendix 5. Hexadecimal instruction code table INSTRUCTION CODE TABLE 7 (The first word's code of each instruction is 6116) D3-D0 Hexadecimal D7-D4 notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F 0000 0 MOVRB DIR/IMM 0001 1 MOVR DIR/IMM 0010 2 MOVRB ABS/IMM 0011 3 MOVR ABS/IMM 0100 4 MOVRB DIR/DIR 0101 5 MOVR DIR/DIR 0110 6 MOVRB ABS/DIR 0111 7 MOVR ABS/DIR 1000 8 MOVRB DIR/ABS 1001 9 MOVR DIR/ABS 1010 A MOVRB ABS/ABS 1011 B MOVR ABS/ABS 1100 C 1101 D 1110 E 1111 F INSTRUCTION CODE TABLE 8 (The first word's code of each instruction is 7116) D3-D0 Hexadecimal D7-D4 notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F 0000 0 MOVRB DIR/ABS,X 0001 1 MOVR DIR/ABS,X 0010 2 0011 3 0100 4 0101 5 0110 6 MOVRB ABS/DIR,X 0111 7 MOVR ABS/DIR,X 1000 8 1001 9 1010 A 1011 B 1100 C 1101 D 1110 E 1111 F 21-50 BSS DIR,b,REL BSC DIR,b,REL BSS ABS,b,REL BSC ABS,b,REL 7902 Group User's Manual APPENDIX Appendix 5. Hexadecimal instruction code table INSTRUCTION CODE TABLE 9 (The first word's code of each instruction is 8116) D3-D0 Hexadecimal D7-D4 notation 0000 0001 0010 0 1 2 0011 0100 0101 0110 0111 3 4 5 6 7 1000 1001 1010 1011 1100 1101 1110 1111 8 9 A B C D E F LDAB B,(DIR),Y LDAB B,L(DIR),Y LDAB B,DIR LDAB B,DIR,X LDAB B,ABL LDAB B,ABL,X LDAB B,ABS LDAB B,ABS,X LDA B,IMM LDA B,(DIR),Y LDA B,L(DIR),Y LDA B,DIR LDA B,DIR,X LDA B,ABL LDA B,ABL,X LDA B,ABS LDA B,ABS,X ADD B,IMM LDAB B,IMM ADDB B,IMM ADD B,DIR ADD B,DIR,X ADD B,ABS ADD B,ABS,X SUB B,IMM CMPB B,IMM SUBB B,IMM SUB B,DIR SUB B,DIR,X SUB B,ABS SUB B,ABS,X 0000 0 ASL B 0001 1 ROL B 0010 2 ANDB B,IMM NEG B 0011 3 EORB B,IMM EXTZ B 0100 4 LSR B CLRB B CMP B,IMM CMP B,DIR CMP B,DIR,X CMP B,ABS CMP B,ABS,X 0101 5 ROR B CLR B ORA B,IMM ORA B,DIR ORA B,DIR,X ORA B,ABS ORA B,ABS,X 0110 6 ORAB B,IMM ASR B AND B,IMM AND B,DIR AND B,DIR,X AND B,ABS AND B,ABS,X 0111 7 E OR B,IMM E OR B,DIR E OR B,DIR,X E OR B,ABS E OR B,ABS,X 1000 8 PHB STK 1001 9 PLB STK 1010 A CBEQB B/IMM,REL INC B TXB IMP CBEQ B/IMM,REL 1011 B CBNEB B/IMM,REL DEC B TYB IMP CBNE B/IMM,REL 1100 C TBX IMP STAB B,(DIR),Y STAB B,L(DIR),Y STAB B,DIR STAB B,DIR,X STAB B,ABL STAB B,ABL,X STAB B,ABS STAB B,ABS,X 1101 D TBY IMP STA B,(DIR),Y STA B,L(DIR),Y STA B,DIR STA B,DIR,X STA B,ABL STA B,ABL,X STA B,ABS STA B,ABS,X 1110 E 1111 F EXTS B ABS B INSTRUCTION CODE TABLE 10 (The first word's code of each instruction is 9116) D3-D0 Hexadecimal D7-D4 notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F LDAB B,(DIR,X) LDAB B,L(DIR) LDAB B,SR LDAB B,(SR),Y LDAB B,ABS,Y 0000 0 LDAB B,(DIR) 0001 1 LDA B,(DIR) LDA B,(DIR,X) LDA B,L(DIR) LDA B,SR LDA B,(SR),Y LDA B,ABS,Y 0010 2 ADD B,(DIR) ADD B,(DIR,X) ADD B,L(DIR) ADD B,SR ADD B,(SR),Y ADD B,ABS,Y ADD ADD B,(DIR),Y B,L(DIR),Y ADD B,ABL ADD B,ABL,X 0011 3 SUB B,(DIR) SUB B,(DIR,X) SUB B,L(DIR) SUB B,SR SUB B,(SR),Y SUB B,ABS,Y SUB SUB B,(DIR),Y B,L(DIR),Y SUB B,ABL SUB B,ABL,X 0100 4 CMP B,(DIR) CMP B,(DIR,X) CMP B,L(DIR) CMP B,SR CMP B,(SR),Y CMP B,ABS,Y CMP CMP B,(DIR),Y B,L(DIR),Y CMP B,ABL CMP B,ABL,X 0101 5 ORA B,(DIR) ORA B,(DIR,X) ORA B,L(DIR) ORA B,SR ORA B,(SR),Y ORA B,ABS,Y ORA ORA B,(DIR),Y B,L(DIR),Y ORA B,ABL ORA B,ABL,X 0110 6 AND B,(DIR) AND B,(DIR,X) AND B,L(DIR) AND B,SR AND B,(SR),Y AND B,ABS,Y AND AND B,(DIR),Y B,L(DIR),Y AND B,ABL AND B,ABL,X 0111 7 E OR B,(DIR) E OR B,(DIR,X) E OR B,L(DIR) E OR B,SR E OR B,(SR),Y E OR B,ABS,Y E OR E OR B,(DIR),Y B,L(DIR),Y E OR B,ABL E OR B,ABL,X 1000 8 1001 9 1010 A 1011 B 1100 C STAB B,(DIR) STAB B,(DIR,X) STAB B,L(DIR) STAB B,SR STAB B,(SR),Y STAB B,ABS,Y 1101 D STA B,(DIR) STA B,(DIR,X) STA B,L(DIR) STA B,SR STA B,(SR),Y STA B,ABS,Y 1110 E 1111 F 7902 Group User's Manual 21-51 APPENDIX Appendix 5. Hexadecimal instruction code table INSTRUCTION CODE TABLE 11 (The first word's code of each instruction is A116) D3-D0 Hexadecimal D7-D4 notation 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 A 1011 B 1100 C 1101 D 1110 E 1111 F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F ADC B,(DIR) ADC B,(DIR,X) ADC B,L(DIR) ADC B,SR ADC B,(SR),Y ADC B,ABS,Y ADC ADC B,(DIR),Y B,L(DIR),Y ADC B,DIR ADC B,DIR,X ADC B,ABL ADC B,ABL,X ADC B,ABS ADC B,ABS,X SBC B,(DIR) SBC B,(DIR,X) SBC B,L(DIR) SBC B,SR SBC B,(SR),Y SBC B,ABS,Y SBC B,(DIR),Y SBC B,DIR SBC B,DIR,X SBC B,ABL SBC B,ABL,X SBC B,ABS SBC B,ABS,X SBC B,L(DIR),Y INSTRUCTION CODE TABLE 12 (The first word's code of each instruction is B116) D3-D0 Hexadecimal D7-D4 notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F ADCB B,IMM SBCB B,IMM 0000 0 TBD,0 IMP 0001 1 TBD,1 IMP 0010 2 TBD,2 IMP 0011 3 TBD,3 IMP 0100 4 TDB,0 IMP 0101 5 TDB,1 IMP 0110 6 TDB,2 IMP 0111 7 TDB,3 IMP 1000 8 TBS IMP 1001 9 TSB IMP 1010 A 1011 B 1100 C 1101 D 1110 E 1111 F 21-52 ADC B,IMM SBC B,IMM 7902 Group User's Manual APPENDIX Appendix 5. Hexadecimal instruction code table INSTRUCTION CODE TABLE 13 (The first word's code of each instruction is C116) D3-D0 Hexadecimal D7-D4 notation 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 A 1011 B 1100 C 1101 D 1110 E 1111 F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F LSR,#n A ROR,#n A ASL,#n A ROL,#n A ASR,#n A DEBNE DIR/IMM,REL INSTRUCTION CODE TABLE 14 (The first word's code of each instruction is D116) D3-D0 Hexadecimal D7-D4 notation 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 A 1011 B 1100 C 1101 D 1110 E 1111 F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F LSRD,#n E RORD,#n E ASLD,#n E ROLD,#n E ASRD,#n E DEBNE ABS/IMM,REL 7902 Group User's Manual 21-53 APPENDIX APPENDIX Appendix 6. Machine instructions Appendix 6. Machine instructions Appendix 6. Machine instructions Note: For an instruction of which "Operation length (Bit)" = 16/8 is executed in the bit length described below. * 16-bit length when m = 0 or x = 0. * 8-bit length when m = 1 or x = 1. For an instruction of which "Operation length (Bit)" = 8 or 32 is executed in 8-bit or 32-bit length regardless of the contents of flags m and x. Symbol IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK Multiplied accumulation op n # C Z I D x m V N IPL + - / || Acc Acc H Acc L A AH AL B BH BL 21-54 7902 Group User's Manual Description Symbol Implied addressing mode Immediate addressing mode Accumulator addressing mode Direct addressing mode Direct indexed X addressing mode Direct indexed Y addressing mode Direct indirect addressing mode Direct indexed X indirect addressing mode Direct indirect indexed Y addressing mode Direct indirect long addressing mode Direct indirect long indexed Y addressing mode Absolute addressing mode Absolute indexed X addressing mode Absolute indexed Y addressing mode Absolute long addressing mode Absolute long indexed X addressing mode Absolute indirect addressing mode Absolute indirect long addressing mode Absolute indexed X indirect addressing mode Stack addressing mode Relative addressing mode Direct bit relative addressing mode Absolute bit relative addressing mode Stack pointer relative addressing mode Stack pointer relative indirect indexed Y addressing mode Block transfer addressing mode Multiplied accumulation addressing mode Instruction code (Op code) Number of cycles Number of bytes Carry flag Zero flag Interrupt disable flag Decimal operation mode flag Index register length selection flag Data length selection flag Overflow flag Negative flag Processor interrupt priority level Addition Subtraction Multiplication Division Logical AND Logical OR Logical exclusive OR Absolute value Negation Movement to the arrow direction Movement to the arrow direction Exchange Accumulator Accumulator's high-order 8 bits Accumulator's low-order 8 bits Accumulator A Accumulator A's high-order 8 bits Accumulator A's low-order 8 bits Accumulator B Accumulator B's high-order 8 bits Accumulator B's low-order 8 bits E EH EL X XH XL Y YH YL S REL PC PCH PCL PG DT DPR0 DPR0H DPR0L DPRn DPRnH DPRnL PS PSH PSL PSL(bit n) M M(S) M(bit n) Mn IMM IMMn IMMH IMML ADH ADM ADL EAR EARH EARL imm immn dd i i1, i2 source dest 7902 Group User's Manual Description Accumulator E Accumulator E's high-order 16 bits (Accumulator B) Accumulator E's low-order 16 bits (Accumulator A) Index register X Index register X's high-order 8 bits Index register X's low-order 8 bits Index register Y Index register Y's high-order 8 bits Index register Y's low-order 8 bits Stack pointer Relative address Program counter Program counter's high-order 8 bits Program counter's low-order 8 bits Program bank register Data back register Direct page register 0 Direct page register 0's high-order 8 bits Direct page register 0's low-order 8 bits Direct page register n Direct page register n's high-order 8 bits Direct page register n's low-order 8 bits Processor status register Processor status register's high-order 8 bits Processor status register's low-order 8 bits nth bit in processor status register Contents of memory Contents of memory at address indicated by stack pointer nth bit of memory n-bit memory's address or contents Immediate value (8 bits or 16 bits) n-bit immediate value 16-bit immediate value's high-order 8 bits 16-bit immediate value's low-order 8 bits Value of 24-bit address's high-order 8 bits (A23-A16) Value of 24-bit address's middle-order 8 bits (A15-A8) Value of 24-bit address's low-order 8 bits (A7-A0) Effective address (16 bits) Effective address's high-order 8 bits Effective address's low-order 8 bits 8-bit immediate value n-bit immediate value Displacement for DPR (8 bits or 16 bits) Number of transfer bytes, rotation or repeated operations Number of registers pushed or pulled Operand to specify transfer source Operand to specify transfer destination 21-55 APPENDIX APPENDIX Appendix 6. Machine instructions Appendix 6. Machine instructions 7900 Series Machine Instructions Addressing Modes Symbol ABS (Note 1) Function Acc | Acc | Operation length (Bit) IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 16/8 Addressing Modes Processor Status register ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK MAA 10 9 8 7 6 5 4 3 2 1 0 op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # IPL N V m x D I Z C E1 3 1 * * * 0 V * * * * Z 0 81 4 2 E1 ABSD E | E | ADC AccAcc + M + C (Notes 1 and 2) ADCB (Note 1) Acc LAccL + IMM8 + C ADCD EE + M32 + C 32 16/8 8 31 5 2 90 * * * 0 V * * * * Z 0 31 3 3 87 21 5 3 21 6 3 8A 8B 21 7 3 21 8 3 21 8 3 21 9 3 21 10 3 80 81 88 82 89 21 5 4 21 6 4 21 6 4 21 6 5 21 7 5 8E 8F 86 8C 8D 21 6 3 21 9 3 83 84 B1 3 3 87 A1 7 3 A1 8 3 8A 8B A1 9 3 A1 10 3 A1 10 3 A1 11 3 A1 12 3 89 80 81 88 82 A1 7 4 A1 8 4 A1 8 4 A1 8 5 A1 9 5 8E 8F 86 8C 8D A1 8 3 A1 11 3 83 84 31 3 3 1A * * * NV * * * * Z C * * * N V * * * * Z C B1 3 3 1A ADD AccAcc + M (Notes 1 and 2) ADDB (Note 1) Acc LAccL + IMM8 32 31 4 6 1C 21 7 3 21 8 3 9A 9B 21 9 3 21 10 3 21 10 3 21 11 3 21 12 3 99 90 91 98 92 21 7 4 21 8 4 21 8 4 21 8 5 21 9 5 9E 9F 96 9C 9D 21 8 3 21 11 3 93 94 * * * NV * * * * Z C 16/8 26 1 2 2A 3 2 2B 4 2 11 6 3 11 7 3 11 7 3 11 8 3 11 9 3 29 20 21 28 22 2E 3 3 2F 4 3 11 5 4 11 5 5 11 6 5 26 2C 2D 11 5 3 11 8 3 93 24 * * * NV * * * * Z C 81 2 3 26 81 4 3 81 5 3 2A 2B 91 6 3 91 7 3 91 7 3 91 8 3 91 9 3 29 20 21 28 22 81 4 4 81 5 4 91 5 4 91 5 5 91 6 5 2E 2F 26 2C 2D 91 5 3 91 8 3 23 24 8 29 1 2 * * * NV * * * * Z C 81 2 3 29 21-56 ADDD EE + M32 32 ADDM (Note 3) MM + IMM 16/8 51 7 4 03 51 7 5 07 * * * NV * * * * Z C ADDMB M8M8 + IMM8 8 51 7 4 02 51 7 5 06 * * * NV * * * * Z C ADDMD M32M32 + IMM32 32 51 10 7 83 51 10 8 87 * * * N V * * * * Z C ADDS SS + IMM8 16 31 2 3 0A * * * NV * * * * Z C ADDX XX + IMM (IMM = 0 to 31) 16/8 01 2 2 * * * NV * * * * Z C ADDY (Note 4) YY + IMM (IMM = 0 to 31) 16/8 01 2 2 20 + imm * * * NV * * * * Z C 2D 3 5 7902 Group User's Manual 9A 6 2 9B 7 2 11 9 3 11 10 3 11 10 3 11 11 3 11 12 3 90 91 98 92 99 9E 6 3 9F 7 3 11 8 4 11 8 5 11 9 5 96 9C 9D 11 8 3 11 11 3 93 94 7902 Group User's Manual * * * NV * * * * Z C 21-57 APPENDIX APPENDIX Appendix 6. Machine instructions Appendix 6. Machine instructions Addressing Modes Symbol Function AND AccAcc M (Notes 1 and 2) ANDB (Note 1) Acc LAccL IMM8 ANDM (Note 3) MM IMM ANDMB M8M8 IMM8 ANDMD M32M32 IMM32 ASL (Note 1) Arithmetic shift to the left by 1 bit Operation length (Bit) 16/8 8 IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # Addressing Modes Processor Status register ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK MAA 10 9 8 7 6 5 4 3 2 1 0 op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # IPL N V m x D I Z C 66 1 2 6A 3 2 6B 4 2 11 6 3 11 7 3 11 7 3 11 8 3 11 9 3 60 61 68 62 69 6E 3 3 6F 4 3 11 5 4 11 5 5 11 6 5 66 6C 6D 11 5 3 11 8 3 63 64 81 2 3 66 81 4 3 81 5 3 6B 6A 91 6 3 91 7 3 91 7 3 91 8 3 91 9 3 60 61 68 62 69 81 4 4 81 5 4 91 5 4 91 5 5 91 6 5 6E 6F 66 6C 6D 91 5 3 91 8 3 63 64 23 1 2 * * * N * * * * * Z * * * * N * * * * * Z * 81 2 3 23 16/8 51 7 4 63 51 7 5 67 * * * N * * * * * Z * 8 51 7 4 62 51 7 5 66 * * * N * * * * * Z * 32 51 10 7 E3 51 10 8 E7 * * * N * * * * * Z * 16/8 03 1 1 21 7 3 21 8 3 0B 0A 21 7 4 21 8 4 0E 0F * * * N * * * * * Z C m=0 Acc or M16 C b15 ... b0 0 81 2 2 03 m=1 AccL or M8 C b7 ... b0 0 ASL #n (Note 4) Arithmetic shift to the left by n bits (n = 0 to 15) m=0 A C b15 ... b0 0 16/8 C1 6 2 40 + + imm imm * * * N * * * * * Z C 32 D1 8 2 40 + + imm imm * * * N * * * * * Z C m=1 AL C b7 ... b0 0 ASLD #n (Note 4) Arithmetic shift to the left by n bits (n = 0 to 31) E C b31 ... b0 0 ASR (Note 1) Arithmetic shift to the right by 1 bit m=0 Acc or M16 b15 ... b0 C 16/8 m=1 AccL or M8 b7 ... b0 C ASR #n (Note 4) Arithmetic shift to the right by n bits (n = 0 to 15) m=0 A b 15 ... b0 C 64 1 1 21 7 3 21 8 3 4A 4B 21 7 4 21 8 4 4E 4F * * * N * * * * * ZC 81 2 2 64 16/8 C1 6 2 80 + + imm imm * * * N * * * * * ZC m=1 AL b7 ... b0 C 21-58 7902 Group User's Manual 7902 Group User's Manual 21-59 APPENDIX APPENDIX Appendix 6. Machine instructions Appendix 6. Machine instructions Addressing Modes Symbol 21-60 Operation length (Bit) Function IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # Addressing Modes Processor Status register ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK MAA 10 9 8 7 6 5 4 3 2 1 0 op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # IPL N V m x D I Z C ASRD #n (Note 4) Arithmetic shift to the right by n bits (n = 0 to 31) E b31 ... b0 C 32 D1 8 2 80 + + imm imm BBC (Note 3) if M(bit n) = 0 then PCPC + cnt + REL (-128 to +127) (cnt: Number of bytes of instruction) 16/8 41 9 5 41 9 6 5A 5E * * * * * * * * * * * BBCB if M8(bit n) = 0 then PCPC + cnt + REL (-128 to +127) (cnt: Number of bytes of instruction) 8 52 8 4 57 8 5 * * * * * * * * * * * BBS (Note 3) if M(bit n) = 1 then PCPC + cnt + REL (-128 to +127) (cnt: Number of bytes of instruction) 16/8 41 9 5 41 9 6 4A 4E * * * * * * * * * * * BBSB if M8(bit n) = 1 then PCPC+cnt+REL (-128 to +127) (cnt: Number of bytes of instruction) 8 42 8 4 47 8 5 * * * * * * * * * * * BCC if C = 0 then PCPC + 2 + REL (-128 to +127) - 90 6 2 * * * * * * * * * * * BCS if C = 1 then PCPC + 2 + REL (-128 to +127) - B0 6 2 * * * * * * * * * * * BEQ if Z = 1 then PCPC + 2 + REL (-128 to +127) - F0 6 2 * * * * * * * * * * * BGE if NV = 0 then PCPC + 2 + REL (-128 to +127) - C0 6 2 * * * * * * * * * * * BGT if Z = 0 and NV = 0 then PCPC + 2 + REL (-128 to +127) - 80 6 2 * * * * * * * * * * * BGTU if C = 1 and Z = 0 then PCPC + 2 + REL (-128 to +127) - 40 6 2 * * * * * * * * * * * BLE if Z = 1 or NV = 1 then PCPC + 2 + REL (-128 to +127) - A0 6 2 * * * * * * * * * * * BLEU if C = 0 or Z = 1 then PCPC + 2 + REL(-128 to +127) - 60 6 2 * * * * * * * * * * * BLT if NV = 1 then PCPC + 2 + REL (-128 to +127) - E0 6 2 * * * * * * * * * * * 7902 Group User's Manual * * * N * * * * * ZC 7902 Group User's Manual 21-61 APPENDIX APPENDIX Appendix 6. Machine instructions Appendix 6. Machine instructions Addressing Modes Symbol 21-62 Operation length (Bit) Function IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # Addressing Modes Processor Status register ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK MAA 10 9 8 7 6 5 4 3 2 1 0 op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # IPL N V m x D I Z C BMI if N = 1 then PCPC + 2 + REL (-128 to +127) - 30 6 2 * * * * * * * * * * * BNE if Z = 0 then PCPC + 2 + REL (-128 to +127) - D0 6 2 * * * * * * * * * * * BPL if N = 0 then PCPC + 2 + REL (-128 to +127) - 10 6 2 * * * * * * * * * * * BRA/BRAL (Note 5) PCPC + cn t + REL (BRA:-128 to +127, BRAL: -32768 to +32767) (cnt: Number of bytes of instruction) PGPG + 1 (When carry occurs) PGPG - 1 (When borrow occurs) - 20 5 2 * * * * * * * * * * * BRK (Note 6) PCPC + 2 M(S)PG SS - 1 M(S)PCH SS - 1 M(S)PCL SS - 1 M(S)PSH SS - 1 M(S)PSL SS - 1 I1 PCLADL PCHADM PG0016 or FF 16 - BSC (Note 7) if A(bit n) or M(bit n) = 0 (n = 0 to 15), then PCPC + cnt + REL (-128 to +127) (cnt: Number of bytes of instruction) BSR (S)PC + 2 PCPC + 2 + REL (-1024 to +1023) BSS (Note 7) if A(bit n) or M(bit n) = 1 (n = 0 to 15), then PCPC + cnt + REL (-128 to +127) (cnt: Number of bytes of instruction) BVC if V = 0 then PCPC + 2 + REL (-128 to +127) - 50 6 2 * * * * * * * * * * * BVS if V = 1 then PCPC + 2 + REL (-128 to +127) - 70 6 2 * * * * * * * * * * * A7 5 3 16/8 00 15 2 74 * * * * * * * *1 * * 01 7 3 71 11 4 A0 A0 + + n n 71 10 5 E + n F8 7 2 | FF - 16/8 * * * * * * * * * * * 01 7 3 71 11 4 80 80 + + n n 7902 Group User's Manual 71 10 5 C0 + n * * * * * * * * * * * * * * * * * * * * * * 7902 Group User's Manual 21-63 APPENDIX APPENDIX Appendix 6. Machine instructions Appendix 6. Machine instructions Addressing Modes Symbol Function if Acc = IMM or M = IMM CBEQ (Notes 1 and then PCPC + cnt + REL(-128 to +127) 3) (cnt: Number of bytes of instruction) CBEQB (Note 1) if AccL = IMM8 or M8 = IMM8 then PCPC + cnt + REL (-128 to +127) (cnt: Number of bytes of instruction) CBNE if Acc IMM or M IMM (Notes 1 and then PCPC + cnt + REL (-128 to 3) +127) (cnt: Number of bytes of instruction) Operation length (Bit) IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # Addressing Modes A6 6 3 41 9 5 6A 16/8 Processor Status register ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK MAA 10 9 8 7 6 5 4 3 2 1 0 op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # IPL N V m x D I Z C * * * NV * * * * Z C 81 7 4 A6 8 A2 6 3 62 8 4 16/8 B6 6 3 41 9 5 7A * * * NV * * * * Z C 81 7 4 A2 * * * NV * * * * Z C 81 7 4 B6 CBNEB (Note 1) if AccL IMM8 or M8 IMM8 then PCPC+cnt+REL(-128 to +127) (cnt: Number of bytes of instruction) 8 CLC C0 - 14 1 1 * * * * * * * * * * 0 CLI I0 - 15 3 1 * * * * * * * * 0 * * CLM m0 - 45 3 1 * * * * * 0 * * * * * CLP PS L(bit n)0 (n = 0 to 7. Multiple bits can be specified.) - CLR (Note 1) Acc0 B2 6 3 72 8 4 * * * NV * * * * Z C 81 7 4 B2 98 4 2 16/8 * * * Specified flag becomes "0." 54 1 1 * * * 0 * * * * * 1 * 81 2 2 54 CLRB (Note 1) Acc L0016 CLRM M0 CLRMB M80016 CLRX X0 16/8 E4 1 1 * * * 0 * * * * * 1 * CLRY Y0 16/8 F4 1 1 * * * 0 * * * * * 1 * 8 44 1 1 * * * 0 * * * * * 1 * 81 2 2 44 21-64 16/8 D2 5 2 D7 5 3 * * * * * * * * * * * 8 C2 5 2 C7 5 3 * * * * * * * * * * * 7902 Group User's Manual 7902 Group User's Manual 21-65 APPENDIX APPENDIX Appendix 6. Machine instructions Appendix 6. Machine instructions Addressing Modes Symbol CLV Function V0 CMP Acc - M (Notes 1 and 2) CMPB (Note 1) Acc L - IMM8 Operation length (Bit) - IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # Addressing Modes Processor Status register ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK MAA 10 9 8 7 6 5 4 3 2 1 0 op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # IPL N V m x D I Z C 65 1 1 16/8 8 * * * * 0 * * * * * * 46 1 2 4A 3 2 4B 4 2 11 6 3 11 7 3 11 7 3 11 8 3 11 9 3 42 40 41 48 49 4E 3 3 4F 4 3 11 5 4 11 5 5 11 6 5 46 4C 4D 11 5 3 11 8 3 43 44 81 2 3 46 81 4 3 81 5 3 4A 4B 91 6 3 91 7 3 91 7 3 91 8 3 91 9 3 40 41 48 49 42 81 4 4 81 5 4 91 5 4 91 5 5 91 6 5 4E 4F 46 4C 4D 91 5 3 91 8 3 43 44 38 1 2 * * * NV * * * * Z C * * * NV * * * * Z C 81 2 3 38 21-66 CMPD E - M32 32 CMPM (Note 3) M - IMM 16/8 51 5 4 23 51 5 5 27 * * * NV * * * * Z C CMPMB M8 - IMM8 8 51 5 4 22 51 5 5 26 * * * NV * * * * Z C CMPMD M32 - IMM32 32 51 7 7 A3 51 7 8 A7 * * * NV * * * * Z C CPX (Note 8) X-M 16/8 E6 1 2 22 3 2 41 4 4 2E * * * NV * * * * Z C CPY (Note 8) Y-M 16/8 F6 1 2 32 3 2 41 4 4 3E * * * NV * * * * Z C DEBNE (Note 4) MM - IMM(IMM = 0 to 31) if M 0, then PCPC + cnt + REL (-128 to +127) (cnt: Number of bytes of instruction) 16/8 C1 12 4 A0 + imm D1 11 5 E0 + imm * * * * * * * * * * * DEC (Note 1) AccAcc - 1 or MM - 1 16/8 B3 1 1 92 6 2 41 8 3 9B 97 6 3 41 8 4 9F * * * N * * * * * Z * DEX XX - 1 16/8 E3 1 1 * * * N * * * * * Z * DEY YY - 1 16/8 F3 1 1 * * * N * * * * * Z * DIV (Notes 2, 9, and 10) A (quotient) (B, A) / M B (remainder) 16/8 3C 3 5 BA 6 2 BB 7 2 11 9 3 11 10 3 11 10 3 11 11 3 11 12 3 B0 B1 B8 B2 B9 BE 6 3 BF 7 3 11 8 4 11 8 5 11 9 5 B6 BC BD 11 8 3 11 11 3 B3 B4 * * * NV * * * * Z C 81 2 2 B3 31 15 3 E7 7902 Group User's Manual 21 16 3 21 17 3 EA EB 21 18 3 21 19 3 21 19 3 21 20 3 21 21 3 E0 E1 E8 E2 E9 21 16 4 21 17 4 21 17 4 21 17 5 21 18 5 EE EF E6 EC ED 21 17 3 21 20 3 E3 E4 7902 Group User's Manual * * * NV * * * I Z C 21-67 APPENDIX APPENDIX Appendix 6. Machine instructions Appendix 6. Machine instructions Addressing Modes Symbol Function Operation length (Bit) IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # Addressing Modes Processor Status register ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK MAA 10 9 8 7 6 5 4 3 2 1 0 op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # IPL N V m x D I Z C DIVS (Notes 2, 9, and 10) A (quotient) (B, A) / M B (remainder) (Signed) 16/8 31 22 3 F7 DXBNE (Note 4) XX - IMM (IMM = 0 to 31) if X 0, then PCPC + cnt + REL (-128 to +127) (cnt: Number of bytes of instruction) 16/8 01 7 3 C0 + imm * * * * * * * * * * * DYBNE (Note 4) YY - IMM (IMM = 0 to 31) if Y0, then PCPC + cnt + REL (-128 to +127) (cnt: Number of bytes of instruction) 16/8 01 7 3 E0 + imm * * * * * * * * * * * 16/8 76 1 2 7A 3 2 7B 4 2 11 6 3 11 7 3 11 7 3 11 8 3 11 9 3 70 71 78 79 72 7E 3 3 7F 4 3 11 5 4 11 5 5 11 6 5 76 7C 7D 11 5 3 11 8 3 73 74 81 2 3 76 81 4 3 81 5 3 7A 7B 91 6 3 91 7 3 91 7 3 91 8 3 91 9 3 70 71 78 79 72 81 4 4 81 5 4 91 5 4 91 5 5 91 6 5 7E 7F 76 7C 7D 91 5 3 91 8 3 73 74 8 33 1 2 EOR AccAccM (Notes 1 and 2) EORB (Note 1) Acc LAccLIMMB 21 23 3 21 24 3 FA FB 21 25 3 21 26 3 21 26 3 21 27 3 21 28 3 F0 F1 F8 F2 F9 21 23 4 21 24 4 21 24 4 21 24 5 21 25 5 FE FF F6 FC FD 21 24 3 21 27 3 F3 F4 * * * NV * * * I Z C * * * N * * * * * Z * * * * N * * * * * Z * 81 2 3 33 16/8 51 7 4 73 51 7 5 77 * * * N * * * * * Z * 8 51 7 4 72 51 7 5 76 * * * N * * * * * Z * M32M32IMM32 32 51 10 7 F3 51 10 8 F7 * * * N * * * * * Z * AccAccL (Extension sign) (Bit 7 of Acc L = 0) b15 b7 b0 00000000 0 AccH Acc L (Bit 7 of Acc L = 1) b15 b7 b0 16 EORM (Note 3) MMIMM EORMB M8M8IMM8 EORMD EXTS (Note 1) 11111111 1 AccH EXTSD 35 1 1 * * * N * * * * * Z * 81 2 2 35 AccL 32 31 5 2 B0 * * * N * * * * * Z * AccAccL (Extension zero) b 15 b8 b7 b0 00000000 AccL AccH 16 34 1 1 * * * 0 * * * * * Z * EEL (= A) (Extension zero) b 15 b0 b15 b0 000016 E H(B) EL(A) 32 EE L(= A) (Extension sign) (Bit 15 of A = 0) b15 b0 b 15 b0 000016 0 E H(B) E L(A) (Bit 15 of A = 1) b15 b0 b 15 b0 FFFF 16 1 E L(A) E H(B) EXTZ (Note 1) EXTZD 21-68 81 2 2 34 31 3 2 A0 7902 Group User's Manual * * * 0 * * * * * Z * 7902 Group User's Manual 21-69 APPENDIX APPENDIX Appendix 6. Machine instructions Appendix 6. Machine instructions Addressing Modes Symbol INC (Note 1) Function Operation length (Bit) IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # Addressing Modes Processor Status register ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK MAA 10 9 8 7 6 5 4 3 2 1 0 op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # IPL N V m x D I Z C 87 6 3 41 8 4 8F AccAcc + 1 or MM + 1 16/8 A3 1 1 82 6 2 41 8 3 8B INX XX + 1 16/8 C3 1 1 * * * N * * * * * Z * INY YY + 1 16/8 D3 1 1 * * * N * * * * * Z * JMP/JMPL When ABS specified PCLADL PCHADM * * * N * * * * * Z * 81 2 2 A3 - 9C 4 3 AC 5 4 31 7 4 31 9 4 BC 7 3 5C 5D * * * * * * * * * * * - 9D 6 3 AD 7 4 BD 8 3 * * * * * * * * * * * When ABL specified PCLADL PCHADM PGADH When (ABS) specified PCL(ADM, ADL) PCH(ADM, ADL + 1) When L(ABS) specified PCL(ADM, ADL) PCH(ADM, ADL + 1) PG(ADM, ADL + 2) When (ABS,X) specified PCL(ADM, ADL + X) PCH(ADM, ADL + X + 1) JSR/JSRL When ABS specified M(S)PCH SS-1 M(S)PCL SS-1 PCLADL PCHADM When ABL specified M(S)PG SS - 1 M(S)PCH SS - 1 M(S)PCL SS - 1 PCLADL PCHADM PGADH When (ABS,X) specified M(S)PCH SS - 1 M(S)PCL SS - 1 PCL(ADM, AD L + X) PCH(ADM, ADL + X + 1) LDA AccM (Notes 1 and 2) LDAB (Note 1) 21-70 AccM8 (Extension zero) 16/8 16 16 1 2 1A 3 2 1B 4 2 11 6 3 11 7 3 18 6 2 11 8 3 19 8 2 11 12 10 1E 3 3 1F 4 3 11 5 4 1C 4 4 1D 5 4 16 11 5 3 11 8 3 13 14 81 2 3 16 81 4 3 81 5 3 1B 1A 91 6 3 91 7 3 81 7 3 91 8 3 81 9 3 10 11 18 19 12 81 4 4 81 5 4 91 5 4 81 5 5 81 6 5 1E 16 1C 1D 1F 91 5 3 91 8 3 13 14 28 1 2 0A 3 2 0B 4 2 11 6 3 11 7 3 08 6 2 11 8 3 09 8 2 00 01 02 0E 3 3 0F 4 3 11 5 4 0C 4 4 0D 5 4 06 11 5 3 11 8 3 03 04 81 2 3 28 81 4 3 81 5 3 0A 0B 91 6 3 91 7 3 81 7 3 91 8 3 81 9 3 01 08 09 00 02 81 4 4 81 5 4 91 5 4 81 5 5 81 6 5 0E 0F 06 0C 0D 91 5 3 91 8 3 03 04 7902 Group User's Manual 7902 Group User's Manual * * * N * * * * * Z * * * * 0 * * * * * Z * 21-71 APPENDIX APPENDIX Appendix 6. Machine instructions Appendix 6. Machine instructions Addressing Modes Symbol Function Operation length (Bit) IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # LDAD EM32 32 2C 3 5 LDD n (Notes 11 and 12) DPRnIMM16 (n = 0 to 3. Multiple DPRs can be specified.) 16 B8 13 4 ?0 LDT DTIMM8 8 31 4 3 4A LDX (Note 8) XM 16/8 C6 1 2 LDXB XIMM8 (Extension zero) 16 27 1 2 LDY (Note 8) YM 16/8 D6 1 2 LDYB YIMM8 (Extension zero) 16 37 1 2 LSR (Note 1) Logical shift to the right by 1 bit 16/8 m=0 Acc or M16 0 b15 ... b0 C Logical shift to the right by n bits (n = 0 to 15) 11 9 3 11 10 3 88 9 2 11 11 3 89 11 2 80 81 82 Processor Status register 8E 6 3 8F 7 3 11 8 4 8C 7 4 8D 8 4 86 11 8 3 11 11 3 83 84 * * * N * * * * * Z * * * * * * * * * * * * B8 11 2 ?0 + + 2i 2i * * * * * * * * * * * 02 3 2 41 5 3 05 07 3 3 41 5 4 06 * * * N * * * * * Z * * * * 0 * * * * * Z * 12 3 2 41 5 3 1B 17 3 3 41 5 4 1F * * * N * * * * * Z * * * * 0 * * * * * Z * 43 1 1 21 7 3 21 8 3 2A 2B 21 7 4 21 8 4 2E 2F * * * 0 * * * * * Z C 81 2 2 43 m=1 AccL or M8 0 b7 ... b0 C LSR #n (Note 4) 8A 6 2 8B 7 2 Addressing Modes ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK MAA 10 9 8 7 6 5 4 3 2 1 0 op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # IPL N V m x D I Z C 16/8 C1 6 2 + imm * * * 0 * * * * * Z C 32 D1 8 2 + imm * * * 0 * * * * * Z C m=0 A 0 b15 ... b0 C m=1 AL 0 b7 ... b0 C LSRD #n (Note 4) 21-72 Logical shift to the right by n bits (n = 0 to 31) E 0 b31 ... b0 C 7902 Group User's Manual 7902 Group User's Manual 21-73 APPENDIX APPENDIX Appendix 6. Machine instructions Appendix 6. Machine instructions Destination Symbol MOVM (Note 2) Function m=0 M16(dest)M16(source) Operation length (Bit) IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 16/8 IMM DIR Source m=1 M8(dest)M8(source) ABS, X MOVMB M8(dest)M8(source) 8 IMM Source DIR ABS, X ... ... M8(dest1) M8(source1) Source Source 7C 5 5 A9 5 3 31 7 4 3A B9 4 4 31 6 5 3B 48 6 3 68 5 4 6C 5 5 4D 7 4 * * * * * * * * * * * 71 3 2 70 + + + 6n 3n n DIR, X ABS 61 3 2 90 + + + 6n 3n n ABS, X 71 3 2 10 + + + 6n 3n n IMM 61 3 2 00 + + + 5n 2n n 61 3 2 20 + + + 4n 3n n DIR 61 3 2 40 + + + 6n 2n n 61 3 2 60 + + + 5n 3n n 61 3 2 B0 + + + 5n 4n n * * * * * * * * * * * 71 3 2 60 + + + 6n 3n n DIR, X ABS 61 3 2 80 + + + 6n 3n n ABS, X 71 3 2 00 + + + 6n 3n n 7902 Group User's Manual * * * * * * * * * * * 69 6 4 4C 6 4 61 3 2 70 + + + 5n 3n n (n = to 15) * * * * * * * * * * * 5D 7 4 61 3 2 50 + + + 6n 2n n M8(dest n)M8(source n) 21-74 5C 6 4 DIR 8 ... ... MOVRB (Note 7) Processor Status register 79 6 4 61 3 2 30 + + + 4n 3n n ... ... M8(dest n)M8(source n) 78 5 4 61 3 2 10 + + + 5n 2n n M16(dest n)M16(source n) (n = 0 to 15) 58 6 3 IMM 16/8 m=1 M8(dest1) M8(source1) 96 4 4 31 6 5 57 DIR, X ABS MOVR m=0 (Notes 7 and M16(dest1) M16(source1) 13) 86 5 3 31 7 4 47 DIR, X ABS Destination ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK MAA 10 9 8 7 6 5 4 3 2 1 0 op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # IPL N V m x D I Z C 61 3 2 A0 + + + 5n 4n n 7902 Group User's Manual 21-75 APPENDIX APPENDIX Appendix 6. Machine instructions Appendix 6. Machine instructions Addressing Modes Symbol Operation length (Bit) Function IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # Addressing Modes Processor Status register ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK MAA 10 9 8 7 6 5 4 3 2 1 0 op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # IPL N V m x D I Z C MPY (B, A)A M (Notes 2 and 14) 16/8 31 8 3 C7 21 9 3 21 10 3 CB CA 21 11 3 21 12 3 21 12 3 21 13 3 21 14 3 C9 C0 C1 C8 C2 21 9 4 21 10 4 21 10 4 21 10 5 21 11 5 CC CE CF C6 CD 21 10 3 21 13 3 C3 C4 * * * N * * * * * Z 0 MPYS (B, A)A M (Signed) (Notes 2 and 14) 16/8 31 8 3 D7 21 9 3 21 10 3 DB DA 21 11 3 21 12 3 21 12 3 21 13 3 21 14 3 D9 D0 D1 D8 D2 21 9 4 21 10 4 21 10 4 21 10 5 21 11 5 DD DE DF D6 DC 21 10 3 21 13 3 D3 D4 * * * N * * * * * Z 0 MVN (Note 15) 16/8 31 5 4 2B + 5i * * * * * * * * * * * 16/8 31 9 4 2A + 5i * * * * * * * * * * * M(Y + k)M(X + k) k = 0 to i - 1 i: Number of transfer bytes specified by accumulator A ( MVP (Note 16) M(Y-k)M(X-k) k = 0 to i-1 i: Number of transfer bytes specified by accumulator A ( NEG (Note 1) ) ) Acc -Acc 16/8 24 1 1 * * * NV * * * * Z C 81 2 2 24 NEGD NOP E -E PCPC + 1 32 - 31 4 2 80 * * * NV * * * * Z C 74 1 1 * * * * * * * * * * * When catty occurs in PC PGPG + 1 ORA AccAcc M (Notes 1 and 2) ORAB (Note 1) Acc LAccL IMM8 16/8 8 56 1 2 5A 3 2 5B 4 2 11 6 3 11 7 3 11 7 3 11 8 3 11 9 3 59 50 51 58 52 5E 3 3 5F 4 3 11 5 4 11 5 5 11 6 5 56 5C 5D 11 5 3 11 8 3 53 54 81 2 3 56 81 4 3 81 5 3 5A 5B 91 6 3 91 7 3 91 7 3 91 8 3 91 9 3 59 50 51 58 52 81 4 4 81 5 4 91 5 4 91 5 5 91 6 5 56 5C 5D 5E 5F 91 5 3 91 8 3 53 54 63 1 2 * * * N * * * * * Z * * * * N * * * * * Z * 81 2 3 63 ORAM (Note 3) 21-76 MM IMM ORAMB M8M8 IMM8 ORAMD M32M32 IMM32 16/8 51 7 4 33 51 7 5 37 * * * N * * * * * Z * 8 51 7 4 32 51 7 5 36 * * * N * * * * * Z * 32 51 10 7 B3 51 10 8 B7 * * * N * * * * * Z * PEA M(S)IMM H SS - 1 M(S)IMM L SS - 1 16 31 5 4 4C * * * * * * * * * * * PEI M(S)M((DPRn) + dd + 1) SS + 1 M(S)M((DPRn)+dd) SS - 1 (n = 0 to 3) 16 31 7 3 4B * * * * * * * * * * * 7902 Group User's Manual 7902 Group User's Manual 21-77 APPENDIX APPENDIX Appendix 6. Machine instructions Appendix 6. Machine instructions Addressing Modes Symbol Function PER EARPC + IMM16 M(S)EARH SS - 1 M(S)EARL SS - 1 PHA m=0 M(S)AH SS - 1 M(S)AL SS - 1 Operation length (Bit) IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # Addressing Modes Processor Status register ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK MAA 10 9 8 7 6 5 4 3 2 1 0 op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # IPL N V m x D I Z C 16 31 6 4 4D * * * * * * * * * * * 16/8 85 4 1 * * * * * * * * * * * 16/8 81 5 2 85 * * * * * * * * * * * m=1 M(S)AL SS - 1 PHB m=0 M(S)BH SS - 1 M(S)BL SS - 1 m=1 M(S)BL SS - 1 PHD M(S)DPR0H SS - 1 M(S)DPR0L SS - 1 16 83 4 1 * * * * * * * * * * * PHD n (Note 11) M(S)DPRnH SS - 1 M(S)DPRnL SS - 1 16 B8 12 2 01 0F * * * * * * * * * * * (n = 0 to 3) When multiple DPRs are specified, the above operations are repeated. PHG M(S)PG SS - 1 PHLD n (Note 11) M(S)DPRnH SS - 1 M(S)DPRnL SS - 1 DPRnIMM16 B8 11 2 01 + | i 0F 8 31 4 2 60 * * * * * * * * * * * 16 B8 14 4 01 | 0F * * * * * * * * * * * (n = 0 to 3) B8 11 2 01 + + | 3i 2i 0F When multiple DPRs are specified, the above operations are repeated. 21-78 PHP M(S)PSH SS - 1 M(S)PSL SS - 1 16 A5 4 1 * * * * * * * * * * * PHT M(S)DT SS - 1 8 31 4 2 40 * * * * * * * * * * * 7902 Group User's Manual 7902 Group User's Manual 21-79 APPENDIX APPENDIX Appendix 6. Machine instructions Appendix 6. Machine instructions Addressing Modes Symbol Function x=0 M(S)XH SS - 1 M(S)XL SS - 1 Operation length (Bit) IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # Addressing Modes Processor Status register ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK MAA 10 9 8 7 6 5 4 3 2 1 0 op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # IPL N V m x D I Z C 16/8 C5 4 1 * * * * * * * * * * * 16/8 E5 4 1 * * * * * * * * * * * 16/8 95 4 1 * * * N * * * * * Z * 16/8 81 5 2 95 * * * N * * * * * Z * SS + 1 DPR0 LM(S) SS + 1 DPR0 HM(S) 16 93 5 1 * * * * * * * * * * * PLD n SS + 1 (Notes 11 and DPRnLM(S) 12) SS + 1 DPRnHM(S) 16 77 11 2 ?0 * * * * * * * * * * * PHX x=1 M(S)XL SS - 1 PHY x=0 M(S)YH SS - 1 M(S)YL SS - 1 x=1 M(S)YL SS - 1 PLA m=0 SS + 1 A LM(S) SS + 1 A HM(S) m=1 SS + 1 A LM(S) PLB m=0 SS + 1 B LM(S) SS + 1 B HM(S) m=1 SS + 1 B LM(S) PLD (n = 0 to 3) 77 8 2 ?0 + 3i When multiple DPRs are specified, the above operations are repeated. 21-80 PLP (Note 22) SS + 1 PS LM(S) SS + 1 PS HM(S) PLT SS + 1 DTM(S) 16 B5 5 1 8 31 6 2 50 7902 Group User's Manual 7902 Group User's Manual Value restored from stack * * * N * * * * * Z * 21-81 APPENDIX APPENDIX Appendix 6. Machine instructions Appendix 6. Machine instructions Addressing Modes Symbol PLX Function x=0 SS + 1 X LM(S) SS + 1 X HM(S) Operation length (Bit) IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # Addressing Modes Processor Status register ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK MAA 10 9 8 7 6 5 4 3 2 1 0 op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # IPL N V m x D I Z C 16/8 D5 4 1 * * * N * * * * * Z * 16/8 F5 4 1 * * * N * * * * * Z * x=1 SS + 1 X LM(S) PLY x=0 SS + 1 Y LM(S) SS + 1 Y HM(S) x=1 SS + 1 Y LM(S) PSH (Note 17) M(S to S - i + 1)A, B, X... SS - i i: Number of bytes corresponding to register pushed on stack 16/8 A8 11 2 + 2i 1 + i 2 * * * * * * * * * * * PUL (Notes 18 and 22) A, B, X...M(S + 1 to S + i) SS + i i: Number of bytes corresponding to register restored from stack 16/8 67 13 2 + 3 i1 When the contents of PS is restored, this becomes the value. In the other cases, nothing changes. RLA (Note 3) Rotate to the left by n bits m=0 16/8 (n = 0 to 65535) 31 5 3 07 + n * * * * * * * * * * * A b 15 ... b0 m=1 (n = 0 to 255) AL b7 ... b0 RMPA (Note 19) m=0 Repeat (B, A)(B, A) + M(DT:X) M(DT:Y) (Signed) XX + 2 YY + 2 ii - 1 Until i = 0 16/8 31 5 3 * * * N V * * * * Z C 5A + 14 imm m=1 Repeat (BL, AL)(BL, AL)+M(DT,X) M(DT,Y) (Signed) XX + 1 YY + 1 ii - 1 Until i = 0 i: Numder of repetitions (0 to 255) 21-82 7902 Group User's Manual 7902 Group User's Manual 21-83 APPENDIX APPENDIX Appendix 6. Machine instructions Appendix 6. Machine instructions Addressing Modes Symbol ROL (Note 1) Function Rotate to the left by 1 bit Operation length (Bit) 16/8 m=0 Acc or M16 b15 ... b0 C m=1 AccL or M8 b7 ... b0 C ROL #n (Note 4) Rotate to the left by n bits (n = 0 to 15) m=0 A b 15 ... b0 C IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # 13 1 1 21 7 3 21 8 3 1A 1B Addressing Modes Processor Status register ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK MAA 10 9 8 7 6 5 4 3 2 1 0 op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # IPL N V m x D I Z C 21 7 4 21 8 4 1E 1F * * * N * * * * * Z C 81 2 2 13 16/8 C1 6 2 60 + + imm imm * * * N * * * * * ZC 32 D1 8 2 60 + + imm imm * * * N * * * * * Z C m=1 AL b 7 ... b0 C ROLD #n (Note 4) Rotate to the left by n bits (n = 0 to 31) E b 31 ... b0 C ROR (Note 1) Rotate to the right by 1 bit 16/8 m=0 53 1 1 21 7 3 21 8 3 3B 3A 21 7 4 21 8 4 3E 3F * * * N * * * * * Z C Acc or M16 C b15 ... b0 m=1 81 2 2 53 AccL or M8 C b7 ... b0 ROR #n (Note 4) Rotate to the right by n bits (n = 0 to 15) 16/8 C1 6 2 20 + + imm imm * * * N * * * * * Z C 32 D1 8 2 20 + + imm imm * * * N * * * * * Z C m=0 A C b15 ... b0 m=1 AL C b7 ... b0 RORD #n (Note 4) Rotate to the right by n bits (n = 0 to 31) E b 31 ... b0 C 21-84 7902 Group User's Manual 7902 Group User's Manual 21-85 APPENDIX APPENDIX Appendix 6. Machine instructions Appendix 6. Machine instructions Addressing Modes Symbol Function Operation length (Bit) IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # Addressing Modes Processor Status register ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK MAA 10 9 8 7 6 5 4 3 2 1 0 op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # IPL N V m x D I Z C RTI SS + 1 PSLM(S) SS + 1 PSHM(S) SS + 1 PCLM(S) SS + 1 PCHM(S) SS + 1 PGM(S) - F1 12 1 Value restored from stack RTL SS + 1 PCLM(S) SS + 1 PCHM(S) SS + 1 PGM(S) - 94 10 1 * * * * * * * * * * * RTLD n SS + 1 (Notes 11 and DPRn LM(S) 12) SS + 1 DPRn HM(S) SS + 1 PCLM(S) SS + 1 PCHM(S) SS + 1 PGM(S). (n = 0 to 3. Multiple DPRs can be specified.) RTS SS + 1 PCLM(S) SS + 1 PCHM(S) SS + 1 RTSD n (Notes 11 and DPRn LM(S) SS + 1 12) DPRn HM(S) SS + 1 PCLM(S) SS + 1 PCHM(S), (n = 0 to 3. Multiple DPRs can be specified.) SBC AccAcc - M - C (Notes 1 and 2) SBCB (Note 1) AccL Acc L - IMM8 - C 16 77 15 2 ?C * * * * * * * * * * * 77 12 2 ?C + 3i - 84 7 1 * * * * * * * * * * * 16 77 14 2 ?8 * * * * * * * * * * * 77 11 2 ?8 + 3i 16/8 31 3 3 A7 21 5 3 21 6 3 AA AB 21 7 3 21 8 3 21 8 3 21 9 3 21 10 3 A0 A1 A8 A2 A9 21 5 4 21 6 4 21 6 4 21 6 5 21 7 5 AE AF A6 AC AD 21 6 3 21 9 3 A3 A4 B1 3 3 A7 A1 7 3 A1 8 3 AA AB A1 9 3 A1 10 3 A1 10 3 A1 11 3 A1 12 3 A0 A1 A8 A2 A9 A1 7 4 A1 8 4 A1 8 4 A1 8 5 A1 9 5 AE AF A6 AD AC A1 8 3 A1 11 3 A3 A4 8 31 3 3 1B * * * NV * * * * Z C * * * NV * * * * Z C B1 3 3 1B 21-86 32 SBCD EE - M32 - C 31 4 6 1D SEC C1 - 04 1 1 * * * * * * * * * * 1 SEI I1 - 05 4 1 * * * * * * * * 1 * * 7902 Group User's Manual 21 7 3 21 8 3 BA BB 21 9 3 21 10 3 21 10 3 21 11 3 21 12 3 B0 B1 B2 B9 B8 21 7 4 21 8 4 21 8 4 21 8 5 21 9 5 BE BF B6 BC BD 21 8 3 21 11 3 B3 B4 7902 Group User's Manual * * * N V * * * * Z C 21-87 APPENDIX APPENDIX Appendix 6. Machine instructions Appendix 6. Machine instructions Addressing Modes Symbol Function Operation length (Bit) SEM m1 - SEP PS L(bit n)1 (n = 0, 1, 3 to 7. Multiple bits can be specified.) - STA (Note 1) MAcc IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # Processor Status register 25 3 1 * * * * * 1 * * * * * 99 3 2 * * * Specified flag becomes "1" (Note 21). DA 4 2 DB 5 2 11 7 3 11 8 3 D8 7 2 11 9 3 D9 9 2 D0 D1 D2 DE 4 3 DF 5 3 11 6 4 DC 5 4 DD 6 4 D6 11 6 3 11 9 3 D3 D4 81 5 3 81 6 3 DA DB 91 7 3 91 8 3 81 8 3 91 9 3 81 10 3 D9 D0 D1 D8 D2 81 5 4 81 6 4 91 6 4 81 6 5 81 7 5 DE DF D6 DC DD 91 6 3 91 9 3 D3 D4 8 CA 4 2 CB 5 2 11 7 3 11 8 3 C8 7 2 11 9 3 C9 9 2 C0 C1 C2 CE 4 3 CF 5 3 11 6 4 CC 5 4 CD 6 4 C6 11 6 3 11 9 3 C3 C4 81 5 3 81 6 3 CA CB 91 7 3 91 8 3 81 8 3 91 9 3 81 10 3 C9 C8 C2 C0 C1 81 5 4 81 6 4 91 6 4 81 6 5 81 7 5 CE CF C6 CC CD 91 6 3 91 9 3 C3 C4 32 EA 6 2 EB 7 2 11 9 3 11 10 3 E8 9 2 11 11 3 E9 11 2 E0 E1 E2 EE 6 3 EF 7 3 11 8 4 EC 7 4 ED 8 4 E6 11 8 3 11 11 3 E3 E4 16/8 STAB (Note 1) M8AccL STAD M32E STP Oscillation stopped STX MX 16/8 E2 4 2 STY MY 16/8 F2 4 2 41 6 3 FB SUB AccAcc - M (Notes 1 and 2) Addressing Modes ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK MAA 10 9 8 7 6 5 4 3 2 1 0 op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # IPL N V m x D I Z C - 16/8 31 - 2 30 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 41 6 3 F5 E7 4 3 * * * * * * * * * * * F7 4 3 * * * * * * * * * * * 36 1 2 3A 3 2 3B 4 2 11 6 3 11 7 3 11 7 3 11 8 3 11 9 3 39 31 38 32 30 3E 3 3 3F 4 3 11 5 4 11 5 5 11 6 5 36 3C 3D 11 5 3 11 8 3 33 34 81 2 3 36 81 4 3 81 5 3 3A 3B 91 6 3 91 7 3 91 7 3 91 8 3 91 9 3 39 31 38 32 30 81 4 4 81 5 4 91 5 4 91 5 5 91 6 5 3E 3F 36 3C 3D 91 5 3 91 8 3 34 33 * * * NV * * * * ZC SUBB (Note 1) Acc LAccL - IMM8 SUBD EE - M32 32 SUBM (Note 3) MM - IMM 16/8 51 7 4 13 51 7 5 17 * * * NV * * * * Z C SUBMB M8M8 - IMM8 8 51 7 4 12 51 7 5 16 * * * NV * * * * Z C SUBMD M32M32 - IMM32 32 51 10 7 93 51 10 8 97 * * * NV * * * * Z C 8 39 1 2 * * * NV * * * * Z C 81 2 3 39 21-88 3D 3 5 7902 Group User's Manual AA 6 2 AB 7 2 11 9 3 11 10 3 11 10 3 11 11 3 11 12 3 A0 A1 A8 A2 A9 AE 6 3 AF 7 3 11 8 4 11 8 5 11 9 5 A6 AC AD 11 8 3 11 11 3 A3 A4 7902 Group User's Manual * * * NV * * * * Z C 21-89 APPENDIX APPENDIX Appendix 6. Machine instructions Appendix 6. Machine instructions Addressing Modes Symbol 21-90 Function SUBS SS - IMM8 SUBX (Note 4) Operation length (Bit) IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # Addressing Modes Processor Status register ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK MAA 10 9 8 7 6 5 4 3 2 1 0 op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # IPL N V m x D I Z C 16 31 2 3 0B * * * NV * * * * Z C XX - IMM (IMM = 0 to 31) 16/8 01 2 2 40 + imm * * * NV * * * * ZC SUBY (Note 4) YY - IMM (IMM = 0 to 31) 16/8 01 2 2 60 + imm * * * NV * * * * Z C TAD n (Note 20) DPRnA (n = 0 to 3) 16 31 3 2 n2 * * * * * * * * * * * TAS SA 16 31 2 2 82 * * * * * * * * * * * TAX XA 16/8 C4 1 1 * * * N * * * * * Z * TAY YA 16/8 D4 1 1 * * * N * * * * * Z * TBD n (Note 20) DPRnB (n = 0 to 3) 16 B1 3 2 n2 * * * * * * * * * * * TBS SB 16 B1 2 2 82 * * * * * * * * * * * TBX XB 16/8 81 2 2 C4 * * * N * * * * * Z * TBY YB 16/8 81 2 2 D4 * * * N * * * * * Z * TDA n (Note 20) ADPRn (n = 0 to 3) 16/8 31 2 2 40 + n2 * * * N * * * * * Z * TDB n (Note 20) BDPRn (n = 0 to 3) 16/8 B1 2 2 40 + n2 * * * N * * * * * Z * TDS SDPR0 16 31 2 2 73 * * * * * * * * * * * 7902 Group User's Manual 7902 Group User's Manual 21-91 APPENDIX APPENDIX Appendix 6. Machine instructions Appendix 6. Machine instructions Addressing Modes Symbol 21-92 Function Operation length (Bit) IMP IMM A DIR DIR, X DIR, Y (DIR) (DIR, X) (DIR), Y L(DIR) L(DIR), Y op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # Addressing Modes Processor Status register ABS ABS, X ABS, Y ABL ABL, X (ABS) L(ABS) (ABS, X) STK REL DIR, b, R ABS, b, R SR (SR), Y BLK MAA 10 9 8 7 6 5 4 3 2 1 0 op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # op n # IPL N V m x D I Z C TSA AS 16/8 31 2 2 92 * * * N * * * * * Z * TSB BS 16/8 B1 2 2 92 * * * N * * * * * Z * TSD DPR0S 16 31 4 2 70 * * * * * * * * * * * TSX XS 16/8 31 2 2 F2 * * * N * * * * * Z * TXA AX 16/8 A4 1 1 * * * N * * * * * Z * TXB BX 16/8 81 2 2 A4 * * * N * * * * * Z * TXS SX 16/8 31 2 2 E2 * * * * * * * * * * * TXY YX 16/8 31 2 2 C2 * * * N * * * * * Z * TYA AY 16/8 B4 1 1 * * * N * * * * * Z * TYB BY 16/8 81 2 2 B4 * * * N * * * * * Z * TYX XY 16/8 31 2 2 D2 * * * N * * * * * Z * WIT CPU clock stopped - 31 - 2 10 * * * * * * * * * * * XAB A B 16/8 55 2 1 * * * N * * * * * Z * 7902 Group User's Manual 7902 Group User's Manual 21-93 APPENDIX APPENDIX Appendix 6. Machine instructions Notes for machine instructions table The table lists the minimum number of instruction cycles for each instruction. The number of cycle is changed by the following condition. * The value of the low-order bytes of DPR (DPRnL ) The number of cycle of the addressing mode related with DPRn (n = 0 to 3) is applied when DPRn = 0. When DPRn 0, add 1 to the number of cycles. * The number of bytes of instruction which fetched into the instruction queue buffer * The address at read and write of memory (either even or odd) * When the external area accessed in BYTE = Vcc level (at external data bus width 8 bits) * The number of wait Note 1. The op code at the upper row is used for accumulator A, and the op code at the lower row is used for accumulator B. Note 2. When handing 16-bit data with flag m = 0 in the immediate addressing mode, add 1 to the numder of bytes. Note 3. When handing 16-bit data with flag m = 0, add 1 to the numder of bytes. Note 4. Imm is the immediate value specified with an operand (imm = 0-31). Note 5. The op code at the upper row is used for branching in the range of -128 to +127, and the op code at the lower row is used for branching in the range of -32768 to +32767. Note 6. The BRK instruction is a instruction for debugger; it cannot be used. Note 7. Any value from 0 through 15 is placed in an "n." Note 8. When handling 16-bit data with flag x = 0 in the immediate addressing mode, add 1 to the numder of bytes. Note 9. The number of cycles is the case of the 16-bit / 8-bit operation. In the case of the 32-bit / 16-bit operation, add 8 to the number of cycles. Appendix 6. Machine instructions Note 15. The number of cycles is the case where the number of bytes to be transferred (i) is even. When the number of bytes to be transferred (i) is odd, the number is calculated as; 5 i + 10 Note 16. The number of cycles is the case where the number of bytes to be transferred (i) is even. When the number of bytes to be transferred (i) is odd, the number is calculated as; 5 i + 14 Note that it is 10 cycles in the case of 1-byte thanster. Note 17. i 1 is the number of registers to be stored among A, B, X, Y, DPR0, and PS. i 2 is the number of registers to be stored between DT and PG. Note 18. Letter "i 1" indicates the number of registers to be restored. Note 19. The number of cycles is applied when flag m = "1." When flag m="0," the number is calculated as; 18 imm + 5 Note 20. Any value from 0 through 3 is placed in an "n" in op code." Note 21. Do not use the SEP instruction to specify flag I. (When setting flag I to "1," be sure to use the SEI instruction.) Note 22. Be sure to keep flag I = "1" when executing the PLP or PUL instruction. Also, be sure to use the SEI instruction when setting flag I to "1." Note 10. When a zero division interrupt occurs, the number of cycles is 16 cycles. It is regardless of the data length. Note 11. When placing a value in any of DPRs, the op code at the upper row is applied. When placing values to multiple DPRs, the op code at the lower row is applied. The letter "i" represents the number of DPRn specified: 1 to 4. Note 12. A "?" indicates to the value of 4 bits which the bit corressing to the specified DPRn becomes "1." Note 13. When the source is in the immediate addressing mode and flag m = 0, add n (n = 0 to 15) to the number of bytes. Note 14. The number of cycles of the case of the 8-bit 8-bit operation. In the case of the 16-bit 16-bit operation, add 4 to the number of cycles. 21-94 7902 Group User's Manual 7902 Group User's Manual 21-95 APPENDIX Appendix 7. Countermeasure against noise Appendix 7. Countermeasure against noise General countermeasure examples against noise are described below. Although the effect of these countermeasure depends on each system. The user shall modify them according to the actual application and test them. 1. Short wiring length The wiring on a printed circuit board may function as an antenna which feeds noise into the microcomputer. The shorter the total wiring length (by mm unit), the less possibility of noise insertion into the microcomputer. ______ (1) Wiring for RESET pin ______ Make the length of wiring connected to the RESET pin as short as possible. ______ In particular, connect a capacitor between the RESET pin and the Vss pin with the shortest possible wiring (within 20 mm). ______ Reason: If noise is input to the RESET pin, the microcomputer restarts operation before the internal state of the microcomputer is completely initialized. This may cause a program runaway. Noise Reset circuit Vss M37902 M37902 Reset circuit RESET RESET Vss Vss Vss Not acceptable Acceptable ______ Fig. 3 Wiring for RESET pin (2) Wiring for clock input/output pins Make the length of wiring connected to the clock input/output pins as short as possible. Make the length of wiring between the grounding lead of the capacitor, which is connected to the oscillator, and the Vss pin of the microcomputer, as short as possible (within 20 mm). Separate the Vss pattern for oscillation from all other Vss patterns. (Refer to "Figure 11.") Reason: The microcomputer's operation synchronizes with a clock generated by the oscillation circuit. If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a malfunction or a program runaway. Also, if the noise causes a potential difference between the Vss level of the microcomputer and the Vss level of an oscillator, the correct clock will not be input in the microcomputer. Noise M37902 M37902 XIN XOUT Vss XIN XOUT Vss Not acceptable Acceptable Fig. 4 Wiring for clock input/output pins 21-96 7902 Group User's Manual APPENDIX Appendix 7. Countermeasure against noise (3) Wiring for MD0 and MD1 pins Connect MD0 and MD1 pins to the Vss pin (or Vcc pin) with the shortest possible wiring. Reason: The processor mode of the microcomputer is influenced by a potential at the MD0 and MD1 pins when the MD0 and MD1 pins and the Vss pin (or Vcc pin) are connected. If the noise causes a potential difference between the MD0 and MD1 pins and the Vss pin (or Vcc pin), the processor mode may become unstable. This may cause a microcomputer malfunction or a program runaway. M37902 Noise M37902 MD1 MD1 MD0 MD0 Vss Vss Not Acceptable Acceptable Fig. 5 Wiring for MD0 and MD1 pins 2. Connection of bypass capacitor between Vss and Vcc lines Connect an approximate 0.1 F bypass capacitor as follows: Connect a bypass capacitor between the Vss and Vcc pins, at equal lengths. The wiring connecting the bypass capacitor between the Vss and Vcc pins should be as short as possible. Use thicker wiring for the Vss and Vcc lines than that for the other signal lines. Bypass capacitor AA AA AA AA AA AA Wiring pattern Wiring pattern Vcc Vss M37902 Fig. 6 Bypass capacitor between Vss and Vcc lines 7902 Group User's Manual 21-97 APPENDIX Appendix 7. Countermeasure against noise 3. Wiring for analog input pins, analog power source pins, etc. (1) Processing for analog input pins Connect a resistor to the analog signal line, which is connected to an analog input pin, in series. Additionally, connect the resistor to the microcomputer as close as possible. Connect a capacitor between the analog input pin and the AVss pin, as close to the AVss pin as possible. Reason: A signal which is input to the analog input pin is usually an output signal from a sensor. The sensor, which detects changes in status, is installed far from the microcomputer's printed circuit board. Therefore, this long wiring between them becomes an antenna which picks up noise and feeds it into the microcomputer's analog input pin. If a capacitor between an analog input pin and the AVss pin is grounded far away from the AVss pin, noise on the GND line may enter the microcomputer through the capacitor. Noise (Note 2) Acceptable M37902 RI ANi Thermistor Acceptable Not acceptable CI AVss Reference values RI : Approximate 100 to 1000 CI : Approximate 100 pF to 1000 pF Notes 1: Design an external circuit for the ANi pin so that charge/discharge is available within 1 cycle of AD. 2: This resistor and thermistor are used to divide resistance. Fig. 7 Countermeasure example against noise for analog input pin using thermistor 21-98 7902 Group User's Manual APPENDIX Appendix 7. Countermeasure against noise (2) Processing for analog power source pins, etc. Use independent power sources for the Vcc, AVcc and VREF pins. Insert capacitors between the AVcc and AVss pins, and between the VREF and AVss pins. Reasons: Prevents the A-D converter from noise on the Vcc line. M37902 Reference values C1 0.47 F AVcc C2 0.47 F VREF C1 C2 Note : Connect capacitors using the thickest, shortest wiring possible. AVss ANi (sensor, etc.) Fig. 8 Processing for analog power source pins, etc. 7902 Group User's Manual 21-99 APPENDIX Appendix 7. Countermeasure against noise 4. Oscillator protection The oscillator, which generates the basic clock for the microcomputer operations, must be protected from the affect of other signals. (1) Distance oscillator from signal lines with large current flows Install the microcomputer, especially the oscillator, as far as possible from signal lines which handle currents larger than the microcomputer current value tolerance. Reason: The microcomputer is used in systems which contain signal lines for controlling motors, LEDs, thermal heads, etc. Noise occurs due to mutual inductance when a large current flows through the signal lines. M37902 Mutual inductance M XIN XOUT Vss Large current Fig. 9 Wiring for signal lines where large current flows (2) Distance oscillator from signal lines with frequent potential level changes Install an oscillator and its wiring pattern away from signal lines where potential levels change frequently. Do not cross these signal lines over the clock-related or noise-sensitive signal lines. Reason: Signal lines with frequently changing potential levels may affect other signal lines at a rising or falling edge. In particular, if the lines cross over a clock-related signal line, clock waveforms may be deformed, which causes a microcomputer malfunction or a program runaway. M37902 Do not cross. XIN XOUT VSS I/O pin for signal with frequently changing potential levels Fig. 10 Wiring for signal lines where potential levels frequently change (3) Oscillator protection using Vss pattern Print a Vss pattern on the bottom (soldering side) of a double-sided printed circuit board, under the oscillator mount position. Connect the Vss pattern to the Vss pin of the microcomputer with the shortest possible wiring, separating it from other Vss patterns. An example of Vss pattern on the underside of an oscillator. M37902 A AAA AA AAA A AA AAA A AA AA Mounted pattern example of oscillator unit. XIN XOUT Vss Separate Vss lines for oscillation and supply. Fig. 11 Vss pattern underneath mounted oscillator 21-100 7902 Group User's Manual APPENDIX Appendix 7. Countermeasure against noise 5. Setup for I/O ports Setup I/O ports by hardware and software as follows: <Hardware protection> Connect a resistor of 100 or more to an I/O port in series. <Software protection> Read the data of an input port several times to confirm that input levels are equal. Since the output data may reverse because of noise, rewrite data to the output port's Pi register periodically. Rewrite data to port Pi direction registers periodically. Data bus Noise Direction register Port latch Port Fig. 12 Setup for I/O ports 6. Reinforcement of the power source line For the Vss and Vcc lines, use thicker wiring than that of other signal lines. When using a multilayer printed circuit board, the Vss and Vcc patterns must each be one of the middle layers. The following is necessary for double-sided printed circuit boards: *On one side, the microcomputer is installed at the center, and the Vss line is looped or meshed around it. The vacant area is filled with the Vss line. *On the opposite side, the Vcc line is wired the same as the Vss line. *The power source lines of external devices which are connected by bus to the microcomputer must be connected to the microcomputer's power source lines with the shortest possible wiring. Reasons: With external devices connected to the microcomputer, the levels of many of the signal lines (total external address buses: 24 bits) may change simultaneously, causing noise on the power source line. 7902 Group User's Manual 21-101 APPENDIX Appendix 8. 7902 Group Q & A Appendix 8. 7902 Group Q & A Information which may be helpful in fully utilizing the 7902 Group is provided in Q & A format. In Q & A, as a rule, one question and its answer are summarized within one page. The upper box on each page is a question, and a box below the question is its answer. (If a question or an answer extends to two or more pages, there is a page number at the lower right corner.) At the upper right corner of each page, the main function related to the contents of description in that page is listed. 21-102 7902 Group User's Manual APPENDIX Appendix 8. 7902 Group Q & A Interrupts Q If an interrupt request (b) occurs while an interrupt routine (a) is executed, is it true that the main routine is not executed at all after the execution of the interrupt routine (a) is completed until the execution of the INTACK sequence for the next interrupt (b) starts? Sequence of execution ? RTI instruction Interrupt routine (a) INTACK sequence for interrupt (b) Main routine Conditions: Flag I is cleared to "0" by executing the RTI instruction. The interrupt priority level of interrupt (b) is higher than IPL of the main routine. The interrupt priority detection time = 2 cycles of f sys . A An interrupt request is sampled by a sampling pulse generated synchronously with the CPU's op-code fetch cycle. (1) If the next interrupt request (b) occurs before sampling pulse for the RTI instruction is generated, the microcomputer executes the INTACK sequence for (b) without executing the main routine. (No instruction of the main routine is executed.) It is because that sampling is completed while executing the RTI instruction. Interrupt request (b) Sampling pulse RTI instruction Interrupt routine (a) INTACK sequence for interrupt (b) (2) If the next interrupt request (b) occurs immediately after sampling pulse is generated, the microcomputer executes one instruction of the main routine before executing the INTACK sequence for (b). It is because that the interrupt request is sampled by the next sampling pulse . Interrupt request (b) Sampling pulse RTI instruction One instruction executed Interrupt routine (a) Main routine 7902 Group User's Manual INTACK sequence for interrupt (b) 21-103 APPENDIX Appendix 8. 7902 Group Q & A Interrupts Q Suppose that there is a routine which should not accept a certain interrupt request. (This routine can accept any of the other interrupt request.) Although the interrupt priority level select bits for a certain interrupt are set to "000 2" (in other words, although this interrupt is set to be disabled), this interrupt request is actually accepted immediately after the change of the priority level. Why did this occur, and what should I do about it? : Interrupt request is MOVMB XXXIC, #00H ; Writes "000 2" to the interrupt priority level select bits. accepted in this ; Clears the interrupt request bit to "0." interval LDA A,DATA ; Instruction at the beginning of the routine which should not accept a certain interrupt request. : ; A As for the change of the interrupt priority level, if the following are met, the microcomputer may pretend to accept an interrupt request immediately after this interrupt is set to be disabled: *The next instruction (in the above example, it is the LDA instruction) is already stored into a instruction queue buffer of the BIU. *Requirements for accepting the interrupt request which should not be accepted are satisfied immediately before the next instruction in the instruction queue buffer is executed. When writing to a memory or an I/O, the CPU passes an address and data to the BIU. Then, the CPU executes the next instruction in the instruction queue buffer while the BIU is writing data into the actual address. Detection of the interrupt priority level is performed at the beginning of each instruction. In the above case, the CPU executes the next instruction before the BIU completes the change of the interrupt priority level. Therefore, in the detection of the interrupt priority level performed synchronously with the execution of the next instruction, actually, the interrupt priority level before the change is used to detection, and its interrupt request is accepted. Interrupt request generated Interrupt request accepted Sequence of execution Interrupt priority detection time CPU operation Previous instruction executed BIU operation (Instruction prefetched) MOVMB instruction executed LDA instruction executed Writing to interrupt priority level select bits. Change of interrupt priority level completed (1/2) 21-104 7902 Group User's Manual APPENDIX Appendix 8. 7902 Group Q & A Interrupts A To prevent this problem, make sure that the routine which should not accept a certain interrupt request will be executed after the change of the interrupt priority level (IPL) has been completed. (This is to be made by software.) The following is a sample program. [Sample program] After writing "0002" to the interrupt priority level select bits, the instruction queue buffer is filled with several NOP instructions to make the next instruction not to be executed before this writing is completed. : MOVMB XXXIC, #00H NOP : NOP LDA A,DATA : ; Writes "0002 " to the interrupt priority level select bits. ; Inserts ten NOP instructions. ; ; Instruction at the beginning of the routine that should not accept a certain interrupt request (2/2) 7902 Group User's Manual 21-105 APPENDIX Appendix 8. 7902 Group Q & A Interrupts Q After execution of the SEI instruction, a branch is made in an interrupt routin. Why did this occur? * * * * SEI LDAB A, #00H * * * * CLI Interrupt routine * * * * RTI A When an interrupt request is generated before the SEI instruction is executed, this interrupt request may be accepted immediately before the execution of the SEI instruction. (This acceptance occurs depending on the timing when that interrupt request occurs.) In this case, a branch to the interrupt routine is made immediately after execution of the SEI instruction. Accordingly, the interrupt routine which is executed immediately after the SEI instruction is due to an interrupt request generated before execution of the SEI instruction. Note that, in the routine ( a ) which should not accept the interrupt request, the following occur. (This routine follows the SEI instruction.): * No interrupt request is accepted. * No interrupt routine is made. * Interrupt request * * generated * SEI LDAB A, #00H * * * * a CLI Interrupt routine * * * * RTI Note: "Interrupt" described here means "maskable interrupt" which can be disabled by the SEI instruction. (Refer to section "7.2 Interruput source.") 21-106 7902 Group User's Manual APPENDIX Appendix 8. 7902 Group Q & A Interrupts Q (1) Which timing of clock 1 is the external interrupts (input signals to the INT i pin) detected? (2) When external interrupt input (INT i) pins are not enough, what should I do? A (1) In both of the edge sense and level sense, an external interrupt request occurs when the input signal to the INT i pin changes its level. This is independent of clock 1. In the edge sense, also, the interrupt request bit is set to "1" at this time. (2) There are two methods: one uses external interrupt's level sense, and the other uses the timer's event counter mode. Method using external interrupt's level sense As for hardware, input a logical sum of multiple interrupt signals (e.g., `a', `b', and `c') to the INTi pin, and input each signal to each corresponding port pin. As for software, check the port pin's input levels in the INT i interrupt routine in order to detect which signal (`a', `b', or `c') was input. M37902 Port pin Port pin Port pin a b c INTi Also, this can be realized by using the key input interrupt's function. For details, refer to "CHAPTER 8. KEY INPUT INTERRUPT." Method using timer's event counter mode As for hardware, input an interrupt signal to the TAi IN pin or TBi IN pin. As for software, set the timer's operating mode to the event counter mode. Then, set a value of "0000 16 " into the timer register and select the valid edge. A timer's interrupt request occurs when an interrupt signal (selected valid edge) is input. 7902 Group User's Manual 21-107 APPENDIX Appendix 8. 7902 Group Q & A Processor mode Q If the processor mode is switched as described below by using the processor mode bits (bits 1 and 0 at address 5E 16 ) during program execution, is there any precaution in programming? Single-chip mode Microprocessor mode Memory expansion mode Microprocessor mode A If the processor mode is set to be switched as described above by using the processor mode bits, the mode is actually switched simultaneously when a write cycle for the processor mode bits is completed. Then, the program counter indicates the address next to the address (address XXXX16 ) that stores a write instruction for the processor mode bits. Additionally, access to the internal ROM area is disabled. However, since the instruction queue buffer can prefetch instructions up to 10 bytes, the external ROM area's address which will be accessed first after the mode has been switched is one of addresses "XXXX 16 + 1" to "XXXX 16 + 11." Also, there is a possibility that each instruction at addresses "XXXX 16 + 1" to "XXXX16 + 10" is executed. To prevent a problem, be sure to do as follows by software. Transfer a write instruction for the processor mode bits to an internal RAM area, and make a branch to there in order to execute the write instruction. After that, make a branch to the programming address in the external ROM area. (The contents of the instruction queue buffer are initialized by a branch instruction.) Program a write instruction for the processor mode bits and the following instructions (10 bytes or more) to a certain address in the internal ROM area and the same one in the external ROM area. (See below.) Internal ROM area XXXX16 21-108 : : MOVMB NOP : NOP : External ROM area PMR, #00000010B XXXX16 10 bytes or more 7902 Group User's Manual : : MOVMB NOP : NOP : PMR, #00000010B APPENDIX Appendix 8. 7902 Group Q & A Watchdog timer Q In detection of a program runaway with usage of the watchdog timer, if the same value as that at the reset vector address is set to the watchdog timer interrupt's vector address, not performing software reset, how does it occur? When a branch is made to the branch destination address for reset within the watchdog timer interrupt routine, how does it occur? A The CPU registers and the SFR are not initialized in the above-mentioned way. Accordingly, the user must initialize all of them by software. Note that the processor interrupt priority level (IPL) retains "7" and is not initialized. Consequently, all interrupt requests cannot be accepted. When rewriting the IPL by software, be sure to save the 16-bit immediate value to the stack area, and then restore that 16-bit immediate value to all bits of the processor status register (PS). When a program runaway occurs, we recommend to perform software reset in order to initialize the microcomputer. 7902 Group User's Manual 21-109 APPENDIX Appendix 9. M37902FGCGP electrical characteristics Appendix 9. M37902FGCGP electrical characteristics The electrical characteristics of the M37902FGCGP are described below. For the electrical characteristics, be sure to refer to the latest datasheets. ABSOLUTE MAXIMUM RATINGS Symbol VCC AVCC VI VO Pd Topr Tstg 21-110 Parameter Power source voltage Analog power source voltage Input voltage P00 -P07, P1 0-P17, P2 0-P27 , P30-P3 3, P40-P4 7, P50 -P57, P60 -P67, P7 0-P77, P8 0-P87 , P100-P10 7, P110-P117, VREF, XIN, RESET, BYTE, MD0, MD1, NMI, VCONT Output voltage P00 -P07, P1 0-P17, P2 0-P27 , P30-P3 3, P40-P4 7, P50 -P57, P60 -P67, P7 0-P77, P8 0-P87 , P100-P107 , P110-P117, XOUT Power dissipation Operating ambient temperature Storage temerature 7902 Group User's Manual Ratings -0.3 to 6.5 -0.3 to 6.5 Unit V V -0.3 to VCC+0.3 V -0.3 to VCC+0.3 V 300 -20 to 85 -40 to 150 mW C C APPENDIX Appendix 9. M37902FGCGP electrical characteristics RECOMMENDED OPERATING CONDITIONS (Vcc = 5 V, Ta = -20 to 85 C, unless otherwise noted) Symbol VCC AVCC VSS AVSS VIH VIH VIH VIH VIH VIH VIH VIH VIL VIL VIL VIL VIL VIL I OH(peak) I OH(avg) I OL(peak) I OL(avg) f(X IN) f(fsys ) Parameter Power source voltage Analog power source voltage Power source voltage Analog power source voltage High-level input voltage XIN, RESET, BYTE, MD0, MD1 High-level input voltage P10-P17, P2 0-P27 , P30-P3 3, P40-P4 7, P50 -P57, P60-P67, P7 0-P77 , P80-P8 7, P100-P10 7, P110-P117 High-level input voltage P00-P07 (When the port P0 input level select bit = "0") High-level input voltage P00-P07 (When the port P0 input level select bit = "1") High-level input voltage D0-D7, D 8-D15 High-level input voltage RDY, HOLD, TA0IN-TA4 IN, TA0 OUT-TA4 OUT, TB0IN-TB2IN, KI0-KI3, INT0-INT4, NMI, AD TRG, CTS0 , CTS1, CLK0, CLK1, RxD0, RxD1 High-level input voltage SCLK, SDA (Note 1) Low-level input voltage XIN, RESET, BYTE, MD0, MD1 Low-level input voltage P10-P17, P2 0-P27 , P30-P3 3, P40-P4 7, P50 -P57, P60-P67, P7 0-P77 , P80-P8 7, P100-P10 7, P110-P117 Low-level input voltage P00-P07 (When the port P0 input level select bit = "0") Low-level input voltage P00-P07 (When the port P0 input level select bit = "1") Low-level input voltage D 0-D7, D 8-D15 Low-level input voltage RDY, HOLD, TA0IN-TA4 IN, TA0 OUT-TA4 OUT, TB0IN-TB2IN, KI0-KI3, INT0-INT4, NMI, AD TRG, CTS0 , CTS1, CLK0, CLK1, RxD0, RxD1 Low-level input voltage SCLK, SDA (Note 1) High-level peak output current P00-P0 7, P10-P1 7, P20 -P27, P3 0-P33, P4 0-P47 , P50-P5 7, P60-P6 7, P70 -P77, P8 0-P87, P10 0-P107 , P110-P117 High-level average output current P00-P0 7, P1 0-P17, P2 0-P27 , P30-P3 3, P40-P4 7, P5 0-P57, P6 0-P67 , P70-P7 7, P80-P8 7, P100 -P107, P110-P117 Low-level peak output current P00-P0 7, P1 0-P17, P2 0-P27 , P30-P3 3, P40-P4 7, P5 0-P57, P6 0-P67 , P70-P7 7, P80-P8 7, P100 -P107, P110-P117 Low-level average output current P00-P0 7, P1 0-P17, P2 0-P27 , P30-P3 3, P40-P4 7, P5 0-P57, P6 0-P67 , P70-P7 7, P80-P8 7, P100 -P107, P110-P117 External clock input frequency (Note 2) System clock frequency Min. 4.5 Limits Typ. 5.0 VCC 0 0 Max. 5.5 Unit 0.8 Vcc 0.7 VCC Vcc VCC V V V V V V 0.7 Vcc 0.43 Vcc 0.43 Vcc 0.43 Vcc Vcc Vcc Vcc Vcc V V V V 0.43 Vcc 0 0 Vcc 0.2 VCC 0.2 VCC V V V 0 0 0 0 0.2 VCC 0.16 VCC 0.16 VCC 0.16 VCC V V V V 0 0.16 VCC -10 V mA -5 mA 10 mA 5 mA 26 26 MHz MHz Notes 1: Pins SCLK and SDA are used only in the flash memory serial I/O mode. 2: When using the PLL frequency multiplier, be sure that f(fsys) = 26 MHz or less. 3: Average output current is the average value of an interval of 100 ms. 4: The sum of IOL(peak) for ports P0-P2, P8, P10, and P11 must be 80 mA or less, the sum of I OH(peak) for ports P0-P2, P8, P10, and P11 must be 80 mA or less, the sum of IOL(peak) for ports P3-P7 must be 80 mA or less, the sum of IOH(peak) for ports P3-P7 must be 80 mA or less. 7902 Group User's Manual 21-111 APPENDIX Appendix 9. M37902FGCGP electrical characteristics DC ELECTRICAL CHARACTERISTICS I IL (VCC = 5 V, VSS = 0 V, Ta = -20 to 85 C, f(f sys) = 26 MHz, unless otherwise noted) Limits Parameter Unit Test conditions Typ. Max. Min. High-level output voltage P00-P07, P1 0-P17 , I OH = -10 mA 3 V P20-P27, P30, P40-P47, P50-P57, P6 0-P67 , P70-P77, P8 0-P87 , P10 0-P107, P110 -P117 High-level output voltage P00-P07, P10-P1 7, I OH = -400 A 4.7 V P20-P27, P40, P42, P44-P47, P10 0-P107, P110 -P117 High-level output voltage P31-P33 I OH = -10 mA 3.4 V I OH = -400 A 4.8 Low-level output voltage P00-P07, P1 0-P17 , 2 I OL = 10 mA V P20-P27, P30, P40-P47, P50-P57, P6 0-P67 , P70-P77, P8 0-P87 , P10 0-P107, P110 -P117 Low-level output voltage P00-P07, P1 0-P17 , 0.45 I OL = 2 mA V P20-P27, P4 0, P42 , P44-P47, P10 0-P107, P110 -P117 Low-level output voltage P31-P33 1.6 I OL = 10 mA V 0.4 I OL = 2 mA Hysteresis RDY, HOLD, TA0 IN-TA4IN, 0.7 0.2 V TA0 OUT-TA4OUT, TB0IN-TB2IN, KI0-KI3, INT0-INT4, NMI, ADTRG, CTS0, CTS1, CLK0, CLK1, RxD0, RxD1 Hysteresis RESET 1.5 0.5 V Hysteresis XIN 0.3 0.1 V High-level input current P00-P0 7, P10-P1 7, 5 VI = 5.0 V A P20-P27, P30-P3 3, P40-P47, P50-P57, P60-P6 7, P70-P77, P80-P8 7, P100-P10 7, P110-P117, XIN, RESET, BYTE, MD0, MD1, NMI Low-level input current P00-P0 7, P10-P1 7, VI = 0 V -5 A P20-P27, P30-P3 3, P40-P43, P50-P53, P60-P6 7, P70-P77, P80-P8 7, P100-P10 7, P110-P117, XIN, RESET, BYTE, MD0, MD1 Low-level input current P44-P47, P54 -P57, NMI VI = 0 V, No pullup transistor -5 A VRAM I CC RAM hold voltage Power source current Symbol VOH VOH VOH VOL VOL VOL VT+ --VT- VT+ --VT- VT+ --VT- I IH I IL 21-112 VI = 0 V, Pullup transistor used When clock is stoped. Output-only pins f(fsys ) = 26 MHz. are open, and the CPU operates. other pins are connected to Vss or Vcc. An external Ta = 25 C when square-waveform clock is stopped. clock is input. (Pin XOUT is open.) The PLL frequency Ta = 85 C when multiplier stops its clock is stopped. operation. 7902 Group User's Manual -0.4 2 -0.7 -1.1 30 54 mA V mA 1 A 20 APPENDIX Appendix 9. M37902FGCGP electrical characteristics A-D CONVERTER CHARACTERISTICS (VCC = AVCC = 5 V 0.5 V, VSS = AVSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol ---------- ---------- RLADDER Parameter Resolution VREF = VCC Ladder resistance VREF = VCC Conversion time VREF VIA Reference voltage Analog input voltage Min. Max. 10 3 2 VREF = VCC Absolute accuracy t CONV Limits Test conditions 10-bit resolution mode 8-bit resolution mode f(fsys) 26 MHz 10-bit resolution mode 8-bit resolution mode 5 4.54 1.89 (Note) 2.7 0 Unit Bits LSB LSB k s VCC VREF V V Note: This is applied when A-D conversion freguency (AD) = f1 . D-A CONVERTER CHARACTERISTICS (VCC = 5 V, VSS = AVSS = 0 V, V REF = 5 V, Ta = -20 to 85 C, unless otherwise noted) Symbol ---- ---- tsu RO IVREF Parameter Test conditions Resolution Absolute accuracy Set time Output resistance Reference power source input current Min. 1 Limits Typ. 2.5 (Note) Max. 8 1.0 3 4 3.2 Unit Bits % s k mA Note: The test conditions are as follows: * One D-A converter is used. * The D-A register value of the unused D-A converter is "0016 ." * The reference power source input current for the ladder resistance of the A-D converter is excluded. RESET INPUT Reset input timing requirements (VCC = 5 V 0.5 V, VSS = 0V, Ta = -20 to 85 C, unless otherwise noted) Symbol tw(RESETL) Parameter Min. 2 RESET input low-level pulse width Limits Typ. Max. Unit s RESET input tw(RESETL) 7902 Group User's Manual 21-113 APPENDIX Appendix 9. M37902FGCGP electrical characteristics PERIPHERAL DEVICE INPUT/OUTPUT TIMING (VCC = 5 V0.5 V, V SS = 0 V, Ta = -20 to 85 C, f(fsys) = 26 MHz unless otherwise noted) For limits depending on f(fsys), their calculation formulas are shown below. Also, the values at f(f sys) = 26 MHz are shown in ( ). Timer A input (Count input in event counter mode) Symbol tc(TA) tw(TAH) tw(TAL) Limits Parameter Min. 80 40 40 TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width Max. Unit ns ns ns Timer A input (Gating input in timer mode) Symbol Parameter tc(TA) TAiIN input cycle time f(fsys) 26 MHz tw(TAH) TAiIN input high-level pulse width f(fsys) 26 MHz tw(TAL) TAiIN input low-level pulse width f(fsys) 26 MHz Limits Min. 16 x 109 (615) f(f sys) 9 8 x 10 (307) f(f sys) 9 8 x 10 (307) f(f sys) Max. Unit ns ns ns Note : The TAiIN input cycle time requires 4 or more cycles of a count source. The TAiIN input high-level pulse width and the TAiIN input low-level pulse width respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f 2 at f(f sys) 26 MHz. Timer A input (External trigger input in one-shot pulse mode) Symbol Limits Parameter t c(TA) TAi IN input cycle time t w(TAH) t w(TAL) TAi IN input high-level pulse width TAi IN input low-level pulse width Min. f(fsys) 26 MHz 8 x 109 f(fsys) Max. (307) Unit ns 80 80 ns ns Timer A input (External trigger input in pulse width modulation mode) Symbol tw(TAH) tw(TAL) Parameter TAiIN input high-level pulse width TAiIN input low-level pulse width Limits Min. 80 80 Max. Unit ns ns Timer A input (Up-down input and Count input in event counter mode) Symbol t c(UP) t w(UPH) t w(UPL) t su(UP-TIN) t h(TIN-UP) 21-114 Parameter TAiOUT input cycle time TAiOUT input high-level pulse width TAiOUT input low-level pulse width TAiOUT input setup time TAiOUT input hold time 7902 Group User's Manual Limits Min. 2000 1000 1000 400 400 Max. Unit ns ns ns ns ns APPENDIX Appendix 9. M37902FGCGP electrical characteristics Timer A input (Two-phase pulse input in event counter mode) Symbol tc(TA) tsu(TAjIN-TAjOUT) tsu(TAjOUT-TAjIN) Limits Parameter Min. 800 200 200 TAiIN input cycle time TAjIN input setup time TAjOUT input setup time Max. Unit ns ns ns * Gating input in timer mode * Count input in event counter mode * External trigger input in one-shot pulse mode * External trigger input in pulse width modulation mode tc(TA) tw(TAH) TAiIN input tw(TAL) * Up-down and Count input in event counter mode tc(UP) tw(UPH) TAiOUT input (Up-down input) tw(UPL) TAiOUT input (Up-down input) th(TIN-UP) tsu(UP-TIN) TAiIN input (When count by falling) TAiIN input (When count by rising) * Two-phase pulse input in event counter mode tc(TA) TAjIN input tsu(TAjIN-TAjOUT) tsu(TAjIN-TAjOUT) tsu(TAjOUT-TAjIN) TAjOUT input tsu(TAjOUT-TAjIN) Test conditions * VCC = 5 V0.5 V, Ta = -20 to 85 C * Input timing voltage : VIL = 0.8 V, VIH = 2.15 V 7902 Group User's Manual 21-115 APPENDIX Appendix 9. M37902FGCGP electrical characteristics Timer B input (Count input in event counter mode) Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Parameter TBiIN input cycle time (one edge count) TBiIN input high-level pulse width (one edge count) TBiIN input low-level pulse width (one edge count) TBiIN input cycle time (both edge count) TBiIN input high-level pulse width (both edge count) TBiIN input low-level pulse width (both edge count) Timer B input Limits Min. 80 40 40 160 80 80 Max. Unit ns ns ns ns ns ns (Pulse period measurement mode) Symbol Parameter tc(TB) TBiIN input cycle time f(fsys ) 26 MHz tw(TBH) TBiIN input high-level pulse width f(fsys ) 26 MHz tw(TBL) TBiIN input low-level pulse width f(fsys ) 26 MHz Limits Min. 16 x 109 (615) f(fsys) 8 x 109 (307) f(fsys) 8 x 109 (307) f(fsys) Max. Unit ns ns ns Note: The TBiIN input cycle time requires 4 or more cycles of a count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f 2 at f(fsys) 26 MHz. Timer B input (Pulse width measurement mode) Symbol Parameter tc(TB) TBiIN input cycle time f(fsys ) 26 MHz tw(TBH) TBiIN input high-level pulse width f(fsys ) 26 MHz tw(TBL) TBiIN input low-level pulse width f(fsys ) 26 MHz Limits Min. 16 x 109 (615) f(fsys) 8 x 109 (307) f(fsys) 8 x 109 (307) f(fsys) Max. Unit ns ns ns Note: The TBiIN input cycle time requires 4 or more cycles of a count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f 2 at f(fsys) 26 MHz. A-D trigger input Symbol tc(AD) tw(ADL) 21-116 Parameter ADTRG input cycle time (minimum allowable trigger) ADTRG input low-level pulse width 7902 Group User's Manual Limits Min. 1000 125 Max. Unit ns ns APPENDIX Appendix 9. M37902FGCGP electrical characteristics Serial I/O Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) Limits Parameter Min. 200 100 100 CLKi input cycle time CLKi input high-level pulse width CLKi input low-level pulse width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Max. 80 0 20 90 Unit ns ns ns ns ns ns ns External interrupt (INTi) input, NMI input, Key input interrupt (KIi) input Symbol tw(INH) tw(INL) Limits Parameter Min. 250 250 INTi input/NMI input/KIi input high-level pulse width INTi input/NMI input/KIi input low-level pulse width Max. Unit ns ns tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input tc(CK) tw(CKH) CLKi input tw(CKL) th(C - Q) TxDi output td(C - Q) tsu(D - C) th(C - D) RxDi input tw(INL) INTi input, NMI input, KIi input tw(INH) Test conditions * Vcc = 5 V 0.5 V, Ta = -20 to 85 C * Input timing voltage : VIL = 0.8 V, VIH = 2.15 V * Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 50 pF 7902 Group User's Manual 21-117 APPENDIX Appendix 9. M37902FGCGP electrical characteristics READY, HOLD TIMING Timing requirements (VCC = 5 V0.5 V, VSS = 0 V, Ta = -20 to 85 C, f(f sys) = 26 MHz, unless otherwise noted) Symbol tsu(RDY-1) tsu(HOLD-1) th(1-RDY) th(1-HOLD) Parameter RDY input setup time HOLD input setup time RDY input hold time HOLD input hold time Switching characteristics Symbol td( 1-HLDAL) td(RDH-HLDAL) td(BXWH-HLDAL) tpxz(HLDAL-RDZ) tpxz(HLDAL-BXWZ) tpxz(HLDAL-CSiZ) tpxz(HLDAL-ALEZ) tpxz(HLDAL-AZ) tpzx(HLDAL-RDZ) tpzx(HLDAL-BXWZ) tpzx(HLDAL-CSiZ) tpzx(HLDAL-ALEZ) tpzx(HLDAL-AZ) Max. Unit ns ns ns ns (VCC = 5 V0.5 V, VSS = 0 V, Ta = -20 to 85 C, f(f sys ) = 26 MHz, unless otherwise noted) Parameter HLDA output delay time HLDA low-level output delay time after read HLDA low-level output delay time after write Floating start delay time Floating start delay time Floating start delay time Floating start delay time Floating start delay time Floating release delay time Floating release delay time Floating release delay time Floating release delay time Floating release delay time Note: tc = 1/f(fsys). 21-118 Limits Min. 40 40 0 0 7902 Group User's Manual Limits Min. Max. 20 tc -15 (Note) tc -15 (Note) -15 -15 -15 -15 -15 0 0 0 0 0 10 10 10 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns APPENDIX Appendix 9. M37902FGCGP electrical characteristics RDY input 1 RD, BLW, BHW tsu (RDY-1) th (1-RDY) RDY input : Wait inserted by software (The above is applied when bus cycle = 1 + 2) : Wait inserted by ready function HOLD input 1 tsu (HOLD-1) th (1-HOLD) HOLD input td (1-HLDAL) td (1-HLDAL) HLDA output td (RDH-HLDAL) tpxz (HLDAL-RDZ) tpzx (HLDAL-RDZ) Hi-Z RD td (BXWH-HLDAL) tpxz (HLDAL-BXWZ) tpzx (HLDAL-BXWZ) Hi-Z BLW BHW tpxz (HLDAL-CSiZ) tpzx (HLDAL-CSiZ) Hi-Z CSi tpxz (HLDAL-ALEZ) tpzx (HLDAL-ALEZ) Hi-Z ALE tpxz (HLDAL-AZ) tpzx (HLDAL-AZ) Hi-Z A0-A23 output Test conditions * VCC = 5 V 0.5 V, Ta= -20 to 85 C * RDY input, HOLD input : VIL = 0.8V, VIH = 2.15 V * HLDA output : VOL = 0.8V, VOH = 2.0 V, CL = 50 pF 7902 Group User's Manual 21-119 APPENDIX Appendix 9. M37902FGCGP electrical characteristics External bus timing For limits depending on f(fsys), their calculation formulas are shown below. Bus cycle 1 +1 1 +2 1 +3 2 +2 WH WL 1 1 1 2 1 2 3 2 Bus cycle WH WL 2 2 3 3 3 4 3 4 2 +3 2 +4 3 +3 3 +4 tc = 1/f(fsys). Timing Requirements (VCC = 5 V0.5 V, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 26 MHz, unless otherwise noted) Symbol tc(in) tw(harf) tw(H) tw(L) tr tf ta(A-D) ta(A-D) ta(CSiL-D) ta(RDL-D) tsu(D-RDL) th(RDH-D) ta(BA-D) th(BA-D) ta(LA-D) Limits Parameter Min. 38 0.45 tc 0.5 tc - 6 0.5 tc - 6 6 6 External clock input cycle time External clock input pulse width with half input-volage External clock input high-level pulse width External clock input low-level pulse width External clock input rise time External clock input fall time Address access time (the address output select bit = 0) Address access time (the address output select bit = 1) Chip select access time Read access time Read data setup time Data input hold time after read Address access time at burst ROM access Data hold time after address at burst ROM access Address access time (the multiplexed bus select bit = 1) Max. 0.55 tc (WH + WL) tc-45 (WH + WL-0.5) tc-35 (WH + WL-0.5) tc-35 WL tc-30 15 0 WL tc-35 8 (WH + W L-0.5)tc-35 (Note) Note: This is independent of the address output select bit's contents. External clock input tw(L) tw(H) tr XIN Test conditions * Vcc = 5 V 0.5 V, Ta = -20 to 85 C * Input timing voltage : VIL = 1.0 V, VIH = 4.0 V (tw(H), tw(L), tr, tf) * Output timing voltage : 2.5 V (tc(in), tw(half)) 21-120 7902 Group User's Manual tf tc(in) tw(half) Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns APPENDIX Appendix 9. M37902FGCGP electrical characteristics Switching characteristics (VCC = 5 V0.5 V, VSS = 0 V, Ta = -20 to 85 C, f(f sys) = 26 MHz, unless otherwise noted) Symbol Parameter td(1-RDL) td(1-RDH) td(1-BXWL) td(1-BXWH) td(1L-CSiL) td(1L-CSiH) td(1H-A) td(1L-A) tw(ALEH) Read low-level output delay time Read high-level output delay time Write low-level output delay time Write high-level output delay time Chip select low-level output delay time Chip select high-level output delay time Address output delay time (the address output select bit = 0) Address output delay time (the address output select bit = 1) ALE pulse width Bus cycle = 1 + 1, 1 + 2, 1 + 3 td(A-ALEL) Bus cycle = 2 + 2 Bus cycle = 2 + 3, 2 + 4, 3 + 3, 3 + 4 ALE completion delay time Bus cycle = 1 + 1, 1 + 2, 1 + 3 after address stabilization Bus cycle = 2 + 2 (when the address output Bus cycle = 2 + 3, 2 + 4, 3 + 3, 3 + 4 select bit = 0) tw(RDL) tw(RDH) td(RDH-BXWH) td(A-RDH) td(A-RDH) th(RDH-A) th(RDH-A) td(RDH-ALEL) td(ALEL-RDH) td(CSiL-RDH) td(CSiL-RDL) th(RDH-CSiL) td(RDH-D) tw(BXWL) tw(BXWH) td(BXWH-RDH) td(A-BXWH) td(A-BXWH) th(BXWH-A) th(BXWH-A) td(BXWH-ALEL) td(ALEL-BXWH) td(CSiL-BXWH) td(CSiL-BXWL) th(BXWH-CSiL) td(D-BXWL) th(BXWH-D) tpxz(BXWH-DZ) Limits Min. -18 -18 -18 -18 -20 -22 -5 -20 0.5tc-19 tc-20 1.5tc-20 Unit ns ns ns ns ns ns ns ns ns ns ns tc-30 ns 1.5tc-30 2tc-30 0.5tc-19 ns ALE completion delay time Bus cycle = 1 + 1, 1 + 2, 1 + 3 after address stabilization Bus cycle = 2 + 2 tc-20 (when the address output Bus cycle = 2 + 3, 2 + 4, 3 + 3, 3 + 4 1.5tc-20 select bit = 1) WL tc-15 Read output pulse width Read output high-level width (Note 1) WH tc-15 Write disable valid time after read (Note 2) tc-15 WH tc-30 Address valid time before read (when the address output select bit = 0) Address valid time before read (when the address output select bit = 1) (WH -0.5)tc-19 Address hold time after read (when the address output select bit = 0) (Note 2) 8 0.5tc-10 Address hold time after read (when the address output select bit = 1) (Note 2) ALE completion delay time after read start Read disable valid time Bus cycle = 2 + 2 0.5tc-19 after ALE completion tc-15 Bus cycle = 3 + 3, 3 + 4 Chip select valid time before read (WH -0.5)tc-19 Chip select output valid time before read completion (W H + WL-0.5)tc-20 Chip select hold time after read 0.5tc-14 Next write cycle data output delay time after read (Note 2) tc-15 Write output pulse width WL tc-15 Write output high-level width (Note 1) WH tc-15 Read disable valid time after write (Note 2) tc-15 Address valid time before write (when the address output select bit = 0) WH tc-30 (WH -0.5)tc-19 Address valid time before write (when the address output select bit = 1) Address hold time after write (when the address output select bit = 0) (Note 2) 8 Address hold time after write (when the address output select bit = 1) (Note 2) 0.5tc-10 ALE completion delay time after write start Write disable valid time 0.5tc-19 Bus cycle = 2 + 2 after ALE completion Bus cycle = 2 + 3, 2 + 4, 3 + 3, 3 + 4 tc-15 (WH -0.5)tc-19 Chip select valid time before write Chip select output valid time before write completion Chip select hold time after write Data output valid time before write completion Data hold time after write (Note 3) Floating start delay time after write (Note 3) Max. 0 0 0 0 0 10 25 16 ns ns ns ns ns ns ns ns ns ns 20 ns ns ns ns ns ns ns 20 (WH + WL-0.5)tc-20 0.5tc-14 WL tc-20 0.5tc-10 0.5tc + 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 1: When the bus cycle just before this parameter is for the area where the recovery cycle insertion is selected, this parameter is extended by tc (ns: one recovery cycle is inserted.) or by 2tc (ns: two recovery cycles are inserted.). 2: When accessing the area where the recovery cycle insertion is selected, this parameter is extended by tc (ns: one recovery cycle is inserted.) or by 2tc (ns: two recovery cycles are inserted.). 3: This parameter is extended by tc (ns) when both of the following conditions are satisfied: * When accessing the area where the recovery cycle insertion is selected. * When two recovery cycles are inserted. 7902 Group User's Manual 21-121 APPENDIX Appendix 9. M37902FGCGP electrical characteristics Switching characteristics (VCC = 5 V0.5 V, VSS = 0 V, Ta = -20 to 85 C, f(fsys) = 26 MHz, unless otherwise noted) Symbol td(LA-RDH) td(LA-ALEL) th(ALEL-LA) tpxz(RDH-LAZ) td(LA-BXWH) tpzx(RDH-DZ) Parameter Address valid time before read ALE completion delay time Bus cycle = 2 + 2 after address stabilization Bus cycle = 3 + 3, 3 + 4 Address hold time after Bus cycle = 2 + 2 ALE completion Bus cycle = 3 + 3, 3 + 4 Floating start delay time Address valid time before write Floating release delay time Note: This is independent of the address output select bit's contents. 21-122 7902 Group User's Manual Limits Min. (WH-0.5)tc-19 (Note) tc-20 (Note) 1.5tc-20 (Note) 0.5tc-19 tc-15 Max. 5 (WH-0.5)tc-19 (Note) 0.5tc-19 (Note) Unit ns ns ns ns ns ns ns ns APPENDIX Appendix 9. M37902FGCGP electrical characteristics Normal access: bus cycle = 1 + 1, 1 + 2, 1+ 3, 2 + 3, or 2 + 4 tc fsys Bus cycle <At read> td(1L-CSiL) td(1L-CSiH) 1 td(1H-A) td(1-RDL) tw(ALEH) td(1L-A) td(1-RDH) ALE td(A-ALEL) tw(RDH) tw(RDL) RD td(RDH-ALEL) td(RDH-BXWH) BLW BHW th(RDH-A) td(A-RDH) A0-A23 (when the address output select bit = 0) td(A-ALEL) td(A-RDH) th(RDH-A) A0-A23 (when the address output select bit = 1) td(CSiL-RDH) td(CSiL-RDL) th(RDH-CSiL) CSi ta(A-D) ta(A-D) ta(CSiL-D) ta(RDL-D) td(RDH-D) tsu(D-RDL) th(RDH-D) D0-D7, D8-D15 Test conditions * VCC = 5 V 0.5 V, Ta = -20 to 85 C * Input timing voltage : VIL=0.8 V, VIH=2.15 V * Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=15 pF (CSi) * Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=50 pF (except for CSi) 7902 Group User's Manual 21-123 APPENDIX Appendix 9. M37902FGCGP electrical characteristics Normal access: bus cycle = 1 + 1, 1 + 2, 1 + 3, 2 + 3, or 2 + 4 tc fsys <At write> Bus cycle td(1L-CSiL) td(1L-CSiH) 1 td(1H-A) td(1L-A) td(1-BXWL) tw(ALEH) td(1-BXWH) ALE td(A-ALEL) td(BXWH-RDH) RD tw(BXWH) tw(BXWL) BLW BHW td(A-BXWH) td(BXWH-ALEL) th(BXWH-A) A0-A23 (when the address output select bit = 0) td(A-ALEL) td(A-BXWH) A0-A23 (when the address output select bit = 1) td(CSiL-BXWH) td(CSiL-BXWL) th(BXWH-A) th(BXWH-CSiL) CSi td(D-BXWL) th(BXWH-D) D0-D7, D8-D15 tpxz(BXWH-DZ) Test conditions * VCC = 5 V 0.5 V, Ta = -20 to 85 C * Input timing voltage : VIL=0.8 V, VIH=2.15 V * Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=15 pF (CSi) * Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=50 pF (except for CSi) 21-124 7902 Group User's Manual APPENDIX Appendix 9. M37902FGCGP electrical characteristics Normal access: bus cycle = 2 + 2, 3 + 3, 3 + 4 tc fsys <At read> Bus cycle td(1L-CSiL) td(1L-CSiH) 1 td(1H-A) td(1L-A) tw(ALEH) td(1-RDL) td(1-RDH) td(ALEL-RDH) ALE td(A-ALEL) tw(RDH) tw(RDL) RD td(RDH-BXWH) BLW BHW A0-A23 (when the address output select bit = 0) A0-A23 (when the address output select bit = 1) td(A-RDH) th(RDH-A) td(A-ALEL) td(A-RDH) th(RDH-A) td(CSiL-RDH) td(CSiL-RDL) th(RDH-CSiL) CSi ta(A-D) ta(A-D) D0-D7, D8-D15 (when the multiplexed bus select bit = 0) ta(CSiL-D) ta(RDL-D) td(RDH-D) tsu(D-RDL) th(RDH-D) ta(RDL-D) tsu(D-RDL) th(RDH-D) td(LA-RDH) tpzx(RDH-DZ) ta(LA-D) LA0/D0-LA7/D7 (when the multiplexed bus select bit = 1, Note) Address td(LA-ALEL) Input data Address tpxz(RDH-LAZ) th(ALEL-LA) Note: Valid only when area CS2 is accessed with the external data bus width = 8 bits. Test conditions * VCC = 5 V 0.5 V, Ta = -20 to 85 C * Input timing voltage : VIL=0.8 V, VIH=2.15 V * Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=15 pF (CSi) * Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=50 pF (except for CSi) 7902 Group User's Manual 21-125 APPENDIX Appendix 9. M37902FGCGP electrical characteristics Normal access: bus cycle = 2 + 2, 3 + 3, 3 + 4 tc fsys <At write> Bus cycle td(1L-CSiL) 1 td(1H-A) td(1L-CSiH) td(1L-A) tw(ALEH) td(1-BXWH) td(1-BXWL) ALE td(ALEL-BXWH) td(A-ALEL) td(BXWH-RDH) RD tw(BXWH) tw(BXWL) BLW BHW th(BXWH-A) td(A-BXWH) A0-A23 (when the address output select bit = 0) A0-A23 (when the address output select bit = 1) td(A-ALEL) td(A-BXWH) th(BXWH-A) td(CSiL-BXWH) th(BXWH-CSiL) td(CSiL-BXWL) CSi td(D-BXWL) D0-D7, D8-D15 (when the multiplexed bus select bit = 0) td(D-BXWL) td(LA-BXWH) LA0/D0-LA7/D7 (when the multiplexed bus select bit = 1, Note) Address td(LA-ALEL) tpxz(BXWH-DZ) th(BXWH-D) Output data th(ALEL-LA) Note: Valid only when area CS2 is accessed with the external data bus width = 8 bits. Test conditions * VCC = 5 V 0.5 V, Ta = -20 to 85 C * Input timing voltage : VIL=0.8 V, VIH=2.15 V * Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=15 pF (CSi) * Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=50 pF (except for CSi) 21-126 th(BXWH-D) 7902 Group User's Manual tpxz(BXWH-DZ) 7902 Group User's Manual ta(A-D) ta(A-D) ta(RDL-D) ta(CSiL-D) td(CSiL-RDH) td(RDH-ALEL) ta(BA-D) th(BA-D) Test conditions * VCC = 5 V 0.5 V, Ta = -20 to 85 C * Input timing voltage : VIL=0.8 V, VIH=2.15 V * Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=15 pF (CSi) * Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=50 pF (except for CSi) D0-D7, D8-D15 CSi A0-A23 (when the address output select bit = 1) td(A-RDH) td(A-RDH) td(A-ALEL) td(A-ALEL) tw(RDH) A0-A23 (when the address output select bit = 0) BLW BHW RD ALE tw(ALEH) Burst ROM access: bus cycle = 1 + 1, 1 + 2, 1 + 3, 2 + 3, 2 + 4 th(BA-D) ta(BA-D) th(BA-D) ta(BA-D) th(RDH-D) th(RDH-CSiL) th(RDH-A) th(RDH-A) td(RDH-BXWH) APPENDIX Appendix 9. M37902FGCGP electrical characteristics 21-127 APPENDIX Appendix 10. M37902FGMHP electrical characteristics Appendix 10. M37902FGMHP electrical characteristics The electrical characteristics of the M37902FGMHP are described below. For the electrical characteristics, be sure to refer to the latest datasheets. ABSOLUTE MAXIMUM RATINGS Symbol VCC AVCC VI VO Pd Topr Tstg 21-128 Parameter Power source voltage Analog power source voltage Input voltage P00 -P07, P1 0-P17, P2 0-P27 , P30-P3 3, P40-P4 7, P50 -P57, P60 -P67, P7 0-P77, P8 0-P87 , P100-P10 7, P110-P117, VREF, XIN, RESET, BYTE, MD0, MD1, NMI, VCONT Output voltage P00 -P07, P1 0-P17, P2 0-P27 , P30-P3 3, P40-P4 7, P50 -P57, P6 0-P67, P7 0-P77 , P80-P8 7, P100-P10 7, P110-P117 , XOUT Power dissipation Operating ambient temperature Storage temerature 7902 Group User's Manual Ratings -0.3 to 4.6 -0.3 to 4.6 Unit V V -0.3 to VCC+0.3 V -0.3 to VCC+0.3 V 300 -20 to 85 -40 to 150 mW C C APPENDIX Appendix 10. M37902FGMHP electrical characteristics RECOMMENDED OPERATING CONDITIONS (Vcc = 3.3 V, Ta = -20 to 85 C, unless otherwise noted) Symbol VCC AVCC VSS AVSS VIH VIH VIH VIH VIH VIH VIH VIH VIL VIL VIL VIL VIL VIL I OH(peak) I OH(avg) I OL(peak) I OL(avg) f(X IN) f(fsys ) Parameter Power source voltage Analog power source voltage Power source voltage Analog power source voltage High-level input voltage XIN, RESET, BYTE, MD0, MD1 High-level input voltage P10-P17, P2 0-P27, P3 0-P3 3, P40-P4 7, P50 -P57, P60-P67, P7 0-P77, P8 0-P8 7, P100-P10 7, P110-P117 High-level input voltage P00-P07 (When the port P0 input level select bit = "0") High-level input voltage P00-P07 (When the port P0 input level select bit = "1") High-level input voltage D0-D7, D 8-D15 High-level input voltage RDY, HOLD, TA0IN-TA4 IN, TA0 OUT-TA4 OUT, TB0IN-TB2IN, KI0-KI3, INT0-INT4, NMI, ADTRG, CTS0, CTS1, CLK0, CLK1, RxD0, RxD1 High-level input voltage SCLK, SDA (Note 1) Low-level input voltage XIN, RESET, BYTE, MD0, MD1 Low-level input voltage P10-P17, P2 0-P27, P3 0-P3 3, P40-P4 7, P50 -P57, P60-P67, P7 0-P77, P8 0-P8 7, P100-P10 7, P110-P117 Low-level input voltage P00-P07 (When the port P0 input level select bit = "0") Low-level input voltage P00-P07 (When the port P0 input level select bit = "1") Low-level input voltage D 0-D7, D 8-D15 Low-level input voltage RDY, HOLD, TA0IN-TA4 IN, TA0 OUT-TA4 OUT, TB0IN-TB2IN, KI0-KI3, INT0-INT4, NMI, ADTRG, CTS0, CTS1, CLK0, CLK1, RxD0, RxD1 Low-level input voltage SCLK, SDA (Note 1) High-level peak output current P00-P0 7, P10-P1 7, P20-P2 7, P3 0-P33, P4 0-P47 , P50-P5 7, P60-P6 7, P70-P7 7, P8 0-P87, P10 0-P107, P110-P117 High-level average output current P00-P0 7, P10 -P17, P2 0-P27, P3 0-P33 , P40-P4 7, P50 -P57, P6 0-P67, P7 0-P77 , P80-P8 7, P100-P10 7, P110-P117 Low-level peak output current P00-P0 7, P10 -P17, P2 0-P27, P3 0-P33 , P40-P4 7, P50 -P57, P6 0-P67, P7 0-P77 , P80-P8 7, P100-P10 7, P110-P117 Low-level average output current P00-P0 7, P10 -P17, P2 0-P27, P3 0-P33 , P40-P4 7, P50 -P57, P6 0-P67, P7 0-P77 , P80-P8 7, P100-P10 7, P110-P117 External clock input frequency (Note 2) System clock frequency Min. 3.0 Limits Typ. 3.3 VCC 0 0 Max. 3.6 Unit 0.8 Vcc 0.7 VCC Vcc VCC V V V V V V 0.7 Vcc 0.5 Vcc 0.5 Vcc 0.5 Vcc Vcc Vcc Vcc Vcc V V V V 0.5 Vcc 0 0 Vcc 0.2 V CC 0.2 V CC V V V 0 0 0 0 0.2 V CC 0.16 VCC 0.22 VCC 0.16 VCC V V V V 0 0.16 VCC -10 V mA -5 mA 10 mA 5 mA 26 26 MHz MHz Notes 1: Pins SCLK and SDA are used only in the flash memory serial I/O mode. 2: When using the PLL frequency multiplier, be sure that f(fsys) = 26 MHz or less. 3: Average output current is the average value of an interval of 100 ms. 4: The sum of IOL(peak) for ports P0-P2, P8, P10, and P11 must be 80 mA or less, the sum of I OH(peak) for ports P0-P2, P8, P10, and P11 must be 80 mA or less, the sum of IOL(peak) for ports P3-P7 must be 80 mA or less, the sum of IOH(peak) for ports P3-P7 must be 80 mA or less. 7902 Group User's Manual 21-129 APPENDIX Appendix 10. M37902FGMHP electrical characteristics DC ELECTRICAL CHARACTERISTICS (Vcc = 3.3 V, Vss = 0 V, Ta = -20 to 85 C, f(fsys) = 26 MHz, unless otherwise noted) Symbol VOH VOH VOL VOL VT+ --VT- VT+ --VT- VT+ --VT- IIH IIL IIL VRAM ICC 21-130 Parameter Test conditions High-level output voltage P00-P07, P1 0-P17, P20-P27, P30, P40-P47, P50-P57, P6 0-P67, P70-P77, P8 0-P87, P100 -P107, P110-P117 High-level output voltage P31-P33 Low-level output voltage P00-P07, P1 0-P17, P20-P27, P30, P40-P47, P50-P57, P6 0-P67, P70-P77, P8 0-P87, P100 -P107, P110-P117 Low-level output voltage P31-P33 Hysteresis RDY, HOLD, TA0 IN-TA4IN, TA0 OUT-TA4OUT, TB0 IN-TB2IN, KI0-KI3, INT0-INT4 , NMI, ADTRG, CTS0, CTS1, CLK0, CLK1, RxD0, RxD1 Hysteresis RESET Hysteresis XIN High-level input current P00-P07 , P10-P1 7, P20-P27, P3 0-P33, P40-P47, P50-P57, P6 0-P67, P70-P77, P80-P87 , P100-P107 , P110-P117, XIN, RESET, BYTE, MD0, MD1, NMI Low-level input current P00-P07 , P10-P1 7, P20-P27, P3 0-P33, P40-P43, P50-P53, P6 0-P67, P70-P77, P80-P87 , P100-P107 , P110-P117, XIN, RESET, BYTE, MD0, MD1 Low-level input current P44-P47, P54-P5 7, NMI RAM hold voltage Power source current IOH = -1 mA IOH = -1 mA IOL = 1 mA Min. 2.5 Limits Typ. 0.5 V V 0.4 V 0.08 0.5 V 0.3 0.05 1 0.26 4 V V V -4 A -0.36 -4 -0.54 15.6 31.2 A mA V mA 1 A 2.6 VI = 3.3 V VI = 0 V 7902 Group User's Manual Unit V IOL = 1 mA VI = 0 V, No pullup transistor VI = 0 V, Pullup transistor used When clock is stoped. Output-only pins f(fsys) = 26 MHz. are open, and the CPU operates. other pins are connected to Vss or Vcc. An external Ta = 25 C when square-waveform clock is stopped. clock is input. (Pin XOUT is open.) The PLL frequency Ta = 85 C when multiplier stops its clock is stopped. operation. Max. -0.20 2 20 APPENDIX Appendix 10. M37902FGMHP electrical characteristics A-D CONVERTER CHARACTERISTICS (VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol Parameter ---------- Resolution VREF = VCC ---------- Absolute accuracy VREF = VCC Ladder resistance VREF = VCC RLADDER tCONV Conversion time VREF VIA Reference voltage Analog input voltage Limits Test conditions Min. Max. 10 3 2 10-bit resolution mode 8-bit resolution mode f(f sys) 26 MHz 10-bit resolution mode 8-bit resolution mode 5 4.54 1.89 (Note) 2.7 0 Unit Bits LSB LSB k s VCC VREF V V Note: This is applied when A-D conversion freguency ( AD) = f1. D-A CONVERTER CHARACTERISTICS (VCC = 3.3 V, V SS = AVSS = 0 V, VREF = 3.3 V, Ta = -20 to 85 C, unless otherwise noted) Symbol ---- ---- tsu RO IVREF Parameter Test conditions Resolution Absolute accuracy Set time Output resistance Reference power source input current Min. 1 Limits Typ. 2.5 (Note) Max. 8 1.0 3 4 3.2 Unit Bits % s k mA Note: The test conditions are as follows: * One D-A converter is used. * The D-A register value of the unused D-A converter is "0016 ." * The reference power source input current for the ladder resistance of the A-D converter is excluded. RESET INPUT Reset input timing requirements (VCC = 3.3 V 0.3 V, VSS = 0V, Ta = -20 to 85 C, unless otherwise noted) Symbol t w(RESETL) Parameter Min. 2 RESET input low-level pulse width Limits Typ. Max. Unit s RESET input tw(RESETL) 7902 Group User's Manual 21-131 APPENDIX Appendix 10. M37902FGMHP electrical characteristics PERIPHERAL DEVICE INPUT/OUTPUT TIMING (VCC = 3.3 V0.3 V, VSS = 0 V, Ta = -20 to 85 C, f(f sys) = 26 MHz unless otherwise noted) For limits depending on f(fsys), their calculation formulas are shown below. Also, the values at f(f sys) = 26 MHz are shown in ( ). Timer A input (Count input in event counter mode) Symbol tc(TA) tw(TAH) tw(TAL) Limits Parameter Min. 80 40 40 TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width Max. Unit ns ns ns Timer A input (Gating input in timer mode) Symbol Parameter tc(TA) TAiIN input cycle time f(fsys) 26 MHz tw(TAH) TAiIN input high-level pulse width f(fsys) 26 MHz tw(TAL) TAiIN input low-level pulse width f(fsys) 26 MHz Limits Min. 16 x 109 (615) f(f sys) 9 8 x 10 (307) f(f sys) 9 8 x 10 (307) f(f sys) Max. Unit ns ns ns Note : The TAiIN input cycle time requires 4 or more cycles of a count source. The TAiIN input high-level pulse width and the TAiIN input low-level pulse width respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f 2 at f(f sys) 26 MHz. Timer A input (External trigger input in one-shot pulse mode) Symbol Limits Parameter t c(TA) TAi IN input cycle time t w(TAH) t w(TAL) TAi IN input high-level pulse width TAi IN input low-level pulse width Min. f(fsys) 26 MHz 8 x 109 f(fsys) Max. (307) Unit ns 80 80 ns ns Timer A input (External trigger input in pulse width modulation mode) Symbol tw(TAH) tw(TAL) Parameter TAiIN input high-level pulse width TAiIN input low-level pulse width Limits Min. 80 80 Max. Unit ns ns Timer A input (Up-down input and Count input in event counter mode) Symbol t c(UP) t w(UPH) t w(UPL) t su(UP-TIN) t h(TIN-UP) 21-132 Parameter TAiOUT input cycle time TAiOUT input high-level pulse width TAiOUT input low-level pulse width TAiOUT input setup time TAiOUT input hold time 7902 Group User's Manual Limits Min. 2000 1000 1000 400 400 Max. Unit ns ns ns ns ns APPENDIX Appendix 10. M37902FGMHP electrical characteristics Timer A input (Two-phase pulse input in event counter mode) Symbol tc(TA) tsu(TAjIN-TAjOUT) tsu(TAjOUT-TAjIN) Limits Parameter Min. 800 200 200 TAiIN input cycle time TAjIN input setup time TAjOUT input setup time Max. Unit ns ns ns * Gating input in timer mode * Count input in event counter mode * External trigger input in one-shot pulse mode * External trigger input in pulse width modulation mode tc(TA) tw(TAH) TAiIN input tw(TAL) * Up-down and Count input in event counter mode tc(UP) tw(UPH) TAiOUT input (Up-down input) tw(UPL) TAiOUT input (Up-down input) th(TIN-UP) tsu(UP-TIN) TAiIN input (When count by falling) TAiIN input (When count by rising) * Two-phase pulse input in event counter mode tc(TA) TAjIN input tsu(TAjIN-TAjOUT) tsu(TAjIN-TAjOUT) tsu(TAjOUT-TAjIN) TAjOUT input tsu(TAjOUT-TAjIN) Test conditions * VCC = 3.3 V0.3 V, Ta = -20 to 85 C * Input timing voltage : VIL = 0.53 V, VIH = 1.65 V 7902 Group User's Manual 21-133 APPENDIX Appendix 10. M37902FGMHP electrical characteristics Timer B input (Count input in event counter mode) Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Parameter TBiIN input cycle time (one edge count) TBiIN input high-level pulse width (one edge count) TBiIN input low-level pulse width (one edge count) TBiIN input cycle time (both edge count) TBiIN input high-level pulse width (both edge count) TBiIN input low-level pulse width (both edge count) Timer B input Limits Min. 80 40 40 160 80 80 Max. Unit ns ns ns ns ns ns (Pulse period measurement mode) Symbol Parameter tc(TB) TBiIN input cycle time f(fsys ) 26 MHz tw(TBH) TBiIN input high-level pulse width f(fsys ) 26 MHz tw(TBL) TBiIN input low-level pulse width f(fsys ) 26 MHz Limits Min. 16 x 109 (615) f(fsys) 8 x 109 (307) f(fsys) 8 x 109 (307) f(fsys) Max. Unit ns ns ns Note: The TBiIN input cycle time requires 4 or more cycles of a count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f 2 at f(fsys) 26 MHz. Timer B input (Pulse width measurement mode) Symbol Parameter tc(TB) TBiIN input cycle time f(fsys ) 26 MHz tw(TBH) TBiIN input high-level pulse width f(fsys ) 26 MHz tw(TBL) TBiIN input low-level pulse width f(fsys ) 26 MHz Limits Min. 16 x 109 (615) f(fsys) 8 x 109 (307) f(fsys) 8 x 109 (307) f(fsys) Max. Unit ns ns ns Note: The TBiIN input cycle time requires 4 or more cycles of a count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f 2 at f(fsys) 26 MHz. A-D trigger input Symbol tc(AD) tw(ADL) 21-134 Parameter ADTRG input cycle time (minimum allowable trigger) ADTRG input low-level pulse width 7902 Group User's Manual Limits Min. 1000 125 Max. Unit ns ns APPENDIX Appendix 10. M37902FGMHP electrical characteristics Serial I/O Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) Limits Parameter Min. 200 100 100 CLKi input cycle time CLKi input high-level pulse width CLKi input low-level pulse width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Max. 80 0 20 90 Unit ns ns ns ns ns ns ns External interrupt (INTi) input, NMI input, Key input interrupt (KIi) input Symbol tw(INH) tw(INL) Limits Parameter Min. 250 250 INTi input/NMI input/KIi input high-level pulse width INTi input/NMI input/KIi input low-level pulse width Max. Unit ns ns tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input tc(CK) tw(CKH) CLKi input tw(CKL) th(C - Q) TxDi output td(C - Q) tsu(D - C) th(C - D) RxDi input tw(INL) INTi input, NMI input, KIi input tw(INH) Test conditions * Vcc = 3.3 V0.3 V, Ta = -20 to 85C * Input timing voltage : VIL = 0.53 V, VIH = 1.65 V *Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 50 pF 7902 Group User's Manual 21-135 APPENDIX Appendix 10. M37902FGMHP electrical characteristics READY, HOLD TIMING Timing requirements (VCC = 3.3 V0.3 V, VSS = 0 V, Ta = -20 to 85 C, f(fsys) = 26 MHz, unless otherwise noted) Symbol tsu(RDY-1) tsu(HOLD-1) th(1-RDY) th(1-HOLD) Parameter RDY input setup time HOLD input setup time RDY input hold time HOLD input hold time Switching characteristics Symbol td( 1-HLDAL) td(RDH-HLDAL) td(BXWH-HLDAL) tpxz(HLDAL-RDZ) tpxz(HLDAL-BXWZ) tpxz(HLDAL-CSiZ) tpxz(HLDAL-ALEZ) tpxz(HLDAL-AZ) tpzx(HLDAL-RDZ) tpzx(HLDAL-BXWZ) tpzx(HLDAL-CSiZ) tpzx(HLDAL-ALEZ) tpzx(HLDAL-AZ) Max. Unit ns ns ns ns (VCC = 3.3 V0.3 V, VSS = 0 V, Ta = -20 to 85 C, f(f sys) = 26 MHz, unless otherwise noted) Parameter HLDA output delay time HLDA low-level output delay time after read HLDA low-level output delay time after write Floating start delay time Floating start delay time Floating start delay time Floating start delay time Floating start delay time Floating release delay time Floating release delay time Floating release delay time Floating release delay time Floating release delay time Note: tc = 1/f(fsys). 21-136 Limits Min. 40 40 0 0 7902 Group User's Manual Limits Min. Max. 20 tc -15 (Note) tc -15 (Note) -15 -15 -15 -15 -15 0 0 0 0 0 10 10 10 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns APPENDIX Appendix 10. M37902FGMHP electrical characteristics RDY input 1 RD, BLW, BHW tsu (RDY-1) th (1-RDY) RDY input : Wait inserted by software (The above is applied when bus cycle = 1 + 2) : Wait inserted by ready function HOLD input 1 tsu (HOLD-1) th (1-HOLD) HOLD input td (1-HLDAL) td (1-HLDAL) HLDA output td (RDH-HLDAL) tpxz (HLDAL-RDZ) tpzx (HLDAL-RDZ) Hi-Z RD td (BXWH-HLDAL) tpxz (HLDAL-BXWZ) tpzx (HLDAL-BXWZ) Hi-Z BLW BHW tpxz (HLDAL-CSiZ) tpzx (HLDAL-CSiZ) Hi-Z CSi tpxz (HLDAL-ALEZ) tpzx (HLDAL-ALEZ) Hi-Z ALE tpxz (HLDAL-AZ) tpzx (HLDAL-AZ) Hi-Z A0-A23 output Test conditions * VCC = 3.3 V 0.3 V, Ta= -20 to 85 C * RDY input, HOLD input:VIL = 0.53 V, VIH = 1.65 V * HLDA output : VOL = 0.8V, VOH = 2.0 V, CL = 50 pF 7902 Group User's Manual 21-137 APPENDIX Appendix 10. M37902FGMHP electrical characteristics External bus timing For limits depending on f(fsys), their calculation formulas are shown below. Bus cycle 1 +1 1 +2 1 +3 2 +2 WH WL 1 1 1 2 1 2 3 2 Bus cycle WH WL 2 2 3 3 3 4 3 4 2 +3 2 +4 3 +3 3 +4 tc = 1/f(fsys). Timing Requirements (VCC = 3.3 V0.3 V, VSS = 0 V, Ta = -20 to 85 C, f(XIN) = 26 MHz, unless otherwise noted) Symbol tc(in) tw(harf) tw(H) tw(L) tr tf ta(A-D) ta(A-D) ta(CSiL-D) ta(RDL-D) tsu(D-RDL) th(RDH-D) ta(BA-D) th(BA-D) ta(LA-D) Limits Parameter Min. 38 0.45 tc 0.5 tc - 6 0.5 tc - 6 6 6 External clock input cycle time External clock input pulse width with half input-volage External clock input high-level pulse width External clock input low-level pulse width External clock input rise time External clock input fall time Address access time (the address output select bit = 0) Address access time (the address output select bit = 1) Chip select access time Read access time Read data setup time Data input hold time after read Address access time at burst ROM access Data hold time after address at burst ROM access Address access time (the multiplexed bus select bit = 1) Max. 0.55 tc (WH + WL) tc-45 (WH + WL-0.5) tc-35 (WH + WL-0.5) tc-35 WL tc-30 15 0 WL tc-35 8 (WH + WL-0.5)tc-35 (Note) Note: This is independent of the value of the address output select bit's contents. External clock input tw(L) tw(H) tr tf XIN Test conditions * Vcc = 3.3 V 0.3 V, Ta = -20 to 85 C * Input timing voltage : VIL = 0.66 V, VIH = 2.64 V (tw(H), tw(L), tr, tf) * Output timing voltage : 1.65 V (tc(in), tw(half)) 21-138 7902 Group User's Manual tc(in) tw(half) Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns APPENDIX Appendix 10. M37902FGMHP electrical characteristics Switching characteristics (VCC = 3.3 V0.3 V, VSS = 0 V, Ta = -20 to 85 C, f(fsys) = 26 MHz, unless otherwise noted) Symbol td(1-RDL) td(1-RDH) td(1-BXWL) td(1-BXWH) td(1L-CSiL) td(1L-CSiH) td(1H-A) td(1L-A) tw(ALEH) Parameter Read low-level output delay time Read high-level output delay time Write low-level output delay time Write high-level output delay time Chip select low-level output delay time Chip select high-level output delay time Address output delay time (the address output select bit = 0) Address output delay time (the address output select bit = 1) ALE pulse width Bus cycle = 1 + 1, 1 + 2, 1 + 3 Bus cycle = 2 + 2 Bus cycle = 2 + 3, 2 + 4, 3 + 3, 3 + 4 td(A-ALEL) tw(RDL) tw(RDH) td(RDH-BXWH) td(A-RDH) td(A-RDH) th(RDH-A) th(RDH-A) td(RDH-ALEL) td(ALEL-RDH) ALE completion delay time Bus cycle = 1 + 1, 1 + 2, 1 + 3 after address stabilization (when the address output Bus cycle = 2 + 2 select bit = 0) Bus cycle = 2 + 3, 2 + 4, 3 + 3, 3 + 4 ALE completion delay time Bus cycle = 1 + 1, 1 + 2, 1 + 3 after address stabilization Bus cycle = 2 + 2 (when the address output Bus cycle = 2 + 3, 2 + 4, 3 + 3, 3 + 4 select bit = 1) Read output pulse width Read output high-level width (Note 1) Write disable valid time after read (Note 2) Address valid time before read (when the address output select bit = 0) Address valid time before read (when the address output select bit = 1) Address hold time after read (when the address output select bit = 0) (Note 2) Address hold time after read (when the address output select bit = 1) (Note 2) ALE completion delay time after read start Read disable valid time Bus cycle = 2 + 2 after ALE completion Bus cycle = 3 + 3, 3 + 4 td(CSiL-RDH) td(CSiL-RDL) th(RDH-CSiL) td(RDH-D) tw(BXWL) tw(BXWH) td(BXWH-RDH) td(A-BXWH) td(A-BXWH) th(BXWH-A) th(BXWH-A) td(BXWH-ALEL) td(ALEL-BXWH) Chip select valid time before read Chip select output valid time before read completion Chip select hold time after read Next write cycle data output delay time after read (Note 2) Write output pulse width Write output high-level width (Note 1) Read disable valid time after write (Note 2) Address valid time before write (when the address output select bit = 0) Address valid time before write (when the address output select bit = 1) Address hold time after write (when the address output select bit = 0) (Note 2) Address hold time after write (when the address output select bit = 1) (Note 2) ALE completion delay time after write start Write disable valid time Bus cycle = 2 + 2 after ALE completion Bus cycle = 2 + 3, 2 + 4, 3 + 3, 3 + 4 td(CSiL-BXWH) td(CSiL-BXWL) th(BXWH-CSiL) td(D-BXWL) th(BXWH-D) tpxz(BXWH-DZ) Chip select valid time before write Chip select output valid time before write completion Chip select hold time after write Data output valid time before write completion Data hold time after write (Note 3) Floating start delay time after write (Note 3) Limits Min. -18 -18 -18 -18 -20 -22 -5 -20 Max. 0 0 0 0 0 10 25 16 Unit ns ns ns ns ns ns ns ns 0.5tc-19 tc-20 1.5tc-20 tc-30 1.5tc-30 ns ns 2tc-30 ns 0.5tc-19 tc-20 ns 1.5tc-20 ns WL tc-15 ns WH tc-15 ns tc-15 WH tc-30 ns (WH -0.5)tc-19 8 0.5tc-10 ns ns ns ns ns ns ns ns 20 0.5tc-19 tc-15 (WH -0.5)tc-19 (W H + WL-0.5)tc-20 0.5tc-14 tc-15 ns ns ns ns ns WL tc-15 WH tc-15 tc-15 WH tc-30 (WH -0.5)tc-19 8 0.5tc-10 20 0.5tc-19 tc-15 (WH -0.5)tc-19 (WH + WL-0.5)tc-20 0.5tc-14 WL tc-20 0.5tc-10 0.5tc + 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 1: When the bus cycle just before this parameter is for the area where the recovery cycle insertion is selected, this parameter is extended by tc (ns: one recovery cycle is inserted.) or by 2tc (ns: two recovery cycles are inserted.). 2: When accessing the area where the recovery cycle insertion is selected, this parameter is extended by tc (ns: one recovery cycle is inserted.) or by 2tc (ns: two recovery cycles are inserted.). 3: This parameter is extended by tc (ns) when both of the following conditions are satisfied: * When accessing the area where the recovery cycle insertion is selected. * When two recovery cycles are inserted. 7902 Group User's Manual 21-139 APPENDIX Appendix 10. M37902FGMHP electrical characteristics Switching characteristics (VCC = 3.3 V0.3 V, VSS = 0 V, Ta = -20 to 85 C, f(f sys) = 26 MHz, unless otherwise noted) Symbol td(LA-RDH) td(LA-ALEL) th(ALEL-LA) tpxz(RDH-LAZ) td(LA-BXWH) tpzx(RDH-DZ) Parameter Address valid time before read ALE completion delay time Bus cycle = 2 + 2 after address stabilization Bus cycle = 3 + 3, 3 + 4 Address hold time after Bus cycle = 2 + 2 ALE completion Bus cycle = 3 + 3, 3 + 4 Floating start delay time Address valid time before write Floating release delay time Note: This is independent of the address output select bit's contents. 21-140 7902 Group User's Manual Limits Min. (WH-0.5)tc-19 (Note) tc-20 (Note) 1.5tc-20 (Note) 0.5tc-19 tc-15 Max. 5 (WH-0.5)tc-19 (Note) 0.5tc-19 (Note) Unit ns ns ns ns ns ns ns ns APPENDIX Appendix 10. M37902FGMHP electrical characteristics Normal access: bus cycle = 1 + 1, 1 + 2, 1+ 3, 2 + 3, or 2 + 4 tc fsys Bus cycle <At read> td(1L-CSiL) td(1L-CSiH) 1 td(1H-A) td(1-RDL) tw(ALEH) td(1L-A) td(1-RDH) ALE td(A-ALEL) tw(RDH) tw(RDL) RD td(RDH-ALEL) td(RDH-BXWH) BLW BHW th(RDH-A) td(A-RDH) A0-A23 (when the address output select bit = 0) td(A-ALEL) td(A-RDH) th(RDH-A) A0-A23 (when the address output select bit = 1) td(CSiL-RDH) td(CSiL-RDL) th(RDH-CSiL) CSi ta(A-D) ta(A-D) ta(CSiL-D) ta(RDL-D) td(RDH-D) tsu(D-RDL) th(RDH-D) D0-D7, D8-D15 Test conditions * VCC = 3.3 V 0.3 V, Ta = -20 to 85 C * Input timing voltage : VIL=0.53 V, VIH=1.65 V * Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=15 pF (CSi) * Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=50 pF (except for CSi) 7902 Group User's Manual 21-141 APPENDIX Appendix 10. M37902FGMHP electrical characteristics Normal access: bus cycle = 1 + 1, 1 + 2, 1 + 3, 2 + 3, or 2 + 4 tc fsys <At write> Bus cycle td(1L-CSiL) td(1L-CSiH) 1 td(1H-A) td(1L-A) td(1-BXWL) tw(ALEH) td(1-BXWH) ALE td(A-ALEL) td(BXWH-RDH) RD tw(BXWH) tw(BXWL) BLW BHW td(A-BXWH) td(BXWH-ALEL) th(BXWH-A) A0-A23 (when the address output select bit = 0) td(A-ALEL) td(A-BXWH) A0-A23 (when the address output select bit = 1) td(CSiL-BXWH) td(CSiL-BXWL) th(BXWH-A) th(BXWH-CSiL) CSi td(D-BXWL) th(BXWH-D) D0-D7, D8-D15 tpxz(BXWH-DZ) Test conditions * VCC = 3.3 V 0.3 V, Ta = -20 to 85 C * Input timing voltage : VIL=0.53 V, VIH=1.65 V * Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=15 pF (CSi) * Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=50 pF (except for CSi) 21-142 7902 Group User's Manual APPENDIX Appendix 10. M37902FGMHP electrical characteristics Normal access: bus cycle = 2 + 2, 3 + 3, 3 + 4 tc fsys <At read> Bus cycle td(1L-CSiL) td(1L-CSiH) 1 td(1H-A) td(1L-A) tw(ALEH) td(1-RDL) td(1-RDH) td(ALEL-RDH) ALE td(A-ALEL) tw(RDH) tw(RDL) RD td(RDH-BXWH) BLW BHW A0-A23 (when the address output select bit = 0) A0-A23 (when the address output select bit = 1) td(A-RDH) th(RDH-A) td(A-ALEL) td(A-RDH) th(RDH-A) td(CSiL-RDH) td(CSiL-RDL) th(RDH-CSiL) CSi ta(A-D) ta(A-D) D0-D7, D8-D15 (when the multiplexed bus select bit = 0) ta(CSiL-D) ta(RDL-D) td(RDH-D) tsu(D-RDL) th(RDH-D) ta(RDL-D) tsu(D-RDL) th(RDH-D) td(LA-RDH) tpzx(RDH-DZ) ta(LA-D) LA0/D0-LA7/D7 (when the multiplexed bus select bit = 1, Note) Address td(LA-ALEL) Input data Address tpxz(RDH-LAZ) th(ALEL-LA) Note: Valid only when area CS2 is accessed with the external data bus width = 8 bits. Test conditions * VCC = 3.3 V 0.3 V, Ta = -20 to 85 C * Input timing voltage : VIL=0.53 V, VIH=1.65 V * Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=15 pF (CSi) * Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=50 pF (except for CSi) 7902 Group User's Manual 21-143 APPENDIX Appendix 10. M37902FGMHP electrical characteristics Normal access: bus cycle = 2 + 2, 3 + 3, 3 + 4 tc fsys <At write> Bus cycle td(1L-CSiL) 1 td(1H-A) td(1L-CSiH) td(1L-A) tw(ALEH) td(1-BXWH) td(1-BXWL) ALE td(ALEL-BXWH) td(A-ALEL) td(BXWH-RDH) RD tw(BXWH) tw(BXWL) BLW BHW th(BXWH-A) td(A-BXWH) A0-A23 (when the address output select bit = 0) A0-A23 (when the address output select bit = 1) td(A-ALEL) td(A-BXWH) th(BXWH-A) td(CSiL-BXWH) th(BXWH-CSiL) td(CSiL-BXWL) CSi td(D-BXWL) D0-D7, D8-D15 (when the multiplexed bus select bit = 0) td(D-BXWL) td(LA-BXWH) LA0/D0-LA7/D7 (when the multiplexed bus select bit = 1, Note) Address td(LA-ALEL) tpxz(BXWH-DZ) th(BXWH-D) Output data th(ALEL-LA) Note: Valid only when area CS2 is accessed with the external data bus width = 8 bits. Test conditions * VCC = 3.3 V 0.3 V, Ta = -20 to 85 C * Input timing voltage : VIL=0.53 V, VIH=1.65 V * Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=15 pF (CSi) * Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=50 pF (except for CSi) 21-144 th(BXWH-D) 7902 Group User's Manual tpxz(BXWH-DZ) 7902 Group User's Manual ta(A-D) ta(A-D) ta(RDL-D) ta(CSiL-D) td(CSiL-RDH) td(RDH-ALEL) ta(BA-D) th(BA-D) Test conditions * VCC = 3.3 V0.3 V, Ta = -20 to 85C * Input timing voltage : VIL=0.53 V, VIH=1.65 V * Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=15 pF (CSi) * Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=50 pF (except for CSi) D0-D7, D8-D15 CSi A0-A23 (when the address output select bit = 1) td(A-RDH) td(A-RDH) td(A-ALEL) td(A-ALEL) tw(RDH) A0-A23 (when the address output select bit = 0) BLW BHW RD ALE tw(ALEH) Burst ROM access: bus cycle = 1 + 1, 1 + 2, 1 + 3, 2 + 3, 2 + 4 th(BA-D) ta(BA-D) th(BA-D) ta(BA-D) th(RDH-D) th(RDH-CSiL) th(RDH-A) th(RDH-A) td(RDH-BXWH) APPENDIX Appendix 10. M37902FGMHP electrical characteristics 21-145 APPENDIX Appendix 11. Standard characteristics Appendix 11. Standard characteristics Standard characteristics described below are just examples of the M37902's characteristics and are not guaranteed. For each parameter's limits, refer to sections "Appendix 9. M37902FGCGP electrical characteristics" and "Appendix 10. M37902FGMHP electrical characteristics." 1. Programmable I/O port (CMOS output) standard characteristics: P0-P2, P3 0, P4, P10, P11 (1) P-channel I OH-VOH characteristics M37902FGCGP (Power source voltage: Vcc = 5 V) M37902FGMHP (Power source voltage: Vcc = 3.3 V) 30.0 20.0 IOH [mA] IOH [mA] Ta = 25 C Ta = 85 C 15.0 0 Ta = 25 C 10.0 1.0 2.0 3.0 4.0 0 5.0 Ta = 85 C 0.66 VOH [V] 1.32 1.98 VOH [V] 2.64 3.3 (2) N-channel I OL-V OL characteristics M37902FGCGP (Power source voltage: Vcc = 5 V) M37902FGMHP (Power source voltage: Vcc = 3.3 V) 30.0 IOL [mA] IOL [mA] 20.0 Ta = 25 C Ta = 25 C Ta = 85 C 15.0 0 10.0 1.0 2.0 3.0 4.0 5.0 0 VOL [V] 21-146 7902 Group User's Manual Ta = 85 C 0.66 1.32 1.98 VOL [V] 2.64 3.3 APPENDIX Appendix 11. Standard characteristics 2. Programmable I/O port (CMOS output) standard characteristics: P3 1-P33 (1) P-channel I OH-VOH characteristics M37902FGCGP (Power source voltage: Vcc = 5 V) M37902FGMHP (Power source voltage: Vcc = 3.3 V) Ta = 25 C 20.0 30.0 Ta = 85 C IOH [mA] IOH [mA] Ta = 25 C 10.0 15.0 0 Ta = 85 C 1.0 2.0 3.0 4.0 0 5.0 0.66 VOH [V] 1.32 1.98 VOH [V] 2.64 3.3 (2) N-channel IOL-V OL characteristics M37902FGCGP (Power source voltage: Vcc = 5 V) M37902FGMHP (Power source voltage: Vcc = 3.3 V) Ta = 25 C Ta = 85 C Ta = 25 C 20.0 IOL [mA] IOL [mA] 30.0 10.0 15.0 0 Ta = 85 C 1.0 2.0 3.0 4.0 5.0 0 VOL [V] 7902 Group User's Manual 0.66 1.32 1.98 VOL [V] 2.64 3.3 21-147 APPENDIX Appendix 11. Standard characteristics 3. Programmable I/O port (CMOS output) standard characteristics: P5-P8 (1) P-channel I OH-VOH characteristics M37902FGCGP (Power source voltage: Vcc = 5 V) M37902FGMHP (Power source voltage: Vcc = 3.3 V) 20.0 IOH [mA] IOH [mA] 30.0 Ta = 25 C 15.0 10.0 Ta = 85 C Ta = 25 C Ta = 85 C 0 1.0 2.0 3.0 4.0 0 5.0 0.66 VOH [V] 1.32 1.98 VOH [V] 2.64 3.3 (2) N-channel IOL-V OL characteristics M37902FGCGP (Power source voltage: Vcc = 5 V) M37902FGMHP (Power source voltage: Vcc = 3.3 V) 20.0 IOL [mA] IOL [mA] 30.0 Ta = 25 C 10.0 15.0 Ta = 25 C Ta = 85 C Ta = 85 C 0 1.0 2.0 3.0 4.0 5.0 0 VOL [V] 21-148 7902 Group User's Manual 0.66 1.32 1.98 VOL [V] 2.64 3.3 APPENDIX Appendix 11. Standard characteristics 4. Icc-f(XIN) standard characteristics M37902FGCGP 35.0 Measurement condition *Vcc = 5.0 V *Ta = 25 C *f(XIN) : square waveform input *single-chip mode *PLL frequency multiplier is stopped. *CPU and peripheral device is operated. *External clock input select bit = "1" In operating 30.0 Icc [mA] 25.0 20.0 15.0 10.0 5.0 0.0 At Wait mode 0 5 10 15 20 25 30 f(XIN) [MHz] M37902FGMHP 35.0 Measurement condition *Vcc = 3.3 V *Ta = 25 C *f(XIN ) : square waveform input *single-chip mode *PLL frequency multiplier is stopped. *CPU and peripheral device is operated. *External clock input select bit = "1" 30.0 Icc [mA] 25.0 20.0 In operating 15.0 10.0 5.0 0.0 At Wait mode 0 5 10 15 20 25 30 f(XIN) [MHz] 7902 Group User's Manual 21-149 APPENDIX Appendix 11. Standard characteristics 5. A-D converter standard characteristics The lower lines of the graph indicate the absolute precision errors. These are expressed as the deviation from the ideal value when the output code changes. For example, the change in M37902FGCGP's output code from 159 to 160 should occur at 797.5 mV, but the measured value is +1.3 mV. Accordingly, the measured point of change is 797.5 + 1.3 = 798.8 mV. The upper lines of the graph indicate the input voltage width for which the output code is constant. For example, the measured input voltage width for which the output code is 56 is 6.2 mV, so that the differential non-linear error is 6.2 - 5 = 1.2 mV (0.24 LSB). 21-150 7902 Group User's Manual APPENDIX Appendix 11. Standard characteristics 7.5 7.5 5.0 5.0 2.5 2.5 0.0 0.0 -2.5 -5.0 -7.5 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 1LSB WIDTH (mV) ERROR (mV) M37902FGCGP (Measurement conditions Vcc = 5.0 V, VREF = 5.12 V, f(fsys) = 26 MHz, Ta = 25 C, AD = f(fsys) divided by 2) 256 7.5 7.5 5.0 5.0 2.5 2.5 0.0 0.0 -2.5 -5.0 -7.5 256 272 288 304 320 336 352 368 384 400 416 432 448 464 480 496 1LSB WIDTH (mV) ERROR (mV) STEP No. 512 7.5 7.5 5.0 5.0 2.5 2.5 0.0 0.0 -2.5 -5.0 -7.5 512 528 544 560 576 592 608 624 640 656 672 688 704 720 736 752 1LSB WIDTH (mV) ERROR (mV) STEP No. 768 7.5 7.5 5.0 5.0 2.5 2.5 0.0 0.0 -2.5 -5.0 -7.5 768 784 800 816 832 848 864 880 896 912 928 944 960 976 992 1LSB WIDTH (mV) ERROR (mV) STEP No. 1008 1024 STEP No. : ERROR (mV) : 1LSB WIDTH (mV) 7902 Group User's Manual 21-151 APPENDIX Appendix 11. Standard characteristics 4.8 4.8 3.2 3.2 1.6 1.6 0.0 0.0 -1.6 -3.2 -4.8 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 1LSB WIDTH (mV) ERROR (mV) M37902FGMHP (Measurement conditions Vcc = 3.3 V, VREF = 3.3 V, f(fsys) = 26 MHz, Ta = 25 C, AD = f(fsys) divided by 2) 256 4.8 4.8 3.2 3.2 1.6 1.6 0.0 0.0 -1.6 -3.2 -4.8 256 272 288 304 320 336 352 368 384 400 416 432 448 464 480 496 1LSB WIDTH (mV) ERROR (mV) STEP No. 512 4.8 4.8 3.2 3.2 1.6 1.6 0.0 0.0 -1.6 -3.2 -4.8 512 528 544 560 576 592 608 624 640 656 672 688 704 720 736 752 1LSB WIDTH (mV) ERROR (mV) STEP No. 768 4.8 4.8 3.2 3.2 1.6 1.6 0.0 0.0 -1.6 -3.2 -4.8 768 784 800 816 832 848 864 880 896 912 928 944 960 976 992 1008 1024 STEP No. : ERROR (mV) : 1LSB WIDTH (mV) 21-152 7902 Group User's Manual 1LSB WIDTH (mV) ERROR (mV) STEP No. APPENDIX Appendix 12. Memory assignment of 7902 Group Appendix 12. Memory assignment of 7902 Group 1. M37902FJCGP/HP, M37902FJMHP Single-chip mode Memory expansion mode Microprocessor mode SFR area SFR area SFR area Internal RAM area (12 Kbytes) Internal RAM area (12 Kbytes) Internal RAM area (12 Kbytes) (Note 1) Internal flash memory area Internal flash memory area (User ROM area) (User ROM area) (498 Kbytes) (Note 2) (498 Kbytes) (Note 2) 016 FF16 10016 7FF16 80016 Unused area 37FF16 380016 7FFFF16 8000016 FEFFFF16 FF000016 Reserved area (Note 3) Reserved area (Note 3) FFFFFF16 : This is an external area. The access to this area enables the access to an externally-connected device. Notes 1: When the internal RAM area is followed by an external area, do not assign a program to the last 8 bytes of the internal RAM area. 2: Do not assign a program to the last 8 bytes of the internal ROM area. 3: Do not access this area. Fig. 13 Memory assigment of M37902FJCGP/HP, M37902FJMHP 7902 Group User's Manual 21-153 APPENDIX Appendix 12. Memory assignment of 7902 Group 2. M37902FHCGP/HP, M37902FHMHP Single-chip mode Memory expansion mode Microprocessor mode SFR area SFR area SFR area Internal RAM area (12 Kbytes) Internal RAM area (12 Kbytes) Internal RAM area (12 Kbytes) (Note 1) Internal flash memory area Internal flash memory area (User ROM area) (User ROM area) (370 Kbytes) (Note 2) (370 Kbytes) (Note 2) 016 FF16 10016 7FF16 80016 Unused area 37FF16 380016 5FFFF16 6000016 FEFFFF16 FF000016 Reserved area (Note 3) Reserved area (Note 3) FFFFFF16 : This is an external area. The access to this area enables the access to an externally-connected device. Notes 1: When the internal RAM area is followed by an external area, do not assign a program to the last 8 bytes of the internal RAM area. 2: Do not assign a program to the last 8 bytes of the internal ROM area. 3: Do not access this area. Fig. 14 Memory assigment of M37902FHCGP/HP, M37902FHMHP 21-154 7902 Group User's Manual APPENDIX Appendix 12. Memory assignment of 7902 Group 3. M37902FGCGP/HP, M37902FGMHP Single-chip mode Memory expansion mode Microprocessor mode 016 FF16 10016 7FF16 80016 1FFF16 200016 SFR area SFR area Internal RAM area (6 Kbytes) Internal RAM area (6 Kbytes) Internal RAM area Internal flash memory area Internal flash memory area (User ROM area) (User ROM area) (248 Kbytes) (Note 2) (248 Kbytes) (Note 2) SFR area Unused area (6 Kbytes) (Note 1) 3FFFF16 4000016 FEFFFF16 FF000016 Reserved area (Note 3) Reserved area (Note 3) FFFFFF16 : This is an external area. The access to this area enables the access to an externally-connected device. Notes 1: When the internal RAM area is followed by an external area, do not assign a program to the last 8 bytes of the internal RAM area. 2: Do not assign a program to the last 8 bytes of the internal ROM area. 3: Do not access this area. Fig. 15 Memory assigment of M37902FGCGP/HP, M37902FGMHP 7902 Group User's Manual 21-155 APPENDIX Appendix 12. Memory assignment of 7902 Group 4. M37902FECGP/HP, M37902FEMHP Single-chip mode Memory expansion mode Microprocessor mode 016 FF16 10016 7FF16 80016 1FFF16 200016 2FFFF16 SFR area SFR area Internal RAM area (6 Kbytes) Internal RAM area (6 Kbytes) Internal RAM area Internal flash memory area Internal flash memory area (User ROM area) (User ROM area) (184 Kbytes) (Note 2) (184 Kbytes) (Note 2) SFR area Unused area (6 Kbytes) (Note 1) 3000016 FEFFFF16 FF000016 FFFFFF16 Reserved area (Note 3) Reserved area (Note 3) : This is an external area. The access to this area enables the access to an externally-connected device. Notes 1: When the internal RAM area is followed by an external area, do not assign a program to the last 8 bytes of the internal RAM area. 2: Do not assign a program to the last 8 bytes of the internal ROM area. 3: Do not access this area. Fig. 16 Memory assigment of M37902FECGP/HP, M37902FEMHP 21-156 7902 Group User's Manual APPENDIX Appendix 12. Memory assignment of 7902 Group 5. M37902FCCGP/HP, M37902FCMHP Single-chip mode Memory expansion mode Microprocessor mode 016 FF16 10016 SFR area Unused area 7FF16 80016 Internal RAM area 17FF16 (4 Kbytes)(Note 1) 180016 1FFF16 Unused area 200016 Internal flash memory area 1FFFF16 SFR area SFR area Internal RAM area (4 Kbytes)(Note 1) Internal RAM area (4 Kbytes)(Note 1) Internal flash memory area (User ROM area) (User ROM area) (120 Kbytes) (Note 2) (120 Kbytes) (Note 2) 2000016 FEFFFF16 FF000016 Reserved area (Note 3) Reserved area (Note 3) FFFFFF16 : This is an external area. The access to this area enables the access to an externally-connected device. Notes 1: When the internal RAM area is followed by an unused area or an external area, do not assign a program to the last 8 bytes of the internal RAM area. 2: Do not assign a program to the last 8 bytes of the internal ROM area. 3: Do not access this area. Fig. 17 Memory assigment of M37902FCCGP/HP, M37902FCMHP 7902 Group User's Manual 21-157 APPENDIX Appendix 12. Memory assignment of 7902 Group 6. M37902F8CGP/HP, M37902F8MHP Single-chip mode Memory expansion mode SFR area SFR area SFR area Internal RAM area (2 Kbytes) Internal RAM area (2 Kbytes)(Note 1) Microprocessor mode 016 FF16 10016 Unused area 7FF16 80016 Internal RAM area (2 Kbytes) FFF16 100016 Internal flash memory area Internal flash memory area (User ROM area) FFFF16 (User ROM area) (60 Kbytes) (Note 2) (60 Kbytes) (Note 2) 1000016 FEFFFF16 FF000016 FFFFFF16 Reserved area (Note 3) Reserved area (Note 3) : This is an external area. The access to this area enables the access to an externally-connected device. Notes 1: When the internal RAM area is followed by an external area, do not assign a program to the last 8 bytes of the internal RAM area. 2: Do not assign a program to the last 8 bytes of the internal ROM area. 3: Do not access this area. Fig. 18 Memory assigment of M37902F8CGP/HP, M37902F8MHP 21-158 7902 Group User's Manual MITSUBISHI SEMICONDUCTORS USER'S MANUAL 7902 Group Rev. 2.0, Dec., 1999 Editioned by Committee of editing of Mitsubishi Semiconductor USER'S MANUAL Published by Mitsubishi Electric Corp., Semiconductor Marketing Division This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation. (c)1999 MITSUBISHI ELECTRIC CORPORATION User's Manual 7902 Group MITSUBISHI ELECTRIC CORPORATION HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN (c) 1999 MITSUBISHI ELECTRIC CORPORATION. New publication, effective sep. 1999. Specifications subject to change without notice.