7902 Group User’s Manual 21-129
APPENDIX
Appendix 10. M37902FGMHP electrical characteristics
Parameter
Power source voltage
Analog power source voltage
Power source voltage
Analog power source voltage
High-level input voltage XIN, RESET, BYTE, MD0, MD1
High-level input voltage P10–P17, P20–P27, P30–P33, P40–P47, P50–P57,
P60–P67, P70–P77, P80–P87, P100–P107, P110–P117
High-level input voltage P00–P07 (When the port P0 input level select bit = “0”)
High-level input voltage P00–P07 (When the port P0 input level select bit = “1”)
High-level input voltage D0–D7, D8–D15
High-level input voltage RDY, HOLD, TA0IN–TA4IN, TA0OUT–TA4OUT,
TB0IN–TB2IN, KI0–KI3, INT0–INT4, NMI, ADTRG, CTS0,
CTS1, CLK0, CLK1, RxD0, RxD1
High-level input voltage SCLK, SDA (Note 1)
Low-level input voltage XIN, RESET, BYTE, MD0, MD1
Low-level input voltage P10–P17, P20–P27, P30–P33, P40–P47, P50–P57,
P60–P67, P70–P77, P80–P87, P100–P107, P110–P117
Low-level input voltage P00–P07 (When the port P0 input level select bit = “0”)
Low-level input voltage P00–P07 (When the port P0 input level select bit = “1”)
Low-level input voltage D0–D7, D8–D15
Low-level input voltage RDY, HOLD, TA0IN–TA4IN, TA0OUT–TA4OUT,
TB0IN–TB2IN, KI0–KI3, INT0–INT4, NMI, ADTRG, CTS0,
CTS1, CLK0, CLK1, RxD0, RxD1
Low-level input voltage SCLK, SDA (Note 1)
High-level peak output current P00–P07, P10–P17, P20–P27, P30–P33, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87,
P100–P107, P110–P117
High-level average output current P00–P07, P10–P17, P20–P27, P30–P33,
P40–P47, P50–P57, P60–P67, P70–P77,
P80–P87, P100–P107, P110–P117
Low-level peak output current P00–P07, P10–P17, P20–P27, P30–P33,
P40–P47, P50–P57, P60–P67, P70–P77,
P80–P87, P100–P107, P110–P117
Low-level average output current P00–P07, P10–P17, P20–P27, P30–P33,
P40–P47, P50–P57, P60–P67, P70–P77,
P80–P87, P100–P107, P110–P117
External clock input frequency (Note 2)
System clock frequency
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
MHz
MHz
Max.
3.6
Vcc
VCC
Vcc
Vcc
Vcc
Vcc
Vcc
0.2 VCC
0.2 VCC
0.2 VCC
0.16 VCC
0.22 VCC
0.16 VCC
0.16 VCC
–10
–5
10
5
26
26
Symbol
VCC
AVCC
VSS
AVSS
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
VIL
VIL
IOH(peak)
IOH(avg)
IOL(peak)
IOL(avg)
f(XIN)
f(fsys)
RECOMMENDED OPERATING CONDITIONS (Vcc = 3.3 V, Ta = –20 to 85 °C, unless otherwise noted)
Notes 1: Pins SCLK and SDA are used only in the flash memory serial I/O mode.
2: When using the PLL frequency multiplier, be sure that f(fsys) = 26 MHz or less.
3: Average output current is the average value of an interval of 100 ms.
4: The sum of IOL(peak) for ports P0–P2, P8, P10, and P11 must be 80 mA or less, the sum of I OH(peak) for ports P0–P2, P8, P10, and P11 must be 80
mA or less, the sum of IOL(peak) for ports P3–P7 must be 80 mA or less, the sum of IOH(peak) for ports P3–P7 must be 80 mA or less.
Limits
Min.
3.0
0.8 Vcc
0.7 VCC
0.7 Vcc
0.5 Vcc
0.5 Vcc
0.5 Vcc
0.5 Vcc
0
0
0
0
0
0
0
Typ.
3.3
VCC
0
0