ADVANCED AND EVER ADVANCINGMITSUBISHI ELECTRIC
MITSUBISHI 16-BIT SINGLE-CHIP MICROCOMPUTER
7700 FAMILY / 7900 SERIES
7902
Group
User’s Manual
MITSUBISHI
ELECTRIC
Keep safety first in your circuit designs!
Notes regarding these materials
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor
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Rev. Rev.
No. date
1.0 First Edition. 990910
2.0 The following are revised/added points: 991220
(1) Corrections and Supplementary Explanation for 7902 Group User’s Manual (REV. A)
(2) “2. Remark” in “BEFORE USING THIS MANUAL”
<Rev.1.0>
Product expansion
Refer to the latest datasheet and catalog, or contact the appropriate office, as listed
in “CONTACT ADDRESSES FOR FURTHER INFORMATION” on the last page.
•••••••••
Development support tools
Refer to the “Mitsubishi Microcomputer Development Support Tools” Homepage
(http://www.tool-spt.mesc.co.jp/index_e.htm).
<Rev.2.0 and after>
Product expansion
Mitsubishi Microcomputers General Catalog
•••••••••
Development Support Tools
Datasheets
Microcomputers Development Support Tools Catalog
Microcomputers Development Support Tools Accessory Guide
Please Visit Our Web Site.
Mitsubishi MCU Technical Information (http://www.infomicom.mesc.co.jp/indexe.htm)
• Mitsubishi Microcomputer Development Support Tools
(http://www.tool-spt.mesc.co.jp/index_e.htm)
(3) Page 1-2
The item name has been changed. (The definition of this item is not changed.)
Operating temperature range Operating ambient temperature range
(4) Page 10-6, Figure 10.2.5/Functions
<Error>
When using this pin as timer Ai’s input pin, ••••
<Correction>
When using this pin as timer Bi’s input pin, ••••
(5) “Topr” in Page 21-110 and Page 21-128
The parameter name has been changed. (The definition of this parameter is not changed.)
Operating temperature Operating ambient temperature
REVISION DESCRIPTION LIST 7902 Group User’s Manual
(1/1)
Revision Description
(1/4)
Corrections and Supplementary Explanation for “7902 Group User’s Manual” (REV.A) No.1
Page Error Correction
P2-7
Figure 2.1.5,
P3-9
Figure 3.2.2,
P21-26
(Address 5F16)
Processor mode register 1 (Address 5F16)
Recovery-cycle-insert
number select bit
5: After reset, this bit can be set to “1” only once.
6: Make sure that a program to be used to change
this bit’s contents is allocated in the internal area.
7: In the microprocessor mode, •••• reprogramming
mode.”)
7Internal ROM bus cycle
select bit (Note 6)
5: After reset, this bit can be set only once.
6: In the microprocessor mode, •••• reprogramming
mode.”)
Processor mode register 1 (Address 5F16)
6 Recovery-cycle-insert
number select bit (Note 6)
7Internal ROM bus cycle
select bit (Note 7)
P3-10
Last line and bit 6 at addresses 8016, 8216, 8416, or 8616)
must be set to “1.” and bit 6 at address 8016, 8216, 8416, or 8616) must
be set to “1.”
Make sure that a program to be used to change
this bit’s contents is allocated in the internal area.
P3-32
Figure 3.2.18 Burst ROM access
φ1
RD
BLW, BHW
Burst ROM access
φ1
RD
P5-6
First line Figure 5.2.2 shows •••, and Figure 5.2.3 shows the
procedure for setting or changing the PLL multipli-
cation ratio.
Figure 5.2.2 shows •••, and Figure 5.2.3 shows the
setting procedure for the clock control register when
using the PLL frequency multiplier.
P5-8
Figure 5.2.3 Fig. 5.2.3 Procedure for setting or changing PLL
multiplication ratio Fig. 5.2.3 Setting procedure for clock control
register when using PLL frequency multiplier
6
(2/4)
Corrections and Supplementary Explanation for “7902 Group User’s Manual” (REV.A) No.2
Correction
P9-35
Figure 9.6.1,
P21-20
(Addresses
5616 to 5A16)
Timer Ai mode register (i = 0 to 4) (Addresses 5616
to 5A16)
3 Trigger
select bits Writing “1” to one-shot
start bit (•••)
4
0 0 :
0 1 :
1 0 :
1 1 :
b4 b3
P5-8
Figure 5.2.3 (Revised figure)
Page Error Correction
Page
(Note 2)
Notes 1: After reset, these bits are allowed to be changed only once. If it is
necessary to write a certain value to these bits, be sure to write the
same value that has been written after the latest reset.
2: This decision is unnecessary if “double” is selected and the period of
RESET = “L” is “the oscillation stabilizing time of an oscillator + 2 ms”
or more.
b0 Clock control register (Address BC16)
b7
PLL multiplication ratio select bits
(Note 1)
0 1 : Double
1 0 : Triple
1 1 : Quadruple
00 1
b3 b2
System clock select bit
0 : fXIN
2 ms elapsed ?
b0 Clock control register (Address BC16)
b7 10 1
System clock select bit
0 : fPLL
Setting of system clock select bit to “1.”
N
Y
PLL frequency multiplier is active,
and pin VCONT is valid.
1
1
P5-11
[Precautions for
clock generating
circuit]
Last line
••• (bits 2, 3 at address BC16). (See Figure 5.2.3.) ••• (bits 2, 3 at address BC16). (See Figure 5.2.3.)
After reset, the PLL multiplication ratio select bits
are allowed to be changed only once. If it is nece-
ssary to write a certain value to these bits, be sure
to write the same value that has been written after
the latest reset.
Timer Ai mode register (i = 0 to 4) (Addresses 5616
to 5A16)
3 Trigger
select bits Writing “1” to count start
bit (•••)
4
0 0 :
0 1 :
1 0 :
1 1 :
b4 b3
P12-6
Figure 12.2.3,
P21-14
(Addresses
3416, 3C16)
Notes 1: Valid when the CTS/RTS enable bit
(bit 4) is “0.” Notes 1: Valid when the CTS/RTS enable bit (bit 4)
is “0” and CTSi/RTSi separate select bit
(bit 0 or 1 at address AC16) is “0.”
(3/4)
Corrections and Supplementary Explanation for “7902 Group User’s Manual” (REV.A) No.3
P12-17
Figure 12.2.13,
P21-41
(Address AC16)
Serial I/O pin control register (Address AC16)
Bit Bit name Function
0 CTS0/RTS0 separate select bit
CTS1/RTS1 separate select bit
P12-23
12.3.3 line 13,
P12-28
12.3.5 line 12,
P12-40
12.4.3 line 12,
P12-47
12.4.5 line 6
By connecting the RTS pin (receiver side) and
CTS pin (transmitter side), •••
Page CorrectionError
Serial I/O pin control register (Address AC16)
Bit Bit name Function
0 CTS0/RTS0 separate select bit (Note)
1 CTS1/RTS1 separate select bit (Note)
Note: Valid when the CTS/RTS enable bit (bit 4 at
addresses 3416 and 3C16) is “0.”
By connecting the RTSi pin (receiver side) and
CTSi pin (transmitter side), •••
1
P14-3
Figure 14.2.3,
P21-37
(Addresses
9816 to 9A16)
D-A register i (i = 0 to 2) (Addresses 9816 to 9A16)
Bit Function
7 to 0 Any value from 0016 through FF16 can be set,
and this value is D-A converted and is output.
P14-3
Figure 14.2.2,
P21-37
(Address 9616)
D-A control register (Address 9616)
Bit Bit name Function
0 D-A0 output enable
bit
1 D-A1 output enable
bit
Note: Pin DAi is multiplexed ••••• (including programm-
able I/O port pin).
2 D-A2 output enable
bit
0 : Output is disabled.
1 : Output is enabled. (Note)
0 : Output is disabled.
1 : Output is enabled. (Note)
0 : Output is disabled.
1 : Output is enabled. (Note)
Notes 1: Pin DAi is multiplexed ••••• (including progra-
mmable I/O port pin).
2: When not using the D-A converter, be sure to
clear the contents of this bit to “0.”
Note: When not using the D-A converter, be sure to
clear the contents of these bits to “0016.”
P14-7
[Precautions for
D-A converter]
Last line
any other multiplexed input/output pin (including
programmable I/O port pin).
4. When not using the D-A converter, be sure to do
as follows:
•Clear the D-Ai (i = 0 to 2) output enable bit (bits
0 to 2 at address 9616) to “0.”
•Clear the contents of the D-A register i (addre-
sses 9816 to 9A16) to “0016.”
any other multiplexed input/output pin (including
programmable I/O port pin).
D-A control register (Address 9616)
Bit Bit name Function
0 D-A0 output enable
bit
1 D-A1 output enable
bit
2 D-A2 output enable
bit
0 : Output is disabled.
1 : Output is enabled. (Notes 1, 2)
0 : Output is disabled.
1 : Output is enabled. (Notes 1, 2)
0 : Output is disabled.
1 : Output is enabled. (Notes 1, 2)
D-A register i (i = 0 to 2) (Addresses 9816 to 9A16)
Bit Function
7 to 0 Any value from 0016 through FF16 can be set
(Note), and this value is D-A converted and is
output.
P16-2
Table 16.1.1 Item Stop mode
PLL frequency multiplier
fCPU, fBIU Operates.
Inactive.
Item Stop mode
PLL frequency multiplier
φCPU, φBIU Stopped.
Inactive.
(4/4)
Corrections and Supplementary Explanation for 7902 Group User s Manual (REV.A ) No.4
P18-8
Figure 18.3.2,
P18-9
Figure 18.3.3 STAB A, LG : 0h (Note 3)
RTI
RTI
3. Make sure that this instruction is executed in the ab-
solute long addressing mode. The above is just an
example. In an actual programming, be sure to refer
to the format of the assembler description to be used.
ErrorPage Correction
P21-95
Last line Note 21. Do not use the SEP •••• SEI instruction.)
Note 22. Be sure to keep flag I = “1” when execu-
ting the PLP or PUL instruction. Also, be
sure to use the SEI instruction when sett-
ing flag I to “1.”
P21-80
PLP PLP PLP
(Note 22)
P21-82
PUL PUL
(Note 18) PUL
(Notes 18 and 22)
Note 21. Do not use the SEP •••• SEI instruction.)
This manual describes the hardware of the Mitsubishi
CMOS 16-bit microcomputers 7902 Group. After
reading this manual, the user will be able to understand
the functions, so that they can utilize their capabilities
fully.
For details of software, refer to the “7900 Series Software
Manual.”
For details of development support tools, refer to the
“Mitsubishi Microcomputer Development Support Tools”
Homepage (http://www.tool-spt.mesc.co.jp/index_e.htm).
Preface
1
BEFORE USING THIS MANUAL
1. Constitution
This user’s manual consists of the following chapters. Refer to the chapters relevant to the products and
processor mode.
In this manual, “M37902” means all of or one of the 7902 Group products, unless otherwise noted. Each
chapter, except for Chapter 20, describes functions of the 7902 Group product at MD1 = Vss level.
Chapter 1. DESCRIPTION to Chapter 18. DEBUG FUNCTION (Except for Chapter 3)
Functions which are common to all products and all processor modes are described.
Chapter 3. CONNECTION WITH EXTERNAL DEVICES
Functions used for connection with external devices in the memory expansion and microprocessor
modes are explained.
Chapter 19. APPLICATIONS
Connection examples with external devices are described.
Chapter 20. FLASH MEMORY VERSION
Characteristics information for the flash memory version is described.
Appendix
Practical information for using the 7902 Group is described.
2. Remark
Product expansion
Mitsubishi Microcomputers General Catalog
Electrical characteristics
Refer to the latest datasheet.
Software
Refer to the “7900 Series Software Manual.”
Development support tools
Datasheets
Microcomputers Development Support Tools Catalog
Microcomputers Development Support Tools Accessory Guide
Please Visit Our Web Site.
• Mitsubishi MCU Technical Information (http://www.infomicom.mesc.co.jp/indexe.htm)
• Mitsubishi Microcomputer Development Support Tools (http://www.tool-spt.mesc.co.jp/index_e.htm)
3. Signal levels in Figure
As a rule, signal levels in each operation example and timing diagram are as follows.
• Signal levels
The upper line indicates “1,” and the lower line indicates “0.”
• Input/Output levels of pin
The upper line indicates “H,” and the lower line indicates “L.”
Foe the exception, the level is shown on the left side of a signal.
2
4. Register structure
The view of the register structure is described below:
XXX register (address XX16)
0
1
2
3
4
5
6
7
• • • select bit
• • • select bit
• • • flag
Fix this bit to “0.”
This bit is invalid in … mode.
Nothing is assigned.
The value is “0” at reading.
b7 b6 b5 b4 b3 b2 b1 b0
0 : …
1 : …
0 : …
1 : …
The value is “0” at reading.
0X
0 0 : …
0 1 : …
1 0 : …
1 1 : …
b2 b1
12
3
5
Undefined
0
0
0
0
0
Undefined
0
6
WO
RW
RW
RO
RW
RW
1Blank : Set to “0” or “1” according to the usage.
0 : Set to “0” at writing.
1 : Set to “1” at writing.
: Invalid depending on the mode or state. It may be “0” or “1.”
: Nothing is assigned.
20 : “0” immediately after reset.
1 : “1” immediately after reset.
Undefined : Undefined immediately after reset.
3RW : It is possible to read the bit state at reading. The written value becomes valid.
RO : It is possible to read the bit state at reading. The written value becomes
invalid. Accordingly, the written
value may be “0” or “1.”
WO : The written value becomes valid. It is impossible to read the bit state. The value is undefined at reading.
However, when [“0” at reading”] is indicated in the “Function” or “Note” column, the bit is always “0” at
reading. (See5 above.)
: It is impossible to read the bit state. The value is undefined at reading.
However, when [“0” at reading”] is indicated in the “Function” or “Note” column, the bit is always “0” at
reading. (See6 above.)
The written value becomes invalid. Accordingly, the written value may be “0” or “1.”
4Invalid for that function or mode.
Bit nameBit Function At reset R/W
4
7902 Group User’s Manual i
Table of contents
Table of contents
CHAPTER 1. DESCRIPTION
1.1 Performance overview ..........................................................................................................1-2
1.2 Pin configuration ................................................................................................................... 1-3
1.3 Pin description ....................................................................................................................... 1-5
1.4 Block diagram ........................................................................................................................1-9
CHAPTER 2. CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit (CPU) ........................................................................................... 2-2
2.1.1 Accumulator (Acc) ..........................................................................................................2-3
2.1.2 Index register X (X)....................................................................................................... 2-3
2.1.3 Index register Y (Y)....................................................................................................... 2-3
2.1.4 Stack pointer (S)............................................................................................................ 2-4
2.1.5 Program counter (PC) ................................................................................................... 2-5
2.1.6 Program bank register (PG) ......................................................................................... 2-5
2.1.7 Data bank register (DT) ................................................................................................ 2-5
2.1.8 Direct page register 0 to 3 (DPR0 to DPR3) ............................................................ 2-6
2.1.9 Processor status register (PS) ..................................................................................... 2-8
2.2 Bus interface unit (BIU).....................................................................................................2-10
2.2.1 Instruction prefetch ......................................................................................................2-11
2.2.2 Data Transfer (read and write) ..................................................................................2-14
2.3 Access space .......................................................................................................................2-18
2.4 Memory assignment ............................................................................................................2-19
2.4.1 Memory assignment in internal area.........................................................................2-19
2.5 Processor modes .................................................................................................................2-22
2.5.1 Single-chip mode..........................................................................................................2-23
2.5.2 Memory expansion and Microprocessor modes .......................................................2-23
2.5.3 Setting of processor mode..........................................................................................2-25
[Precautions for setting of processor mode] ...................................................................... 2-27
CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES
3.1 Signals required for accessing external devices .......................................................... 3-2
3.2 Chip select wait controller.................................................................................................. 3-7
3.2.1 Related registers ............................................................................................................ 3-8
3.2.2 External bus operations ..............................................................................................3-23
3.2.3 Setting method .............................................................................................................3-30
3.2.4. Address output selection............................................................................................3-31
[Precautions for CSWC] ............................................................................................................3-33
3.3 Ready function.....................................................................................................................3-34
3.3.1 Operation description...................................................................................................3-35
3.4 Hold function........................................................................................................................3-36
3.4.1 Operation description...................................................................................................3-37
7902 Group User’s Manual
ii
Table of contents
CHAPTER 4. RESET
4.1 Reset operation ......................................................................................................................4-2
4.1.1 Hardware reset ...............................................................................................................4-2
4.1.2 Software reset ................................................................................................................4-3
4.1.3 Power-on reset ...............................................................................................................4-4
4.2 Pin state ..................................................................................................................................4-5
4.3 State of internal area............................................................................................................4-6
4.4 Internal processing sequence after reset ......................................................................4-13
CHAPTER 5. CLOCK GENERATING CIRCUIT
5.1 Oscillation circuit examples ...............................................................................................5-2
5.1.1 Connection example with resonator/oscillator............................................................ 5-2
5.1.2 Externally generated clock input example.................................................................. 5-2
5.1.3 Connection example of filter circuit.............................................................................5-3
5.2 Clocks ...................................................................................................................................... 5-4
5.2.1 Clocks generated in clock generating circuit .............................................................5-5
5.2.2 Clock control register .....................................................................................................5-6
5.2.3 Particular function select register 0.............................................................................5-9
[Precautions for clock generating circuit] ...........................................................................5-11
CHAPTER 6. INPUT/OUTPUT PINS
6.1 Overview ..................................................................................................................................6-2
6.2 Programmable I/O ports .......................................................................................................6-2
6.2.1 Direction register ............................................................................................................6-3
6.2.2 Port register ....................................................................................................................6-4
6.2.3 Selectable functions.......................................................................................................6-7
6.3 Examples of handling unused pins .................................................................................. 6-8
6.3.1 In the single-chip mode.................................................................................................6-8
6.3.2 In memory expansion and microprocessor modes.................................................... 6-9
CHAPTER 7. INTERRUPTS
7.1 Overview ..................................................................................................................................7-2
7.2 Interrupt sources ................................................................................................................... 7-4
7.3 Interrupt control .....................................................................................................................7-8
7.3.1 Interrupt disable flag (I) ................................................................................................ 7-8
7.3.2 Interrupt request bit .......................................................................................................7-8
7.3.3 Interrupt priority level select bits and Processor interrupt priority level (IPL) ......7-5
7.4 Interrupt priority level ........................................................................................................7-10
7.5 Interrupt priority level detection circuit .........................................................................7-11
7.6 Interrupt priority level detection time ............................................................................7-13
7.7 Sequence from acceptance of interrupt request until execution of interrupt routine... 7-14
7.7.1 Change in IPL at acceptance of interrupt request..................................................7-15
7.7.2 Push operation for registers.......................................................................................7-16
7.8 Return from interrupt routine...........................................................................................7-17
7.9 Multiple interrupts ...............................................................................................................7-17
7902 Group User’s Manual iii
Table of contents
7.10 External interrupts ............................................................................................................7-19
7.10.1 NMI interrupt...............................................................................................................7-19
7.10.2 INTi interrupt ...............................................................................................................7-19
7.10.3 Functions of INTi interrupt request bit ....................................................................7-23
7.10.4 Switching of INTk to (k = 0 to 2) interrupt request occurrence factor ...............7-24
[Precautions for interrupts] .....................................................................................................7-25
CHAPTER 8. KEY INPUT INTERRUPT
8.1 Overview .................................................................................................................................. 8-2
8.2 Block description .................................................................................................................. 8-3
8.2.1 External interrupt input control register ......................................................................8-4
8.2.2 INT3 interrupt control register....................................................................................... 8-5
8.2.3 Port P5 direction register .............................................................................................. 8-6
8.3 Initial setting example for related registers ................................................................... 8-7
CHAPTER 9. TIMER A
9.1 Overview .................................................................................................................................. 9-2
9.2 Block description .................................................................................................................. 9-3
9.2.1 Counter and Reload register (timer Ai register)........................................................ 9-4
9.2.2 Timer A clock division select register......................................................................... 9-5
9.2.3 Count start register........................................................................................................9-6
9.2.4 Timer Ai mode register .................................................................................................9-6
9.2.5 Timer Ai interrupt control register................................................................................9-7
9.2.6 Port P5 and port P6 direction registers......................................................................9-8
9.3 Timer mode............................................................................................................................. 9-9
9.3.1 Setting for timer mode ................................................................................................9-11
9.3.2 Operation in timer mode .............................................................................................9-12
9.3.3 Select function..............................................................................................................9-13
[Precautions for timer mode] ..................................................................................................9-15
9.4 Event counter mode ...........................................................................................................9-16
9.4.1 Setting for event counter mode .................................................................................9-19
9.4.2 Operation in event counter mode ..............................................................................9-21
9.4.3 Switching between countup and countdown ............................................................9-22
9.4.4 Selectable functions .....................................................................................................9-23
[Precautions for event counter mode] ..................................................................................9-25
9.5 One-shot pulse mode .........................................................................................................9-26
9.5.1 Setting for one-shot pulse mode ...............................................................................9-28
9.5.2 Trigger ...........................................................................................................................9-30
9.5.3 Operation in one-shot pulse mode ............................................................................9-31
[Precautions for one-shot pulse mode] ................................................................................9-33
9.6 Pulse width modulation (PWM) mode ............................................................................9-34
9.6.1 Setting for PWM mode ................................................................................................9-36
9.6.2 Trigger ...........................................................................................................................9-38
9.6.3 Operation in PWM mode.............................................................................................9-39
[Precautions for pulse width modulation (PWM) mode] ...................................................9-43
7902 Group User’s Manual
iv
Table of contents
CHAPTER 10. TIMER B
10.1 Overview ..............................................................................................................................10-2
10.2 Block description ..............................................................................................................10-2
10.2.1 Counter and Reload register (timer Bi register) ....................................................10-3
10.2.2 Count start register....................................................................................................10-4
10.2.3 Timer Bi mode register .............................................................................................10-4
10.2.4 Timer Bi interrupt control register............................................................................10-5
10.2.5 Port P6 direction register ..........................................................................................10-6
10.2.6 Count source (in timer mode and pulse period/pulse width measurement mode) .....10-6
10.3 Timer mode .........................................................................................................................10-7
10.3.1 Setting for timer mode ..............................................................................................10-9
10.3.2 Operation in timer mode .........................................................................................10-10
[Precautions for timer mode] ................................................................................................10-11
10.4 Event counter mode .......................................................................................................10-12
10.4.1 Count source ............................................................................................................10-14
10.4.2 Setting for event counter mode .............................................................................10-15
10.4.3 Operation in event counter mode..........................................................................10-16
[Precautions for event counter mode] ................................................................................10-17
10.5 Pulse period/Pulse width measurement mode .........................................................10-18
10.5.1 Setting for pulse period/pulse width measurement mode ..................................10-20
10.5.2 Operation in pulse period/pulse width measurement mode...............................10-21
[Precautions for pulse period/pulse width measurement mode]..................................10-23
CHAPTER 11. REAL-TIME OUTPUT
11.1 Overview ..............................................................................................................................11-2
11.2 Block description ..............................................................................................................11-4
11.2.1 Real-time output control register .............................................................................11-4
11.2.2 Pulse output data registers 0 and 1 .......................................................................11-5
11.2.3 Port P5 direction register ..........................................................................................11-6
11.2.4 Timers A0 and A2......................................................................................................11-6
11.3 Setting of real-time output ..............................................................................................11-7
11.4 Real-time output operation ...........................................................................................11-10
CHAPTER 12. SERIAL I/O
12.1 Overview ..............................................................................................................................12-2
12.2 Block description ..............................................................................................................12-3
12.2.1 UARTi transmit/receive mode register ....................................................................12-4
12.2.2 UARTi transmit/receive control register 0...............................................................12-6
12.2.3 UARTi transmit/receive control register 1...............................................................12-8
12.2.4 UARTi transmit register and UARTi transmit buffer register .............................12-10
12.2.5 UARTi receive register and UARTi receive buffer register ................................12-12
12.2.6 UARTi baud rate register (BRGi)...........................................................................12-14
12.2.7 UARTi transmit interrupt control and UARTi receive interrupt control registers. 12-15
12.2.8 Serial I/O pin control register.................................................................................12-17
12.2.9 Port P8 direction register ........................................................................................12-18
12.2.10 CTS/RTS function ..................................................................................................12-19
12.3 Clock synchronous serial I/O mode ...........................................................................12-20
12.3.1 Transfer clock (Synchronizing clock).....................................................................12-20
12.3.2 Transfer data format................................................................................................12-22
7902 Group User’s Manual v
Table of contents
12.3.3 Method of transmission ...........................................................................................12-23
12.3.4 Transmit operation ...................................................................................................12-26
12.3.5 Method of reception.................................................................................................12-28
12.3.6 Receive operation ....................................................................................................12-31
12.3.7 Processing on detecting overrun error..................................................................12-34
[Precautions for clock synchronous serial I/O mode] ....................................................12-35
12.4 Clock asynchronous serial I/O (UART) mode ...........................................................12-36
12.4.1 Transfer rate (Frequency of transfer clock) .........................................................12-37
12.4.2 Transfer data format................................................................................................12-39
12.4.3 Method of transmission ...........................................................................................12-40
12.4.4 Transmit operation ...................................................................................................12-44
12.4.5 Method of reception.................................................................................................12-47
12.4.6 Receive operation ....................................................................................................12-50
12.4.7 Processing on detecting error ................................................................................12-52
12.4.8 Sleep mode ...............................................................................................................12-53
[Precautions for clock asynchronous serial I/O (UART) mode]....................................12-54
CHAPTER 13. A-D CONVERTER
13.1 Overview..............................................................................................................................13-2
13.2 Block description ..............................................................................................................13-3
13.2.1 A-D control register 0, 1...........................................................................................13-4
13.2.2 A-D register i (i = 0 to 7).........................................................................................13-8
13.2.3 A-D conversion interrupt control register ................................................................13-9
13.2.4 Port P7 direction register........................................................................................13-10
13.3 A-D conversion method.................................................................................................13-11
13.4 Absolute accuracy and Differential non-linearity error..........................................13-14
13.4.1 Absolute accuracy....................................................................................................13-14
13.4.2 Differential non-linearity error .................................................................................13-15
13.5 Comparison voltage in 8-bit resolution mode..........................................................13-16
13.6 One-shot mode.................................................................................................................13-17
13.6.1 Settings for one-shot mode ....................................................................................13-17
13.6.2 One-shot mode operation .......................................................................................13-18
13.7 Repeat mode.....................................................................................................................13-19
13.7.1 Settings for repeat mode ........................................................................................13-19
13.7.2 Repeat mode operation ...........................................................................................13-20
13.8 Single sweep mode.........................................................................................................13-21
13.8.1 Settings for single sweep mode ............................................................................13-21
13.8.2 Single sweep mode operation ................................................................................13-22
13.9 Repeat sweep mode .......................................................................................................13-23
13.9.1 Settings for repeat sweep mode ............................................................................13-23
13.9.2 Repeat sweep mode operation ..............................................................................13-24
[Precautions for A-D converter]............................................................................................13-25
CHAPTER 14. D-A CONVERTER
14.1 Overview..............................................................................................................................14-2
14.2 Block description ..............................................................................................................14-2
14.2.1 D-A control register ...................................................................................................14-3
14.2.2 D-A Register i (i = 0 to 2)........................................................................................14-3
14.2.3 A-D control register 1 ................................................................................................14-4
7902 Group User’s Manual
vi
Table of contents
14.3 D-A conversion method ...................................................................................................14-5
14.4 Setting method .................................................................................................................14-6
14.5 Operation description .......................................................................................................14-6
[Precautions for D-A converter]..............................................................................................14-7
CHAPTER 15. WATCHDOG TIMER
15.1 Block description ..............................................................................................................15-2
15.1.1 Watchdog timer ..........................................................................................................15-3
15.1.2 Watchdog timer frequency select register ..............................................................15-3
15.1.3 Particular function select register 2.........................................................................15-4
15.2 Operation description .......................................................................................................15-5
15.2.1 Basic operation ...........................................................................................................15-5
15.2.2 Stop period .................................................................................................................15-7
15.2.3 Operations in stop mode ..........................................................................................15-7
[Precautions for watchdog timer] ...........................................................................................15-8
CHAPTER 16. STOP AND WAIT MODES
16.1 Overview ..............................................................................................................................16-2
16.2 Block description ..............................................................................................................16-3
16.2.1 Particular function select register 0.........................................................................16-4
16.2.2 Particular function select register 1.........................................................................16-6
16.2.3 Watchdog timer frequency select register ..............................................................16-7
16.3 Stop mode ...........................................................................................................................16-8
16.3.1 Terminate operation at interrupt request occurrence (when using watchdog timer) ...16-8
16.3.2
Terminate operation at interrupt request occurrence (when not using watchdog timer)
16-9
16.3.3 Terminate operation at hardware reset.................................................................16-11
16.4 Wait mode .........................................................................................................................16-12
16.4.1 Terminate operation at interrupt request occurrence..........................................16-12
16.4.2 Terminate operation at hardware reset.................................................................16-12
CHAPTER 17. POWER SAVING FUNCTION
17.1 Overview ..............................................................................................................................17-2
17.1.1 Particular function select register 0.........................................................................17-3
17.1.2 Particular function select register 1.........................................................................17-5
17.2
Bus fixation in stop and wait modes.............................................................................
17-6
17.3
Stop of system clock in wait mode ...............................................................................
17-8
17.4 Stop of oscillation circuit................................................................................................17-9
17.5 Pin VREF disconnection .....................................................................................................17-9
CHAPTER 18. DEBUG FUNCTION
18.1 Overview ..............................................................................................................................18-2
18.2 Block description ..............................................................................................................18-2
18.2.1 Debug control register 0 ...........................................................................................18-3
18.2.2 Debug control register 1 ...........................................................................................18-4
18.2.3 Address compare registers 0 and 1 ........................................................................18-5
18.3 Address matching detection mode ...............................................................................18-6
18.3.1 Setting procedure for address matching detection mode.....................................18-6
7902 Group User’s Manual vii
Table of contents
18.3.2 Operations in address matching detection mode..................................................18-7
18.4 Out-of-address-area detection mode ...............................................................................18-10
18.4.1 Setting procedure for out-of-address-area detection mode ...............................18-10
18.4.2 Operations in out-of-address-area detection mode .............................................18-11
[Precautions for debug function] .........................................................................................18-12
CHAPTER 19. APPLICATIONS
19.1 Connection examples with external devices ..............................................................19-2
19.1.1 Examples with ready function used.........................................................................19-3
19.1.2 Connection examples with memories ......................................................................19-6
19.1.3 I/O expansion examples..........................................................................................19-10
19.2 Examples of handling control pins in flash memory serial I/O mode...............19-13
19.2.1 With control signals not affecting user system circuit........................................19-13
19.2.2 With control signals affecting user system circuit ...............................................19-14
CHAPTER 20. FLASH MEMORY VERSION
20.1 Overview..............................................................................................................................20-2
20.1.1 Memory assignment ...................................................................................................20-4
20.1.2 Boot mode.................................................................................................................20-12
20.2 Flash memory CPU reprogramming mode ................................................................20-13
20.2.1 Flash memory control register ...............................................................................20-14
20.2.2 Status register ..........................................................................................................20-16
20.2.3 Data protect function ...............................................................................................20-17
20.2.4 Setting and Terminate procedure for flash memory CPU reprogramming mode ..... 20-17
20.2.5 Software commands ................................................................................................20-18
20.2.6 Full status check......................................................................................................20-22
20.2.7 Electrical characteristics ..........................................................................................20-24
[Precautions for flash memory CPU reprogramming mode] .........................................20-25
20.3 Flash memory serial I/O mode .....................................................................................20-26
20.3.1 Pin description ..........................................................................................................20-26
[Precautions for flash memory serial I/O mode] ..............................................................20-30
20.4 Flash memory parallel I/O mode .................................................................................20-31
[Precautions for flash memory parallel I/O mode] ...........................................................20-32
APPENDIX
Appendix 1. Memory assignment in SFR area ....................................................................21-2
Appendix 2. Control registers.................................................................................................21-8
Appendix 3. Package outline .................................................................................................21-43
Appendix 4. Examples of handling unused pins..............................................................21-44
Appendix 5. Hexadecimal instruction code table .............................................................21-46
Appendix 6. Machine instructions........................................................................................21-54
Appendix 7. Countermeasure against noise......................................................................21-96
Appendix 8. 7902 Group Q & A ..........................................................................................21-102
Appendix 9. M37902FGCGP electrical characteristics...................................................21-110
Appendix 10. M37902FGMHP electrical characteristics ................................................21-128
Appendix 11. Standard characteristics .............................................................................21-146
Appendix 12. Memory assignment of 7902 Group .........................................................21-153
CHAPTER 1CHAPTER 1
DESCRIPTION
1.1 Performance overview
1.2 Pin configuration
1.3 Pin description
1.4 Block diagram
DESCRIPTION
7902 Group User’s Manual
1-2
Items
Number of basic instructions
Instruction execution time
External clock input frequency f(XIN)
System clock frequency f(fsys)
Memory sizes Flash memory
RAM
Programmable P0–P2, P4–P8, P10, P11
Input/Output ports P3
Multifunctional TA0–TA4
timer TB0–TB2
Serial I/O UART0, UART1
A-D converter
D-A converter
Watchdog timer
Chip select wait controller
Real-time output
Interrupt Maskable
Non-maskable
Clock generating circuit
PLL frequency multiplier
Power source voltage
Power dissipation
Port Input/Output
Input/Output withstand voltage
characteristics Output current
Memory expansion
Operating ambient temperature range
Device structure
Package
1.1 Performance overview
1.1 Performance overview
Table 1.1.1 lists the performance overview of the M37902FGCGP/HP.
Table 1.1.1 M37902FGCGP/HP performance overview Performance
203
38.46 ns (the minimum instruction at f(fsys) = 26 MHz)
26 MHz (maximum)
26 MHz (maximum)
248 Kbytes (User ROM area)
16 Kbytes (Boot ROM area)
6144 bytes
8 bits 10
4 bits 1
16 bits 5
16 bits 3
(UART or clock synchronous serial I/O) 2
10-bit successive approximation method 1 (8 channels)
8 bits 3
12 bits 1______ ______
Chip select 4 (CS 0–CS3). Each chip select area can select its bus cycle
and external data bus’s width, respectively.
4 bits 2 channels, or 6 bits 1 channel + 2 bits 1 channel
5 external, 13 internal
(Any of priority levels 0 through 7 can be set for each interrupt, by software.)
1 external, 3 internal
Built-in (externally connected to a ceramic resonator or a quartz-crystal oscillator)
Double, Triple, or Quadruple
5 V ± 0.5 V
150 mW (at f(fsys) = 26 MHz, typ, the PLL frequency multiplier is stopped.)
5 V
5 mA
Maximum 16 Mbytes (Bank FF16 is a reserved area.)
–20 °C to 85 °C
CMOS high-performance silicon gate process
100-pin plastic molded QFP (GP: 100P6S-A, HP: 100P6Q-A)
DESCRIPTION
7902 Group User’s Manual 1-3
1.2 Pin configuration
1.2 Pin configuration
Figures 1.2.1 and 1.2.2 show the M37902 pin configuration.
Fig. 1.2.1 M37902 pin configuration (outline 100P6S-A, top view)
Outline 100P6S-A
V
REF
P8
6
/R
X
D
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P6
2
/INT
0
P6
1
/TA4
IN
P6
0
/TA4
OUT
P5
1
/TA0
IN
/RTP0
1
P5
0
/TA0
OUT
/RTP0
0
P5
3
/TA1
IN
/RTP0
3
P5
2
/TA1
OUT
/RTP0
2
P5
5
/TA2
IN
/RTP1
1
/KI
1
P5
4
/TA2
OUT
/RTP1
0
/KI
0
P4
5
/CS
1
P4
3
/HOLD
P4
1
/φ
1
P4
0
/ALE
P3
3
/BHW
P3
2
/BLW
P3
1
/RD
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P4
6
/CS
2
P4
7
/CS
3
P4
4
/CS
0
P4
2
/HLDA
P6
5
/TB0
IN
P6
6
/TB1
IN
P6
7
/TB2
IN
P7
0
/AN
0
P7
1
/AN
1
P7
2
/AN
2
P1
0
/D
0
/LA
0
P1
1
/D
1
/LA
1
P1
2
/D
2
/LA
2
P1
3
/D
3
/LA
3
P1
4
/D
4
/LA
4
MD1
V
SS
P11
0
/A
8
P10
7
/A
7
P11
1
/A
9
P11
2
/A
10
P11
3
/A
11
P11
4
/A
12
P11
5
/A
13
P11
6
/A
14
P11
7
/A
15
P0
0
/A
16
P0
1
/A
17
P0
2
/A
18
P0
3
/A
19
P0
4
/A
20
P0
5
/A
21
P0
6
/A
22
P0
7
/A
23
P10
6
/A
6
P10
5
/A
5
P10
4
/A
4
P10
3
/A
3
P10
2
/A
2
P10
1
/A
1
81
82
83
84
858687888990919293949596979899
100
5049484746454443424140
39
3837363534333231
P3
0
/RDY
BYTE
V
CONT
RESET
MD0
V
SS
X
IN
X
OUT
V
CC
P2
7
/D
15
P2
6
/D
14
P2
5
/D
13
P2
4
/D
12
P2
3
/D
11
P2
2
/D
10
P2
1
/D
9
P2
0
/D
8
P1
7
/D
7
/LA
7
P1
6
/D
6
/LA
6
P1
5
/D
5
/LA
5
P10
0
/A
0
P8
7
/T
X
D
1
P8
4
/CTS
1
/RTS
1
/INT
4
P8
1
/CTS
0
/CLK
0
P8
2
/R
X
D
0
V
CC
AV
CC
AV
SS
V
SS
NMI
P7
6
/AN
6
/DA
0
P7
4
/AN
4
/(INT
3
)
P7
3
/AN
3
P7
7
/AN
7
/AD
TRG
/DA
1
/(INT
2
)
P8
0
/CTS
0
/RTS
0
/DA
2
/INT
3
P7
5
/AN
5
/(INT
4
)
P8
3
/T
X
D
0
P8
5
/CTS
1
/CLK
1
P5
7
/TA3
IN
/RTP1
3
/KI
3
P5
6
/TA3
OUT
/RTP1
2
/KI
2
P6
3
/INT
1
P6
4
/INT
2
DESCRIPTION
7902 Group User’s Manual
1-4
1.2 Pin configuration
Fig. 1.2.2 M37902 pin configuration (outline 100P6Q-A, top view)
Outline 100P6Q-A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P6
3
/INT
2
P6
3
/INT
1
P6
2
/INT
0
P6
1
/TA4
IN
P6
0
/TA4
OUT
P5
5
/TA2
IN
/RTP1
1
/KI
1
P5
4
/TA2
OUT
/RTP1
0
/KI
0
P5
3
/TA1
IN
/RTP0
3
P5
2
/TA1
OUT
/RTP0
2
P5
1
/TA0
IN
/RTP0
1
P5
0
/TA0
OUT
/RTP0
0
P4
7
/CS
3
P4
6
/CS
2
P4
5
/CS
1
P4
4
/CS
0
P4
3
/HOLD
P4
0
/ALE
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P4
2
/HLDA
P4
1
/φ
1
P6
5
/TB0
IN
P6
6
/TB1
IN
P6
7
/TB2
IN
P7
0
/AN
0
P3
0
/RDY
P3
1
/RD
P3
2
/BLW
P3
3
/BHW
BYTE
V
CONT
RESET
MD0
V
SS
P2
5
/D
13
P2
4
/D
12
P2
6
/D
14
X
IN
X
OUT
V
CC
P2
7
/D
15
P2
3
/D
11
P2
2
/D
10
P2
1
/D
9
P2
0
/D
8
P1
7
/D
7
/LA
7
P1
6
/D
6
/LA
6
P1
5
/D
5
/LA
5
P1
0
/D
0
/LA
0
P1
1
/D
1
/LA
1
P1
2
/D
2
/LA
2
V
SS
P10
5
/A
5
P10
4
/A
4
P10
7
/A
7
P10
6
/A
6
P11
0
/A
8
P11
2
/A
10
P11
1
/A
9
P11
3
/A
11
P11
5
/A
13
P11
4
/A
12
P11
6
/A
14
P0
0
/A
16
P11
7
/A
15
P0
1
/A
17
P0
2
/A
18
P0
4
/A
20
P0
3
/A
19
P0
5
/A
21
P0
7
/A
23
MD1
P0
6
/A
22
P1
4
/D
4
/LA
4
P1
3
/D
3
/LA
3
P10
0
/A
0
P8
7
/T
X
D
1
P8
6
/R
X
D
1
P8
5
/CTS
1
/CLK
1
P8
4
/CTS
1
/RTS
1
/INT
4
P8
3
/T
X
D
0
P10
3
/A
3
P10
2
/A
2
P10
1
/A
1
P8
2
/R
X
D
0
V
CC
AV
CC
V
REF
AV
SS
V
SS
P7
7
/AN
7
/AD
TRG
/DA
1
/(INT
2
)
P7
6
/AN
6
/DA
0
P7
5
/AN
5
/(INT
4
)
P7
4
/AN
4
/(INT
3
)
P7
3
/AN
3
P7
2
/AN
2
P7
1
/AN
1
P8
0
/CTS
0
/RTS
0
/DA
2
/INT
3
NMI
P8
1
/CTS
0
/CLK
0
P5
7
/TA3
IN
/RTP1
3
/KI
3
P5
6
/TA3
OUT
/RTP1
2
/KI
2
5049484746454443424140
39
38373635343332313029282726
81
82
83
84
858687888990919293949596979899
100
767778
79
80
DESCRIPTION
7902 Group User’s Manual 1-5
Apply 5 V ± 0.5 V to pin Vcc and 0 V to pin Vss.
This pin switches the operating mode.
Note: When MD1 = Vss and MD0= Vss, the microcomputer starts
operation in the single-chip mode after reset. It’s processor
mode can be switched to the memory expansion or
microprocessor mode by software.
The microcomputer is reset when “L” level is input to this pin.
Pins XIN and XOUT are the input and output pins of the clock
generating circuit, respectively. Connect these pins via a
ceramic resonator or a quartz-crystal oscillator. When an
external clock is input, this clock should be input to pin XIN,
and pin XOUT should be left open.
The input level to this pin determines whether the external
data bus has a 16-bit width or an 8-bit width. A 16-bit width
is selected when the input level = Vss, and an 8-bit width is
selected when the input level = Vcc. When BYTE = Vss, by
software, the external data bus width can be set to 8 bits for
each of areas CS1 to CS3.
This is the input pin for the NMI interrupt. While pin RESET
is at “L” level or after reset, this pin is pulled up. This pullup
state can be removed by software.
To use the PLL frequency multiplier, be sure to connect this
pin to the filter circuit.
The power source input pin for the A-D and D-A converters.
Connect this pin to pin Vcc.
The power source input pin for the A-D and D-A converters.
Connect this pin to pin Vss.
This is the reference voltage input pin for the A-D and D-A converters.
1.3 Pin description
Single-chip mode (Note),
Memory expansion mode,
Microprocessor mode
Microprocessor mode
Boot mode
Flash memory parallel I/O mode
Input
Input
Input
Output
Input
Input
Input
Input/Output
Power source input
MD0
MD1
Reset input
Clock input
Clock output
External data bus
width select input
NMI interrupt input
Filter circuit connection
Analog power source
input
Reference voltage input
Vcc, Vss
MD0
MD1
RESET
XIN
XOUT
BYTE
NMI
VCONT
AVcc
AVss
VREF
1.3 Pin description
Tables 1.3.1 to 1.3.4 list the pin description.
Table 1.3.1 Pin description (1)
NamePin Function
Vss
Vcc
Vss
Vcc
MD1
Vss
Vss
Vcc
Vcc
MD0 Operating mode
DESCRIPTION
7902 Group User’s Manual
1-6
1.3 Pin description
I/O port P0
I/O port P1
I/O port P2
I/O port P3
Name
P00–P07
A16–A23
P10–P17
D0–D7,
LA0–LA7
P20–P27
P20/D8
P27/D15
P30–P33
P30,
RDY,
RD,
BLW,
BHW
Pin
Table 1.3.2 Pin description (2)
I/O
Output
I/O
I/O
I/O
I/O
I/O
I/O,
Input,
Output,
Output,
Output
Input/Output
Function
[Single-chip mode]
P0 is an 8-bit CMOS I/O port and has an I/O direction register.
Each pin can function as an input or output port pin.
[Memory expansion mode][Microprocessor mode]
High-order 8 bits (A16–A23) of an address are output.
By software, these pins can function as an I/O port with the
same function as port P0.
[Single-chip mode]
P1 is an 8-bit I/O port with the same function as port P0.
[Memory expansion mode][Microprocessor mode]
Low-order 8 bits (D0–D7) of data are input or output.
When area CS2 is accessed with the external data bus width
= 8 bits, by software, address (LA0–LA7) output and data
(D
0
–D
7
) input/output can be performed with the time-sharing method.
[Single-chip mode]
P2 is an 8-bit I/O port with the same function as port P0.
[Memory expansion mode][Microprocessor mode]
When the external data bus width = 8 bits (BYTE = Vcc level)
P2 is an 8-bit I/O port with the same function as port P0.
When the external data bus width = 16 bits (BYTE = Vss level)
High-order 8 bits (D8–D15) of data are input and output.
[Single-chip mode]
P3 is a 4-bit I/O port with the same function as port P0.
[Memory expansion mode][Microprocessor mode]
When MD1 = Vss level, MD0 = Vss level
P3
0
functions as an I/O port pin with the same function as port P0.
By software, P30 can function as pin RDY.
When MD1 = Vss level, MD0 = Vcc level
P30 functions as pin RDY. By software, P3 0 can function as
an I/O port with the same function as port P0.
While pin RDY’s input level = “L,” the microcomputer is placed
in Ready state.
P31, P32, and P33 become pins RD, BLW, and BHW, respectively.
The microcomputer reads data or instruction codes while
pin RD’s level = “L.”
When the external data bus width = 8 bits (BYTE = Vcc level)
The microcomputer writes data when pin BLW’s level =
“L.” Pin BHW functions as an I/O port pin (P33), with the
same function as port P0.
When the external data bus width = 16 bits (BYTE = Vss level)
The microcomputer writes data into an even-numbered
address while pin BLW’s level = “L.” The microcomputer
writes data into an odd-numbered address when pin BHW’s
evel = “L.”
DESCRIPTION
7902 Group User’s Manual 1-7
1.3 Pin description
[Single-chip mode]
P4 is an 8-bit I/O port with the same function as port P0.
By software, P41 can function as the clock φ1 output pin. While
pin RESET = “L” level and after reset, P4 4–P47 are pulled up.
This pullup state can be removed by software.
[Memory expansion mode]
P4 is an 8-bit I/O port with the same function as port P0.
By software, P40 can function as pin ALE, P4 1 as the clock φ1
output pin, P42 as pin HLDA, P43 as pin HOLD, P44–P47 as pins
CS0–CS3. While pin RESET = “L” level and after reset, P44–P47
are pulled up. This pullup state can be removed by software.
[Microprocessor mode]
P40 functions as pin ALE, P41 as the clock φ1 output pin, P42
as pin HLDA, P43 as pin HOLD, P44 as pin CS0.
Signal ALE
This signal is used to latch an address.
Signal φ1
This signal has the same period as system clock fsys.
Signal HOLD
The microcomputer is in Hold state while pin HOLD’s
input level = “L.”
Signal HLDA
This signal informs the external whether this microcomputer
enters Hold state or not.
Signal
CS
0
This signal is a chip select signal.
P45–P47 function as I/O port pins with the same function as
port P0. By software, pin ALE, the clock φ1 output pin, pins
HLDA, HOLD can function
as I/O port pins (P4
0
, P4
1
, P4
2
, P4
3
)
and
P45–P47
as pins CS
1
to CS
3
.
Also,
P45–P47
are pulled up while pin RESET = “L” level and after
reset. This pullup state can be removed by software.
P5 is an 8-bit I/O port with the same function as port P0.
By software, these pins can function as I/O pins for timers A0 to
A3, pulse output pins for real-time output, or input pins for the
key input interrupt.
P6 is an 8-bit I/O port with the same function as port P0.
By software, these pins can function as I/O pins for timer A4, input
pins for the external interrupts, or input pins for timers B0 to B2.
P7 is an 8-bit I/O port with the same function as port P0.
By software, these pins can function as input pins for the
A-D converter, output pins for the D-A converter, or input
pins for the external interrupts.
I/O port P4
I/O port P5
I/O port P6
I/O port P7
I/O
I/O
Output,
Output,
Output,
Input,
Output,
I/O
I/O
I/O
I/O
P40–P47
P40–P47
ALE,
φ1,
HLDA,
HOLD,
CS0,
P45–P47
P50–P57
P60–P67
P70–P77
Table 1.3.3 Pin description (3)
Pin Name
Input/Output
Function
DESCRIPTION
7902 Group User’s Manual
1-8
I/O port P8
I/O port P10
I/O port P11
I/O
I/O
Output
I/O
Output
P80–P87
P100–P107
A0–A7
P110–P117
A8–A15
Table 1.3.4 Pin description (4)
P8 is an 8-bit I/O port with the same function as port P0.
By software, these pins can function as I/O pins for serial
I/O, output pins for the D-A converter, or input pins for the
external interrupts.
[Single-chip mode]
P10 is an 8-bit I/O port with the same function as port P0.
[Memory expansion mode][Microprocessor mode]
Low-order 8 bits (A0–A7) of an address are output.
[Single-chip mode]
P11 is an 8-bit I/O port with the same function as port P0.
[Memory expansion mode][Microprocessor mode]
Middle-order 8 bits (A8–A15) of an address are output. By
software, these pins can funtion as an 8-bit I/O port with the
same function as port P0.
Pin Name
Input/Output
Function
1.3 Pin description
DESCRIPTION
7902 Group User’s Manual 1-9
1.4 Block diagram
1.4 Block diagram
Figure 1.4.1 shows the M37902 block diagram.
Fig. 1.4.1 M37902 block diagram
Data bank Register DT (8)
Program Counter PC (16)
Incrementer/Decrementer (24)
Program Bank Register PG (8)
Input Buffer Register IB (16)
Direct Page Register DPR0 (16)
Stack Pointer S (16)
Index Register Y (16)
Index Register X (16)
Arithmetic Logic
Unit (16)
Accumulator B (16)
Accumulator A (16)
Instruction register (8)
Central Processing Unit (CPU)
Incrementer (24)
Program Address Register PA (24)
Data Address Register DA (24)
Bus
Interface
Unit
(BIU)
RESET MD1
Reference
voltage input
V
REF
(0V)
AV
SS
AVcc
Vcc
External data bus width
select input
BYTE
Clock Generating Circuit
Clock input
X
IN
V
CONT
X
OUT
Data Buffer DQ
0
(8)
Instruction Queue Buffer Q
0
(8)
Data Bus (Odd)
Address Bus
A-D converter (10)
UART1 (9)
UART0 (9)
Watchdog timer
Timer TB1 (16)
Timer TB2 (16)
Timer TB0 (16)
D-A
1
converter (8)
D-A
2
converter (8)
Timer TA1 (16)
Timer TA2 (16)
Timer TA3 (16)
Timer TA4 (16)
Timer TA0 (16)
RAM
P8(8)
Input/Output
port P8
P7(8)
Input/Output
port P7 Input/Output
port P4
P4(8)
P10(8)
Input/Output
port P10
P6(8)
Input/Output
port P6
P5(8)
Input/Output
port P5
P11(8)
Input/Output
port P11
P1(8)
Input/Output
port P1
P2(8)
Input/Output
port P2
P3(4)
Input/Output
port P3
P0(8)
Input/Output
port P0
MD0
(0V)
Vss
Processor Status Register PS (11)
NMI
ROM
D-A
0
converter (8)
Data Bus (Even)
Data Buffer DQ
1
(8)
Data Buffer DQ
2
(8)
Data Buffer DQ
3
(8)
Instruction Queue Buffer Q
1
(8)
Instruction Queue Buffer Q
2
(8)
Instruction Queue Buffer Q
3
(8)
Instruction Queue Buffer Q
4
(8)
Instruction Queue Buffer Q
5
(8)
Instruction Queue Buffer Q
6
(8)
Instruction Queue Buffer Q
7
(8)
Instruction Queue Buffer Q
8
(8)
Instruction Queue Buffer Q
9
(8)
Direct Page Register DPR1 (16)
Direct Page Register DPR2 (16)
Direct Page Register DPR3 (16)
Clock output Reset input
DESCRIPTION
7902 Group User’s Manual
1-10
1.4 Block diagram
MEMORANDUM
CHAPTER 2CHAPTER 2
CENTRAL
PROCESSING UNIT
(CPU)
2.1 Central processing unit (CPU)
2.2 Bus interface unit (BIU)
2.3 Access space
2.4 Memory assignment
2.5 Processor modes
[Precautions for setting of processor
mode]
7902 Group User's Manual
CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit (CPU)
2-2
2.1 Central processing unit (CPU)
The CPU (Central Processing Unit) has 13 registers shown in Figure 2.1.1.
Fig. 2.1.1 CPU registers
D
i
r
e
c
t
p
a
g
e
r
e
g
i
s
t
e
r
1
(
D
P
R
1
)
D
P
R
1
H
D
P
R
1
L
b
1
5b
8b
7b
0
A
c
c
u
m
u
l
a
t
o
r
B
(
B
)
B
H
B
L
b
1
5b
8b
7b
0
A
c
c
u
m
u
l
a
t
o
r
E
(
E
)
E
b
3
1b
0
I
n
d
e
x
r
e
g
i
s
t
e
r
X
(
X
)
X
H
X
L
b
1
5b
8b
7b
0
I
n
d
e
x
r
e
g
i
s
t
e
r
Y
(
Y
)
Y
H
Y
L
b
1
5b
8b
7b
0
S
t
a
c
k
p
o
i
n
t
e
r
(
S
)
S
H
S
L
b
1
5b
8b
7b
0
D
a
t
a
b
a
n
k
r
e
g
i
s
t
e
r
(
D
T
)
D
T
b
7b
0
D
i
r
e
c
t
p
a
g
e
r
e
g
i
s
t
e
r
0
(
D
P
R
0
)
D
P
R
0
H
D
P
R
0
L
b
1
5b
8b
7b
0
b
1
5b
8b
7b
0b
2
3b
1
6P
r
o
g
r
a
m
c
o
u
n
t
e
r
(
P
C
)
P
r
o
g
r
a
m
b
a
n
k
r
e
g
i
s
t
e
r
(
P
G
)
P
C
H
P
C
L
P
G
b
7b
0
A
c
c
u
m
u
l
a
t
o
r
A
(
A
)
A
H
A
L
b
1
5b
8b
7b
0
D
i
r
e
c
t
p
a
g
e
r
e
g
i
s
t
e
r
2
(
D
P
R
2
)
D
P
R
2
H
D
P
R
2
L
b
1
5b
8b
7b
0
D
i
r
e
c
t
p
a
g
e
r
e
g
i
s
t
e
r
3
(
D
P
R
3
)
D
P
R
3
H
D
P
R
3
L
b
1
5b
8b
7b
0
P
r
o
c
e
s
s
o
r
s
t
a
t
u
s
r
e
g
i
s
t
e
r
(
P
S
)
P
S
H
P
S
L
b
1
5b
8b
7b
0
b
0b
1b
2b
3b
4b
5b
6b
7b
8b
1
0b
1
5
C
Z
IDxm
V
NI
P
00000
C
a
r
r
y
f
l
a
g
Z
e
r
o
f
l
a
g
I
n
t
e
r
r
u
p
t
d
i
s
a
b
l
e
f
l
a
g
D
e
c
i
m
a
l
m
o
d
e
f
l
a
g
I
n
d
e
x
r
e
g
i
s
t
e
r
l
e
n
g
t
h
f
l
a
g
D
a
t
a
l
e
n
g
t
h
f
l
a
g
O
v
e
r
f
l
o
w
f
l
a
g
N
e
g
a
t
i
v
e
f
l
a
g
P
r
o
c
e
s
s
o
r
i
n
t
e
r
r
u
p
t
p
r
i
o
r
i
t
y
l
e
v
e
l
7902 Group User’s Manual
2.1 Central processing unit (CPU)
CENTRAL PROCESSING UNIT (CPU)
2-3
2.1.1 Accumulator (Acc)
Accumulators A and B are available. Also, accumulators A and B can be connected in series in order to
be used as a 32-bit accumulator (accumulator E).
(1) Accumulator A (A)
Accumulator A is the main register of the microcomputer. The transaction of data such as calculation,
data transfer, and input/output are performed mainly through accumulator A. It consists of 16 bits,
and the low-order 8 bits can also be used separately. The data length flag (m) determines whether
the register is used as a 16-bit register or as an 8-bit register. Flag m is a part of the processor status
register, which is described later. When an 8-bit register is selected, only the low-order 8 bits of
accumulator A are used, and the contents of the high-order 8 bits is unchanged.
(2) Accumulator B (B)
Accumulator B is a 16-bit register with the same function as accumulator A. Accumulator B can be
used instead of accumulator A. The use of accumulator B, however except for some instructions,
requires more instruction bytes and execution cycles than those of accumulator A. Accumulator B is
also affected by flag m just as in accumulator A.
(3) Accumulator E (E)
This 32-bit accumulator consists of accumulator A located in the low-order 16 bits and accumulator
B located in the high-order 16 bits. This accumulator is used by an instruction that handles 32-bit
data. It is not affected by flag m.
2.1.2 Index register X (X)
Index register X consists of 16 bits and the low-order 8 bits can also be used separately. The index register
length flag (x) determines whether the register is used as a 16-bit register or as an 8-bit register. Flag x
is a part of the processor status register, which is described later. When an 8-bit register is selected, only
the low-order 8 bits of index register X are used, and the contents of the high-order 8 bits are not
unchanged.
In an addressing mode in which index register X is used as an index register, the address obtained by
adding the contents of this register to the operand’s contents is accessed.
Also, each of the MVP, MVN and RMPA instructions uses index register X.
Refer to “7900 Series Software Manual” for addressing modes and instructions.
2.1.3 Index register Y (Y)
Index register Y is a 16-bit register with the same function as index register X. Just as in index register
X, this register is affected by flag X.
7902 Group User's Manual
CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit (CPU)
2-4
2.1.4 Stack pointer (S)
The stack pointer (S) is a 16-bit register. It is used for a subroutine call or an interrupt. It is also used when
addressing modes using the stack are executed. The contents of S indicate an address (stack area) for
storing registers during subroutine calls and interrupts. Bank 016 is specified for the stack area. (Refer to
section “2.3 Access space.”)
When an interrupt request is accepted, the microcomputer stores the contents of the program bank register
(PG) at the address indicated by the contents of S and decrements the contents of S by 1. Then the
contents of the program counter (PC) and the processor status register (PS) are stored. The contents of
S after accepting an interrupt request is equal to the contents of S decremented by 5 before accepting of
Fig. 2.1.2 Contents of stack area after accepting
interrupt request
S
i
s
t
h
e
i
n
i
t
i
a
l
a
d
d
r
e
s
s
t
h
a
t
t
h
e
s
t
a
c
k
p
o
i
n
t
e
r
(
S
)
i
n
d
i
c
a
t
e
s
a
t
a
c
c
e
p
t
i
n
g
a
n
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
.
T
h
e
S
s
c
o
n
t
e
n
t
s
b
e
c
o
m
e
S
5
a
f
t
e
r
s
t
o
r
i
n
g
t
h
e
a
b
o
v
e
r
e
g
i
s
t
e
r
s
.
A
d
d
r
e
s
s
S
4
S
3
S
2
S
1
S
S
t
a
c
k
a
r
e
a
S
5
P
r
o
c
e
s
s
o
r
s
t
a
t
u
s
r
e
g
i
s
t
e
r
s
l
o
w
-
o
r
d
e
r
b
y
t
e
(
P
S
L
)
P
r
o
c
e
s
s
o
r
s
t
a
t
u
s
r
e
g
i
s
t
e
r
s
h
i
g
h
-
o
r
d
e
r
b
y
t
e
(
P
S
H
)
P
r
o
g
r
a
m
c
o
u
n
t
e
r
s
l
o
w
-
o
r
d
e
r
b
y
t
e
(
P
C
L
)
P
r
o
g
r
a
m
c
o
u
n
t
e
r
s
h
i
g
h
-
o
r
d
e
r
b
y
t
e
(
P
C
H
)
P
r
o
g
r
a
m
b
a
n
k
r
e
g
i
s
t
e
r
(
P
G
)
the interrupt request. (See Figure 2.1.2.)
When completing the process in the interrupt routine
and returning to the original routine, the contents of
registers stored in the stack area are restored into
the original registers in the reverse sequence
(PSPCPG) by executing the RTI instruction. The
contents of S is returned to the state before accepting
an interrupt request.
The same operation is performed during a subroutine
call, however, the contents of PS is not automatically
stored. (The contents of PG may not be stored.
This depends on the addressing mode.)
During interrupts or subroutine calls, the other
registers are not automatically stored. Therefore, if
the contents of these registers need to be held on,
be sure to store them by software.
Additionally, the S’s contents become “0FFF16” at
reset. The stack area changes when subroutines
are nested or when multiple interrupt requests are
accepted. Therefore, make sure of the subroutine’s
nesting depth not to destroy the necessary data.
Refer to “7900 Series Software Manual” for addressing modes and instructions.
7902 Group User’s Manual
2.1 Central processing unit (CPU)
CENTRAL PROCESSING UNIT (CPU)
2-5
2.1.5 Program counter (PC)
The program counter is a 16-bit counter that indicates the low-order 16 bits of the address (24 bits) at
which an instruction to be executed next (in other words, an instruction to be read out from an instruction
queue buffer next) is stored. The contents of the high-order program counter (PCH) become “FF16,” and the
low-order program counter (PCL) becomes “FE16” at reset. The contents of the program counter becomes
the contents of the reset’s vector address (addresses FFFE16, FFFF16) just after reset.
Figure 2.1.3 shows the program counter and the program bank register.
Fig. 2.1.3 Program counter and Program bank register
2.1.6 Program bank register (PG)
The memory space is divided into units of 64 Kbytes. This unit is called “bank.” (Refer to section “2.3
Access space.”)
The program bank register is an 8-bit register that indicates the high-order 8 bits of the address (24 bits)
at which an instruction to be executed next (in other words, an instruction to be read out from an instruction
queue buffer next) is stored. These 8 bits indicate a bank.
When a carry occurs after adding the contents of the program counter or adding the offset value to the
contents of the program counter in the branch instruction and others, the contents of the program bank
register is automatically incremented by 1. When a borrow occurs after subtracting the contents of the
program counter, the contents of the program bank register is automatically decremented by 1. Therefore,
there is no need to consider bank boundaries during programming, usually.
This register is cleared to “0016” at reset.
P
C
H
P
C
L
b
7b
0b
1
5b
8b
7b
0
(
b
1
6
)
P
G
(
b
2
3
)
2.1.7 Data bank register (DT)
The data bank register is an 8-bit register. In the following addressing modes using the data bank register,
the contents of this register is used as the high-order 8 bits (bank) of a 24-bit address to be accessed.
Use the LDT instruction when setting a value to this register.
This register is cleared to “0016” at reset.
Addressing modes using data bank register
•Direct indirect
•Direct indexed X indirect
•Direct indirect indexed Y
•Absolute
•Absolute indexed X
•Absolute indexed Y
•Absolute bit relative
•Stack pointer relative indirect indexed Y
•Multiplied accumulation
Refer to “7900 Series Software Manual” for addressing modes.
7902 Group User's Manual
CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit (CPU)
2-6
2.1.8 Direct page register 0 to 3 (DPR0 to DPR3)
Each of direct page registers 0 to 3 (hereafter called the “DPRi”) is a 16-bit register. The contents of this
register specify the direct page area in bank 016 or in the space across banks 016 and 116. The following
addressing modes use DPRi.
The contents of the DPRi indicate the base address (the lowest address) of the direct page area. The direct
page area is specified in the space above this address.
After reset, whether to use DPR0 only or DPR0 to DPR3 can be selected by the direct page register select
bit. (See Figure 2.1.5). This selection specifies the direct page area. Table 2.1.1 lists the selection of the
direct page register. Figure 2.1.4 shows setting examples of the direct page area.
At reset, DPR0 = “000016,” and each of DPR1 to DPR3 becomes undefined.
Addressing modes using direct page register Table 2.1.1 Selection of direct page register
Usable DPRi
Direct page area
Direct page register select bit
0
DPR0
256 bytes
1
DPR0 to DPR3
64 bytes at
each DPRi
Fig. 2.1.4 Setting examples of direct page area
• Direct
• Direct indexed X
• Direct indexed Y
• Direct indirect
• Direct indexed X indirect
• Direct indirect indexed Y
• Direct indirect long
• Direct indirect long indexed Y
• Direct bit relative
Refer to “7900 Series Software Manual” for addressing modes and instructions.
1000F
16
10000
16
1000F
16
Bank 0
16
0
16
0
16
FF
16
123
16
222
16
FF10
16
10000
16
FFFF
16
When DPR0 0000
16
When DPR0 0123
16
When DPR0 FF10
16
Note: When the low-order 8 bits of DPRi = “00,” the number of c
y
cles re
q
uired for address
g
eneration becomes 1 c
y
cle smaller.
The direct page area is specified in space across banks 0
16
and
1
16
when
DPR0 is “FF01
16
” or more.
Direct page register select bit = 0
0
16
3F
16
40
16
7F
16
FFD0
16
FFFF
16
Bank 0
16
When DPR0 0000
16
When DPR1 0040
16
When DPR3 FFD0
16
800
16
83F
16
When DPR2 0800
16
Direct page register select bit = 1
0
16
The direct page area is specified in the space across banks 0
16
and
1
16
when
DPRi is “FFC1
16
” or more.
Bank 1
16
Bank 1
16
7902 Group User’s Manual
2.1 Central processing unit (CPU)
CENTRAL PROCESSING UNIT (CPU)
2-7
Fig. 2.1.5 Structure of processor mode register 1
RW
RW
RW
RW
RW
RW
RW
RW
0
0
(Note 4)
(Note 4)
(Note 4)
(Note 4)
0
0
Processor mode register 1 (Address 5F16)
Bit nameBit Function
At reset
R/W
b7 b6 b5 b4 b3 b2 b1 b0
0 : Only DPR0 is used.
1 : DPR0 through DPR3 are used.
0 : RDY input is disabled.
(P30 functions as a programmable I/O port pin.)
1 : RDY input is enabled. (P30 functions as pin RDY.)
0 : ALE output is disabled.
(P40 functions as a programmable I/O port pin.)
1 : ALE output is enabled. (P40 functions as pin ALE.)
0 : No recovery cycle is inserted at access to external area.
1 : Recovery cycle is inserted at access to external area.
0 : HOLD input and HLDA output are disabled.
(P43 and P4 2 function as programmable I/O port pins.)
1 : HOLD input and HLDA output are enabled.
(P43 and P4 2 function as pins HOLD and HLDA.)
0 : 1 cycle
1 : 2 cycles
0 : 3φ
1 : 2φ
(Note 5)
(Note 5)
The combination of this bit and the external bus cycle
select bit 0 selects the bus cycle.
0 : 1φ + 1φ, 1φ + 2φ, 1φ + 3φ, or 2φ + 2φ
1 : 2φ + 3φ, 2φ + 4φ, 3φ + 3φ, or 3φ + 4φ
(Note 2)
External bus cycle select bit 1
(Note 1)
Direct page register switch bit
RDY input select bit (Note 3)
ALE output select bit (Note 3)
Recovery cycle insert select bit
(Note 3)
HOLD input, HLDA output select
bit (Note 3)
Recovery-cycle-insert number
select bit (Note 6)
Internal ROM bus cycle select bit
(Note 7)
Notes 1: This bit is valid for the external area except for area CSi. Regardless of these bits’ contents, the bus cycle of area CSi is
decided by the corresponding area CSi bus cycle select bits 0, 1 (bits 0, 1 at addresses 8016, 82 16, 8416, 86 16, and bit 3 at
addresses 8116, 8316, 8516, 8716).
2: After reset, this bit can be set only once. (During the software execution, be sure not to change this bit’s contents.)
3: In the single-chip mode, all of these bits’ functions are disabled regardless of these bits’ contents.
4: When the Vss-level voltage is applied to pin MD0, this bit is “0”; when the Vcc-level voltage is applied to pin MD0, this bit
is “1.”
5: After reset, this bit can be set to “1” only once. Once this bit has been cleared from “1” to “0,” it cannot be back to “1”
again. (Fixed to “0.”)
6: Make sure that a program to be used to change this bit’s contents is allocated in the internal area.
7: In the microprocessor mode, this bit is invalid. This bit is not assigned to the external ROM version. (“0” at reading.)
To reprogram the internal flash memory by using the CPU reprogramming mode, clear this bit to “0.” (Refer to section
“20.2 Flash memory CPU reprogramming mode.”)
0
1
2
3
4
5
6
7
7902 Group User's Manual
CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit (CPU)
2-8
2.1.9 Processor status register (PS)
PS is an 11-bit register.
Figure 2.1.6 shows the structure of PC. Refer to “7900 Series Software Manual” for detale about the
change of each bit.
Fig. 2.1.6 Structure of PS
(1) Bit 0: Carry flag (C)
This flag retains a carry or a borrow generated in the arithmetic and logic unit (ALU) during an
arithmetic operation. This flag is also affected by shift and rotate instructions.
Be sure to use the SEC or SEP instruction to set this flag to “1”; and be sure to use the CLC or CLP
instruction to clear it to “0”.
The contents of this flag is undefined at reset.
(2) Bit 1: Zero flag (Z)
This flag is set to “1” when the result of an arithmetic operation or data transfer is “0,” and cleared
to “0” when otherwise. This flag is invalid in the decimal arithmetic operation.
Be sure to use the SEP instruction to set this flag to “1”; and be sure to use the CLP instruction to
clear it to “0.”
The contents of this flag is undefined at reset.
(3) Bit 2: Interrupt disable flag (I)
This flag disables all maskable interrupts except the following: the address matching detection, NMI,
watchdog timer, and 0 division interrupts. Interrupts are disabled when this flag is “1.” When an
interrupt request has been accepted, this flag is automatically set to “1,” and multiple interrupts
become disabled. Be sure to use the SEI instruction to set this flag to “1”; and be sure to use the
CLI or CLP instruction to clear this flag to “0.”
This flag is set to “1” at reset.
(4) Bit 3: Decimal mode flag (D)
This flag determines whether addition and subtraction are performed in binary or decimal. Binary
arithmetic operation is performed when this flag is “0.” When it is “1,” decimal arithmetic operation
is performed with each 8 bits treated as 2-digit decimal (at m = 1) or each 16 bits treated as 4-digit
decimal (at m = 0). Decimal adjust is automatically performed. Decimal operation is possible only
with the ADC, ADCB, SBC and SBCB instructions. Be sure to use the SEP instruction to set this
flag to “1”; and be sure to use the CLP instruction to clear it to “0.”
This flag is cleared to “0” at reset.
(5) Bit 4: Index register length flag (x)
This flag determines whether each of index register X and index register Y is used as a 16-bit
register or an 8-bit register. That register is used as a 16-bit register when this flag is “0,” and as
an 8-bit register when it is “1” (Note). Be sure to use the SEP instruction to set this flag to “1”; and
be sure to use the CLP instruction to clear it to “0.”
This flag is cleared to “0” at reset.
b15 b8 b7 b0b1b2b3b4b5b6b14 b9b10b11b12b13
0NCZIDxmV0 IPL000
Note: Be sure to fix bits 15 through 11 to “0.”
Processor status register
(PS)
7902 Group User’s Manual
2.1 Central processing unit (CPU)
CENTRAL PROCESSING UNIT (CPU)
2-9
(6) Bit 5: Data length flag (m)
This flag determines whether to use data as a 16-bit unit or as an 8-bit unit. Each data is treated
as a 16-bit unit when this flag is “0,” and as an 8-bit unit when it is “1” (Note).
Be sure to use the SEM or SEP instruction to set this flag to “1,” and be sure to use the CLM or
CLP instruction to clear it to “0.”
This flag is cleared to “0” at reset.
Note: When transferring data between registers which are different in bit length, this data is transferred
with the length of the transfer destination register, except for the case where the TXA, TYA,
TXB, TYB, and TXS instructions used. Refer to “7900 series software manual” for detail.
(7) Bit 6: Overflow flag (V)
This flag is used when addition or subtraction is performed with a word regarded as signed binary.
The overflow flag is set to “1” when the result of addition or subtraction exceeds the range between
–2147483648 and +2147483647 (when 32-bit length operation), the range between –32768 and
+32767 (when 16-bit length operation), or the range between –128 and +127 (when 8-bit length
operation).
The overflow flag is also set to “1” when the operation result of the DIV or DIVS instruction exceeds
the length of the register which will store that result. This flag is invalid in the decimal mode. Be sure
to use the SEP instruction to set this flag to “1,” and be sure to use the CLV or CLP instruction to
clear it to “0.”
The contents of this flag is undefined at reset.
(8) Bit 7: Negative flag (N)
This flag is set to “1” when the result of arithmetic operation or data transfer is negative. (The most
significant bit of the result is “1.”) It is cleared to “0” in all other cases. This flag is invalid in the
decimal mode. Be sure to use the SEP instruction to set this flag to “1,” and be sure to use the CLP
instruction to clear it to “0.”
The contents of this flag is undefined at reset.
(9) Bits 10 to 8: Processor interrupt priority level (IPL)
These 3 bits can determine the processor interrupt priority level to one of levels 0 through 7. When
the interrupt priority level of a requested interrupt, which has been set in the corresponding interrupt
control register, is higher than IPL, that interrupt becomes enabled. When an interrupt request is
accepted, IPL is stored in the stack area, and IPL is replaced by the interrupt priority level of the
accepted interrupt request.
There are no instruction to directly set or clear the bits of IPL. IPL can be changed by storing the
new IPL into the stack area and updating PS with the PUL or PLP instruction.
The contents of IPL is cleared to “0002” at reset.
CENTRAL PROCESSING UNIT (CPU)
7902 Group User’s Manual
2-10
2.2 Bus interface unit (BIU)
Fig. 2.2.1 Bus and BIU
2.2 Bus interface unit
The bus interface unit (hereafter called “BIU”) performs the following two operations:
Instruction prefetch
Data transfer (read and write)
Figure 2.2.1 shows the bus and BIU.
BIU is structured with four kinds of registers shown in Figure 2.2.2. Table 2.2.1 lists the function of the BIU
registers.
M37902
External
devices
HOLD
Hold request
HLDA
CPU bus Bus
interface
unit
(BIU)
Internal code bus (CB
0
to
CB
31
)
Internal address bus (AD
0
to
Internal control signal
Internal data bus (DB
0
to
DB
15
)
AD
23
)
Internal buses
Internal
memory
Internal
peripheral
devices
(SFR)
A
0
to
A
23
D
8
to
D
15
Control signals
D
0
to D
7
(LA
0
to LA
7
)
Bus
conversion
circuit
SFR : Special Function Register
Notes 1: The CPU bus, internal bus, and external bus are independent of one another.
2: Refer to “CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES” about the signals of
the external buses.
External buses
Central
processing
unit
(CPU)
CENTRAL PROCESSING UNIT (CPU)
7902 Group User’s Manual 2-11
2.2 Bus interface unit (BIU)
4-byte boundaries
8-byte boundaries
Even-numbered address
Fig. 2.2.2 BIU registers’ structure
Program address register
Instruction queue buffer
Data address register
Data buffer
PA
DA
Q0
Q9
DB
b23 b0
b0
b0
b0
b23
b31
b7
Table 2.2.1 Functions of BIU registers
Name
Program
address
register
Instruction
queue buffer
Data address
register
Data buffer
In the M37902, the internal buses are used when the CPU accesses the internal area (the internal memory
and SFR) or the external area (the external devices).
2.2.1 Instruction prefetch
While the CPU does not use the internal buses, the BIU reads instructions from the memory and then
stores them in the instruction queue buffer. The CPU reads instructions from the instruction queue buffer
and executes them, so that the CPU can operate at high speed without access to the memory, which
requires a long access time.
The instruction queue buffer can store instructions up to ten bytes. The contents of the instruction queue
buffer is initialized when a branch is made, and the BIU reads a new instruction from the branch destination
address.
When instructions in the instruction queue buffer are insufficient for the CPU’s needs, the BIU extends the
low-level duration of φCPU (See Figure 5.2.1.) in order to keep the CPU waiting until the BIU fetches
instructions of the required byte number or more.
The operation of instruction prefetch is determined
whether instructions are fetched from the internal
memory or external memory. Figure 2.2.3 shows
operating waveform examples at instruction prefetch.
Note that the operation of BIU’s instruction prefetch
also vary with the store addresses of instructions.
Table 2.2.2 lists the store address of prefetched
instructions.
Table 2.2.2 Store address of prefetched instruction
(1) Instruction prefetch from internal memory
Instructions are fetched from 4-byte boundaries, 4 bytes at a time. (See Figure 2.2.3-(a).)
Also, at branch, regardless of the low-order 2 bits’ contents (AD1 and AD0) of the branch destination
address, 4 bytes are fetched at at time from the 4-byte boundaries. (See Figure 2.2.3 (a).)
In this case, out of the data (instructions) which will be output onto the internal code buses, 4 bytes
at a time, the instructions assigned at the branch destination address and the following addresses
will be fetched into the instruction queue buffer. Accordingly, as listed in Table 2.2.3, the number of
bytes to be fetched into the instruction queue buffer varies according to the branch destination
address.
Functions
Indicates a storage address of the
instruction to be fetched into an
instruction queue buffer, next.
Temporarily stores an instruction
which has been fetched.
Indicates an address from which data
will be read or to which data will be
written, next.
Temporarily stores data which has
been read from memory•I/O device
by BIU or which will be written to
memory•I/O device by the CPU.
X: It may be “0” or “1.”
AD2 (A2)
0
AD1 (A1)
0
0
AD0(A0)
0
0
0
Low-order 3 bits
at store address
CENTRAL PROCESSING UNIT (CPU)
7902 Group User’s Manual
2-12
2.2 Bus interface unit (BIU)
4
3
2
1
Table 2.2.3 Number of bytes to be fetched into instruction queue buffer
(2) Instruction prefetch from external memory
With external data bus width = 16 bits (BYTE = Vss level)
8 bytes are fetched at a time from 8-byte boundaries. (See Figure 2.2.3-(b): 4 successive accesses).
At branch, regardless of the low-order 2 bits’ contents (A1, A0) of the branch destination address,
4 bytes are fetched at a time from 4-byte boundaries. (See Figure 2.2.3-(c): 2 successive accesses).
At this time, the number of prefetched bytes varies according to the branch destination address.
The operations succeedingly performed vary according to the address to be fetched next, as
follows:
• When the address is at an 8-byte boundary, 8 bytes will be fetched from the next time. (See
Figure 2.2.3-(b): 4 successive accesses).
• When the address is at a 4-byte boundary, 4 bytes will be fetched. (See Figure 2.2.3-(c): 2
successive accesses). Then, from the next time, 8 bytes will be fetched. (See Figure 2.2.3-
(b): 4 successive accesses).
With external data bus width = 8 bits (BYTE = Vcc level)
4 bytes are fetched at a time from 4-byte boundaries. (See Figure 2.2.3-(b): 4 successive accesses).
At branch, when the branch destination is at an even-numbered address, 2 bytes are fetched from
even-numbered addresses; when the branch destination is at an odd-numbered address, 2 bytes
are fetched from the address given by (odd-numbered address – 1). (See Figure 2.2.3 (c): 2
successive accesses);
The operations succeedingly performed vary according to the address to be fetched next, as
follows:
• When the address is at a 4-byte boundary, 4 bytes will be fetched from the next time. (See
Figure 2.2.3-(b): 4 successive accesses).
• When the address is at an even-numbered one, 2 bytes will be fetched. (See Figure 2.2.3-
(c) : 2 successive accesses). Then, from the next time, 4 bytes will be fetched. (See Figure
2.2.3-(b): 4 successive accesses).
AD0 (A0)
0
1
0
1
AD1 (A1)
0
0
1
1
AD1 (A1)
0
0
0
0
Low-order 2 bits of branch destination
address Low-order 2 bits of address to be
output onto address bus
Number of bytes to be
fetched into instruction
queue buffer
AD0 (A0)
0
0
0
0
CENTRAL PROCESSING UNIT (CPU)
7902 Group User’s Manual 2-13
2.2 Bus interface unit (BIU)
Notes 1: When the external data bus width = 8 bits (BYTE = Vcc), external data bus D0 to D7 is used only.
2: Waveform (a) applies when bus cycle = 2φ. For details of the bus cycle at access to the internal
area, see Table 2.2.4. Waveforms (b) and (c) apply when bus cycle = 1φ + 1φ at normal access.
For any of the bus cycle, recovery cycle, and burst ROM access at access to the external area,
refer to “CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES.”
Internal address bus
(AD
0
AD
23
)
φ
BIU
Internal code bus
(CB
0
CB
31
)
(instruction)
(a)
Address
External address bus
(A
0
A
23
)
RD
External data bus
(D
0
D
7
)
External data bus
(D
8
D
15
)
(b)
φ
1
Address Address Address Address
(c)
RD
φ
1
φ
BIU
: Operation clock of BIU (Refer to “CHAPTER 5. CLOCK GENERATING CIRCUIT.”)
Data
(instruction)
Data (instruction)
Data (instruction)
Data (instruction)
Data
(instruction)
Data (instruction)
Data (instruction)
Data (instruction)
Data
External address bus
(A
0
A
23
)
External data bus
(D
0
D
7
)
External data bus
(D
8
D
15
)
Address Address
(instruction)
Data (instruction)
Data
(instruction)
Data (instruction)
Data
(Note 1)
(Note 1)
Fig. 2.2.3 Waveform examples at instruction prefetch
CENTRAL PROCESSING UNIT (CPU)
7902 Group User’s Manual
2-14
2.2 Bus interface unit (BIU)
Internal ROM bus cycle select bit: Bit 7 at address 5F16
Note: When reprogramming the internal flash memory in the CPU reprogramming mode, be sure to select
bus cycle = 3φ. (Refer to section “20.2 Flash memory CPU reprogramming mode.”)
2.2.2 Data Transfer (read and write)
When the CPU reads or writes data from or to the internal/external area, it requests the BIU to read or write
data. The BIU outputs control signals in order to control the internal address and data buses in response
to the request from the CPU. The cycle where the following are performed is referred to “bus cycle”:
• The BIU controls buses.
• Data transfer is performed between the external and internal areas.
Table 2.2.4 lists the bus cycles at access to the internal area. For details of bus cycles and each signal
at access to the external area, refer to “CHAPTER. 3 CONNECTION WITH EXTERNAL DEVICES.” Figure
2.2.4 shows operating waveform examples at reading from or writing to the internal area. Figures 2.2.5 and
2.2.6 show operating waveform examples at reading from and writing to the external area.
(1) Reading data
The CPU informs the BIU’s data address register of the address where the data to be read is stored,
so the CPU requests the data. In this case, the CPU waits until the requested data is ready in the
BIU.
The BIU outputs the address informed by the CPU onto the internal address bus. Then, the CPU
reads the contents of the informed address and takes them into the data buffer. The CPU continues
processing using data in the data buffer.
(2) Writing data
The CPU informs the BIU’s data address register of the address to which the data will be written,
so the CPU writes the data into the data buffer. The BIU outputs the address informed by the CPU
onto the internal address bus. Then, the BIU writes the data in the data buffer into the informed
address.
Table 2.2.4 Bus cycles at access to internal area
Bus cycle = 3φ (Note)
(Internal ROM bus cycle select bit = 0)
ROM
RAM
SFR
Internal address bus
Internal data bus
φBIU
Address
1 bus cycle = 2φ
φBIU
Internal address bus
Internal data bus
Address
1 bus cycle = 2φ
Bus cycle = 2φ
(Internal ROM bus cycle select bit = 1)
φBIU
Internal address bus
Internal data bus Data
Address
1 bus cycle = 3φ
Data
Data
CENTRAL PROCESSING UNIT (CPU)
7902 Group User’s Manual 2-15
2.2 Bus interface unit (BIU)
Internal address bus
(AD
0
AD
23
)
φ
BIU
Internal data bus
(DB
0
DB
7
)
Internal data bus
(DB
8
DB
15
)
RD: Data to be read, WD: Data to be written
Note 2: The above waveforms apply when bus cycle = 2φ.
For the bus cycles at access to the internal area, see Table 2.2.4.
Note 1:
Internal address bus
(AD
0
AD
23
)
φ
BIU
Internal data bus
(DB
0
DB
7
)
RD
(even)
(a) When accessing 8-bit data (Note 1) or accessing 16-bit data starting from an even-numbered address
Internal data bus
(DB
8
DB
15
)
RD
(odd)
WD (even)
WD (odd)
Address
WD (odd)
Internal address bus
(AD
0
AD
23
)
φ
BIU
Internal data bus
(DB
0
DB
7
)
Internal data bus
(DB
8
DB
15
)
RD
(odd)
Address Address + 1
RD
(even)
WD (even)
RD
(odd)
RD
(even)
WD (even)
RD
(even)
WD (even)
WD(odd)
RD
(odd)
WD (odd)
RD
(odd)
Address Address + 1
RD
(even)
WD (even)
Address + 3
WD (odd)
RD
(odd)
WD (even)
WD (odd)
When reading 8-bit data at an even-numbered address, only RD (even)
will be taken into an instruction queue buffer.
When reading 8-bit data at an odd-numbered address, only RD (odd)
will be taken into an instruction queue buffer.
When writing 8-bit data to an even-numbered address, only WD (even)
will be written to an instruction queue buffer.
When writing 8-bit data to an odd-numbered address, only WD (odd)
will be written to an instruction queue buffer.
Internal address bus
(AD
0
AD
23
)
φ
BIU
Internal data bus
(DB
0
DB
7
)
Internal data bus
(DB
8
DB
15
)
Address Address + 2
(b) When accessing 16-bit data starting from an odd-numbered address
(c) When accessing 32-bit data starting from an even-numbered address
(d) When accessing 32-bit data starting from an odd-numbered address
RD
(even)
Fig. 2.2.4 Operating waveform examples at reading from or writing to internal area
CENTRAL PROCESSING UNIT (CPU)
7902 Group User’s Manual
2-16
2.2 Bus interface unit (BIU)
16-bit data access starting from an odd-numbered address
When the external data bus width = 16 bits (BYTE = V
SS
level)
(a) When accessing 16-bit data starting from an even-numbered address
< At reading > < At writing >
Address
φ
1
External address bus
( A
0
–A
23
)
External data bus
( D
0
–D
7
)
External data bus
( D
8
–D
15
)
RD
BLW
BHW
H
H
Address
WD
(even)
WD
(odd)
φ
1
External address bus
(A
0
–A
23
)
External data bus
(D
0
–D
7
)
External data bus
(D
8
–D
15
)
RD
BLW
BHW
H
Address
φ
1
External address bus
(A
0
–A
23
)
External data bus
(D
0
–D
7
)
External data bus
(D
8
–D
15
)
RD
BLW
BHW
Address + 1
16-bit data access starting from odd-numbered address
8-bit data access to
odd-numbered
address
WD
(odd)
Address
φ
1
External address bus
(A
0
–A
23
)
External data bus
(D
0
–D
7
)
External data bus
(D
8
–D
15
)
RD
BLW
BHW
H
Address + 1
8-bit data access to
odd-numbered
address
WD
(even)
Address
φ
1
External address bus
(A
0
–A
23
)
External data bus
(D
0
–D
7
)
External data bus
(D
8
–D
15
)
RD
BLW
BHW
H
H
Address + 2
< At reading > < At writing >
WD (even)
WD (odd)
Address
φ
1
External address bus
(A
0
–A
23
)
External data bus
(D
0
–D
7
)
External data bus
(D
8
–D
15
)
RD
BLW
BHW
H
Address + 2
WD (even)
WD (odd)
(d) When accessing 32-bit data starting from odd-numbered address
< At reading > < At writing >
Address
φ
1
External address bus
(A
0
–A
23
)
External data bus
(D
0
–D
7
)
External data bus
(D
8
–D
15
)
RD
BLW
BHW
H
H
Address + 1 Address + 3 Address Address + 1 Address + 3
WD (odd)
φ
1
External address bus
(A
0
–A
23
)
External data bus
(D
0
–D
7
)
External data bus
(D
8
–D
15
)
RD
BLW
BHW
H
WD (even)
WD (odd)
WD (even)
< At reading > < At writing >
Invalid
Invalid
RD
(odd)
RD
(even)
RD
(odd)
RD
(even)
Invalid
RD: Data to be read, WD: Data to be written
Invalid: Invalid data. At reading, this data is not taken into a data buffer.
Note: The above waveforms apply when bus cycle = 1φ + 1φ at normal access.
For any of the bus cycle, recovery cycle, and burst ROM access, refer to “CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES.”
RD
(even)
RD
(odd)
(b) When accessing 16-bit data starting from an odd-numbered address
or accessing 8-bit data
H
H
8-bit data access to
even-numbered
address
(c) When accessing 32-bit data starting from an even-numbered address
RD
(even)
RD
(odd)
RD
(even)
RD
(even)
RD
(odd) RD
(odd)
8-bit data access to
even-numbered
address
Fig. 2.2.5 Operating waveform examples at reading from or writing to external area (1)
CENTRAL PROCESSING UNIT (CPU)
7902 Group User’s Manual 2-17
2.2 Bus interface unit (BIU)
RD: Data to be read, WD: Data to be written
Notes 1: When BYTE = Vcc level, D8 to D15 and BHW serve as programable I/O port pins (P2 and P33).
2: The above waveforms apply when bus cycle = 1φ + 1φ at normal access.
For any of the bus cycle, recovery cycle, and burst ROM access, refer to “CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES.”
When the external data bus width = 8 bits
(e) When accessing 8-, 16-, 32-bit data
BYTE = Vcc level
< At reading > < At writing >
Address
φ
1
External address bus
(A
0
–A
23
)
External data bus
(D
0
–D
7
)
RD
BLW
H
Address + 1 Address + 2 Address + 3
8-bit data access
16-bit data access
32-bit data access
Address
φ
1
External address bus
(A
0
–A
23
)
External data bus
(D
0
–D
7
)
RD
BLW
H
Address + 1 Address + 2 Address + 3
RD RD RD RD WD WD WD WD
8-bit data access
16-bit data access
32-bit data access
< At reading > < At writing >
Address
φ
1
External address bus
(A
0
–A
23
)
External data bus
(D
0
–D
7
)
RD
BLW
H
Address + 1 Address + 2 Address + 3
8-bit data access
16-bit data access
32-bit data access
Address
φ
1
External address bus
(A
0
–A
23
)
External data bus
(D
0
–D
7
)
RD
BLW
H
Address + 1 Address + 2 Address + 3
RD RD RD RD WD WD WD WD
8-bit data access
16-bit data access
32-bit data access
BYTE = Vcc level and the external data bus width select bit (bit 2 at addresses 82
16
, 84
16
, 86
16
) = 1
BHW
H
BHW
H
Fig. 2.2.6 Operating waveform examples at reading from or writing to external area (2)
7902 Group User's Manual
2-18
CENTRAL PROCESSING UNIT (CPU)
2.3 Access space
The memory space of the M37902 is assigned to a 16-Mbyte space from addresses 016 to FFFFFF16. (See
Figure 2.3.1.) Note that, however, addresses FF000016 to FFFFFF16 cannot be used because this area is
reserved.
The space of 15.9 Mbytes (addresses from 016 through FEFFFF16) can be accessed by combination of the
program counter (PC), which consists of 16 bits, and the program bank register (PG). Refer to “CHAPTER
3. CONNECTION WITH EXTERNAL DEVICES” about the access to the external area.
The memory and I/O devices are assigned in the same access space. Accordingly, it is possible to perform
transfer and arithmetic operations using the same instructions, without discrimination of the memory from
I/O devices.
Fig. 2.3.1 M37902’s access space
: Nothing is assigned.
: Reserved area (Do not use.)
0
16
FFFF
16
10000
16
FE0000
16
FF0000
16
FFFFFF
16
SFR area
Internal RAM area
(Note 1) Bank 0
16
Internal ROM area
(Note 2)
20000
16
SFR : Special Function Register
Bank 1
16
Bank FE
16
: Memory assignment of internal area
Reserved area
FEFFFF
16
••
FF
16
Bank FF
16
Notes 1: When the internal RAM area is followed by an unused area or an external area, do not assign a program to
the last 8 bytes of the internal RAM area.
2: Do not assign a program to the last 8 bytes of the internal ROM area.
3: The memory assignment of the internal area varies according to the product type.
Refer to section “Appendix 12. Memory assignment of 7902 Group,” or the latest datasheets,
catalogs.
2.3 Access space
7902 Group User's Manual 2-19
CENTRAL PROCESSING UNIT (CPU)
2.4 Memory assignment
This section describes the memory assignment in the internal area. For more information about the external
area, refer to “2.5 Processor modes,” also.
2.4.1 Memory assignment in internal area
SFR (Special Function Register), internal RAM, and internal ROM are assigned to the internal area. Figure
2.4.1 shows the memory assignment in the internal area.
(1) SFR area
The registers used to set the internal peripheral devices are assigned to addresses 016 to FF16. This
area is called SFR. Figures 2.4.2 shows the SFR area’s memory assignment.
For each register in the SFR area, refer to each functional description in this manual.
For the state of the SFR area immediately after reset, refer to section “4.3 State of internal area.”
(2) Internal RAM area
The internal RAM area is used as a stack area, as well as an area to store data. Accordingly, be
sure to set the nesting depth of a subroutine and multiple interrupts’ level not to destroy the necessary
data.
When the internal RAM area is followed by an unused area or an external area, do not assign a
program to the last 8 bytes of the internal RAM area. (Data is allowed to be assigned there. Also,
when the internal RAM area is followed by the internal ROM area succeedingly, a program is allowed
to be assigned there.)
(3) Internal ROM area
Addresses FFC016 to FFFF16 are the vector addresses for reset and interrupts. (This is called the
interrupt vector table.) For the external ROM version or the microcomputers in the microprocessor
mode, where the internal ROM area cannot be used, be sure to assign a ROM to addresses FFC016
to FFFF16.
Do not assign a program to the last 8 bytes of the internal ROM area. (Data is allowed to be assigned
there.)
2.4 Memory assignment
7902 Group User's Manual
2–20
CENTRAL PROCESSING UNIT (CPU)
2.4 Memory assignment
Timer B2
Watchdog timer
NMI
INT0
INT1
INT2
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
These are interrupts only for debugging; do not use these interrupts.
The access to the internal area is disabled in the microprocessor mode. (Refer to section “2.5 Processor
modes”).
Memory assignment in the internal area varies according to the type of microcomputer. Refer to section
“Appendix 12. Memory assignment of 7902 Group” or the latest catalogues, datasheets.
: The internal memory is not assigned
RESET
Zero divide
L
H
FFFA16
FFFC16
FFFE16
Interrupt vector table
FF16
016
FFFF16
FFC016
Internal RAM area
Æ See Fig.2.4.2.
Internal ROM area
SFR area
L
H
L
H
BRK instruction (Note 1)
FFF816
L
H
DBC (Note 1)
FFF616
L
H
FFF416
L
H
FFF216
L
H
FFF016
L
H
FFEE16
L
H
FFEC16
L
H
FFEA16
L
H
FFE816
L
H
FFE616
L
H
FFE416
L
H
FFE216
L
H
FFE016
L
H
FFDE16
L
H
FFDC16
L
H
UART0 receive
FFDA16
L
H
UART0 transmit
FFD816
L
H
UART1 receive
FFD616
L
H
UART1 transmit
FFD416
L
H
A-D conversion
FFD216
L
H
INT3
FFD016
L
H
INT4
FFCE16
L
H
Reserved area
FFCC16
L
H
Reserved area
FFCA16
L
H
Address matching detection
FFC816
L
H
Reserved area
FFC616
L
H
Reserved area
FFC416
L
H
Reserved area
FFC216
L
H
Reserved area
FFC016
L
H
Reserved area
Notes 1:
2:
3:
Fig. 2.4.1 Memory assignment in internal area
7902 Group User's Manual 2-21
CENTRAL PROCESSING UNIT (CPU)
Port P4 register
Port P5 register
Port P4 direction register
Port P5 direction register
Port P6 register
Port P7 register
Port P6 direction register
Port P7 direction register
Port P8 register
Port P8 direction register
Port P10 register
Port P11 register
Port P10 direction register
Port P11 direction register
Address
UART1 transmit/receive mode register
Address
UART0 transmit/receive mode register
UART0 baud rate register (BRG0)
UART0 transmit/receive control register 0
UART0 transmit/receive control register 1
UART0 transmit buffer register
UART1 transmit/receive control register 0
UART1 baud rate register (BRG1)
UART1 transmit/receive control register 1
UART0 receive buffer register
UART1 transmit buffer register
UART1 receive buffer register
0
16
1
16
2
16
3
16
4
16
5
16
6
16
7
16
8
16
9
16
A
16
B
16
C
16
D
16
E
16
F
16
10
16
11
16
12
16
13
16
14
16
15
16
16
16
17
16
18
16
19
16
1A
16
1B
16
1C
16
1D
16
1E
16
1F
16
20
16
21
16
22
16
23
16
24
16
25
16
26
16
27
16
28
16
29
16
2A
16
2B
16
2C
16
2D
16
2E
16
2F
16
30
16
31
16
32
16
33
16
34
16
35
16
36
16
37
16
38
16
39
16
3A
16
3B
16
3C
16
3D
16
3E
16
3F
16
40
16
41
16
42
16
43
16
44
16
45
16
46
16
47
16
48
16
49
16
4A
16
4B
16
4C
16
4D
16
4E
16
4F
16
50
16
51
16
52
16
53
16
54
16
55
16
56
16
57
16
58
16
59
16
5A
16
5B
16
5C
16
5D
16
5E
16
5F
16
60
16
61
16
62
16
63
16
64
16
65
16
66
16
67
16
68
16
69
16
6A
16
6B
16
6C
16
6D
16
6E
16
6F
16
70
16
71
16
72
16
73
16
74
16
75
16
76
16
77
16
78
16
79
16
7A
16
7B
16
7C
16
7D
16
7E
16
7F
16
A-D register 0
A-D register 1
A-D register 2
A-D register 3
A-D register 4
A-D register 5
A-D register 6
A-D register 7
Port P0 register
Port P1 register
Port P0 direction register
Port P1 direction register
Port P2 register
Port P3 register
Port P2 direction register
Port P3 direction register
A-D control register 0
A-D control register 1
A-D conversion interrupt control register
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT
0
interrupt control register
INT
1
interrupt control register
INT
2
interrupt control register
Timer A clock division select register
Processor mode register 0
Processor mode register 1
Watchdog timer register
Watchdog timer frequency select register
INT
3
interrupt control register
INT
4
interrupt control register
One-shot start flag
Up-down flag
Count start flag
AAAAAA
A
AAAA
A
A
AAAA
A
A
AAAA
A
A
AAAA
A
A
AAAA
A
A
AAAA
A
A
AAAA
A
A
AAAA
A
A
AAAA
A
A
AAAA
A
A
AAAA
A
AAAAAA
Timer A0 register
Timer A1 register
Timer A2 register
Timer A3 register
Timer A4 register
Timer B0 register
Timer B1 register
Timer B2 register
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
Address
CS
0
control register L
CS
0
control register H
CS
1
control register L
CS
1
control register H
CS
2
control register L
CS
2
control register H
CS
3
control register L
CS
3
control register H
Area CS
0
start address register
Area CS
1
start address register
Area CS
2
start address register
Area CS
3
start address register
Port function select register
External interrupt input control register
External interrupt input read register
D-A control register
D-A register 0
D-A register 1
D-A register 2
80
16
81
16
82
16
83
16
84
16
85
16
86
16
87
16
88
16
89
16
8A
16
8B
16
8C
16
8D
16
8E
16
8F
16
90
16
91
16
92
16
93
16
94
16
95
16
96
16
97
16
98
16
99
16
9A
16
9B
16
9C
16
9D
16
9E
16
9F
16
Particular function select register 0
Particular function select register 1
Particular function select register 2
(Note 2)
Debug control register 0
Debug control register 1
Notes 1:
2:
3:
4:
Address compare register 0 (Note 3)
Address compare register 1 (Note 3)
(Note 1)
(Note 1)
Flash memory control register (Note 4)
(Note 2)
(Note 2)
Do not read out and write to.
Do not write to.
In order to access these registers, be sure to set the address compare register access enable bit (bit 2 at address 67
16
) to “1.”
(Refer to “CHAPTER 18. DEBUG FUNCTION.”)
This register is assigned only in the flash memory version. (Refer to “CHAPTER 20. FLASH MEMORY VERSION.”)
Do no write to this register in the mask ROM version and external ROM version.
A0
16
A1
16
A2
16
A3
16
A4
16
A5
16
A6
16
A7
16
A8
16
A9
16
AA
16
AB
16
AC
16
AD
16
AE
16
AF
16
B0
16
B1
16
B2
16
B3
16
B4
16
B5
16
B6
16
B7
16
B8
16
B9
16
BA
16
BB
16
BC
16
BD
16
BE
16
BF
16
Realtime output control register
Pulse output data register 0
Pulse output data register 1
(Note 2)
(Note 2)
Clock control register
(Note 2)
(Note 2)
(Note 2)
Serial I/O pin control register
Fig. 2.4.2 SFR area’s memory map
2.4 Memory assignment
7902 Group User's Manual
2-22
CENTRAL PROCESSING UNIT (CPU)
2.5 Processor modes
2.5 Processor modes
The M37902 can operate in three processor modes: single-chip mode, memory expansion mode, and
microprocessor mode (Note). Some pins’ functions, memory assignment, and access space vary according
to the processor mode. This section describes the differences according to the processor mode. Figure 2.5.1
shows the memory assignment in each processor mode.
Note: The external ROM version can operate only in the microprocessor mode.
Fig. 2.5.1 Memory assignment in each processor mode
Unused area
Internal
ROM area
(Note 2)
Unused area
016
FF16
SFR area
Single-chip mode
Internal
RAM area
(Note 1)
SFR area
Memory expansion mode
FFFFFF16
SFR area
Microprocessor mode
Internal
RAM area
(Note 1)
Internal
RAM area
(Note 1)
Internal
ROM area
(Note 2)
: This is an external area. The access to this area enables the access to an externally-connected device.
Notes 1: When the internal RAM area is followed by an unused area or an external area, do not assign a program to
the last 8 bytes of the internal RAM area.
2: Do not assign a program to the last 8 bytes of the internal ROM area.
3: Do not access this area.
4: The memory assignment of the internal area varies according to the product type.
Refer to section “Appendix 12. Memory assignment of 7902 Group,” or the latest datasheets, catalogs.
FF000016
FEFFFF16
Reserved
area
(Note 3)
Reserved
area
(Note 3)
7902 Group User's Manual 2-23
CENTRAL PROCESSING UNIT (CPU)
2.5 Processor modes
Figure 2.5.2 shows the pin configuration in each processor mode.
2.5.1 Single-chip mode
This mode is used when not connecting an external device with buses. In this mode, ports P0 to P8, P10,
P11 serve as programmable I/O port pins. (When an internal peripheral device is used, they serve as
corresponding I/O pins).
In this mode, only the internal area (SFR, internal RAM, and internal ROM) can be accessed.
2.5.2 Memory expansion and Microprocessor modes
Each of these modes is used when connecting an external device with buses. In these modes, an external
device can be connected to any required location in the 15.9-Mbyte access space. Also, some programmable
I/O port pins serve as the I/O pins of signals required for the access to the external devices. For the access
to external devices, refer to “CHAPTER 3. CONNECTION WITH EXTERNAL DEVICES.”
The memory expansion and microprocessor modes have the same functions except for the following:
In the microprocessor mode, the access to the internal ROM area is forcedly disabled, and this internal
ROM area is handled as an external area.
If an external device is allocated to an area which overlaps with the internal area, the following are
performed:
When this overlapped area is read out, data in the internal area will be taken into the CPU, but data
in the external area will not be taken in.
When data is written to an overlapped area, the data will be written to the internal area, and the data
will not be output to the external.
For each pin’s function, refer to section “1.3 Pin description,” “CHAPTER 3. CONNECTION WITH EXTERNAL
DEVICES,” “CHAPTER 5. CLOCK GENERATING CIRCUIT,” “CHAPTER 6. INPUT/OUTPUT PINS,” and
each internal peripheral function’s description (chapters 7 through 14).
7902 Group User's Manual
2–24
CENTRAL PROCESSING UNIT (CPU)
2.5 Processor modes
Fig. 2.5.2 Pin configuration in each processor mode (top view)
n Single-chip mode
49
3534 36 39
NMI
P3
0
/RDY
P4
2
/HLDA
D
1
/LA
1
n Memory expansion and Miocroprocessor modes
403736 383534333231 39
64
63
62
61
30
29
28
27
26
25
24
23
22
21
3
2
1
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50494847464544434241
79
78
77
76
75
74
73
72
71
69
68
67
66
65
70
80
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
P4
1
/f
1
P8
1
/CTS
0
/CLK
0
P8
2
/R
X
D
0
P8
3
/T
X
D
0
V
SS
AV
SS
V
REF
V
CC
AV
CC
V
SS
P7
3
/AN
3
P8
4
/CTS
1
/RTS
1
/INT
4
P8
5
/CTS
1
/CLK
1
P8
6
/R
X
D
1
MD1
V
CC
V
SS
X
OUT
X
IN
P4
0
P4
2
V
CONT
RESET
MD0
P10
3
P10
4
P10
5
P10
6
P10
7
P10
1
P10
2
P11
0
P11
1
P11
2
P11
3
P11
4
P11
5
P11
6
P11
7
P0
0
P0
1
P0
2
P0
3
P0
4
P0
5
P0
7
P0
6
P1
0
P1
1
P1
2
P1
5
P2
5
P2
4
P2
3
P2
0
P1
7
P2
2
P2
1
P1
6
P3
3
P3
1
P3
2
P4
5
P6
0
/TA4
OUT
P6
1
/TA4
IN
P6
2
/INT
0
P6
3
/INT
1
P6
4
/INT
2
P6
5
/TB0
IN
P6
6
/TB1
IN
P5
0
/TA0
OUT
/RTP0
0
P5
1
/TA0
IN
/RTP0
1
P5
2
/TA1
OUT
/RTP0
2
P5
3
/TA1
IN
/RTP0
3
P5
4
/TA2
OUT
/RTP1
0
/KI
0
P5
5
/TA2
IN
/RTP1
1
/KI
1
P5
6
/TA3
OUT
/RTP1
2
/KI
2
P5
7
/TA3
IN
/RTP1
3
/KI
3
P4
6
P4
4
P4
3
P2
7
P2
6
P4
7
P6
7
/TB2
IN
P7
0
/AN
0
P7
4
/AN
4
/(INT
3
)
P7
5
/AN
5
/(INT
4
)
P7
6
/AN
6
/DA
0
P7
7
/AN
7
/AD
TRG
/DA
1
/(INT
2
)
P8
0
/CTS
0
/RTS
0
/DA
2
/INT
3
NMI
P8
7
/T
X
D
1
P10
0
P7
1
/AN
1
P7
2
/AN
2
P3
0
BYTE
P1
3
P1
4
Outline: 100P6S-A
4037 38
32 3331
64
63
62
61
3
2
1
4
5
6
7
8
9
10
11
12
13
14
60
59
58
57
56
55
54
53
52
51
50
484746454443
4241
100
79
78
77
76
75
74
73
72
71
69
68
67
66
65
70
80
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
P4
1
/f
1
P8
1
/CTS
0
/CLK
0
P8
2
/R
X
D
0
P8
3
/T
X
D
0
V
SS
P7
3
/AN
3
P8
4
/CTS
1
/RTS
1
/INT
4
P8
5
/CTS
1
/CLK
1
P8
6
/R
X
D
1
MD1
V
CC
V
SS
X
OUT
X
IN
V
CONT
RESET
MD0
A
3
A
4
A
5
A
6
A
7
A
1
A
2
P11
0
/A
8
P11
1
/A
9
P11
2
/A
10
P11
3
/A
11
P11
4
/A
12
P11
5
/A
13
P11
6
/A
14
P11
7
/A
15
P0
0
/A
16
P0
1
/A
17
P0
2
/A
18
P0
3
/A
19
P0
4
/A
20
P0
5
/A
21
P0
7
/A
23
P0
6
/A
22
D
0
/LA
0
D
2
/LA
2
D
5
/LA
5
P2
5
/D
13
P2
4
/D
12
P2
3
/D
11
P2
0
/D
8
D
7
/LA
7
P2
2
/D
10
P2
1
/D
9
D
6
/LA
6
RD
BLW
P4
5
/CS
1
P6
0
/TA4
OUT
P6
1
/TA4
IN
P6
2
/INT
0
P6
3
/INT
1
P6
4
/INT
2
P6
5
/TB0
IN
P6
6
/TB1
IN
P5
0
/TA0
OUT
/RTP0
0
P5
1
/TA0
IN
/RTP0
1
P5
2
/TA1
OUT
/RTP0
2
P5
3
/TA1
IN
/RTP0
3
P5
4
/TA2
OUT
/RTP1
0
/KI
0
P5
5
/TA2
IN
/RTP1
1
/KI
1
P5
6
/TA3
OUT
/RTP1
2
/KI
2
P5
7
/TA3
IN
/RTP1
3
/KI
3
P4
6
/CS
2
P4
4
/CS
0
P4
3
/HOLD
P2
7
/D
15
P2
6
/D
14
P4
7
/CS
3
P6
7
/TB2
IN
P7
0
/AN
0
P7
4
/AN
4
/(INT
3
)
P7
5
/AN
5
/(INT
4
)
P7
6
/AN
6
/DA
0
P7
7
/AN
7
/AD
TRG
/DA
1
/(INT
2
)
P8
0
/CTS
0
/RTS
0
/DA
2
/INT
3
V
SS
AV
SS
V
REF
V
CC
AV
CC
P8
7
/T
X
D
1
A
0
P7
1
/AN
1
P7
2
/AN
2
BYTE
D
3
/LA
3
D
4
/LA
4
30
29
28
27
26
25
24
23
22
21
15
16
17
18
19
20
Each function of these pins in the single-chip mode
is different from that in the memory expansion or
microprocessor mode.
Each function of these pins in the single-chip mode
is different from that in the memory expansion or
microprocessor mode.
P4
0
/ALE
P3
3
/BHW
7902 Group User's Manual 2-25
CENTRAL PROCESSING UNIT (CPU)
2.5 Processor modes
2.5.3 Setting of processor mode
The processor mode is set by the following:
• Voltage level applied to the MD0 pin
• Processor mode bits (bits 1 and 0 at address 5E16)
Note: While the microcomputer is operating, do not switch the voltage level applied to the MD0 pin.
(1) When Vss level is applied to MD0 pin
After reset, the microcomputer starts its operation in the single-chip mode. After the operation starts,
the processor mode can be switched by the processor mode bits. When the processor mode bits =
“012,” the microcomputer enters the memory expansion mode; when these bits = “102,” the microcomputer
enters the microprocessor mode. When the processor mode has been switched during the program
execution, the contents of the instruction queue buffer will not be initialized. (Refer to section “Appendix
8. 7902 Group Q & A.”)
(2) When Vcc level is applied to MD0 pin
After reset, the microcomputer starts its operation in the microprocessor mode. In this case, the
microcomputer cannot operate in any of the other modes. (Fix the processor mode bits = “102.”)
Table 2.5.1 lists the setting methods for processor modes. Figure 2.5.3 shows the structure of processor
mode register 0 (address 5E16).
Table 2.5.1 Setting methods for setting processor mode Processor mode bits
b1 b0
Single-chip mode Vss (Note 1) 0 0
Memory expansion mode Vss (Note 1) 0 1
Microprocessor mode Vss (Note 1)
Vcc (Note 2)
Notes 1: After reset, the microcomputer starts its operation in the single-chip mode. The processor mode
can be switched to another processor mode by the processor mode bits.
2: After reset, the microcomputer starts its operation in the microprocessor mode. The microcomputer
cannot operate in any of the other processor modes, so be sure that the processor mode bits are
fixed as follows: b1 = “1” and b0 = “0.”
Processor mode Voltage level at MD0 pin
1 0
7902 Group User's Manual
2-26
CENTRAL PROCESSING UNIT (CPU)
2.5 Processor modes
Bit nameBit
Processor mode register 0 (Address 5E16)
Function
At reset
R/W
Processor mode bits
External bus cycle select bit 0
(Note 2)
Interrupt priority detection time
select bits
Software reset bit
Clock φ1 output select bit
b7 b6 b5 b4 b3 b2 b1 b0
Notes 1: When the Vss-level voltage is applied to pin MD0, this bit is “0”; when the Vcc-level voltage is applied to pin MD0, this bit
is “1.” (Fixed to “1.”)
2: These bits are valid for the external area except for area CSi. Regardless of these bits’ contents, the bus cycle of area CSi
is decided by the corresponding area CSi bus cycle select bits 0, 1 (bits 0, 1 at addresses 8016, 8216, 8416, 8616, and bit 3
at addresses 8116, 8316, 8516, 8716).
3: When the Vss-level voltage is applied to pin MD0, this bit is “0”; when the Vcc-level voltage is applied to pin MD0, this bit
is “1.”
0 0 : Single-chip mode
0 1 : Memory expansion mode
1 0 : Microprocessor mode
1 1 : Do not select.
b1 b0
0 0 : 7 cycles of fsys
0 1 : 4 cycles of fsys
1 0 : 2 cycles of fsys
1 1 : Do not select.
b5 b4
The microcomputer is reset by writing “1” to this
bit. The value is “0” at reading.
0 : φ1 output is disabled. (P41 functions as a
programmable I/O port pin.)
1 : φ1 output is enabled. (P41 functions as a clock φ1
output pin.)
0
(Note 1)
0
1
0
0
0
(Note 3)
RW
RW
RW
RW
RW
RW
WO
RW
0 0 :
1φ + 1φ
0 1 :
1φ + 2φ
1 0 :
1φ + 3φ
1 1 :
2φ + 2φ
b2b3 0 0 :
2φ + 3φ
0 1 :
2φ + 4φ
1 0 :
3φ + 3φ
1 1 :
3φ + 4φ
b2b3
(External bus cycle select
bit 1 = 0) (External bus cycle select
bit 1 = 1)
Fig. 2.5.3 Structure of processor mode register 0
0
1
2
3
4
5
6
7
7902 Group User's Manual 2-27
CENTRAL PROCESSING UNIT (CPU)
[Precautions for setting of processor mode]
[Precautions for setting of processor mode]
Only the microprocessor mode is available for the external ROM version. Therefore, for the external ROM
version, do as follows:
• The MD0 pin must be connected to Vcc.
• The processor mode bits (bits 0 and 1 at address 5E16) must be fixed to “102.”
7902 Group User's Manual
2-28
CENTRAL PROCESSING UNIT (CPU)
[Precautions for setting of processor mode]
MEMORANDUM
CHAPTER 3CHAPTER 3
CONNECTION WITH
EXTERNAL DEVICES
3.1 Signals required for accessing
external devices
3.2 Chip select wait controller
[Precautions for CSWC]
3.3 Ready function
3.4 Hold function
CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual
3-2
3.1 Signals required for accessing external devices
This chapter explains the functions for connection with external devices.
The bus interface unit (BIU) controls the following. (Refer to section “2.2 Bus interface unit (BIU).”:
• Reading data from devices connected externally
• Writing data to devices connected externally
The bus cycle at access to external devices can be changed by the chip select wait controller (CSWC) and
Ready function. Also, by Hold function, buses can be opened to the external.
3.1 Signals required for accessing external devices
When connecting devices externally, make sure that the microcomputer operates in the memory expansion
or microprocessor mode. (Refer to section “2.5 Processor modes.”) While the microcomputer operates in
one of these modes, a part of programmable I/O port pins serve as I/O pins of signals required for accessing
external devices.
Figure 3.1.1 shows the pin configuration in the memory expansion and microprocessor modes, Figure 3.1.2
shows the external area, Table 3.1.1 lists the pins used for accessing external devices.
Fig. 3.1.1 Pin configuration in memory expansion and microprocessor modes (Top view)
Outline: 100P6Q-A
When BYTE = V
CC
,
P2
0
to P2
7
When BYTE = V
SS
,
D
8
to D
15
When BYTE = V
CC
,
P3
When BYTE = V
SS
,
BHW
P4
1
/φ
1
P4
0
/ALE
P4
2
/HLDA
P4
5
/CS
1
P6
0
/TA4
OUT
P6
1
/TA4
IN
P6
2
/INT
0
P6
3
/INT
1
P6
4
/INT
2
P6
5
/TB0
IN
P6
6
/TB1
IN
P5
0
/TA0
OUT
/RTP0
0
P5
1
/TA0
IN
/RTP0
1
P5
2
/TA1
OUT
/RTP0
2
P5
3
/TA1
IN
/RTP0
3
P5
4
/TA2
OUT
/RTP1
0
/KI
0
P5
5
/TA2
IN
/RTP1
1
/KI
1
P5
6
/TA3
OUT
/RTP1
2
/KI
2
P5
7
/TA3
IN
/RTP1
3
/KI
3
P4
6
/CS
2
P4
4
/CS
0
P4
3
/HOLD
P4
7
/CS
3
P6
7
/TB2
IN
P7
0
/AN
0
100 99 98 97 96
59
58
57
56
55
54
53
52
51
95
74
73
72
71
70
69
68
67
66
64
63
62
61
60
65
75
94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
3029282726 403736 383534333231 39 50494847464544434241
25
24
23
22
21
3
2
1
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
V
CC
V
SS
X
OUT
X
IN
V
CONT
RESET
MD0
D
3
/LA
3
D
4
/LA
4
D
5
/LA
5
P2
5
/D
13
P2
4
/D
12
P2
3
/D
11
P2
0
/D
8
D
7
/LA
7
P2
2
/D
10
P2
1
/D
9
D
6
/LA
6
P2
7
/D
15
P2
6
/D
14
P3
3
/BHW
RD
BLW
P3
0
/RDY
BYTE
V
SS
MD1
A
4
A
5
A
6
A
7
P11
0
/A
8
P11
1
/A
9
P11
2
/A
10
P11
3
/A
11
P11
4
/A
12
P11
5
/A
13
P11
6
/A
14
P11
7
/A
15
P0
0
/A
16
P0
1
/A
17
P0
2
/A
18
P0
3
/A
19
P0
4
/A
20
P0
5
/A
21
P0
7
/A
23
P0
6
/A
22
D
0
/LA
0
D
1
/LA
1
D
2
/LA
2
A
3
A
1
A
2
P8
7
/T
X
D
1
A
0
P8
1
/CTS
0
/CLK
0
P8
2
/R
X
D
0
P8
3
/T
X
D
0
V
SS
AV
SS
V
REF
V
CC
AV
CC
P7
3
/AN
3
P7
2
/AN
2
P7
1
/AN
1
P8
4
/CTS
1
/RTS
1
/INT
4
P8
5
/CTS
1
/CLK
1
P8
6
/R
X
D
1
P7
4
/AN
4
/(INT
3
)
P7
5
/AN
5
/(INT
4
)
P7
6
/AN
6
/DA
0
P7
7
/AN
7
/AD
TRG
/DA
1
/(INT
2
)
P8
0
/CTS
0
/RTS
0
/DA
2
/INT
3
NMI
CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual 3-3
3.1 Signals required for accessing external devices
Fig. 3.1.2 External area
Memory expansion mode
SFR area
Internal RAM
area (Note 1)
Internal ROM
area
(Note 2)
Reserved area
(Note 3)
Microprocessor mode
SFR area
Internal RAM
area (Note 1)
Reserved area
(Note 3)
016
FF16
FEFFFF16
FF000016
FFFFFF16
External area : Access to this area enables the access to the devices which
are connected with the external.
Notes 1: When the internal RAM area is followed by an external area, do not assign
a program to the last 8 bytes of the internal RAM area.
2: Do not assign a program to the last 8 bytes of the internal ROM area.
3: Do not access this area.
4: The memory map of the internal area depends on the devices type.
Therefore, for details, refer to section “Appendix 12. Memory assignment
of 7902 Group,” the latest datasheets, and catalogs.
CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual
3-4
3.1 Signals required for accessing external devices
Address ( A0–A23) output pins
I/O pins for data (D0–D7) at an even- I/O pins for data (D0–D7)
numbered address
I/O pins for data (D8–D15) at an odd- Programmable I/O port pins (P2)
numbered address (Note 3)
Input pin for signals related to Ready function (Refer to section “3.3 Ready function.” )
Output pin for read singnal (“L” level is output while data bus is read out.)
Output pin for write signal (“L” level
is output while data is written to an
even-numbered address.)
Output pin for write signal (“L” level
is output while data is written to an
odd-numbered address.) (Note 5)
Output pin for address latch enable signal (This pin indicates address
stabilization and can be used to latch an address.)
Clock φ
1
output pin (This pin outputs a signal with the same period of f
sys
. Refer to “CHAPTER 5. CLOCK GENERATING CIRCUIT.”)
Input pin for signals related to Hold function (Refer to section “3.4 Hold function.”)
Output pin for signals related to Hold function (Refer to section “3.4 Hold function.”)
Chip select output pins (Refer to section “3.2 Chip select wait controller.”)
External data bus width select input pin (When VSS level is input, 16-bit width is selected; When
VCC level is input, 8-bit width is selected.)
Table 3.1.1 Pins used for accessing external devices
A0–A23
D0–D7 (Note 2)
D8–D15
RDY
RD
BLW
BHW
ALE
φ1
HOLD
HLDA
CS0–CS3
BYTE (Note 6)
Pin Access to external devices
External data bus width = 16 bits (BYTE = Vss level) External data bus width = 8 bits (BYTE = Vcc level)
Undefined (Note 1).
Floating.
Floating.
(Note 4)
Invalid.
“H” level is output.
“H” level is output.
“H” level is output.
(Note 4)
“L” level is output.
Invalid.
“H” level is output.
“H” level is output.
Programmable I/O port pin (P33)
Access to internal
devices
Output pin for write signal (“L” level
is output while data is written to the
external area.)
Notes 1: Address outputs at access to internal areas can be fixed by software. (Refer to section “3.2.4
Address output selection.”)
2: When area CS2 is accessed with the external data bus width = 8 bits, by software, the address
output (LA0–LA7) and the data input/output (D0–D7) can be performed with the time-sharing method.
(Refer to section “3.2.2 External bus operations.”)
3: When an area with the external data bus width = 8 bits is accessed by software, these pins are
placesd in the floating state. (See Figure 2.2.6.)
4: This applies only when the external data bus width = 16 bits (BYTE = Vss level).
5: When an area with the external data bus width = 8 bits is accessed by software, “H” level is output.
(See Figure 2.2.6.)
6: Do not change the input level to this pin while the microcomputer is operating.
The data bus width selected by the input to pin BYTE is valid only for the external areas. (See
Figure 3.1.2.) When an internal area is accessed, the data bus width is always fixed to 16 bits.
When BYTE = Vss, the external data bus width of 8 bits can independently be selected by
software for each of areas CS1–CS3. (Refer to section “3.2 Chip select wait controller.”)
7: For details of each signal and input/output timings, refer to each reference and section “Appendix
9. M37902FGCGP electrical characteristics” and “Appendix 10. M37902FGMHP electrical
characteristics.”
CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual 3-5
3.1 Signals required for accessing external devices
The pins required for accessing external devices are explained below:
(1) In order to switch the processor mode from the single-chip mode to memory expansion or microprocessor
mode after reset with Vss applied to pin MD0, specify the function of the related pins by using the
following bits. (Reset with MD0 = Vss makes these pins to be programmable I/O port pins).
• Pin RDY: RDY input select bit (bit 2 at address 5F16)
• Pin ALE: ALE output select bit (bit 3 at address 5F16)
• Pin φ1: clock φ1 output select bit (bit 7 at address 5E16)
• pins HOLD, HLDA
: HOLD input, HLDA output select bit (bit 5 at address 5F16)
• Pins CS0–CS3: CS0 output select bit (bit 7 at address 8016)
CS1 output select bit (bit 7 at address 8216)
CS2 output select bit (bit 7 at address 8416)
CS3 output select bit (bit 7 at address 8616)
(2) Switches between addresses and ports
The address/port switch bits switch between addresses A8–A23 and ports P0, P11 (See Figure 3.1.3.),
so that address output pins not needed can be used as programmable I/O port pins, according to the
access space required. (Refer to section “2.3 Access space.”)
(3) Pullups of P44 (CS0)–P47 (CS3)
While pin RESET = “L” level and after reset, pins P44 (CS0)–P47 (CS3) are pulled up. Therefore,
external pullup resistors are not needed for these pins.
Setting the pins P44–P47 pullup select bit to “1” removes the pullups. (See Figure 3.1.3.)
Either of the following settings also removes the pullups regardless of the contents of the pins P44
P47 pullup select bit. (The bit’s contents remain unchanged).
• Setting the port direction register corresponding to P44–P47 to “1” (output mode).
• Setting the CS0–CS3 output select bits (bit 7 at addresses 8016, 8216, 8416, and 8616) corresponding
to P44 (CS0)–P47 (CS3) to “1” (CS0–CS3 outputs enabled).
Note that P44–P47 in the flash memory parallel I/O mode (MD1 and MD0 = Vcc), and CS0 (P44) in the
microprocessor mode (MD1 = Vss and MD0 = Vcc) will not be pulled up regardless of the pins P44
P47 pullup select bit.
For details of the flash memory parallel I/O mode, refer to section “20.4 Flash memory parallel
I/O mode.”
CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual
3-6
3.1 Signals required for accessing external devices
Fig. 3.1.3 Structure of port function control register
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
Port function control register (Address 9216)b7 b6 b5 b4 b3 b2 b1 b0
0
1
2
3
4
6, 5
7
Bit nameBit Function
At reset
R/W
Address/Port switch select bits
Port P0 input level select bit
P44–P47 pullup select bit
Fix these bit s to “1.”
Pin NMI pullup connection
select bit
0 0 0 : A0 to A23 (16 Mbytes)
0 0 1 : A0 to A21, P06, P07 (4 Mbytes)
0 1 0 : A0 to A19, P04 to P07 (1 Mbytes)
0 1 1 : A0 to A17, P02 to P07 (256 Kbytes)
1 0 0 : A0 to A15, P00 to P07 (64 Kbytes)
1 0 1 : Do not select.
1 1 0 : A0 to A11, P00 to P07, P114 to P117 (4 Kbytes)
1 1 1 : A0 to A7, P00 to P07, P110 to P117 (256 bytes)
b2 b1b0
Notes 1: For the M37902FxMHP (power source voltage = 3.3 V±0.3 V), VIH = 0.5 VCC.
2: When MD 1 = V CC and MD 0 = V CC (flash memory parallel I/O mode), pins P 44 to P 47 and NM I are not pulled up, regardless of
these bits’ contents.
3: When MD1 = VSS and MD0 = VCC (microprocessor mode), pin CS0 (P44) is not pulled up, regardless of the bits’ contents.
0 : P44 to P47 are pulled up.
1 : P44 to P47 are not pulled up. (Notes 2 and 3)
0 : Pin NMI is pulled up.
1 : Pin NMI is not pulled up. (Note 2)
0 : VIH = 0.7 VCC, VIL = 0.2 VCC
1 : VIH = 0.43 VCC (Note 1), VIL = 0.16 VCC
00
CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual 3-7
3.2 Chip select wait controller
3.2 Chip select wait controller
The chip select wait controller (CSWC) controls the bus cycle at access to the external areas. By CSWC,
the chip select areas (CS0–CS3) of the maximum of 4 blocks can be set in the address space from banks
016 through FE16. (See Figures 3.2.10 to 3.2.12). For each chip select area, the functions listed in Table 3.2.1
can be specified.
For the external areas except for areas CS0–CS3, the functions listed in Table 3.2.1 can also be specified.
Table 3.2.1 Functions of areas CS0 through CS3
Notes 1: When BYTE = Vcc level, the external data bus width is fixed to 8 bits.
2: Burst ROM access is valid only when the external data bus width is 16 bits with instruction prefetched.
3: Burst ROM access and area multiplexed bus access cannot be used at the same time.
4: Valid only when area CS2 is accessed with the 8-bit external data bus width.
5: The address output selection cannot be specified for each area. (Refer to section “3.2.4 Address
output selection.”)
Space where start
address can be set
Block size
Bus cycle
External data bus
width
RDY control
Burst ROM access
(Notes 2, 3)
Recovery cycle
insertion
Area multiplexed bus
access (Note 3)
Address output
selection (Note 5)
CS0CS1, CS 2CS3
External area except
for CS
0
to CS
3
Mode 0 Mode 1
Banks 216
to FE 16
128 Kbytes,
256 Kbytes,
512 Kbytes,
1 Mbytes,
2 Mbytes,
4 Mbytes,
or 8 Mbytes
Bus cycle
•1φ + 1 φ
•1φ + 2 φ
•1φ + 3 φ
•2φ + 2 φ
•2φ + 3 φ
•2φ + 4 φ
•3φ + 3 φ
•3φ + 4 φ
(Selected by bits 0, 1 at address
80 16 and bit 3 at address 8116.)
Determined by pin BYTE’s level.
Valid (Selected by bit 2 at address
5F16 and bit 3 at address 8016.)
Available.
Available.
Not available.
Available.
Banks 216
to FE16
128 Kbytes,
256 Kbytes,
512 Kbytes,
1 Mbytes,
2 Mbytes,
4 Mbytes,
or 8 Mbytes
Bus cycle
•1φ + 1φ
•1φ + 2φ
•1φ + 3φ
•2φ + 2φ
•2φ + 3φ
•2φ + 4φ
•3φ + 3φ
•3φ + 4φ
(Selected by bits 0, 1 at addresses
8216, 8416 and bit 3 at addresses
8316, 8516.)
When BYTE = V SS level, 8-bit width or
16-bit width can be selected arbitrary
(Note 1) .
Valid (Selected by bit 2 at address
5F16 and bit 3 at addresses 8216,
8416.)
Available.
Available.
CS1: Not available.
CS2: Available. (Note 4)
Available.
Bank 016
4 Kbytes,
or 8 Kbytes
Banks 216
to FE16
128 Kbytes,
256 Kbytes,
512 Kbytes,
1 Mbytes,
2 Mbytes,
4 Mbytes,
or 8 Mbytes
Bus cycle
•1φ + 1φ
•1φ + 2φ
•1φ + 3φ
•2φ + 2φ
•2φ + 3φ
•2φ + 4φ
•3φ + 3φ
•3φ + 4φ
(Selected by bits 0,
1 at address 86
16
and bit 3 at address
87
16
.)
When BYTE = V
SS
level, 8-bit width or
16-bit width can be
selected arbitrary
(Note 1).
Valid (Selected by
bit 2 at address
5F16 and bit 3 at
address 8616.)
Available.
Available.
Not available.
Available.
Bus cycle
•1φ + 1φ
•1φ + 2φ
•1φ + 3φ
•2φ + 2φ
•2φ + 3φ
•2φ + 4φ
•3φ + 3φ
•3φ + 4φ
(Selected by bits 2,
3 at address 5E
16
and bit 0 at address
5F
16
.)
Determined by pin
BYTE’s level.
Valid (Selected by
bit 2 at address
5F16.)
Not available.
Available.
Not available.
Available.
Mode 0 Mode 1
Bank 016
128 Kbytes,
256 Kbytes,
512 Kbytes,
1 Mbytes,
2 Mbytes,
4 Mbytes,
or 8 Mbytes
CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual
3-8
Bit nameBit
Processor mode register 0 (Address 5E16)
Function
At reset
R/W
Processor mode bits
External bus cycle select bit 0
(Note 2)
Interrupt priority detection time
select bits
Software reset bit
Clock φ1 output select bit
b7 b6 b5 b4 b3 b2 b1 b0
Notes 1: When the Vss-level voltage is applied to pin MD0, this bit is “0”; when the Vcc-level voltage is applied to pin MD0, this bit
is “1.” (Fixed to “1.”)
2: These bits are valid for the external area except for area CSi. Regardless of these bits’ contents, the bus cycle of area CSi
is decided by the corresponding area CSi bus cycle select bits 0, 1 (bits 0, 1 at addresses 8016, 8216, 8416, 8616, and bit 3
at addresses 8116, 8316, 8516, 8716).
3: When the Vss-level voltage is applied to pin MD0, this bit is “0”; when the Vcc-level voltage is applied to pin MD0, this bit
is “1.”
0 0 : Single-chip mode
0 1 : Memory expansion mode
1 0 : Microprocessor mode
1 1 : Do not select.
b1 b0
0 0 : 7 cycles of fsys
0 1 : 4 cycles of fsys
1 0 : 2 cycles of fsys
1 1 : Do not select.
b5 b4
The microcomputer is reset by writing “1” to this
bit. The value is “0” at reading.
0 : φ1 output is disabled. (P41 functions as a
programmable I/O port pin.)
1 : φ1 output is enabled. (P41 functions as a clock φ1
output pin.)
0
1
2
3
4
5
6
7
0
(Note 1)
0
1
0
0
0
(Note 3)
RW
RW
RW
RW
RW
RW
WO
RW
0 0 :
1φ + 1φ
0 1 :
1φ + 2φ
1 0 :
1φ + 3φ
1 1 :
2φ + 2φ
b2b3 0 0 :
2φ + 3φ
0 1 :
2φ + 4φ
1 0 :
3φ + 3φ
1 1 :
3φ + 4φ
b2b3
(External bus cycle select
bit 1 = 0) (External bus cycle select
bit 1 = 1)
3.2.1 Related registers
The related registers are explained below.
(1) Processor mode register 0
Figure 3.2.1 shows the structure of the processor mode register 0.
Fig. 3.2.1 Structure of processor mode register 0
External bus cycle select bit 0 (bits 2, 3)
The combination of this bit and the external bus cycle select bit 1 (bit 0 at address 5F16) selects
the bus cycle at access to the external areas except for areas CS0–CS3. (Refer to section “3.2.2
External bus operations.”)
3.2 Chip select wait controller
CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual 3-9
3.2 Chip select wait controller
(2) Processor mode register 1
Figure 3.2.2 shows the structure of the processor mode register 1.
RW
RW
RW
RW
RW
RW
RW
RW
0
0
(Note 4)
(Note 4)
(Note 4)
(Note 4)
0
0
Processor mode register 1 (Address 5F16)
0
1
2
3
4
5
6
7
Bit nameBit Function
At reset
R/W
b7 b6 b5 b4 b3 b2 b1 b0
0 : Only DPR0 is used.
1 : DPR0 through DPR3 are used.
0 : RDY input is disabled.
(P30 functions as a programmable I/O port pin.)
1 : RDY input is enabled. (P30 functions as pin RDY.)
0 : ALE output is disabled.
(P40 functions as a programmable I/O port pin.)
1 : ALE output is enabled. (P40 functions as pin ALE.)
0 : No recovery cycle is inserted at access to external area.
1 : Recovery cycle is inserted at access to external area.
0 : HOLD input and HLDA output are disabled.
(P43 and P4 2 function as programmable I/O port pins.)
1 : HOLD input and HLDA output are enabled.
(P43 and P4 2 function as pins HOLD and HLDA.)
0 : 1 cycle
1 : 2 cycles
0 : 3φ
1 : 2φ
(Note 5)
(Note 5)
The combination of this bit and the external bus cycle
select bit 0 selects the bus cycle.
0 : 1φ + 1φ, 1φ + 2φ, 1φ + 3φ, or 2φ + 2φ
1 : 2φ + 3φ, 2φ + 4φ, 3φ + 3φ, or 3φ + 4φ
(Note 2)
External bus cycle select bit 1
(Note 1)
Direct page register switch bit
RDY input select bit (Note 3)
ALE output select bit (Note 3)
Recovery cycle insert select bit
(Note 3)
HOLD input, HLDA output select
bit (Note 3)
Recovery-cycle-insert number
select bit (Note 6)
Internal ROM bus cycle select bit
(Note 7)
Notes 1: This bit is valid for the external area except for area CSi. Regardless of these bits’ contents, the bus cycle of area CSi is
decided by the corresponding area CSi bus cycle select bits 0, 1 (bits 0, 1 at addresses 8016, 82 16, 8416, 86 16, and bit 3 at
addresses 8116, 8316, 8516, 8716).
2: After reset, this bit can be set only once. (During the software execution, be sure not to change this bit’s contents.)
3: In the single-chip mode, all of these bits’ functions are disabled regardless of these bits’ contents.
4: When the Vss-level voltage is applied to pin MD0, this bit is “0”; when the Vcc-level voltage is applied to pin MD0, this bit
is “1.”
5: After reset, this bit can be set to “1” only once. Once this bit has been cleared from “1” to “0,” it cannot be back to “1”
again. (Fixed to “0.”)
6: Make sure that a program to be used to change this bit’s contents is allocated in the internal area.
7: In the microprocessor mode, this bit is invalid. This bit is not assigned to the external ROM version. (“0” at reading.)
To reprogram the internal flash memory by using the CPU reprogramming mode, clear this bit to “0.” (Refer to section
“20.2 Flash memory CPU reprogramming mode.”)
Fig. 3.2.2 Structure of processor mode register 1
CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual
3-10
External bus cycle select bit 1 (bit 0)
The combination of this bit and the external bus cycle select bit 0 (bits 2, 3 at address 5E16) selects
the bus cycle at access to the external areas except for areas CS0 to CS3. (Refer to section “3.2.2
External bus operations.”)
RDY input select bit (bit 2)
This bit selects whether the RDY input is enabled or not. Setting this bit to “1” enables the RDY
control at access to the external areas except for areas CS0 to CS3.
To validate the RDY control at the access to any of areas CS0 to CS3, set this bit to “1” and clear
the corresponding RDY control bit for areas CS0 to CS3 (bit 3 at address 8016, 8216, 8416, or 8616)
to “0.”
Recovery cycle insert select bit (bit 4)
This bit decides whether recovery cycles are inserted or not at access to the external areas except
for areas CS0 to CS3. Setting this bit to “1” inserts such recovery cycles as 1 or 2 cycles of φ1 after
the bus cycle for access to an external area. The number of recovery cycles to be inserted is
specified by the recovery-cycle-insert number select bit (bit 6). Insertion of recovery cycles allows
devices with longer output disable time at read to be connected without using bus buffers.
Since addresses are maintained throughout recovery cycles, devices requiring longer address hold
time can easily be connected; on the other hand, by inserting 2 recovery cycles to extend the data
hold time at write by 1 cycle of φ1, devices requiring longer data hold time can also be connected.
(Refer to section “3.2.2 External bus operations.”)
Recovery-cycle-insert number select bit (bit 6)
This bit selects the number of recovery cycles to be inserted. 1 and 2 cycles are selectable.
The number of recovery cycles selected by this bit is valid for all of the external areas including
areas CS0 to CS3.
To insert recovery cycles, each recovery cycle insert select bit for each area (bit 4 at address 5F 16
and bit 6 at address 8016, 8216, 8416, or 8616) must be set to “1.”
Make sure that a program to be used to change this bit’s contents is allocated in the internal area.
3.2 Chip select wait controller
CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual 3-11
3.2 Chip select wait controller
(3) CS0 control register L
Figure 3.2.3 shows the structure of the CS0 control register L.
CS0 control register L (Address 8016)b7 b6 b5 b4 b3 b2 b1 b0
Notes 1: This bit is “0” when Vss-level voltage is applied to pin BYTE; this bit is “1” when Vcc-level voltage is applied.
2: This bit is valid when the RDY input select bit (bit 2 at address 5F16) is “1.”
3: When Vcc-level voltage is applied to pin BYTE, “normal access” is selected regardless of this bit’s value.
4: This bit’s contents are invalid in the single-chip mode. (CS0 output disabled)
5: This bit is “0” when Vss-level voltage is applied to pin MD0; this bit is “1” when Vcc-level voltage is applied. (Fixed to “1.”)
The input level at pin BYTE is read out.
0 : 16-bit width
1 : 8-bit width
0 : RDY control is valid.
1 : RDY control is invalid.
0 : Normal access
1 : Burst ROM access
0 : No recovery cycle is inserted at access to area CS0.
1 : Recovery cycle is inserted at access to area CS0.
0 : CS0 output is disabled. (P44 functions as a
programmable I/O port pin.)
1 : CS0 output is enabled. (P44 functions as pin CS0.)
Bit nameBit Function At reset R/W
0
1
2
3
4
5
6
7
Area CS0 bus cycle select bit 0
External data bus width select bit
RDY control bit (Note 2)
The value is “0” at reading.
Burst ROM access select bit
(Note 3)
Recovery cycle insert select bit
CS0 output select bit (Note 4)
RW
RW
RO
RW
RW
RW
RW
0
1
(Note 1)
0
0
0
1
(Note 5)
0 0 :
1φ + 1φ
0 1 :
1φ + 2φ
1 0 :
1φ + 3φ
1 1 :
2φ + 2φ
b0b1 0 0 :
2φ + 3φ
0 1 :
2φ + 4φ
1 0 :
3φ + 3φ
1 1 :
3φ + 4φ
b0b1
(Area CS0 bus cycle select
bit 1 = 0) (Area CS0 bus cycle select
bit 1 = 1)
Fig. 3.2.3 Structure of CS0 control register L
CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual
3-12
3.2 Chip select wait controller
Area CS0 bus cycle select bit 0 (bits 0, 1)
The combination of this bit and the area CS0 bus cycle select bit 1 (bit 3 at address 8116) selects
the bus cycle at access to area CS0. (Refer to section “3.2.2 External bus operations.”)
External data bus width select bit (bit 2)
Reading this bit informs the input level at pin BYTE. The external data bus width at access to area
CS0 is decided by the input level at pin BYTE. (When BYTE = Vss level, 16-bit width; when BYTE
= Vcc level, 8-bit width.)
RDY control bit (bit 3)
This bit decides whether the RDY control is valid or not at access to area CS0.
While the RDY input select bit (bit 2 at address 5F16) = “1,” this bit is valid. (Refer to section “3.3
Ready function.”)
Burst ROM access select bit (bit 5)
When ROM, etc., supporting burst access, is allocated to area CS0, the burst access for the
maximum of 8 bytes becomes available if this bit is set to “1.” The burst ROM access is valid only
when the external data bus width = 16 bits with instructions prefetched. When the external data
bus width = 8 bits or when data is read or written, “normal access” is specified regardless of this
bit’s contents. (Refer to section “3.2.2 External bus operations.”)
Recovery cycle insert select bit (bit 6)
This bit decides whether recovery cycles are inserted or not at access to area CS0. Setting this
bit to “1” inserts such recovery cycles as 1 or 2 cycles of φ1 after the bus cycle for access to area
CS0. The number of recovery cycles to be inserted is selected by the recovery-cycle-insert number
select bit (bit 6 at address 5F16). Insertion of recovery cycles allows devices with longer output
disable time at read to be connected without using bus buffers.
Since addresses are maintained throughout recovery cycles, devices requiring longer address hold
time can easily be connected; on the other hand, by inserting 2 recovery cycles to extend the data
hold time at write by 1 cycle of φ1, devices requiring longer data hold time can also be connected.
(Refer to section “3.2.2 External bus operations.”)
CS0 output select bit (bit 7)
Setting this bit to “1” outputs a chip select signal at access to area CS0.
Even though this bit has been cleared to “0” in order to disable CS0 output, setting for each
function of area CS0 (See Table 3.2.1.) is valid if the area CS0 block size select bits (bits 2 to 0
at address 8116) are not “0002” (in other words, area CS0 is invalid.)
Moreover, even when area CS0 is invalid, setting this bit to “1” validates pin CS0. (“H” level is
output.)
CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual 3-13
3.2 Chip select wait controller
(4) CS0 control register H
Figure 3.2.4 shows the structure of the CS0 control register H.
0: Mode 0 (A block can be set to 16-Mbyte space.)
1: Mode 1 (Area CS0 start address is set in bank 0.)
CS0 control register H (Address 8116)
0
1
2
3
6 to 4
7
Bit nameBit Function
At reset
R/W
Ares CS0 block size select bits
Area CS0 bus cycle select bit 1
The value is “0” at reading.
Area CS0 setting mode select bit
0 0 0 : 0 byte (Area CS0 is invalid.)
0 0 1 : 128 Kbytes
0 1 0 : 256 Kbytes
0 1 1 : 512 Kbytes
1 0 0 : 1 Mbytes
1 0 1 : 2 Mbytes
1 1 0 : 4 Mbytes
1 1 1 : 8 Mbytes
b2 b1b0
b7 b6 b5 b4 b3 b2 b1 b0
1
0
0
0
0
1
RW
RW
RW
RW
RW
The combination of this bit and the area CS0 bus cycle
select bit 0 selects the bus cycle.
0 : 1φ + 1φ, 1φ + 2φ, 1φ + 3φ, or 2φ + 2φ
1 : 2φ + 3φ, 2φ + 4φ, 3φ + 3φ, or 3φ + 4φ
Area CS0 block size select bit (bits 2 to 0)
These bits select the block size of area CS0. Clearing these bits to “0002” invalidates area CS0.
When the block size has been selected, area CS0 becomes valid, and setting for each function of
area CS0 is valid, regardless of the CS0 output select bit (bit 7 at address 8016). (See Table 3.2.1.)
Area CS0 bus cycle select bit 1 (bit 3)
The combination of this bit and the area CS0 bus cycle select bit 0 (bits 0, 1 at address 8016)
selects the bus cycle at access to area CS0. (Refer to section “3.2.2 External bus operations.”)
Area CS0 setting mode select bit (bit 7)
This bit selects the setting mode of the block size.
For details of area CS0, see Figures 3.2.10 and 3.2.11.
Fig. 3.2.4 Structure of CS0 control register H
CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual
3-14
3.2 Chip select wait controller
CS1 control register L (Address 8216)
CS2 control register L (Address 8416)
CS3 control register L (Address 8616)
0
1
2
3
4
5
6
7
Area CSj bus cycle select bit 0
(j = 1 to 3)
External data bus width select bit
RDY control bit (Note 2)
The value is “0” at reading.
Burst ROM access select bit
(Note 3)
Recovery cycle insert select bit
CSj output select bit
(j = 1 to 3) (Note 4)
(5) CSj control register L
Figure 3.2.5 shows the structure of the CSj (j = 1 to 3) control register L.
Fig. 3.2.5 Structure of CSj (j = 1 to 3) control register L
RW
RW
RW
RW
RW
RW
RW
b7 b6 b5 b4 b3 b2 b1 b0
Notes 1: This bit is fixed to “1” (8-bit width) when Vcc-level voltage is applied to pin BYTE.
2: Valid when the RDY input select bit (bit 2 at 5F16) is “1.”
3: When the external data bus width select bit (bit 2) is “1” or when Vcc-level voltage is applied to pin BYTE, “normal access”
is selected regardless of this bit’s value.
4: This bit’s value is invalid in the single-chip mode. (CSj output is disabled.)
0 : 16-bit width
1 : 8-bit width (Note 1)
0 : RDY control is valid.
1 : RDY control is invalid.
0 : Normal access
1 : Burst ROM access
0 : No recovery cycle is inserted with area CSj selected.
1 : Recovery cycle is inserted with area CSj selected.
0 : CSj output is disabled. (P4 5 to P47 function as
programmable I/O port pins.)
1 :
CS
j
output is enabled. (P4
5
to P4
7
function as pin CS
j
.)
0
1
0
0
0
0
1
0
Bit nameBit Function At reset R/W
0 0 :
1φ + 1φ
0 1 :
1φ + 2φ
1 0 :
1φ + 3φ
1 1 :
2φ + 2φ
b0b1 0 0 :
2φ + 3φ
0 1 :
2φ + 4φ
1 0 :
3φ + 3φ
1 1 :
3φ + 4φ
b0b1
(Area CSj bus cycle select
bit 1 = 0) (Area CSj bus cycle select
bit 1 = 1)
CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual 3-15
3.2 Chip select wait controller
Area CSj bus cycle select bit 0 (bits 0, 1)
The combination of this bit and the area CSj bus cycle select bit 1 (bit 3 at addresses 8316, 8516,
8716) selects the bus cycle at access to area CSj. (Refer to section “3.2.2 External bus operations.”)
External data bus width select bit (bit 2)
When the input level at pin BYTE = Vss level, this bit can arbitrarily select the external data bus
width at access to area CSj.
When the input level at pin BYTE = Vcc level, the external data bus width = 8 bits regardless of
this bit’s contents.
RDY control bit (bit 3)
This bit decides whether the RDY control is valid or not at access to area CSj.
While the RDY input select bit (bit 2 at address 5F16) = “1,” this bit is valid. (Refer to section “3.3
Ready function.”)
Burst ROM access select bit (bit 5)
When ROM, etc., supporting burst access, is allocated to area CSj, the burst access for the
maximum of 8 bytes becomes available if this bit is set to “1.” The burst ROM access is valid only
when the external data bus width = 16 bits with instructions prefetched. When the external data
bus width = 8 bits or when data is read or written, “normal access” is specified regardless of this
bit’s contents. (Refer to section “3.2.2 External bus operations.”)
Recovery cycle insert select bit (bit 6)
This bit decides whether recovery cycles are inserted or not at access to area CSj. Setting this bit
to “1” inserts such recovery cycles as 1 or 2 cycles of φ1 after the bus cycle for accessing area
CSj. The number of recovery cycles to be inserted is selected by the recovery-cycle-insert number
select bit (bit 6 at address 5F16). Insertion of recovery cycles allows devices with longer output
disable time at read to be connected without using bus buffers.
Since addresses are maintained throughout recovery cycles, devices requiring longer address hold
time can easily be connected; on the other hand, by inserting 2 recovery cycles to extend the data
hold time at write by 1 cycle of φ1, devices requiring longer data hold time can also be connected.
(Refer to section “3.2.2 External bus operations.”)
CSj output select bit (bit 7)
Setting this bit to “1” outputs a chip select signal at access to area CSj.
Even though clearing this bit to “0” in order to disable CSj output, setting for each function of area
CSj (See Table 3.2.1.) is valid if the area CSj block size select bits (bits 2 to 0 at addresses 8316,
8516, 8716) are not “0002” (in other words, area CSj is invalid.)
Moreover, even when area CSj is invalid, setting this bit to “1” validates pin CSj. (“H” level is
output.)
CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual
3-16
3.2 Chip select wait controller
(6) CS1 control register H
Figure 3.2.6 shows the structure of the CS1 control register H.
Fig. 3.2.6 Structure of CS1 control register H
CS1 control register H (Address 8316)
0
1
2
3
4
5
6
7
Area CS1 block size select bits
Area CS1 bus cycle select bit 1
The value is “0” at reading.
Fix this bit to “0.”
The value is “0” at reading.
Area CS 1 setting mode select bit
0 0 0 : 0 byte
(Area CS
1
is invalid.)
0 0 1 : 128 Kbytes
0 1 0 : 256 Kbytes
0 1 1 : 512 Kbytes
1 0 0 : 1 Mbytes
1 0 1 : 2 Mbytes
1 1 0 : 4 Mbytes
1 1 1 : 8 Mbytes
b2 b1b0
b7 b6 b5 b4 b3 b2 b1 b0
0 : Mode 0 (A block can be set to 16-Mbyte space.)
1 : Mode 1 (A block can be set to bank 0.)
(Mode 0) 0 byte
(Area CS
1
is invalid.)
Do not select.
Do not select.
Do not select.
4 Kbytes
8 Kbytes
Do not select.
Do not select.
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
Bit nameBit Function At reset R/W
(Mode 1)
The combination of this bit and the area CS1 bus
cycle select bit 0 selects the bus cycle.
0 : 1φ + 1φ, 1φ + 2φ, 1φ + 3φ, or 2φ + 2φ
1 : 2φ + 3φ, 2φ + 4φ, 3φ + 3φ, or 3φ + 4φ
0
Area CS1 block size select bit (bits 2 to 0)
These bits select the block size of area CS1. Clearing these bits to “0002” invalidates area CS1.
When the block size has been selected, area CS1 becomes valid and setting for each function of
area CS1 becomes valid, regardless of the CS1 output select bit (bit 7 at address 8216). (See Table
3.2.1.)
Area CS1 bus cycle select bit 1 (bit 3)
The combination of this bit and the area CS1 bus cycle select bit 0 (bits 0, 1 at address 8216)
selects the bus cycle at access to area CS1. (Refer to section “3.2.2 External bus operations.”)
Area CS1 setting mode select bit (bit 7)
This bit selects the setting mode of the block size.
For details of area CS1, see Figures 3.2.10 and 3.2.12.
CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual 3-17
3.2 Chip select wait controller
(7) CS2 control register H
Figure 3.2.7 shows the structure of the CS2 control register H.
Fig. 3.2.7 Structure of CS2 control register H
CS2 control register H (Address 8516)
0 0 0 : 0 byte
(Area CS
2
is invalid.)
0 0 1 : 128 Kbytes
0 1 0 : 256 Kbytes
0 1 1 : 512 Kbytes
1 0 0 : 1 Mbytes
1 0 1 : 2 Mbytes
1 1 0 : 4 Mbytes
1 1 1 : 8 Mbytes
b2 b1b0
b7 b6 b5 b4 b3 b2 b1 b0
0 : Mode 0 (A block can be set to 16-Mbyte space.)
1 : Mode 1 (A block can be set to bank 0.)
(Mode 0) 0 byte
(Area CS
2
is invalid.)
Do not select.
Do not select.
Do not select.
4 Kbytes
8 Kbytes
Do not select.
Do not select.
Bit nameBit Function At reset R/W
(Mode 1)
The combination of this bit and the area CS2 bus
cycle select bit 0 selects the bus cycle.
0 : 1φ + 1φ, 1φ + 2φ, 1φ + 3φ, or 2φ + 2φ
1 : 2φ + 3φ, 2φ + 4φ, 3φ + 3φ, or 3φ + 4φ
0
1
2
3
4
5
6
7
Area CS2 block size select bits
Area CS2 bus cycle select bit 1
The value is “0” at reading.
Multiplexed bus select bit
The value is “0” at reading.
Area CS2 setting mode select bit
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
0 : Separated bus. Input/Output for D0–D7.
1 : Multiplexed bus. LA0/D0–LA7/D7 are input/output
when the external data bus = 8 bits (bit 2 at address
8416 = 1) with area CS2 accessed.
Area CS2 block size select bit (bits 2 to 0)
These bits select the block size of area CS2. Clearing these bits to “0002” invalidates area CS2.
When the block size has been selected, area CS2 becomes valid and setting for each function of
area CS2 becomes valid, regardless of the CS2 output select bit (bit 7 at address 8416). (See Table
3.2.1.)
Area CS2 bus cycle select bit 1 (bit 3)
The combination of this bit and the area CS2 bus cycle select bit 0 (bits 0, 1 at address 8416)
selects the bus cycle at access to area CS2. (Refer to section “3.2.2 External bus operations.”)
Multiplexed bus select bit (bit 5)
Setting this bit to “1” performs the following with the time-sharing method only when area CS2 is
accessed with the external data bus width = 8 bits (Note):
• Address (LA0 to LA7) output from pins D0–D7
• Data (D0 to D7) input/output
Note: This applies when BYTE = Vcc level or when the external data bus width select bit (bit 2
at address 8416) = 1
Area CS2 setting mode select bit (bit 7)
This bit selects the setting mode of the block size.
For details of area CS2, see Figures 3.2.10 and 3.2.12.
CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual
3-18
3.2 Chip select wait controller
(8) CS3 control register H
Figure 3.2.8 shows the structure of the CS3 control register H.
Fig. 3.2.8 Structure of CS3 control register H
0 0 0 : 0 byte (Area CS3 is invalid.)
0 0 1 : 128 Kbytes
0 1 0 : 256 Kbytes
0 1 1 : 512 Kbytes
1 0 0 : 1 Mbytes
1 0 1 : 2 Mbytes
1 1 0 : 4 Mbytes
1 1 1 : 8 Mbytes
b2 b1b0
CS3 control register H (Address 8716)b7 b6 b5 b4 b3 b2 b1 b0
Bit nameBit Function At reset R/W
The combination of this bit and the area CS3 bus
cycle select bit 0 selects the bus cycle.
0 : 1φ + 1φ, 1φ + 2φ, 1φ + 3φ, or 2φ + 2φ
1 : 2φ + 3φ, 2φ + 4φ, 3φ + 3φ, or 3φ + 4φ
0
1
2
3
7 to 4
Area CS3 block size select bits
Area CS3 bus cycle select bit 1
The value is “0” at reading.
0
0
0
0
0
RW
RW
RW
RW
Area CS3 block size select bit (bits 2 to 0)
These bits select the block size of area CS3. Clearing these bits to “0002” invalidates area CS3.
When the block size has been selected, area CS3 becomes valid and setting for each function of
area CS3 becomes valid, regardless of the CS3 output select bit (bit 7 at address 8616). (See Table
3.2.1.)
Area CS3 bus cycle select bit 1 (bit 3)
The combination of this bit and the area CS3 bus cycle select bit 0 (bits 0, 1 at address 8616)
selects the bus cycle at access to area CS3. (Refer to section “3.2.2 External bus operations.”)
For details of area CS3, see Figures 3.2.10.
(9) Area CSi start address register
Figure 3.2.9 shows the structure of area CSi (i = 0 to 3) start address register.
Addresses which can be set into each register differ according to the block size, which is selected by
the area CSi block size select bits. (See Figures 3.2.10 to 3.2.12.)
CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual 3-19
3.2 Chip select wait controller
Bit
0
1
2
3
4
5
6
7
Area CS0 start address register (Address 8A16)
Function
At reset
R/W
Mode 0
A16–A23 of the start address are set.
Mode 1
A8–A15 of the start address are set.
Any value of 1016, 2016, 4016, and 8016 can be set.
(Bit 0 is always “0” at reading.)
0
0
0
0
1
0
0
0
RW
RW
RW
RW
RW
RW
RW
b7 b6 b5 b4 b3 b2 b1 b0
Bit
0
1
2
3
4
5
6
7
Area CS1 start address register (Address 8C16)
Area CS2 start address register (Address 8E16)
Function
At reset
R/W
Mode 0
A16–A23 of the start address are set.
Mode 1
A8–A15 of the start address are set.
(Bit 0 is always “0” at reading.)
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
Bit
0
1
2
3
4
5
6
7
Area CS3 start address register (Address 9016)
Function
At reset
R/W
A16–A23 of the start address are set.
(Bit 0 is always “0” at reading.)
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
Note: Depending on the block size, which has been selected by the area CS0 block size select bits 0 to 2 at address 8116), the start
address which can be set is changed. (See Figures 3.2.10 and 3.2.11.)
Note: Depending on the block size, which has been selected by the area CS1/CS2 block size select bits (bits 0 to 2 at address 8316/
8516), the start address which can be set is changed. (See Figures 3.2.10 and 3.2.12.)
Note: Depending on the block size, which has been selected by the area CS3 block size select bits (bits 0 to 2 at address 8716), the
start address which can be set is changed. (See Figure 3.2.10.)
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
Fig. 3.2.9 Structure of area CSi start address register
CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual
3-20
3.2 Chip select wait controller
Fig. 3.2.10 Area CS0/CS1/CS2 (mode 0) and area CS3
Notes 1: Only A
16
to A
23
of each address can be set to the area CS
0
/CS
1
/CS
2
/CS
3
start
address register. Do not set another address not shown here.
2: When an area which overlaps with the internal area is accessed, the internal area
will be accessed. In this case, pin CS
0
/CS
1
/CS
2
/CS
3
outputs “H” level.
,,,
Block size : 128 Kbytes
Addresses which can be
specified as start address
(Note 1)
(Addresses 0
16
and
FF0000
16
to FFFFFF
16
are not included.)
: Area CS0/CS1/CS2/CS3 cannot be assigned here.
(016)
2000016
4000016
6000016
8000016
A000016
C000016
E000016
10000016
F6000016
F8000016
FA000016
FC000016
FE000016
(FF000016)
(FFFFFF16)
12000016
,,,
Block size : 256 Kbytes
Addresses which can be
specified as start address
(Note 1)
(Addresses 0
16
and
FF0000
16
to FFFFFF
16
are not included.)
(016)
4000016
8000016
C000016
10000016
F8000016
FC000016
(FF000016)
(FFFFFF16)
,,,
Block size : 512 Kbytes
Addresses which can be
specified as start address
(Note 1)
(Addresses 0
16
and
FF0000
16
to FFFFFF
16
are not included.)
(016)
8000016
10000016
F8000016
(FF000016)
(FFFFFF16)
,,,
Block size : 1 Mbytes
Addresses which can be
specified as start address
(Note 1)
(Addresses 0
16
and
FF0000
16
to FFFFFF
16
are not included.)
(016)
10000016
20000016
30000016
40000016
50000016
60000016
70000016
80000016
B0000016
C0000016
D0000016
E0000016
F0000016
(FF000016)
(FFFFFF16)
90000016
A0000016
,,,
Block size : 2 Mbytes
Addresses which can be
specified as start address
(Note 1)
(Addresses 0
16
and
FF0000
16
to FFFFFF
16
are not included.)
(016)
20000016
40000016
60000016
80000016
C0000016
E0000016
(FF000016)
(FFFFFF16)
A0000016
,,,
Block size : 4 Mbytes
Addresses which can be
specified as start address
(Note 1)
(Addresses 0
16
and
FF0000
16
to FFFFFF
16
are not included.)
(016)
40000016
80000016
C0000016
(FF000016)
(FFFFFF16)
,,,
Block size : 8 Mbytes
Addresses which can be
specified as start address
(Note 1)
(Addresses 0
16
and
FF0000
16
to FFFFFF
16
are not included.)
(016)
80000016
(FF000016)
(FFFFFF16)
,
: Reserved area. Do not access this area.
CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual 3-21
3.2 Chip select wait controller
Fig. 3.2.11 Area CS0 (mode 1)
128K
bytes
512K
bytes
2M
bytes
1M
bytes
4M
bytes
8M
bytes
128K
bytes
512K
bytes
2M
bytes
256K
bytes
1M
bytes
4M
bytes
8M
bytes
0
16
1000
16
1FFFF
16
7FFFF
16
FFFFF
16
128K
bytes
512K
bytes
2M
bytes
Start address : 1000
16
Value to be set into area CS
0
start
address register = “10
16
Block size
2000
16
Start address : 2000
16
Value to be set into area CS
0
start
address register = “20
16
4000
16
Start address : 4000
16
Value to be set into area CS
0
start
address register = “40
16
8000
16
128K
bytes
Start address : 8000
16
Value to be set into area CS
0
start
address register = “80
16
Area CS
0
cannot be assigned here.
Note: When an area which overlaps with the internal area is accessed, the internal area will be accessed. In this case,
pin CS
0
outputs “H” level.
3FFFF
16
256K
bytes
1FFFFF
16
1M
bytes
4M
bytes
8M
bytes
512K
bytes
2M
bytes
256K
bytes
1M
bytes
4M
bytes
8M
bytes
3FFFFF
16
7FFFFF
16
Block size Block size Block size
256K
bytes
CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual
3-22
3.2 Chip select wait controller
Fig. 3.2.12 Area CS1/CS2 (mode 1)
016
100016
200016
(FFFF16)
Block size : 4 Kbytes
Addresses which can be specified
as start address (Note 1)
(Address FFFF16 is not included.)
300016
400016
500016
600016
700016
800016
016
200016
(FFFF16)
Block size : 8 Kbytes
Addresses which can be specified
as start address (Note 1)
(Address FFFF16 is not included.)
400016
600016
4 Kbytes
8 Kbytes
F00016
E00016
800016
Notes 1: Only A8 to A15 of each address can be set to
the area CS1/CS2 start address register.
Do not set an address not shown here.
2: When an area which overlaps with the internal
area is accessed, the internal area will be
accessed. In this case, pin CS1/CS2 outputs
“H” level.
CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual 3-23
3.2 Chip select wait controller
3.2.2 External bus operations
By selecting the following functions by software, the external bus operation can be specified for each area
CSi:• Bus cycle
• Burst ROM access
• Recovery cycle
• Area CS2 multiplexed bus access
• RDY control
The relationship between the external bus operations and the above functions are explained below. For
details of RDY control, refer to section “3.3 Ready control.”
CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual
3-24
3.2 Chip select wait controller
(1) Bus cycle
For each area CSi, one of the following bus cycle types can be specified arbitrary. Table 3.2.2 lists
the bus cycle types at normal access.
Table 3.2.2 Bus cycle types at normal access
1 0
0 1
0 0
Bus cycle select bit 1 = 0 (Note)
Bus cycle select
bit 0 (Note)
RD
BLW,BHW
RD
BLW,BHW
φ
1
External address
bus
External data bus
CS
i
RD
BLW,BHW
ALE
Address
1 bus cycle = 2φ
φ
1
External address
bus
External data bus
CS
i
ALE
Address
1 bus cycle = 3φ
φ
1
External address
bus
External data bus
CS
i
ALE
Address
1 bus cycle = 4φ
φ
1
External address
bus
External data bus
CS
i
ALE
Address
1 bus cycle = 4φ
Data
Data
Data
Data
RD
BLW,BHW
1 1
Bus cycle select bit 1 = 1 (Note)
RD
BLW,BHW
1 bus cycle = 5φ
φ
1
External address
bus
External data bus
CS
i
ALE
Address
3φ
RD
BLW,BHW
1 bus cycle = 6φ
φ
1
External address
bus
External data bus
CS
i
ALE
Address
4φ2φ
2φ
RD
BLW,BHW
1 bus cycle = 6φ
φ
1
External address
bus
External data bus
CS
i
ALE
Address
3φ3φ
RD
BLW,BHW
1 bus cycle = 7φ
φ
1
External address
bus
External data bus
CS
i
ALE
Address
4φ
3φ
Data
Data
Data
Data
Bus cycle 1φ + 1φ
Bus cycle 1φ + 2φ
Bus cycle 1φ + 3φ
Bus cycle 2φ + 2φ
Bus cycle 2φ + 3φ
Bus cycle 2φ + 4φ
Bus cycle 3φ + 3φ
Bus cycle 3φ + 4φ
Note: The bus cycles type is determined by the following bits:
• Areas except for area CS
i
: external bus cycle select bit 0 (bits 2 and 3 at address 5E
16
)
external bus cycle select bit 1 (bit 0 at address 5F
16
)
• Area CS
i
: area CS
i
bus cycle select bit 0 (bits 0 and 1 at addresses 80
16
, 82
16
, 84
16
, 86
16
)
area CS
i
bus cycle select bit 1 (bit 3 at addresses 81
16
, 83
16
, 85
16
, 87
16
)
CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual 3-25
3.2 Chip select wait controller
(2) Burst ROM access
When ROM, etc., supporting burst access, is allocated to area CSi, the burst access for the maximum
of 8 bytes becomes available if the burst ROM access is specified (the burst ROM access select bit
= “1”). The burst ROM access is valid only when the external data bus width = 16 bits with instructions
prefetched. In the other cases, normal access is specified regardless of the burst ROM access select
bit.
Figure 3.2.13 shows the operating waveform at burst ROM access.
Also, for the instruction prefetch, refer to section “2.2.1 Instruction prefetch.”
At instruction prefetch with burst ROM access, 8 bytes are fetched from an 8-byte boundary. (See
Figure 3.2.13 (a): quadruple consecutive access.)
At branch, 4 bytes are fetched from a 4-byte boundary regardless of the low-order 2 bits (A1, A0) of
the branch destination address. (See Figure 3.2.13 (b): double consecutive access.) In this case, the
number of fetched bytes depends on the branch destination address. (See Table 2.2.3.)
Also, the address of data (instruction) to be fetched next controls the following operations as below:
• If this address is placed at an 8-byte boundary, data (instruction) will be fetched in a unit of 8 bytes.
(See Figure 3.2.13 (a): quadruple consecutive access.)
• If this address is placed at a 4-byte boundary, after 4-byte data is fetched (See Figure 3.2.13 (b):
double consecutive access.), data will be fetched in a unit of 8 bytes. (See Figure 3.2.13 (a):
quadruple consecutive access.)
Fig. 3.2.13 Operating waveform at burst ROM access
(b)
External address bus
RD
External data bus
Data
(Instruction)
External data bus
Data
(Instruction)
Data
(Instruction)
Data
(Instruction)
Address Address
(a)
External address bus
(A0 to A23)
RD
External data bus
(D0 to D7)
Data
(Instruction)
External data bus
Data
(Instruction)
Data
(Instruction)
Data
(Instruction)
φ
1
Address Address Address Address
Data
(Instruction)
Data
(Instruction)
Data
(Instruction)
Data
(Instruction)
(D8 to D15)
(A0 to A23)
(D0 to D7)
(D8 to D15)
φ
1
Note: The above is applied when 1 bus cycle = 1φ + 1φ. For details of the bus cycle
types, refer to section “(1) Bus cycle.”
CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual
3-26
3.2 Chip select wait controller
Table 3.2.3 lists the waveform examples at burst ROM access for each bus cycle.
Table 3.2.3 Waveform examples at burst ROM access for each bus cycle
1 bus cycle = 9φ
2φ2φ2φ3φ
1 bus cycle = 5φ
0 0
0 1
1 0
1 1
Burst ROM access select bit = 1
Area CS
i
bus cycle
select bit 0
φ
1
External
address bus
External
data bus
CS
i
RD
ALE
Address
Address Address Address
Data Data Data
φ
1
External
address bus
External
data bus
CS
i
RD
ALE
Address
Data Data Data
Address Address Address
φ
1
External
address bus
External
data bus
CS
i
RD
ALE
Address
Data Data Data
Address Address Address
Do not select.
Data
Data
Data
1φ1φ1φ2φ
1 bus cycle = 13φ
3φ3φ3φ4φ
Address Address Address Address
Do not select.
Do not select.
RD
1 bus cycle = 14φ
φ
1
External
address bus
External
data bus
CS
i
ALE
Address
3φ5φ3φ3φ
Address Address Address
Data Data DataData
RD
1 bus cycle = 18φ
φ
1
External
address bus
External
data bus
CS
i
ALE
4φ6φ4φ4φ
Data Data DataData
0 0
0 1
1 0
1 1
0
1
Area CS
i
bus cycle
select bit 1
Area CSi bus cycle select bit 0: Bits 1, 0 at addresses 8016, 8216, 8416, 8616
Area CSi bus cycle select bit 1: Bit 3 at addresses 8116, 8316, 8516, 8716
Burst ROM access select bit: Bit 5 at addresses 8016, 8216, 8416, 8616
CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual 3-27
3.2 Chip select wait controller
(3) Recovery cycle
As the recovery cycle, 1 or 2 cycles of φ1 can be selected by both the recovery cycle insert select bit
and the recovery-cycle-insert number select bit. (See Figures 3.2.2, 3.2.3, and 3.2.5). Insertion of
recovery cycles allows devices with longer output disable time at read to be connected without using
bus buffers.
Since addresses are maintained throughout recovery cycles, devices requiring longer address hold
time can easily be connected; on the other hand, by inserting 2 recovery cycles to extend the data
hold time at write by 1 cycle of φ1, devices requiring longer data hold time can also be connected.
Figures 3.2.14 and 3.2.15 show operating waveforms at recovery cycle insertion.
Fig. 3.2.14 Operating waveforms at recovery cycle insertion (1)
RD
BLW,BHW
Write Data
Access to
area CS
i
φ
1
CS
i
ALE
A B A A + 1
<No recovery cycle inserted>
Access to
internal area 16-bit data is accessed starting
from an odd-numbered address
in area CS
i
.
(a) At read/write of data
If area CS
i
where recovery cycles have been inserted at the preceding bus cycle is accessed, the same recovery cycles will also be inserted here.
A
0
to A
23
Access to
area CS
i
φ
1
CS
i
ALE
A A A + 1
<1 recovery cycle inserted>
Access to
internal area 16-bit data is accessed starting from an
odd-numbered address in area CS
i
.
B
Recovery
cycle Recovery
cycle Recovery
cycle (Next bus
cycle)
A
0
to A
23
Access to
area CS
i
A A A + 1
<2 recovery cycles inserted>
Access to
internal area 16-bit data is accessed starting from an odd-
numbered address in area CS
i
.
B
Recovery
cycle Recovery
cycle Recovery
cycle (Next bus
cycle)
φ
1
ALE
A A + 2 A + 4 A + 6
<No recovery cycle inserted>
RD
(b) At instruction prefetch (Normal access; quadruple consecutive access)
If area CS
i
where recovery cycles have been inserted at the preceding bus cycle is accessed, the same recovery cycles will also be inserted here.
Notes 1: This applies when the external data bus width = 16 bits. When 8 bits, each address is incremented by 1.
2: When the same area CS
i
is consecutively accessed, pin CS
i
outputs “L” level consecutively.
CS
i
(Note 2)
A
0
–A
23
(Note 1) A A + 2 A + 6
<1 recovery cycle inserted>
A + 4
Recovery
cycle (Next bus cycle)
A A + 2 A + 6
<2 recovery cycles inserted>
A + 4
Recovery
cycle (Next bus cycle)
Write Data Data Data Data Data
Data Data Data
DataData
RD
BLW,BHW
Write Data
φ
1
CS
i
ALE
A
0
to A
23
RD
BLW,BHW
φ
1
ALE
RD
CS
i
(Note 2)
A
0
–A
23
(Note 1)
φ
1
ALE
RD
CS
i
(Note 2)
A
0
–A
23
(Note 1)
CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual
3-28
Fig. 3.2.15 Operating waveforms at recovery cycle insertion (2)
3.2 Chip select wait controller
φ
1
CS
i
(Note 2)
RD
ALE
A A + 2
<No recovery cycle inserted>
(C) At instruction prefetch (Normal access; double consecutive access)
If area CS
i
where recovery cycles have been inserted at the preceding bus cycle is accessed, the same recovery cycles will also be inserted here.
Notes 1: This applies when the external data bus width = 16 bits. When 8 bits, each address is incremented by 1.
2: When the same area CS
i
is consecutively accessed, pin CS
i
outputs “L” level consecutively.
A
0
–A
23
(Note 1) A A + 2
<1 recovery cycle inserted>
Recovery
cycle (Next bus cycle)
A A + 2
<2 recovery cycles inserted>
Recovery
cycle (Next bus cycle)
CS
i
φ
1
RD
ALE
A A + 2 A + 4
<No recovery cycle inserted>
(d) At instruction prefetch (Burst ROM access; quadruple consecutive access)
If area CS
i
where recovery cycles have been inserted at the preceding bus cycle is accessed, the same recovery cycles will also be inserted here.
Note: This applies when the external data bus width = 16 bits.
A + 6
A
0
–A
23
φ
1
CS
i
RD
ALE
A A + 2 A + 6
<1 recovery cycle inserted>
A + 4
Recovery
cycle (Next bus cycle)
A
0
–A
23
φ
1
CS
i
RD
ALE
A A + 2 A + 6
<2 recovery cycles inserted>
A + 4
Recovery
cycle (Next bus cycle)
A
0
–A
23
CS
i
φ
1
RD
ALE
A A + 2
<No recovery cycle inserted>
(e) At instruction prefetch (Burst ROM access; double consecutive access)
If area CS
i
where recovery cycles have been inserted at the preceding bus cycle is accessed, the same recovery cycles will also be inserted here.
Note: This applies when the external data bus width = 16 bits.
φ
1
CS
i
RD
ALE
A A + 2
<1 recovery cycle inserted>
Recovery
cycle (Next bus cycle)
A
0
–A
23
A
0
–A
23
φ
1
CS
i
RD
ALE
A A + 2
<2 recovery cycles inserted>
Recovery
cycle (Next bus cycle)
A
0
–A
23
φ
1
CS
i
(Note 2)
RD
ALE
A
0
–A
23
(Note 1)
φ
1
CS
i
(Note 2)
RD
ALE
A
0
–A
23
(Note 1)
CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual 3-29
3.2 Chip select wait controller
(4) Area CS2 multiplexed bus access
Setting the multiplexed bus select bit (bit 5 at address 8516) to “1” performs the following with the time-
sharing method. This is performed only when area CS2 is accessed with the external data bus width
= 8 bits (Note):
• Address (LA0 to LA7) output from pins D0 to D7
• Data (D0 to D7) input/output
Table 3.2.4 lists the multiplexed bus access waveform examples at bus cycle type selection
Note: This applies when BYTE = Vcc level or when the external data bus width select bit (bit 2 at
address 8416) = 1
Table 3.2.4 Multiplexed bus access waveform examples at bus cycle type selection
RD
WDLA
0
to LA
7
2φ
RD
BLW
φ
1
LA
0
/D
0
to LA
7
/D
7
CS
2
ALE
LA
0
/D
0
to LA
7
/D
7
External
address bus Address
0 0
0 1
1 0
1 1
Multiplexed bus select bit = 1
Area CS
2
bus cycle
select bit 0
Do not select.
Do not select.
Do not select.
0 0
0 1
1 0
1 1
0
1
Area CS
2
bus cycle
select bit 1
Do not select.
Do not select.
RD
BLW
1 bus cycle = 6φ
φ
1
CS
2
ALE
3φ3φ
RD
BLW
1 bus cycle = 7φ
φ
1
CS
2
ALE
4φ3φ
External
address bus Address
External
address bus Address
1 bus cycle = 4φ
2φ
LA
0
to LA
7
RD
LA
0
/D
0
to LA
7
/D
7
WDLA
0
to LA
7
LA
0
to LA
7
LA
0
/D
0
to LA
7
/D
7
LA
0
/D
0
to LA
7
/D
7
WDLA
0
to LA
7
LA
0
to LA
7
LA
0
/D
0
to LA
7
/D
7
RD
RD: Read Data, WD: Write Data
Area CS2 bus cycle select bit 0: Bits 1, 0 at address 8416
Area CS2 bus cycle select bit 1: Bit 3 at address 8516
Multiplexed bus select bit: Bit 5 at address 8516
CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual
3-30
3.2.3 Setting method
Figure 3.2.16 shows an initial setting example of registers related to CSWC.
Fig. 3.2.16 Initial setting example of registers related to CSWC
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b7 b0
CS
0
control register L (Address 80
16
)
Area CS
0
bus cycle select bit 0
See Table 3.2.2.
RDY control bit (Note 1)
0 : RDY control is valid.
1 : RDY control is invalid.
Recovery cycle insert select bit
0 : No recovery cycle is inserted.
1 : Recovery cycles are inserted.
CS
0
output select bit
0 : CS
0
output is disabled.
1 : CS
0
output is enabled.
b7 b0
CS
1
control register L (Address 82
16
)
CS
2
control register L (Address 84
16
)
CS
3
control register L (Address 86
16
)
Area CS
j
bus cycle select bit 0 (j = 1 to 3)
See Table 3.2.2.
Notes 1: Valid when the RDY input
select bit (bit 2 at address
5F
16
) = “1.”
2: Normal access is selected
when the external data bus
width = 8 bits, regardless of
this bit’s contents.
3: Fixed to “1” (8-bit width) while
V
CC
-level voltage is applied to
pin BYTE.
Burst ROM access select bit (Note 2)
0 : Normal access
1 : Burst ROM access
RDY control bit (Note 1)
0 : RDY control is valid.
1 : RDY control is invalid.
External data bus width select bit (Note 3)
0 : 16-bit width
1 : 8-bit width
Recovery cycle insert select bit
0 : No recovery cycle is inserted.
1 : Recovery cycles are inserted.
CS
j
output select bit
0 : CS
j
output is disabled.
1 : CS
j
output is enabled.
Burst ROM access select bit (Note 2)
0 : Normal access
1 : Burst ROM access
b7 b0
CS
0
control register H (Address 81
16
)
b2 b1 b0
Setting of block size
b7 b0
CS
1
control register H (Address 83
16
)
Area CS
1
block size select bits
(mode 0)
0 0 1 : 128 Kbytes
0 1 0 : 256 Kbytes
0 1 1 : 512 Kbytes
1 0 0 : 1 Mbytes
1 0 1 : 2 Mbytes
1 1 0 : 4 Mbytes
1 1 1 : 8 Mbytes
b2 b1 b0
(mode 1)
1 0 0 : 4 Mbytes
1 0 1 : 8 Mbytes
b2 b1 b0
b7 b0
CS
3
control register H (Address 87
16
)
Area CS
3
block size select bits
0 0 1 : 128 Kbytes
0 1 0 : 256 Kbytes
0 1 1 : 512 Kbytes
1 0 0 : 1 Mbytes
1 0 1 : 2 Mbytes
1 1 0 : 4 Mbytes
1 1 1 : 8 Mbytes
b2 b1 b0
CSWC operation is started
AAA
AAA
AAA
Area CS
j
setting mode select bit
0 : Mode 0
1 : Mode 1
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
b7 b0
Area CS
0
start address register (Address 8A
16
)
Setting of start address
b7 b0
Area CS
1
start address register (Address 8C
16
)
Area CS
2
start address register (Address 8E
16
)
See Figures 3.2.10 and 3.2.12.
b7 b0
Area CS
3
start address register (Address 90
16
)
See Figure 3.2.10.
See Figures 3.2.10 and 3.2.11.
Area CS
0
block size select bits
0 0 1 : 128 Kbytes
0 1 0 : 256 Kbytes
0 1 1 : 512 Kbytes
1 0 0 : 1 Mbytes
1 0 1 : 2 Mbytes
1 1 0 : 4 Mbytes
1 1 1 : 8 Mbytes
Area CS
0
setting mode select bit
0 : Mode 0
1 : Mode 1
b7 b0
CS
2
control register H (Address 85
16
)
Area CS
2
block size select bits
(mode 0)
0 0 1 : 128 Kbytes
0 1 0 : 256 Kbytes
0 1 1 : 512 Kbytes
1 0 0 : 1 Mbytes
1 0 1 : 2 Mbytes
1 1 0 : 4 Mbytes
1 1 1 : 8 Mbytes
b2 b1 b0
(mode 1)
1 0 0 : 4 Mbytes
1 0 1 : 8 Mbytes
b2 b1 b0
Area CS
2
setting mode select bit
0 : Mode 0
1 : Mode 1
Multiplexed bus select bit
0 : Separate bus
1 : Multiplexed bus
b7 b0
CS
0
control register H (Address 81
16
)
Area CS
0
bus cycle select bit 1
See Table 3.2.2.
b7 b0
CS
1
control register H (Address 83
16
)
Area CS
1
bus cycle select bit 1
See Table 3.2.2.
b7 b0
CS
2
control register H (Address 85
16
)
Area CS
2
bus cycle select bit 1
See Table 3.2.2.
b7 b0
CS
3
control register H (Address 87
16
)
Area CS
3
bus cycle select bit 1
See Table 3.2.2.
0
0
3.2 Chip select wait controller
CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual 3-31
3.2.4. Address output selection
When internal areas are accessed, address outputs will be undefined. Setting the address output select bit
(See Figure 3.2.17.) to “1” allows the address output at access to an internal area to be fixed. It is because
the address output at access to an internal area will maintain the state at the preceding access to an
external area, by this setting.
Figure 3.2.17 shows the structure of the particular function select register 1, and Figure 3.2.18 shows the
relationship between address output select bit and address output waveforms.
0
1
2
3
4
5
6
7
Notes 1: At power-on reset, this bit becomes “0.” At hardware reset or software reset, this bit retains the value just before reset.
2: Even when “1” is written, the bit status will not change.
3: Setting this bit to “1” must be performed just before execution of the WIT instruction. Also, after the wait state is termi-
nated, this bit must be cleared to “0” immediately.
(Note 1)
(Note 1)
0
0
0
0
0
0
0 : External bus
1 : Programmable I/O port
Bit nameBit
Particular function select register 1 (Address 6316)
Function
At reset
R/W
b7 b6 b5 b4 b3 b2 b1 b0
0 : Normal operation.
1 : STP instruction has been executed.
0 : Normal operation.
1 : WIT instruction has been executed.
0 : In wait mode, system clock fsys is active.
1 : In wait mode, system clock fsys is stopped.
0 : Address output changes at access to the inter-
nal area and external area.
1 : Address output changes only at access to the
external area.
0 : External signal input to the TB2IN pin is counted.
1 : fX32 is counted.
RW
(Note 2)
RW
(Note 2)
RW
RW
RW
RW
Fig. 3.2.17 Structure of particular function select register 1
3.2 Chip select wait controller
STP-instruction-execution status
bit
WIT-instruction-execution status
bit
Standby state select bit
System clock stop select bit at
WIT (Note 3)
Address output select bit
The value is “0” at reading.
Timer B2 clock source select bit
(Valid in event counter mode)
The value is “0” at reading.
CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual
3-32
Fig. 3.2.18 Relationship between address output select bit and address output waveforms
Access to
external area
φ1
RD
BLW,BHW
A0 to A23
A0 to A23
Access to
external area
Address output select bit = 0
Address output select bit = 1
Access to
internal area
Normal access
Address Address
Unde-
fined Unde-
fined
Address Address
Access to external area
φ1
RD
A0 to A23
A0 to A23
Access to external area
Address output select bit = 0
Address output select bit = 1
Access to
internal area
Burst ROM access
Address Unde-
fined
Address Address Address Unde-
fined Address
Address Address Address Address Address
3.2 Chip select wait controller
CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual 3-33
[Precautions for CSWC]
1. When an overlapping area of area CSi (i = 0 to 3) and the internal area is accessed, the internal area
will be accessed. In this case, signal CSi is not output (CSi = “H” level output). Also, the data bus width,
bus cycle, etc., are the same as those at access to internal areas. (See Table 2.2.4.)
2. Be sure that area CSi does not overlap each other.
[Precautions for CSWC]
CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual
3-34
3.3 Ready function
3.3 Ready function
Ready function facilitates access to external devices that require long access time.
The microcomputer enters Ready state by input of “L” level to pin RDY and retains this state while the level
of pin RDY = “L.” Table 3.3.1 lists the microcomputer’s state in Ready state.
To use Ready function, set the following bits as below:
• Area CSi (i = 0 to 3): RDY input select bit (bit 2 at address 5F16) = 1,
RDY control bit (bit 3 at addresses 8016, 8216, 8416, 8616) = 0
• External areas except for area CSi: RDY input select bit (bit 2 at address 5F16) = 1
Item State
Oscillation, fsys
CPU, BIU
Pins A0 to A 23, D0 to D7, D8 to D15, RD, BLW, BHW, ALE, HLDA,
CS0 to CS3
Pin φ1
Port pins P0, P2, P33, P4 to P8, P11 (Note 2)
Watchdog timer
Operating.
Operating (Note 1).
Retain the state when Ready request was
accepted.
Outputs clock φ1.
Operating.
Operating.
Table 3.3.1 Microcomputer’s state in Ready state
Notes 1: When access to the external areas (including the instruction prefetch) becomes necessary, both of CPU and
BIU stop their operations. Until the access to the internal area stops, both of CPU and BIU continue to
operate.
2: This applies when these pins serve as programmable I/O port pins or I/O pins of internal peripheral devices
not shown in the above table.
CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual 3-35
3.3 Ready function
Fig. 3.3.1 Timing of acceptance of Ready request and termination of Ready state
φ1
RD
BLW
BHW
RDY
tsu(RDY-φ1)
(Note 1)
CSi
Notes 1: Be sure to input signal RDY which satisfies these timing conditions.
2: At the burst ROM access, until the quadruple/double consecutive access is completed, signal
RD is not risen to “H.”
3: Broken lines for CSi, RD, BLW, and BHW apply when the input level at pin RDY = “H” (no Ready
request).
1 bus cycle
th(φ1-RDY)
(Note 1)
: Extended by Ready function
This applies when 1 bus cycle = 1φ + 3φ.
(Note 2)
tsu(RDY-φ1)
(Note 1)
3.3.1 Operation description
The input level of pin RDY is judged at the last falling edge of clock φ1 for each bus cycle. (While buses
are not in use, the input level at pin RDY is not judged.)
When “L” level is detected at this point, the microcomputer enters Ready state. (This is called “Acceptance
of Ready request.”)
In Ready state, the input level of pin RDY is judged at every falling edge of clock φ1. When “H” level is
detected at this time, the microcomputer terminates Ready state at the next rising edge of clock φ1.
Figure 3.3.1 shows the timing of acceptance of Ready request and termination of Ready state. Refer also
to “CHAPTER 19. APPLICATIONS” for usage of Ready function.
CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual
3-36
3.4 Hold function
Hold function opens the external buses to external devices.
In the memory expansion or microprocessor mode, the microcomputer enters Hold state when “L” level is
input to pin HOLD. While the level at pin HOLD = “L,” the microcomputer retains Hold state. Table 3.4.1 lists
the microcomputer’s state in Hold state.
To use Hold function, be sure to set the HOLD input, HLDA output select bit (bit 5 at address 5F16) to “1.”
Item State
Oscillation, fsys
CPU, BIU
Pins A0 to A 23, D0 to D7, D8 to D15, RD, BLW, BHW, ALE,
CS0 to CS3
Pin HLDA
Pin φ1
Port pins P0, P2, P30, P33, P40 to P4 2, P5 to P8, P11 (Note 2)
Watchdog timer
Operating.
Operating (Note 1).
Floating.
Outputs “L” level.
Outputs clock φ1.
Operating.
Operating (Note 1).
Table 3.4.1 Microcomputer’s state in Hold state
Notes 1: When access to the external areas (including the instruction prefetch) becomes necessary, all of CPU, BIU,
and the watchdog timer stop their operations. Until the access to the internal area stops, all of CPU, BIU, and
the watchdog timer continue to operate.
2: This applies when these pins serve as programmable I/O port pins or I/O pins of internal peripheral devices
not shown in the above table.
3.4 Hold function
CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual 3-37
3.4.1 Operation description
The judgement timing of the input level at pin HOLD depends on the usage state of buses. While buses
are not in use, the input level at pin HOLD is judged at every rising edge of clock φ1. While buses are in
use, the input level is judged at the rising edge of clock φ1, which precedes the end of the bus cycle by
1 cycle.
When “L” level (Hold request) is detected at the judgement of the input level, the microcomputer will enter
Hold state after completion of the present bus cycle. (This is called “Acceptance of Hold request.”)
When Hold request is accepted, pin HLDA’s level changes from “H” to “L” at the next rising edge of clock
φ1.
Simultaneously, pins RD, BLW, BHW, ALE, CSi (i = 0 to 3), and external buses enter the floating state.
In Hold state, the input level at pin HOLD is judged every rising edge of clock φ1. When “H” level is detected
at this time, pin HLDA’s level will change from “L” to “H” at the next rising edge of clock φ1.
When pin HLDA’s level becomes “H,” the microcomputer terminates Hold state after 1 cycle of clock φ1 is
elapsed.
Figure 3.4.1 shows the timing of acceptance of Hold request and termination of Hold state.
Fig. 3.4.1 Timing of acceptance of Hold request and termination of Hold state
φ
1
RD
BLW
BHW
HOLD
CS
i
Bus cycle
(Bus in use) Hold state Bus cycle
Undefi-
ned
Undefined
A
0
to A
23
D
0
to D
15
HLDA
Input level at pin HOLD is judged.
Hold request is sampled, and priority is determined (Acceptance of Hold request.)
Input level at pin HOLD is judged. ( Request to terminate Hold state is generated.)
Address
Data
Address
Data
ALE
3.4 Hold function
CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual
3-38
3.4 Hold function
MEMORANDUM
CHAPTER 4CHAPTER 4
RESET
4.1 Reset operation
4.2 Pin state
4.3 State of internal area
4.4 Internal processing sequence after
reset
RESET
7902 Group User’s Manual
4-2
There are 3 ways to reset the microcomputer:
Hardware reset : Apply “L” level of voltage to pin RESET while the power source voltage (Vcc) meets
the recommended operating conditions.
Software reset : Write “1” to the software reset bit (bit 6 of address 5E16) while the power source
voltage (Vcc) meets the recommended operating conditions.
Power-on reset : Apply “L” level of voltage to pin RESET until the voltage level at pin Vcc meets the
recommended operating conditions after powered on.
4.1 Reset operation
Operations of hardware, software, and power-on reset are described below.
4.1.1 Hardware reset
Figure 4.1.1 shows an example of hardware reset timing.
Fig. 4.1.1 Example of hardware reset timing
The following explains how the microcomputer operates in the above periods, to .
After applying “L” level of voltage to pin RESET, the microcomputer initializes pins within a period of several
ten cycles of fsys. (Refer to section “4.2 Pin state.”)
The microcomputer initializes the central processing unit (CPU) and SFR area in the following periods.
(Refer to section “4.3 State of internal area.”)
• While pin RESET is at “L” level.
• A period of 8 to 9 cycles of fsys after pin RESET goes from “L” to “H.”
After , the microcomputer performs Internal processing sequence after reset.” (Refer to section “4.4
Internal processing sequence after reset.”)
The microcomputer executes a program beginning with the address which has been set into the reset
vector addresses (addresses FFFE16 and FFFF16).
RESET
2 µs or more 8 to 9 cycles of fsys
Internal processing
sequence after
reset Program is executed.
(Note)
Note: The above is applied when the oscillator is stably oscillating or when an
external clock is stably input from pin XIN. When the oscillator is not stably
oscillating (including the case at the stop mode’s termination; refer to section
“16.3 Stop mode.”), apply “L” level of voltage for 2 µs or more after the
oscillation becomes stable.
4.1 Reset operation
RESET
7902 Group User’s Manual 4-3
Bit nameBit
Processor mode register 0 (Address 5E16)
Function
At reset
R/W
Processor mode bits
External bus cycle select bit 0
(Note 2)
Interrupt priority detection time
select bits
Software reset bit
Clock φ1 output select bit
b7 b6 b5 b4 b3 b2 b1 b0
Notes 1: When the Vss-level voltage is applied to pin MD0, this bit is “0”; when the Vcc-level voltage is applied to pin MD0, this bit
is “1.” (Fixed to “1.”)
2: These bits are valid for the external area except for area CSi. Regardless of these bits’ contents, the bus cycle of area CSi
is decided by the corresponding area CSi bus cycle select bits 0, 1 (bits 0, 1 at addresses 8016, 8216, 8416, 8616, and bit 3
at addresses 8116, 8316, 8516, 8716).
3: When the Vss-level voltage is applied to pin MD0, this bit is “0”; when the Vcc-level voltage is applied to pin MD0, this bit
is “1.”
0 0 : Single-chip mode
0 1 : Memory expansion mode
1 0 : Microprocessor mode
1 1 : Do not select.
b1 b0
0 0 : 7 cycles of fsys
0 1 : 4 cycles of fsys
1 0 : 2 cycles of fsys
1 1 : Do not select.
b5 b4
The microcomputer is reset by writing “1” to this
bit. The value is “0” at reading.
0 : φ1 output is disabled. (P41 functions as a
programmable I/O port pin.)
1 : φ1 output is enabled. (P41 functions as a clock φ1
output pin.)
0
1
2
3
4
5
6
7
0
(Note 1)
0
1
0
0
0
(Note 3)
RW
RW
RW
RW
RW
RW
WO
RW
0 0 :
1φ + 1φ
0 1 :
1φ + 2φ
1 0 :
1φ + 3φ
1 1 :
2φ + 2φ
b2b3 0 0 :
2φ + 3φ
0 1 :
2φ + 4φ
1 0 :
3φ + 3φ
1 1 :
3φ + 4φ
b2b3
(External bus cycle select
bit 1 = 0) (External bus cycle select
bit 1 = 1)
Fig. 4.1.2 Structure of processor mode register 0
4.1.2 Software reset
The microcomputer initializes pins, CPU, and SFR area just as in the case of hardware reset (Refer to
sections “4.2 Pin state” and “4.3 State of internal area”) by writing “1” to the software reset bit. (See
Figure 4.1.2.)
After initialization completed, the microcomputer performs “Internal processing sequence after reset.” (Refer
to section “4.4 Internal processing sequence after reset.”) After that, it executes a program beginning
with the address which has been set into the reset vector addresses (FFFE16 and FFFF16).
4.1 Reset operation
RESET
7902 Group User’s Manual
4-4
4.1.3 Power-on reset
The following describes the operation of the microcomputer at power-on reset.
After powered on, within the several ten cycles of f sys after the voltage level at pin Vcc meets the recommended
operating conditions with the voltage level at pin RESET = “L,” the microcomputer initializes pins: refer to
section “4.2 Pin state.”
After the voltage level at pin RESET goes from “L” to “H,” the microcomputer initializes the CPU and
SFR area within a period of 8 to 9 cycles of fsys. (Contents of the internal RAM area become undefined:
refer to section “4.3 State of internal area.”)
After , the microcomputer performs “Internal processing sequence after reset.”: refer to section “4.4
Internal processing sequence after reset.”
The microcomputer executes a program beginning with the address which has been set into the reset
vector addresses (addresses FFFE16 and FFFF16).
Fig. 4.1.4 Example of power-on reset circuit
4.1 Reset operation
1
V
CC
IN OUT
GND
Delay
capacity
RESET
V
CC
V
SS
47
SW
C
d
GND
3
25
5 V
M51957AL M37902
27 k
10 k4
The delay time is about 11 ms when C
d
= 0.033 µF.
t
d
0.34 C
d
[µs], C
d
: [pF]
Figure 4.1.3 shows the power-on reset conditions.
Figure 4.1.4 shows an example of a power-on reset
circuit.
After the voltage level at pin Vcc meets the
recommended operating conditions and the oscillator’s
operation is stabilized (see Figure 4.1.3.), apply “L”
level of voltage to pin RESET for 2 µs or more.
When an oscillator is used, the time required for
stabilizing oscillation depends on the oscillator. For
details, contact the oscillator manufacturer.
V
CC
RESET
Powered on there
VCC level
0.2 VCC level
Oscillation stabilized
2 µs
X
IN
0 V
0 V
0 V
Fig. 4.1.3 Power-on reset conditions
RESET
7902 Group User’s Manual 4-5
Vss or Vcc
Vcc
Vss
Vcc
P0–P3, P40–P43, P5–P8, P10, P11
P44–P47, NMI
A0–A23
RDY, HOLD, D0–D7,
P20/D8–P27/D15, P5–P8
P45–P47, NMI
RD, BLW, BHW, HLDA, CS0
ALE
φ1
P0–P3, P40–P43, P5–P8, P10, P11
P44–P47, NMI
P0–P3, P40, P41, P43–P47, P5–P8,
P10, P11, NMI
P42
Floating.
Pulled up.
Outputs “H” or “L” level.
Floating.
Pulled up.
Outputs “H” level (Note 1) .
Outputs “L” level.
Outputs φ1.
Floating.
Pulled up.
Floating (Note 3).
Outputs “H” level.
4.2 Pin state
4.2 Pin state
Table 4.2.1 lists the microcomputer’s pin state while the voltage level at pin RESET is “L.”
Table 4.2.1 Pin state while voltage level at pin RESET is “L”
Notes 1: When BYTE = Vcc, pin BHW enters the floating state.
2: Refer to “CHAPTER 20. FLASH MEMORY VERSION.”
3: When applying the voltage of “H” level to pin VCONT and “L” level to pins P54 and P55, P1 and P2 output “H” or “L” level.
Vss
Vcc
MASK ROM version,
Flash memory version
External ROM version
Flash memory version
(Note 2)
Pin statePin (Bus, Port) name
Pin MD1’s level Pin MD0’s level
RESET
7902 Group User’s Manual
4-6
4.3 State of internal area
Figure 4.3.1 shows the state of CPU registers immediately after reset. Figures 4.3.2 to 4.3.7 show the state
of the SFR and internal RAM areas immediately after reset.
4.3 State of internal area
Fig. 4.3.1 State of CPU registers immediately after reset
0
1
?
: "0" immediately after reset.
: "1" immediately after reset.
: Undefined immediately after reset.
Data bank register (DT) 00
16
b7 b0
Program bank register (PG) 00
16
b7 b0
Program counter (PC) Contents at address FFFE
16
Contents at address FFFF
16
b7 b0b15 b8
Direct page register 0 (DPR0) 00
16
b7 b0
00
16
b15 b8
Processor status register (PS) 0000001
b7 b0
b15 b8
NVmxDIZCIPL
????
Stack pointer (S) FF
16
b7 b0
0F
16
b15 b8
Index register Y (Y) ?
b7 b0
?
b15 b8
Index register X (X) ?
b7 b0
?
b15 b8
Accumulator B (B) ?
b7 b0
?
b15 b8
Accumulator A (A) ?
b7 b0
?
b15 b8
Register name State immediately after reset
: "0" immediately after reset.
Fix this bit to "0."
Direct page register i (DPRi) ?
b7 b0
?
b15 b8
(i = 1 to 3)
0
00 0 00
RESET
7902 Group User’s Manual 4-7
4.3 State of internal area
Fig. 4.3.2 State of SFR and internal RAM areas immediately after reset (1)
0 1 1
0 00
?
0
?
: It is possible to read the bit state at reading. The written value becomes valid.
: It is possible to read the bit state at reading. The written value becomes invalid.
: The written value becomes valid. It is impossible to read the bit state.
: Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid.
SFR area (Addresses 0
16
to FF
16
)
RW
RO
WO
Access characteristics
0
1
?
: “0” immediately after reset.
: “1” immediately after reset.
: Undefined immediately after
reset.
: Always “0” at reading.
: Always “1” at reading.
: Always undefined at reading.
: “0” immediately after reset. Fix this bit to “0.”
0
?
1
State immediately after reset
10
16
11
16
12
16
13
16
14
16
15
16
16
16
17
16
18
16
19
16
1A
16
1C
16
1B
16
1D
16
1E
16
1F
16
0
16
1
16
2
16
3
16
4
16
5
16
6
16
7
16
8
16
9
16
B
16
C
16
D
16
E
16
F
16
A
16
Address
Port P8 direction register
Port P4 register
Port P5 register
Port P4 direction register
Port P5 direction register
Port P6 register
Port P7 register
Port P6 direction register
Port P7 direction register
Port P8 register
A-D control register 0
A-D control register 1
Register name
Port P10 register
Port P10 direction register
Port P0 register
Port P1 register
Port P0 direction register
Port P1 direction register
Port P2 register
Port P3 register
Port P2 direction register
Port P3 direction register
Port P11 register
Port P11 direction register
00
16
?
Access characteristics
State immediately after reset
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
?
?
00
16
00
16
?
?
00
16
00
16
00
16
?
?
?
00
16
?
?
?
?
?
?
b7 b0 b7 b0
?
RW
RW
RW
RW
00
16
00
16
??
00
16
?
RW
RW
RW
RW
RW
RW
RW
RW RW
RW 0000
00000000
??00?000
(Note 1)
(Note 1)
Notes 1: Do not read and write.
0
0
RESET
7902 Group User’s Manual
4-8
000000
000000?
?
?
000000
?
000000
RORO
RORO
RORO
RORO
UART0 transmit/receive control register 0
UART0 transmit/receive mode register
UART0 baud rate register
UART0 transmit buffer register
UART1 receive buffer register
UART0 transmit/receive control register 1
UART0 receive buffer register
UART1 transmit/receive mode register
UART1 baud rate register
UART1 transmit buffer register
UART1 transmit/receive control register 0
UART1 transmit/receive control register 1
30
16
31
16
32
16
33
16
34
16
35
16
36
16
37
16
38
16
39
16
3A
16
3B
16
3C
16
3D
16
3E
16
28
16
29
16
2B
16
2C
16
2D
16
2E
16
2F
16
2A
16
20
16
21
16
22
16
23
16
24
16
25
16
26
16
27
16
3F
16
b7 b0
Register name
Address Access characteristics State immediately after reset
b7 b0
A-D register 5
A-D register 1
A-D register 3
A-D register 2
A-D register 4
A-D register 0
A-D register 6
A-D register 7
RW
RW
?
000000
?
000000
?
000000
RW
WO
WO
RO RO
WO
RWRO
RO RORW RW
RO RO
RW
WO
WO WO
RWRO
RO RORW RW
?
?
?
?
?
?
?
01000
?
?
?
00
16
?
?
?
?
0000000?
?
?
00
16
00000010
0000000?
1000
00000010
RO
RO
RO
RO
RO
RO
RO
RO
000
0000
?
RO
RO
RORO
RORO
RORO
000000
Fig. 4.3.3 State of SFR and internal RAM areas immediately after reset (2)
4.3 State of internal area
RESET
7902 Group User’s Manual 4-9
(Note 5)
0
0
0
0
00
1
00?? 000
00??000
Timer B2 register
40
16
41
16
42
16
43
16
44
16
45
16
46
16
47
16
48
16
49
16
50
16
51
16
52
16
53
16
54
16
55
16
56
16
57
16
58
16
59
16
5A
16
5B
16
5C
16
5D
16
5E
16
5F
16
4B
16
4C
16
4D
16
4E
16
4F
16
4A
16 Timer A2 register
Timer A3 register
Timer A4 register
Timer B0 register
Timer B1 register
Processor mode register 0
One-shot start register
Timer A0 register
Up-down register
Timer A1 register
Count start register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
WO
RW
b7 b0
RW
RW
RW
RW
RW
RW
RW
RWWO
??
?
?
?
?
?
?
?
?
?
?
?
?
00
16
00
16
00
16
?
00
16
b7 b0
?
?
0
WO RW
RW
RW
Timer A0 mode register
Timer A4 mode register
Processor mode register 1
(Note 7)
RW
RW
RW
(Note 4)
0000000
?
?
00?? 0000
(Note 5)
000
RW
00 0
(Note 4)
(Note 4)
0
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 3)
(Note 3)
0
0
0
000
000 0
00
16
00
16
(Note 5)
RWRW
Timer A clock division select register
(Note 6) (Note 6)
RW
RWRW 0
RW RW
RW
Register name
Address Access characteristics State immediately after reset
Notes 2: The access characteristics at addresses 46
16
to 4F
16
vary according to the timer A’s operating mode. (Refer to
“CHAPTER 9. TIMER A.”)
3: The access characteristics at addresses 50
16
to 55
16
vary according to the timer B’s operating mode. (Refer to
“CHAPTER 10. TIMER B.”)
4: The access characteristics for bit 5 at addresses 5B
16
and 5D
16
vary according to the timer B’s operating mode.
(Refer to “CHAPTER 10. TIMER B.”)
5: This bit is “0” when Vss-level voltage is applied to pin MD0; this bit is “1” when Vcc-level voltage is applied.
6: After reset, this bit can be set to “1” only once. Once this bit goes from “1” to “0,” it cannot be set to “1” again.
(This bit is fixed to “0.”)
7: In the external ROM version, for bit 7, nothing is assigned. This bit is “0” at reading.
0
Fig. 4.3.4 State of SFR and internal RAM areas immediately after reset (3)
4.3 State of internal area
RESET
7902 Group User’s Manual
4-10
Fig. 4.3.5 State of SFR and internal RAM areas immediately after reset (4)
00
?
?
?
?
0
RW
1
0(Note 12)
UART1 receive interrupt control register
60
16
61
16
62
16
63
16
64
16
65
16
66
16
67
16
68
16
69
16
70
16
71
16
72
16
73
16
74
16
75
16
76
16
77
16
78
16
79
16
7A
16
7B
16
7C
16
7D
16
7E
16
7F
16
6B
16
6C
16
6D
16
6E
16
6F
16
6A
16
A-D conversion interrupt control register
UART0 transmit interrupt control register
UART1 transmit interrupt control register
INT
2
interrupt control register
Watchdog timer frequency select register
Watchdog timer register
Timer A0 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT
0
interrupt control register
b7 b0 b7
UART0 receive interrupt control register
Timer A1 interrupt control register
Timer B0 interrupt control register
INT
1
interrupt control register
Debug control register 0
INT
4
interrupt control register
RW
RW
(Note 8)
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RWRW RW RW
b0
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
? (Note 9) 000
0000
0
0
0000
?000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
00
00
00
RW
RW
RW
RW
INT
3
interrupt control register
Debug control register 1
RW RWRO ?
?
(Note 12)
0000
0
?
Particular function select register 0
Particular function select register 1
000
(Note 12)
(Note 11)
RORO RW
RW
RWRWRW
RW
RW (Note 14)
RW (Note 14)
RW (Note 14)
RW (Note 14)
RW (Note 14)
RW (Note 14)
Address comparison register 0
Address comparison register 1
0
RW (Note 10)
0
(Note 13)
Particular function select register 2
Register name
Address Access characteristics State immediately after reset
Notes 8 : By writing dummy data to address 60
16
, a value of “FFF
16
” is set to the watchdog timer.
The dummy data is not retained anywhere.
9 : A value of “FFF
16
” is set to the watchdog timer. (Refer to “CHAPTER 15. WATCHDOG TIMER.”)
10 : After writing “55
16
” to address 62
16
, each bit must be set.
11 : It is possible to read the bit state at reading. By writing “0” to this bit, this bit becomes “0.”
But when writing “1” to this bit, this bit will not change.
12 : This bit becomes “0” at power-on reset. This bit retains the state immediately before reset in the case of
hardware reset and software reset.
13 : Do not write.
14 : When these registers are accessed, set the address comparison register access enable bit (bit 2 at address
67
16
) to “1.” (Refer to “CHAPTER 18. DEBUG FUNCTION.”)
0
000000
0
00 0
4.3 State of internal area
RESET
7902 Group User’s Manual 4-11
Fig. 4.3.6 State of SFR and internal RAM areas immediately after reset (5)
RO 0
1
1
1
RW
RW
RW
RW
0
0
0
0
?
?
1
000 000
00
000
10
00
00000
00
00 0
10
00
0000
00
00
1000
01
00
(Note 15)
1010
80
16
81
16
82
16
83
16
84
16
85
16
86
16
87
16
88
16
89
16
90
16
91
16
92
16
93
16
94
16
95
16
96
16
97
16
98
16
99
16
9A
16
9B
16
9C
16
9D
16
9E
16
9F
16
8B
16
8C
16
8D
16
8E
16
8F
16
8A
16
CS0 control register H
CS0 control register L b7 b0 b7
RW
RW RW
b0
RW
RW
RW
RW
RW
RW
RO
RW
?
?
CS1 control register H
CS1 control register L
CS2 control register H
CS2 control register L
CS3 control register H
CS3 control register L
Area CS0 start address register
Area CS1 start address register
Area CS2 start address register
Area CS3 start address register
RWRWRORWRW
RW
RW
RW
RW RW
RW
RW
RW
0000 0
10
000000
00
0000 000
?
0000 000
?
000
00
000
0000
00
0000
00
?
?
??
?
?
?
?
(Note 16)
RW
RW
(Note 17)
(Note 17)
Flash memory control register (Note 18)
D-A register 2
D-A register 1
D-A register 0
D-A control register
External interrupt input read-out register
External interrupt input control register
Port function control register
0
0001
RWRW RW
RW
Register name
Address Access characteristics State immediately after reset
Notes 15 : This bit is “0” when Vss-level voltage is applied to pin MD0; this bit is “1” when Vcc-level voltage is applied.
16 : This bit is “0” when Vss-level voltage is applied to pin BYTE; this bit is “1” when Vcc-level voltage is applied.
17 : Do not write.
18 : This register is allocated only to the flash memory version. (Refer to “CHAPTER 20. FLASH MEMORY
VERSION.”) Do not write to this register in the mask ROM and external ROM versions.
0 0
00
16
00
16
00
16
00
00
00
0
4.3 State of internal area
RESET
7902 Group User’s Manual
4-12
Fig. 4.3.7 State of SFR and internal RAM areas immediately after reset (6)
?
?
00000 000
00
?
?
00
A0
16
A1
16
A2
16
A3
16
A4
16
A5
16
A6
16
A7
16
A8
16
A9
16
B0
16
B1
16
B2
16
B3
16
B4
16
B5
16
B6
16
B7
16
B8
16
B9
16
BA
16
BB
16
BC
16
BD
16
BE
16
BF
16
AB
16
AC
16
AD
16
AE
16
AF
16
AA
16
Real-time output control register b7 b0 b7
WO
b0
Pulse output data register 0
Pulse output data register 1
Serial I/O pin control register
Clock control register
RW
WO
RWRWRWRW
?
?
?
?
?
?
?
?
0
?
?
?
?
0001
11
?
?
?
?
?
?
?
?
?
?
?
?
?
Notes 19 : Do not write to this register.
20 : After reset, these bits are allowed to be changed only once.
00000
(Note 19)
(Note 19)
(Note 19)
(Note 19)
(Note 19)
Register name
Address Access characteristics State immediately after reset
Internal RAM area
At hardware reset ................................................................................. Retains the state immediately before reset (Note 21).
At software reset.................................................................................................... Retains the state immediately before reset.
At termination of the stop or wait mode
(when hardware reset is used for the termination.)....................................Retains the state immediately before the STP or
WIT instruction is executed.
At power-on reset..................................................................................................................................................... Undefined.
Notes 21 : When a reset operation starts while writing to the internal RAM area is in process, the microcomputer will be
reset before the completion of writing. Accordingly, the contents of the area where the writing was in process
will become undefined.
RWRW RWRW
(Note 20)
RWRW
4.3 State of internal area
RESET
7902 Group User’s Manual 4-13
Note : When the stack area is in the internal area, the above signals are not output to the external.
When the stack area is in the external area, A
0
to A
23
, RD, BLW, and BHW are output to the
external.
The above waveforms are applied when the external data bus has a width of 16 bits. When the
external data bus has a width of 8 bits, D
8
to D
15
and BHW enter the floating state.
0000
16
00
16
FFFE
16
AD
15
to AD
0
IPL, Vector addresses of reset
00
16
00
16
Undefined Next op-code
f
sys
: System clock (See Figure 5.2.1.)
AD
0
to AD
15
: Internal address bus
IPL: Processor interrupt priority level
This is an internal signal and is not output to the external.
AD
0
to AD
15
: Internal address bus
IPL: Processor interrupt priority level
This is an internal signal and is not output to the external.
f
sys
A
H(CPU)
A
L
A
M(CPU)
DATA
(CPU)
(2) At MD0 = V
CC
(microprocessor mode)
(1) At MD0 = V
SS
(single-chip mode)
next op-code
0000
16
00
16
FFFE
16
AD
15
to AD
0
IPL, Vector addresses of reset
00
16
00
16
Undefined
Floating
H
φ
1
A
23
to A
16
A
15
to A
0
DATA
(CPU)
RD
ALE
BLW
BHW
D
0
to D
15
CS
0
AD
15
to AD
0
AD
15
to AD
0
4.4 Internal processing sequence after reset
Fig. 4.4.1 Internal processing sequence after reset
4.4 Internal processing sequence after reset
Figure 4.4.1 shows the internal processing sequence after reset.
RESET
7902 Group User’s Manual
4-14
4.4 Internal processing sequence after reset
MEMORANDUM
CHAPTER 5CHAPTER 5
CLOCK
GENERATING
CIRCUIT
5.1 Oscillation circuit examples
5.2 Clocks
[Precautions for clcok generating circuit]
CLOCK GENERATING CIRCUIT
7902 Group User’s Manual
5-2
5.1 Oscillation circuit examples
5.1 Oscillation circuit examples
To the oscillation circuit, a ceramic resonator or a quartz-crystal oscillator can be connected, or the clock
which is externally generated can be input. Oscillation circuit examples are shown below.
5.1.1 Connection example with resonator/oscillator
Figure 5.1.1 shows an example where pins XIN and XOUT connect across a ceramic resonator/quartz-crystal
oscillator.
The circuit constants such as Rf, Rd, CIN, and COUT (shown in “Figure 5.1.1”) depend on the resonator/
oscillator. These values shall be set to the values recommended by the resonator/oscillator manufacturer.
Fig. 5.1.1
Connection example of resonator/oscillator
Fig. 5.1.2 Externally generated clock input example
M37902
XIN XOUT
Rf
CIN COUT
Rd
M37902
XIN XOUT
Vcc
Vss
Externally generated clock
Open
5.1.2 Externally generated clock input example
Figure 5.1.2 shows an input example of a clock which is externally generated. An external clock must be
input from pin XIN, and pin XOUT must be left open.
When an externally generated clock is input, the power source current consumption can be saved by the
stop of internal circuit’s operation between pins XIN and XOUT. (Refer to “CHAPTER 17. POWER SAVING
FUNCTION.”)
CLOCK GENERATING CIRCUIT
7902 Group User’s Manual 5-3
5.1 Oscillation circuit examples
5.1.3 Connection example of filter circuit
In the usage of the PLL frequency multiplier, be sure to connect a filter circuit with pin VCONT.
Figure 5.1.3 shows a connection example of the filter circuit.
Fig. 5.1.3
Connection example of filter circuit
M37902
VCONT
1 k
0.1 µF
220pF
Note: Connect the elements of the filter circuit as
close as possible and enclose the whole
circuit with a Vss pattern.
CLOCK GENERATING CIRCUIT
7902 Group User’s Manual
5-4
5.2 Clocks
5.2 Clocks
Figure 5.2.1 shows the clock generating circuit block diagram.
Fig. 5.2.1 Clock generating circuit block diagram
f
2
f
64
f
512
f
4096
Q
R
S
STP
instruction
φ
BIU
(Clock for BIU)
φ
CPU
(Clock for CPU)
CPU wait request
1/4
1/8 1/8
Reset
• Watchdog timer frequency select bit : bit 0 at address 61
16
Watchdog timer clock source select bits at STP termination :
bits 6, 7 at address 61
16
• External clock input select bit : bit 1 at address 62
16
• System clock stop select bit at WIT : bit 3 at address 63
16
• PLL circuit operation enable bit : bit 1 at address BC
16
• PLL multiplication ratio select bits : bits 2, 3 at address BC
16
• System clock select bit : bit 5 at address BC
16
• Peripheral device’s clock select bit 0, 1 : bits 6, 7 at address BC
16
1/8
1/2
1/16
Watchdog
timer
Wf
32
Wf
512
f
16
f
1
Peripheral device’s clocks
0
1
Watchdog timer
frequency select bit
X
IN
X
OUT
System clock stop select bi at WIT
1/16
Access to
external area
HLDA
0
1
Watchdog timer clock source select
bits at STP termination
φ
1
Wait mode
1
0
1
0
1/2
1
0
1
Wait mode
System clock
frequency select bit
PLL frequency
multiplier
f
PLL
V
CONT
Wait mode
External clock
input select bit
Q
R
S
STP
instruction
Interrupt
request
Q
R
S
WIT
instruction
Interrupt
request Wait mode
PLL circuit operation enable bit
PLL multiplication ratio select bits
fX
IN
f/n
0
fX
16
fX
32
fX
64
fX
128
fX
16
fX
32
fX
64
fX
128
Peripheral
device’s clock
select bit 0
Peripheral
device’s clock
select bit 1
BIU : Bus interface Unit
CPU : Central Processing Unit
: Signal generated when the watchdog timer’s most significant bit becomes “0.”
f
sys
System clock frequency select bit
Operating clock for
serial I/O, timer B
A-D conversion frequency
(φ
AD
) clock source
Operating clock for timer A
External clock input select bit
Interrupt
request
CLOCK GENERATING CIRCUIT
7902 Group User’s Manual 5-5
5.2.1 Clocks generated in clock generating circuit
(1) fXIN
It is the input clock from pin XIN.
(2) fPLL
It is the output clock from the PLL frequency multiplier.
(3) fsys
It is the system clock which becomes the clock source of CPU, BIU, and internal peripheral devices.
Whether fXIN = fsys or fPLL = fsys can be selected by software.
(4) φCPU
It is the operating clock of CPU.
(5) φBIU
It is the operating clock of BIU.
(6) Clock φ1
It has the same period as fsys and is output to the external from pin P41/φ1.
(7) f1, f2, f16, f64, f512, f4096
Each of them is the internal peripheral device’s operating clock.
(8) Wf32, Wf512
These are the operating clocks of the watchdog timer, and their clock source is f2.
(9) fX16, fX32, fX64, fX128
These are the divide clocks of fXIN and become the watchdog timer’s clock source at STP termination.
5.2 Clocks
CLOCK GENERATING CIRCUIT
7902 Group User’s Manual
5-6
5.2 Clocks
5.2.2 Clock control register
Figure 5.2.2 shows the structure of the clock control register, and Figure 5.2.3 shows the setting procedure
for the clock control register when using the PLL frequency multiplier.
1
1
1
0
0
0
0
0
Clock control register (Address BC16)
Bit nameBit Function
At reset
R/W
Fix this bit to “1.”
PLL circuit operation enable bit
(Note 1)
PLL multiplication ratio select bits
(Note 2)
Fix this bit to “0.”
System clock select bit (Note 3)
Peripheral device’s clock select bit 0
Peripheral device’s clock select bit 1
b7 b6 b5 b4 b3 b2 b1 b0
0 : PLL frequency muliplier is inactive, and pin VCONT
is invalid. (Floating)
1 : PLL frequency muliplier is active, and pin VCONT is
valid.
0 0 : Do not select.
0 1 : Double
1 0 : Triple
1 1 : Quadruple
b3 b2
See Table 5.2.2.
0 : fXIN
1 : fPLL
01
Notes 1: Clear this bit to “0” if the PLL frequency multiplier need not to be active.
In the stop and flash memory parallel I/O modes, the PLL frequency multiplier is inactive and pin VCONT is invalid regard-
less of the contents of this bit.
2: Rewriting of these bits must be performed simultaneously with clearance of the system clock select bit (bit 5). Then, set
bit 5 to “1” 2 ms after the rewriting of these bits. (After reset, these bits are allowed to be changed only once.)
3: Clearing the PLL circuit operation enable bit (bit 1) to “0” clears the system clock select bit to “0.” Also, while the PLL circuit
operation enable bit = “0,” nothing can be written to the system clock select bit. (Fixed to be “0.”)
In order to set the system clock select bit to “1” after reset, it is necessary to wait 2 ms after the stabilization of f(XIN).
0
1
2
3
4
5
6
7
Fig. 5.2.2 Structure of clock control register
RW
RW
RW
RW
RW
RW
RW
RW
(1) PLL circuit operation enable bit (bit 1)
Setting this bit to “1” enables the PLL frequency multiplier to be active and pin VCONT to be valid.
This bit = “1” while pin RESET = “L” level and after reset, so that, in this case, the PLL frequency
multiplier is active. Clear this bit to “0” if the PLL frequency multiplier need not to be active.
Note that, in the stop and flash memory parallel I/O modes, the PLL frequency multiplier is in active
and pin VCONT is invalid regardless of the contents of this bit. (Refer to sections “16.3 Stop mode” and
“20.4 Flash memory parallel I/O mode.”)
(2) PLL multiplication ratio select bits (bits 2, 3)
These bits select the multiplication ratio of the PLL frequency multiplier. (See Table 5.2.1.) To rewrite
these bits, clear the system clock select bit (bit 5) to “0” simultaneously. Then, set the system clock
select bit to “1” 2 ms after the rewriting of this bit. (See Figure 5.2.3.)
Note that, after reset, these bits are allowed to be changed only once.
CLOCK GENERATING CIRCUIT
7902 Group User’s Manual 5-7
5.2 Clocks
(3) System clock select bit (bit 5)
This bit selects a clock source of fsys. When this bit = “0,” fXIN is selected as fsys; and when this bit =
“1,” fPLL as the one. (See Table 5.2.1.)
Clearing the PLL circuit operation enable bit (bit 1) to “0” clears the system clock select bit to “0.” Also,
while the PLL circuit operation enable bit = “0,” nothing can be written to the system clock select bit.
(Fixed to be “0.”)
In order to set the system clock select bit to “1” after reset, it is necessary to wait 2 ms after the
stabilization of f(XIN).
To rewrite the PLL multiplication ratio select bits (bits 2 and 3), clear the system clock select bit to
“0” simultaneously. Then, set this bit to “1” 2 ms after the rewriting of the PLL multiplication ratio select
bits. (See Figure 5.2.3.)
System clock select bit
(bit 5)
PLL multiplication ratio select bits
(bits 3, 2) (Note 1) fsys
0
1
01 (double)
10 (triple)
11 (quadruple)
f(XIN)
f(XIN) 2
f(XIN) 3
f(XIN) 4
PLL circuit operation enable bit
(bit 1)
1
Clock source
Frequency (Note 2)
fXIN
fPLL
fPLL
fPLL
fsys/2
fsys/4
fsys/32
fsys/128
fsys/1024
fsys/8192
Do not select.
Internal peripheral
device’s operation clock 00
Peripheral device’s clock select bits 1, 0
f1
f2
f16
f64
f512
f4096
fsys
fsys/2
fsys/16
fsys/64
fsys/512
fsys/4096
01 10 11
fsys
fsys
fsys/8
fsys/32
fsys/256
fsys/2048
(Note)
Table 5.2.1 fsys selection
Notes 1: The PLL multiplication ratio select bits must be set so that fsys is in the range from 10 MHz to 26 MHz. After
reset, these bits are allowed to be changed only once.
2: Be sure that fsys does not exceed 26 MHz.
Table 5.2.2 Internal peripheral device’s operation clock frequency
(4) Peripheral device’s clock select bits 1, 0 (bits 7, 6)
These bits select the internal peripheral device’s operation clock frequency listed in Table 5.2.2.
Note: To set the peripheral device’ s clock select bits 1, 0 to “012,” be sure that a frequency of f sys must be 13 MHz or less.
CLOCK GENERATING CIRCUIT
7902 Group User’s Manual
5-8
5.2 Clocks
Fig. 5.2.3 Setting procedure for clock control register when using PLL frequency multiplier
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
2 ms elapsed ?
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
b0 Clock control register (Address BC16)
b7 10 1
System clock select bit
0 : fPLL
Setting of system clock select bit to “1.”
N
Y
(Note 2)
Notes 1: After reset, these bits are allowed to be changed only once. If
it is necessary to write a certain value to these bits, be sure to
write the same value that has been written after the latest reset.
2: This decision is unnecessary If double is selected and the
period of RESET = “L” is “the oscillation stabilizing time of an
oscillator + 2 ms” or more.
b0 Clock control register (Address BC16)
b7
PLL multiplication ratio select bits (Note 1)
0 1 : Double
1 0 : Triple
1 1 : Quadruple
00 1
b3 b2
System clock select bit
0 : fXIN
PLL frequency multiplier is active, and
pin VCONT is valid.
1
1
CLOCK GENERATING CIRCUIT
7902 Group User’s Manual 5-9
5.2 Clocks
RW
(Note)
RW
(Note)
RW
0
0
0
Bit nameBit
0
1
7 to 2
Particular function select register 0 (Address 6216)
Function
At reset
R/W
STP instruction invalidity select bit
External clcok input select bit
Fix this bit to “0.”
b7 b6 b5 b4 b3 b2 b1 b0
0 : STP instruction is valid.
1 : STP instruction is invalid.
0 : Oscillation circuit is active. (Oscillator is connected.)
Watchdog timer is used at stop mode termination.
1 : Oscillation circuit is inactive. (External clock is
input.)
When the system clock select bit (bit 5 at address BC
16
) = “0,”
watchdog timer is not used at stop mode termination.
When the system clock select bit = “1,”
watchdog timer is used at stop mode termination.
000000
5.2.3 Particular function select register 0
Figure 5.2.4 shows the structure of the particular function select register 0, and Figure 5.2.5 shows the
writing procedure for the particular function select register 0.
Fig. 5.2.4 Structure of particular function select register 0
Note: Writing to these bits requires the following procedure:
• Write “5516” to this register. (The bit status does not change only by this writing.)
• Succeedingly, write “0” or “1” to each bit.
Also, use the MOVMB (MOVM when m = 1) instruction or STAB (STA when m = 1) instruction.
If an interrupt occurs between writing of “5516” and next writing of “0” or “1,” latter writing may be ignored. When there is a
possibility that an interrupt occurs at the above timing, be sure to read this bit’s contents after writing of “0” or “1,” and verify
whether “0” or “1” has correctly been written or not.
CLOCK GENERATING CIRCUIT
7902 Group User’s Manual
5-10
(1) External clock input select bit (bit 1)
Setting this bit to “1” stops the oscillation driver circuit between pins XIN and XOUT and keeps the output
level at pin XOUT being “H.” (Refer to section “17.4 Stop of oscillation circuit.”) At the stop mode
termination owing to an interrupt occurrence, the watchdog timer is not used if the system clock select
bit (bit 5 at address BC16) = “0,” where as the watchdog timer is used if the system clock select bit
= “1.”
To rewrite this bit, write “0” or “1” just after writing of “5516” to address 6216. (See Figure 5.2.5.)
Note that if an interrupt occurs between writing of “5516” and next writing of “0” or “1,” latter writing
may be ignored. When there is a possibility that an interrupt occurs at the above timing, be sure to
read this bit’s contents after writing of “0” or “1,” and verify whether “0” or “1” has correctly been
written or not.
In addition, even when the watchdog timer is disabled by the particular function select register 2
(address 6416), the watchdog timer can be active only at the stop mode termination if this bit = “0.”
(Refer to section “16.3 Stop mode.”)
5.2 Clocks
Fig. 5.2.5 Writing procedure for particular function select register 0
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
00
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
0
Writing of “55
16
b0
Particular function select register 0 (Address 62
16
)
b7
1
Setting completed
AAA
AAA
AAA
10
Writing to bits 0, 1
b0
Particular function select register 0 (Address 62
16
)
b7
External clock input select bit
0 : Oscillation circuit is active. (Oscillator is connected.)
Watchdog timer is used at stop mode termination.
1 : Oscillation circuit is inactive. (External clock is input.)
When the system clock select bit (bit 5 at address BC
16
) = “0,”
watchdog timer is not used at stop mode termination.
When the system clock select bit = “1,”
watchdog timer is used at stop mode termination.
STP instruction invalidity select bit
0 : STP instruction is valid.
1 : STP instruction is invalid.
Next
instruction
Note: Bits’ state does not change only
by writing of “55
16
.”
000000
11
00
CLOCK GENERATING CIRCUIT
7902 Group User’s Manual 5-11
[Precautions for clock generating circuit]
[Precautions for clock generating circuit]
1. While pin RESET = “L” level and after reset, the PLL frequency multiplier is inactive. Clear the PLL circuit
operation enable bit (bit 1 at address BC16) to “0” if the PLL frequency multiplier need not to be active.
2. To select fPLL as fsys after reset, set the system clock select bit (bit 5 at address BC16) to “1” 2 ms after
f(XIN) has been stabilized. (See Figure 5.2.3.)
3. To rewrite the PLL multiplication ratio for the PLL frequency multiplier, clear the system clock select bit
(bit 5 at address BC16) to “0” simultaneously. Then, set the system clock select bit to “1” 2 ms after the
rewriting of the PLL multiplication ratio select bits (bits 2, 3 at address BC16). (See Figure 5.2.3.)
After reset, the PLL multiplication ratio select bits are allowed to be changed only once. If it is necessary
to write a certain value to these bits, be sure to write the same value that has been written after the latest
reset.
CLOCK GENERATING CIRCUIT
7902 Group User’s Manual
5-12
[Precautions for clock generating circuit]
MEMORANDUM
CHAPTER 6CHAPTER 6
INPUT/OUTPUT
PINS
6.1 Overview
6.2 Programmable I/O ports
6.3 Examples of handling unused pins
INPUT/OUTPUT PINS
7902 Group User’s Manual
6-2
6.1 Overview, 6.2 Programmable I/O ports
6.1 Overview
Input/output pins (hereafter called I/O pins) have functions as programmable I/O port pins, internal peripheral
devices’s I/O pins, external buses, etc.
For the basic functions of each I/O pin, refer to section “1.3 Pin description.” For the I/O functions of the
internal peripheral devices, refer to relevant sections of each internal peripheral device. For the external
address bus, external data bus, bus control signals, etc., refer to “CHAPTER 3. CONNECTION WITH
EXTERNAL DEVICES.”
This chapter describes the programmable I/O ports and examples of handling unused pins.
6.2 Programmable I/O ports
The programmable I/O ports have direction registers and port registers in the SFR area. Figure 6.2.1 shows
the memory map of direction registers and port registers.
Fig. 6.2.1 Memory map of direction registers and port registers
17
16
18
16
A
16
B
16
C
16
D
16
E
16
F
16
10
16
11
16
12
16
13
16
14
16
Addresses
15
16
16
16
Port P0 register
Port P1 register
Port P0 direction register
Port P1 direction register
19
16
2
16
3
16
4
16
5
16
6
16
7
16
8
16
9
16
Port P2 register
Port P3 register
Port P2 direction register
Port P3 direction register
Port P4 register
Port P5 register
Port P4 direction register
Port P5 direction register
Port P6 register
Port P7 register
Port P6 direction register
Port P7 direction register
Port P8 register
Port P8 direction register
Port P10 register
Port P11 register
Port P10 direction register
Port P11 direction register
INPUT/OUTPUT PINS
7902 Group User’s Manual 6-3
6.2 Programmable I/O ports
6.2.1 Direction register
This register determines the I/O direction of programmable I/O ports. One bit of this register corresponds
to one pin of the microcomputer, and this is the one-to-one relationship.
Figure 6.2.2 shows the structure of port Pi (i = 0 to 8, 10, 11) direction register.
Fig. 6.2.2 Structure of port Pi (i = 0 to 8, 10, 11) direction register
0
1
2
3
4
5
6
7
Port Pi direction register (i = 0 to 8, 10, 11)
(Addresses 416, 516, 816, 916, C16, D16, 1016, 1116, 1416, 1816, 1916)
Port Pi0 direction bit
Port Pi1 direction bit
Port Pi2 direction bit
Port Pi3 direction bit
Port Pi4 direction bit
Port Pi5 direction bit
Port Pi6 direction bit
Port Pi7 direction bit
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
b7 b6 b5 b4 b3 b2 b1 b0
Note: Nothing is assigned for bits 4 to 7 of the port P3 direction register. These bits are “0” at reading.
0 : Input mode
(The port functions as an input port)
1 : Output mode
(The port functions as an output port)
Bit nameBit Function At reset R/W
INPUT/OUTPUT PINS
7902 Group User’s Manual
6-4
6.2 Programmable I/O ports
6.2.2 Port register
Data is input from or output to the external by writing/reading data to/from a port register. A port register
consists of a port latch which holds the output data and a circuit which reads the pin state. One bit of the
port register corresponds to one pin of the microcomputer. (This is the one-to-one relationship.) Figure
6.2.3 shows the structure of the port Pi (i = 0 to 8, 10, 11) register.
When outputting data from programmable I/O port which has been set to output mode
By writing data to the corresponding bit of the port register, the data is written into the port latch.
The data is output from the pin according to the contents of the port latch.
By reading the port register of a port which has been set to the output mode, the contents of the port
latch is read out, instead of the pin state. Accordingly, the output data can be correctly read out without
being affected by an external load, etc. (Refer to “Figures 6.2.4 and 6.2.5.”)
When inputting data from programmable I/O port which has been set to input mode
A pin which has been set to the input mode enters the floating state.
By reading the corresponding bit of the port register, the data which has been input from the pin can
be read out.
By writing data to a port register of a programmable I/O port which has been set to the input mode,
the data is written only into the port latch and is not output to the external (Note). This pin remains
floating state.
Note: When executing a read-modify-write instruction to a port register of a programmable I/O port
which has been set to the input mode, the instruction will be executed to the data which has
been input from the pin and the result will be written into the port register.
6.2 Programmable I/O ports
Fig. 6.2.3 Structure of port Pi (i = 0 to 8, 10, 11) register
Port Pi register (i = 0 to 8, 10, 11)
(Addresses 216, 316, 616, 716, A16, B16, E16, F16, 1216, 1616, 1716)
b7 b6 b5 b4 b3 b2 b1 b0
RW
RW
RW
RW
RW
RW
RW
RW
Bit nameBit
0
1
2
3
4
5
6
7
Funtion At reset R/W
Pin port Pi0
Pin port Pi1
Pin port Pi2
Pin port Pi3
Pin port Pi4
Pin port Pi5
Pin port Pi6
Pin port Pi7
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Note: Nothing is assigned for bits 4 to 7 of the port P3 register. These bits are “0” at reading.
Data is input from or output to a pin by reading from
or writing to the corresponding bit.
0 : “L” level
1 : “H” level
INPUT/OUTPUT PINS
7902 Group User’s Manual 6-5
6.2 Programmable I/O ports
Figures 6.2.4 and 6.2.5 show the port peripheral circuits.
Fig. 6.2.4 Port peripheral circuits (1)
[Inside dotted-line not included]
P0
0
to P0
7
, P1
0
to P1
7
, P2
0
to P2
7
,
P3
1
to P3
3
, P10
0
to P10
7
,
P11
0
to P11
7
[Inside dotted-line included]
P3
0
/RDY, P4
3
/HOLD,
P6
1
/TA4
IN
,
P6
2
/INT
0
, P6
3
/INT
1
, P6
4
/INT
2
,
P6
5
/TB0
IN
, P6
6
/TB1
IN
, P6
7
/TB2
IN
,
P8
2
/R
X
D
0
, P8
6
/R
X
D
1
[Shaded area not included]
P5
1
/TA0
IN
/RTP0
1
,
P5
3
/TA1
IN
/RTP0
3
[Shaded area included]
P5
5
/TA2
IN
/RTP1
1
/KI
1
,
P5
7
/TA3
IN
/RTP1
3
/KI
3
[Inside dotted-line not included]
P4
0
/ALE, P4
1
/φ
1
, P4
2
/HLDA,
P8
3
/T
X
D
0
, P8
7
/T
X
D
1
[Inside dotted-line included]
P6
0
/TA4
OUT
[Shaded area included]
P4
4
/CS
0
, P4
5
/CS
1
,
P4
6
/CS
2
, P4
7
/CS
3
[Shaded area not included]
P5
0
/TA0
OUT
/RTP0
0
,
P5
2
/TA1
OUT
/RTP0
2
[Shaded area included]
P5
4
/TA2
OUT
/RTP1
0
/KI
0
,
P5
6
/TA3
OUT
/RTP1
2
/KI
2
Data bus
Port latch
Direction register
1
Data bus
Port latch
Direction register
Pullup selection Pullup
transistor
Data bus
Port latch
Direction register
Latch T
CK
Timer
underflow signal
Pullup selection Pullup
transistor
Output
(Internal peripheral devices)
Data bus
Port latch
Direction register
Latch T
CK
Timer
underflow signal
1
Pullup selection Pullup
transistor
Q
Q
Output
(Internal peripheral devices)
INPUT/OUTPUT PINS
7902 Group User’s Manual
6-6
P8
1
/CTS
0
/CLK
0
,
P8
4
/CTS
1
/RTS
1
/INT
4
,
P8
5
/CTS
1
/CLK
1
[Inside dotted-line not included]
P7
0
/AN
0
, P7
1
/AN
1
,
P7
2
/AN
2
, P7
3
/AN
3
[Inside dotted-line included]
P7
4
/AN
4
/(INT
3
),
P7
5
/AN
5
/(INT
4
)
P8
0
/CTS
0
/RTS
0
/DA
2
/INT
3
[Inside dotted-line not included]
P7
6
/AN
6
/DA
0
[Inside dotted-line included]
P7
7
/AN
7
/AD
TRG
/DA
1
/(INT
2
)
Analog input
Analog output Enable D-A output
1
0
1
0
Analog output
Enable D-A output
Analog input
NMI
Pullup selection
Data bus
Port latch
Direction register
Data bus
Port latch
Direction register
Data bus
Port latch
Direction register
Data bus
Port latch
Direction register
Pullup
transistor
Output
(Internal peripheral devices)
Output
(Internal peripheral devices)
Fig. 6.2.5 Port peripheral circuits (2)
6.2 Programmable I/O ports
INPUT/OUTPUT PINS
7902 Group User’s Manual 6-7
6.2 Programmable I/O ports
6.2.3 Selectable functions
In the usage of programmable I/O ports, the following items are selectable:
Port P0 input level
Port pins P44–P47 pullup function
Notes 1: For the M37902FxM (power source voltage = 3.3 V±0.3 V), VIH = 0.5Vcc.
2: When MD1 = Vcc and MD0 = Vcc (flash memory parallel I/O mode), pins P44 to P47 and NMI are not pulled up, regardless
of these bits’ contents.
3: When MD1 = Vss and MD0 = Vcc (microprocessor mode), pin CS0 (P44) is not pulled up regardless of this bit’s contents.
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
Port function control register (Address 9216)b7 b6 b5 b4 b3 b2 b1 b0
0
1
2
3
4
6, 5
7
Bit nameBit Function At reset R/W
Address/Port switch bits
Port P0 input level select bit
Pins P44–P47 pullup select bit
Fix these bits to “0”.
Pin NMI pullup select bit
0 0 0 : A0 to A23 (16 Mbytes)
0 0 1 : A0 to A21, P06, P07 (4 Mbytes)
0 1 0 : A0 to A19, P04 to P07 (1 Mbytes)
0 1 1 : A0 to A17, P02 to P07 (256 Kbytes)
1 0 0 : A0 to A15, P00 to P07 (64 Kbytes)
1 0 1 : Do not select.
1 1 0 : A0 to A11, P00 to P07, P114 to P117 (4 Kbytes)
1 1 1 : A0 to A7, P00 to P07, P110 to P117 (256 bytes)
b2 b1b0
0 : Pins P44–P47 are pulled up.
1 : Pins P44–P47 are not pulled up (Notes 2, 3).
0 : Pin NMI is pulled up.
1 : Pin NMI is not pulled up (Note 2).
0 : VIH = 0.7 Vcc, VIL = 0.2 Vcc
1 : VIH = 0.43 Vcc (Note 1), VIL = 0.16 Vcc
00
Fig. 6.2.6 Structure of port function control register
(1) Port P0 input level select bit (bit 3)
This bit allows the user to select the input level to port P0 (VIH, VIL). According to the external devices
to be connected with port P0, set this bit’s contents.
(2) Pins P44–P47 pullup select bit (bit 4)
While the voltage level at pin RESET = “L” and after reset, this bit = “0” and pins P44–P47 are pulled
up.
Accordingly, no external pullup resistor is necessary.
By setting this bit to “1,” the pullup state is removed.
When one of the following settings is selected, the pullup state is removed regardless of this bit’s
contents. (The bit’s contents do not change.)
• The P44–P47 direction registers are set to “1” (output mode).
• The CS0 to CS3 output select bits (bit 7 at addresses 8016, 8216, 8416, 8616) are set to “1”. (By this
setting, the CS0/CS1/CS2/CS3 outputs become enabled.)
Regardless of this bit’s contents;
• Pins P44–P47 are not pulled up in the flash memory parallel I/O mode (MD1 = Vcc, MD0 = Vcc).
• Pin CS0 (P44) is not pulled up in the microprocessor mode (MD1 = Vss, MD0 = Vcc).
For the flash memory parallel I/O mode, refer to the section on “20.4 Flash memory parallel I/O
mode”.
INPUT/OUTPUT PINS
7902 Group User’s Manual
6-8
6.3 Examples of handling unused pins
6.3 Examples of handling unused pins
When unusing an I/O pin, some handling is necessary for this pin. Examples of handling unused pins are
described below.
The following are just examples. In actual use, the user shall modify them according to the user’s application
and properly evaluate their performance.
6.3.1 In the single-chip mode
Table 6.3.1 Example of handling unused pins in single-chip mode
Handling example
Set these pins to the input mode and connect each
pin to Vcc or Vss via a resistor; or set these pins to
the output mode and leave them open (Note 1).
Set these pins to the input mode and leave them open (Notes 2, 3)
Leave these pins open.
Connect this pin to Vcc.
Connect these pins to Vss.
Pin name
P0 to P3, P40 to P43, P5 to P8, P10, P11
P44 to P47
NMI (Notes 2, 4), XOUT (Note 5), VCONT (Note 6)
AVCC
AVSS, VREF, BYTE
Notes 1: When leaving these pins open after they have been set to the output mode, note the following:
these port pins are placed in the input mode from reset until they are switched to the output mode
by software. Therefore, voltage levels of these pins are undefined and the power source current
may increase while these port pins are placed in the input mode.
Software reliability can be enhanced by setting the contents of the above ports’ direction registers
periodically. This is because these contents may be changed by noise, a program runaway which
occurs owing to noise, etc.
For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer’s pins).
2: Do not connect these pins to Vss.
3: Be sure that the pins P44–P47 pullup select bit (bit 4 at address 9216) = 0.
4: Be sure that the pin NMI pullup select bit (bit 7 at address 9216) = 0.
5: This applies when a clock externally generated is input to pin XIN.
6: Be sure that the PLL circuit operation enable bit (bit 1 at address BC16) = 0.
Fig. 6.3.1 Example of handling unused pins in single-chip mode
P0–P3, P4
0
–P4
3
,
P5–P8, P10, P11
M37902
Left open
When setting port pins to input mode
V
CC
P4
4
–P4
7
NMI
X
OUT
V
CONT
V
CC
V
SS
P0–P8, P10, P11
M37902
When setting port pins to output mode (Note)
AV
CC
AV
SS
V
REF
BYTE
AV
CC
AV
SS
V
REF
BYTE
NMI
X
OUT
V
CONT
Note: Be sure to set P44–P47 to the input mode.
V
SS
Left open
Left open
INPUT/OUTPUT PINS
7902 Group User’s Manual 6-9
6.3 Examples of handling unused pins
6.3.2 In memory expansion and microprocessor modes
Table 6.3.2 Example of handling unused pins in memory expansion and microprocessor modes
Handling example
Set these pins to the input mode and connect each
pin to Vcc or Vss via a resistor; or set these pins to
the output mode and leave them open (Note 2).
Set these pins to the input mode and leave them open (Notes 3,4)
Leave these pins open.
Connect this pin to Vcc.
Connect these pins to Vss.
Leave these pins open.
Connect these pins to Vcc via a resistor.
Pin name
P2 (Note 1), P30, P33 (Note 1), P40 to P43, P5 to P8
P44 to P47
NMI (Notes 3, 5), XOUT (Note 6), VCONT (Note 7)
AVCC
AVSS, VREF
φ1 (Note 8), ALE (Note 8), HLDA (Note 8)
RDY (Note 8), HOLD (Note 8)
Notes 1: This applies when the VCC level voltage is applied to pin BYTE.
2: When leaving these pins open after they have been set to the output mode, note the following:
these port pins are placed in the input mode from reset until they are switched to the output mode
by software. Therefore, voltage levels of these pins are undefined and the power source current
may increase while these pins are placed in the input mode.
Software reliability can be enhanced by setting the contents of the above ports’ direction registers
periodically. This is because these contents may be changed by noise, a program runaway which
occurs owing to noise, etc.
3: Do not connect these pins to Vss.
4: Be sure that the pins P44–P47 pullup select bit (bit 4 at address 9216) = 0.
5: Be sure that the pin NMI pullup select bit (bit 7 at address 9216) = 0.
6: This applies when a clock externally generated is input to pin XIN.
7: Be sure that the PLL circuit operation enable bit (bit 1 at address BC16) = 0.
8: This applies when the Vcc-level voltage is applied to pin MD0. (It is also possible to disable these functions
by software and use these pins as programmable I/O port pins.)
Fig. 6.3.2 Example of handling unused pins in memory expansion and microprocessor modes
P2, P3
0
, P3
3
,
P4
0
–P4
3
, P5–P8
M37902
V
CC
P4
4
–P4
7
NMI
X
OUT
V
CONT
V
CC
V
SS
P2, P3
0
, P3
3
, P4–P8
M37902
AV
CC
AV
SS
V
REF
AV
CC
AV
SS
V
REF
V
SS
φ
1
ALE
HLDA
RDY
HOLD
V
CC
φ
1
ALE
HLDA
RDY
HOLD
NMI
X
OUT
V
CONT
V
CC
When setting port pins to input mode When setting port pins to output mode
Note: Be sure to set P4
4
–P4
7
to the input mode.
Left open Left open
Left open
Left open
Left open
INPUT/OUTPUT PINS
7902 Group User’s Manual
6-10
6.3 Examples of handling unused pins
MEMORANDUM
CHAPTER 7CHAPTER 7
INTERRUPTS
7.1 Overview
7.2 Interrupt sources
7.3 Interrupt control
7.4 Interrupt priority level
7.5 Interrupt priority level detection
circuit
7. 6 Interrupt priority level detection time
7.7 Sequence from acceptance of
interrupt request until execution of
interrupt routine
7.8 Return from interrupt routine
7.9 Multiple interrupts
7.10 External interrupts
[Precautions for interrupts]
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7-2
7.1 Overview
The M37902 provides 23 (including the reset) interrupt sources to generate interrupt requests.
Figure 7.1.1 shows the interrupt processing sequence.
When an interrupt request is accepted, a branch is made to the start address of the interrupt routine set
in the interrupt vector table (addresses FFC016 to FFFF16). Set the start address of each interrupt routine
to the corresponding interrupt vector address in the interrupt vector table.
7.1 Overview
Fig. 7.1.1 Interrupt processing sequence
Interrupt routine
Interrupt request is accepted.
Processing is resumed.
Processing is suspended.
Returns to original routine.
RTI instruction
Interrupt processing
Routine in progress
Branches to start address
of interrupt routine.
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INTERRUPTS
When an interrupt request is accepted, the following registers’ contents just before acceptance of an interrupt
request are automatically pushed onto the stack area in ascending sequence from to .
For other registers of which contents are necessary, be sure to push and pop them by software.
Program bank register (PG)
Program counter (PCL, PCH)
Processor status register (PSL, PSH)
Figure 7.1.2 shows the state of the stack area just before entering an interrupt routine.
Execute the RTI instruction at the end of this interrupt routine in order to return to the routine that the
microcomputer was executing just before the interrupt request was accepted. By executing the RTI instruction,
the register contents pushed onto the stack area are pulled in descending sequence from to . Then, the
suspended processing is resumed from where it left off.
7.1 Overview
[S] is an initial address that the stack pointer (S) indicates
when an interrupt request is accepted. The S’s contents
become “[S] – 5” after all of the above registers are pushed.
Address
[S] – 4
[S] – 3
[S] – 2
[S] – 1
[S]
Processor status register’s low-order byte (PSL)
Stack area
[S] – 5
Processor status register’s high-order byte (PSH)
Program counter’s low-order byte (PCL)
Program counter’s high-order byte (PCH)
Program bank register (PG)
Fig. 7.1.2 State of stack area just before entering interrupt routine
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Remarks
Non-maskable
Non-maskable software interrupt
Do not use.
Non-maskable internal interrupt
Non-maskable external interrupt
Maskable external interrupts
Maskable internal interrupts
Maskable internal interrupts
Maskable internal interrupts
Maskable internal interrupt
Maskable external interrupts
Do not use.
Non-maskable software interrupt
Do not use.
7.2 Interrupt sources
Table 7.2.1 lists the interrupt sources and the interrupt vector addresses. When programming, set the start
address of each interrupt routine to the vector addresses listed in this table.
7.2 Interrupt sources
Low-order
address
FFFE16
FFFC16
FFFA16
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
FFE216
FFE016
FFDE16
FFDC16
FFDA16
FFD816
FFD616
FFD416
FFD216
FFD016
FFCE16
FFCC16
FFCA16
FFC816
FFC616
FFC416
FFC216
FFC016
Interrupt vector addresses
Table 7.2.1 Interrupt sources and interrupt vector addresses
High-order
address
FFFF16
FFFD16
FFFB16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFE116
FFDF16
FFDD16
FFDB16
FFD916
FFD716
FFD516
FFD316
FFD116
FFCF16
FFCD16
FFCB16
FFC916
FFC716
FFC516
FFC316
FFC116
Interrupt source
Reset
Zero division
BRK instruction (Note)
____
DBC (Note)
Watchdog timer
____
NMI
____
INT0
____
INT1
____
INT2
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
Timer B2
UART0 receive
UART0 transmit
UART1 receive
UART1 transmit
A-D conversion
____
INT3
____
INT4
Reserved area
Reserved area
Address matching detection
Reserved area
Reserved area
Reserved area
Reserved area
Reserved area
____
Note: The BRK instruction and the DBC interrupt are used exclusively for a debugger.
Maskable interrupt: An interrupt of which request’s acceptance can be disabled by software.
____
Non-maskable interrupt (including zero division, watchdog timer, NMI, and address matching detection
interrupts):
An interrupt which is certain to be accepted when its request occurs. These interrupts do not have their
interrupt control registers and are not affected by the interrupt disable flag (I).
Reference
4. RESET
7900 Series Software Manual
15. WATCHDOG TIMER
7.10 External interrupts
9. TIMER A
10. TIMER B
12. SERIAL I/O
13. A-D CONVERTER
7.10 External interrupts
18. DEBUG FUNCTION
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INTERRUPTS
7.3 Interrupt control
The maskable interrupts are controlled by the following :
•Interrupt request bit
•Interrupt priority level select bits
•Processor interrupt priority level (IPL)
•Interrupt disable flag (I)
Figure 7.3.1 shows the memory assignment of the interrupt control registers, and Figures 7.3.2 and 7.3.3
show their structures.
}
}Assigned to an interrupt control register of each interrupt.
Assigned to the processor status register (PS).
7.3 Interrupt control
Fig. 7.3.1 Memory assignment of interrupt control registers
UART0 transmit interrupt control register
6F
16
UART1 transmit interrupt control register
UART1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT
0
interrupt control register
INT
1
interrupt control register
INT
2
interrupt control register
Address
UART0 receive interrupt control register
70
16
71
16
72
16
73
16
74
16
75
16
76
16
77
16
78
16
79
16
7A
16
7B
16
7C
16
7D
16
7E
16
7F
16
A-D conversion interrupt control register
6E
16
INT
4
interrupt control register
INT
3
interrupt control register
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INTERRUPTS
7-6
Fig. 7.3.2 Structure of interrupt control register (1)
7.3 Interrupt control
A-D conversion, UART0 and 1 transmit, UART0 and 1 receive,
timers A0 to A4, timers B0 to B2 interrupt control registers
(Addresses 7016 to 7C16)
b7 b6 b5 b4 b3 b2 b1 b0
0
1
2
3
7 to 4
Interrupt priority level select bits
Interrupt request bit
Nothing is assigned.
Notes 1: The A-D conversion interrupt request bit is undefined after reset.
2: When writing to this bit, use the MOVM (MOVMB) or STA (STAB, STAD) instruction.
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1b0
0 : No interrupt requested
1 : Interrupt requested
0
0
0
0
(Note 1)
Undefined
RW
RW
RW
RW
(Note 2)
Bit nameBit Function At reset R/W
7902 Group User’s Manual 7-7
INTERRUPTS
0
1
2
3
4
5
7, 6
INT0 to INT2 interrupt control registers (Addresses 7D16 to 7F16)
Interrupt priority level select bits
Interrupt request bit (Note 1)
Polarity select bit
Level sense/Edge sense select
bit
Nothing is assigned.
b7 b6 b5 b4 b3 b2 b1 b0
Notes 1: The interrupt request bits of INT0 to INT2 interrupts are invalid when the level sense is selected.
2: When writing to this bit, use the MOVM (MOVMB) or STA (STAB, STAD) instruction.
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1b0
0 : No interrupt requested
1 : Interrupt requested
0 : The interrupt request bit is set to “1” at “H” level
when level sense is selected; this bit is set to “1”
at falling edge when edge sense is selected.
1 : The interrupt request bit is set to “1” at “L” level
when level sense is selected; this bit is set to “1”
at rising edge when edge sense is selected.
0 : Edge sense
1 : Level sense
0
0
0
0
0
0
Undefined
RW
RW
RW
RW
(Note 2)
RW
RW
Bit nameBit Function At reset R/W
Fig. 7.3.3 Structure of interrupt control register (2)
7.3 Interrupt control
0
1
2
3
4
7 to 5
INT3, INT4 interrupt control registers (Addresses 6E16, 6F16)
Interrupt priority level select bits
Interrupt request bit
Polarity select bit
Nothing is assigned.
b7 b6 b5 b4 b3 b2 b1 b0
Note: When writing to this bit, use the MOVM (MOVMB) or STA (STAB, STAD) instruction.
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1b0
0 : No interrupt requested
1 : Interrupt requested
0 : The interrupt request bit is set to “1” at the falling
edge.
1 : The interrupt request bit is set to “1” at the rising
edge.
0
0
0
0
0
Undefined
RW
RW
RW
RW
(Note)
RW
Bit nameBit Function At reset R/W
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7-8
7.3.1 Interrupt disable flag (I)
All maskable interrupts can be disabled by this flag. When this flag is set to “1,” all maskable interrupts
are disabled; when this flag is cleared to “0,” those interrupts are enabled. Because this flag is set to “1”
at reset, clear this flag to “0” when enabling interrupts.
7.3.2 Interrupt request bit
When an interrupt request occurs, this bit is set to “1.” This bit remains set to “1” until the interrupt request
is accepted; it is cleared to “0” when the interrupt request is accepted.
This bit can also be set to “0” or “1” by software.
The INTi interrupt request bit (i = 0 to 2) is ignored when the corresponding INTi interrupt is used with the
level sense.
7.3.3 Interrupt priority level select bits and Processor interrupt priority level (IPL)
The interrupt priority level select bits are used to determine the priority level of each interrupt.
When an interrupt request occurs, its interrupt priority level is compared with the processor interrupt priority
level (IPL). The requested interrupt is enabled only when the comparison result meets the following condition.
Accordingly, any interrupt can be disabled by setting its interrupt priority level to 0.
Each interrupt priority level > Processor interrupt priority level (IPL)
Table 7.3.1 lists the setting of interrupt priority levels, and Table 7.3.2 lists the enabled interrupt’s levels
according to the IPL contents.
The interrupt disable flag (I), interrupt request bit, interrupt priority level select bits, and processor interrupt
priority level (IPL) are independent of one another; they do not affect one another. Interrupt requests are
accepted only when all of the following conditions are satisfied.
•Interrupt disable flag (I) = “0”
•Interrupt request bit = “1”
•Interrupt priority level > Processor interrupt priority level (IPL)
7.3 Interrupt control
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INTERRUPTS
b0
0
1
0
1
0
1
0
1
b2
0
0
0
0
1
1
1
1
Table 7.3.1 Setting of interrupt priority level
b1
0
0
1
1
0
0
1
1
Level 0 (Interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Low
High
7.3 Interrupt control
Interrupt priority level
Interrupt priority level select bits Priority
IPL2
0
0
0
0
1
1
1
1
Enabled interrupt’s level
Level 1 and above are enabled.
Level 2 and above are enabled.
Level 3 and above are enabled.
Level 4 and above are enabled.
Level 5 and above are enabled.
Levels 6 and 7 are enabled.
Only level 7 is enabled.
All maskable interrupts are disabled.
IPL1
0
0
1
1
0
0
1
1
IPL0
0
1
0
1
0
1
0
1
Table 7.3.2 Enabled interrupt’s levels according to IPL contents
IPL0: Bit 8 in processor status register (PS)
IPL1: Bit 9 in processor status register (PS)
IPL2: Bit 10 in processor status register (PS)
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7.4 Interrupt priority level
When the interrupt disable flag (I) = “0” (interrupts enabled) and more than one interrupt request is detected
at the same sampling timing, which means a timing to check whether an interrupt request exists or not, they
are accepted in descending sequence from the highest priority level.
A maskable interrupt can be set to the desired priority level by using the interrupt priority level select bits.
The priority levels of reset, a watchdog timer interrupt, and an NMI interrupt are set by hardware. Figure
7.4.1 shows the interrupt priority levels set by hardware.
Note that software interrupts are not affected by the interrupt priority levels. Whenever an instruction is
executed, a branch is certainly made to the interrupt routine.
7.4 Interrupt priority level
Fig. 7.4.1 Interrupt priority levels set by hardware
The user can set the desired priority level to a maskable interrupt.
Priority levels determined by hardware
HighLow Priority level
••••••••••••••••••
Reset
Watchdog
timer
NMI
Maskable
interrupts
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INTERRUPTS
7.5 Interrupt priority level detection circuit
The interrupt priority level detection circuit is used to select the interrupt with the highest priority level from
multiple interrupt requests sampled at the same timing. Figure 7.5.1 shows the interrupt priority level detection
circuit.
7.5 Interrupt priority level detection circuit
Fig. 7.5.1 Interrupt priority level detection circuit
Timer B2
Timer B1
Timer B0
Interrupt with the highest priority level
Interrupt priority level Level 0 (Initial value)
A-D conversion
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
INT
2
INT
1
INT
0
IPL
Processor interrupt priority level
Interrupt
disable flag (I)
Watchdog timer interrupt
Reset
Accepting of interrupt request
Interrupt priority level
INT
4
INT
3
NMI interrupt
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INTERRUPTS
7-12
The following explains the operation of the interrupt priority level detection circuit using Figure 7.5.2.
The interrupt priority level of a requested interrupt (Y in Figure 7.5.2) is compared with the resultant priority
level which is sent from the preceding comparator (X in Figure 7.5.2); the interrupt with the higher priority
level will be sent to the next comparator (Z in Figure 7.5.2). (The initial value of the comparison level is “0.”)
For an interrupt which is not requested, the comparison is not performed, and the priority level which is sent
from the preceding comparator is sent to the next comparator as it is. When the two priority levels are found
the same, as a resultant of the comparison, the priority level which is sent from the preceding comparator
will be sent to the next comparator. Accordingly, when the same priority level is set to multiple interrupts
by software, their interrupt priority levels are handled as follows:
____ ____
INT4 > INT3 > A-D conversion > UART1 transmit > UART1 receive > UART0 transmit > UART0 receive >
____ ____
Timer B2 > Timer B1 > Timer B0 > Timer A4 > Timer A3 > Timer A2 > Timer A1 > Timer A0 > INT2 > INT1
____
> INT0
Among the multiple interrupt requests sampled at the same timing, one request with the highest priority level
is detected by the above comparison.
Then, this highest interrupt priority level is compared with the processor interrupt priority level (IPL). When
this interrupt priority level is higher than IPL and the interrupt disable flag (I) is “0,” the interrupt request is
accepted. An interrupt request which is not accepted here is retained until it is accepted or its interrupt
request bit is cleared to “0” by software.
The interrupt priority level is detected when the CPU fetches an op code, which is called the CPU’s op-code
fetch cycle. However, when an op-code fetch cycle starts during detection of an interrupt priority, a new
interrupt priority detection does not start. (See Figure 7.6.2.) Since the state of the interrupt request bit and
interrupt priority levels are latched during the interrupt priority detection, even if they change, the interrupt
priority detection is performed for the state just before the change occurs.
The interrupt priority level is detected when the CPU fetches an op code. Therefore, in the following case,
no interrupt request is accepted until the CPU fetches the op code of the next instruction after the following
operation is completed:
•Execution of an instruction which requires many cycles, such as the MVN and MVP instructions
7.5 Interrupt priority level detection circuit
YX
Z
Comparator
(Priority level
comparison)
When X Y then Z = X
When X <
Y then Z = Y
Interrupt source Y
X : Priority level sent from the preceding
comparator (Highest priority level at this point)
Y : Priority level of interrupt source Y
Z : Highest priority level at this point
Time
Fig. 7.5.2 Interrupt priority level detection model
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7.6 Interrupt priority level detection time
When the interrupt priority level detection time has passed after sampling starts, an interrupt request is
accepted. The interrupt priority level detection time can be selected by software. (See Figure 7.6.1.) Usually,
select “2 cycles of fsys” as the interrupt priority level detection time.
Figure 7.6.2 shows the interrupt priority level detection time.
7.6 Interrupt priority level detection time
Fig. 7.6.2 Interrupt priority level detection time
fsys
Op-code fetch cycle
Sampling pulse
(a) 7 cycles of fsys
(b) 4 cycles of fsys
(c) 2 cycles of fsys
Interrupt priority level
detection time
(Note)
Note: The pulse resides when “2 c
y
cles of fs
y
s” is selected.
Fig. 7.6.1 Structure of processor mode register 0
Bit nameBit
Processor mode register 0 (Address 5E16)
Function
At reset
R/W
Processor mode bits
External bus cycle select bit 0
(Note 2)
Interrupt priority level detection
time select bits
Software reset bit
Clock φ1 output select bit
b7 b6 b5 b4 b3 b2 b1 b0
Notes 1: When the Vss-level voltage is applied to pin MD0, this bit is “0”; when the Vcc-level voltage is applied to pin MD0, this bit
is “1.” (Fixed to “1.”)
2: These bits are valid for the external area except for area CSi. Regardless of these bits’ contents, the bus cycle of area CSi
is decided by the corresponding area CSi bus cycle select bits 0, 1 (bits 0, 1 at addresses 8016, 8216, 8416, 8616, and bit 3
at addresses 8116, 8316, 8516, 8716).
3: When the Vss-level voltage is applied to pin MD0, this bit is “0”; when the Vcc-level voltage is applied to pin MD0, this bit
is “1.”
0 0 : Single-chip mode
0 1 : Memory expansion mode
1 0 : Microprocessor mode
1 1 : Do not select.
b1 b0
0 0 : 7 cycles of fsys
0 1 : 4 cycles of fsys
1 0 : 2 cycles of fsys
1 1 : Do not select.
b5 b4
The microcomputer is reset by writing “1” to this
bit. The value is “0” at reading.
0 : φ1 output is disabled. (P41 functions as a
programmable I/O port pin.)
1 : φ1 output is enabled. (P41 functions as a clock φ1
output pin.)
0
1
2
3
4
5
6
7
0
(Note 1)
0
1
0
0
0
(Note 3)
RW
RW
RW
RW
RW
RW
WO
RW
0 0 :
1φ + 1φ
0 1 :
1φ + 2φ
1 0 :
1φ + 3φ
1 1 :
2φ + 2φ
b2b3 0 0 :
2φ + 3φ
0 1 :
2φ + 4φ
1 0 :
3φ + 3φ
1 1 :
3φ + 4φ
b2b3
(External bus cycle select
bit 1 = 0) (External bus cycle select
bit 1 = 1)
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7.7 Sequence from acceptance of interrupt request until execution of
interrupt routine
The sequence from acceptance of an interrupt request until execution of the interrupt routine is described
below.
When an interrupt request is accepted, the interrupt request bit of the accepted interrupt is cleared to “0.”
And then, the interrupt processing starts from the cycle just after completion of the instruction execution
which was executed at acceptance of the interrupt request. Figure 7.7.1 shows the sequence from acceptance
of an interrupt request until execution of the interrupt routine. After execution of an instruction at acceptance
of the interrupt request is completed, an INTACK (Interrupt Acknowledge) sequence is executed, and a
branch is made to the start address of the interrupt routine allocated in addresses 016 to FFFF16.
In the INTACK sequence, the following are automatically performed in ascending sequence from to .
The contents of the program bank register (PG) just before performing the INTACK sequence are pushed
onto stack.
The contents of the program counter (PC) just before performing the INTACK sequence are pushed onto
stack.
The contents of the processor status register (PS) just before performing the INTACK sequence is
pushed onto stack.
The interrupt disable flag (I) is set to “1.”
The interrupt priority level of the accepted interrupt is set into the processor interrupt priority level (IPL).
The contents of the program bank register (PG) are cleared to “0016,” and the contents of the interrupt
vector address are set into the program counter (PC).
Performing the INTACK sequence requires at least 15 cycles of fsys. Figure 7.7.2 shows the INTACK sequence
timing. After the INTACK sequence is completed, the instruction execution starts from the start address of
the interrupt routine.
7.7 Sequence from acceptance of interrupt request until execution of interrupt routine
@
@ : Interrupt priority level detection time
Interrupt request occurs.
Interrupt request is accepted.
Instruction
1Instruction
2INTACK sequence Instructions in interrupt routine
Interrupt response time
Time
@
Time from occurrence of an interrupt request until comparison of an instruction execution which
is in progress at that time.
Time from execution start of an instruction next to until completion of execution of the instruction
which was in progress at detection completed.
Time required to perform the INTACK sequence (15 cycles of φ at minimum)
Fig. 7.7.1 Sequence from acceptance of interrupt request until execution of interrupt routine
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7.7 Sequence from acceptance of interrupt request until execution of interrupt routine
Fig. 7.7.2 INTACK sequence timing (at minimum)
7.7.1 Change in IPL at acceptance of interrupt request
When an interrupt request is accepted, the processor interrupt priority level (IPL) is replaced with the
interrupt priority level of the accepted interrupt. This results in easy control of the processing for multiple
interrupts. (Refer to section “7.9 Multiple interrupts.”)
At acceptance of a watch dog timer interrupt request, an NMI interrupt request, a zero division request, or
address matching detection interrupt request or at reset, a value in Table 7.7.1 is set into the IPL.
Table 7.7.1 Change in IPL at acceptance of interrupt request
Interrupts
Reset
Watchdog timer
NMI
Zero division
Address matching detection
Other interrupts
Change in IPL
Level 0 (“0002”) is set.
Level 7 (“1112”) is set.
Level 7 (“1112”) is set.
Not changed.
Not changed.
Accepted interrupt’s priority level is set.
When stack pointer (S)’s contents are even at acceptance of an interrupt request with bus cycle = 1φ + 1φ
Undefined 00 00 00 00 00
AD
23
–AD
16
BLW
BHW
f
sys
RD
00
INTACK sequence
φ
CPU
[S]: Contents of stack pointer (S)
FFXX
16
: Vector address
f
sys
, φ
CPU
: Internal clock (See Figure 5.2.1.)
AD
23
–AD
0
: Internal address bus
DB
15
–DB
0
: Internal data bus
AD
15
–AD
0
DB
15
–DB
8
DB
7
–DB
0
Undefined 0000 [S] – 2 [S] – 4 FFXX
16
AD
15
–AD
0
[S]
Undefined IPL PC
H
PS
H
AD
15
–AD
8
Next instruction
Undefined
(low-order)
PC
L
PS
L
AD
7
–AD
0
Next instructionPG
Note: When the stack area is in the internal area, above signals are not output to the external.
When the stack area is in the external area, AD
23
–AD
0
(A
23
–A
0
), DB
15
–DB
0
(D
15
–D
0
)
,
RD, BLW, and BHW are output to the external.
(f
sys
can always be output as φ
1
).
Vector address
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7.7.2 Push operation for registers
The push operation for registers performed in the INTACK sequence depends on whether the contents of
the stack pointer (S) at acceptance of an interrupt request are even or odd.
When the contents of the stack pointer (S) are even, the contents of the program counter (PC) and the
processor status register (PS) are simultaneously pushed in a unit of 16 bits. When the contents of the
stack pointer (S) are odd, each of PC and PS is pushed in a unit of 8 bits. Figure 7.7.3 shows the push
operation for registers.
In the INTACK sequence, only the contents of the program bank register (PG), program counter (PC), and
processor status register (PS) are pushed onto the stack area. Other necessary registers must be pushed
by software at the start of the interrupt routine.
By using the PSH instruction, all CPU registers, except the stack pointer (S), can be pushed with 1
instruction.
7.7 Sequence from acceptance of interrupt request until execution of interrupt routine
Fig. 7.7.3 Push operation for registers
Pushed in 3 times.
Pushed in a unit of 16 bits.
Pushed in a unit of 16 bits.
(1) When contents of stack pointer (S) are even
Program bank register (PG)
Address
[S] – 4 (even)
[S] – 3 (odd)
[S] – 2 (even)
[S] – 1 (odd)
[S] (even)
Order for push
[S] – 5 (odd)
Address
[S] – 4 (odd)
[S] – 3 (even)
[S] – 2 (odd)
[S] – 1 (even)
[S] (odd)
Pushed in a unit of 8 bits.
Order for push
Pushed in 5 times.
[S] – 5 (even)
Low-order byte of program counter (PCL)
High-order byte of program counter (PCH)
(2) When contents of stack pointer (S) are odd
Low-order byte of processor status register (PS
L
)
Program bank register (PG)
High-order byte of processor status register (PS
H
)
Low-order byte of program counter (PCL)
High-order byte of program counter (PCH)
[S] is the initial address that the stack pointer (S) indicates at acceptance of an interrupt request.
The S’s contents become “[S] – 5” after all of the above registers are pushed.
Low-order byte of processor status register (PS
L
)
High-order byte of processor status register (PS
H
)
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INTERRUPTS
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7.8 Return from interrupt routine
When the RTI instruction is executed at the end of the interrupt routine, the contents of the program bank
register (PG), program counter (PC), and processor status register (PS) which were pushed onto the stack
area just before the INTACK sequence are automatically pulled. After this, the control returns to the original
routine. And then, the suspended processing, which was in progress before acceptance of the interrupt
request, is resumed.
Before the RTI instruction is executed, registers which were pushed by software in the interrupt routine must
be pulled in the same data length and register length as those in pushing, using the PUL instruction, etc.
7.9 Multiple interrupts
Just after a branch is made to an interrupt routine, the following occur:
•Interrupt disable flag (I) = “1” (Interrupts are disabled.)
•Interrupt request bit of accepted interrupt = “0”
•Processor interrupt priority level (IPL) = Interrupt priority level of accepted interrupt
Accordingly, as long as the IPL remains unchanged, an interrupt request, whose priority level is higher than
that of the interrupt which is in progress, can be accepted by clearing the interrupt disable flag (I) to “0” in
an interrupt routine. In this way, multiple interrupts are processed.
Figure 7.9.1 shows the processing for multiple interrupts.
An interrupt request which has not been accepted because its priority level is lower is retained. When the
RTI instruction is executed, the interrupt priority level of the routine which was in progress just before
acceptance of an interrupt request is pulled into the IPL. Therefore, if the following relationship is satisfied
when interrupt priority level detection is performed next, the retained interrupt request will be accepted.
Retained interrupt request’s priority level > Processor interrupt priority level (IPL)
Note:When any of the following interrupt request is generated while an interrupt routine is in progress, this
interrupt request is accepted at once: zero division, watchdog timer, NMI, and address matching
detection.
7.8 Return from interrupt routine, 7.9 Multiple interrupts
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INTERRUPTS
7-18
7.9 Multiple interrupts
Fig. 7.9.1 Processing for multiple interrupts
Interrupt priority level = 2
Main routineReset
I = 1
IPL = 0
I = 0
Interrupt 1
I = 1
IPL = 3
I = 0
I = 1
IPL = 5
RTI
I = 0
IPL = 3
RTI
I = 0
IPL = 0
I = 1
IPL = 2
RTI
I = 0
IPL = 0
Interrupt 1
Interrupt priority level = 3
This request cannot be accepted
because its priority level is lower
than the interrupt 1’s one.
Interrupt request
generated Nesting
Time
: They are automatically executed.
: They must be set by software.
I : Interrupt disable flag
IPL : Processor interrupt priority level
Multiple interrupts
Interrupt 2
Interrupt priority level = 5
Interrupt 3
Interrupt 2
Interrupt 3
Interrupt 3
The instruction in the main routine is
not executed.
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INTERRUPTS
7-19
Level sense/Edge sense
select bit (bit 5 at addresses
7D16 to 7F16)
0
0
1
1
7.10 External interrupts
The external interrupts consist of NMI interrupts and INTi interrupts.
7.10.1 NMI interrupt
An NMI interrupt request occurs at the falling edge of an input signal to pin NMI. Regardless of flag I, the
NMI interrupt request is always accepted when this interrupt occurs, because the NMI interrupt is a non-
maskable interrupt. When the NMI interrupt request occurs again while the NMI interrupt processing is in
progress, this new NMI interrupt request is accepted, too (multiple interrupts).
There is the possibility of the many times NMI interrupt request occurrence when the noise or the chattering
is input to pin NMI. In this case, take care not to destroy the necessary data by the increment of the
multiple interrupt nesting and the stack area.
By reading out the NMI read bit (See Figure 7.10.3.), the state of pin NMI can be read out. Also, while the
level at pin RESET = “L” or after reset, pin NMI is pulled up. Therefore, it is not necessary to connect a
pullup resistor externally. When the pin NMI pullup select bit is set to “1” (See Figure 7.10.1.), the pullup
state is removed. The signal input to pin NMI requires the “L” level width of 250 ns or more, independent
of f(XIN).
7.10.2 INTi interrupt
An INTi (i = 0 to 4) interrupt request occurs by an input signal to pin INTi (i = 0 to 4) pin. Table 7.10.1 lists
the occurrence factor of the INTi interrupt request.
The each allocation of pins INT2 to INT4 can be changed by the pin INTk (k = 2 to 4) select bit. (See Figure
7.10.2.) When using pins P60/INT0 to P63/INT1, P64(P77)/INT2, P80(P74)/INT3, and P84(P75)/INT4 as input
pins of external interrupts, clear the port direction registers’ bits corresponding to the above pins. (See
Figure 7.10.4.) The signal input to pin INTi requires “H” or “L” level width of 250 ns or more, independent
of f(XIN) (Note). By reading out the INTi read bit (See Figure 7.10.3.), the state of pin INTi can be read out.
Note: Selection of the interrupt occurrence factor requires the following conditions:
• when an input signal’s falling edge or “L” level is selected, be sure that “L” level width 250 ns.
• when an input signal’s rising edge or “H” level is selected, be sure that “H” level width 250 ns.
7.10 External interrupts
Table 7.10.1 Occurrence factor of INTi interrupt request
Polarity select bit
(bit 4 at addresses 6E16,
6F16, 7D16 to 7F16)
0
1
0
1
0
1
The INTi interrupt request occurs by detecting the state of pin INTi all the time. Therefore, when the user
does not use an INTi interrupt, be sure to set the INTi interrupt’s priority level to 0.
INT0 to INT2
INT3, INT4
Occurrence factor of interrupt request
(An interrupt request occurs when the
input signal of pin INTi is as follows.)
Falling edge (Edge sense)
Rising edge (Edge sense)
“H” level (Level sense)
“L” level (Level sense)
Falling edge (Edge sense)
Rising edge (Edge sense)
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INTERRUPTS
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7.10 External interrupts
Fig. 7.10.1 Structure of port function control register
Notes 1: For the M37902FxM (power source voltage = 3.3 V±0.3 V), VIH = 0.5Vcc.
2: When MD1 = Vcc and MD0 = Vcc (flash memory parallel I/O mode), pins P4 4 to P4 7 and NMI are not pulled up, regardless
of these bits’ contents.
3: When MD1 = Vss and MD0 = Vcc (microprocessor mode), pin CS 0 (P44) is not pulled up regardless of this bit’s contents.
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
Port function control register (Address 9216)b7 b6 b5 b4 b3 b2 b1 b0
0
1
2
3
4
6, 5
7
Bit nameBit Function At reset R/W
Address/Port switch bits
Port P0 input level select bit
Pins P44–P47 pullup select bit
Fix these bits to “0.”
Pin NMI pullup select bit
0 0 0 : A0 to A23 (16 Mbytes)
0 0 1 : A0 to A21, P06, P07 (4 Mbytes)
0 1 0 : A0 to A19, P04 to P07 (1 Mbytes)
0 1 1 : A0 to A17, P02 to P07 (256 Kbytes)
1 0 0 : A0 to A15, P00 to P07 (64 Kbytes)
1 0 1 : Do not select.
1 1 0 : A0 to A11, P00 to P07, P114 to P117 (4 Kbytes)
1 1 1 : A0 to A7, P00 to P07, P110 to P117 (256 bytes)
b2 b1b0
0 : Pins P44–P47 are pulled up.
1 : Pins P44–P47 are not pulled up (Notes 2, 3).
0 : Pin NMI is pulled up.
1 : Pin NMI is not pulled up (Note 2).
0 : VIH = 0.7 Vcc, VIL = 0.2 Vcc
1 : VIH = 0.43 Vcc (Note 1), VIL = 0.16 Vcc
00
Fig. 7.10.2 Structure of external interrupt input control register
Notes 1: When using pin KIi, do not select timer As output pins and pulse output pins which are multiplexed with pin KIi. Refer to
“CHAPTER 9. TIMER A” and “CHAPTER 11. REAL-TIME OUTPUT.”
2: When allocating pin INT 2 to P77, do not use pin AN7/ADTRG. Additionally, clear the D-A1 output enable bit (bit 1 at address
9616) to “0” (output disabled).
3: When allocating pin INT3 to P80, clear the D-A2 output enable bit (bit 2 at address 9616) to “0” (output disabled).
When allocating pin INT3 to P74, do not use pin AN4.
4: When allocating pin INT4 to P75, do not use pin AN5.
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
External interrupt input control register (Address 9416)b7 b6 b5 b4 b3 b2 b1 b0
0
1
2
3
4
5
6
7
Bit nameBit Function At reset R/W
Key input interrupt select bit
Key input interrupt pin pullup
select bit
Key input interrupt pin select bits
Pin INT2 select bit
Pin INT3 select bit
Pin INT4 select bit
Fix this bit to “0.”
0 : Allocate pin INT2 to P64.
1 : Allocate pin INT2 to P77.(Note 2)
0 0 : Pins KI0 to KI3
0 1 : Pins KI0 to KI2
1 0 : Pins KI0 and KI1
1 1 : Pin KI0(Note 1)
0
0 : INT3 interrupt
1 : Key input interrupt
0 : Pins KI0 to KI3 are not pulled up.
1 : Pins KI0 to KI3 are pulled up.
b3 b2
0 : Allocate pin INT3 to P80.(Note 3)
1 : Allocate pin INT3 to P74.
0 : Allocate pin INT4 to P84.(Note 4)
1 : Allocate pin INT4 to P75.
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INTERRUPTS
7-21
Bit nameBit Function At reset R/W
7.10 External interrupts
0
1
2
3
4
5
7, 6
External interrupt input read register (Address 9516)
INT0 read out bit
INT1 read out bit
INT2 read out bit
INT3 read out bit (Note)
INT4 read out bit
NMI read out bit
The value is undefined at reading.
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
RO
RO
RO
RO
RO
RO
RO
b7 b6 b5 b4 b3 b2 b1 b0
Note : When the key input interrupt select bit (bit 0 at address 9416) = “1,” the input level at pin INT3 cannot be read out.
The input level at the corresponding pin is read out.
0 : “L” level
1 : “H” level
Fig. 7.10.3 Structure of external interrupt input read register
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INTERRUPTS
7-22
Pin INT
3
(Pin CTS
0
/RTS
0
/DA
2
) (Note 1)
Pin CTS0/CLK0
Pin RxD0
Pin TxD0
Pin INT3 (Pin CTS1/RTS1) (Note 1)
Pin CTS1/CLK1
Pin RxD1
Pin TxD1
Pin AN0
Pin AN1
Pin AN2
Pin AN3
Pin INT3 (Pin AN4)(Note 1)
Pin INT4 (Pin AN5)(Note 1)
Pin AN6/DA0
Pin INT
2
(Pin AN
7
/AD
TRG
/DA
1
) (Note 1)
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Fig. 7.10.4 Relationship between port P6/P7P8 direction register and external interrupt’s input pins
7.10 External interrupts
Corresponding pinBit Function At reset R/W
0
1
2
3
4
5
6
7
Port P6 direction register (Address 1016)b7 b6 b5 b4 b3 b2 b1 b0
Note: This applies when the pin INT2 select bit (bit 4 at address 9416) = “0.”
Pin TA4OUT
Pin TA4IN
Pin INT0
Pin INT1
Pin INT2 (Note)
Pin TB0IN
Pin TB1IN
Pin TB2IN
0 : Input mode
1 : Output mode
When using this pin as an external interrupt’s
input pin, be sure to clear the corresponding bit
to “0.”
Corresponding pinBit Function At reset R/W
0
1
2
3
4
5
6
7
Port P7 direction register (Address 1116)
b7 b6 b5 b4 b3 b2 b1 b0
Notes 1: This applies when the pin INTk (k = 2 to 4) select bit (bits 4 to 6 at address 9416) = “1.”
2: ( ) shows the I/O pin of the other internal peripheral devices which are multiplexed.
0 : Input mode
1 : Output mode
When using this pin as an external interrupt’s
input pin, be sure to clear the corresponding bit
to “0.”
Corresponding pinBit Function At reset R/W
0
1
2
3
4
5
6
7
Port P8 direction register (Address 1416)
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
b7 b6 b5 b4 b3 b2 b1 b0
Notes 1: This applies when the pins INT3 and INT4 select bit (bits 5, 6 at address 9416) = “0.”
2: ( ) shows the I/O pin of the other internal peripheral devices which are multiplexed.
0 : Input mode
1 : Output mode
When using this pin as an external interrupt’s
input pin, be sure to clear the corresponding bit
to “0.”
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INTERRUPTS
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7.10 External interrupts
7.10.3 Functions of INTi interrupt request bit
Figure 7.10.5 shows an INTi interrupt request.
(1) Functions when edge sense is selected (INT0 to INT4)
In this case, the interrupt request bit has the same function as that of an internal interrupt. That is,
when an interrupt request occurs, the interrupt request bit is set to “1” and retains this state until the
interrupt request is accepted. When this bit is cleared to “0” by software, the interrupt request is
cancelled; when this bit is set to “1” by software, the interrupt request can occur.
(2) Functions when level sense is selected (INT0 to INT2)
In this case, the interrupt request bit is ignored.
INTk (k = 0 to 2) interrupt requests continuously occur while the level at pin INTk is the valid level1;
when the level at pin INTk changes from the valid level to the invalid level2 before the corresponding
INTk interrupt request is accepted, this interrupt request is not retained. (See Figure 7.10.6.)
Valid level1: This means the level selected by the polarity select bit (bit 4 at addresses 7D16 to 7F16)
Invalid level2: This means the reversed level of “valid level”
Pins INT3 and INT4
Pins INT0 to INT2 Edge detection
circuit
Interrupt request
Data bus
Interrupt request bit “0”
“1”
Interrupt request
Edge detection
circuit Interrupt request
bit
Fig. 7.10.5 INTi Interrupt request
Fig. 7.10.6 Occurrence of INTk interrupt request when level sense is selected (k = 0 to 2)
When the level at pin INTk changes
to the invalid level before the INTk
interrupt request is accepted, this
interrupt request is not retained.
First interrupt routine
Level at pin INTk (k = 0 to 2) Valid
Invalid
Main routine
Interrupt request is accepted.
Return to main routine.
Second interrupt
routine
Third interrupt
routine
Main routine
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INTERRUPTS
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7.10 External interrupts
7.10.4 Switching of INTk to (k = 0 to 2) interrupt request occurrence factor
When the INTk interrupt request occurrence factor is switched in one of the following ways, there is a
possibility that the corresponding interrupt request bit is set to “1”:
• Switching the factor from the level sense to the edge sense
• Switching the polarity
Therefore, after this switching, make sure to clear the corresponding interrupt request bit to “0.” Figure
7.10.7 shows an example of the switching procedure for the INTk interrupt request’s occurrence factor.
Fig. 7.10.7 Example of switching procedure for INTk (k = 0 to 2) interrupt request occurrence factor
Set the interrupt priority level to one of
levels 1–7
or clear the interrupt disable flag (I) to “0.”
(INT
0
to INT
2
interrupt requests are acceptable.)
Set the interrupt priority level to one of
levels 1–7
or clear the interrupt disable flag (I) to “0.”
(INT
0
to INT
2
interrupt requests are acceptable.)
Clear the level sense/Edge sense select bit to “0.”
(Edge sense is selected.)
Clear the interrupt request bit to “0.”
Set the polarity select bit.
Clear the interrupt request bit to “0.”
(2) Switching the polarity
(1) Switching the factor from the level sense
to the edge sense
Set the interrupt priority level to 0
or set the interrupt disable flag (I) to “1.”
(INT
0
to INT
2
interrupts are disabled.)
Note: The above settings must be done separately.
Multiple settings must not be done at the same time, in other words, they must not be
done only by 1 instruction.
Set the interrupt priority level to 0
or set the interrupt disable flag (I) to “1.”
(INT
0
to INT
2
interrupts are disabled.)
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7-25
b4
0
1
0
1
Fig. 7.10.8 Program example to reserve time required for change of interrupt priority level
Table 7.10.2 Correspondence between number of instructions to be inserted in Figure 7.10.8 and
interrupt priority detection time select bits
[Precautions for interrupts]
[Precautions for interrupts]
1. In order to change the interrupt priority level select bits (bits 0 to 2 at addresses 6E16 to 7F16), 2 to 7
cycles of fsys are required after execution of a write instruction until change of the interrupt priority level.
Therefore, when the interrupt priority level of a certain interrupt source is repeatedly changed in a very
short time, which consists of a few instructions, it is necessary to reserve the time required for the change
by software. Figure 7.10.8 shows a program example to reserve the time required for the change. Note
that the time required for the change depends on the contents of the interrupt priority detection time
select bits (bits 4 and 5 at address 5E16). Table 7.10.2 lists the correspondence between the number of
instructions inserted in Figure 7.10.8 and the interrupt priority detection time select bits.
Interrupt priority detection time select bits (Note) Interrupt priority level
detection time
7 cycles of fsys
4 cycles of fsys
2 cycles of fsys
Do not select.
b5
0
0
1
1
Number of inserted
NOP instructions
7 or more
4 or more
2 or more
Note: We recommend [b5 = “1”, b4 = “0”].
2. When allocating pin INT2 to pin P77, be sure not use pin AN7/ADTRG. Additionally, be sure that the D-A1
output enabled bit (bit 1 at address 9616) = 0 (output disabled).
When allocating pin INT3 to pin P80, be sure that the D-A2 output enabled bit (bit 2 at address 9616) =
0 (output disabled).
When allocating pin INT3 to pin P74, be sure not to use pin AN4.
When allocating pin INT4 to pin P75, be sure not use pin AN5.
; Write instruction for the interrupt priority level select bits
; Inserted NOP instruction (Note)
;
;
; Write instruction for the interrupt priority level select bits
Note: Except a write instruction for address XX16, any instruction which has the same
cycles as the NOP instruction can also be inserted, instead of the NOP instruction.
For the number of inserted NOP instructions, see Table 7.10.2.
XX: any of 6C to 7F
:
MOVMB 00XXH, #0XH
NOP
NOP
NOP
MOVMB 00XXH, #0XH
:
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[Precautions for interrupts]
MEMORANDUM
CHAPTER 8CHAPTER 8
KEY INPUT INTERRUPT
8.1 Overview
8.2 Block description
8.3 Initial setting example for related
registers
KEY INPUT INTERRUPT
7902 Group User’s Manual
8-2
8.1 Overview
The key input interrupt function is used to generate an interrupt request at the falling edge of the signal
which is input to one pin, selected from four pins.
When terminating the stop or wait mode by using this function, the key-on wakeup function can be realized.
For details, refer to “CHAPTER 16. STOP AND WAIT MODES.”
8.1 Overview
The key input interrupt request is generated at the falling edge of the signal input to one pin selected from
the following: KI0 to KI3. By composing an external key matrix as shown in Figure 8.1.1, an interrupt request
can occur simply by pressing the key. Any of the KI0 to KI3 pins can be programmed as a key input interrupt
pin. Also, each pin programmed as a key input pin can be pulled up by software. The Interrupt vector
addresses and interrupt control register are common to the key input interrupt and the INT3 interrupt. When
the key input interrupt is selected, the INT3 interrupt cannot be used.
Fig. 8.1.1 Key matrix example using key input interrupt function
KI3
KI2
KI1
KI0
P67
P66
P65
P64
M37902 Key matrix
7902 Group User’s Manual 8-3
KEY INPUT INTERRUPT
8.2 Block description
Figure 8.2.1 shows the block diagram of the key input interrupt function.
Fig. 8.2.1 Block diagram of key input interrupt function
8.2 Block description
Pullup
transistor
Pullup
transistor
Pullup
transistor
P5
4
/KI
0
Port P5
6
direction register
Key input interrupt pin
pullup select bit
P5
6
/KI
2
KI
2
enable signal (Note)
INT
3
interrupt request
INT
3
interrupt control register
0
1
Key input interrupt pin
pullup select bit
P5
7
/KI
3
Port P5
7
direction register
KI
3
enable signal (Note)
P5
7
/KI
3
Interrupt control circuit
Note: KI
i
enable signal (i = 0 to 3) means a signal which becomes
“1” when the key input interrupt select bit = “1” and pin KI
i
is
selected by the key input interrupt pin select bits.
• Port P5j direction register : bit j (j = 4 to 7) at address D
16
• INT
3
interrupt control register : address 6E
16
• Key input interrupt select bit : bit 0 at address 94
16
Key input interrupt pin pullup select bit
: bit 1 at address 94
16
• Pin INT
3
select bit : bit 5 at address 94
16
0
1
P7
4
/(INT
3
)
P8
0
/INT
3
Pin INT
3
select bit Key input interrupt
select bit
Port P5
5
direction register
Key input interrupt pin
pullup select bit
P5
5
/KI
1
KI
1
enable signal (Note)
Port P5
4
direction register
Key input interrupt pin
pullup select bit
KI
0
enable signal (Note)
Pullup
transistor
KEY INPUT INTERRUPT
7902 Group User’s Manual
8-4
0
1
2
3
4
5
6
7
8.2.1 External interrupt input control register
Figure 8.2.2 shows the structure of the external interrupt input control register.
8.2 Block description
(1) Key input interrupt select bit (bit 0)
The interrupt vector addresses and interrupt control register are common to the key input interrupt and
the INT3 interrupt. When setting this bit to “1,” the key input interrupt is selected. When the key input
interrupt is selected, the INT3 interrupt cannot be used.
(2) Key input interrupt pin pullup select bit (bit 1)
When setting this bit to “1,” the KIi pin programmed as a key input interrupt pin is pulled up. When
composing a key matrix, it is unnecessary to connect the KIi pin with an external pullup transistor.
Also, when the KIi pin serves as a programmable I/O port pin, this pin is not pulled up regardless of
this bit’s contents.
(3) Key input interrupt pin select bit (bit 2, 3)
These bits are used to select pins to be used as key input interrupt pins. (These pins are selected
from the KI0 to KI3 pins.) Some pins not to be used as key input interrupt pins can serve as programmable
I/O port pins.
The signal input to the KIi pin requires the low-level pulse width of 250 ns or more, regardless of f(XIN).
Fig. 8.2.2 Structure of external interrupt input control register
Notes 1: When using pin KIi, do not select timer As output pins and pulse output pins which are multiplexed with pin KIi. Refer to
“CHAPTER 9. TIMER A” and “CHAPTER 11. REAL-TIME OUTPUT.”
2: When allocating pin INT 2 to P7 7, do not use pin AN7/ADTRG. Additionally, clear the D-A1 output enable bit (bit 1 at address
9616) to “0” (output disabled).
3: When allocating pin INT3 to P80, clear the D-A2 output enable bit (bit 2 at address 9616) to “0” (output disabled).
When allocating pin INT3 to P74, do not use pin AN4.
4: When allocating pin INT4 to P75, do not use pin AN5.
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
External interrupt input control register (Address 9416)b7 b6 b5 b4 b3 b2 b1 b0
Bit nameBit Function At reset R/W
Key input interrupt select bit
Key input interrupt pin pullup
select bit
Key input interrupt pin select bits
Pin INT2 select bit
Pin INT3 select bit
Pin INT4 select bit
Fix this bit to “0.”
0 : Allocate pin INT2 to P64.
1 : Allocate pin INT2 to P77.(Note 2)
0 0 : Pins KI0 to KI3
0 1 : Pins KI0 to KI2
1 0 : Pins KI0 and KI1
1 1 : Pin KI0(Note 1)
0
0 : INT3 interrupt
1 : Key input interrupt
0 : Pins KI0 to KI3 are not pulled up.
1 : Pins KI0 to KI3 are pulled up.
b3 b2
0 : Allocate pin INT3 to P80.(Note 3)
1 : Allocate pin INT3 to P74.
0 : Allocate pin INT4 to P84.(Note 4)
1 : Allocate pin INT4 to P75.
7902 Group User’s Manual 8-5
KEY INPUT INTERRUPT
0
1
2
3
4
7 to 5
8.2.2 INT3 interrupt control register
The interrupt vector addresses and interrupt control register are common to the key input interrupt and the
INT3 interrupt, so set as follows:
• Interrupt vector addresses: addresses FFD216 and FFD316 (INT3 interrupt’s vector addresses)
• Interrupt control register: address 6E16 (INT3 interrupt control register)
When the key input interrupt is selected, the INT3 interrupt cannot be used.
When a key input interrupt request is accepted, the microcomputer operates in the same way as when an
INT3 interrupt request is accepted. (Refer to “CHAPTER 7. INTERRUPTS.”)
Figure 8.2.3 shows the structure of the INT3 interrupt control register when selecting the key input interrupt
function. For details of each bit, refer to “CHAPTER 7. INTERRUPTS.”
8.2 Block description
Fig. 8.2.3 Structure of INT3 interrupt control register when selecting key input interrupt function
INT3 interrupt control register (Address 6E16)
Interrupt priority level select bits
Interrupt request bit
Polarity select bit
Nothing is assigned.
b7 b6 b5 b4 b3 b2 b1 b0
Note: When writing to this bit, use the MOVM (MOVMB) or STA (STAB, STAD) instruction.
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1b0
0 : No interrupt requested
1 : Interrupt requested
0 : The interrupt request bit is set to “1” at the falling
edge.
0
0
0
0
0
Undefined
RW
RW
RW
RW
(Note)
RW
Bit nameBit Function At reset R/W
0
KEY INPUT INTERRUPT
7902 Group User’s Manual
8-6
0
1
2
3
4
5
6
7
8.2 Block description
RW
RW
RW
RW
RW
RW
RW
RW
8.2.3 Port P5 direction register
The key input interrupt pins are multiplexed with port P5 pins. When using these pins as key input interrupt
pins, clear the corresponding bits of the port P5 direction register to “0” in order to set these port pins for
the input mode. Figure 8.2.4 shows the relationship between the port P5 direction register and the key input
interrupt pins.
By reading out bits 4 to 7 of the port P5 register (address B16) when the key input interrupt is selected,
the corresponding KIi pin’s state can be read out.
Fig. 8.2.4 Relationship between port P5 direction register and key input interrupt pins
Port P5 direction register (Address D16)
Pin TA0OUT/RTP00
Pin TA0IN/RTP01
Pin TA1OUT/RTP02
Pin TA1IN/RTP03
Pin KI0 (Pin TA2OUT/RTP10)
Pin KI1 (Pin TA2IN/RTP11)
Pin KI2 (Pin TA3OUT/RTP12)
Pin KI3 (Pin TA3IN/RTP13)
b7 b6 b5 b4 b3 b2 b1 b0
0 : Input mode
1 : Output mode
When using this pin as key input interrupt pin, be
sure to clear the corresponding bit to “0.”
0
0
0
0
0
0
0
0
Corresponding pinBit Functions At reset R/W
Note: ( ) shows the I/O pin of another internal peripheral device which is multiplexed.
7902 Group User’s Manual 8-7
KEY INPUT INTERRUPT
8.3 Initial setting example for related registers
Figure 8.3.1 shows an initial setting example for related registers of the key input interrupt function.
Fig. 8.3.1 Initial setting example for related registers of key input interrupt function
8.3 Initial setting example for related registers
AAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAA
b7 b0
Setting of interrupt priority level
INT3 interrupt control register (Address 6E16)
Interrupt priority level select bits
Set the level to one of 1 through 7 when using this interrupt.
Interrupt request bit
0
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
b7 b0
Setting of port P5 direction register
Port P5 direction register (Address D16)
Pin KI0
Pin KI1
Pin KI2
Pin KI3
When using this pin as key input
interrupt pin, be sure to clear the
corresponding bit to “0.”
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
b7 b0
0 : Pins KI0 to KI3 are not pulled up.
1 : Pins KI0 to KI3 are pulled up (Note).
Setting of key input interrupt
External interrupt input control register
(Address 9416)
Key input interrupt pin pullup select bit
0
Selection of key input
1
0 0 : Pins KI0 to KI3
0 1 : Pins KI0 to KI2
1 0 : Pins KI0 and KI1
1 1 : Pin KI0
Key input interrupt pin select bits
b3b2
Note: When the polarity select bit (bit 4 at
address 6E16) = “1,” be sure to set
this bit to “1.”
Polaruty select bit
0 : The interrupt request bit is set to “1” at falling edge.
0
KEY INPUT INTERRUPT
7902 Group User’s Manual
8-8
8.3 Initial setting example for related registers
MEMORANDUM
CHAPTER 9CHAPTER 9
TIMER A
9.1 Overview
9.2 Block description
9.3 Timer mode
[Precautions for timer mode]
9.4 Event counter mode
[Precautions for event counter mode]
9.5 One-shot pulse mode
[Precautions for one-shot pulse mode]
9.6 Pulse width modulation (PWM) mode
[Precautions for pulse width modulation
(PWM) mode]
TIMER A
7902 Group User’s Manual
9-2
9.1 Overview
Timer A consists of five counters, Timers A0 to A4, each equipped with a 16-bit reload function. Timers A0
to A4 operate independently of one other.
Timer Ai (i = 0 to 4) has four operating modes listed below. Except for the event counter mode, Timers A0
to A4 all have the same functions.
(1) Timer mode
In this mode, the timer counts an internally generated count source. Following functions can be used
in this mode:
• Gate function
• Pulse output function
(2) Event counter mode
In this mode, the timer counts an external signal. Following functions can be used in this mode:
• Pulse output function
• Two-phase pulse signal processing function (Timers A2, A3, and A4)
(3) One-shot pulse mode
In this mode, the timer outputs a pulse which has an arbitrary width once.
(4) Pulse width modulation (PWM) mode
In this mode, the timer outputs pulses which have an arbitrary width in succession. In this mode, the
timer serves as one of the following pulse width modulators:
• 16-bit pulse width modulator
• 8-bit pulse width modulator
9.1 Overview
TIMER A
7902 Group User’s Manual 9-3
9.2 Block description
Figure 9.2.1 shows the block diagram of timer A. Explanation of registers relevant to timer A is described
below.
9.2 Block description
Fig. 9.2.1 Block diagram of timer A
Data bus (odd)
Data bus (even)
f2
f16
f512
Count source
select bit
Timer mode
One-shot pulse mode
PWM mode
Polarity
switching
Timer mode
(Gate function)
Event counter mode
Trigger
Count start bit
Countdown
Up-down bit
(Low-order 8 bits) (High-order 8 bits)
Timer Ai reload register (16)
Timer Ai counter (16) Timer Ai
interrupt
request bit
Countup/Countdown
switching
(Always “countdown” except
for in the event counter
mode)
Toggle
F.F.
Pulse output
function select bit
TAiIN
TAiOUT
i = 0 to 4
f64
f1
f4096
Timer A clock division
select bits
TIMER A
7902 Group User’s Manual
9-4
Timer Ai register High-order byte Low-order byte
Timer A0 register Address 47
16
Address 46
16
Timer A1 register Address 49
16
Address 48
16
Timer A2 register Address 4B
16
Address 4A
16
Timer A3 register Address 4D
16
Address 4C
16
Timer A4 register Address 4F
16
Address 4E
16
9.2.1 Counter and Reload register (timer Ai register)
Each of timer Ai counter and reload register consists of 16 bits.
Countdown in the counter is performed each time the count source is input. In the event counter mode,
it can also function as an up-counter.
The reload register is used to store the initial value of the counter. When a counter underflow or overflow
occurs, the reload register’s contents are reloaded into the counter.
A value is set to the counter and reload register by writing the value to the timer Ai register. Table 9.2.1
lists the memory assignment of the timer Ai register.
The value written into the timer Ai register while counting is not in progress is set to the counter and reload
register. The value written into the timer Ai register while counting is in progress is set only to the reload
register. In this case, the reload register’s updated contents are transferred to the counter at the next
reload time. The value obtained when reading out the timer Ai register varies according to the operating
mode. Table 9.2.2 lists reading from and writing to the timer Ai register.
9.2 Block description
Table 9.2.2 Reading from and writing to timer Ai register
Write
<While counting>
Written only to reload register.
<While not counting>
Written to both of the counter
and reload register.
Operating mode
Timer mode
Event counter mode
One-shot pulse mode
Pulse width modulation (PWM) mode
Note: At reset, the contents of the timer Ai register
are undefined.
Notes 1: Also refer to sections “[Precautions for timer mode]” and “[Precautions for event counter
mode].”
2: When reading from and writing to the timer Ai register, perform it in a unit of 16 bits.
Read
Counter value is read out.
(Note 1)
Undefined value is read out.
Table 9.2.1 Memory assignment of timer Ai register
TIMER A
7902 Group User’s Manual 9-5
9.2.2 Timer A clock division select register
In the timer mode, one-shot pulse mode, and pulse width modulation (PWM) mode, the count source select
bits (bits 6 and 7 at addresses 5616 to 5A16), and timer A clock division select bits (bits 0 and 1 at addresses
4516) select the count source. Figure 9.2.2 shows the structures of the timer A clock division select register.
Table 9.2.3 lists the count source (in the timer mode, one-shot pulse mode, and pulse width modulation
(PWM) mode).
9.2 Block description
Fig. 9.2.2 Structures of timer A clock division select register
Table 9.2.3Count source (in timer mode, one-shot
pulse mode, and pulse width modulation
(PWM) mode)
Count source select
bits (bits 6 and 7 at
addresses 56
16
to 5A
16
)
00
01
10
11
00
f2
f16
f64
f512
01
f1
f16
f64
f4096
10
f1
f64
f512
f4096
11
Do not
select.
Timer A clock division select bits
(bits 0 and 1 at address 45
16
)
0
1
7 to 2
Timer A clock division select register (Address 4516)
Timer A clock division select bits
The value is “0” at reading.
0
0
0
RW
RW
b7 b6 b5 b4 b3 b2 b1 b0
See Table 9.2.3.
Bit nameBit Function At reset R/W
TIMER A
7902 Group User’s Manual
9-6
9.2.3 Count start register
This register is used to start and stop counting. One bit of this registar corresponds to one timer. (This is
the one-to-one relationship.) Figure 9.2.3 shows the structure of the count start register.
9.2 Block description
0
1
2
3
4
5
6
7
Count start register (Address 4016)
Timer A0 count start bit
Timer A1 count start bit
Timer A2 count start bit
Timer A3 count start bit
Timer A4 count start bit
Timer B0 count start bit
Timer B1 count start bit
Timer B2 count start bit
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
b7 b6 b5 b4 b3 b2 b1 b0
0 : Stop counting
1 : Start counting
Bit nameBit Function At reset R/W
Fig. 9.2.3 Structure of count start register
9.2.4 Timer Ai mode register
Figure 9.2.4 shows the structure of the timer Ai mode register. The operating mode select bits are used
to select the operating mode of timer Ai. Bits 2 to 7 have different functions according to the operating
mode. These bits are described in the paragraph of each operating mode.
Fig. 9.2.4 Structure of timer Ai mode register
Operating mode select bits
These bits have different functions according to the operating mode.
0
1
2
3
4
5
6
7
Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16)b7 b6 b5 b4 b3 b2 b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot pulse mode
1 1 : Pulse width modulation (PWM) mode.
b1 b0 0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Bit nameBit Function At reset R/W
TIMER A
7902 Group User’s Manual 9-7
9.2.5 Timer Ai interrupt control register
Figure 9.2.5 shows the structure of the timer Ai interrupt control register. For details about interrupts, refer
to “CHAPTER 7. INTERRUPTS.”
9.2 Block description
Fig. 9.2.5 Structure of timer Ai interrupt control register
(1) Interrupt priority level select bits (bits 2 to 0)
These bits are used to select a timer Ai interrupt’s priority level. When using timer Ai interrupts,
select the priority level from levels 1 through 7. When a timer Ai interrupt request occurs, its priority
level is compared with the processor interrupt priority level (IPL), so that the requested interrupt is
enabled only when its priority level is higher than the IPL. (However, this applies when the interrupt
disable flag (I) = “0.”) To disable timer Ai interrupts, set these bits to “0002” (level 0).
(2) Interrupt request bit (bit 3)
This bit is set to “1” when a timer Ai interrupt request occurs. This bit is automatically cleared to “0”
when the timer Ai interrupt request is accepted. This bit can be set to “1” or cleared to “0” by
software.
b7 b6 b5 b4 b3 b2 b1 b0
0
1
2
3
7 to 4
Interrupt priority level select bits
Interrupt request bit
Nothing is assigned.
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1b0
0 : No interrupt requested
1 : Interrupt requested
0
0
0
0
Undefined
RW
RW
RW
RW
(Note)
Bit nameBit Function At reset R/W
Timer Ai interrupt control register (i = 0 to 4) (Addresses 7516 to 7916)
Note: When writing to this bit, use the MOVM (MOVMB) instruction or STA (STAB, STAD) instruction.
TIMER A
7902 Group User’s Manual
9-8
RW
RW
RW
RW
RW
RW
RW
RW
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
Pin TA4OUT
Pin TA4IN
Pin INT0
Pin INT1
Pin INT2 (Note)
Pin TB0IN
Pin TB1IN
Pin TB2IN
9.2 Block description
9.2.6 Port P5 and port P6 direction registers
The I/O pins of timers A0 and A3 are multiplexed with port P5 pins, and the I/O pins of timer A4 are
multiplexed with port P6 pins. When using these pins as timer Ai’s input pins, clear the corresponding bits
of the port P5 and port P6 direction registers to “0” in order to set these port pins for the input mode. When
used as timer Ai’s output pins, these pins are forcibly set to the output pins of timer Ai regardless of the
direction registers’s contents. Figure 9.2.6 shows the relationship between the port P5 and port P6 direction
registers and the timer Ai’s I/O pins.
Fig. 9.2.6 Relationship between port P5 and port P6 direction registers and timer Ai’s I/O pins
0
1
2
3
4
5
6
7
Port P6 direction register (Address 1016)b7 b6 b5 b4 b3 b2 b1 b0
0 : Input mode
1 : Output mode
When using this pin as timer Ai’s input pin, be sure
to clear the corresponding bit to “0.”
RW
RW
RW
RW
RW
RW
RW
Corresponding pinBit Functions At reset R/W
Note: This applies when the pin INT2 select bit (bit 4 at address 9416) = “0.”
Port P5 direction register (Address D16)
Pin TA0OUT (Pin RTP00)
Pin TA0IN (Pin RTP01)
Pin TA1OUT (Pin RTP02)
Pin TA1IN (Pin RTP03)
Pin TA2OUT (Pin RTP10/KI0)
Pin TA2IN (Pin RTP11/KI1)
Pin TA3OUT (Pin RTP12/KI2)
Pin TA3IN (Pin RTP13/KI3)
b7 b6 b5 b4 b3 b2 b1 b0
0 : Input mode
1 : Output mode
When using this pin as timer Ai’s input pin, be sure
to clear the corresponding bit to “0.”
0
0
0
0
0
0
0
0
Corresponding pinBit Functions At reset R/W
Note: ( ) shows the I/O pin of another internal peripheral device which is multiplexed.
TIMER A
7902 Group User’s Manual 9-9
9.3 Timer mode
In this mode, the timer counts an internally generated count source. Table 9.3.1 lists the specifications of
the timer mode. Figure 9.3.1 shows the structures of the timer Ai register and timer Ai mode register in the
timer mode.
Table 9.3.1 Specifications of timer mode
Item
Count source fi
Count operation
Division ratio
Count start condition
Count stop condition
Interrupt request occurrence timing
TAiIN pin function
TAiOUT pin function
Read from timer Ai register
Write to timer Ai register
Specifications
f1, f2, f16, f64, f512, or f4096
• Countdown
• When a counter underflow occurs, reload register’s contents are
reloaded, and counting continues.
When count start bit is set to “1.”
When count start bit is cleared to “0.”
When a counter underflow occurs.
Programmable I/O port pin or gate input pin
Programmable I/O port pin or pulse output pin
Counter value can be read out.
While counting is stopped
When a value is written to the timer Ai register, it is written to both
reload register and counter.
While counting is in progress
When a value is written to the timer Ai register, it is written to only
reload register. (Transferred to the counter at the next reload timing.)
n : Timer Ai register setting value
1
(n + 1)
9.3 Timer mode
TIMER A
7902 Group User’s Manual
9-10
9.3 Timer mode
Fig. 9.3.1 Structures of timer Ai register and timer Ai mode register in timer mode
Timer A0 register (Addresses 4716, 4616)
Timer A1 register (Addresses 4916, 4816)
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
Undefined
15 to 0 These bits to can be set to “000016” to “FFFF16.”
Assuming that the set value = n, the counter divides the count source frequency by (n + 1).
When reading, the register indicates the counter value.
RW
b0b7b0b7
(b15) (b8)
Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16)
Operating mode select bits
Pulse output function select bit
Gate function select bits
Fix this bit to “0” in timer mode.
Count source select bits
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : Timer mode
b1 b0
00
0 0 : No gate function
0 1 : (TAiIN pin functions as a programmable I/O
port pin.)
1 0 : Gate function
(Counter counts only while TAiIN pin’s input
signal is at “L” level.)
1 1 : Gate function
(Counter counts only while TAiIN pin’s input
signal is at “H” level.)
b4 b3
0 : No pulse output
(TAiOUT pin functions as a programmable I/O port
pin.)
1 : Pulse output
(TAiOUT pin functions as a pulse output pin.) (Note)
0
0
0
0
0
0
0
0
See Table 9.2.3.
0
Note: Reading from or writing to this register must be performed in a unit of 16 bits.
Bit nameBit Function At reset R/W
Bit Function At reset R/W
Note: In order to make the TA2OUT and TA3OUT pins serve as pulse output pins, be sure not to select the key input
interrupt pins (KI0 and KI2 pins), which are multiplexed with the above pins. (Refer to “CHAPTER 8. KEY INPUT
INTERRUPT.”)
RW
RW
RW
RW
RW
RW
RW
RW
0
1
2
3
4
5
6
7
TIMER A
7902 Group User’s Manual 9-11
9.3.1 Setting for timer mode
Figure 9.3.2 shows an initial setting example for registers related to the timer mode.
Note that when using interrupts, set up to enable the interrupts. For details, refer to section “CHAPTER
7. INTERRUPTS.”
9.3 Timer mode
Fig. 9.3.2 Initial setting example for registers relevant to timer mode
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
Note: Counter divides the count source frequency by (n + 1).
AAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAA
b7 b0
Pulse output function select bit
0 : No pulse output
1 : Pulses output
00
Selecting timer mode and each function
Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16)
See Table 9.2.3.
0 0 :
0 1 :
b4 b3
Selection of timer mode
AAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAA
Setting division ratio
b7 b0
Can be set to “0000
16
” to “FFFF
16
” (n).
(b15) (b8) b7 b0
Timer A0 register (Addresses 4716, 4616)
Timer A1 register (Addresses 4916, 4816)
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
Gate function select bits
Count source select bits
No Gate function
0
AAAA
AAAA
AAAA
Count starts.
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
Setting count start bit to “1.”
b7 b0
Count start register (Address 4016)
Timer A0 count start bit
Timer A1 count start bit
Timer A2 count start bit
Timer A3 count start bit
Timer A4 count start bit
Setting interrupt priority level
b7 b0
Timer Ai interrupt control register (i = 0 to 4)
(Addresses 7516 to 7916)
Interrupt priority level select bits
When using interrupts, set these bits to one of
levels 1 to 7.
When disabling interrupts, set these bits to level 0.
Setting port P5 and port P6 direction registers
b7 b0
Port P5 direction register (Address D
16
)
Pin TA0
IN
Pin TA3
IN
When gate function is selected, clear the bit corresponding to the TAiIN
pin to “0.”
b7 b0
Port P6 direction register (Address 10
16
)
Pin TA1
IN
1 0 : Gate function (Counter counts only while TAi
IN
pin’s input signal level is “L.”)
1 1 : Gate function (Counter counts only while TAi
IN
pin’s input signal level is “H.”)
Pin TA1
IN
Pin TA2
IN
TIMER A
7902 Group User’s Manual
9-12
9.3 Timer mode
Fig. 9.3.3 Example of operation in timer mode (without pulse output and gate functions)
9.3.2 Operation in timer mode
When the count start bit is set to “1,” the counter starts counting of the count source.
When a counter underflow occurs, the reload register’s contents are reloaded, and counting continues.
The timer Ai interrupt request bit is set to “1” at the underflow in . The interrupt request bit remains
set to “1” until the interrupt request is accepted or until the interrupt request bit is cleared to “0” by
software.
Figure 9.3.3 shows an example of operation in the timer mode.
Stops counting.
Restarts counting.
FFFF16
n
000016
Time
Count start bit
Timer Ai interrupt
request bit
Counter contents (Hex.)
Cleared to “0” when interrupt request is
accepted or cleared by software.
Set to “1” by software.
Starts counting. (1 / fi) (n+1)
Cleared to “0” by software. Set to “1” by software.
fi : Frequency of count source
n : Reload register’s contents
TIMER A
7902 Group User’s Manual 9-13
9.3 Timer mode
9.3.3 Select function
The following describes the gate and pulse output functions.
(1) Gate function
The gate function is selected by setting the gate function select bits (bits 4 and 3 at addresses 5616
to 5A16) to “102” or “112.” The gate function makes it possible to start or stop counting depending on
the TAiIN pin’s input signal. Table 9.3.2 lists the count valid levels.
Figure 9.3.4 shows an example of operation with the gate function selected.
When selecting the gate function, set the port P5 and port P6 direction registers’ bits which correspond
to the TAiIN pin for the input mode. Additionally, make sure that the TAiIN pin’s input signal has a pulse
width equal to or more than two cycles of the count source.
Table 9.3.2 Count valid levels
Gate function select bits Count valid level (Duration while counter counts)
b4 b3
1 0 While TAiIN pin’s input signal level is at “L” level
1 1 While TAiIN pin’s input signal level is at “H” level
Note:The counter does not count while the TAiIN pin’s input signal is not at the count valid level.
Fig. 9.3.4 Example of operation with gate function selected
FFFF16
n
000016
Time
Starts counting.
Counter contents (Hex.)
Stops counting.
Set to “1” by software.
Count start bit
TAiIN pin’s
input signal
Count valid
level
Timer Ai interrupt
request bit
Cleared to “0” when
interrupt request is
accepted or cleared
by software.
The counter counts while the count start bit = “1” and the TAiIN pin’s input signal is at the count valid level.
The counter stops counting while the TAiIN pin’s input signal is not at the count valid level, and the counter
value is retained.
Invalid level
n : Reload register’s contents
TIMER A
7902 Group User’s Manual
9-14
(2) Pulse output function
The pulse output function is selected by setting the pulse output function select bit (bit 2 at addresses
5616 to 5A16) to “1.” When this function is selected, the TAiOUT pin is forcibly set for the pulse output
pin regardless of the corresponding bits of the port P5 and port P6 direction registers. The TAiOUT pin
outputs pulse of which polarity is inverted each time a counter underflow occurs.
When the count start bit (bits 0 to 4 at address 4016) is “0” (count stopped), the TAiOUT pin outputs
“L” level. Figure 9.3.5 shows an example of operation with the pulse output function selected.
Note that in order to make the TA2OUT and TA3OUT pins serve as pulse output pins, be sure not to
select the key input interrupt pins (KI0 and KI2 pins), which are multiplexed with the above pins.
(Refer to “CHAPTER 8. KEY INPUT INTERRUPT.”)
9.3 Timer mode
Fig. 9.3.5 Example of operation with pulse output function selected
FFFF
16
n
0000
16
Time
Count start bit
Timer Ai interrupt
request bit
Counter contents (Hex.)
Cleared to “0” when interrupt request is accepted or cleared by software.
Set to “1” by software.
Starts counting.
Pulse output from
TAi
OUT
pin
Set to “1” by software.
Cleared to “0” by software.
Starts counting.
Restarts
counting.
n : Reload register’s contents
TIMER A
7902 Group User’s Manual 9-15
[Precautions for timer mode]
[Precautions for timer mode]
1. By reading the timer Ai register, the counter value can be read out at any timing. However, if the timer
Ai register is read at the reload timing shown in Figure 9.3.6, the value “FFFF16” is read out. If reading
is performed in the period from when a value is set into the timer Ai register with the counter stopped
until the counter starts counting, the set value is correctly read out.
Fig. 9.3.6 Reading timer Ai register
2. In order to make the TA2OUT and TA3OUT pins serve as pulse output pins, be sure not to select the key
input interrupt pins (KI0 and KI2 pins), which are multiplexed with the above pins. (Refer to “CHAPTER
8. KEY INPUT INTERRUPT.”)
210n n – 1
Counter value
(Hex.)
21 0
FFFF n – 1
Read value
(Hex.)
Reload
Time
n : Reload register’s contents
TIMER A
7902 Group User’s Manual
9-16
Item
Count source
Count operation
Division ratio
Count start condition
Count stop condition
Interrupt request occurrence timing
TAiIN pin’s function
TAiOUT pin’s function
Read from timer Ai register
Write to timer Ai register
Specifications
External signal input to the TAiIN pin
The count source’s valid edge can be selected from the falling edge
and the rising edge by software.
Countup or countdown can be switched by external signal or software.
When a counter overflow or underflow occurs, reload register’s con-
tents are reloaded, and counting continues.
For countdown
For countup
When the count start bit is set to “1.”
When the count start bit is cleared to “0.”
When a counter overflow or underflow occurs.
Count source input
Programmable I/O port pin, pulse output pin, or countup/countdown
switch signal input pin
Counter value can be read out.
While counting is stopped
When a value is written to timer Ai register, it is written to both of
the reload register and counter.
While counting is in progress
When a value is written to timer Ai register, it is written only to the
reload register. (Transferred to the counter at the next reload timing.)
9.4 Event counter mode
In this mode, the timer counts an external signal. Tables 9.4.1 and 9.4.2 list the specifications of the event
counter mode. Figure 9.4.1 shows the structures of the timer Ai register and timer Ai mode register in the
event counter mode.
Table 9.4.1 Specifications of event counter mode (when not using two-phase pulse signal processing
function)
(n + 1)
1
(FFFF16 – n + 1)
1n: Timer Ai register’s set value
9.4 Event counter mode
TIMER A
7902 Group User’s Manual 9-17
Item
Count source
Count operation
Division ratio
Count start condition
Count stop condition
Interrupt request occurrence timing
TAj
IN
, TAj
OUT
(j = 2 to 4) pin function
Read from timer Aj register
Write to timer Aj register
Specifications
External signal (two-phase pulse) input to the TAjIN or TAjOUT pin (j =
2 to 4)
Countup or countdown can be switched by external signal (two-
phase pulse).
When a counter overflow or underflow occurs, reload register’s con-
tents are reloaded, and counting continues.
For countdown
For countup
When the count start bit is set to “1.”
When the count start bit is cleared to “0.”
When a counter overflow or underflow occurs.
Two-phase pulse input
Counter value can be read out by reading timer Aj register.
While counting is stopped
When a value is written to timer Aj register, it is written to both of
the reload register and counter.
While counting is in progress
When a value is written to timer Aj register, it is written only to the
reload register. (Transferred to the counter at the next reload timing.)
Table 9.4.2 Specifications of event counter mode (when using two-phase pulse signal processing
function in timers A2 and A4)
9.4 Event counter mode
(n + 1)
1
1n: Timer Aj register’s set value
(FFFF16 – n + 1)
TIMER A
7902 Group User’s Manual
9-18
X : It may be either “0” or “1.”
Note: In order to make the TA2OUT and TA3OUT pins serve as pulse output pins, be sure not to select the key input
interrupt pins (KI0 and KI2 pins), which are multiplexed with the above pins. (Refer to “CHAPTER 8. KEY INPUT
INTERRUPT.”)
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
15 to 0 RW
b0b7
Timer A0 register (Addresses 4716, 4616)
Timer A1 register (Addresses 4916, 4816)
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
b0b7
(b15) (b8)
0
1
2
3
4
5
6
7
Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16)
Operating mode select bits
Pulse output function select bit
Count polarity select bit
Up-down switching factor select
bit
Fix this bit to “0” in event counter mode.
These bits are invalid in event counter mode.
b7 b6 b5 b4 b3 b2 b1 b0
0 1 : Event counter mode
b1 b0
01
0 : No pulse output (TAiOUT pin functions as a
programmable I/O port pin.)
1 : Pulse output (TAiOUT pin functions as a pulse
output pin.) (Note)
XX0
0 : Counts at falling edge of external signal
1 : Counts at rising edge of external signal
0 : Contents of up-down register
1 : Input signal to TAiOUT pin
Bit Function At reset R/W
Bit nameBit Function At reset R/W
Undefined
These bits to can be set to “000016” to “FFFF16.”
Assuming that the set value = n, the counter divides the count source frequency by (n + 1)
during countdown, or by (FFFF16 – n + 1) during countup.
When reading, the register indicates the counter value.
Note: Reading from or writing to this register must be performed in a unit of 16 bits.
9.4 Event counter mode
Fig. 9.4.1 Structures of timer Ai register and timer Ai mode register in event counter mode
TIMER A
7902 Group User’s Manual 9-19
9.4 Event counter mode
9.4.1 Setting for event counter mode
Figures 9.4.2 and 9.4.3 show an initial setting example for registers related to the event counter mode.
Note that when using interrupts, set up to enable the interrupts. For details, refer to “CHAPTER 7.
INTERRUPTS.”
Fig. 9.4.2 Initial setting example for registers related to event counter mode (1)
The counter divides the count source frequency by (n + 1)
when counting down, or by (FFFF
16
– n + 1) when counting
up.
Continued to
Figure 9.4.3
on the next page
b7 b0
010
Selecting event counter mode and each function
Timer Ai mode register (i = 0 to 4)
(Addresses 56
16
to 5A
16
)
Pulse output function select bit
0: No pulse output
1: Pulse output
Count polarity select bit
0: Counts at falling edge of external signal.
1: Counts at rising edge of external signal.
Up-down switching factor select bit
0: Contents of up-down register
1: Input signal to TAi
OUT
pin
X: It may be either “0” or “1.”
Selection of event counter mode
Setting divide ratio
b7 b0
Can be set to
0000
16
to
FFFF
16
(n).
(b15) (b8) b7 b0
Timer A0 register (Addresses 47
16
, 46
16
)
Timer A1 register (Addresses 49
16
, 48
16
)
Timer A2 register (Addresses 4B
16
, 4A
16
)
Timer A3 register (Addresses 4D
16
, 4C
16
)
Timer A4 register (Addresses 4F
16
, 4E
16
)
✕✕
b7 b0
Setting up–down register
Up–down register (Address 44
16
)
Timer A0 up–down bit
Timer A1 up–down bit
Timer A2 up–down bit
Timer A3 up–down bit
Timer A4 up–down bit
Timer A2 two–phase pulse signal processing select bit
Timer A3 two–phase pulse signal processing select bit
Timer A4 two–phase pulse signal processing select bit
Set to the corresponding up–down bit when the contents of
the up-down register are selected as the up-down switching
factor.
Set the corresponding bit to “1” when the two–phase pulse
signal processing function is selected for timers A2 to A4.
0: Countdown
1: Countup
0: Two–phase pulse signal processing
function disabled
1: Two–phase pulse signal processing
function enabled
TIMER A
7902 Group User’s Manual
9-20
9.4 Event counter mode
Fig. 9.4.3 Initial setting example for registers relevant to event counter mode (2)
AAAAAA
Setting the count start bit to “1”
b7 b0
Count start register
(Address 40
16
)
Timer A0 count start bit
Timer A1 count start bit
Timer A2 count start bit
Timer A3 count start bit
Timer A4 count start bit
AAA
AAA
AAA
Count starts.
From preceding
Figure 9.4.2
Setting port P5 and port P6 direction registers
b7 b0
Port P5 direction register (Address D
16
)
Pin TA0
IN
Pin TA3
OUT
Pin TA3
IN
Clear the bit corresponding to the TAi
IN
pin to “0.”
When selecting the TAi
OUT
pin's input signal as up-down switching factor, clear
the bit corresponding to the TAi
OUT
pin to “0.”
When selecting the two–phase pulse signal processing function, clear the bit
corresponding to the TAj
OUT
(j = 2 to 4) pin to “0.”
b7 b0
Port P6 direction register (Address 10
16
)
Pin TA4
OUT
Pin TA4
IN
Pin TA0
OUT
Setting interrupt priority level
b7 b0
Timer Ai interrupt control register (i = 0 to 4)
(Addresses 75
16
to 79
16
)
Interrupt priority level select bits
When using interrupts, set these bits to one
of levels 1 to 7.
When disabling interrupts, set these bits to
level 0.
Pin TA1
OUT
Pin TA1
IN
Pin TA2
OUT
Pin TA2
IN
TIMER A
7902 Group User’s Manual 9-21
9.4.2 Operation in event counter mode
When the count start bit is set to “1,” the counter starts counting of the count source’s valid edge.
When a counter underflow or overflow occurs, the reload register’s contents are reloaded, and counting
continues.
The timer Ai interrupt request bit is set to “1” at the underflow or overflow in .
The interrupt request bit remains set to “1” until the interrupt request is accepted or until the interrupt
request bit is cleared to “0” by software.
Figure 9.4.4 shows an example of operation in the event counter mode.
9.4 Event counter mode
Fig. 9.4.4 Example of operation in event counter mode (without pulse output and two-phase pulse
signal processing functions)
Timer Ai interrupt
request bit
FFFF
16
n
0000
16
Time
Count start bit
Counter contents (Hex.)
Cleared to “0” when interrupt request is accepted or cleared by software.
Set to “1” by software.
Starts counting.
Up-down bit
Note: The above applies when the up-down bit’s contents are selected as the up-down switching factor (i.e., up-down
switching factor select bit = “0” ).
Set to “1” by software.
n : Reload register’s contents
TIMER A
7902 Group User’s Manual
9-22
9.4 Event counter mode
9.4.3 Switching between countup and countdown
Figure 9.4.5 shows structure of the up-down register.
The up-down register or the input signal from the TAiOUT pin is used to switch countup from and to
countdown. This switching is performed by the up-down bit when the up-down switching factor select bit
(bit 4 at addresses 5616 to 5A16) is “0,” and by the input signal from the TAiOUT pin when the up-down
switching factor select bit is “1.”
When the switching between countup and countdown is set while counting is in progress, this switching is
actually performed when the count source’s next valid edge is input.
(1) Switching by up-down bit
Countdown is performed when the up-down bit is “0,” and countup is performed when the up-down
bit is “1.” Figure 9.4.5 shows the structure of the up-down register.
(2) Switching by TAiOUT pin’s input signal
Countdown is performed when the TAiOUT pin’s input signal is at “L” level, and countup is performed
when the TAiOUT pin’s input signal is at “H” level.
When using the TAiOUT pin’s input signal to switch countup from and to countdown, set the port P5
and port P6 direction registers’ bits which correspond to the TAiOUT pin for the input mode.
Fig. 9.4.5 Structure of up-down register
b7 b6 b5 b4 b3 b2 b1 b0
0
1
2
3
4
5
6
7
Up-down register (Address 4416)
Timer A0 up-down bit
Timer A1 up-down bit
Timer A2 up-down bit
Timer A3 up-down bit
Timer A4 up-down bit
Timer A2 two-phase pulse signal
processing select bit
Timer A3 two-phase pulse signal
processing select bit
Timer A4 two-phase pulse signal
processing select bit
0 : Countdown
1 : Countup
This function is valid when the contents of the up-
down register is selected as the up-down switching
factor.
0 : Two-phase pulse signal processing function disabled
1 : Two-phase pulse signal processing function enabled
When not using the two-phase pulse signal processing
function, clear the bit to “0.”
The value is “0” at reading.
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
WO
(Note)
WO
(Note)
WO
(Note)
Note: Use the MOVM(MOVMB) or STA(STAB, STAD) instruction for writing to bits 5 to 7.
Bit nameBit Function At reset R/W
TIMER A
7902 Group User’s Manual 9-23
9.4 Event counter mode
9.4.4 Selectable functions
The following describes the selectable pulse output, and two-phase pulse signal processing functions.
(1) Pulse output function
The pulse output function is selected by setting the pulse output function select bit (bit 2 at addresses
5616 to 5A16) to “1.” When this function is selected, the TAiOUT pin is forcibly set for the pulse output
pin regardless of the corresponding bits of the port P5 and port P6 direction registers. The TAiOUT pin
outputs pulses of which polarity is inverted each time a counter underflow or overflow occurs. (Refer
to Figure 9.3.5).
When the count start bit (address 4016) is “0” (count stopped), the TAiOUT pin outputs “L” level.
In order to make the TA2OUT and TA3OUT pins serve as pulse output pins, be sure not to select the
key input interrupt pins (KI0 and KI2 pins), which are multiplexed with the above pins. (Refer to
“CHAPTER 8. KEY INPUT INTERRUPT.”)
(2) Two-phase pulse signal processing function (Timers A2 to A4)
For timers A2 to A4, the two-phase pulse signal processing function is selected by setting the two-
phase pulse signal processing select bits (bits 5 to 7 at address 4416) to “1.” (See Figure 9.4.5.)
Figure 9.4.6 shows the timer A2/A3/A4 mode registers when the two-phase pulse signal processing
function is selected.
For timers with two-phase pulse signal processing function selected, the timer counts two kinds of
pulses of which phases differ by 90 degrees. There are two types of the two-phase pulse signal
processing: normal processing and quadruple processing. In timer A2 and A3, normal processing is
performed; in timer A4, quadruple processing is performed.
For the port P5 and P6 direction registers’ bits corresponding to the pins used for two-phase pulse
input, be sure to set these bits for the input mode.
Fig. 9.4.6 Timer A2/A3/A4 mode registers when two-phase pulse signal processing function is selected
100001
Timer A2 mode register (Address 58
16
)
Timer A3 mode register (Address 59
16
)
Timer A4 mode register (Address 5A
16
)
b7 b6 b5 b4 b3 b2 b1 b0
: It may be either “0” or “1.”
✕✕
TIMER A
7902 Group User’s Manual
9-24
Input signal to TA4OUT pin
<Normal processing>
Countup is performed at the rising edges
input to the TAkIN pin when the TAkIN and
TAkOUT have the relationship that the TAkIN
pin’s input signal goes from “L” to “H” while
the TAkOUT (k = 2 and 3) pin’s input signal
is at “H” level.
Countdown is performed at the falling edges
input to the TAkIN pin when the TAkIN and
TAkOUT have the relationship that the TAkIN
pin’s input signal goes from “H” to “L” while
the TAkOUT pin’s input signal is “H.” (See
Figure 9.4.7.)
<Quadruple processing>
Countup is performed at all rising and fall-
ing edges input to the TA4OUT and TA4IN
pins when the TAkIN and TAkOUT have the
relationship that the TA4IN pin’s input signal
level goes from “L” to “H” while the TA4OUT
pin’s input signal is at “H” level.
Countdown is performed at all rising and
falling edges input to the TA4OUT and TA4IN
pins when the TAkIN and TAkOUT have the
relationship that the TA4IN pin’s input signal
level goes from “H” to “L” while the TA4OUT
pin’s input signal is at “H” level. (See Figure
9.4.8.)
Table 9.4.3 lists the input signals on the
TA4OUT and TA4IN pins when the quadruple
processing is selected.
Fig. 9.4.7 Normal processing
Table 9.4.3 TA4OUT and TA4IN pin’s input signals when quadruple processing is selected
“H” level
“L” level
Rising edge
Falling edge
“H” level
“L” level
Rising edge
Falling edge
Rising edge
Falling edge
“L” level
“H” level
Falling edge
Rising edge
“H” level
“L” level
Countup
Countdown
Fig. 9.4.8 Quadruple processing
Input signal to TA4IN pin
9.4 Event counter mode
TA4
OUT
TA4
IN
“H”
“H”
“L”
“L”
+1
+1
+1
+1
+1
+1
+1
+1
+1
+1
Counted up at all edges.
–1
–1
–1
–1
–1
–1
–1
–1
–1
–1
Counted down at all edges.
Counted up at all edges. Counted down at all edges.
TAk
OUT
TAk
IN
(k=2, 3)
“H”
“H”
“L”
+1 +1 +1 –1 –1 –1
“L”
Countup Countup Countup Countdown Countdown Countdown
TIMER A
7902 Group User’s Manual 9-25
[Precautions for event counter mode]
1. While counting is in progress, by reading the timer Ai register, the counter value can be read out at any
timing. However, if the timer Ai register is read at the reload timing shown in Figure 9.4.9, the value
“FFFF16” (at an underflow) or “000016” (at the overflow) is read out. If reading is performed in the period
from when a value is set into the timer Ai register with the counter stopped until the counter starts
counting, the set value is correctly read out.
[Precautions for event counter mode]
Fig. 9.4.9 Reading timer Ai register
2. The TAiOUT pin is used for all functions listed below. Accordingly, only one of these functions can be
selected for each timer.
Switching between countup and countdown by TAiOUT pin’s input signal
Pulse output function
Two-phase pulse signal processing function (Timers A2 to A4)
3. In order to make the TA2OUT and TA3OUT pins serve as pulse output pins, be sure not to select the key
input interrupt pins (KI0 and KI2 pins), which are multiplexed with the above pins. (Refer to “CHAPTER
8. KEY INPUT INTERRUPT.”)
210nn – 1
Counter value
(Hex.)
210
FFFF n – 1
Read value
(Hex.)
Reload
Time
n : reload register’s contents
(1) For countdown
FFFD FFFE FFFF nn + 1
FFFD FFFE FFFF 0000 n + 1
(2) For countup
Counter value
(Hex.)
Read value
(Hex.)
Reload
Time
n : reload register’s contents
TIMER A
7902 Group User’s Manual
9-26
Item
Count source fi
Count operation
Output pulse width (“H”)
Count start condition
Count stop condition
Interrupt request occurrence timing
TAiIN pin’s function
TAiOUT pin’s function
Read from timer Ai register
Write to timer Ai register
Specifications
f1, f2, f16, f64, f512, or f4096
Countdown
When the counter value becomes “000016,” reload register’s con-
tents are reloaded, and counting stops.
If a trigger occurs during counting, reload register’s contents are
reloaded, and counting continues.
When a trigger occurs. (Note)
Internal or external trigger can be selected by software.
When the counter value becomes “000016
When the count start bit is cleared to “0”
When counting stops.
Programmable I/O port pin or trigger input pin
One-shot pulse output
An undefined value is read out.
While counting is stopped
When a value is written to timer Ai register, it is written to both of
the reload register and counter.
While counting is in progress
When a value is written to timer Ai register, it is written only to the
reload register. (Transferred to counter at the next reload timing.)
9.5 One-shot pulse mode
In this mode, the timer outputs a pulse which has an arbitrary width once. When a trigger occurs, the timer
outputs “H” level from the TAiOUT pin for an arbitrary time. Table 9.5.1 lists the specifications of the one-shot
pulse mode. Figure 9.5.1 shows the structures of the timer Ai register and timer Ai mode register in the one-
shot pulse mode.
Table 9.5.1 Specifications of one-shot pulse mode
9.5 One-shot pulse mode
n
fi[s] n : Timer Ai register’s set value
Note:The trigger is generated with the count start bit = “1.”
TIMER A
7902 Group User’s Manual 9-27
RW
RW
RW
RW
RW
RW
RW
RW
0
1
2
3
4
5
6
7
Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16)
Operating mode select bits
Fix this bit to “1” in one-shot pulse mode.
Trigger select bits
Fix this bit to “0” in one-shot pulse mode.
Count source select bits
b7 b6 b5 b4 b3 b2 b1 b0
1 0 : One-shot pulse mode
b1 b0
10
0
0 0 : Writing “1” to one-shot start bit
0 1 : (TAiIN pin functions as a programmable I/O
port pin.)
1 0 : Falling edge of TAiIN pin’s input signal
1 1 : Rising edge of TAiIN pin’s input signal
b4 b3
1
0
0
0
0
0
0
0
0
See Table 9.2.3.
Undefined
15 to 0 These bits can be set to “000016” to “FFFF16.”
Assuming that the set value = n, the “H” level width of the one-shot pulse which is
output from the TAiOUT pin is expressed as follows :
WO
b0b7
Timer A0 register (Addresses 4716, 4616)
Timer A1 register (Addresses 4916, 4816)
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
b0b7
(b15) (b8)
fi: Frequency of count source
Note: Use the MOVM or STA(STAD) instruction for writing to this register.
Writing to this register must be performed in a unit of 16 bits.
n
fi.
Bit Function At reset R/W
Bit nameBit Function At reset R/W
Fig. 9.5.1 Structures of timer Ai register and timer Ai mode register in one-shot pulse mode
9.5 One-shot pulse mode
TIMER A
7902 Group User’s Manual
9-28
9.5.1 Setting for one-shot pulse mode
Figures 9.5.2 and 9.5.3 show an initial setting example for registers related to the one-shot pulse mode.
Note that when using interrupts, set up to enable the interrupts. For details, refer to “CHAPTER 7.
INTERRUPTS.”
9.5 One-shot pulse mode
Fig. 9.5.2 Initial setting example for registers related to one-shot pulse mode (1)
Continue to Figure 9.5.3.
Setting interrupt priority level
b7 b0 Timer Ai interrupt control register (i = 0 to 4)
(Addresses 7516 to 7916)
Interrupt priority level select bits
When using interrupts, set these bits to one of levels 1 to 7.
When disabling interrupts, set these bits to level 0.
b7 b0
100
Selecting one-shot pulse mode and each function
Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16)
1
Trigger select bits
0 0 :
0 1 :
1 0 : Falling of TAiIN pin’s input signal: External trigger
1 1 : Rising of TAiIN pin’s input signal: External trigger
b4 b3
Count source select bits
See Table 9.2.3.
Selection of one-shot pulse mode
Setting “H” level width of one-shot pulse
b7 b0
Can be set to “000016” to “FFFF16” (n).
(b15) (b8) b7 b0 Timer A0 register (Addresses 4716, 4616)
Timer A1 register (Addresses 4916, 4816)
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
“H” level width =
fi = Frequency of count source
However, if n = “000016”, the counter does not operate and the
TAiOUT pin outputs “L” level. At this time, no timer Ai interrupt
request occurs.
Writing “1” to one-shot start bit: Internal trigger
fi
Note. n
TIMER A
7902 Group User’s Manual 9-29
9.5 One-shot pulse mode
Fig. 9.5.3 Initial setting example for registers related to one-shot pulse mode (2)
AAA
AAA
AAA
AAA
Count starts.
Trigger generated
Trigger input to TAiIN pin
When internal trigger
is selected
When external trigger
is selected
From preceding Figure 9.5.2
b7 b0
One-shot start register
(Address 4216)
Setting one-shot start bit to “1”
Timer A0 one-shot start bit
Timer A1 one-shot start bit
Timer A2 one-shot start bit
Timer A3 one-shot start bit
Timer A4 one-shot start bit
Setting count start bit to “1”
b7 b0
Timer A0 count start bit
Timer A1 count start bit
Timer A2 count start bit
Timer A3 count start bit
Timer A4 count start bit
Count start register (Address 4016)
b7 b0
Port P5 direction register
(Address D16)
Setting port P5 and port P6 direction registers
Pin TA0
IN
Pin TA3
IN
Setting count start bit to “1”
b7 b0
Timer A0 count start bit
Timer A1 count start bit
Timer A2 count start bit
Timer A3 count start bit
Timer A4 count start bit
Count start register (Address 4016)
Port P6 direction register
(Address 1016)
b7 b0
Pin TA1
IN
Clear the corresponding bit to “0.”
Pin TA1
IN
Pin TA2
IN
TIMER A
7902 Group User’s Manual
9-30
9.5.2 Trigger
The counter is enabled for counting when the count start bit (address 4016) has been set to “1.” The counter
starts counting when a trigger is generated after counting has been enabled. An internal or external trigger
can be selected as that trigger.
An internal trigger is selected when the trigger select bits (bits 4 and 3 at addresses 5616 to 5A16) are “002
or “012”; an external trigger is selected when the bits are “102” or “112.”
If a trigger is generated during counting, the reload register’s contents are reloaded and the counter
continues counting. If a trigger generated during counting, make sure that a certain time which is equivalent
to one cycle of the timer’s count source or more has passed between the previously trigger occurrence and
a new trigger occurrence.
(1) When selecting internal trigger
A trigger is generated when writing “1” to the one-shot start bit (bits 0 to 4 at address 4216). Figure
9.5.4 shows the structure of the one-shot start register.
(2) When selecting external trigger
A trigger is generated at the falling edge of the TAiIN pin’s input signal when bit 3 at addresses 5616
to 5A16 is “0,” or at its rising edge when bit 3 is “1.”
When using an external trigger, set the port P5 and port P6 direction registers’ bits which correspond
to the TAiIN pins for the input mode.
9.5 One-shot pulse mode
Fig. 9.5.4 Structure of one-shot start register
WO
WO
WO
WO
WO
RW
0
0
0
0
0
Undefined
0
0
1
2
3
4
6, 5
7
One-shot start register (Address 4216)b7 b6 b5 b4 b3 b2 b1 b0
1 : Start outputting one-shot pulse.
(Valid when an internal trigger is selected.)
The value is “0” at reading.
0
Timer A0 one-shot start bit
Timer A1 one-shot start bit
Timer A2 one-shot start bit
Timer A3 one-shot start bit
Timer A4 one-shot start bit
Nothing is assigned.
Fix this bit to “0.”
Bit nameBit Function At reset R/W
TIMER A
7902 Group User’s Manual 9-31
9.5 One-shot pulse mode
9.5.3 Operation in one-shot pulse mode
When the one-shot pulse mode is selected with the operating mode select bits, the TAiOUT pin outputs
“L” level.
When the count start bit is set to “1,” the counter is enabled for counting. After that, counting starts when
a trigger is generated.
When the counter starts counting, the TAiOUT pin outputs “H” level. (When a value of “000016” is set to
the timer Ai register, the counter stops operating, the output level at pin TAiOUT remains “L,” and no timer
Ai interrupt request does not occur.)
When the counter value becomes “000016,” the output from the TAiOUT pin becomes “L” level.
Additionally, the reload register’s contents are reloaded and the counter stops counting there.
Simultaneously with , the timer Ai interrupt request bit is set to “1.”
This interrupt request bit remains set to “1” until the interrupt request is accepted or until the interrupt
request bit is cleared to “0” by software.
Figure 9.5.5 shows an example of operation in the one-shot pulse mode.
When a trigger is generated after above, the counter and TAiOUT pin perform the same operations
beginning from again. Furthermore, if a trigger is generated during counting, the counter performs
countdown once after this new trigger is generated, and then, it continues counting with the reload register’s
contents reloaded. If generating a trigger during counting, make sure that a certain time which is equivalent
to one cycle of the timer’s count source or more has passed between the previously trigger occurrence and
a new trigger occurrence.
The one-shot pulse output from the TAiOUT pin can be disabled by clearing the timer Ai mode register’s bit
2 to “0.” Accordingly, timer Ai can also be used as an internal one-shot timer that does not perform the
pulse output. In this case, the TAiOUT pin functions as a programmable I/O port pin.
In order to make the TA2OUT and TA3OUT pins serve as pulse output pins, be sure not to select the key input
interrupt pins (KI0 and KI2 pins), which are multiplexed with the above pins. (Refer to “CHAPTER 8. KEY
INPUT INTERRUPT.”)
TIMER A
7902 Group User’s Manual
9-32
9.5 One-shot pulse mode
Fig. 9.5.5 Example of operation in one-shot pulse mode (selecting external trigger)
Stops
counting. Starts counting.
FFFF
16
n
0001
16
Time
Count start bit
Timer Ai interrupt
request bit
Counter contents (Hex.)
n = Reload register’s contents
Cleared to “0” when interrupt request is accepted
or cleared by software.
Set to “1” by software.
Starts counting.
TAi
IN
pin
input signal
One-shot pulse
output from
TAi
OUT
pin
Trigger during counting
(1 / f
i
) (n)
Note: The above applies when an external trigger (rising edge of TAi
IN
pin’s input signal) is selected.
(1 / f
i
) (n+1)
When the count start bit = “0” (counting stopped), the TAi
OUT
pin outputs “L” level.
When a trigger is generated during counting, the counter counts the count source (n + 1) times after a new trigger is generated.
f
i
: Frequency of count source
Stops counting.
Reloaded Reloaded
n : Reload register’s contents
TIMER A
7902 Group User’s Manual 9-33
[Precautions for one-shot pulse mode]
[Precautions for one-shot pulse mode]
1. If the count start bit is cleared to “0” during counting, the counter becomes as follows:
•The counter stops counting, and the reload register’s contents are reloaded into the counter.
•The TAiOUT pin’s output level becomes “L.”
•The timer Ai interrupt request bit is set to “1.”
2. A one-shot pulse is output synchronously with an internally generated count source. Accordingly, when
selecting an external trigger, there will be a delay equivalent to one cycle of the count source at
maximum, in a period from when a trigger is input to the TAiIN pin until a one-shot pulse is output.
Fig. 9.5.6 Output delay in one-shot pulse output
3. When the timer’s operating mode has been set by one of the following procedures, the timer Ai interrupt
request bit will be set to “1.”
When the one-shot pulse mode is selected after reset
When the operating mode is switched from the timer mode to the one-shot pulse mode
When the operating mode is switched from the event counter mode to the one-shot pulse mode
Accordingly, when using a timer Ai interrupt (interrupt request bit), be sure to clear the timer Ai interrupt
request bit to “0” after the above setting.
4. In order to make the TA2OUT and TA3OUT pins serve as pulse output pins, be sure not to select the key
input interrupt pins (KI0 and KI2 pins), which are multiplexed with the above pins. (Refer to “CHAPTER
8. KEY INPUT INTERRUPT.”)
Note: The above applies when an external trigger (falling edge of TAiIN pin’s input signal) is selected.
TAiIN pin’s
input signal
Count
source
Trigger input
Starts outputting of one-shot pulse
One-shot pulse
output from
TAiOUT pin
TIMER A
7902 Group User’s Manual
9-34
9.6 Pulse width modulation (PWM) mode
9.6 Pulse width modulation (PWM) mode
In this mode, the timer continuously outputs pulses which have an arbitrary width. Table 9.6.1 lists the
specifications of the PWM mode. Figure 9.6.1 shows the structures of the timer Ai register and timer Ai
mode register in the PWM mode.
Table 9.6.1 Specifications of PWM mode
Item
Count source fi
Count operation
PWM period/“H” level width
Count start condition
Count stop condition
Interrupt request occurrence timing
TAiIN pin’s function
TAiOUT pin’s function
Read from timer Ai register
Write to timer Ai register
Specifications
f1, f2, f16, f64, f512, or f4096
Countdown (operating as an 8-bit or 16-bit pulse width modulator)
Reload register’s contents are reloaded at rising edge of PWM pulse,
and counting continues.
A trigger generated during counting does not affect the counting.
<16-bit pulse width modulator>
<8-bit pulse width modulator>
When a trigger is generated. (Note)
Internal or external trigger can be selected by software.
When the count start bit is cleared to “0.”
At falling edge of PWM pulse
Programmable I/O port pin or trigger input pin
PWM pulse output
An undefined value is read out.
While counting is stopped
When a value is written to the timer Ai register, it is written to both
of the reload register and counter.
While counting is in progress
When a value is written to the timer Ai register, it is written only to
the reload register. (Transferred to the counter at the next reload
time.)
Period = (216–1)
fi[s]
“H” level width = [s]
Period = (m + 1)(28–1)
fi
“H” level width =
[s]
n(m + 1)
fi
n : Timer Ai register’s set value
[s]
m : Timer Ai register’s low-order 8
bits’ set value
n : Timer Ai register’s high-order
8 bits’ set value
Note: The trigger is generated with the count start bit = “1.”
n
fi
TIMER A
7902 Group User’s Manual 9-35
9.6 Pulse width modulation (PWM) mode
RW
RW
RW
RW
RW
RW
RW
RW
0
1
2
3
4
5
6
7
Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16)
Operating mode select bits
Fix this bit to “1” in PWM mode.
Trigger select bits
16/8-bit PWM mode select bit
Count source select bits
b7 b6 b5 b4 b3 b2 b1 b0
1 1 : PWM mode
b1 b0
11
0 0 : Writing “1” to count start bit
0 1 : (TAiIN pin functions as a programmable I/O
port pin.)
1 0 : Falling edge of TAiIN pin’s input signal
1 1 : Rising edge of TAiIN pin’s input signal
b4 b3
1
0 : 16-bit pulse width modulator
1 : 8-bit pulse width modulator
0
0
0
0
0
0
0
0
See Table 9.2.3.
Timer A0 register (Addresses 4716, 4616)
Timer A1 register (Addresses 4916, 4816)
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
Undefined
15 to 0 These bits can be set to “000016” to “FFFE16.”
Assuming that the set value = n, the “H” level width of the PWM pulse which is output
from the TAiOUT pin is expressed as follows :
(PWM pulse period = )
WO
b0b7
b0
b7
(b15) (b8)
fi: Frequency of count source
Note: Use the MOVM or STA(STAD) instruction for writing to this register.
Writing to this register must be performed in a unit of 16 bits.
n
fi
216–1
fi
<When operating as a 16-bit pulse width modulator>
Timer A0 register (Addresses 4716, 4616)
Timer A1 register (Addresses 4916, 4816)
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
Undefined
Undefined
7 to 0
15 to 8
These bits can be set to “0016” to “FF16.”
Assuming that the set value = m, the period of the PWM pulse which is output from the
TAiOUT pin is expressed as follows:
WO
WO
b0b7
b0
b7
(b15) (b8)
(m + 1) (28 – 1)
fi
<When operating as an 8-bit pulse width modulator>
These bits can be set to “0016” to “FF16.”
Assuming that the set value = n, the “H” level width of the PWM pulse which is output
from the TAiOUT pin is expressed as follows: n(m + 1)
fi
fi: Frequency of count source
Note: Use the MOVM or STA(STAD) instruction for writing to this register.
Writing to this register must be performed in a unit of 16 bits.
Bit Function At reset R/W
Bit nameBit Function At reset R/W
Bit Function At reset R/W
Fig. 9.6.1 Structures of timer Ai registers and timer Ai mode registers in PWM mode.
TIMER A
7902 Group User’s Manual
9-36
9.6 Pulse width modulation (PWM) mode
9.6.1 Setting for PWM mode
Figures 9.6.2 and 9.6.3 show an initial setting example for registers relevant to the PWM mode.
Note that when using interrupts, set up to enable the interrupts. For details, refer to “CHAPTER 7.
INTERRUPTS.”
Fig. 9.6.2 Initial setting example for registers related to PWM mode (1)
Note. When operating as 8-bit pulse width modulator
(m+1) (2 – 1)
fi
n(m+1)
fi
However, if n = “00
16
”, the pulse width modulator
does not operate and the TAi
OUT
pin outputs “L”
level. At this time, no timer Ai interrupt request
occurs.
b7 b0
Count source select bits
See Table 9.2.3.
11
Selecting PWM mode and each function
Timer Ai mode register (i=0 to 4) (Addresses 56
16
to 5A
16
)
1
16/8-bit PWM mode select bit
0 : Operates as 16-bit pulse width modulator
1 : Operates as 8-bit pulse width modulator
Continue to Figure 9.6.3.
Trigger select bits
0 0 :
0 1 :
1 0 : Falling edge of TAi
IN
pin’s input signal: External trigger
1 1 : Rising edge of TAi
IN
pin’s input signal: External trigger
b3
b4
Selection of PWM mode
Setting PWM pulse’s period and “H” level width
b7 b0
Can be set to “000016” to “FFFE16” (n)
(b15) (b8) b7 b0
Timer A0 register (Addresses 47
16
, 46
16
)
Timer A1 register (Addresses 49
16
, 48
16
)
Timer A2 register (Addresses 4B
16
, 4A
16
)
Timer A3 register (Addresses 4D
16
, 4C
16
)
Timer A4 register (Addresses 4F
16
, 4E
16
)
Note. When operating as 16-bit pulse width modulator
(2 – 1)
fi
n
fi
However, if n = “0000
16
”, the pulse width modulator does
not operate and the TAi
OUT
pin outputs “L” level. At this
time, no timer Ai interrupt request occurs.
When operating as 16-bit pulse width modulator
b7 b0
Can be set to “0016” to “FF16” (m)
(b15) (b8) b7 b0
When operating as 8-bit pulse width modulator
Can be set to “0016” to “FE16” (n)
16
8
Timer A0 register (Addresses 47
16
, 46
16
)
Timer A1 register (Addresses 49
16
, 48
16
)
Timer A2 register (Addresses 4B
16
, 4A
16
)
Timer A3 register (Addresses 4D
16
, 4C
16
)
Timer A4 register (Addresses 4F
16
, 4E
16
)
Writing “1” to count start bit: Internal trigger
Period =
“H” level width =
Period =
“H” level width =
(fi : Frequency of
count source) (fi : Frequency of count source)
TIMER A
7902 Group User’s Manual 9-37
9.6 Pulse width modulation (PWM) mode
Fig. 9.6.3 Initial setting example for registers related to PWM mode (2)
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
b7 b0
A
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAA
AAA
AAA
AA
AA
AA
AA
AA
AA
AAAA
AAAA
AAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
b7 b0
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
b7 b0
b7 b0
AA
AAAA
AAAA
AAAA
AAAA
AAA
AAA
AAA
AAA
AAA
AAA
AA
AA
AAAAAA
AAAAAA
From preceding Figure 9.6.2
Setting interrupt priority level
Timer Ai interrupt control register (i = 0 to 4)
(Addresses 7516 to 7916)
Interrupt priority level select bits
When using interrupts, set these bits to
one of levels 1 to 7.
When disabling interrupts, set these bits to
level 0.
When internal trigger is selected
When external trigger is selected
Setting port P5 and port P6 direction registers
Port P5 direction register
(Address D16)
Pin TA0
IN
Clear the corresponding bit to “0.”
b7 b0
AA
AA
Pin TA4
IN
Port P6 direction
register (Address 1016)
Setting count start bit to “1”
Count start register
(Address 4016)
Timer A1 count start bit
Timer A2 count start bit
Timer A3 count start bit
Timer A4 count start bit
Timer A0 count start bit
Setting count start bit to “1”
Count start register
(Address 4016)
Timer A1 count start bit
Timer A2 count start bit
Timer A3 count start bit
Timer A4 count start bit
Timer A0 count start bit
Trigger input
to TAiIN pin
Count starts.
Trigger generated
Pin TA1
IN
Pin TA2
IN
AAAAAA
AAAAAA
AAAAAA
AAAAAA
Pin TA3
IN
AAAAA
AAAAA
AAAAA
AAA
AAA
AAA
AA
AA
TIMER A
7902 Group User’s Manual
9-38
9.6 Pulse width modulation (PWM) mode
9.6.2 Trigger
When a trigger is generated, the TAiOUT pin starts to output PWM pulses. An internal or an external trigger
can be selected as that trigger.
An internal trigger is selected when the trigger select bits (bits 4 and 3 at addresses 5616 to 5A16) are “002
or “012”; an external trigger is selected when these bits are “102” or “112.”
A trigger generated during PWM pulse output is invalid, and it does not affect the pulse output operation.
(1) When selecting internal trigger
A trigger is generated when “1” is written to the count start bit (address 4016).
(2) When selecting external trigger
A trigger is generated at the falling edge of the TAiIN pin’s input signal when bit 3 at addresses
5616 to 5A16 is “0,” or at its rising edge when bit 3 is “1.” However, the trigger input is acceptable
only when the count start bit is “1.”
When using an external trigger, set the port P5 and port P6 direction registers’ bits which correspond
to the TAiIN pins for the input mode.
TIMER A
7902 Group User’s Manual 9-39
9.6 Pulse width modulation (PWM) mode
9.6.3 Operation in PWM mode
When the PWM mode is selected with the operating mode select bits, the TAiOUT pin outputs “L” level.
When a trigger is generated, the counter (pulse width modulator) starts counting and the TAiOUT pin
outputs a PWM pulse (Notes 1 and 2).
The timer Ai interrupt request bit is set to “1” each time the PWM pulse level goes from “H” to “L.”
The interrupt request bit remains set to “1” until the interrupt request is accepted or until the interrupt
request bit is cleared to “0” by software.
Each time a PWM pulse has been output for one period, the reload register’s contents are reloaded and
the counter continues counting.
The following explains operations of the pulse width modulator.
(1) 16-bit pulse width modulator
When the 16/8-bit PWM mode select bit is cleared to “0,” the counter operates as a 16-bit pulse width
modulator. Figures 9.6.4 and 9.6.5 show operation examples of the 16-bit pulse width modulator.
(2) 8-bit pulse width modulator
When the 16/8-bit PWM mode select bit is set to “1,” the counter is divided into 8-bit halves. Then,
the high-order 8 bits operate as an 8-bit pulse width modulator, and the low-order 8 bits operate as
an 8-bit prescaler. Figures 9.6.6 and 9.6.7 show operation examples of the 8-bit pulse width modulator.
Notes 1: If a value “000016” is set into the timer Ai register when the counter operates as a 16-bit
pulse width modulator, the pulse width modulator does not operate and the output from the
TAiOUT pin remains “L” level. The timer Ai interrupt request does not occur. Similarly, if a
value “0016” is set into the high-order 8 bits of the timer Ai register when the counter
operates as an 8-bit pulse width modulator, the same is performed.
2: When the counter operates as an 8-bit pulse width modulator, after a trigger is generated,
the TAiOUT pin outputs “L” level for a period of (1 / fi) (m + 1) (n + 1). After that, the
PWM pulse output will start.
In order to make the TA2OUT and TA3OUT pins serve as pulse output pins, be sure not to select the key input
interrupt pins (KI0 and KI2 pins), which are multiplexed with the above pins. (Refer to “CHAPTER 8. KEY
INPUT INTERRUPT.”)
TIMER A
7902 Group User’s Manual
9-40
9.6 Pulse width modulation (PWM) mode
Fig. 9.6.4 Operation example of 16-bit pulse width modulator
Fig. 9.6.5 Operation example of 16-bit pulse width modulator (when counter value is updated during
pulse output)
(1 / fi) (216 1)
(1 / fi) (n)
Count source
TAiIN pin’s input signal
PWM pulse output
from TAiOUT pin
Note: The above applies when n = “000316” and an external trigger (rising edge of TAiIN pin’s input
signal) is selected.
Trigger is not generated by this signal.
Timer Ai interrupt
request bit
Cleared to “0” when interrupt request is accepted
or cleared by software.
fi: Frequency of count source
n: Reload register
When an arbitrary value is set to the timer Ai register after setting “0000
16
” to it, the timing when the PWM pulse goes “H”
depends on the timing when the new value is set.
Note: The above applies when an external trigger (rising edge of TAi
IN
pin’s input signal) is selected.
FFFE
16
n
0001
16
TAi
IN
pin’s
input signal
Counter contents (Hex.)
(1 / f
i
) (2
16
–1)
(2
16
–1) – n
(1 / f
i
) (2
16
–1)
PWM pulse
output from
TAi
OUT
pin
“0000
16
” is set to timer Ai
register. “2000
16
” is set to timer Ai
register.
2000
16
“FFFE
16
” is set to timer Ai
register.
n = Reload register’s contents
f
i
: Frequency of count source
Restarts counting.
Stops
counting.
Time
(1 / f
i
) (2 –1)
16
n: Reload register’s contents
TIMER A
7902 Group User’s Manual 9-41
9.6 Pulse width modulation (PWM) mode
Fig. 9.6.6 Operation example of 8-bit pulse width modulator
Count source
TAiIN pin’s
input signal
(1 / fi) (m + 1) (28 – 1)
PWM pulse output
from TAiOUT pin
Note: The above applies when n = “0216”, m = “0216”, and an external trigger
(falling edge of TAiIN pin’s input signal) is selected.
Timer Ai interrupt
request bit
Cleared to “0” when interrupt request is accepted or cleared by software.
fi: Frequency of count source
n: Reload register’s high-order 8 bits
m: Reload register’s low-order 8 bits
The 8-bit prescaler counts the count source.
The 8-bit pulse width modulator counts the 8-bit prescaler’s underflow signal.
8-bit prescaler’s
underflow signal
(1 / fi) (m + 1) (n)
(1 / fi) (m + 1)
TIMER A
7902 Group User’s Manual
9-42
9.6 Pulse width modulation (PWM) mode
Fig. 9.6.7 Operation example of 8-bit pulse width modulator (when counter value is updated during
pulse output)
(1 / f
i
) (m+1) (2
8
–1)
PWM pulse output
from TAi
OUT
pin
Count source
TAi
IN
pin’s input
signal
(1 / f
i
) (m+1) (2
8
–1) (1 / f
i
) (m + 1) (2
8
–1)
00
16
Prescaler's
contents (Hex.)
02
16
Time
Stops
counting.
01
16
Counter’s contents (Hex.)
04
16
0A
16
Time
When an arbitrary value is set to the timer Ai register after setting “00
16
” to it, the timing when the PWM pulse level goes “H” depends on the timing when the new value is set.
“0002
16
” is set to timer Ai register.
0A02
16
is set to timer Ai register. “0402
16
” is set to timer Ai register.
Restarts
counting.
Note: The above applies when an external trigger (falling edge of TAi
IN
pin’s input signal) is selected.
f
i
: Frequency of count source
m: Reload register’s low-order 8 bits
TIMER A
7902 Group User’s Manual 9-43
[Precautions for pulse width modulation (PWM) mode]
1. If the count start bit is cleared to “0” during PWM pulse output, the counter stops counting. If the TAiOUT
pin outputs “H” level at that time, the output level will become “L” and the timer Ai interrupt request bit
will be set to “1.” When the TAiOUT pin outputs “L” level at that time, the output level will not change and
no timer Ai interrupt request will occur.
2. When the timer’s operating mode is set by one of the following procedures, the timer Ai interrupt request
bit is set to “1.”
When the PWM mode is selected after reset
When the operating mode is switched from the timer mode to the PWM mode
When the operating mode is switched from the event counter mode to the PWM mode
Accordingly, when using a timer Ai interrupt (interrupt request bit), be sure to clear the timer Ai interrupt
request bit to “0” after the above setting.
3. When using timers A2 and A3 in the PWM mode, the TA2OUT and TA3OUT pins serve as pulse output
pins. Therefore, be sure not to select the key input interrupt pins (KI0 and KI2 pins), which are
multiplexed with the above pins. (Refer to “CHAPTER 8. KEY INPUT INTERRUPT.”)
[Precautions for pulse width modulation PWM mode]
TIMER A
7902 Group User’s Manual
9-44
[Precautions for pulse width modulation PWM mode]
MEMORANDUM
CHAPTER 10CHAPTER 10
TIMER B
10.1 Overview
10.2 Block description
10.3 Timer mode
[Precautions for timer mode]
10.4 Event counter mode
[Precautions for event counter mode]
10.5
Pulse period/Pulse width measurement mode
[Precautions for pulse period/pulse width
measurement mode]
7902 Group User’s Manual
10-2
TIMER B
10.1 Overview, 10.2 Block description
10.1 Overview
Timer B consists of three counters (timers B0 to B2) each equipped with a 16-bit reload function. Timers
B0 to B2 have identical functions and operate independently of one other.
Timer Bi (i = 0 to 2) has three operating modes listed below.
(1) Timer mode
The timer counts an internally generated count source.
(2) Event counter mode
The timer counts an external signal.
(3) Pulse period/Pulse width measurement mode
The timer measures an external signal’s pulse period or pulse width.
10.2 Block description
Figure 10.2.1 shows the block diagram of timer B. Explanation of registers relevant to timer B is described
below.
Fig. 10.2.1 Block diagram of timer B
f
2
f
16
f
64
f
512
Count source select bits
•Timer
•Pulse period measurement/pulse
width measurement
Event counter
mode
Count start register
Counter reset circuit
Data bus (odd)
Data bus (even)
(Low-order 8 bits) (High-order 8 bits)
Timer Bi reload register (16)
Timer Bi
interrupt
request bit
TBi
IN
Timer Bi
overflow
flag
(Valid in the pulse period/pulse width
measurement mode.)
Timer Bi counter (16)
Polarity selection
and edge pulse
generator
Timer B2 clock source
select bit (Note)
Timer B2 clock source select bit : Bit 6 at address 63
16
Note: Only for timer B2, a count source in the event counter mode can be selected.
7902 Group User’s Manual 10-3
TIMER B
10.2.1 Counter and Reload register (timer Bi register)
Each of timer Bi counter and reload register consists of 16 bits and has the following functions.
(1) Functions in timer mode and event counter mode
Countdown in the counter is performed each time the count source is input. The reload register is
used to store the initial value of the counter. When a counter underflow occurs, the reload register’s
contents are reloaded into the counter.
A value is set to the counter and reload register by writing the value to the timer Bi register.
Table 10.2.1 lists the memory assignment of the timer Bi register.
The value written into the timer Bi register while counting is not in progress is set to the counter and
reload register. The value written into the timer Bi register while counting is in progress is set only
to the reload register. In this case, the reload register’s updated contents are transferred to the
counter at the next underflow. The counter value is read out by reading out the timer Bi register.
Note: When reading from or writing to the timer Bi register, perform it in a unit of 16 bits. For more
information about the value obtained by reading the timer Bi register, refer to sections
“[Precautions for timer mode]” and “[Precautions for event counter mode].”
(2) Functions in pulse period/pulse width measurement mode
Countup in the counter is performed each time the count source is input. The reload register is used
to retain the pulse period or pulse width measurement result. When a valid edge is input to the TBiIN
pin, the counter value is transferred to the reload register. In this mode, the value obtained by
reading the timer Bi register is the reload register’s contents, so that the measurement result is
obtained.
Note: When reading from the timer Bi register, perform it in a unit of 16 bits.
10.2 Block description
Timer Bi register
Timer B0 register
Timer B1 register
Timer B2 register
Low-order byte
Address 5016
Address 5216
Address 5416
High-order byte
Address 5116
Address 5316
Address 5516
Note: At reset, the contents of the timer Bi register
are undefined.
Table 10.2.1 Memory assignment of timer Bi registers
7902 Group User’s Manual
10-4
TIMER B
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
10.2.3 Timer Bi mode register
Figure 10.2.3 shows the structure of the timer Bi mode register. The operating mode select bits are used
to select the operating mode of timer Bi. Bits 2, 3, and bits 5 to 7 have different functions according to the
operating mode. These bits are described in the paragraph of each operating mode.
10.2.2 Count start register
This register is used to start and stop counting. One bit of this register corresponds to one timer. (This is
the one-to-one relationship.) Figure 10.2.2 shows the structure of the count start register.
Fig. 10.2.2 Structure of count start register
10.2 Block description
Fig. 10.2.3 Structure of timer Bi mode register
Count start register (Address 4016)
Timer A0 count start bit
Timer A1 count start bit
Timer A2 count start bit
Timer A3 count start bit
Timer A4 count start bit
Timer B0 count start bit
Timer B1 count start bit
Timer B2 count start bit
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
b7 b6 b5 b4 b3 b2 b1 b0
0 : Stop counting
1 : Start counting
Bit nameBit Function At reset R/W
Operating mode select bits
These bits have different functions according to the operating mode.
Nothing is assigned.
These bits have different functions according to the operating mode.
Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16)b7 b6 b5 b4 b3 b2 b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : Pulse period/Pulse width measurement mode
1 1 : Do not select.
b1 b0
Note: Bit 5 is invalid in the timer and event counter modes; its value is undefined at reading.
0
0
0
0
Undefined
Undefined
0
0
RW
RW
RW
RW
RO
(Note)
RW
RW
Bit nameBit Function At reset R/W
7902 Group User’s Manual 10-5
TIMER B
0
1
2
3
7 to 4
10.2.4 Timer Bi interrupt control register
Figure 10.2.4 shows the structure of the timer Bi interrupt control register. For details about interrupts, refer
to “CHAPTER 7. INTERRUPTS.”
10.2 Block description
Fig. 10.2.4 Structure of timer Bi interrupt control register
(1) Interrupt priority level select bits (bits 2 to 0)
These bits are used to select a timer Bi interrupt’s priority level. When using timer Bi interrupts,
select the priority level from levels 1 through 7. When a timer Bi interrupt request occurs, its priority
level is compared with the processor interrupt priority level (IPL), so that the requested interrupt is
enabled only when its priority level is higher than the IPL. (However, this applies when the interrupt
disable bit (I) = “0.”) To disable timer Bi interrupts, set these bits to “0002” (level 0).
(2) Interrupt request bit (bit 3)
This bit is set to “1” when a timer Bi interrupt request occurs. This bit is automatically cleared to “0”
when the timer Bi interrupt request is accepted. This bit can be set to “1” or cleared to “0” by
software.
Timer Bi interrupt control register (i = 0 to 2) (Addresses 7A16 to 7C16)
Interrupt priority level select bits
Interrupt request bit
Nothing is assigned.
b7 b6 b5 b4 b3 b2 b1 b0
Note: When writing to this bit, use the MOVM (MOVMB) or STA (STAB, STAD) instruction.
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1b0
0 : No interrupt requested
1 : Interrupt requested
0
0
0
0
Undefined
RW
RW
RW
RW
(Note)
Bit nameBit Function At reset R/W
7902 Group User’s Manual
10-6
TIMER B
0
0
0
0
0
0
0
0
10.2.5 Port P6 direction register
The input pins of timer Bi are multiplexed with port P6 pins. When using these pins as timer Bi’s input pins,
clear the corresponding bits of the port P6 direction register to “0” in order to set these port pins for the
input mode. Figure 10.2.5 shows the relationship between port P6 direction register and the timer Bi’s input
pins.
10.2 Block description
Fig. 10.2.5 Relationship between port P6 direction register and timer Bi’s input pins
10.2.6 Count source (in timer mode and pulse period/pulse width measurement mode)
In the timer mode and pulse period/pulse width measurement mode, the count source select bits (bits 6
and 7 at addresses 5B16 to 5D16) are used to select the count source (f2, f16, f64, or f512). (See Figures 10.3.1
and 10.5.1.)
Pin TA4OUT
Pin TA4IN
Pin INT0
Pin INT1
Pin INT2 (Note)
Pin TB0IN
Pin TB1IN
Pin TB2IN
Port P6 direction register (Address 1016)b7 b6 b5 b4 b3 b2 b1 b0
0 : Input mode
1 : Output mode
When using this pin as timer Bi’s input pin, be sure
to clear the corresponding bit to “0.”
RW
RW
RW
RW
RW
RW
RW
Corresponding pinBit Functions At reset R/W
Note: This applies when the pin INT2 select bit (bit 4 at address 9416) = “0.”
0
1
2
3
4
5
6
7
7902 Group User’s Manual 10-7
TIMER B
10.3 Timer mode
In this mode, the timer counts an internally generated count source. Table 10.3.1 lists the specification of
the timer mode. Figure 10.3.1 shows the structures of the timer Bi register and timer Bi mode register in
the timer mode.
Table 10.3.1 Specifications of timer mode
10.3 Timer mode
Item
Count source fi
Count operation
Division ratio
Count start condition
Count stop condition
Interrupt request occurrence timing
TBiIN pin’s function
Read from timer Bi register
Write to timer Bi register
Specifications
f2, f16, f64, or f512
•Countdown
•When a counter underflow occurs, reload register’s contents are re-
loaded, and counting continues.
When the count start bit is set to “1.”
When the count start bit is cleared to “0.”
When a counter underflow occurs.
Programmable I/O port pin
Counter value can be read out.
While counting is stopped
When a value is written to the timer Bi register, it is written to both
of the reload register and counter.
While counting is in progress
When a value is written to the timer Bi register, it is written only to the
reload register. (Transferred to the counter at the next reload timing.)
1
(n + 1) n: Timer Bi register’s set value
7902 Group User’s Manual
10-8
TIMER B
0
1
2
3
4
5
6
7
Fig. 10.3.1 Structures of timer Bi register and timer Bi mode register in timer mode
10.3 Timer mode
Operating mode select bits
These bits are invalid in timer mode.
Nothing is assigned.
This bit is invalid in timer mode; its value is undefined at reading.
Count source select bits
Undefined
15 to 0 These bits can be set to “000016” to “FFFF16.”
Assuming that the set value = n, the counter divides the count source frequency by (n + 1).
When reading, the register indicates the counter value.
RW
b0b7b0b7
(b15) (b8)
Timer B0 register (Addresses 5116, 5016)
Timer B1 register (Addresses 5316, 5216)
Timer B2 register (Addresses 5516, 5416)
Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16)b7 b6 b5 b4 b3 b2 b1 b0
0 0 : Timer mode
b1 b0
00
0 0 : f2
0 1 : f16
1 0 : f64
1 1 : f512
b7 b6
X : It may be either “0” or “1.”
XXX
0
0
0
0
Undefined
Undefined
0
0
RW
RW
RW
RW
RO
RW
RW
Note: Reading from or writing to this register must be performed in a unit of 16 bits.
Bit Function At reset R/W
Bit nameBit Function At reset R/W
7902 Group User’s Manual 10-9
TIMER B
10.3.1 Setting for timer mode
Figure 10.3.2 shows an initial setting example for registers relevant to the timer mode.
Note that when using interrupts, set up registers to enable the interrupts. For details, refer to “CHAPTER
7. INTERRUPTS.”
Fig. 10.3.2 Initial setting example for registers relevant to timer mode
10.3 Timer mode
AAAA
AAAA
AAAA
Count starts.
b7 b0
Count source select bits
0 0 : f
2
0 1 : f
16
1 0 : f
64
1 1 : f
512
00
Selecting timer mode and count source
Timer Bi mode register (i = 0 to 2)
(Addresses 5B
16
to 5D
16
)
Setting count start bit to “1”
b7 b0
Count start register (Address 40
16
)
Timer B0 count start bit
Timer B1 count start bit
Timer B2 count start bit
b7b6
Setting interrupt priority level
b7 b0
Timer Bi interrupt control register (i = 0 to 2)
(Addresses 7A
16
to 7C
16
)
Interrupt priority level select bits
When using interrupts, set these bits to one of levels 1 to 7.
When disabling interrupts, set these bits to level 0.
: It may be either “0” or “1.”
Selection of timer mode
Note: The counter divides the count source by (n + 1).
Setting division ratio
b7 b0
Can be set to “0000
16
” to “FFFF
16
” (n).
(b15) (b8) b7 b0
Timer B0 register (Addresses 51
16
, 50
16
)
Timer B1 register (Addresses 53
16
, 52
16
)
Timer B2 register (Addresses 55
16
, 54
16
)
7902 Group User’s Manual
10-10
TIMER B
10.3 Timer mode
10.3.2 Operation in timer mode
When the count start bit is set to “1,” the counter starts counting of the count source.
When a counter underflow occurs, the reload register’s contents are reloaded and counting continues.
The timer Bi interrupt request bit is set to “1” at the counter underflow in . The interrupt request bit
remains set to “1” until the interrupt request is accepted or until the interrupt request bit is cleared to
“0” by software.
Figure 10.3.3 shows an example of operation in the timer mode.
Fig. 10.3.3 Example of operation in timer mode
Stops counting.
Restarts counting.
FFFF16
n
000016
Time
Count start bit
Timer Bi interrupt
request bit
Counter contents (Hex.)
Cleared to “0” when interrupt request is
accepted or cleared by software.
Set to “1” by software.
Starts counting.
Set to “1” by software.
1 / fi (n+1)
fi : Frequency of count source
Cleared to “0” by software.
n : Reload register’s contents
7902 Group User’s Manual 10-11
TIMER B
[Precautions for timer mode]
[Precautions for timer mode]
While counting is in progress, by reading the timer Bi register, the counter value can be read out at any
timing. However, if the timer Bi register is read at the reload timing shown in Figure 10.3.4, the value
“FFFF16” is read out. If reading is performed in the period from when a value is set into the timer Bi register
with the counter stopped until the counter starts counting, the set value is correctly read out.
Fig. 10.3.4 Reading timer Bi register
210n n – 1
Counter value
(Hex.)
210
FFFF n – 1
Read value
(Hex.)
Reload
Time
n = Reload register’s contents
7902 Group User’s Manual
10-12
TIMER B
10.4 Event counter mode
10.4 Event counter mode
In this mode, the timer counts an external signal. Table 10.4.1 lists the specifications of the event counter
mode. Figure 10.4.1 shows the structures of the timer Bi register and the timer Bi mode register in the event
counter mode.
Table 10.4.1 Specifications of event counter mode
Item
Count source
Count operation
Division ratio
Count start condition
Count stop condition
Interrupt request occurrence timing
TBiIN pin’s function
Read from timer Bi register
Write to timer Bi register
Specifications
•External signal input to the TBiIN pin, fX32 (Note 1)
•The count source’s valid edge can be selected from the falling edge,
the rising edge, and both of the falling and rising edges by software.
•Countdown
•When a counter underflow occurs, reload register’s contents are
reloaded, and counting continues.
When the count start bit is set to “1.”
When the count start bit is cleared to “0.”
When the counter underflow occurs.
Count source input pin (Note 2)
Counter value can be read out.
While counting is stopped
When a value is written to the timer Bi register, it is written to both
of the reload register and counter.
While counting is in progress
When a value is written to the timer Bi register, it is written only to the
reload register. (Transferred to the counter at the next reload timing.)
(n + 1)
1n: Timer Bi register’s set value
Notes 1 :Only for timer B2, fX32 can be selected.
2 :When fX32 is selected as the count source in timer B2, the TB2IN pin can be used as a programmable
I/O port pin.
7902 Group User’s Manual 10-13
TIMER B
10.4 Event counter mode
Fig. 10.4.1 Structures of timer Bi register and timer Bi mode register in event counter mode
Operating mode select bits
Count polarity select bits
Nothing is assigned.
This bit is invalid in event counter mode; its value is undefined at reading.
These bits are invalid in event counter mode.
RW
RW
RW
RW
RO
RW
RW
0
1
2
3
4
5
6
7
Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16)b7 b6 b5 b4 b3 b2 b1 b0
0 1 : Event counter mode
b1 b0
01
0 0 : Count at falling edge of external signal
0 1 : Count at rising edge of external signal
1 0 : Count at both falling and rising edges of external
signal
1 1 : Do not select. (Note)
b3 b2
X : It may be either “0” or “1.”
Note: When the timer B2 clock source select bit (bit 6 at address 6316) = “1,” be sure to fix these bits to “012” (count at the rising
edge of the external signal).
XXX
0
0
0
0
Undefined
Undefined
0
0
Bit nameBit Function At reset R/W
Undefined
15 to 0 These bits can be set to “000016” to “FFFF16.”
Assuming that the set value = n, the counter divides the count source frequency by (n + 1).
When reading, the register indicates the counter value.
RW
b0b7
b0b7
(b15) (b8)
Timer B0 register (Addresses 5116, 5016)
Timer B1 register (Addresses 5316, 5216)
Timer B2 register (Addresses 5516, 5416)
Note: Reading from or writing to this register must be performed in a unit of 16 bits.
Bit Function At reset R/W
7902 Group User’s Manual
10-14
TIMER B
RW
(Note 2)
RW
(Note 2)
RW
RW
RW
RW
0
1
2
3
4
5
6
7
10.4 Event counter mode
10.4.1 Count source
For timer B2 in the event counter mode, a count source (an external signal into the TB2IN pin, or fX32) can
be selected by using the timer B2 clock source select bit. (See Figure 10.4.2.) Timers B0 and B1 count
the external signals input to the TB0IN and TB1IN pins, respectively.
When fX32 is selected as the count source, the TB2IN pin serves as a programmable I/O port pin.
Fig. 10.4.2 Structures of particular function select register 1
Notes 1: At power-on reset, this bit becomes “0.” At hardware reset or software reset, this bit retains the value just before reset.
2: Even when “1” is written, the bit status will not change.
3: Setting this bit to “1” must be performed just before execution of the WIT instruction. Also, after the wait state is termi-
nated, this bit must be cleared to “0” immediately.
(Note 1)
(Note 1)
0
0
0
0
0
0
Particular function select register 1 (Address 6316)b7 b6 b5 b4 b3 b2 b1 b0
Bit nameBit Function At reset R/W
STP-instruction-execution
status bit
WIT-instruction-execution
status bit
Standby state select bit
System clock stop select bit
at WIT (Note 3)
Address output select bit
The value is “0” at reading.
Timer B2 clock source select bit
(Valid in event counter mode.)
The value is “0” at reading.
0 : Address output changes at access to the inter-
nal area and external area.
1 : Address output changes only at access to the
external area.
0 : Normal operation.
1 : STP instruction has been executed.
0 : Normal operation.
1 : WIT instruction has been executed.
0 : External signal input to the TB2 IN pin is counted.
1 : fX32 is counted.
0 : External bus
1 : Programmable I/O port
0 : In the wait mode, system clock fsys is active.
1 : In the wait mode, system clock fsys is stopped.
7902 Group User’s Manual 10-15
TIMER B
10.4 Event counter mode
10.4.2 Setting for event counter mode
Figure 10.4.3 shows an initial setting example for registers relevant to the event counter mode.
Note that when using interrupts, set up to enable the interrupts. For details, refer to section “CHAPTER
7. INTERRUPTS.”
Fig. 10.4.3 Initial setting example for registers relevant to event counter mode
Note: The counter divides the count source by (n + 1).
Setting division ratio
b7 b0
Can be set to “0000
16
” to “FFFF
16
” (n).
(b15) (b8) b7 b0
Timer B0 register (Addresses 51
16
, 50
16
)
Timer B1 register (Addresses 53
16
, 52
16
)
Timer B2 register (Addresses 55
16
, 54
16
)
AAA
AAA
AAA
Count starts.
b7 b0
0 0 : Count at falling edge of external signal.
0 1 : Count at rising edge of external signal.
1 0 : Count at both of falling and rising edges of external signal.
1 1 : Do not selected.
01
Selecting event counter mode and count polarity
Timer Bi mode register (i = 0 to 2) (Addresses 5B
16
to 5D
16
)
Setting count start bit to “1”
b7 b0
Count start register (Address 40
16
)
Timer B0 count start bit
Timer B1 count start bit
Timer B2 count start bit
b3 b2
Setting interrupt priority level
b7 b0
Timer Bi interrupt control register (i = 0 to 2)
(Addresses 7A
16
to 7C
16
)
Interrupt priority level select bits
When using interrupts, set these bits to one of levels 1 to 7.
When disabling interrupts, set these bits to level 0.
AAAA
AAAA
Setting port P6 direction register
b7 b0
Port P6 direction register (Address 10
16
)
Clear the corresponding bit to “0.”
Pin TB0
IN
Pin TB1
IN
Pin TB2
IN
(Note)
: It may be either “0” or “1.”
Selection of event counter mode
Count polarity select bits
Selecting clock source
b7 b0
Particular function select register 1
(Address 63
16
)
Timer B2 clock source select bit
0 : Count an external signal input to the TB2
IN
pin
1 : Count fX
32
Timers B0 and B1
Note: When fX
32
is selected as the count
source of timer B2 (bit 6 at address
63
16
= “1”), this setting is unnecessary.
Timer B2
7902 Group User’s Manual
10-16
TIMER B
10.4 Event counter mode
10.4.3 Operation in event counter mode
When the count start bit is set to “1,” the counter starts counting of the count source.
When a counter underflow occurs, the reload register’s contents are reloaded, and counting continues.
The timer Bi interrupt request bit is set to “1” at the counter underflow in .
The interrupt request bit remains set to “1” until the interrupt request is accepted or until the interrupt
request bit is cleared to “0” by software.
Figure 10.4.4 shows an example of operation in the event counter mode.
Fig. 10.4.4 Example of operation in event counter mode
Stops counting.
Restarts counting .
FFFF16
n
000016
Time
Count start bit
Timer Bi interrupt
request bit
Counter contents (Hex.)
Cleared to “0” when interrupt request is accepted or cleared to “0” by software.
Set to “1” by software.
Starts counting.
Cleared to “0” by
software. Set to “1” by software.
n : Reload ragister’s contents
7902 Group User’s Manual 10-17
TIMER B
[Precautions for event counter mode]
[Precautions for event counter mode]
While counting is in progress, by reading the timer Bi register, the counter value can be read out at any
timing. However, if the timer Bi register is read at the reload timing shown in Figure 10.4.5, a value
“FFFF16” is read out. If reading is performed in the period from when a value is set into the timer Bi register
with the counter stopped until the counter start counting, the set value is correctly read out.
Fig. 10.4.5 Reading timer Bi register
210n n – 1
Counter value
(Hex.)
21 0
FFFF n – 1
Read value
(Hex.)
Reload
Time
n = Reload register’s contents
7902 Group User’s Manual
10-18
TIMER B
10.5 Pulse period/Pulse width measurement mode
10.5 Pulse period/Pulse width measurement mode
In this mode, the timer measures an external signal’s pulse period or pulse width. Table 10.5.1 lists the
specifications of the pulse period/pulse width measurement mode. Figure 10.5.1 shows the structures of the
timer Bi register and timer Bi mode register in the pulse period/pulse width measurement mode.
(1) Pulse period measurement
The timer measures the pulse period of the external signal that is input to the TBiIN pin.
(2) Pulse width measurement
The timer measures the pulse width (“L” level and “H” level widths) of the external signal that is input
to the TBiIN pin.
Table 10.5.1 Specifications of pulse period/pulse width measurement mode
Item
Count source fi
Count operation
Count start condition
Count stop condition
Interrupt request occurrence timing
TBiIN pin’s function
Read from timer Bi register
Write to timer Bi register
Timer Bi overflow flag: This bit is used to identify the source of an interrupt request occurrence.
Notes 1: No interrupt request occurs when the first valid edge is input after the counter starts counting.
2: The value read out from the timer Bi register is undefined in the period after the counter starts
counting until the second valid edge is input.
Specifications
f2, f16, f64, or f512
Countup
Counter value is transferred to the reload register at valid edge of
measurement pulse, and counting continues after clearing the counter
value to “000016.”
When the count start bit is set to “1.”
When the count start bit is cleared to “0.”
When a valid edge of measurement pulse is input (Note 1).
When a counter overflow occurs (The timer Bi overflow flag is set
to “1” simultaneously.)
Measurement pulse input pin
The value obtained by reading the timer Bi register is the reload
register’s contents (Measurement result) (Note 2).
Invalid
7902 Group User’s Manual 10-19
TIMER B
10.5 Pulse period/Pulse width measurement mode
Fig. 10.5.1 Structures of timer Bi register and timer Bi mode register in pulse period/pulse width
measurement mode
Note: Reading from this register must be performed in a unit of 16 bits.
Undefined
15 to 0 The measurement result of pulse period or pulse width is read out. RO
Timer B0 register (Addresses 5116, 5016)
Timer B1 register (Addresses 5316, 5216)
Timer B2 register (Addresses 5516, 5416)
0
1
2
3
4
5
6
7
Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16)
Operating mode select bits
Measurement mode select bits
Nothing is assigned.
Timer Bi overflow flag (Note)
Count source select bits
b7 b6 b5 b4 b3 b2 b1 b0
1 0 : Pulse period/Pulse width measurement mode
b1 b0
10
0 0 : Pulse period measurement
(Interval between falling edges of measurement pulse)
0 1 : Pulse period measurement
(Interval between rising edges of measurement pulse)
1 0 : Pulse width measurement
(Interval from a falling edge to a rising edge, and from
a rising edge to a falling edge of measurement pulse)
1 1 : Do not select.
b3 b2
0 0 : f2
0 1 : f16
1 0 : f64
1 1 : f512
b7 b6
Note: The timer Bi overflow flag is cleared to “0” when a value is written to the timer Bi mode register with the count start bit = “1.”
This flag cannot be set to “1” by software.
0 : No overflow
1 : Overflowed
0
0
0
0
Undefined
Undefined
0
0
RW
RW
RW
RW
RO
RW
RW
b0b7b0b7
(b15) (b8)
Bit Function At reset R/W
Bit nameBit Function At reset R/W
7902 Group User’s Manual
10-20
TIMER B
10.5 Pulse period/Pulse width measurement mode
10.5.1 Setting for pulse period/pulse width measurement mode
Figure 10.5.2 shows an initial setting example for registers relevant to the pulse period/pulse width measurement
mode.
Note that when using interrupts, set up to enable the interrupts. For details, refer to “CHAPTER 7.
INTERRUPTS.”
Fig. 10.5.2 Initial setting example for registers relevant to pulse period/pulse width measurement
mode
AAA
AAA
AAA
Count starts.
b7 b0
Measurement mode select bits
10
Selecting pulse period/pulse width measurement mode and each function
Timer Bi mode register (i = 0 to 2)
(Addresses 5B
16
to 5D
16
) (Note 1)
Setting count start bit to “1”
b7 b0
Count start register
(Address 40
16
)
Timer B0 count start bit
Timer B1 count start bit
Timer B2 count start bit
b3 b2
Setting interrupt priority level
b7 b0
Timer Bi interrupt control register (i = 0 to 2)
(Addresses 7A
16
to 7C
16
)
Interrupt priority level select bits
When using interrupts, set these bits to one of levels 1 to 7.
When disabling interrupts, set these bits to level 0.
Count source select bits
b7b6
Timer Bi overflow flag (Note 2)
0: No overflow
1: Overflowed
Setting port P6 direction register
b7 b0
Port P6 direction register (Address 10
16
)
Clear the corresponding bit to “0.”
Pin TB0
IN
Pin TB1
IN
Pin TB2
IN
0 0 : Pulse period measurement (Interval between falling edges
of measurement pulse)
0 1 : Pulse period measurement (Interval between rising edges
of measurement pulse)
1 0 : Pulse width measurement
1 1 : Do not select.
0 0 : f
2
0 1 : f
16
1 0 : f
64
1 1 : f
512
Notes 1: When using timer B2, be sure to clear the timer B2 clock source select bit (See Figure 10.4.2.) to “0.”
2: The timer Bi overflow flag is a read-only bit. This bit is undefined after reset. When a value is written to the timer Bi mode register
with the count start bit = “1,” this bit will be cleared to “0.”
Selection of pulse period/pulse width measurement mode
7902 Group User’s Manual 10-21
TIMER B
10.5 Pulse period/pulse width measurement mode
10.5.2 Operation in pulse period/pulse width measurement mode
When the count start bit is set to “1,” the counter starts counting of the count source.
The counter value is transferred to the reload register when an valid edge of the measurement pulse
is detected. (Refer to section “(1) Pulse period/Pulse width measurement.”)
The counter value is cleared to “000016” after the transfer in , and the counter continues counting.
The timer Bi interrupt request bit is set to “1” when the counter value is cleared to “000016” in (Note).
The interrupt request bit remains set to “1” until the interrupt request is accepted or until the interrupt
request bit is cleared to “0” by software.
The timer repeats operations to above.
Note: No timer Bi interrupt request occurs when the first valid edge is input after the counter starts counting.
(1) Pulse period/pulse width measurement
The measurement mode select bits (bits 3 and 2 at addresses 5B16 and 5D16) specify whether the
pulse period of an external signal is measured or its pulse width is done. Table 10.5.2 lists the
relationship between the measurement mode select bits and the pulse period/pulse width measurements.
Make sure that the measurement pulse interval from the falling edge to the rising edge, and vice
versa are two cycles of the count source or more. Additionally, use software to identify whether the
measurement result indicates the “H” level width or the “L” level width.
Table 10.5.2 Relationship between measurement mode select bits and pulse period/pulse width
measurements
(2) Timer Bi overflow flag
A timer Bi interrupt request occurs when a measurement pulse’s valid edge is input or when a
counter overflow occurs. The timer Bi overflow flag is used to identify the source of the interrupt
request occurrence, that is, whether it is an overflow occurrence or a valid edge input.
The timer Bi overflow flag is set to “1” at an overflow occurrence. Accordingly, the source of the
interrupt request occurrence is identified by checking the timer Bi overflow flag in the interrupt
routine. When a value is written to the timer Bi mode register with the count source start bit = “1,”
the timer Bi overflow flag will be cleared to “0” at the next count timing of the count source.
The timer Bi overflow flag is a read-only bit.
Use the timer Bi interrupt request bit to detect the overflow timing. Do not use the timer Bi overflow
flag for this detection.
Figure 10.5.3 shows the operation example during the pulse period measurement, and Figure 10.5.4
shows the operation example during the pulse width measurement.
b3
0
0
1
Pulse period/Pulse width measurement
Pulse period measurement
Pulse width measurement
Measurement interval (Valid edges)
From falling edge to falling edge (Falling edges)
From rising edge to rising edge (Rising edges)
From falling edge to rising edge, and vice versa
(Falling and rising edges)
b2
0
1
0
7902 Group User’s Manual
10-22
TIMER B
Fig. 10.5.3 Operation example during pulse period measurement
Fig. 10.5.4 Operation example during pulse width measurement
10.5 Pulse period/pulse width measurement mode
Count source
Measurement pulse
Timing at which counter is
cleared to “0000
16
Note: The above applies when measurement is performed for an interval from one falling edge to the next
falling edge of the measurement pulse.
Reload register Counter
Transfer timing
Count start bit
Counter is initialized by completion of measurement.
Counter overflow.
Cleared to “0” when interrupt request is accepted or
cleared to “0” by software.
Timer Bi interrupt
request bit
Timer Bi overflow flag
Transferred
(undefined value) Transferred
(measured value)
Measurement pulse
Count source
Timing at which counter is
cleared to “000016
Count start bit
Timer Bi interrupt
request bit
Timer Bi overflow flag
Reload register Counter
Transfer timing
Counter is initialized by completion of measurement.
Counter overflow.
Transferred
(measured
value)
Transferred
(measured
value)
Transferred
(measured
value)
Transferred
(undefined
value)
➀➀
Cleared to “0” when interrupt request is accepted or
cleared to “0” by software.
7902 Group User’s Manual 10-23
TIMER B
[Precautions for pulse period/pulse width measurement mode]
[Precautions for pulse period/pulse width measurement mode]
1. A timer Bi interrupt request is generated by one of the following sources:
Valid edge input of measured pulse
Counter overflow
When an overflow generates an interrupt request, the timer Bi overflow flag will be set to “1.”
2. After reset, the timer Bi overflow flag is undefined. When a value is written to the timer Bi mode register
with the count start bit = “1,” this flag will be cleared to “0” at the next count timing of the count source.
3. An undefined value is transferred to the reload register at the first valid edge input after the count start.
In this case, no timer Bi interrupt request will occur.
4. The counter value at count start is undefined. Accordingly, there is a possibility that a timer Bi interrupt
request occurs by an overflow immediately after the count start.
5. If the contents of the measurement mode select bits are changed after the count start, the timer Bi
interrupt request bit is set to “1.” When the value, which has been set in these bits before, are written
again, the timer Bi interrupt request bit will not change, that is to say, this bit retains this state.
6. When using timer B2, be sure to clear the timer B2 clock source select bit (bit 6 at address 6316) to “0.”
7. If the input signal to the TBiIN pin is affected by noise, etc., there is a possibility that the counter cannot
perform the exact measurement. We recommend to verify, by software, that the measurement values are
within a constant range.
7902 Group User’s Manual
10-24
TIMER B
[Precautions for pulse period/pulse width measurement mode]
MEMORANDUM
CHAPTER 11CHAPTER 11
REAL-TIME
OUTPUT
11.1 Overview
11.2 Block description
11.3 Setting of real-time output
11.4 Real-time output operation
REAL-TIME OUTPUT
7902 Group User’s Manual
11-2
11.1 Overview
11.1 Overview
The real-time output function is used to change the output levels of several pins simultaneously at every
period of the timer. Figure 11.1.1 shows the block diagram of real-time output per bit. The real-time output
function has two operating modes described below.
(1) Pulse mode 0
The 8-bit pulse output pins serve as two independent 4-bit outputs. Figure 11.1.2 shows the configuration
of real-time output in the pulse mode 0.
(2) Pulse mode 1
The 8-bit pulse output pins serve as a 2-bit and a 6-bit outputs. Figure 11.1.3 shows the configuration
of real-time output in the pulse mode 1.
Fig. 11.1.1 Block diagram of real-time output per bit
AA
AA
AA
AA
AA
AA
AA
Data bus
Pulse output data register j
Waveform output select bit j
Bit i of port P5 direction register
T
DQ
Timer Aj
underflow signal
1
0
P5i/RTP0k, P5i/RTP1k
• i = 0 to 7
• j = 0, 2
• k = 0 to 3
Flip-flop
Port P5i latch
REAL-TIME OUTPUT
7902 Group User’s Manual 11-3
Fig. 11.1.2 Configuration of real-time output in pulse mode 0
11.1 Overview
Fig. 11.1.3 Configuration of real-time output in pulse mode 1
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
aPort P5i direction register
Port P5i latch
(i = 0 to 7)
1
0
Data bus (even)
a
a
a
a
P54/RTP10
P55/RTP11
P56/RTP12
P57/RTP13
Timer A2
T
D Q
T
D Q
T
D Q
T
D Q
b7 b0
Pulse output data register 0
Bit 0 of waveform output select bits
P50/RTP00
P51/RTP01
P52/RTP02
P53/RTP03
a
a
a
a
T
D Q
T
D Q
T
D Q
T
D Q
b7 b0 Timer A0
Pulse output data register 1
Bit 1 of waveform output select bits
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
aPort P5i direction register
Port P5i latch
(i = 0 to 7)
1
0
Data bus (even)
Pulse output data register 0
Bit 0 of waveform output select bits
P50/RTP00
P51/RTP01
a
a
T
D Q
T
D Q
b7 b0 Timer A0
a
P52/RTP02
P53/RTP03
P54/RTP10
P55/RTP11
P56/RTP12
P57/RTP13
Bit 1 of waveform output select bits
T
D Q
T
D Q
T
D Q
T
D Q
a
a
a
a
a
T
D Q
T
D Q
b7 b0 Timer A1
Pulse output data register 1
REAL-TIME OUTPUT
7902 Group User’s Manual
11-4
11.2 Block description
Registers relevant to the real-time output function are described below.
11.2.1 Real-time output control register
Figure 11.2.1 shows the structure of the real-time output control register.
11.2 Block description
Fig. 11.2.1 Structure of real-time output control register
RW
RW
RW
0
0
0
0
Bit nameBit
0
1
2
7 to 3
Real-time output control register (Address A016)
Function At reset R/W
Waveform output select bits
Pulse output mode select bit
The value is “0” at reading.
b7 b6 b5 b4 b3 b2 b1 b0
See the table below.
Note: When using pins P50 to P57 as pulse output pins of the real-time output function, be sure to set the corresponding bits of the
port P5 direction register (address D16) to “1.” When using pins RTP10 to RTP1 3, do not select the key input interrupt pins (KI 0
to KI3) multiplexed with pins RTP10 to RTP13. (Refer to “CHAPTER 8. KEY INPUT INTERRUPT.”)
0 : Pulse mode 0
1 : Pulse mode 1
b1 b0
Pulse mode 0
00
P57/RTP13
P56/RTP12
P55/RTP11
P54/RTP10
P53/RTP03
P52/RTP02
P51/RTP01
P50/RTP00
Port
01
P57/RTP13
P56/RTP12
P55/RTP11
P54/RTP10
P53/RTP03
P52/RTP02
P51/RTP01
P50/RTP00
Port
Port
RTP
10
P57/RTP13
P56/RTP12
P55/RTP11
P54/RTP10
P53/RTP03
P52/RTP02
P51/RTP01
P50/RTP00
RTP
11
P57/RTP13
P56/RTP12
P55/RTP11
P54/RTP10
P53/RTP03
P52/RTP02
P51/RTP01
P50/RTP00
Port
RTP
RTP
P57/RTP13
P56/RTP12
P55/RTP11
P54/RTP10
P53/RTP03
P52/RTP02
P51/RTP01
P50/RTP00
Port
Port
Pulse mode 1
P57/RTP13
P56/RTP12
P55/RTP11
P54/RTP10
P53/RTP03
P52/RTP02
P51/RTP01
P50/RTP00
Port
RTP
P57/RTP13
P56/RTP12
P55/RTP11
P54/RTP10
P53/RTP03
P52/RTP02
P51/RTP01
P50/RTP00Port
RTP
P57/RTP13
P56/RTP12
P55/RTP11
P54/RTP10
P53/RTP03
P52/RTP02
P51/RTP01
P50/RTP00
RTP
RTP
Port : This functions as a programmable I/O port pin.
RTP : This functions as a pulse output pin.
REAL-TIME OUTPUT
7902 Group User’s Manual 11-5
11.2 Block description
11.2.2 Pulse output data registers 0 and 1
Figure 11.2.2 shows the structures of the pulse output data registers 0 and 1. Each of data written into the
pulse output data registers 0 and 1 is output from the corresponding pulse output pins at each underflow
of timers A0 and A2.
The bit position of the RTP02 and RTP03 pulse output data bits depends on the pulse mode. Before setting
the pulse output data registers 0 and 1, be sure to set the pulse output mode select bit (bit 2 at address
A016).
Fig. 11.2.2 Structures of pulse output data registers 0 and 1
WO
WO
WO
WO
Undefined
Undefined
Undefined
Undefined
Undefined
Bit nameBit
0
1
2
3
7 to 4
Pulse output data register 0 (Address A216)
Function At reset R/W
RTP00 pulse output data bit
RTP01 pulse output data bit
RTP02 pulse output data bit
(Valid in pulse mode 0.)
RTP03 pulse output data bit
(Valid in pulse mode 0.)
Nothing is assigned.
0 : “L” level output
1 : “H” level output
Note: When writing to this register, use the MOVM (MOVMB) instruction or STA (STAB, STAD) instruction.
Bit nameBit
1, 0
2
3
4
5
6
7
Pulse output data register 1 (Address A416)
Function At reset R/W
Nothing is assigned.
RTP02 pulse output data bit
(Valid in pulse mode 1.)
RTP03 pulse output data bit
(Valid in pulse mode 1.)
RTP10 pulse output data bit
RTP11 pulse output data bit
RTP12 pulse output data bit
RTP13 pulse output data bit
0 : “L” level output
1 : “H” level output
Note: When writing to this register, use the MOVM (MOVMB) instruction or STA (STAB, STAD) instruction.
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
WO
WO
WO
WO
WO
WO
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
REAL-TIME OUTPUT
7902 Group User’s Manual
11-6
11.2 Block description
After reset, the port P5 pins are floated since these pins are placed in the input mode. The output levels
of the pulse output pins are undefined until timer A0 or A2 underflows first after data for the timer is written.
It is because the pulse output data registers 0 and 1 are undefined after reset.
When avoiding these states, be sure to follow the procedure “Processing of avoiding undefined output
before starting pulse output” in Figures 11.3.1 and 11.3.2.
When reading the port P5 register (address B16), the output values of the pulse output pins can be read
out.
11.2.4 Timers A0 and A2
Data written into the pulse output registers 0 and 1 is output from the corresponding pulse output pins at
each underflow of timer A0 or A2. Refer to section “9.3 Timer mode” for the setting of timers A0 and A2.
Fig. 11.2.3 Relationship between port P5 direction register and pulse output pins
RW
RW
RW
RW
RW
RW
RW
RW
0
1
2
3
4
5
6
7
11.2.3 Port P5 direction register
The pulse output pins are multiplexed with port P5 pins. When using these pins as pulse output pins of
the real-time output, be sure to set the corresponding bits of the port P5 direction register to “1” in order
to set these port pins for the output mode. Figure 11.2.3 shows the relationship between the port P5
direction register and pulse output pins.
Port P5 direction register (Address D16)
Pin RTP00 (Pin TA0OUT)
Pin RTP01 (Pin TA0IN)
Pin RTP02 (Pin TA1OUT)
Pin RTP03 (Pin TA1IN)
Pin RTP10 (Pin TA2OUT/KI0)
Pin RTP11 (Pin TA2IN/KI1)
Pin RTP12 (Pin TA3OUT/KI2)
Pin RTP13 (Pin TA3IN/KI3)
b7 b6 b5 b4 b3 b2 b1 b0
0 : Input mode
1 : Output mode
When using this pin as a pulse output pin, be sure to
set the corresponding bit to “1.”
0
0
0
0
0
0
0
0
Corresponding pinBit Functions At reset R/W
Notes 1: When any of these bits becomes “0,” the corresponding pin becomes an input port pin (floating state), regardless of the
waveform output select bits (bits 0 and 1 at address A016).
2: ( ) shows the I/O pin of another internal peripheral device which is multiplexed.
REAL-TIME OUTPUT
7902 Group User’s Manual 11-7
11.3 Setting of real-time output
Figures 11.3.1 to 11.3.3 show an initial setting example for registers relevant to the real-time output function.
Note that when using interrupts, set up to enable the interrupts. For details, refer to “CHAPTER 7. INTERRUPTS.”
11.3 Setting of real-time output
Fig. 11.3.1 Initial setting example for registers relevant to real-time output (1)
P5
0
–P5
7
pins serve as programmable I/O port pins.
Continue to “Figure 11.3.2”
Processing of avoiding undefined output before starting pulse output (Note)
b7 b0
Set the initial output
level of real-time output.
0 : “L” level
1 : “H” level
RTP0
0
RTP0
1
RTP0
2
RTP0
3
RTP1
0
RTP1
1
RTP1
2
RTP1
3
Port P5 register (Address B
16
)
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AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
Setting of port P5 direction register
b7 b0
Set the bits corresponding to the
selected pulse output pins to “1.”
Note: This processing can be neglected
when the system is not affected
by the undefined output.
Setting of pulse output mode
b7 b0
Real-time output control register (Address A0
16
)
00
Pulse output mode select bit
0 : Pulse mode 0
1 : Pulse mode 1
When pulse mode 0
is selected
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AAAAAAAAAAA
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AAAAAAAAAAA
Setting of output data
b0
0 : “L” level
1 : “H” level
RTP0
0
RTP0
1
RTP0
2
RTP0
3
Pulse output data register 0
(Address A2
16
)
b7
b0
RTP1
0
RTP1
1
RTP1
2
RTP1
3
b7
: It may be either “0” or “1.”
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AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
b0b7
b0b7
RTP0
0
RTP0
1
RTP0
2
RTP0
3
RTP1
0
RTP1
1
RTP1
2
RTP1
3
Port P5 direction register (Address D
16
)
When pulse mode 1
is selected
Setting of output data
Pulse output data register 1
(Address A4
16
)
0 : “L” level
1 : “H” level
✕✕
: It may be either “0” or “1.”
RTP0
0
RTP0
1
0 : “L” level
1 : “H” level
Pulse output data register 0
(Address A2
16
)
Pulse output data register 1
(Address A4
16
)
0 : “L” level
1 : “H” level
RTP0
2
RTP0
3
RTP1
0
RTP1
1
RTP1
2
RTP1
3
REAL-TIME OUTPUT
7902 Group User’s Manual
11-8
Fig. 11.3.2 Initial setting example for registers relevant to real-time output (2)
11.3 Setting of real-time output
From preceding “Figure 11.3.1”
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A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
AAAAAAAAAAAAAAAAAA
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Processing of avoiding undefined output before starting pulse output (Note)
Timer A0 mode register (Address 56
16
)
Timer A2 mode register (Address 58
16
)
Selection of count source f
2
b7
Set to “0000
16
.”
b0 b7 b0
(b15) (b8)
00
16
00
16
b0b7
0
Interrupt disabled
000
Interrupt request bit
b0
Count start register (Address 40
16
)
b7
Timer A0 count start bit 1 : Start counting
When timer A0 or A2 underflows, the contents of the pulse output data register 0 or 1 are output from the flip-flop.
b0b7
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Setting of timers A0 and A2
Count source select bits
See Table 9.2.3.
b7
Can be set to “0000
16
” to “FFFF
16
” (n)
b0 b7 b0
(b15) (b8)
b0b7
Interrupt priority level select bits
When using interrupts, set these bits to one of levels 1 to 7.
When disabling interrupts, set these bits to level 0.
0
Continue to “Figure 11.3.3”
Note: This processing can be neglected when the system
is not affected by the undefined output.
Timer A0 register (Addresses 47
16
, 46
16
)
Timer A2 register (Addresses 4B
16
, 4A
16
)
Timer A0 interrupt control register (Address 75
16
)
Timer A2 interrupt control register (Address 77
16
)
Timer A2 count start bit
Count start register (Address 40
16
)
Timer A0 count start bit
Timer A2 count start bit 0 : Stop counting
Timer A0 mode register (Address 56
16
)
Timer A2 mode register (Address 58
16
)
Timer A0 register (Addresses 47
16
, 46
16
)
Timer A2 register (Addresses 4B
6
, 4A
16
)
Timer A0 interrupt control register (Address 75
16
)
Timer A2 interrupt control register (Address 77
16
)
b0b7
0000 00
b0b7
00
00
Timer A clock division select register (Address 45
16
)
b0b7
0000 00
b0b7
Timer A clock division select bits
See Table 9.2.3.
Timer A clock division select register (Address 45
16
)
Interruput request bit
REAL-TIME OUTPUT
7902 Group User’s Manual 11-9
11.3 Setting of real-time output
Fig. 11.3.3 Initial setting example for registers relevant to real-time output (3)
When pulse mode 0
is selected
Continue to “Figure 11.3.2”
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AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
Selecting real-time output port
b0
0 1 : RTP0
0
–RTP0
3
1 0 : RTP1
0
–RTP1
3
1 1 : RTP0
0
–RTP0
3
and
RTP1
0
–RTP1
3
Real-time output control register
(Address A0
16
)
b7
0
b1 b0
Pulse mode 0
Waveform output select bits
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AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
b0b7
1
Pulse mode 1
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
Setting count start bit to “1”
b0
Count start register (Address 40
16
)
b7
Timer A0 count start bit
Pulse output starts after overflow of timer A0 or A2.
AAA
AAA
AAA
When pulse mode 1
is selected
Selecting real-time output port
Real-time output control register
(Address A0
16
)
0 1 : RTP0
0
, RTP0
1
1 0 : RTP0
2
, RTP0
3
and
RTP1
0
–RTP1
3
1 1 : RTP0
0
–RTP0
3
and
RTP1
0
–RTP1
3
b1 b0
Waveform output select bits
Timer A2 count start bit
REAL-TIME OUTPUT
7902 Group User’s Manual
11-10
11.4 Real-time output operation
11.4 Real-time output operation
When the timer Ai (i = 0, 2) count start bit is set to “1,” the counter starts counting of a count source.
The contents of pulse output data register i are output from the corresponding pulse output pins at each
underflow of timer Ai. The timer is reloaded with the contents of the reload register and continues
counting.
The timer Ai interrupt request bit is set to “1” when the counter underflows in . The interrupt request
bit retains “1” until the interrupt request is accepted or it is cleared by software.
Write the next output data into the pulse output data register i during a timer Ai interrupt routine (or after
the recognition of a timer Ai interrupt request occurrence.)
Figure 11.4.1 shows an example of real-time output operation.
Contents of bits 3 to 0
of pulse output data register 0
RTP03 output
RTP02 output
RTP01 output
RTP00 output
Timer A0 interrupt
request bit
000316
000016
Undefined 2
0011201102110021001200112
Undefi-
ned
3
Starts counting
1
Counter contents
(Hex.)
1 : Written by software
2 : When avoiding undefined output in these terms (in other words, when stabilizing
these output level), be sure to follow the procedure “Processing of avoiding undefined
output before starting pulse output” in Figures 11.3.1 and 11.3.2.
3 : Cleared to “0” by an interrupt request acceptance or cleared by software.
The above applies when the following conditions are satisfied:
•Pulse mode 0 selected
•RTP00 to RTP03 selected
•Timer A0 register set value (n) = 000316
Starts pulse outputting
11111
Undefined 2
Undefined 2
Undefined 2
3333
1
Fig. 11.4.1 Example of real-time output operation
CHAPTER 12CHAPTER 12
SERIAL I/O
12.1 Overview
12.2 Block description
12.3 Clock synchronous serial I/O mode
[Precautions for clock synchronous serial
I/O mode]
12.4 Clock asynchronous serial I/O
(UART) mode
[Precautions for clock asynchronous
serial I/O (UART) mode]
SERIAL I/O
7902 Group User’s Manual
12-2
Clock synchronous serial I/O mode Transfer data length of 8 bits (LSB first)
Transfer data length of 8 bits (MSB first)
UART mode Transfer data length of 7 bits
Transfer data length of 8 bits
Transfer data length of 9 bits
12.1 Overview
Serial I/O consists of 2 channels: UART0 and UART1. They each have a transfer clock generating timer for
the exclusive use of them and can operate independently.
UARTi (i = 0 and 1) has the following 2 operating modes:
(1) Clock synchronous serial I/O mode
Transmitter and receiver use the same clock as the transfer clock. Transfer data has a length of 8
bits.
(2) Clock asynchronous serial I/O (UART) mode
Transfer rate and transfer data format can arbitrarily be set. The user can select one transfer data
length from the following: 7 bits, 8 bits, and 9 bits.
Figure 12.1.1 shows the transfer data formats in each operating mode.
12.1 Overview
Fig. 12.1.1 Transfer data formats in each operating mode
SERIAL I/O
7902 Group User’s Manual 12-3
12.2 Block description
Figure 12.2.1 shows the block diagram of serial I/O. Registers relevant to serial I/O are described below.
12.2 Block description
AA
AA
AA
AA
AA
AA
RxD
i
Data bus (odd)
Data bus (even)
UARTi receive register
UARTi receive
buffer register
UARTi transmit
buffer register
Receive
control circuit
Transmit control
circuit
1 / (n+1)
1/16
1/16
1/2
BRGi
Clock synchronous
(internal clock selected)
UART
Clock
synchronous
UART
Clock synchronous
(internal clock selected)
Clock synchronous
(external clock selected)
Data bus (odd)
Data bus (even)
TxD
i
Transfer clock
Transfer clock
BRG count source
select bits
AA
AA
AA
AA
AA
UARTi transmit register
Bit converter
Bit converter
n: Values set in UARTi baud rate register (BRGi)
Clock
synchronous
D7D6D5D4D3D2D1D0
f2
f16
f64
f512
D8
0000000
D8
D7D6D5D4D3D2D1D0
CTS
i
/RTS
i
CTS
i
/CLK
i
CTS
i
CLK
i
Fig. 12.2.1 Block diagram of serial I/O
SERIAL I/O
7902 Group User’s Manual
12-4
12.2.1 UARTi transmit/receive mode register
Figure 12.2.2 shows the structure of UARTi transmit/receive mode register.
12.2 Block description
Fig. 12.2.2 Structure of UARTi transmit/receive mode register
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
UART0 transmit/receive mode register (Address 3016)
UART1 transmit/receive mode register (Address 3816)
Serial I/O mode select bits
Internal/External clock select bit
Stop bit length select bit
(Valid in UART mode) (Note)
Odd/Even parity select bit
(Valid in UART mode when parity
enable bit = “1.”) (Note)
Parity enable bit
(Valid in UART mode) (Note)
Sleep select bit
(Valid in UART mode) (Note)
RW
RW
RW
RW
RW
RW
RW
RW
b7 b6 b5 b4 b3 b2 b1 b0
Note: Bits 4 to 6 are invalid in the clock synchronous serial I/O mode. (They may be either “0” or “1.”) Additionally, fix bit 7 to “0.”
0 0 0 : Serial I/O is invalid.
(P8 functions as programmable I/O port pins.)
0 0 1 : Clock synchronous serial I/O mode
0 1 0 :
0 1 1 :
1 0 0 : UART mode (Transfer data length = 7 bits)
1 0 1 : UART mode (Transfer data length = 8 bits)
1 1 0 : UART mode (Transfer data length = 9 bits)
1 1 1 : Do not select.
b2 b1b0
0 : Internal clock
1 : External clock
0 : One stop bit
1 : Two stop bits
0 : Odd parity
1 : Even parity
0 : Parity disabled
1 : Parity enabled
0 : Sleep mode terminated (Invalid)
1 : Sleep mode selected
Do not select.
Bit nameBit Function At reset R/W
SERIAL I/O
7902 Group User’s Manual 12-5
(1) Serial I/O mode select bits (bits 0 to 2)
These bits select a UARTi’s operating mode.
(2) Internal/External clock select bit (bit 3)
Clock synchronous serial I/O mode
By clearing this bit to “0” in order to select an internal clock, the clock which is selected with the
BRG count source select bits (bits 0 and 1 at addresses 3416, 3C16) becomes the count source of
the BRGi. (Refer to section “12.2.6 UARTi baud rate register (BRGi).”) The BRGi’s output
divided by 2 becomes the transfer clock. Additionally, the transfer clock is output from the CLKi
pin.
By setting this bit to “1” in order to select an external clock, the clock input to the CLKi pin
becomes the transfer clock.
UART mode
By clearing this bit to “0” in order to select an internal clock, the clock which is selected with the
BRG count source select bits (bits 0 and 1 at addresses 3416, 3C16) becomes the count source of
the BRGi. (Refer to section “12.2.6 UARTi baud rate register (BRGi).”) Then, the CLKi pin
functions as a programmable I/O port pin.
By setting this bit to “1” in order to select an external clock, the clock input to the CLKi pin
becomes the count source of BRGi.
Always in the UART mode, the BRGi’s output divided by 16 becomes the transfer clock.
(3) Stop bit length select bit, Odd/Even parity select bit, Parity enable bit (bits 4 to 6)
Refer to section “12.4.2 Transfer data format.”
(4) Sleep select bit (bit 7)
Refer to section “12.4.8 Sleep mode.”
12.2 Block description
SERIAL I/O
7902 Group User’s Manual
12-6
12.2 Block description
12.2.2 UARTi transmit/receive control register 0
Figure 12.2.3 shows the structure of UARTi transmit/receive control register 0.
Fig. 12.2.3 Structure of UARTi transmit/receive control register 0
UART0 transmit/receive control register (Address 3416)
UART1 transmit/receive control register (Address 3C16)
0
1
2
3
4
5
6
7
BRG count source select bits
CTS/RTS function select bit
(Note 1)
Transmit register empty flag
CTS/RTS enable bit
UARTi receive interrupt mode
select bit
CLK polarity select bit
(This bit is used in the clock
synchronous serial I/O mode.)
(Note 2)
Transfer format select bit
(This bit is used in the clock
synchronous serial I/O mode.)
(Note 2)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : Clock f2
0 1 : Clock f16
1 0 : Clock f64
1 1 : Clock f512
0 : The CTS function is selected.
1 : The RTS function is selected.
0 : Data is present in the transmit register.
(Transmission is in progress.)
1 : No data is present in the transmit register.
(Transmission is completed.)
0 : The CTS/RTS function is enabled.
1 : The CTS/RTS function is disabled.
0 : Reception interrupt
1 : Reception error interrupt
0 : At the falling edge of the transfer clock, transmit
data is output; at the rising edge of the transfer
clock, receive data is input.
When not in transferring, pin CLKi’s level is “H.”
1 : At the falling edge of the transfer clock, transmit
data is output; at the falling edge of the transfer
clock, receive data is input.
When not in transferring, pin CLKi’s level is “L.”
0 : LSB (Least Significant Bit) first
1 : MSB (Most Significant Bit) first
b1 b0
Notes 1: Valid when the CTS/RTS enable bit (bit 4) is “0” and CTSi/RTSi separate select bit (bit 0 or 1 at address AC16) is “0.”
2: Fix these bits to “0” in the UART mode or when serial I/O is disabled.
0
0
0
1
0
0
0
0
RW
RW
RW
RO
RW
RW
RW
RW
Bit nameBit Function At reset R/W
SERIAL I/O
7902 Group User’s Manual 12-7
(1) BGR count source select bit (bits 0 and 1)
Refer to section “12.2.1 (2) Internal/External clock select bit.”
(2)
________
CTS/RTS function select bit (bit 2)
________
Refer to section “12.2.10 CTS/RTS function.”
(3) Transmit register empty flag (bit 3)
This flag is cleared to “0” when the UARTi transmit buffer register’s contents have been transferred
to the UARTi transmit register. When transmission has been completed and the UARTi transmit
register becomes empty, this flag is set to “1.”
(4)
________
CTS/RTS enable bit (bit 4)
________
Refer to section “12.2.10 CTS/RTS function.”
(5) UARTi receive interrupt mode select bit (bit 5)
Refer to section “12.2.7 (2) Interrupt request bit.”
(6) CLK polarity select bit (bit 6)
Refer to section “12.3.1 (3) Polarity of transfer clock.”
(7) Transfer format select bit (bit 7)
Refer to section “12.3.2 Transfer data format.”
12.2 Block description
SERIAL I/O
7902 Group User’s Manual
12-8
12.2 Block description
12.2.3 UARTi transmit/receive control register 1
Figure 12.2.4 shows the structure of UARTi transmit/receive control register 1.
Fig. 12.2.4 Structure of UARTi transmit/receive control register 1
UART0 transmit/receive control register 1 (Address 3516)
UART1 transmit/receive control register 1 (Address 3D16)
0
1
2
3
4
5
6
7
Transmit enable bit
Transmit buffer empty flag
Receive enable bit
Receive complete flag
Overrun error flag
Framing error flag (Note)
(Valid in UART mode)
Parity error flag (Note)
(Valid in UART mode)
Error sum flag (Note)
(Valid in UART mode)
b7 b6 b5 b4 b3 b2 b1 b0
0 : Reception disabled
1 : Reception enabled
0 : No data is present in the receive buffer register
1 : Data is present in the receive buffer register
Note: Bits 5 to 7 are invalid in the clock synchronous serial I/O mode.
0 : Transmission disabled
1 : Transmission enabled
0 : Data is present in the transmit buffer register
1 : No data is present in the transmit buffer register
0 : No parity error
1 : Parity error detected
0 : No error
1 : Error detected
0 : No overrun error
1 : Overrun error detected
0 : No framing error
1 : Framing error detected
0
1
0
0
0
0
0
0
RW
RO
RW
RO
RO
RO
RO
RO
Bit nameBit Function At reset R/W
SERIAL I/O
7902 Group User’s Manual 12-9
(1) Transmit enable bit (bit 0)
By setting this bit to “1,” UARTi enters the transmission-enabled state. By clearing this bit to “0”
during transmission, UARTi enters the transmission-disabled state after the transmission which was
in progress at that time is completed.
(2) Transmit buffer empty flag (bit 1)
This flag is set to “1” when data set in the UARTi transmit buffer register has been transferred from
the UARTi transmit buffer register to the UARTi transmit register. This flag is cleared to “0” when data
has been set in the UARTi transmit buffer register.
(3) Receive enable bit (bit 2)
By setting this bit to “1,” UARTi enters the reception-enabled state. By clearing this bit to “0” during
reception, UARTi quits the reception immediately and enters the reception-disabled state.
(4) Receive complete flag (bit 3)
This flag is set to “1” when data has been ready in the UARTi receive register and that has been
transferred to the UARTi receive buffer register (i.e., when reception is completed). This flag is
cleared to “0” in one of the following cases:
• When the low-order byte of the UARTi receive buffer register has been read out
• When the receive enable bit (bit 2) has been cleared to “0”
(5) Overrun error flag (bit 4)
Refer to section “12.3.7 Processing on detecting overrun error” and “12.4.7 Processing on
detecting error.”
(6) Framing error flag, Parity error flag, Error sum flag (bits 5 to 7)
Refer to section “12.4.7 Processing on detecting error.”
12.2 Block description
SERIAL I/O
7902 Group User’s Manual
12-10
12.2.4 UARTi transmit register and UARTi transmit buffer register
Figure 12.2.5 shows the block diagram for the transmitter; Figure 12.2.6 shows the structure of UARTi
transmit buffer register.
12.2 Block description
Fig. 12.2.5 Block diagram for transmitter
SP SP PAR
0
2SP
1SP
UART
8-bit UART 7-bit UART
9-bit UART
Clock sync.
Clock sync.
Data bus (even)
Data bus (odd)
TxD
i
UARTi transmit register
Parity
enabled
Parity
disabled
D8D7D6D5D4D3D2D1D0
SP : Stop bit
PAR : Parity bit
UARTi transmit
buffer register
8-bit UART
9-bit UART
AA
AA
AA
7-bit UART
Clock sync.
Fig. 12.2.6 Structure of UARTi transmit buffer register
UART0 transmit buffer register (Addresses
33
16
, 32
16
)
UART1 transmit buffer register (Addresses
3B
16
, 3A
16
)
8 to 0
15 to 9
b0
Note: Use the MOVM (MOVMB) or STA (STAB, STAD) instruction for writing to this register.
b7
b0b7
(b15) (b8)
Transmit data is set.
Nothing is assigned.
Undefined
Undefined
WO
Bit Function At reset R/W
SERIAL I/O
7902 Group User’s Manual 12-11
Transmit data is set into the UARTi transmit buffer register. Set the transmit data into the low-order byte
of this register when the microcomputer operates in the clock synchronous serial I/O mode or when a 7-
bit or 8-bit length of transfer data is selected in the UART mode. When a 9-bit length of transfer data is
selected in the UART mode, set the transmit data into the UARTi transmit buffer register as follows:
Bit 8 of the transmit data into bit 0 of high-order byte of this register.
Bits 7 to 0 of the transmit data into the low-order byte of this register.
The transmit data which has been set in the UARTi transmit buffer register is transferred to the UARTi
transmit register when the transmission conditions are satisfied, and then it is output from the TxDi pin
synchronously with the transfer clock. The UARTi transmit buffer register becomes empty when the data
set in the UARTi transmit buffer register has been transferred to the UARTi transmit register. Accordingly,
the user can set the next transmit data.
When the “MSB first” is selected in the clock synchronous serial I/O mode, bit position of set data is
reversed, and then the data of which bit position was reversed will be written, as a transmit data, into the
UARTi transmit buffer register. (Refer to section “12.3.2 Transfer data format.”) Transmit operation itself
is the same whichever format is selected, “LSB first” or “MSB first.”
When quitting the transmission which is in progress and setting the UARTi transmit buffer register again,
follow the procedure described bellow:
Clear the serial I/O mode select bits (bits 2 to 0 at addresses 3016, 3816) to “0002” (serial I/O disabled).
Set the serial I/O mode select bits again.
Set the transmit enable bit (bit 0 at addresses 3516, 3D16) to “1” (transmission enabled) and set transmit
data in the UARTi transmit buffer register.
12.2 Block description
SERIAL I/O
7902 Group User’s Manual
12-12
12.2.5 UARTi receive register and UARTi receive buffer register
Figure 12.2.7 shows the block diagram of the receiver; Figure 12.2.8 shows the structure of UARTi receive
buffer register.
12.2 Block description
Fig. 12.2.7 Block diagram of receiver
AA
AA
A
A
A
A
Clock sync.
SP
SP PAR
2SP
1SP
UART
0000000
RxD
i
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
SP : Stop bit
PAR : Parity bit
8-bit UART
9-bit UART
7-bit UART
9-bit UART Clock sync.
Clock sync.
7-bit UART
8-bit UART
Data bus (even)
Data bus (odd)
UARTi receive register
Parity
enabled
Parity
disabled
UARTi receive
buffer register
AA
AA
AA
AA
Fig. 12.2.8 Structure of UARTi receive buffer register
UART0 transmit buffer register (Addresses
37
16
, 36
16
)
UART1 transmit buffer register (Addresses
3F
16
, 3E
16
)
8 to 0
15 to 9
b0
b7
b0b7
(b15) (b8)
Receive data is read out from here.
The value is “0” at reading.
Undefined
0
RO
Bit Function At reset R/W
SERIAL I/O
7902 Group User’s Manual 12-13
The UARTi receive register is used to convert serial data, which is input to the RxDi pin, into parallel data.
This register takes in the signal input to the RxDi pin, bit by bit, synchronously with the transfer clock.
The UARTi receive buffer register is used to read out receive data. When reception has been completed,
the receive data taken in the UARTi receive register is automatically transferred to the UARTi receive
buffer register. Note that the contents of the UARTi receive buffer register is updated when the next data
has been ready in the UARTi receive register before the data transferred to the UARTi receive buffer
register is read out. (i.e., an overrun error occurs.)
When “MSB first” is selected in the clock synchronous serial I/O mode, bit position of data in the UARTi
receive buffer register is reversed, and then the data of which bit position was reversed will be read out
as transmit data. (Refer to section “12.3.2 Transfer data format.”) Receive operation itself is the same
whichever format is selected, “LSB first” or “MSB first.”
The UARTi receive buffer register is initialized by setting the receive enable bit (bit 2 at addresses 3516,
3D16) to “1” after clearing it to “0.”
Figure 12.2.9 shows the contents of the UARTi receive buffer register at reception completed.
12.2 Block description
b7 b0 b7 b0
0000000
0000000
0000000
Receive data (9 bits)
Receive data (8 bits)
Receive data (7 bits)
UART mode
(Transfer data length : 9 bits)
Clock synchronous
serial I/O mode,
UART mode
(Transfer data length : 8 bits)
UART mode
(Transfer data length : 7 bits)
Same value as bit
7 in low-order byte
Same value as bit
6 in low-order byte
High-order byte
(addresses 3716, 3F16)Low-order byte
(addresses 3616, 3E16)
Fig. 12.2.9 Contents of UARTi receive buffer register at reception completed
SERIAL I/O
7902 Group User’s Manual
12-14
12.2.6 UARTi baud rate register (BRGi)
The UARTi baud rate register (BRGi) is an 8-bit timer exclusively used for UARTi to generate a transfer
clock. It has a reload register. Assuming that the value set in the BRGi is “n” (n = “0016” to “FF16”), the BRGi
divides the count source frequency by (n + 1).
In the clock synchronous serial I/O mode, the BRGi is valid when an internal clock is selected, and the
BRGi’s output divided by 2 becomes the transfer clock. In the UART mode, the BRGi is always valid, and
the BRGi’s output divided by 16 becomes the transfer clock.
The data written to the BRGi is written to both the timer and the reload register whichever transmission/
reception is in progress or not. Accordingly, writing to these register must be performed while transmission/
reception halts.
Figure 12.2.10 shows the structure of the UARTi baud rate register (BRGi); Figure 12.2.11 shows the block
diagram of transfer clock generating section.
12.2 Block description
BRGi 1/2 Transmit control circuit
Receive control circuit
Transfer clock for transmit operation
Transfer clock for receive operation
Transmit control circuit
Receive control circuit
Transfer clock for transmit operation
Transfer clock for receive operation
BRGi 1/16
<Clock synchronous serial I/O mode>
<UART mode>
fi : Clock selected by BRG count source select bits (f2, f16, f64, or f512)
fEXT : Clock input to CLKi pin (external clock)
1/16
fi
fEXT
fEXT
fi
Fig. 12.2.11 Block diagram of transfer clock generating section
Undefined
7 to 0
UART0 baud rate register (BRG0) (Address 3116)
UART1 baud rate register (BRG1) (Address 3916)
Can be set to “0016” to “FF16.”
Assuming that the set value = n, BRGi divides the count source frequency by (n + 1). WO
b0
Note: Writing to this register must be performed while the transmission/reception halts.
Use the MOVM (MOVMB) or STA (STAB, STAD) instruction for writing to this register.
b7
Bit Function At reset R/W
Fig. 12.2.10 Structure of UARTi baud rate register (BRGi)
SERIAL I/O
7902 Group User’s Manual 12-15
12.2.7 UARTi transmit interrupt control and UARTi receive interrupt control registers
When using UARTi, 2 types of interrupts (UARTi transmit and UARTi receive interrupts) can be used. Each
interrupt has its corresponding interrupt control register. Figure 12.2.12 shows the structure of UARTi
transmit interrupt control and UARTi receive interrupt control registers.
For details about these interrupts, refer to “CHAPTER 7. INTERRUPTS.”
For the UARTi receive interrupt, a receive or receive error interrupt can be selected by the UARTi receive
interrupt mode selected bit (bit 5 at addresses 3416, 3C16).
12.2 Block description
Fig. 12.2.12 Structure of UARTi transmit interrupt control and UARTi receive interrupt control registers
UART0 transmit interrupt control registers (Address 7116)
UART0 receive interrupt control registers (Address 7216)
UART1 transmit interrupt control registers (Address 7316)
UART1 receive interrupt control registers (Address 7416)b7 b6 b5 b4 b3 b2 b1 b0
0
1
2
3
7 to 4
Interrupt priority level select bits
Interrupt request bit
Nothing is assigned.
Note: When writing to this bit, use the MOVM (MOVMB) or STA (STAB, STAD) instruction.
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1b0
0 : No interrupt requested
1 : Interrupt requested
0
0
0
0
Undefined
RW
RW
RW
RW
(Note)
Bit nameBit Function At reset R/W
SERIAL I/O
7902 Group User’s Manual
12-16
12.2 Block description
(1) Interrupt priority level select bits (bits 0 to 2)
These bits select a priority level of the UARTi transmit interrupt or UARTi receive interrupt. When
using UARTi transmit/receive interrupts, select one of the priority levels (1 to 7). When a UARTi
transmit/receive interrupt request occurs, its priority level is compared with the processor interrupt
priority level (IPL). The requested interrupt is enabled only when its priority level is higher than the
IPL. (However, this applies when the interrupt disable flag (I) = “0.”) To disable UARTi transmit/
receive interrupts, be sure to set these bits to “0002” (level 0).
(2) Interrupt request bit (bit 3)
The UARTi transmit interrupt request bit is set to “1” when data has been transferred from the UARTi
transmit buffer register to the UARTi transmit register.
The UARTi receive interrupt request bit functions as below:
When receive interrupt is selected (bit 5 = 0 at addresses 3416, 3C16)
The UARTi receive interrupt request bit is set to “1” when data has been transferred from the
UARTi receive register to the UARTi receive buffer register.
(However, the UARTi receive interrupt request bit does not change when an overrun error has
occurred.)
When receive error interrupt is selected (bit 5 = 1 at addresses 3416, 3C16)
The UARTi receive interrupt request bit is set to “1” when an error (an overrun error in the clock
synchronous serial I/O mode; an overrun error, framing error, or parity error in UART mode) has
occurred.
Each interrupt request bit is automatically cleared to “0” when its corresponding interrupt request has
been accepted. This bit can be set to “1” or cleared to “0” by software.
SERIAL I/O
7902 Group User’s Manual 12-17
Fig. 12.2.13 Structure of serial I/O pin control register
(1) CTS0/RTS0 separate select bit (bit 0)
Refer to section “12.2.10 CTS/RTS function.”
(2) CTS1/RTS1 separate select bit (bit 1)
Refer to section “12.2.10 CTS/RTS function.”
(3) TxD0/P83 switch bit (bit 2)
When this bit is set to “1,” the TxD0 pin functions as a programmable I/O port pin (P83). When only
reception is performed in the clock synchronous serial I/O mode, the TxD0 pin can be used as the
P83 pin. When performing transmission, be sure to clear this bit to “0.”
(4) TxD1/P87 switch bit (bit 3)
When this bit is set to “1,” the TxD1 pin functions as a programmable I/O port pin (P87). When only
reception is performed in the clock asynchronous serial I/O mode, the TxD1 pin can be used as the
P87 pin. When preforming transmission, be sure to clear this bit to “0.”
12.2 Block description
12.2.8 Serial I/O pin control register
Figure 12.2.13 shows the structure of the seral I/O pin control register.
Serial I/O pin control register (Address AC16)b7 b6 b5 b4 b3 b2 b1 b0
0
1
2
3
7 to 4
CTS0/RTS0 separate select bit
(Note)
CTS1/RTS1 separate select bit
(Note)
TxD0/P83 switch bit
TxD1/P87 switch bit
The value is “0” at reading.
0 : CTS0/RTS0 are used together.
1 : CTS0/RTS0 are separated.
0 : Functions as TxD1.
1 : Functions as P87.
RW
RW
RW
RW
Bit nameBit Function At reset R/W
0 : CTS1/RTS1 are used together.
1 : CTS1/RTS1 are separated.
0 : Functions as TxD0.
1 : Functions as P83.
0
0
0
0
0
Note: Valid when the CTS/RTS enable bit (bit 4 at addresses 3416 and 3C16) is “0.”
SERIAL I/O
7902 Group User’s Manual
12-18
12.2 Block description
12.2.9 Port P8 direction register
I/O pins for serial I/O are multiplexed with port P8 pins. When using pins P81, P82, P85, and P86 as serial
I/O’s input pins (CTSi, RxDi), clear the corresponding bits of the port P8 direction register to “0” in order
to set these pins for the input mode. When using these pins as other serial I/O’s pins (CTSi/RTSi, CLKi,
TxDi), these pins are forcibly set as I/O pins for serial I/O regardless of the port P8 direction register’s
contents. Figure 12.2.14 shows the relationship between the port P8 direction register and serial I/O’s
I/O pins. For details, refer to the description of each operating mode.
Fig. 12.2.14 Relationship between port P8 direction register and serial I/O’s I/O pins
Corresponding pin nameBit
0
1
2
3
4
5
6
7
Port P8 direction register (Address
14
16
)
Function
At reset
R/W
Pin CTS0/RTS0 (Pin DA2/INT3)
Pin CTS0/CLK0
Pin RxD0
Pin TxD0
Pin CTS1/RTS1 (Pin INT4)
Pin CTS1/CLK1
Pin RxD1
Pin TxD1
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
b7 b6 b5 b4 b3 b2 b1 b0
0 : Input mode
1 : Output mode
When using pins P81, P82, P85, and P86 as serial
I/O’s input pins (CTS0, RxD 0, CTS1, RxD1), clear
the corresponding bits to “0.”
Note: ( ) shows the I/O pin of another internal peripheral device which is multiplexed.
SERIAL I/O
7902 Group User’s Manual 12-19
12.2.10 CTS/RTS function
When the CTS function is selected, the signal input to the CTSi pin must be at “L” level. (This is one of
the transmit conditions.)
When the RTS function is selected, the RTSi pin outputs the following signals:
(1) Clock synchronous serial I/O mode
When the receive enable bit (bit 2 at addresses 3516, 3D16) = “0” (reception disabled), the RTSi pin
outputs “H” level.
When the receive enable bit = “0” (reception disabled), the RTSi pin outputs “L” level by setting the
receive enable bit to “1,” or by reading the low-order byte of the UARTi receive buffer register.
When the receive enable bit = “1” (continuously reception), the RTSi pin outputs “L” level by reading
the low-order byte of the UARTi receive buffer register.
When reception has started, the RTSi pin outputs “H” level.
When an internal clock is selected (bit 3 at addresses 3016, 3816 = “0”), do not select the RTS function
because the RTS output is undefined.
(2) UART mode
When the receive enable bit (bit 2 at addresses 3516, 3D16) = “0” (reception disabled), the RTSi pin
outputs “H” level.
When the receive enable bit = “0” (reception disabled), the RTSi pin outputs “L” level by setting the
receive enable bit to “1,” or by reading the low-order byte of the UARTi receive buffer register.
When the receive enable bit = “1” (continuously reception), the RTSi pin outputs “L” level by reading
the low-order byte of the UARTi receive buffer register.
When reception has started, the RTSi pin outputs “H” level.
Selection of the CTS/RTS function depends on the following bits.
•CTS/RTS function select bit (bit 2 at addresses 3416, 3C16: see Figure 12.2.3.)
•CTS/RTS enable bit (bit 4 at addresses 3416, 3C16: see Figure 12.2.3.)
•CTS0/RTS0 separate select bit (bit 0 at address AC16: see Figure 12.2.13.)
•CTS1/RTS1 separate select bit (bit 1 at address AC16: see Figure 12.2.13.)
Table 12.2.1 lists the selection of the CTS/RTS function.
12.2 Block description
: It may be either “0” or “1.”
Notes 1: When using the CTS0/RTS0 pin, be sure that the D-A2 output enable bit (bit 2 at address 9616) =
“0” (output disabled).
2: When using the P81 or P85 pin as the CTS pin, be sure to clear the corresponding bit of the port
P8 direction register to “0.”
3: When CTSi/RTSi separation is selected, the CLKi pin cannot be used. Accordingly, CTSi/RTSi
cannot be separated in the clock synchronous serial I/O mode. When separating CTSi/RTSi in
UART mode, be sure to select an internal clock.
Table 12.2.1 Selection of CTS/RTS function
0
1
0
1
CTS/RTS
enable bit Functions
0
1
CTSi/RTSi
separate select bit
CTS/RTS
function select bit
P80/CTS0/RTS0 pin (Note 1)
CTS0
RTS0
RTS0
P80
P81 or CLK0
P81 or CLK0
CTS0 (Notes 2, 3)
P81 or CLK0
P81/CTS0/CLK0 pin P84/CTS1/RTS1 pin
CTS1
RTS1
RTS1
P84
P85 or CLK1
P85 or CLK1
CTS1 (Notes 2, 3)
P85 or CLK1
P85/CTS1/CLK1 pin
SERIAL I/O
7902 Group User’s Manual
12-20
12.3 Clock synchronous serial I/O mode
12.3 Clock synchronous serial I/O mode
Table 12.3.1 lists the performance overview in the clock synchronous serial I/O mode, and Table 12.3.2 lists
the functions of I/O pins in this mode.
Table 12.3.1 Performance overview in clock synchronous serial I/O mode
Item
Transfer data format
Transfer rate
Transmit/Receive control
When selecting internal clock
When selecting external clock
Functions
Transfer data has a length of 8 bits.
LSB first or MSB first can be selected by software.
BRGi’s output divided by 2
Maximum 5 Mbps
CTS function or RTS function can be selected by software.
Table 12.3.2 Functions of I/O pins in clock synchronous serial I/O mode
Functions
Serial data output pin
Programmable I/O port pin
Serial data input pin
Transfer clock output pin
Transfer clock input pin
CTS input pin
RTS output pin
Programmable I/O port pin
Pin name
TxDi (P83, P87)
RxDi (P82, P86)
CLKi (P81, P85)
CTSi, RTSi
(P80, P81, P84, P85)
Method of selection
(Dummy data is output when performing only reception.) (Note)
TxD0/P83 or TxD1/P87 switch bit = “1”
Port P8 direction register’s corresponding bit = “0”
(Can be used as an I/O port pin when performing only transmission.)
Internal/External clock select bit = “0”
Internal/External clock select bit = “1”
See Table 12.2.1.
Port P8 direction register: address 1416
Internal/External clock select bit: bit 3 at addresses 3016, 3816
TxD0/P83 switch bit: bit 2 at address AC16
TxD1/P87 switch bit: bit 3 at address AC16
Note: The TxDi pin outputs “H” level until transmission starts after UARTi’s operating mode is selected.
12.3.1 Transfer clock (Synchronizing clock)
Data transfer is performed synchronously with a transfer clock. For the transfer clock, the following selection
is possible:
Whether to generate a transfer clock internally or to input it from the external.
Polarity of transfer clock.
The transfer clock is generated by operation of the transmit control circuit. Accordingly, even when performing
only reception, set the transmit enable bit to “1,” and set dummy data in the UARTi transmit buffer register
in order to make the transmit control circuit active.
(1) Internal generation of transfer clock
The count source selected with the BRG count source select bits is divided by the BRGi, and the
BRGi output is further divided by 2. This divided output is the transfer clock. The transfer clock is
output from the CLKi pin.
Transfer clock’s frequency = fi: Frequency of BRGi’s count source (f2, f16, f64, or f512)
n: Setting value of BRGi
fi
2 (n+1)
SERIAL I/O
7902 Group User’s Manual 12-21
12.3 Clock synchronous serial I/O mode
(2) Input of transfer clock from the external
A clock input from the CLKi pin becomes the transfer clock.
(3) Porarity of transfer clock
As shown in Figure 12.3.1, the polarity of the transfer clock can be selected by the CLK polarity
select bit (bit 6 at addresses 3416, 3C16).
Fig. 12.3.1 Polarity of transfer clock
CLK polarity select bit = 0
CLKi
D0D1D2D3D4D5D6D7
D0D1D2D3D4D5D6D7
The transmit data is output to the TxDi pin at the falling edge of a transfer clock, and the receive data is
input from the RxDi pin at the rising edge of the transfer clock.
The level at the CLKi pin is “H” when the transfer is not performed.
CLK polarity select bit = 1
D0D1D2D3D4D5D6D7
D0D1D2D3D4D5D6D7
The transmit data is output to the TxDi pin at the rising edge of a transfer clock, and the receive data is
input from the RxDi pin at the falling edge of the transfer clock.
The level at the CLKi pin is “L” when the transfer is not performed.
TxDi
RxDi
CLKi
TxDi
RxDi
SERIAL I/O
7902 Group User’s Manual
12-22
12.3 Clock synchronous serial I/O mode
12.3.2 Transfer data format
LSB first or MSB first can be selected as the transfer data format. Table 12.3.3 lists the relationship
between the transfer data format and writing/reading to and from the UARTi transmit/receive buffer register.
The transfer format select bit (bit 7 at addresses 3416, 3C16) selects the transfer data format. When this bit
is cleared to “0,” the set data is written to the UARTi transmit buffer register as the transmit data, as it is.
Similarly, the data in the UARTi receive buffer register is read out as the receive data, as it is. (See the
upper row in Table 12.3.3.) When this bit is set to “1,” each bit’s position of set data is reversed, and the
resultant data will be written to the UARTi transmit buffer register as the transmit data. Similarly, each bit’s
position of data in the UARTi receive buffer register is reversed, and the resultant data will be read out
as the receive data. (See the lower row in Table 12.3.3.)
Note that only the method of writing/reading to and from the UARTi transmit/receive buffer register is
affected by selection of the transfer data format, and that the transmit/receive operation is unaffected by
it.
Table 12.3.3 Relationship between transfer data format and writing/reading to and from UARTi transmit/
receive buffer register
Writing to UARTi transmit buffer
register Reading from UARTi receive
buffer register
Data bus UARTi transmit
buffer register
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
Data bus UARTi receive
buffer register
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
LSB
(Least Significant Bit)
first
Data bus UARTi transmit
buffer register
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Data bus UARTi receive
buffer register
MSB
(Most Significant Bit)
first
Transfer data format
Transfer format
select bit
0
1
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
SERIAL I/O
7902 Group User’s Manual 12-23
12.3 Clock synchronous serial I/O mode
12.3.3 Method of transmission
Figure 12.3.2 shows an initial setting example for relevant registers when transmitting. Transmission is
started when all of the following conditions ( to ) has been satisfied. When an external clock is selected,
satisfy conditions to with the following preconditions satisfied.
<Preconditions>
The CLKi pin’s input is at “H” level (External clock selected, when the CLK polarity select bit = “0”)
The CLKi pin’s input is at “L” level (External clock selected, when the CLK polarity select bit = “1”)
Note: When an internal clock is selected, the above preconditions are ignored.
Transmit data is present in the UARTi transmit buffer register (transmit buffer empty flag = “0”)
Transmission is enabled (transmit enable bit = “1”).
The CTSi pin’s input is at “L” level (when the CTS function selected).
Note: When the CTS function is not selected, condition is ignored.
By connecting the RTSi pin (receiver side) and CTSi pin (transmitter side), the timing of transmission and
that of reception can be matched. For details, refer to section “12.3.6 Receive operation.”
When using interrupts, it is necessary to set the relevant registers to enable interrupts. For details, refer
to “CHAPTER 7. INTERRUPTS.”
Figure 12.3.3 shows the write operation of data after transmission start, and Figure 12.3.4 shows the detect
operation of transmit completion.
SERIAL I/O
7902 Group User’s Manual
12-24
12.3 Clock synchronous serial I/O mode
Fig. 12.3.2 Initial setting example for relevant registers when transmitting
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
0
UART0 transmit/receive mode register (Address 30
16
)
UART1 transmit/receive mode register (Address 38
16
)
b7 b0
Internal/External clock select bit
0: Internal clock
1: External clock
✕✕
: It may be either “0” or “1.”
Selection of clock synchronous serial
I/O mode
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
UART0 transmit/receive control register 0 (Address 34
16
)
UART1 transmit/receive control register 0 (Address 3C
16
)
b7 b0
BRG count source select bits
CTS
/
RTS
function select bit
0:
CTS
function selected
1:
RTS
function selected
AA
AA
AA
AA
A
A
AA
AA
0 0 : f
2
0 1 : f
16
1 0 : f
64
1 1 : f
512
b1 b0
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
Transmission starts.
UART0 transmit buffer register (Address 32
16
)
UART1 transmit buffer register (Address 3A
16
)
b7 b0
Transmit data is set.
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
1
UART0 transmit/receive control register 1 (Address 35
16
)
UART1 transmit/receive control register 1 (Address 3D
16
)
b7 b0
Transmit enable bit
1: Transmission is enabled.
AAAA
AAAA
AAAA
(In the case of selecting the
CTS
function, transmission
starts when the
CTS
0 pin’s input level is “L.”)
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
UART0 baud rate register (BRG0) (Address 31
16
)
UART1 baud rate register (BRG1) (Address 39
16
)
b7 b0
Can be set to “00
16
” to “FF
16
.”
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
UART0 transmit interrupt control register (Address 71
16
)
UART1 transmit interrupt control register (Address 73
16
)
b7 b0
Interrupt priority level select bits
When using interrupts, set these bits to
one of levels 1 to 7.
When disabling interrupts, set these bits
to level 0.
CTS
/
RTS
enable bit
0:
CTS
/
RTS
function is enabled.
1:
CTS
/
RTS
function is disabled.
CLK polarity select bit
0: At the falling edge of the transfer
clock, transmit data is output.
1: At the rising edge of the transfer
clock, transmit data is output.
Transfer format select bit
0: LSB first
1: MSB first
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
Serial I/O pin control register (Address AC
16
)
b7 b0
AA
AA
A
A
AA
AA
CTS
0
/RTS
0
separate select bit
0: CTS
0
/RTS
0
are used together (Note).
Note: In the clock synchronous serial I/O
mode, CTS
i
/RTS
i
separation cannot
be selected. (Refer to section “[Pre-
cautions for clock synchronous
serial I/O mode].”)
When extenal clock is selected
When internal clock is selected
100
CTS
1
/RTS
1
separate select bit
0: CTS
1
/RTS
1
are used together (Note).
TxD
0
/P8
3
switch bit
0: Functions as TxD
0
.
TxD
1
/P8
7
switch bit
0: Functions as TxD
1
.
SERIAL I/O
7902 Group User’s Manual 12-25
12.3 Clock synchronous serial I/O mode
Fig. 12.3.4 Detect operation of transmit completion
[When not using interrupts] [When using interrupts]
AAA
AAA
AAA
UARTi transmit interrupt
UART0 transmit interrupt control register (Address 71
16
)
UART1 transmit interrupt control register (Address 73
16
)
b7 b0
Interrupt request bit
Checking start of transmission
UART0 transmit/receive control register 0 (Address 34
16
)
UART1 transmit/receive control register 0 (Address 3C
16
)
b7 b0
A
A
Checking completion of transmission
Transmit register empty flag
0: Transmission is in progress.
1: Transmission is completed.
Processing at completion of transmission
0: No interrupt requested
1: Interrupt requested
(Transmission has started.)
A UARTi transmit interrupt request
occurs when the transmission starts.
Note: This figure shows the bits and registers required
for processing.
See Figures 12.3.6 and 12.3.7 for the change
of flag state and the occurrence timing of an
interrupt request.
[When not using interrupts] [When using interrupts]
A UARTi transmit interrupt request occurs
when the transbission starts (when the
UARTi transmit buffer register becomes
empty).
AAA
AAA
AAA
UARTi transmit interrupt
Note:
UART0 transmit buffer register (Address 3216)
UART1 transmit buffer register (Address 3A16)
b7 b0
Writing of next transmit data
Transmit data is set.
b0
UART0 transmit/receive control register 1 (Address 3516)
UART1 transmit/receive control register 1 (Address 3D16)
b7
Transmit buffer empty flag
0: Data is present in transmit buffer register.
1: No data is present in transmit buffer register.
(Writing of next transmit data is possible.)
Checking state of UARTi transmit buffer register
1
This figure shows the bits and registers required
for processing.
See Figures 12.3.6 and 12.3.7 for the change of
flag state and the occurrence timing of an interrupt
request.
b0
Fig. 12.3.3 Write operation of data after transmission start
SERIAL I/O
7902 Group User’s Manual
12-26
12.3 Clock synchronous serial I/O mode
12.3.4 Transmit operation
When the transmit conditions described in section “12.3.3 Method of transmission” have been satisfied
in the case of an internal clock selected, a transfer clock is generated and the following operations are
automatically performed after 1 cycle of the transfer clock or less has passed. In the case of an external
clock selected, when the transmit conditions have been satisfied and then an external clock is input to the
CLKi pin, the following operations are automatically performed:
•The UARTi transmit buffer register’s contents are transferred to the UARTi transmit register.
•The transmit buffer empty flag is set to “1.”
•The transmit register empty flag is cleared to “0.”
•8 transfer clocks are generated (in the case of an internal clock selected).
•A UARTi transmit interrupt request occurs, and the interrupt request bit is set to “1.”
The transmit operations are described below:
Data in the UARTi transmit register is transmitted from the TxDi pin synchronously with the valid edge
of the clock output from or input to the CLKi pin.
This data is transmitted, bit by bit, sequentially beginning with the least significant bit.
When 1-byte data has been transmitted, the transmit register empty flag is set to “1.” This indicates the
completion of transmission.
Valid edge : A falling edge is selected when the CLK polarity select bit = “0.”
A rising edge is selected when the CLK polarity select bit = “1.”
Figure 12.3.5 shows the transmit operation.
When an internal clock is selected, if the transmit conditions for the next data are satisfied at completion
of the transmission, the transfer clock is generated continuously. Accordingly, when performing transmission
continuously, set the next transmit data to the UARTi transmit buffer register during transmission (when the
transmit register empty flag = “0”). When the transmit conditions for the next data are not satisfied, the
transfer clock stops at “H” level (when the CLK polarity select bit = “0”), or “L” level (when the CLK polarity
select bit = “1”).
Figures 12.3.6 and 12.3.7 show examples of transmit timing.
Fig. 12.3.5 Transmit operation
Transfer clock output from
or input to the CLKi pin (Note)
UARTi transmit buffer register
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
7
D
6
D
5
D
4
D
3
D
2
D
7
D
6
D
5
D
4
D
3
Transmit data
MSB
b7 b0
D
0
D
1
D
2
D
7
LSB
UARTi transmit register
Note: This applies when the CLK polarity select bit = “0.”
When the CLK polarity select bit = “1,” data is shifted at the rising edge of the transfer clock.
SERIAL I/O
7902 Group User’s Manual 12-27
12.3 Clock synchronous serial I/O mode
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
Tc
T
CLK
CLK
i
T
END
i
TxD
i
Transfer clock
Transmit enable bit
Transmit buffer
empty flag
Transmit register
empty flag
UARTi transmit
interrupt request bit
Data is set in UARTi transmit buffer register.
UARTi transmit registerUARTi transmit buffer register.
Stopped because transmit enable bit = “0.”
T
ENDi
: Next transmit conditions are examined when this signal level is “H.”
(T
ENDi
is an internal signal. Accordingly, it cannot be read from the external.)
Tc = T
CLK
= 2(n+1) /fi
fi: BRGi count source frequency
n: Value set in BRGi
Cleared to “0” when interrupt request is accepted or cleared to “0” by software.
The above timing diagram applies
when the following conditions are
satisfied:
Internal clock selected
CTS function not selected
CLK polarity select bit = 0
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
Tc
CTS
i
CLKi
T
END
i
TxDi
Transfer clock
Transmit enable bit
Transmit buffer
empty flag
Transmit register
empty flag
UARTi transmit
interrupt request bit
TCLK
Data is set in UARTi transmit buffer register.
UARTi transmit register UARTi transmit buffer register.
Stopped because CTSi = “H.” Stopped because transmit enable bit = “0.”
T
ENDi
: Next transmit conditions are examined when this signal level is “H.”
(T
ENDi
is an internal signal. Accordingly, it cannot be read from the external.)
Tc = T
CLK
= 2(n+1) /fi
fi: BRGi count source frequency
n: Value set in BRGi
Cleared to “0” when interrupt request is accepted or cleared to “0” by software.
The above timing diagram applies when
the following conditions are satisfied:
Internal clock selected
CTS function selected
CLK polarity select bit = 0
Fig. 12.3.6 Example of transmit timing (when internal clock and CTS function selected)
Fig. 12.3.7 Example of transmit timing (when internal clock selected and CTS function not selected)
SERIAL I/O
7902 Group User’s Manual
12-28
12.3 Clock synchronous serial I/O mode
12.3.5 Method of reception
Figure 12.3.8 shows an initial setting example for relevant registers when receiving. Reception is started
when all of the following conditions ( to ) have been satisfied. When an external clock is selected,
satisfy conditions to with the following preconditions satisfied.
<Preconditions>
The CLKi pin’s input is at “H” level (External clock selected, when the CLK polarity select bit = “0” ).
The CLKi pin’s input is at “L” level (External clock selected, when the CLK polarity select bit = “1”).
Note: When an internal clock is selected, the above preconditions are ignored.
Dummy data is present in the UARTi transmit buffer register (transmit buffer empty flag = “0”)
Reception is enabled (receive enable bit = “1”).
Transmission is enabled (transmit enable bit = “1”).
By connecting the RTSi pin (receiver side) and CTSi pin (transmitter side), the timing of transmission and
that of reception can be matched. For details, refer to section “12.3.6 Receive operation.”
When using interrupts, it is necessary to set the relevant registers to enable interrupts. For details, refer
to “CHAPTER 7. INTERRUPTS.”
Figure 12.3.9 shows processing after reception is completed.
SERIAL I/O
7902 Group User’s Manual 12-29
12.3 Clock synchronous serial I/O mode
Fig. 12.3.8 Initial setting example for relevant registers when receiving
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
0
UART0 transmit/receive mode register (Address 30
16
)
UART1 transmit/receive mode register (Address 38
16
)
b7 b0
Internal/External clock select bit
0: Internal clock
1: External clock
✕✕
: It may be either “0” or “1.”
Selection of clock synchronous serial
I/O mode
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
UART0 transmit/receive control register 0 (Address 34
16
)
UART1 transmit/receive control register 0 (Address 3C
16
)
b7 b0
BRG count source select bits
CTS/RTS function select bit
0: CTS function selected
1: RTS function selected
AA
AA
A
A
AA
AA
A
A
0 0 : f
2
0 1 : f
16
1 0 : f
64
1 1 : f
512
b1 b0
Reception starts.
UART0 transmit buffer register (Address 32
16
)
UART1 transmit buffer register (Address 3A
16
)
b7 b0
Dummy data is set.
1
UART0 transmit/receive control register 1 (Address 35
16
)
UART1 transmit/receive control register 1 (Address 3D
16
)
b7 b0
Transmit enable bit
1: Transmission enabled
AAAA
AAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
UART0 receive interrupt control register (Address 72
16
)
UART1 receive interrupt control register (Address 74
16
)
b7 b0
Interrupt priority level select bits
When using interrupts, set these bits to
one of levels 1 to 7.
When disabling interrupts, set these bits
to level 0.
CTS/RTS enable bit
0: CTS/RTS function is enabled.
1: CTS/RTS function is disabled.
CLK polarity select bit
0: At the rising edge of the transfer
clock, receive data is input.
1: At the falling edge of the transfer
clock, receive data is input.
Transfer format select bit
0: LSB first
1: MSB first
When extenal clock is selected
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
UART0 baud rate register (BRG0) (Address 31
16
)
UART1 baud rate register (BRG1) (Address 39
16
)
b7 b0
Can be set to “00
16
” to “FF
16
.”
When internal clock is selected
UARTi receive interrupt mode select bit
0: Reception interrupt
1: Reception error interrupt
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
0
Port P8 direction register (Address 14
16
)
b7 b0
Pin RxD
0
Pin RxD
1
1
Reception enable bit
1: Reception enabled
Note: Set the receive enable bit
and the transmit enable
bit to “1” simultaneously.
100
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
Serial I/O pin control register (Address AC
16
)
b7 b0
AA
A
AA
CTS
0
/RTS
0
separate select bit
0: CTS
0
/RTS
0
are used together (Note 1).
Notes 1: In the clock synchronous serial I/O
mode, CTS
i
/RTS
i
separation cannot
be selected. (Refer to section “[Pre-
cautions for clock synchronous
serial I/O mode].”)
2: When only reception is performed, if
these bits = “1,” the TxD
i
pin can be
used as a programmable I/O port
pin.
CTS
1
/RTS
1
separate select bit
0: CTS
1
/RTS
1
are used together (Note 1).
TxD
0
/P8
3
switch bit (Note 2)
0: Functions as TxD
0
.
1: Functions as P8
3
.
TxD
1
/P8
7
switch bit (Note 2)
0: Functions as TxD
1
.
1: Functions as P8
7
.
SERIAL I/O
7902 Group User’s Manual
12-30
12.3 Clock synchronous serial I/O mode
Fig. 12.3.9 Processing after reception is completed
[When not using interrupts] [When using interrupts]
A UARTi receive interrupt request occurs
when reception is completed.
AAA
AAA
AAA
UARTi receive interrupt
Processing after reading out receive data
UART0 receive buffer register (Address 3616)
UART1 receive buffer register (Address 3E16)
b7 b0
Reading of receive data (Note 2)
Read out receive data.
b7 b0
Checking completion of reception
11
Notes 1: When performing the processing after reception is completed, using an interrupt, be sure to
select a receive interrupt (UARTi receive interrupt mode select bit = “0.”)
2: In the case of an external clock and the RTS function selected, the RTS
i
output level becomes
“L” when the UARTi receive buffer register is read out. Accordingly, when performing reception
continuously, be sure to write the dummy data to the UARTi transmit buffer register before
reading out the UARTi receive buffer register.
3: This figure shows the bits and registers required for the processing.
See Figure 12.3.12 for the change of flag state and the occurrence timing of an interrupt request.
b7 b0
Checking error
11
Overrun error flag
0 : No overrun error
1 : Overrun error detected
UART0 transmit/receive control register 1 (Address 3516)
UART1 transmit/receive control register 1 (Address 3D16)
UART0 transmit/receive control register 1 (Address 3516)
UART1 transmit/receive control register 1 (Address 3D16)
Receive complete flag
0 : Reception not completed
1 : Reception completed
(Note 1)
SERIAL I/O
7902 Group User’s Manual 12-31
12.3 Clock synchronous serial I/O mode
12.3.6 Receive operation
In the case of an internal clock selected, when the receive conditions described in section “12.3.5 Method
of reception” have been satisfied, a transfer clock is generated and the reception is started after 1 cycle
of the transfer clock or less has passed. In the case of an external clock selected, when the receive
conditions have been satisfied, the UARTi enters the receive-enabled state, and then reception will be
started when an external clock is input to the CLKi pin.
In the case of an external clock selected, when connecting the RTSi pin to the CTSi pin of the transmitter
side, the timing of transmission and that of reception can be matched. In the case of an internal clock
selected, do not use the RTS function. It is because the RTS output is undefined in the case of an internal
clock selected.
In the case of an external clock and the RTS function selected, the RTSi pin’s output level becomes as
described below.
When the receive enable bit = “0,” if one of the following is performed, the RTSi pin’s output level becomes
“L” and informs of the transmitter side that reception has become enabled:
• The receive enable bit is set to “1.”
• The low-order byte of the UARTi receive buffer register is read out.
When the receive enable bit = “1,” if the low-order byte of the UARTi receive buffer register is read out,
the RTSi pin’s output level becomes “L.”
Accordingly, when performing reception continuously, an overrun occurrence can be avoided because the
RTS output level does not become “L” until the receive data is read out.
When reception has started, the RTSi pin’s output level becomes “H.”
Figure 12.3.10 shows a connection example.
Fig. 12.3.10 Connection example
TxDi
RxDi
CLKi
TxDi
RxDi
CLKi
Transmitter side Receiver side
CTSiRTSi
SERIAL I/O
7902 Group User’s Manual
12-32
12.3 Clock synchronous serial I/O mode
The receive operations are described below:
The signal input to the RxDi pin is taken into the most significant bit of the UARTi receive register
synchronously with the valid edge of the clock output from the CLKi pin or input to the CLKi pin.
The contents of the UARTi receive register are shifted, bit by bit, to the right.
Steps and are repeated at each valid edge of the clock output from the CLKi pin or input to the
CLKi pin.
When 1-byte data has been prepared in the UARTi receive register, the contents of this register are
transferred to the UARTi receive buffer register.
Simultaneously with step , the receive complete flag is set to “1.” Additionally, when the receive
interrupt is selected (UARTi receive interrupt mode select bit = “0”), a UARTi receive interrupt request
occurs and its interrupt request bit is set to “1.”
Valid edge : A rising edge is selected when the CLK polarity select bit = “0.”
A falling edge is selected when the CLK polarity select bit = “1.”
The receive complete flag is cleared to “0” when the low-order byte of the UARTi receive buffer register
is read out. Figure 12.3.11 shows the receive operation, and Figure 12.3.12 shows an example of receive
timing (when an external clock is selected).
When the transfer format select bit is “1” (MSB first), each bit’s position of this register’s contents is
reversed, and then the resultant data is read out.
SERIAL I/O
7902 Group User’s Manual 12-33
12.3 Clock synchronous serial I/O mode
Fig. 12.3.11 Receive operation
Fig. 12.3.12 Example of receive timing (when external clock selected)
UARTi receive register
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
0
D
1
D
0
Receive data
MSB
b7 b0
LSB
D
2
D
1
D
0
Transfer clock output from
or input to CLKi pin (Note).
UARTi receive buffer register
Note: This applies when the CLK polarity select bit = “0.”
When the CLK polarity select bit = “1,” data is shifted at the rising edge of
the transfer clock.
The above timing diagram applies when the following
conditions are satisfied:
External clock selected
RTS function selected
CLK polarity select bit = “0”
f
EXT
: Frequency of external clock
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
1/f
EXT
RTS
i
CLK
i
RxD
i
When the CLK
i
pin’s input level is “H,” be sure to satisfy
the following conditions:
Writing of dummy data to UARTi transmit buffer register
Transmit enable bit = “1”
Receive enable bit = “1”
Receive enable bit
Transmit enable bit
Transmit buffer
empty flag
Dummy data is set to UARTi transmit buffer register.
UARTi transmit registerUARTi transmit buffer register
Receive data is taken in.
UARTi receive registerUARTi receive buffer register UARTi receive buffer register is read out.
Receive complete flag
UARTi receive
interrupt request bit
Cleared to “0” when interrupt request is accepted or
cleared to “0” by software.
SERIAL I/O
7902 Group User’s Manual
12-34
12.3 Clock synchronous serial I/O mode
12.3.7 Processing on detecting overrun error
In the clock synchronous serial I/O mode, an overrun error can be detected.
An overrun error occurs when the next data has been prepared in the UARTi receive register with the
receive complete flag = “1” (i.e. data is present in the UARTi receive buffer register) and next data is
transferred to the UARTi receive buffer register. In other words, an overrun error occurs when the next data
has been prepared before reading out the contents of the UARTi receive buffer register. When an overrun
error has occurred, the next receive data is written into the UARTi receive buffer register. Additionally,
when the receive error interrupt is selected (UARTi receive interrupt mode select bit = “1”), a UARTi receive
interrupt request occurs and its interrupt request bit is set to “1.” When the receive interrupt is selected
(UARTi receive interrupt mode select bit = “0”), the UARTi receive interrupt request bit does not change.
An overrun error is detected when data is transferred from the UARTi receive register to the UARTi receive
buffer register, and the overrun error flag is set to “1.” The overrun error flag is cleared to “0” by clearing
the receive enable bit to “0.”
When an overrun error occurs during reception, be sure to initialize the overrun error flag and UARTi
receive buffer register, and then perform reception again. When it is necessary to perform retransmission
owing to a receiver-side overrun error which has occurred during transmission, be sure to set the UARTi
transmit buffer register again, and start transmission again.
The methods of initializing the UARTi receive buffer register and that of setting the UARTi transmit buffer
register again are described below.
(1) Method of initializing UARTi receive buffer register
Clear the receive enable bit to “0” (reception disabled).
Set the receive enable bit to “1” again (reception enabled).
(2) Method of setting UARTi transmit buffer register again
Clear the serial I/O mode select bits to “0002” (serial I/O invalidated).
Set the serial I/O mode select bits to “0012” again.
Set the transmit enable bit to “1” (transmission enabled), and set the transmit data to the UARTi
transmit buffer register.
SERIAL I/O
7902 Group User’s Manual 12-35
12.3 Clock synchronous serial I/O mode
[Precautions for clock synchronous serial I/O mode]
1. A transfer clock is generated by operation of the transmit control circuit. Accordingly, even when performing
only reception, the transmit operation (in other words, setting for transmission) must be performed. In this
case, be sure to set as follows. Additionally, in this case, dummy data is output from the TxDi pin to the
external:
• When performing reception, be sure to enable the reception after dummy data is set to the low-order
byte of the UARTi transmit buffer register. Also, be sure to set dummy data at each 1-byte data
reception.
• At reception, be sure to set the receive enable bit and transmit enable bit to “1” simultaneously.
When performing only reception, if any of the TxD0/P83 and TxD1/P87 switch bits (bits 2 and 3 at address
AC16) is set to “1,” the corresponding TxDi pin can be used as a programmable I/O port pin.
2. When an external clock is selected, with the input level at the CLKi pin = “H” (the CLK polarity select bit
= “0”) or “L” (the CLK polarity select bit = “1”), be sure to satisfy all of the following three conditions:
<At transmission>
Transmit data is written to the UARTi transmit buffer register.
The transmit enable bit is set to “1.”
“L” level is input to the CTSi pin (when the CTS function selected).
<At reception>
Dummy data is written to the UARTi transmit buffer register.
The receive enable bit is set to “1.”
The transmit enable bit is set to “1.”
3. When using the CTS0/RTS0 pin, be sure that the D-A2 output enable bit (bit 2 at address 9616) = “0” (output
disabled).
4. While the CTSi/RTSi separation is selected, the CLKi pin cannot be used. Accordingly, in the clock
synchronous serial I/O mode, the CTSi/RTSi separation cannot be selected.
5. Writing to the UARTi baud rate register (BRGi) must be performed while transmission/reception halts.
6. When an internal clock is selected, do not use the RTS function because the RTS output is undefined.
7. When performing transmission, be sure to clear both of the TxD0/P83 and TxD1/P87 switch bits to “0” (bits
2 and 3 at address AC16).
SERIAL I/O
7902 Group User’s Manual
12-36
12.4 Clock asynchronous serial I/O (UART) mode
12.4 Clock asynchronous serial I/O (UART) mode
Table 12.4.1 lists the performance overview in the UART mode, and Table 12.4.2 lists the functions of
I/O pins in this mode.
Table 12.4.1 Performance overview in UART mode
Item
Transfer data
format
Transfer rate
Error detection
Start bit
Character bit (Transfer data)
Parity bit
Stop bit
When selecting internal clock
When selecting external clock
Functions
1 bit
7 bits, 8 bits, or 9 bits
0 bit or 1 bit (Odd or Even can be selected.)
1 bit or 2 bits
BRGi’s output divided by 16
Maximum 312.5 kbps
4 types (overrun, framing, parity, and summing): presence of an
error can be detected only by check of the error sum flag.
Table 12.4.2 Functions of I/O pins in UART mode Method of selection
(Note)
TxD0/P83 or TxD1/P87 switch bit = “1.”
Port P8 direction register’s corresponding bit = “0”
(Can be used as a programmable I/O port pin when
performing only transmission.)
Internal/External clock select bit = “1”
Internal/External clock select bit = “0”
See Table 12.2.1.
Pin name
TxDi (P83, P87)
RxDi (P82, P86)
CLKi (P81, P85)
CTSi/RTSi (P80, P81,
P84, P85)
Functions
Serial data output pin
Programmable I/O port pin
Serial data input pin
BRGi’s count source input pin
Programmable I/O port pin
CTS input pin
RTS output pin
Programmable I/O port pin
Port P8 direction register: address 1416
Internal/External clock select bit: bit 3 at addresses 3016, 3816
TxD0/P83 switch bit: bit 2 at address AC16
TxD1/P87 switch bit: bit 3 at address AC16
Note: The TxDi pin outputs “H” level while transmission is not performed after the UARTi’s operating mode
is selected.
7902 Group User’s Manual 12-37
SERIAL I/O
12.4 Clock asynchronous serial I/O (UART) mode
12.4.1 Transfer rate (Frequency of transfer clock)
The transfer rate is determined by the BRGi (addresses 3116, 3916).
When “n” is set into BRGi, BRGi divides the count source frequency by (n + 1). The BRGi’s output is further divided
by 16, and the resultant clock becomes the transfer clock. Accordingly, “n” is expressed by the following formula.
n = — 1
F
16 B
n: Value set in BRGi (0016 to FF16)
F: BRGi’s count source frequency (Hz)
B: Transfer rate (bps)
An internal clock or an external clock can be selected as the BRGi’s count source with the internal/external
clock select bit (bit 3 at addresses 3016, 3816). When an internal clock is selected, the clock selected with
the BRG count source select bits (bits 0 and 1 at addresses 3416, 3C16) becomes the BRGi’s count source.
When an external clock is selected, the clock input to the CLKi pin becomes the BRGi’s count source.
Be sure to set the same transfer rate for both transmitter and receiver sides. Tables 12.4.3 and 12.4.4 list
the setting examples of transfer rate.
Each of the values, listed in these tables, realizes the actual transfer rate of which error toward an ideal
transfer rate is within 1 %.
Table 12.4.3 Setting examples of transfer rate (1)
BRGi’s set
value: n (Note)
63 (3F16)
127 (7F16)
63 (3F16)
31 (1F16)
127 (7F16)
63 (3F16)
41 (2916)
31 (1F16)
15 (0F16)
Actual time
(bps)
300.00
600.00
1200.00
2400.00
4800.00
9600.00
14628.57
19200.00
38400.00
BRGi’s
count source
f64
f16
f16
f8
f2
f2
f2
f2
f2
BRGi’s set
value: n (Note)
64 (4016)
129 (8116)
64 (4016)
64 (4016)
129 (8116)
64 (4016)
42 (2A16)
19 (1316)
Actual time
(bps)
300.48
600.96
1201.92
2403.85
4807.69
9615.38
14534.88
31250.00
BRGi’s
count source
f64
f16
f16
f16
f2
f2
f2
f2
f2
fsys = 20 MHzfsys = 19.6608 MHz
Transfer
rate (bps)
300
600
1200
2400
4800
9600
14400
19200
31250
38400
BRGi’s set
value: n (Note)
35 (2316)
71 (4716)
35 (2316)
18 (1216)
71 (4716)
35 (2316)
23 (1816)
17 (1116)
11 (0B16)
10 (0A16)
8 (0816)
5 (0516)
3 (0316)
Actual time
(bps)
300.00
600.00
1200.00
2400.00
4800.00
9600.00
14400.00
19200.00
28800.00
31418.18
38400.00
57600.00
115200.00
BRGi’s
count source
f64
f16
f16
f16
f2
f2
f2
f2
f2
f2
f2
f2
f2
fsys = 11.0592 MHz
Transfer
rate (bps)
300
600
1200
2400
4800
9600
14400
19200
28800
31250
38400
57600
115200
Table 12.4.4 Setting examples of transfer rate (2)
Note: This applies when the peripheral
device’s clock select bits 1, 0 (bits 7,
6 at address BC16) = “002.”
SERIAL I/O
7902 Group User’s Manual
12-38
12.4 Clock asynchronous serial I/O (UART) mode
Error-permitted range of transfer baud
During reception, the receive data input to the RxDi pin is taken at the rising edge of the transfer
clock. (Refer to section “12.4.6 Receive operation.”) Accordingly, in order to receive data correctly,
the stop bit must be input when the transfer clock of one-set receive data rises last. Figure 12.4.1
shows the relationship between the transfer clock and receive data.
Fig. 12.4.1 Relationship between transfer clock and receive data
<1ST-8DATA-1SP>
ST D
0
D
7
SP
D
0
ST D
7
SP
At the falling edge of ST, the transfer clock is
generated, and reception starts.
When the transfer rate of
the receive data is faster
than the rate of the transfer
clock on the receiver side
When the transfer rate of
the receive data is slower
than the rate of the transfer
clock on the receiver side
RxD
i
(Receive data)
Transfer clock
(Receiver side)
1 clock 8 clocks 1 clock
9.5 clocks
ST : Start bit
SP : Stop bit
1 period of BRGi’s count source (Maximum)
According to the condition of the input timing,
a maximum of this period () can be omitted.
SP must be detected at
this last rising edge of
the transfer clock.
Accordingly, the transfer rate of the receiver and transmitter sides must satisfy the following formula
in order to receive data correctly.
Br: Transfer rate on receiver side (bps)
Bt: Transfer rate on transmitter side (bps)
F : BRGi’s count source frequency on receiver side (Hz)
b : Entire bit number of one-set data
(ex: 12 bits in the case of 1ST-8DATA-1PAR-2SP; See Figure 12.4.2.)
1
Bt 1
F
1
F1
Br 1
Bt
(b – 1) + (b – 0.5) + b
<<
Be sure to satisfy the above formula, and set the timing with enough margin. Also, the user shall
make sufficient evaluation before actually using it.
7902 Group User’s Manual 12-39
SERIAL I/O
12.4 Clock asynchronous serial I/O (UART) mode
12.4.2 Transfer data format
The transfer data format can be selected from formats shown in Figure 12.4.2. Bits 4 to 6 at addresses
3016 and 3816 select the transfer data format. (See Figure 12.2.2.) Set the same transfer data format for both
transmitter and receiver sides.
Figure 12.4.3 shows an example of transfer data format. Table 12.4.5 lists each bit in transmit data.
Transfer data length of 7 bits
1ST—7DATA 1SP
1ST—7DATA 2SP
1ST—7DATA—1PAR—1SP
1ST—7DATA—1PAR—2SP
Transfer data length of 8 bits
1ST—8DATA 1SP
1ST—8DATA 2SP
1ST—8DATA—1PAR—1SP
1ST—8DATA—1PAR—2SP
Transfer data length of 9 bits
1ST—9DATA 1SP
1ST—9DATA 2SP
1ST—9DATA—1PAR—1SP
1ST—9DATA—1PAR—2SP
ST : Start bit
DATA : Character bit (Transfer data)
PAR : Parity bit
SP : Stop bit
Fig. 12.4.2 Transfer data format
Name
ST
Start bit
DATA
Character bit
PAR
Parity bit
SP
Stop bit
Functions
“L” signal equivalent to 1 character bit. This is added immediately before the character
bits. It indicates start of data transmission.
Transmit data which is set in the UARTi transmit buffer register.
A signal that is added immediately after the character bits in order to improve data
reliability. The level of this signal changes according to selection of odd/even parity
in such a way that the sum of “1”s in the sum of this bit and character bits is always
an odd or even number.
“H” level signal equivalent to 1 or 2 character bits. This is added immediately after
the character bits (or parity bit when parity is enabled). It indicates completion of
data transmission.
Fig. 12.4.3 Example of transfer data format
Table 12.4.5 Each bit in transmit data
Time
• 1ST–8DATA–1PAR–1SP
ST LSB MSB PAR SP ST
Transmit/Receive data
DATA (8 bits) Next transmit/receive data
(When continuously
transferred)
SERIAL I/O
7902 Group User’s Manual
12-40
12.4 Clock asynchronous serial I/O (UART) mode
12.4.3 Method of transmission
Figure 12.4.4 shows an initial setting example for relevant registers when transmitting.
The difference depending on the transfer data length (7 bits, 8 bits, or 9 bits) is the transmit data’s length
only. When selecting a 7- or 8-bit data length, be sure to set the transmit data into the low-order byte of
the UARTi transmit buffer register. When selecting a 9-bit data length, be sure to set the transmit data into
the low-order byte and bit 0 of the high-order byte.
Transmission is started when all of the following conditions ( to ) are satisfied:
Transmit data is present in the UARTi transmit buffer register (transmit buffer empty flag = “0”).
Transmit is enabled (transmit enable bit = “1”).
The CTSi pin’s input level is “L” (when the CTS function selected).
Note: When the CTS function is not selected, condition is ignored.
By connecting the RTSi pin (receiver side) and CTSi pin (transmitter side), the timing of transmission and
that of reception can be matched. For details, refer to section “12.4.6 Receive operation.”
When using interrupts, it is necessary to set the relevant registers to enable interrupts. For details, refer
to “CHAPTER 7. INTERRUPTS.”
Figure 12.4.5 shows writing data after transmission is started, and Figure 12.4.6 shows detection of
transmit completion.
7902 Group User’s Manual 12-41
SERIAL I/O
12.4 Clock asynchronous serial I/O (UART) mode
Fig. 12.4.4 Initial setting example for relevant registers when transmitting
(If the
CTS
function selected, transmission starts
when the
CTS
i
pin’s input level becomes “L.”)
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
1
UART0 transmit/receive control register 1 (Address 35
16
)
UART1 transmit/receive control register 1 (Address 3D
16
)
b7 b0
Transmit enable bit
1: Transmission enabled
AAA
AAA
AAA
AAA
Transmission starts.
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
UART0 baud rate register (BRG0) (Address 31
16
)
UART1 baud rate register (BRG1) (Address 39
16
)
b7 b0
Can be set to “00
16
” to “FF
16
.”
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
UART0 transmit interrupt control register (Address 71
16
)
UART1 transmit interrupt control register (Address 73
16
)
b7 b0
Interrupt priority level select bits
When using interrupts, set these bits
to one of levels 1 to 7.
When disabling interrupts, set these
bits to level 0.
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
b7 b0
Transmit data is set.
b8
UART0 transmit buffer register (Addresses 33
16
, 32
16
)
UART1 transmit buffer register (Addresses 3B
16
, 3A
16
)
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
UART0 transmit/receive mode register (Address 30
16
)
UART1 transmit/receive mode register (Address 38
16
)
b7 b0
Internal/External clock select bit
0: Internal clock
1: External clock
1 0 0: UART mode (7 bits)
1 0 1: UART mode (8 bits)
1 1 0: UART mode (9 bits)
Stop bit length select bit
0: 1 stop bit
1: 2 stop bits
Odd/Even parity select bit
0: Odd parity
1: Even parity
Parity enable bit
0: Parity is disabled.
1: Parity is enabled.
Sleep select bit
0: Sleep mode cleared (invalid)
1: Sleep mode selected
1
b2 b1 b0
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
UART0 transmit/receive control register 0 (Address 34
16
)
UART1 transmit/receive control register 0 (Address 3C
16
)
b7 b0
BRG count source select bits
AA
AA
CTS/RTS function is select bit
0: CTS function selected
1: RTS function selected
0 0 : f
2
0 1 : f
16
1 0 : f
64
1 1 : f
512
b1 b0
b15
00
CTS/RTS enable bit
0: CTS/RTS function is enabled.
1: CTS/RTS function is disabled.
Note: The CLK
i
pin cannot be used when
the CTS
i
/RTS
i
separation is selected.
(Refer to “[Precaution for clock
asynchronous serial I/O (UART)
mode].”)
Serial I/O mode select bit
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
Serial I/O pin control register (Address AC
16
)
b7 b0
AA
AA
A
CTS
0
/RTS
0
separate select bit
0: CTS
0
/RTS
0
are used together.
1: CTS
0
/RTS
0
are separated (Note).
CTS
1
/RTS
1
separate select bit
0: CTS
1
/RTS
1
are used together.
1: CTS
1
/RTS
1
are separated (Note).
TxD
0
/P8
3
switch bit
0: Functions as TxD
0
.
TxD
1
/P8
7
switch bit
0: Functions as TxD
1
.
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
AAAAAAAAAAA
0
Port P8 direction register (Address 14
16
)
b7 b0
Pin CTS
0
0
Pin CTS
1
CTS
i
/RTS
i
are used together.
CTS
i
/RTS
i
are separated.
SERIAL I/O
7902 Group User’s Manual
12-42
12.4 Clock asynchronous serial I/O (UART) mode
[When not using interrupts] [When using interrupts]
A UARTi transmit interrupt request occurs
when the transmission starts. (when the
UARTi transmit buffer register becomes
empty.)
AAA
AAA
AAA
UARTi transmit interrupt
Note:
UART0 transmit buffer register (Addresses 33
16
, 32
16
)
UART1 transmit buffer register (Addresses 3B
16
, 3A
16
)
b7 b0
Writing of next transmit data
Transmit data is set.
b0
UART0 transmit/receive control register 1 (Address 35
16
)
UART1 transmit/receive control register 1 (Address 3D
16
)
b7
Transmit buffer empty flag
0: Data is present in transmit buffer register.
1: No data is present in transmit buffer register.
(Writing of next transmit data is possible.)
Checking state of UARTi transmit buffer register
1
This figure shows the bits and registers
required for processing.
See Figures 12.4.7 to 12.4.9 for the change
of flag state and the occurrence timing of an
interrupt request.
b0
b8b15
Fig. 12.4.5 Write operation of data after transmission start
7902 Group User’s Manual 12-43
SERIAL I/O
12.4 Clock asynchronous serial I/O (UART) mode
[When not using interrupts] [When using interrupts]
AAAA
AAAA
AAAA
UARTi transmit interrupt
UART0 transmit interrupt control register (Address 71
16
)
UART1 transmit interrupt control register (Address 73
16
)
b7 b0
Interrupt request bit
Checking start of transmission
UART0 transmit/receive control register 0 (Address 34
16
)
UART1 transmit/receive control register 0 (Address 3C
16
)
b7 b0
A
A
AA
AA
AA
AA
A
A
Checking completion of transmission.
Transmit register empty flag
0: Transmission is in progress.
1: Transmission is completed.
Processing at completion of transmission
0: No interrupt requested
1: Interrupt requested
(Transmission has started.)
A UARTi transmit interrupt request
occurs when the transmission starts.
Note: This figure shows the bits and registers required
for processing.
See Figures 12.4.7 to 12.4.9 for the change of
flag state and the occurrence timing of an interrupt
request.
00
Fig. 12.4.6 Detect operation of transmit completion
SERIAL I/O
7902 Group User’s Manual
12-44
12.4 Clock asynchronous serial I/O (UART) mode
12.4.4 Transmit operation
When the receive conditions described in section “12.4.3 Method of transmission” have been satisfied,
a transfer clock is generated, and the following operations are automatically performed after 1 cycle of the
transfer clock or less has passed.
The UARTi transmit buffer register’s contents are transferred to the UARTi transmit register.
•The transmit buffer empty flag is set to “1.”
•The transmit register empty flag is cleared to “0.”
•A UARTi transmit interrupt request occurs, and the interrupt request bit is set to “1.”
The transmit operations are described below:
Data in the UARTi transmit register is transmitted from the TxDi pin.
This data is transmitted bit by bit sequentially in order of STDATA (LSB)•••DATA (MSB)PAR
SP according to the transfer data format.
The transmit register empty flag is set to “1” at the center of the stop bit (or the second stop bit if 2 stop
bits selected). This indicates completion of transmission. Additionally, whether the transmit conditions
for the next data are satisfied or not is examined.
When the transmit conditions for the next data are satisfied in step , the start bit is generated following
the stop bit, and the next data is transmitted. When performing transmission continuously, be sure to set
the next transmit data in the UARTi transmit buffer register during transmission (i.e. when the transmit
register empty flag = “0”). When the transmit conditions for the next data are not satisfied, the TxDi pin
outputs “H” level and the transfer clock stops.
Figures 12.4.7 and 12.4.8 show examples of transmit timing when the transfer data length = 8 bits, and
Figure 12.4.9 shows an example of transmit timing when the transfer data length = 9 bits.
7902 Group User’s Manual 12-45
SERIAL I/O
12.4 Clock asynchronous serial I/O (UART) mode
Fig. 12.4.8 Example of transmit timing when transfer data length = 8 bits (when parity enabled,
1 stop bit and selecting CTS function selected)
Fig. 12.4.7 Example of transmit timing when transfer data length = 8 bits (when parity enabled,
1 stop bit selected, CTS function not selected)
Tc
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST PSP D
0
D
1
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST PST
SP
T
ENDi
TxD
i
T
ENDi
: Next transmit conditions are examined when this signal level
becomes “H.”
(T
ENDi
is an internal signal. Accordingly, it cannot be read from
the external.)
Tc: 16 (n + 1)/f
i
or 16 (n + 1)/f
EXT
f
i
: BRGi’s count source frequency (internal clock)
f
EXT
: BRGi’s count source frequency (external clock)
n: Value set in BRGi
Transfer clock
Transmit enable bit
Transmit buffer
empty flag
Transmit register
empty flag
UARTi transmit
interrupt request bit
Data is set in UARTi transmit buffer register.
Cleared to “0” when interrupt request is accepted or cleared to “0” by software.
The above timing diagram applies when
the following conditions are satisfied:
Parity enabled
1 stop bit
CTS function not selected
UARTi transmit register UARTi transmit buffer register
Stopped because transmit enable bit = “0”
ST: Start bit
D
0
to D
7
: Transfer data
P: Parity bit
ST: Stop bit
The above timing diagram applies
when the following conditions are
satisfied:
Parity enabled
1 stop bit
CTS function selected
Tc
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST PSP D
0
D
1
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST PSP ST
T
ENDi
TxD
i
T
ENDi
: Next transmit conditions are examined when this signal level
becomes “H.”
(T
ENDi
is an internal signal. Accordingly, it cannot be read from
the external.)
Tc = 16 (n + 1)/f
i
or 16 (n + 1)/f
EXT
f
i
: BRGi’s count source frequency (internal clock)
f
EXT
: BRGi’s count source frequency (external clock)
n: Value set in BRGi
Transfer clock
Transmit buffer
empty flag
Transmit register
empty flag
UARTi transmit
interrupt request bit
Data is set in UARTi transmit buffer register.
Cleared to “0” when interrupt request is accepted or cleared to “0” by software.
UARTi transmit register UARTi transmit buffer register
Transmit enable bit
CTS
i
Stopped because CTS
i
= “H”
ST: Start bit
D
0
to D
7
: Transfer data
P: Parity bit
ST: Stop bit
Stopped because transmit
enable bit = “0”
SERIAL I/O
7902 Group User’s Manual
12-46
12.4 Clock asynchronous serial I/O (UART) mode
The above timing diagram applies when
the following conditions are satisfied:
Parity disabled
2 stop bits
CTS function not selected
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST D
8
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST SP D
0
D
1
ST
D
8
SP SPSP
Tc
TENDi
TxD
i
T
ENDi
: Next transmit conditions are examined when this signal level
becomes “H.”
(T
ENDi
is an internal signal. Accordingly, it cannot be read from
the external.)
Tc = 16 (n + 1)/f
i
or 16 (n + 1)/f
EXT
f
i
: BRGi count source frequency (internal clock)
f
EXT
: BRGi count source frequency (external clock)
n: Value set in BRGi
Transfer clock
Transmit enable bit
Transmit buffer
empty flag
Transmit register
empty flag
UARTi transmit
interrupt request bit
Data is set in UARTi transmit buffer register.
Cleared to “0” when interrupt request is accepted or cleared to “0” by software.
UARTi transmit register UARTi transmit buffer register
Stopped because transmit enable bit = “0”
ST: Start bit
D
0
to D
7
: Transfer data
P: Parity bit
ST: Stop bit
Fig. 12.4.9 Example of transmit timing when transfer data length = 9 bits (when parity disabled,
2 stop bits selected, CTS function not selected)
7902 Group User’s Manual 12-47
SERIAL I/O
12.4 Clock asynchronous serial I/O (UART) mode
12.4.5 Method of reception
Figure 12.4.10 shows an initial setting example for relevant registers when receiving. Reception is started
when all of the following conditions ( and ) have been satisfied:
Reception is enabled (receive enable bit = “1”).
The start bit (its falling edge) is detected.
By connecting the RTSi pin (receiver side) and CTSi pin (transmitter side), the timing of transmission and
that of reception can be matched. For details, refer to section “12.4.6 Receive operation.”
When using interrupts, it is necessary to set the relevant registers to enable interrupts. For details, refer
to “CHAPTER 7. INTERRUPTS.”
Figure 12.4.11 shows processing after reception is completed.
SERIAL I/O
7902 Group User’s Manual
12-48
12.4 Clock asynchronous serial I/O (UART) mode
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAA
AAAA
AAAA
AAAA
Reception will start when the start bit (’s
falling edge) is detected.
Port P8 direction register (Address 1416)
b7 b0
00
Pin RxD0
Pin RxD1
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
UART0 baud rate register (BRG0) (Address 3116)
UART1 baud rate register (BRG1) (Address 3916)
b7 b0
Can be set to “0016” to “FF16.”
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
UART0 receive interrupt control register (Address 7216)
UART1 receive interrupt control register (Address 7416)
b7 b0
Interrupt priority level select bits
When using interrupts, set these bits to
one of levels 1 to 7.
When disabling interrupts, set these bits
to level 0.
Set the same transfer data format
as that of the transmitter side.
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
1
UART0 transmit/receive control register 1 (Address 3516)
UART1 transmit/receive control register 1 (Address 3D16)
b7 b0
Receive enable bit
1: Reception enabled
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
UART0 transmit/receive mode register (Address 3016)
UART1 transmit/receive mode register (Address 3816)
b7 b0
Internal/External clock select bit
0: Internal clock
1: External clock
1 0 0: UART mode (7 bits)
1 0 1: UART mode (8 bits)
1 1 0: UART mode (9 bits)
Stop bit length select bit
0: 1 stop bit
1: 2 stop bits
Odd/Even parity select bit
0: Odd parity
1: Even parity
Parity enable bit
0: Parity is disabled.
1: Parity is enabled.
Sleep select bit
0: Sleep mode cleared (invalid)
1: Sleep mode selected
1
b2 b1 b0
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
UART0 transmit/receive control register 0 (Address 3416)
UART1 transmit/receive control register 0 (Address 3C16)
b7 b0
BRG count source select bits
AA
CTS/RTS function select bit
0: CTS function selected
1: RTS function selected
0 0 : f2
0 1 : f16
1 0 : f64
1 1 : f512
b1 b0
00
CTS/RTS enable bit
0: CTS/RTS function is enabled.
1: CTS/RTS function is disabled.
Notes 1: The CLKi pin cannot be used
when the CTSi/RTSi separation
is selected. (Refer to “[Precau-
tion for clock asynchronous
serial I/O (UART) mode].”)
2: When performing reception only,
if these bits are set to “1,” the
TxDi pin can be used as a
programmable I/O port pin.
UARTi receive interrupt mode select bit
0: Reception interrupt
1: Reception error interrupt
Serial I/O mode select bit
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
Serial I/O pin control register (Address AC16)
b7 b0
A
AA
AA
CTS0/RTS0 separate select bit
0: CTS0/RTS0 are used together.
1: CTS0/RTS0 are separated (Note 1).
CTS1/RTS1 separate select bit
0: CTS1/RTS1 are used together.
1: CTS1/RTS1 are separated (Note 1).
TxD0/P83 switch bit (Note 2)
0: Functions as TxD0.
1: Functions as P83.
TxD1/P87 switch bit (Note 2)
0: Functions as TxD1.
1: Functions as P87.
Fig. 12.4.10 Initial setting example for relevant registers when receiving
7902 Group User’s Manual 12-49
SERIAL I/O
12.4 Clock asynchronous serial I/O (UART) mode
Fig. 12.4.11 Processing after reception is completed
[When not using interrupts] [When using interrupts]
A UARTi receive interrupt request
occurs when reception is completed.
AAA
AAA
AAA
UARTi receive interrupt
Processing after reading out receive data
UART0 receive buffer register (Addresses 37
16
, 36
16
)
UART1 receive buffer register (Addresses 3F
16
, 3E
16
)
b15 b8
Reading of receive data
Read out receive data.
b7 b0
0000000
UART0 transmit/receive control register 1 (Address 35
16
)
UART1 transmit/receive control register 1 (Address 3D
16
)
b7 b0
Receive complete flag
0 : Reception not completed
1 : Reception completed
Checking completion of reception
1
UART0 transmit/receive control register 1 (Address 35
16
)
UART1 transmit/receive control register 1 (Address 3D
16
)
b7 b0
Checking error
Framing error flag
Parity error flag
Error sum flag
0 : No error
1 : Error detected
1
Notes 1: When performing the processing after the reception is completed, using an interrupt,
be sure to select the receive interrupt (UARTi receive interrupt mode select bit = “0”).
2: This figure shows the bits and registers required for the processing.
See Figure 12.4.13 for the change of flag state and the occurrence timing of an
interrupt request.
UART0 transmit/receive control register 1 (Address 35
16
)
UART1 transmit/receive control register 1 (Address 3D
16
)
b7 b0
Checking error
Overrun error flag
0 : No overrun error
1 : Overrun error detected
1
(Note 1)
SERIAL I/O
7902 Group User’s Manual
12-50
12.4 Clock asynchronous serial I/O (UART) mode
12.4.6 Receive operation
When the receive enable bit is set to “1,” the UARTi enters the receive-enabled state. Then, reception will
start when ST (’s falling edge) is detected and a transfer clock is generated.
If the RTS function selected, when connecting the RTSi pin to the CTSi pin of the transmitter side, the
timing of transmission and that of reception can be matched. If the RTS function selected, the RTSi pin’s
output level becomes as described below.
When the receive enable bit = “0,” if one of the following is performed, the RTSi pin’s output level becomes
“L” and informs of the transmitter side that reception has become enabled:
• The receive enable bit is set to “1.”
• The low-order byte of the UARTi receive buffer register is read out.
When the receive enable bit = “1,” if the low-order byte of the UARTi receive buffer register is read out,
the RTSi pin’s output level becomes “L.”
Accordingly, when performing reception continuously, an overrun occurrence can be avoided because the
RTS output level does not become “L” until the receive data is read out.
When reception has started, the RTSi pin’s output level becomes “H.”
Figure 12.4.12 shows a connection example.
Fig. 12.4.12 Connection example
The receive operation is described below.
The signal input to the RxDi pin is taken into the most significant bit of the UARTi receive register,
synchronously with the transfer clock’s rising edge.
The contents of the UARTi receive register are shifted, bit by bit, to the right.
Steps and are repeated at each rising edge of the transfer clock.
When one set of data has been prepared, in other words, when the shift operation has been performed
several times according to the selected data format, the UARTi receive register’s contents are transferred
to the UARTi receive buffer register.
Simultaneously with step , the receive complete flag is set to “1.” Additionally, when the receive
interrupt is selected (UARTi receive interrupt mode select bit = “0”), a UARTi receive interrupt request
occurs and its interrupt request bit is set to “1.”
The receive complete flag is cleared to “0” when the low-order byte of the UARTi receive buffer register
has been read out. Figure 12.4.13 shows an example of receive timing when the transfer data length = 8
bits.
TxDi
RxDi
TxDi
RxDi
Transmitter side Receiver side
CTSiRTSi
7902 Group User’s Manual 12-51
SERIAL I/O
12.4 Clock asynchronous serial I/O (UART) mode
Fig. 12.4.13 Example of receive timing when transfer data length = 8 bits (when parity disabled, 1
stop bit and RTS function selected)
D
0
D
1
D
7
Start bit
Sampled “L”
Received data taken in
BRGi’s count
source
Receive enable
bit
RxD
i
Transfer clock
Receive
complete flag
RTS
i
Stop bit
The above timing diagram applies when the following
conditions are satisfied:
Parity disabled
1 stop bit
RTS function selected
UARTi receive
interrupt
request bit
Cleared to “0” when interrupt request
is accepted or cleared to “0” by
software.
UARTi receive register UARTi receive buffer register
At falling edge of start bit, the transfer
clock is generated and reception started.
UARTi receive buffer register’s reading out
SERIAL I/O
7902 Group User’s Manual
12-52
12.4 Clock asynchronous serial I/O (UART) mode
12.4.7 Processing on detecting error
In the UART mode, 3 types of errors can be detected. Each error can be detected when the data in the
UARTi receive register is transferred to the UARTi receive buffer register, and the corresponding error flag
is set to “1.” When any error occurs, the error sum flag is set to “1.” Accordingly, presence of errors can
be judged by using the error sum flag.
Table 12.4.6 lists the conditions for setting each error flag to “1” and method to clear it to “0.”
Additionally, when the receive error interrupt is selected (UARTi receive interrupt mode select bit = “1”),
the UARTi receive interrupt request bit is set to “1” only when each error has occurred. When the receive
interrupt is selected (UARTi receive interrupt mode select bit = “0”), the UARTi receive interrupt request
bit is set to “1” when reception has been completed or when a framing or parity error has occurred. (Even
when an overrun error has occurred, this bit does not change).
Table 12.4.6 Conditions for setting each error flag to “1” and method to clear it to “0”
Method to clear
• Clear the receive enable bit to “0.”
• Clear the receive enable bit to “0.”
• Read out the low-order byte of the UARTi
receive buffer register.
• Clear the receive enable bit to “0.”
• Read out the low-order byte of the UARTi
receive buffer register.
• Clear the all error flags, which are
overrun, framing and parity error flags.
Error flag
Overrun error flag
Framing error flag
Parity error flag
Error sum flag
Conditions for setting
When the next data is prepared in the
UARTi receive register with the receive
complete flag = “1” (i.e. data is present
in the UARTi receive buffer register). In
other words, when the next data is
prepared before the contents of the UARTi
receive buffer register are read out (Note).
When the number of detected stop bits
does not match the set number of stop
bits.
When the sum of “1”s in the sum of the
parity bit and character bits does not match
the set number of “1”s.
When any error listed above has occurred.
Note: The next data is written into the UARTi receive buffer register.
When an error occurs during reception, be sure to initialize the error flag and the UARTi receive buffer
register, and then perform reception again. When it is necessary to perform retransmission owing to an
error which has occurred on the receiver side during transmission, be sure to set the UARTi transmit buffer
register again, and then perform the retransmission.
The method to initialize the UARTi receive buffer register and that to set the UARTi transmit buffer register
again are described below.
(1) Method to initialize UARTi receive buffer register
Clear the receive enable bit to “0” (reception disabled).
Set the receive enable bit to “1” again (reception enabled).
(2) Method to set UARTi transmit buffer register again
Clear the serial I/O mode select bits to “0002” (serial I/O invalid).
Set the serial I/O mode select bits again.
Set the transmit enable bit to “1” (transmission enabled), and set the transmit data to the UARTi
transmit buffer register.
7902 Group User’s Manual 12-53
SERIAL I/O
12.4 Clock asynchronous serial I/O (UART) mode
12.4.8 Sleep mode
This mode is used to transfer data between the specified microcomputers, which are connected by using
UARTi. The sleep mode is selected by setting the sleep select bit (bit 7 at addresses 3016, 3816) to “1” when
receiving.
In the sleep mode, receive operation is performed when the MSB (D8 when the transfer data = 9-bit length,
D7 when it is 8-bit length, D6 when it is 7-bit length) of the receive data is “1.” Receive operation is not
performed when the MSB is “0.” (The UARTi receive register’s contents are not transferred to the UARTi
receive buffer register. Additionally, the receive complete flag and each error flag do not change, and no
UARTi receive interrupt request occurs.)
The following shows an usage example of the sleep mode when the transfer data = 8-bit length.
Be sure to set the same transfer data format for the master and slave microcomputers. Additionally, be
sure to select the sleep mode for the slave microcomputers.
Then, transmit the data, of which structure is as follows, from the master microcomputer:
• Bit 7 = “1”
• Bits 6 to 0 indicate the address of the slave microcomputer to be communicated
Each slave microcomputer receives the data described in step . (At this time, a UARTi receive interrupt
request occurs.)
Be sure to check for each slave microcomputer, in the interrupt routine, whether bits 6 to 0 of the receive
data match its own address.
For the slave microcomputer of which address matches bits 6 to 0 of the receive data, terminate the
sleep mode. (Do not terminate the sleep mode for the other slave microcomputers.)
By performing steps to , “the microcomputer which performs transfer” is specified.
Transmit the data of which bit 7 = “0” from the master microcomputer. (Only one slave microcomputer
specified in steps to can receive this data. The other microcomputers do not receive this data.)
By repeating step , continuous transfer can be performed between two specific microcomputers. When
communicating with another slave microcomputer, perform steps to in order to specify the new
slave microcomputer.
Fig. 12.4.14 Sleep mode
Master
Slave BSlave A Slave DSlave C
Data is transferred between the master
microcomputer and one specific slave microcomputer
selected from multiple slave microcomputers.
SERIAL I/O
7902 Group User’s Manual
12-54
[Precautions for clock asynchronous serial I/O (UART) mode]
[Precautions for clock asynchronous serial I/O (UART) mode]
1. When using the CTS0/RTS0 pin, be sure that the D-A2 output enable bit (bit 2 at address 9616) = “0” (output
disabled).
2. When separating CTSi/RTSi, the CLKi pin cannot be used. Accordingly, when separating CTSi/RTSi in
UART mode, be sure to select an internal clock.
3. Writing to the UARTi baud rate register (BRGi) must be performed while transmission/reception halts.
4. When transmitting, be sure to clear the TxD0/P83 or TxD1/P87 switch bit (bits 2, 3 at address AC16) to “0.”
CHAPTER 13CHAPTER 13
A-D CONVERTER
13.1 Overview
13.2 Block description
13.3 A-D conversion method
13.4 Absolute accuracy and Differential
non-linearity error
13.5
Comparison voltage in 8-bit resolution
mode
13.6 One-shot mode
13.7 Repeat mode
13.8 Single sweep mode
13.9 Repeat sweep mode
[Precautions for A-D converter]
A-D CONVERTER
7902 Group User’s Manual
13-2
13.1 Overview
13.1 Overview
The A-D conversion is performed in the 8-bit resolution mode or the 10-bit resolution mode. Table 13.1.1
lists the performance specifications of the A-D converter.
Table 13.1.1 Performance specifications of A-D converter
Item Performance specifications
A-D conversion method Successive approximation conversion method
Resolution Either of 8-bit or 10-bit resolution can be selected by software.
Absolute accuracy 8-bit resolution mode : ±2 LSB
10-bit resolution mode : ±3 LSB
Analog input pin 8 pins (AN0 to AN7)
Conversion rate per analog input pin 8-bit resolution mode : 49
φ
AD cycles
10-bit resolution mode : 59
φ
AD cycles
φ
AD : A-D converter’s operation clock
(1) 8-bit resolution mode
The input voltage from pin ANi (i = 0 to 7) is A-D converted, and the 8-bit A-D conversion result is
stored in A-D register i. (Refer to sections “13.3 A-D conversion method” and “13.5 Comparison
voltage in 8-bit resolution mode.”)
(2) 10-bit resolution mode
The input voltage from pin ANi is A-D converted, and the 10-bit A-D conversion result is stored in
A-D register i. (Refer to section “13.3 A-D conversion method.”)
(3) Operation modes
The A-D converter is equipped with the following 4 modes.
One-shot mode
This mode is used to perform the A-D conversion once for a voltage input from one selected analog
input pin.
Repeat mode
This mode is used to perform the A-D conversion repeatedly for a voltage input from one selected
analog input pin.
Single sweep mode
This mode is used to perform the A-D conversion for voltages input from multiple selected analog
input pins, one at a time.
Repeat sweep mode
This mode is used to perform the A-D conversion repeatedly for voltages input from multiple selected
analog input pins.
A-D CONVERTER
7902 Group User’s Manual 13-3
13.2 Block description
13.2 Block description
Figure 13.2.1 shows the block diagram of the A-D converter. Registers relevant to the A-D converter are
described below.
Fig. 13.2.1 Block diagram of A-D converter
Selector
AN
0
AN
1
AN
2
AN
3
AN
4
AN
5
AN
6
AN
7
/AD
TRG
V
ref
A-D register 0
A-D register 1
A-D register 2
A-D register 3
Data bus (odd)
A-D control register 1
A-D control register 0
φ
AD
(1,1)
Selection of A-D conversion frequency
f
2
(1,0)
(0,1)
(0,0)
1/2
1/2
f
1
Data bus (even)
AV
SS
V
REF
0
1
V
REF
connection select bit
A-D register 4
A-D register 5
A-D register 6
A-D register 7
Resistor ladder
network
Successive
approximation register
Comparator
Decoder
A-D conversion frequency (
φ
AD
)
select bits 1, 0
A-D CONVERTER
7902 Group User’s Manual
13-4
Fig. 13.2.2 Structure of A-D control register 0
13.2.1 A-D control register 0, 1
Figure 13.2.2 shows the structures of the A-D control registers 0 and 1.
13.2 Block description
Undefined
Undefined
Undefined
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
(Note 7)
RW
Notes 1: These bits are invalid in the single sweep and repeat sweep modes. (They may be either “0” or “1.”)
2: When using pin AN4, be sure that the pin INT3 select bit (bit 5 at address 9416) = “0.”
3: When using pin AN5, be sure that the pin INT4 select bit (bit 6 at address 9416) = “0.”
4: When using pin AN6, be sure that the D-A0 output enable bit (bit 0 at address 9616) = “0” (output disabled).
5: When using pin AN7, be sure that the pin INT 2 select bit (bit 4 at address 9416) = “0” and the D-A1 output enable bit (bit 1
at address 9616) = “0.” When using an external trigger, pin AN7 cannot be used as an analog input pin.
6: When using an external trigger, be sure that the pin INT2 select bit (bit 4 at address 9416) = “0” and the D-A1 output enable
bit (bit 1 at address 9616) = “0.”
7: When writing to this bit, use the MOVM (MOVMB) or STA (STAB, STAD) instruction.
8: Writing to each bit (except bit 6) of the A-D control register 0 must be performed while the A-D converter halts.
0
1
2
3
4
5
6
7
A-D control register 0 (Address 1E16)
Analog input select bits
(Valid in the one-shot and repeat
modes.) (Note 1)
A-D operation mode select bits
Trigger select bit
A-D conversion start bit
A-D conversion frequency (
φ
AD)
select bit 0
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 : AN0 is selected.
0 0 1 : AN1 is selected.
0 1 0 : AN2 is selected.
0 1 1 : AN3 is selected.
1 0 0 : AN4 is selected. (Note 2)
1 0 1 : AN5 is selected. (Note 3)
1 1 0 : AN6 is selected. (Note 4)
1 1 1 : AN7 is selected. (Note 5)
b2 b1b0
0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode
b4 b3
0 : Internal trigger
1 : External trigger
(Note 6)
0 : A-D conversion halts.
1 : A-D conversion starts.
See Table 13.2.1.
Bit nameBit Function At reset R/W
A-D CONVERTER
7902 Group User’s Manual 13-5
0
1
2
3
4
5
6
7
Notes 1: These bits are invalid in the one-shot and repeat modes. (They may be either “0” or “1.”)
2: When using pin AN4, be sure that the pin INT3 select bit (bit 5 at address 9416) = “0.”
3: When using pin AN5, be sure that the pin INT4 select bit (bit 6 at address 9416) = “0.”
4: When using pin AN6, be sure that the D-A0 output enable bit (bit 0 at address 9616) = “0” (output disabled).
5: When using pin AN7, be sure that the pin INT2 select bit (bit 4 at address 9416) = “0” and the D-A1 output enable bit (bit 1
at address 9616) = “0.” When an external trigger is selected, pin AN7 cannot be used as an analog input pin.
6: When this bit is cleared from “1” to “0,” be sure to start the A-D conversion or D-A conversion after an interval of 1 µs or
more has elapsed.
7: Writing to each bit of the A-D control register 1 must be performed while the A-D conversion halts.
1
1
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
A-D control register 1 (Address 1F16)
A-D sweep pin select bits
(Valid in the single sweep and repeat
sweep modes.) (Note 1)
Fix this bit to “0.”
Resolution select bit
A-D conversion frequency (
φ
AD) select
bit 1
External trigger polarity select bit
(Valid when external trigger selected.)
VREF connection select bit (Note 6)
The value is “0” at reading.
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : Pins AN0 and AN1 (2 pins)
0 1 : Pins AN0 to AN3 (4 pins)
1 0 : Pins AN0 to AN5 (6 pins) (Notes 2, 3)
1 1 : Pins AN0 to AN7 (8 pins) (Notes 2 to 5)
b1 b0
0 : 8-bit resolution mode
1 : 10-bit resolution mode
See Table 13.2.1.
0
0 : Falling edge of the pin ADTRG’s input signal
1 : Rising edge of the pin ADTRG’s input signal
0 : Pin VREF is connected.
1 : Pin VREF is disconnected.
Bit nameBit Function At reset R/W
Fig. 13.2.3 Structure of A-D control register 1
13.2 Block description
A-D CONVERTER
7902 Group User’s Manual
13-6
13.2 Block description
(1) Analog input pin select bits (bits 0 to 2 at address 1E16)
These bits are used to select an analog input pin in the one-shot mode or repeat mode. Pins which
are not selected as analog input pins serve as programmable I/O port pins.
Also, these bits must be specified again if the user switches the operation mode to the one-shot
mode or repeat mode after the A-D conversion is performed in the single sweep mode or repeat
sweep mode.
(2) A-D operation mode select bit (bits 3 and 4 at address 1E16)
These bits are used to select the operation mode of the A-D converter.
(3) Trigger select bit (bit 5 at address 1E16)
This bit is used to select the source of trigger occurrence. (Refer to section “(4) A-D conversion
start bit.”)
(4) A-D conversion start bit (bit 6 at address 1E16)
When internal trigger is selected
Setting this bit to “1” generates a trigger, causing the A-D converter to start its operation. Clearing
this bit to “0” causes the A-D converter to halt its operation.
In the one-shot mode or single sweep mode, this bit is cleared to “0” when the A-D conversion is
completed. In the repeat mode or repeat sweep mode, the A-D converter continues its operation
until this bit is cleared to “0” by software.
When external trigger is selected
When pin ADTRG’s level changes from “H” to “L” (when the external trigger polarity select bit = “0”)
or from “L” to “H” (when the external trigger polarity select bit = “1”) with this bit = “1,” a trigger
is generated, causing the A-D converter to start its operation. The A-D converter halts when this
bit is cleared to “0.”
In the one-shot mode or single sweep mode, this bit remains set to “1” even after the A-D
conversion is completed. In the repeat mode or repeat sweep mode, the A-D converter continues
its operation until this bit is cleared to “0” by software.
(5) A-D conversion frequency (
φ
AD) select bit 0 (bit 7 at address 1E16), A-D conversion frequency
(
φ
AD) select bit 1 (bit 4 at address 1F16)
These bits are used to select the operation clock (
φ
AD) of the A-D converter. Table 13.2.1 lists the
conversion time per one analog input pin.
Since the A-D converter’s comparator consists of capacity coupling amplifiers, be sure to keep that
φ
AD 250 kHz during A-D conversion.
Table 13.2.1 Conversion time per one analog input pin
0
0
1
1
8-bit resolution mode 10-bit resolution mode
fsys = 26 MHz
Conversion time (µs) (Note)
φ
AD
0
1
0
1
f2 divided by 4
f2 divided by 2
f2
f1
15.08
7.54
3.77
1.88
A-D conversion
frequency (
φ
AD)
select bit 1
A-D conversion
frequency (
φ
AD)
select bit 0
Do not select.
Note: This applies when the peripheral devices’ clock select bit 0, 1 (bits 6, 7 at address BC16) = “002.”
18.15
9.07
4.54
A-D CONVERTER
7902 Group User’s Manual 13-7
(6) A-D sweep pin select bit (bits 0 and 1 at address 1E16)
These bits are used to select analog input pins in the single sweep mode or repeat sweep mode.
Pins which are not selected as analog input pins serve as programmable I/O port pins.
(7) Resolution select bit (bit 3 at address 1F16)
This bit is used to select a resolution.
(8) External trigger polarity select bit (bit 5 at address 1F16)
When an external trigger is selected, this bit is used to select the polarity of the trigger. (Refer to
section “(4) A-D conversion start bit.”)
(9) VREF connection select bit (bit 6 at address 1F16)
When the A-D converter and D-A converter are not used, this bit is used to disconnect the resistor
ladder network of the A-D converter from the reference voltage input pin (VREF).
When the resistor ladder network and pin VREF is disconnected, the current is not flowed from pin VREF
to resistor ladder network. Accordingly, the power dissipation can be saved.
After this bit changes from “1” (VREF disconnect) to “0” (VREF connected), start of the A-D conversion
must be 1 µs or more later.
13.2 Block description
A-D CONVERTER
7902 Group User’s Manual
13-8
13.2 Block description
13.2.2 A-D register i (i = 0 to 7)
Figure 13.2.4 shows the structure of the A-D register i. When the A-D conversion is completed, the conver-
sion result (contents of the successive approximation register) is stored into this register. Each A-D register
i corresponds to an analog input pin (ANi).
Fig. 13.2.4 Structure of A-D register i
Undefined
0
RO
Bit
7 to 0
15 to 8
Function At reset R/W
Reads an A-D conversion result.
The value is “0” at reading.
b0b7
A-D register 0 (Addresses 2116, 2016)
A-D register 1 (Addresses 2316, 2216)
A-D register 2 (Addresses 2516, 2416)
A-D register 3 (Addresses 2716, 2616)
A-D register 4 (Addresses 2916, 2816)
A-D register 5 (Addresses 2B16, 2A16)
A-D register 6 (Addresses 2D16, 2C16)
A-D register 7 (Addresses 2F16, 2E16)
b0b7
(b15) (b8)
When 8-bit resolution mode is selected
A-D register 0 (Addresses 2116, 2016)
A-D register 1 (Addresses 2316, 2216)
A-D register 2 (Addresses 2516, 2416)
A-D register 3 (Addresses 2716, 2616)
A-D register 4 (Addresses 2916, 2816)
A-D register 5 (Addresses 2B16, 2A16)
A-D register 6 (Addresses 2D16, 2C16)
A-D register 7 (Addresses 2F16, 2E16)
When 10-bit resolution mode is selected
Undefined
0
RO
9 to 0
15 to 10
Reads an A-D conversion result.
The value is “0” at reading.
b0b7b0b7
(b15) (b8)
Bit Function At reset R/W
A-D CONVERTER
7902 Group User’s Manual 13-9
13.2.3 A-D conversion interrupt control register
Figure 13.2.5 shows the structure of the A-D conversion interrupt control register. For details about interrupts,
refer to “CHAPTER 7. INTERRUPTS.”
Fig. 13.2.5 Structure of A-D conversion interrupt control register
(1) Interrupt priority level select bits (bits 2 to 0)
These bits are used to select an A-D conversion interrupt’s priority level. When using an A-D conversion
interrupt, be sure to select one of the priority levels (1 to 7). When an A-D conversion interrupt
request occurs, its priority level is compared with the processor interrupt priority level (IPL). The
requested interrupt is enabled only when its priority level is higher than the IPL. (However, this
applies when the interrupt disable flag (I) = “0.”)
To disable an A-D conversion interrupt, set these bits to “0002” (level 0).
(2) Interrupt request bit (bit 3)
This bit is set to “1” when an A-D conversion interrupt request has occurred. This bit is automatically
cleared to “0” when the A-D conversion interrupt request has accepted. This bit can be set to “1” or
cleared to “0” by software.
A-D conversion interrupt control register (Address 7016)b7 b6 b5 b4 b3 b2 b1 b0
0
1
2
3
7 to 4
Interrupt priority level select bits
Interrupt request bit
Nothing is assigned.
Notes 1: Clear this bit “0” by software before using an A-D conversion interrupt.
2: When writing to this bit, use the MOVM (MOVMB) or STA (STAB, STAD) instruction.
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1b0
0 : No interrupt requested
1 : Interrupt requested
0
0
0
Undefined
(Note 1)
Undefined
RW
RW
RW
RW
(Note 2)
Bit nameBit Function At reset R/W
13.2 Block description
A-D CONVERTER
7902 Group User’s Manual
13-10
13.2 Block description
13.2.4 Port P7 direction register
The A-D converter’s input pins are multiplexed with the port P7 pins. When using these pins as A-D
converter’s input pins, be sure to clear the corresponding bits of the port P7 direction register to “0” in order
to set these pins to the input mode. Figure 13.2.6 shows the correspondence between the port P7 direction
register and the A-D converter’s input pins.
Fig. 13.2.6 Correspondence between port P7 direction register and A-D converter’s input pins
0
1
2
3
4
5
6
7
Port P7 direction register (Address 1116)
Pin AN0
Pin AN1
Pin AN2
Pin AN3
Pin AN4 (Pin INT3)
Pin AN5 (Pin INT4)
Pin AN6 (Pin DA0)
Pin AN7/ADTRG (Pin DA1/INT2)
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
b7 b6 b5 b4 b3 b2 b1 b0
0 : Input mode
1 : Output mode
When using any of these pins as A-D converter’s input
pin, be sure to set its corresponding bit to “0.”
Note: The pin in ( ) is an I/O pin of another internal peripheral device and is multiplexed with the corresponding port P7 pins.
Bit nameBit Function At reset R/W
A-D CONVERTER
7902 Group User’s Manual 13-11
13.3 A-D conversion method
13.3 A-D conversion method
The A-D converter compares the comparison voltage (Vref), which is internally generated according to the
contents of the successive approximation register, with the analog input voltage (VIN), which is input from
the analog input pin (ANi). By reflecting the comparison result on the successive approximation register, VIN
is converted into a digital value. When a trigger is generated, the A-D converter performs the following
processing:
Determining bit 9 of the successive approximation register
The A-D converter compares Vref with VIN. At this time, the contents of the successive approximation
register is “10000000002” (initial value).
Bit 9 of the successive approximation register depends on the comparison result as follows:
When Vref < VIN, bit 9 = “1”
When Vref > VIN, bit 9 = “0”
Determining bit 8 of the successive approximation register
After setting bit 8 of the successive approximation register to “1,” the A-D converter compares Vref with
VIN. Bit 8 depends on the comparison result as follows:
When Vref < VIN, bit 8 = “1”
When Vref > VIN, bit 8 = “0”
Determining bits 7 to LSB of the successive approximation register
Operation is performed for each of bits 7 to 0 in the 10-bit resolution mode.
Operation is performed for each of bits 7 to 2 in the 8-bit resolution mode.
When the LSB is determined, the contents of the successive approximation register (in order words,
conversion result) are transferred to the A-D register i.
Vref is generated according to the latest contents of the successive approximation register. Table 13.3.1 lists
the relationship between the successive approximation register’s contents and Vref. Tables 13.3.2 and 13.3.3
list the changes of the successive approximation register and Vref during the A-D conversion, respectively.
Figure 13.3.1 shows the ideal A-D conversion characteristics in the 10-bit resolution mode.
Successive approximation register’s contents: n
0VREF
1024
1 to 1023 × (n – 0.5)
Vref (V)
0
VREF: Reference voltage
Table 13.3.1 Relationship between successive approximation register’s contents and V
ref
A-D CONVERTER
7902 Group User’s Manual
13-12
13.3 A-D conversion method
Table 13.3.2 Change of successive approximation register and Vref during A-D conversion (8-bit resolution)
Table 13.3.3 Change of successive approximation register and Vref during A-D conversion (10-bit resolution)
±
1
1
n
9
000000000
000000000
100000000
n
9
n
8
10000000
n
9
n
8
n
7
n
6
n
5
n
4
n
3
100
n
9
n
8
n
7
n
6
n
5
n
4
n
3
n
2
00
b9 b0
1st comparison result
2nd comparison result
Successive approximation register
Change of V
ref
A-D converter halt
1st comparison
2nd comparison
3rd comparison
8th comparison
Conversion completed
2
V
REF
2048
V
REF
:
2
V
REF
±
2
V
REF
4
V
REF
2048
V
REF
±
2
V
REF
4
V
REF
8
V
REF
2048
V
REF
± ±
2
V
REF
4
V
REF
8
V
REF
± ...... ±V
REF
256 2048
V
REF
[V]
[V]
[V]
[V]
[V]
4
V
REF
•n
9
= 1
4
V
REF
•n
9
= 0
+
8
V
REF
8
V
REF
•n
8
= 1
•n
8
= 0
+
:
:
::
:
1
1
n
9
000000000
000000000
100000000
n
9
n
8
10000000
n
9
n
8
n
7
n
6
n
5
n
4
n
3
n
2
n
1
1
n
9
n
8
n
7
n
6
n
5
n
4
n
3
n
2
n
1
n
0
b9 b0
±
2
V
REF
2048
V
REF
2
V
REF
±
2
V
REF
4
V
REF
2048
V
REF
±
2
V
REF
4
V
REF
8
V
REF
2048
V
REF
± ±
2
V
REF
4
V
REF
8
V
REF
± ...... ±V
REF
1024 2048
V
REF
[V]
[V]
[V]
[V]
[V]
Successive approximation register
Change of V
ref
A-D converter halt
1st comparison
2nd comparison
3rd comparison
10th comparison
Conversion completed
1st comparison result
2nd comparison result
4
V
REF
•n
9
= 1
4
V
REF
•n
9
= 0
+
8
V
REF
8
V
REF
•n
8
= 1
•n
8
= 0
+
:
:
:
:
:
:
A-D CONVERTER
7902 Group User’s Manual 13-13
Fig. 13.3.1 Ideal A-D conversion characteristics in 10-bit resolution mode
00016
00116
00216
00316
3FE16
3FF16
Analog input voltage
VREF
1024 1 VREF
1024 2 VREF
1024 3 1021
VREF
1024 VREF
1024 1022 VREF
1024 1023 VREF
VREF
1024 0.5
ldeal A-D conversion characteristics
0
A-D conversion result
3FD16
13.3 A-D conversion method
A-D CONVERTER
7902 Group User’s Manual
13-14
13.4 Absolute accuracy and Differential non-linearity error
Fig. 13.4.1 Absolute accuracy of A-D converter (10-bit resolution mode)
13.4 Absolute accuracy and Differential non-linearity error
The A-D converter’s accuracy is described below. Refer to section “Appendix 10.4 A-D converter standard
characteristics,” also.
13.4.1 Absolute accuracy
The absolute accuracy is the difference expressed in the LSB between the actual A-D conversion result
and the output code of an A-D converter with ideal characteristics. (See Figure 13.4.1 for more details.)
The analog input voltage at measurement of the absolute accuracy is assumed to be the mid point of the
analog input voltage width that outputs the same output code from an A-D converter with ideal characteristics.
For example, in the case of the 10-bit resolution mode, when VREF = 5.12 V, 1 LSB width is 5 mV, and 0
mV, 5 mV, 10 mV, 15 mV, 20 mV, ... are selected as the analog input voltages.
The absolute accuracy = ±3 LSB indicates that when the analog input voltage is 25 mV, the output code
expected from an ideal A-D conversion characteristics is “00516,” but the actual A-D conversion result is
between “00216” to “00816.”
The absolute accuracy includes the zero error and the full-scale error.
The absolute accuracy degrades when VREF is lowered. Any of the output codes for analog input voltages
in the range from VREF to AVcc is “3FF16.”
00016
00116
00216
00316
00416
00516
00616
05 10152025303540455055
00716
00816
00916
00A16
00B16
+3 LSB
–3 LSB
Ideal A-D conversion
characteristics
Analog input voltage (mV)
Output code
(A-D conversion result)
A-D CONVERTER
7902 Group User’s Manual 13-15
13.4.2 Differential non-linearity error
The differential non-linearity error indicates the difference between the 1 LSB step width (the ideal analog
input voltage width while the same output code is expected to output) of an A-D converter with ideal
characteristics and the actual measured step width (the actual analog input voltage width while the same
output code is output). (See Figure 13.4.2 for more details.) For example, in the case of the 10-bit
resolution mode and VREF = 5.12 V, the 1 LSB width of an A-D converter with ideal characteristics is 5 mV;
but if the differential non-linearity error is ±1 LSB, the actual measured 1 LSB width is in the range from
0 to 10 mV.
Fig. 13.4.2 Differential non-linearity error (10-bit resolution mode)
00016
00116
00216
00316
00416
00516
00616
05 1015202530354045
00716
00816
00916
Output code
(A-D conversion result)
Differential non-linearity error
Analog input voltage (mV)
1 LSB width with ideal
A-D conversion characteristics
13.4 Absolute accuracy and Differential non-linearity error
A-D CONVERTER
7902 Group User’s Manual
13-16
13.5 Comparison voltage in 8-bit resolution mode
In the 8-bit resolution mode, which is selected by the resolution select bit, the high-order 8 bits of the 10-
bit successive approximation register are treated as the A-D conversion result. Accordingly, when compared
with the 8-bit A-D converter, a comparison reference voltage is different by 3VREF/2048. (Refer to the
underlined portions in Table 13.5.1). The difference of the output code change point is generated as shown
in Figure 13.5.1.
Table 13.5.1 Comparison voltage
13.5 Comparison voltage in 8-bit resolution mode
M37902’s 8-bit resolution mode 8-bit A-D converter
VREF
2 8VREF
210
n – VREF
28VREF
28
n – 0.5
Comparison voltage
Vref
VREF : Reference voltage
n : Contents of successive approximation register
0.5
Fig. 13.5.1 Difference of output code change point
07
05
06
03
00
02
Analog input voltage (mV)
02
01
00
04
02
01
00 01
08
09
10 30
17.5 37.5
8-bit A-D converter’s ideal characteristics (when V
REF
= 5.12 V)
Output code
(A-D conversion result)
Output code
(A-D conversion result)
8-bit
resolution
mode
10-bit
resolution
mode
(Note)
Analog input voltage (mV)
8-bit resolution mode
10-bit resolution mode
Note: Difference of output code change point
VREF: Reference voltage
(Note)
M37902’s A-D converter’s ideal characteristics (when V
REF
= 5.12 V)
A-D CONVERTER
7902 Group User’s Manual 13-17
13.6 One-shot mode
13.6 One-shot mode
In the one-shot mode, the A-D conversion for an input voltage from one selected analog input pin is
performed once, and an A-D conversion interrupt request occurs at completion of A-D conversion.
13.6.1 Settings for one-shot mode
Figure 13.6.1 shows an initial setting example for related registers in the one-shot mode.
When using an interrupt, it is necessary to set the related registers to enable an interrupt. Refer to
“CHAPTER 7. INTERRUPTS” for more details.
Fig. 13.6.1 Initial setting example for related registers in one-shot mode
A-D control registers 0 and 1
b7 b0
A-D control register 0 (Address 1E
16
)
000
0 0 0 : AN
0
selected
0 0 1 : AN
1
selected
0 1 0 : AN
2
selected
0 1 1 : AN
3
selected
b1b0
b2
Trigger select bit
0 : Internal trigger
1 : External trigger
A-D conversion start bit
0 : A-D conversion halts.
Analog input pin select bits
A-D conversion frequency (φ
AD
) select bit 0
See Table 13.2.1.
One-shot mode
b7
A-D control register 1 (Address 1F
16
)
X : It may be either “0” or “1.”
b0
0
Resolution select bit
0 : 8-bit resolution mode
1 : 10-bit resolution mode
A-D conversion frequency (φ
AD
) select bit 1
See Table 13.2.1.
External trigger polarity select bit
0 : Falling edge of pin AD
TRG
’s input signal
1 : Rising edge of pin AD
TRG
’s input signal
Note: Writing to the following must be performed during the A-D conversion halts (berore an trigger is generated).
• Each bit of the A-D control register 0 (except bit 6)
• Each bit of the A-D control register 1
Port P7 direction register
b7 b0
Port P7 direction register (Address 11
16
)
AN
0
AN
1
AN
2
AN
3
Interrupt priority level
b7 b0
A-D conversion interrupt control register
(Address 70
16
)
Interrupt priority level select bits
Set the level to one of 1 through 7 when using this
interrupt.
Set the level 0 when disabling interrupts.
Interrupt request bit
“0” : No interrupt requested
0
Clear the bits corresponding to analog input
pins to “0.”
Clear bit 7 to “0” when selecting an external
trigger.
Set A-D conversion start bit to “1.”
b7 b0
A-D control register 0
(Address 1E
16
)
A-D conversion start bit
1
Operation starts.
Trigger generated
Input an external trigger to
pin AD
TRG
(falling edge/
rising edge).
Selecting external trigger
Setting internal trigger
V
REF
connection select bit
0 : Pin V
REF
is connected.
0
1 0 0 : AN
4
selected
1 0 1 : AN
5
selected
1 1 0 : AN
6
selected
1 1 1 : AN
7
selected
AN
4
AN
5
AN
6
AN
7
A-D CONVERTER
7902 Group User’s Manual
13-18
13.6 One-shot mode
13.6.2 One-shot mode operation
(1) When an internal trigger is selected
The A-D converter starts its operation when the A-D conversion start bit is set to “1.”
The A-D conversion is completed after 49 cycles of
φ
AD in the 8-bit resolution mode, or 59 cycles
of
φ
AD in the 10-bit resolution mode. Then, the contents of the successive approximation register
(conversion result) are transferred to the A-D register i.
At the same time as step , the A-D conversion interrupt request bit is set to “1.”
The A-D conversion start bit is cleared to “0,” and the A-D converter halts.
(2) When an external trigger is selected
The A-D converter starts its operation when the input level to pin ADTRG changes from “H” to “L”
(when the external trigger polarity select bit = “0”) or from “L” to “H” (when the external trigger
polarity select bit = “1”) while the A-D conversion start bit = “1.”
The A-D conversion is completed after 49 cycles of
φ
AD in the 8-bit resolution mode, or 59 cycles
of
φ
AD in the 10-bit resolution mode. Then, the contents of the successive approximation register
(conversion result) are transferred to the A-D register i.
At the same time as step , the A-D conversion interrupt request bit is set to “1.”
The A-D converter halts.
The A-D conversion start bit remains set to “1” after step . Accordingly, the operation of the
A-D converter can be performed again from step if an trigger is generated (the level at pin ADTRG
changes from “H” to “L” or from “L” to “H.”)
Also, if an trigger is generated during the operation of A-D converter, the operation at that point is
cancelled and is restarted from step .
Figure 13.6.2 shows the conversion operation in the one-shot mode.
Fig. 13.6.2 Conversion operation in one-shot mode
Trigger generated
Convert input voltage at
pin AN
i
.
Conversion result A-D register i
A-D conversion interrupt request occurs.
A-D converter halts.
A-D CONVERTER
7902 Group User’s Manual 13-19
13.7 Repeat mode
13.7 Repeat mode
In the repeat mode, the A-D conversion for an input voltage from one selected analog input pin is performed
repeatedly.
In this mode, no A-D conversion interrupt request occurs. Additionally, the A-D conversion start bit (bit 6 at
address 1E16) remains set to “1” until it is cleared to “0” by software, and the A-D converter repeates its
operation while the A-D conversion start bit = “1.”
13.7.1 Settings for repeat mode
Figure 13.7.1 shows an initial setting example for related registers in the repeat mode.
Fig. 13.7.1 Initial setting example for related registers in repeat mode
A-D control registers 0 and 1
b7 b0 A-D control register 0 (Address 1E16)
010
b1b0
b2
Trigger select bit
0 : Internal trigger
1 : External trigger
A-D conversion start bit
0 : A-D conversion halts.
Analog input pin select bits
A-D conversion frequency (φ
AD
) select bit 0
See Table 13.2.1.
Repeat mode
b7 A-D control register 1 (Address 1F16)
: It may be either “0” or “1.”
b0
0
Resolution mode select bit
0 : 8-bit resolution mode
1 : 10-bit resolution mode
A-D conversion frequency (φ
AD
) select bit 1
See Table 13.2.1.
External trigger polarity select bit
0 : Falling edge of pin AD
TRG
’s input signal
1 : Rising edge of pin AD
TRG
’s input signal
Note: Writing to the following must be performed during the A-D conversion halts
(berore an trigger is generated).
• Each bit of the A-D control register 0 (except bit 6)
• Each bit of the A-D control register 1
Set A-D conversion start bit to “1.”
b7 b0 A-D control register 0
(Address 1E16)
A-D conversion start bit
1
Operation starts.
Trigger generated
Input an external trigger to
pin ADTRG (falling edge/
rising edge).
Selecting external trigger
Setting internal trigger
V
REF
connection select bit
0 : Pin V
REF
is connected.
0
0 0 0 : AN
0
selected
0 0 1 : AN
1
selected
0 1 0 : AN
2
selected
0 1 1 : AN
3
selected
1 0 0 : AN
4
selected
1 0 1 : AN
5
selected
1 1 0 : AN
6
selected
1 1 1 : AN
7
selected
Port P7 direction register
b7 b0
Port P7 direction register (Address 1116)
AN
0
AN
1
AN
2
AN
3
Clear the bits corresponding to analog input
pins to “0.”
Clear bit 7 to “0” when selecting an external
trigger.
AN
4
AN
5
AN
6
AN
7
A-D CONVERTER
7902 Group User’s Manual
13-20
13.7 Repeat mode
13.7.2 Repeat mode operation
(1) When an internal trigger is selected
The A-D converter starts its operation when the A-D conversion start bit is set to “1.”
The 1st A-D conversion is completed after 49 cycles of
φ
AD in the 8-bit resolution mode, or 59
cycles of
φ
AD in the 10-bit resolution mode. Then, the contents of the successive approximation
register (conversion result) are transferred to the A-D register i.
The A-D converter repeats its operation until the A-D conversion start bit is cleared to “0” by
software. The conversion result is transferred to the A-D register i each time the conversion is
completed.
(2) When an external trigger is selected
The A-D converter starts its operation when the input level at pin ADTRG changes from “H” to “L”
(when the external trigger polarity select bit = “0”) or from “L” to “H” (when the external trigger
polarity select bit = “1”) while the A-D conversion start bit = “1.”
The 1st A-D conversion is completed after 49 cycles of
φ
AD in the 8-bit resolution mode, or 59
cycles of
φ
AD in the 10-bit resolution mode. Then, the contents of the successive approximation
register (conversion result) are transferred to the A-D register i.
The A-D converter repeates its operation until the A-D conversion start bit is cleared to “0” by
software. The conversion result is transferred to the A-D register i each time the conversion is
completed.
If an trigger is generated (the level at pin ADTRG changes from “H” to “L” or from “L” to “H.”) during
the operation of the A-D converter, the operation at that point is cancelled and is restarted from step
.
Figure 13.7.2 shows the conversion operation in the repeat mode.
Fig. 13.7.2 Conversion operation in repeat mode
Convert input voltage at
pin ANi.
Conversion result A-D register i
Trigger generated
A-D CONVERTER
7902 Group User’s Manual 13-21
13.8 Single sweep mode
13.8 Single sweep mode
In the single sweep mode, the A-D conversions for the input voltages from multiple selected analog input
pins are performed, one at a time. The A-D conversion is performed in ascending sequence from pin AN0
to pin AN7. An A-D conversion interrupt request occurs when the A-D conversions for all selected input pins
are completed.
13.8.1 Settings for single sweep mode
Figure 13.8.1 shows an initial setting example for related registers in the single sweep mode.
When using an interrupt, it is necessary to set the related registers to enable an interrupt. Refer to
“CHAPTER 7. INTERRUPTS” for more details.
Fig. 13.8.1 Initial setting example for related registers in single sweep mode
A-D control registers 0 and 1
b7 b0
A-D control register 0 (Address 1E
16
)
100
Trigger select bit
0 : Internal trigger
1 : External trigger
A-D conversion start bit
0 : A-D conversion halts.
A-D conversion frequency (φAD) select bit 0
See Table 13.2.1.
Single sweep mode
b7
A-D control register 1 (Address 1F
16
)
: It may be either “0” or “1.”
b0
0
Resolution select bit
0 : 8-bit resolution mode
1 : 10-bit resolution mode
A-D sweep pin select bits
0 0 : AN0, AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
A-D conversion frequency (φAD) select bit 1
See Table 13.2.1.
External trigger polarity select bit
0 : Falling edge of pin ADTRG’s input signal
1 : Rising edge of pin ADTRG’s input signal
Note: Writing to the following must be performed during the A-D conversion halts (berore an trigger is generated).
• Each bit of the A-D control register 0 (except bit 6)
• Each bit of the A-D control register 1
Interrupt priority level
b7 b0
A-D conversion interrupt control register 0
(Address 70
16
)
Interrupt priority level select bits
Set the level to one of 1 through 7 when using
this interrupt.
Set the level 0 when disabling interrupts.
Interrupt request bit
“0” : No interrupt requested.
0
Set A-D conversion start bit to “1.”
b7 b0
A-D control register 0
(Address 1E
16
)
A-D conversion start bit
1
Operation starts.
Trigger generated
Input an external trigger to
pin AD
TRG
(falling edge/
rising edge).
Selecting external trigger
Setting internal trigger
VREF connection select bit
0 : Pin VREF is connected.
0
1 0 : AN0 to AN5 (6 pins)
1 1 : AN0 to AN7 (8 pins)
Port P7 direction register
b7 b0
Port P7 direction register (Address 11
16
)
AN0
AN1
AN2
AN3
Clear the bits corresponding to analog input
pins to “0.”
Clear bit 7 to “0” when selecting an external
trigger.
AN4
AN5
AN6
AN7
A-D CONVERTER
7902 Group User’s Manual
13-22
13.8 Single sweep mode
13.8.2 Single sweep mode operation
(1) When an internal trigger is selected
The A-D converter starts its operation for the input voltage at pin AN0 when the A-D conversion start
bit is set to “1.”
The A-D conversion for the input voltage at pin AN0 is completed after 49 cycles of
φ
AD in the 8-
bit resolution mode, or 59 cycles of
φ
AD in the 10-bit resolution mode. Then, the contents of the
successive approximation register (conversion result) are transferred to the A-D register 0.
The A-D conversions for all selected analog input pins are performed.
The conversion result is transferred to the corresponding A-D register i each time when the A-D
conversion per one pin is completed.
When step is completed, the A-D conversion interrupt request bit is set to “1.”
The A-D conversion start bit is cleared to “0,” and the A-D converter halts.
(2) When an external trigger is selected
The A-D converter starts its operation for the input voltage at pin AN0 when the input level at pin ADTRG
changes from “H” to “L” (when the external trigger polarity select bit = “0”) or from “L” to “H” (when the
external trigger polarity select bit = “1”) while the A-D conversion start bit = “1.”
The A-D conversion for the input voltage at pin AN0 is completed after 49 cycles of
φ
AD in the 8-
bit resolution mode, or 59 cycles of
φ
AD in the 10-bit resolution mode. Then, the contents of the
successive approximation register (conversion result) are transferred to the A-D register 0.
The A-D conversion for all selected analog input pins are performed.
The conversion result is transferred to the A-D register i each time each when the A-D conversion
per one pin is completed.
When step is completed, the A-D conversion interrupt request bit is set to “1.”
The A-D conversion halts.
The A-D conversion start bit remains set to “1” after step . Accordingly, the operation of the A-D
converter can be performed again from step if an trigger is generated (the level at pin ADTRG
changes from “H” to “L” or from “L” to “H.”)
If an trigger is generated during the operation of the A-D converter, the operation at that point is
cancelled and is restarted from step .
Figure 13.8.2 shows the conversion operation in the single sweep mode.
Fig. 13.8.2 Conversion operation in single sweep mode
Convert input voltage at
pin AN
0
.Conversion result A-D register 0
A-D register i
A-D register 1
Conversion result
Conversion result
A-D converter halts.
A-D converter interrupt
request occurs.
Convert input voltage at
pin AN
1
.
Convert input voltage at
pin AN
i
.
Trigger generated
A-D CONVERTER
7902 Group User’s Manual 13-23
13.9 Repeat sweep mode
13.9 Repeat sweep mode
In the repeat sweep mode, the A-D conversions for input voltages from multiple selected analog input pins
are performed repeatedly. The A-D conversion is performed in ascending sequence from pin AN0 to pin AN7.
In this mode, no A-D conversion interrupt request occurs. Additionally, the A-D conversion start bit (bit 6 at
address 1E16) remains set to “1” until it is cleared to “0” by software, and the A-D converter repeates its
operation while the A-D conversion start bit = “1.”
13.9.1 Settings for repeat sweep mode
Figure 13.9.1 shows an initial setting example for related registers in the repeat sweep mode.
Fig. 13.9.1 Initial setting example for related registers in repeat sweep mode
A-D control registers 0 and 1
b7 b0 A-D control register 0 (Address 1E16)
110
Trigger select bit
0 : Internal trigger
1 : External trigger
A-D conversion start bit
0 : A-D conversion halts.
A-D conversion frequency (φAD) select bit 0
See Table 13.2.1.
Repeat sweep mode
b7 A-D control register 1 (Address 1F16)
: It may be either “0” or “1.”
b0
0
Resolution select bit
0 : 8-bit resolution mode
1 : 10-bit resolution mode
A-D sweep pin select bits
0 0 : AN0, AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
A-D conversion frequency (φAD) select bit 1
See Table 13.2.1.
External trigger polarity select bit
0 : Falling edge of pin ADTRG’s input signal
1 : Rising edge of pin ADTRG’s input signal
Note: Writing to the following must be performed during the A-D conversion halts
(berore an trigger is generated).
• Each bit of the A-D control register 0 (except bit 6)
• Each bit of the A-D control register 1
Set A-D conversion start bit to “1.”
b7 b0 A-D control register 0
(Address 1E16)
A-D conversion start bit
1
Operation starts.
Trigger generated
Input an external trigger to
pin ADTRG (falling edge/
rising edge)
Selecting external trigger
Setting internal trigger
VREF connection select bit
0 : Pin VREF is connected.
0
1 0 : AN0 to AN5 (6 pins)
1 1 : AN0 to AN7 (8 pins)
Port P7 direction register
b7 b0
Port P7 direction register (Address 1116)
AN0
AN1
AN2
AN3
Clear the bits corresponding to analog input
pins to “0.”
Clear bit 7 to “0” when selecting an external
trigger.
AN4
AN5
AN6
AN7
A-D CONVERTER
7902 Group User’s Manual
13-24
13.9 Repeat sweep mode
13.9.2 Repeat sweep mode operation
(1) When an internal trigger is selected
The A-D converter starts its operation for the input voltage at pin AN0 when the A-D conversion start
bit is set to “1.”
The A-D conversion for the input voltage at pin AN0 is completed after 49 cycles of
φ
AD in the 8-
bit resolution mode, or 59 cycles of
φ
AD in the 10-bit resolution mode. Then, the contents of the
successive approximation register (conversion result) are transferred to the A-D register 0.
The A-D conversions for all selected analog input pins are performed.
The conversion result is transferred to the correponding A-D register i each time when the A-D
conversion per one pin is completed.
The A-D conversions for all selected analog input pins are performed again.
The A-D converter repeates its operation until the A-D conversion start bit is cleared to “0” by
software.
(2) When an external trigger is selected
The A-D converter starts its operation for the input voltage at pin AN0 when the input level at pin ADTRG
changes from “H” to “L” (when the external trigger polarity select bit = “0”) or from “L” to “H” (when the
external trigger polarity select bit = “1”) while the A-D conversion start bit = “1.”
The A-D conversion for the input voltage at pin AN0 is completed after 49 cycles of
φ
AD in the 8-
bit resolution mode, or 59 cycles of
φ
AD in the 10-bit resolution mode. Then, the contents of the
successive approximation register (conversion result) are transferred to the A-D register 0.
The A-D conversions for all selected analog input pins is performed.
The conversion result is transferred to the correponding A-D register i each time when the A-D
conversion per one pin is completed.
The A-D conversion for all selected analog input pins are performed again.
The A-D converter repeates its operation until the A-D conversion start bit is cleared to “0” by
software.
When the level at pin ADTRG changes from “H” to “L” or from “L” to “H” during the operation of the
A-D converter, the operation at that point is cancelled and is restarted from step .
Figure 13.9.2 shows the conversion operation in the repeat sweep mode.
Fig. 13.9.2 Conversion operation in repeat sweep mode
Convert input voltage at pin AN
0
.Conversion result A-D register 0
A-D register i
A-D register 1
Conversion result
Conversion result
Convert input voltage at pin AN
1
.
Convert input voltage at pin AN
i
.
Trigger generated
A-D CONVERTER
7902 Group User’s Manual 13-25
[Precautions for A-D converter]
[Precautions for A-D converter]
1. Be sure to clear the VREF connection select bit to “0.”
2. Writing to the following must be performed before a trigger is generated (in other words, while the A-D
converter halts).
• Each bit of the A-D control register 0, except bit 6
• Each bit of the A-D control register 1
Especially, when any instruction which clears the VREF connection select bit from “1” to “0” has been
executed (in other words, the resistor ladder network is connected with pin VREF by this instruction), the
occurrence of an trigger must be performed after an interval of 1 µs or more has elapsed.
3. When an external trigger is selected, pin AN7/ADTRG is disconnected from the comparator. Accordingly,
pin AN7/ADTRG cannot serve as an analog input pin.
When pin AN7 is selected as analog input pin while an external trigger is selected, an undefined value
is stored into the A-D register 7 even though the A-D converter operates.
4. When using pin AN4, be sure that the pin INT3 select bit (bit 5 at address 9416) = “0.”
When using pin AN5, be sure that the pin INT4 select bit (bit 6 at address 9416) = “0.”
When using pin AN6, be sure that the D-A0 output enable bit (bit 0 at address 9616) = “0” (output
disabled).
When using pin AN7/ADTRG, be sure that the pin INT2 select bit (bit 4 at address 9416) = “0” and the
D-A1 output enable bit (bit 1 at address 9616) = “0.”
5. Refer to section “Appendix. 7 Countermeasures against noise” when using the A-D converter.
A-D CONVERTER
7902 Group User’s Manual
13-26
[Precautions for A-D converter]
MEMORANDUM
CHAPTER 14CHAPTER 14
D-A CONVERTER
14.1 Overview
14.2 Block description
14.3 D-A conversion method
14.4 Setting method
14.5 Operation description
[Precautions for D-A converter]
D-A CONVERTER
7902 Group User’s Manual
14-2
14.1 Overview, 14.2 Block description
14.1 Overview
The M37902 is provided with three independent D-A converters of the R-2R type with 8-bit resolution. These
D-A converters convert the values loaded in the D-A registers i (i = 0 to 2) to analog voltages and output
them from pin DAi.
14.2 Block description
Figure 14.2.1 shows the block diagram of the D-A converter. The registers related to the D-A converter are
described below.
AA
AA
Data bus
AVSS
VREF
R-2R ladder network
D-A register i (i = 0 to 2)
(Addresses 9816 to 9A16 )
DAi
D-Ai output enable bit
VREF connection
select bit
0
1
Fig. 14.2.1 D-A converter block diagram
D-A CONVERTER
7902 Group User’s Manual 14-3
14.2 Block description
14.2.1 D-A control register
Figure 14.2.2 shows the structure of the D-A control register.
Pin DAi (i = 0 to 2) serves as the analog voltage output pin of the D-A converter. Since pin DAi is equipped
with no internal buffer amplifier, it is necessary to connect a buffer amplifier externally to pin DAi, if this
pin is needed to be connected with a low-impedance load.
Pin DAi is multiplexed with an analog input, serial I/O, or external interrupt input pin. When any of the
D-Ai output enable bits is set to “1” (output enabled), the corresponding pin is used only as pin DAi, not
as any other multiplexed input/output pin (including programmable I/O port pin).
Fig. 14.2.2 Structure of D-A control register
(1) D-Ai output enable bits (Bits 0 to 2)
Setting any of the D-Ai output enable bits to “1” (output enabled) allows the corresponding pin DAi to
output D-A converted analog voltage, regardless of the contents of the corresponding bits of the port
P7 and P8 registers.
14.2.2 D-A Register i (i = 0 to 2)
Each pin DAi outputs the analog voltage corresponding to the value loaded in the D-A register i. Figure
14.2.3 shows the structure of the D-A register i.
0
1
2
7 to 3
Bit nameBit Function
At reset
R/W
D-A0 output enable bit
D-A1 output enable bit
D-A2 output enable bit
Nothing is assigned.
b7 b6 b5 b4 b3 b2 b1 b0
0: Output is disabled.
1: Output is enabled. (Notes 1, 2)
0: Output is disabled.
1: Output is enabled. (Notes 1, 2)
0: Output is disabled.
1: Output is enabled. (Notes 1, 2)
0
0
0
RW
RW
RW
D-A control register (Address 9616)
Notes 1: Pin DAi is multiplexed with analog input pin, serial I/O pin, and external interrupt input pin. When a D-Ai output enable bit =
“1” (in other words, output is enabled.), however, the corresponding pin cannot function as any other multiplexed input/
output pin (including programmable I/O port pin).
2: When not using the D-A converter, be sure to clear the contents of this bit to “0.”
0
7 to 0
Bit
D-A register i (i = 0 to 2) (Addresses 9816 to 9A16)
Function
At reset
R/W
Any value from 0016 through FF16 can be set (Note), and this value is D-A
converted and is output. RW
b0b7
Fig. 14.2.3 Structure of the D-A register i
Undefined
Note: When not using the D-A converter, be sure to clear the contents of these bits to “0016.”
D-A CONVERTER
7902 Group User’s Manual
14-4
14.2.3 A-D control register 1
Figure 14.2.4 shows the structure of the A-D control register 1.
Fig.14.2.4 Structure of A-D control register 1
(1) VREF connection select bit (Bit 6)
This bit is used to disconnect the ladder network of the D-A converters from the reference voltage
input pin (VREF) when A-D and D-A converters are not used.
Disconnecting the ladder network from pin VREF prevents the current flow from pin VREF to the network
to save the current consumption.
When this bit is cleared from “1” (VREF disconnected) to “0” (VREF connected), start D-A conversion after
1 µs or more has elapsed.
14.2 Block description
0
1
2
3
4
5
6
7
Notes 1: These bits are invalid in the one-shot and repeat modes. (They may be either “0” or “1.”)
2: When using pin AN4, be sure that the pin INT3 select bit (bit 5 at address 9416) = “0.”
3: When using pin AN5, be sure that the pin INT4 select bit (bit 6 at address 9416) = “0.”
4: When using pin AN6, be sure that the D-A0 output enable bit (bit 0 at address 9616) = “0” (output disabled).
5: When using pin AN7, be sure that the pin INT2 select bit (bit 4 at address 9416) = “0” and the D-A1 output enable bit (bit 1
at address 9616) = “0.” When an external trigger is selected, pin AN7 cannot be used as an analog input pin.
6: When this bit is cleared from “1” to “0,” be sure to start the A-D conversion or D-A conversion after an interval of 1 µs or
more has elapsed.
7: Writing to each bit of the A-D control register 1 must be performed while the A-D conversion halts.
1
1
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
Bit nameBit
A-D control register 1 (Address 1F16 )
Function
At reset
R/W
A-D sweep pin select bits
(Valid in the single sweep and repeat
sweep modes.) (Note 1)
Fix this bit to “0.”
Resolution select bit
A-D convertion frequency (φ
AD
) select bit 1
External trigger polarity select bit
(Valid when external trigger is selected.)
VREF connection select bit (Note 6)
The value is “0” at reading.
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : Pins AN0 and AN1 (2 pins)
0 1 : Pins AN0 to AN3 (4 pins)
1 0 : Pins AN0 to AN5 (6 pins) (Notes 2, 3)
1 1 : Pins AN0 to AN7 (8 pins) (Notes 2 to 5)
b1 b0
0 : 8-bit resolution mode
1 : 10-bit resolution mode
See Table 13.2.1.
0
0 : Falling edge of the pin ADTRG’s input signal
1 : Rising edge of the pin ADTRG’s input signal
0 : Pin VREF is connected.
1 : Pin VREF is not connected.
D-A CONVERTER
7902 Group User’s Manual 14-5
14.3 D-A conversion method
14.3 D-A conversion method
The reference voltage VREF is divided according to the value loaded in the D-A register i, and it is output
as an analog voltage from pin DAi.
Figure 14.3.1 shows the equivalent circuit diagram of the D-A converter.
2R
RRRRRRR
2R2R 2R 2R 2R 2R2R 2R
LSBMSB
AV
SS
V
REF
D-A register i
D-A
i
output enable bit
DA
i
0
1
01
Note: In this case, the value of D-A register is “2A
16
.”
V
REF
connection select bit
0
1
Fig. 14.3.1 Equivalent circuit diagram of D-A converter
D-A CONVERTER
7902 Group User’s Manual
14-6
14.4 Setting method
Figure 14.4.1 shows an initial setting example of registers related to the D-A converter.
Fig. 14.4.1 Initial setting example of registers related to D-A converter
14.5 Operation description
When any of the D-Ai output enable bits is set to “1,” the value loaded in the D-A register i is converted
to an analog voltage, and the analog voltage is output from pin DAi.
The relationship between the analog output voltage V and value n, which has been loaded in the D-A
register i, can be expressed as follows :
V = VREF (n = 0 to 255)
VREF : Reference voltage
14.4 Setting method, 14.5 Operation description
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b7 A-D control register1
(Address 1F16)
b0
0
VREF connection select bit
0
Analog voltage output started
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AAAAAAAAAAAAA
AAAAAAAAAAAAA
Setting of the D-Ai output enable bit to “1”.
b7 b0 D-A control register (Address 9616)
D-A0 output enable bit
D-A1 output enable bit
D-A2 output enable bit
AAA
AAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
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AAAAAAAAAAAAA
Setting of a value to D-A register i
b7 b0 D-A register 0 (Address 9816)
D-A register 1 (Address 9916)
D-A register 2 (Address 9A16)
A value (0016 to FF16) to be D-A converted is set.
Connection with VREF
n
256
D-A CONVERTER
7902 Group User’s Manual 14-7
[Precautions for D-A converter]
[Precautions for D-A converter]
1. Be sure to clear the VREF connection select bit to “0.”
2. When the instruction of clearing the VREF connection select bit from “1” to “0” is executed (i.e., a ladder
network is connected with pin VREF), be sure to enable the D-Ai output after 1 µs or more has elapsed.
3. Pin DAi is multiplexed with an analog input, serial I/O, or external interrupt input pin. When any of the
D-Ai output enable bits is set to “1” (output enabled), the corresponding pin is used as pin DAi, not as
any other multiplexed input/output pin (including programmable I/O port pin).
4. When not using the D-A converter, be sure to do as follows:
• Clear the D-Ai (i = 0 to 2) output enable bit (bits 0 to 2 at address 9616) to “0.”
• Clear the contents of the D-A register i (addresses 9816 to 9A16) to “0016.”
D-A CONVERTER
7902 Group User’s Manual
14-8
[Precautions for D-A converter]
MEMORANDUM
CHAPTER 15CHAPTER 15
WATCHDOG TIMER
15.1 Block description
15.2 Operation description
[Precautions for watchdog timer]
WATCHDOG TIMER
7902 Group User’s Manual
15-2
15.1 Block description
The watchdog timer functions as follows:
Detects a program runaway.
At stop mode termination, measures a certain time after oscillation starts. (Refer to section “5.3 Stop
mode.”)
15.1 Block description
Figure 15.1.1 shows the block diagram of the watchdog timer, and registers relevant to the watchdog timer
are described below.
1/16
Watchdog timer
frequency select bit
“FFF
16
” is set.
Writing to watchdog
timer register
STP instruction
Watchdog timer
interrupt request
Wf
32
Wf
512
Watchdog timer
f
2
Wait mode
Access to
external area
HLDA
1/16
1
0
• Watchdog timer register: address 60
16
• Watchdog timer frequency select register: bit 0 at address 61
16
• Watchdog timer clock source select bits at STP termination: bits 7, 6 at address 61
16
When the most significant bit of the watchdog timer becomes “0,” this signal will be generated.
Note: During the stop mode and until the stop mode is terminated, setting for disabling the
watchdog timer is ignored. (Refer to section “15.1.3 Particular function select register 2.”)
RESET
Disables watchdog
timer (Note).
fX
16
fX
32
fX
64
fX
128
Watchdog timer clock source select
bits at STP termination
Stop mode
Divided f(X
IN
)
Fig. 15.1.1 Block diagram of watchdog timer
WATCHDOG TIMER
7902 Group User’s Manual 15-3
15.1.1 Watchdog timer
The watchdog timer is a 12-bit counter where the count source which is selected with the watchdog timer
frequency select bit (bit 0 at address 6116) is counted down. A value of “FFF16” is automatically set in the
watchdog timer if any of the following conditions is satisfied. An arbitrary value cannot be set to the
watchdog timer.
When dummy data is written to the watchdog timer register. (See Figure 15.1.2.)
When the most significant bit of watchdog timer becomes “0.”
When the STP instruction is executed. (Refer to section “16.3 Stop mode.”)
At reset
15.1 Block description
Fig. 15.1.2 Structure of watchdog timer register
Fig. 15.1.3 Structure of watchdog timer frequency select register
15.1.2 Watchdog timer frequency select register
Figure 15.1.3 shows the structure of the watchdog timer frequency select register.
Undefined
7 to 0 Initializes the watchdog timer.
When dummy data has been written to this register, the watchdog timer’s value is
initialized to “FFF16” (dummy data: 0016 to FF16).
b0b7
Watchdog timer register (Address 6016)
Bit Function At reset R/W
RW
RW
RW
Bit nameBit
0
5 to 1
6
7
Watchdog timer frequency select register (Address 6116)
Function
At reset
R/W
Watchdog timer frequency
select bit
Nothing is assigned.
Watchdog timer clock source
select bits at STP termination
0
Undefined
0
0
b7 b6 b5 b4 b3 b2 b1 b0
0 : Wf512
1 : Wf32
0 0 : fX32
0 1 : fX16
1 0 : fX128
1 1 : fX64
b7 b6
(1) Watchdog timer frequency select bit (bit 0)
This bit is used to select a count source of the watchdog timer.
(2) Watchdog timer clock source select bits at STP termination (bits 7, 6)
These bits are used to select a count source at stop mode termination.
For details of the operation at stop mode termination, refer to section “16.3 Stop mode.”
WATCHDOG TIMER
7902 Group User’s Manual
15-4
15.1 Block description
15.1.3 Particular function select register 2
When not using the watchdog timer, this register can be used to disable the watchdog timer. Figure 15.1.4
shows the structure of the particular function select register 2.
Fig. 15.1.4 Structure of particular function select register 2
In addition, even when the watchdog timer is disabled by this register, the watchdog timer can be active
only at the stop mode termination if the external clock input select bit (bit 1 at address 6216) = “0.” (Refer
to section “16.3 Stop mode.”)
Undefined
7 to 0
Bit Function
At reset
R/W
Disables the watchdog timer.
When values of “7916” and “5016” succeedingly in this order, the watchdog timer will
stop its operation.
b0b7
Particular function select register 2 (Address 6416)
Note: After reset, this register can be set only once. Writing to this register requires the following procedure:
• Write values of “7916” and “5016” to this register succeedingly in this order.
• For the above writing, be sure to use the MOVMB (MOVM when m = 1) instruction or the STAB (STA when m = 1).
Note that the following: if an interrupt occurs between writing of “7916” and next writing of “5016,” the watchdog timer does not
stop its operation.
If any of the following has been performed after reset, writing to this register is disabled from that time:
• If this register is read out.
• If writing to this register is performed by the procedure other than the above procedure.
WATCHDOG TIMER
7902 Group User’s Manual 15-5
15.2 Operation description
15.2 Operation description
The operations of the watchdog timer are described below.
15.2.1 Basic operation
Watchdog timer starts counting down from “FFF16.”
When the watchdog timer’s most significant bit becomes “0” (counted 2048 times), a watchdog timer
interrupt request occurs. (See Table 15.2.1.)
When the interrupt request occurs in above , a value of “FFF16” is set to the watchdog timer.
A watchdog timer interrupt is a non-maskable interrupt. When a watchdog timer interrupt request is accepted,
the processor interrupt priority level (IPL) is set to “1112.”
Table 15.2.1 Occurrence interval of watchdog timer
interrupt request
f(fsys) = 26 MHz
Occurrence interval (Note)
40.33 ms
2.52 ms
Count source
Wf512
Wf32
Watchdog timer
frequency select bit
0
1
Note: This applies when the peripheral device’s clock
select bits 1, 0 (bits 7, 6 at address BC 16) = “002.”
WATCHDOG TIMER
7902 Group User’s Manual
15-6
Be sure to write dummy data to the watchdog timer register (address 6016) before the most significant bit
of the watchdog timer becomes “0.” When writing to the watchdog timer is not performed owing to a
program runaway and the watchdog timer’s most significant bit becomes “0,” a watchdog timer interrupt
request occurs. This informs that a program runaway has occurred.
In order to reset the microcomputer when a program runaway has been detected, write “1” to the software
reset bit (bit 6 at address 5E16) in the watchdog timer interrupt routine.
Figure 15.2.1 shows an example of a program runaway detected by the watchdog timer.
15.2 Operation description
RTI
Main routine
Watchdog timer interrupt routine
Watchdog timer register
(Address 6016)8-bit dummy data
Watchdog timer
interrupt request occurrence
(In other words, program run-
away is detected.)
Watchdog timer initialized
(Value of watchdog timer :
“FFF16”) (Note 1)
Software reset bit
(bit 6 at address 5E16)“1” (Note 2)Reset microcomputer
Notes 1: Be sure to initialize the watchdog timer before the most significant bit of the
watchdog timer becomes “0.” (In other words, be sure to write dummy data to
address 6016 before a watchdog timer interrupt request occurs).
2: When a program runaway occurs, values of the data bank register (DT), direct
page register (DPRi), etc., may be changed. When “1” is written to the software
reset bit by an addressing mode using DT, DPRi, etc., be sure to set values to
DT and DPRi, etc. again.
Fig. 15.2.1 Example of program runaway detection by watchdog timer
WATCHDOG TIMER
7902 Group User’s Manual 15-7
15.2.2 Stop period
The watchdog timer stops its operation in any of the following cases:
Hold state with an external area accessed (Refer to section “3.4 Hold function.”)
During Wait mode (Refer to section “16.4 Wait mode.”)
Stop mode (Refer to section “16.3 Stop mode.”)
When state or has been terminated, the watchdog timer restarts counting from the state immediately
before it stops its operation. For the watchdog timer’s operation at termination of state , refer to section
“15.2.3 Operation in stop mode.”
15.2.3 Operations in stop mode
When the STP instruction has been executed, a value of “FFF16” is set to the watchdog timer, and the
watchdog timer stops its operation in the stop mode. Immediately after the stop mode termination, the
watchdog timer operates as follows.
(1) When stop mode is terminated by hardware reset
Supply of
φ
CPU and
φ
BIU starts immediately after the stop mode termination, and the microcomputer
performs “operation after reset.” (Refer to “CHAPTER 4. RESET.”) The watchdog timer frequency
select bit becomes “0,” and the watchdog timer starts counting of Wf512 from “FFF16.”
(2) When stop mode is terminated by interrupt occurrence (with watchdog timer used) (Note)
Immediately after the stop mode termination, the watchdog timer starts counting the count source
selected by the watchdog timer clock source select bits at STP termination (bits 6, 7 at address 6116),
starting from “FFF16.” It is independent of the watchdog timer frequency select bit (bit 0 at address
6116). When the most significant bit of the watchdog timer becomes “0,” supply of
φ
CPU and
φ
BIU starts.
(At this time, no watchdog timer interrupt request occurs.)
When supply of
φ
CPU and
φ
BIU starts, the routine of the interrupt which the microcomputer used to
terminate the stop mode is executed. The watchdog timer restarts counting of the count source (Wf32
or Wf512), which was counted immediately before execution of the STP instruction, starting from “FFF16.”
Note: For the setting of the usage of the watchdog timer, refer to section “16.3 Stop mode.”
(3) When stop mode is terminated by interrupt occurrence (with watchdog timer not used) (Note)
Supply of
φ
CPU and
φ
BIU starts immediately after the stop mode termination, and the routine of the
interrupt which the microcomputer used to terminate the stop mode is executed. The watchdog timer
restarts counting of the count source (Wf32 or Wf512), which was counted immediately before execution
of the STP instruction, starting from “FFF16.”
Note: For the setting of the usage of the watchdog timer, refer to section “16.3 Stop mode.”
15.2 Operation description
WATCHDOG TIMER
7902 Group User’s Manual
15-8
[Precautions for watchdog timer]
[Precautions for watchdog timer]
1. When dummy data has been written to address 6016 with the 16-bit data length, writing to address 6116
is simultaneously performed. Accordingly, when the user does not want to change the contents of the
watchdog timer frequency select bit (bit 0 at address 6116) and watchdog timer clock source select bits
at STP termination (bits 6, 7 at address 6116), be sure to write the previous value to the bit simultaneously
with writing to address 6016.
2. When the STP instruction is executed, the watchdog timer stops its operation. If the STP instruction’s
code (3116, 3016) has accidentally been executed owing to a program runaway, the watchdog timer stops
its operation. Therefore, in the system where the watchdog timer is used to detect a program runaway,
we recommend that the STP instruction invalidity select bit (bit 0 at address 6216) = “1.” (STP instruction
is invalid.) Refer to section “16.3 Stop mode.”
CHAPTER 16CHAPTER 16
STOP AND WAIT
MODES
16.1 Overview
16.2 Block description
16.3 Stop mode
16.4 Wait mode
STOP AND WAIT MODES
7902 Group User’s Manual
16-2
16.1 Overview
16.1 Overview
When there is no need for operation of the central processing unit (CPU), the stop and wait modes are used
to stop oscillation or internal clock. As a result, the power consumption can be saved. The microcomputer
enters the stop mode when the STP instruction has been executed; the microcomputer enters the wait mode
when the WIT instruction has been executed.
The stop and wait modes are terminated by an interrupt request occurrence or hardware reset.
Table 16.1.1 lists the states in the stop and wait modes and operations after these modes are terminated.
Table 16.1.1 States in stop and wait modes and operations after these modes are terminated
Active.
Operates (Note 1).
Inactive.
Active.
Inactive.
Operates.
Operates.
Operates.
Operates.
Stopped.
Retains the state at the WIT instruction execution (Note 2).
Floating (Note 2).
Outputs “H” level (Note 2).
Outputs “L” level (Note 2).
Outputs clock φ
1
(Note 2).
Retains the state at the WIT instruction execution.
Inactive.
Can operate only in the
event counter mode.
Can operate only when an
external clock is selected.
Stopped.
Stopped.
Outputs “L” level (Note 2).
Internal peripheral devices
When watchdog timer is used at
termination (See Figure 16.3.1.)
Stop mode
Operation after hardware reset
A0 to A23
D0 to D15
RD, BLW,
BHW, HLDA,
CS0 to CS3
ALE
φ1
The others
Inactive.
Stopped.
Inactive.
Inactive.
Inactive.
Can operate only in the event counter mode.
Can operate only when an external clock is
selected.
Stopped.
Stopped.
Stopped.
Retains the state at the STP instruction execution (Note 2).
Floating (Note 2).
Outputs “H” level (Note 2).
Outputs “L” level (Note 2).
Outputs “L” level (Note 2).
Retains the state at the STP instruction execution.
Pins
Timers A, B
Serial I/O
A-D converter
D-A converter
Watchdog timer
States
Supply of φ
CPU
, φ
BIU
starts after a
certain time has been measured
by using the watchdog timer.
Oscillation
PLL frequency multiplier
φCPU, φBIU
fsys, clock
φ
1,
f1 to f4096
Wf32, Wf 512
Operation after termination
When watchdog timer is not used
at termination (See Figure 16.3.1.)
Wait mode
System clock is active.
(Bit 3 at address 63
16
= “0”) System clock is inactive.
(Bit 3 at address 63
16
= “1”)
Supply of φCPU, φBIU starts
immediately after termi-
nation (Note 3).Operation after hardware reset
Supply of φCPU, φBIU starts immediately after
termination.
Notes 1: This applies when the PLL circuit operation enable bit (bit 1 at address BC16) = “1.”
2: The I/O pins of the external buses and bus control signals can be switched to programmable I/O port
pins by software. (Refer to section “17.2 Bus fixation in stop and wait modes.”)
3: See Table 16.3.2.
Item
Termination due
to interrupt request
occurrence
Termination due
to hardware reset
STOP AND WAIT MODES
7902 Group User’s Manual 16-3
16.2 Block description
16.2 Block description
Figure 16.2.1 shows the block diagram of the clock generating circuit with the STP and WIT instructions.
Also, registers relevant to these modes are described below.
Fig. 16.2.1 Block diagram of clock generating circuit with STP and WIT instructions
f2
f64
f512
f4096
Q
R
S
STP
instruction
φBIU
(Clock for BIU)
φCPU
(Clock for CPU)
CPU wait request
1/4
1/8 1/8
Reset
• Watchdog timer frequency select bit : bit 0 at address 61
16
Watchdog timer clock source select bits at STP termination :
bits 6, 7 at address 61
16
• External clock input select bit : bit 1 at address 62
16
• System clock stop select bit at WIT : bit 3 at address 63
16
• PLL circuit operation enable bit : bit 1 at address BC
16
• PLL multiplication ratio select bits : bits 2, 3 at address BC
16
• System clock select bit : bit 5 at address BC
16
• Peripheral device’s clock select bit 0, 1 : bits 6, 7 at address BC
16
1/8
1/2
1/16
Watchdog
timer
Wf32
Wf512
f16
f1
Peripheral device’s clocks
0
1
Watchdog timer
frequency select bit
XIN XOUT
System clock stop select bi at WIT
1/16
Access to
external area
HLDA
0
1
Watchdog timer clock source select
bits at STP termination
φ1
Wait mode
1
0
1
0
1/2
1
0
1
Wait mode
System clock
frequency select bit
PLL frequency
multiplier
fPLL
VCONT
Wait mode
External clock
input select bit
Q
R
S
STP
instruction
Interrupt
request
Q
R
S
WIT
instruction
Interrupt
request Wait mode
PLL circuit operation enable bit
PLL multiplication ratio select bits
fXIN
f/n
0
fX16
fX32
fX64
fX128
fX16
fX32
fX64
fX128
Peripheral
device’s clock
select bit 0
Peripheral
device’s clock
select bit 1
BIU : Bus interface Unit
CPU : Central Processing Unit
: Signal generated when the watchdog timer’s most significant bit becomes “0.”
fsys
System clock frequency select bit
Operating clock for
serial I/O, timer B
A-D conversion frequency
(φ
AD
) clock source
Operating clock for timer A
External clock input select bit
Interrupt
request
STOP AND WAIT MODES
7902 Group User’s Manual
16-4
16.2 Block description
RW
(Note)
RW
(Note)
RW
0
0
0
Bit nameBit
Particular function select register 0 (Address 6216)
Function At reset R/W
STP instruction invalidity select bit
External clcok input select bit
Fix this bit to “0.”
b7 b6 b5 b4 b3 b2 b1 b0
0 : STP instruction is valid.
1 : STP instruction is invalid.
0 : Oscillation circuit is active. (Oscillator is connected.)
Watchdog timer is used at stop mode termination.
1 : Oscillation circuit is inactive. (External clock is
input.)
When the system clock select bit (bit 5 at address BC
16
) = “0,”
watchdog timer is not used at stop mode termination.
When the system clock select bit = “1,”
watchdog timer is used at stop mode termination.
000000
16.2.1 Particular function select register 0
Figure 16.2.2 shows the structure of the particular function select register 0, and Figure 16.2.3 shows the
writing procedure for the particular function select register 0.
Fig. 16.2.2 Structure of particular function select register 0
Note: Writing to these bits requires the following procedure:
• Write “5516” to this register. (The bit status does not change only by this writing.)
• Succeedingly, write “0” or “1” to each bit.
Also, use the MOVMB (MOVM when m = 1) instruction or STAB (STA when m = 1) instruction.
If an interrupt occurs between writing of “5516” and next writing of “0” or “1,” latter writing may be ignored. When there is a
possibility that an interrupt occurs at the above timing, be sure to read this bit’s contents after writing of “0” or “1,” and verify
whether “0” or “1” has correctly been written or not.
0
1
7 to 2
(1) STP instruction invalidity select bit (bit 0)
Setting this bit to “1” invalidates the STP instruction. When using the stop mode, be sure to clear this
bit to “0.”
Writing to this bit requires the following procedure:
• Write “5516” to address 6216.
• Succeedingly, write “0” or “1” to this bit. (See Figure 16.2.3.)
If an interrupt occurs between writing of “5516” and next writing of “0” or “1,” latter writing may be
ignored. When there is a possibility that an interrupt occurs at the above timing, be sure to read this
bit’s contents after writing of “0” or “1,” and verify whether “0” or “1” has correctly been written or not.
STOP AND WAIT MODES
7902 Group User’s Manual 16-5
16.2 Block description
(2) External clock input select bit (bit 1)
Setting this bit to “1” stops the oscillation driver circuit between pins XIN and XOUT and keeps the output
level at pin XOUT being “H.” (Refer to section “17.4 Stop of oscillation circuit.”) At the stop mode
termination owing to an interrupt occurrence, the watchdog timer is not used if the system clock select
bit (bit 5 at address BC16) = “0,” where as the watchdog timer is used if the system clock select bit
= “1.”
To rewrite this bit, write “0” or “1” just after writing of “5516” to address 6216. (See Figure 16.2.3.)
Note that if an interrupt occurs between writing of “5516” and next writing of “0” or “1,” latter writing
may be ignored. When there is a possibility that an interrupt occurs at the above timing, be sure to
read this bit’s contents after writing of “0” or “1,” and verify whether “0” or “1” has correctly been
written or not.
In addition, even when the watchdog timer is disabled by the particular function select register 2
(address 6416), the watchdog timer can be active only at the stop mode termination if this bit = “0.”
(Refer to section “16.3 Stop mode.”)
Fig. 16.2.3 Writing procedure for particular function select register 0
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
00
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
0
Writing of “5516b0
Particular function select register 0 (Address 6216)
b7
1
Setting completed
AAA
AAA
AAA
10
Writing to bits 0, 1 b0
Particular function select register 0 (Address 6216)
b7
External clock input select bit
0 : Oscillation circuit is active. (Oscillator is connected.)
Watchdog timer is used at stop mode termination.
1 : Oscillation circuit is inactive. (External clock is input.)
When the system clock select bit (bit 5 at address BC16) = “0,”
watchdog timer is not used at stop mode termination.
When the system clock select bit = “1,”
watchdog timer is used at stop mode termination.
STP instruction invalidity select bit
0 : STP instruction is valid.
1 : STP instruction is invalid.
Next
instruction
Note: Bits’ state does not change only
by writing of “5516.”
000000
11
00
STOP AND WAIT MODES
7902 Group User’s Manual
16-6
16.2 Block description
16.2.2 Particular function select register 1
Figure 16.2.4 shows the structure of the particular function select register 1.
Notes 1: At power-on rest, this bit becomes “0.” At hardware reset or software reset, this bit retains the value just before reset.
2: Even when “1” is written, the bit status will not change.
3: Setting this bit to “1” must be performed just before execution of the WIT instruction. Also, after the wait state is terminated,
this bit must be cleared to “0” immediately.
(Note 1)
(Note 1)
0
0
0
0
0
0
0 : External bus
1 : Programmable I/O port
Bit nameBit
Particular function select register 1 (Address 6316)
Function
At reset
R/W
STP-instruction-execution status
bit
WIT-instruction-execution status
bit
Standby state select bit
System clock stop select bit at
WIT (Note 3)
Address output select bit
The value is “0” at reading.
Timer B2 clock source select bit
(Valid in event counter mode)
The value is “0” at reading.
b7 b6 b5 b4 b3 b2 b1 b0
0 : Normal operation.
1 : STP instruction has been executed.
0 : Normal operation.
1 : WIT instruction has been executed.
0 : In wait mode, system clock fsys is active.
1 : In wait mode, system clock fsys is stopped.
0 : Address output changes at access to the internal
area and external area.
1 : Address output changes only at access to the exter-
nal area.
0 : External signal input to the TB2IN pin is counted.
1 : fX32 is counted.
RW
(Note 2)
RW
(Note 2)
RW
RW
RW
RW
Fig. 16.2.4 Structure of particular function select register 1
0
1
2
3
4
5
6
7
(1) STP-instruction-execution status bit (bit 0)
When the microcomputer enters the stop mode, this bit becomes “1,” indicating that the STP instruction
has been executed.
This bit becomes “0” at power-on reset. At hardware reset and software reset, this bit retains the value
immediately before reset. Therefore, this bit is used for the following verification:
• Which of the power-on reset and hardware reset has been used to reset the system?
• Has the hardware reset been used for the stop mode termination?
This bit is cleared to “0” by writing “0” to this bit. Although, even when “1” is written to this bit, this
bit does not change.
At the stop mode termination, be sure to clear this bit to “0” by software.
(2) WIT-instruction-execution status bit (bit 1)
When the microcomputer enters the wait mode, this bit becomes “1,” indicating that the WIT instruction
has been executed.
This bit becomes “0” at power-on reset. At hardware reset and software reset, this bit retains the value
immediately before reset. Therefore, this bit is used for the following verification:
• Which of the power-on reset and hardware reset has been used to reset the system?
• Has the hardware reset been used for the wait mode termination?
This bit is cleared to “0” by writing “0” to this bit. Although, even when “1” is written to this bit, this
bit does not change.
At the wait mode termination, be sure to clear this bit to “0” by software.
STOP AND WAIT MODES
7902 Group User’s Manual 16-7
16.2 Block description
Fig. 16.2.5 Structure of watchdog timer frequency select register
16.2.3 Watchdog timer frequency select register
Figure 16.2.5 shows the structure of the watchdog timer frequency select register.
RW
RW
RW
Bit nameBit
0
5 to 1
6
7
Watchdog timer frequency select register (Address 6116)
Function At reset R/W
Watchdog timer frequency
select bit
Nothing is assigned.
Watchdog timer clock source
select bits at STP termination
0
Undefined
0
0
b7 b6 b5 b4 b3 b2 b1 b0
0 : Wf512
1 : Wf32
0 0 : fX32
0 1 : fX16
1 0 : fX128
1 1 : fX64
b7 b6
(1) Watchdog timer frequency select bit (bit 0)
This bit is used to select a count source of the watchdog timer.
(2) Watchdog timer clock source select bits at STP termination (bits 7, 6)
These bits are used to select a count source at stop mode termination.
For details of the operation at stop mode termination, refer to section “16.3 Stop mode.”
STOP AND WAIT MODES
7902 Group User’s Manual
16-8
16.3 Stop mode
16.3 Stop mode
When the STP instruction has been executed, each of the oscillation and the PLL frequency multiplier’s
operation stops. This state is called “stop mode.”
In the stop mode, even when oscillation becomes inactive, the contents of the internal RAM can be retained
if Vcc (the power source voltage) VRAM (RAM hold voltage). Furthermore, since the CPU and internal
peripheral devices which use any of clocks f1 to f4096, Wf32, Wf512 stop their operations, the power consumption
can be saved. Also, in the stop mode, the state of each I/O pin of the external buses and bus control signals
can be set arbitrarily, the power consumption of the whole system can be saved. (Refer to section “17.2
Bus fixation in stop and wait modes.”)
The stop mode is terminated owing to an interrupt request occurrence or hardware reset.
When terminated owing to an interrupt request occurrence, an instruction can be executed immediately after
termination if all of the following conditions are satisfied. (Refer to section “16.3.2 Terminate operation at
interrupt request occurrence (when not using watchdog timer).”):
• An stable clock is input from the external. The external clock input select bit (bit 1 at address 6216) = “1.”
• The PLL frequency multiplier is not used. The system clock select bit (bit 5 at address BC16) = “0.”
When terminated owing to an interrupt request occurrence, an instruction will be executed after the oscillation
stabilizing time has been measured by using the watchdog timer if any of the following conditions is satisfied.
(Refer to section “16.3.1 Terminate operation at interrupt request occurrence (when using watchdog
timer).”):
• An oscillator is used. The external clock input select bit (bit 1 at address 6216) = “0.”
• The PLL frequency multiplier is used. The system clock select bit (bit 5 at address BC16) = “1.”
16.3.1 Terminate operation at interrupt request occurrence (when using watchdog timer)
At the stop mode termination, execution of an instruction is started after a certain time has been measured
by using the watchdog timer. (See Figure 16.3.1.)
When an interrupt request occurs, an oscillator starts its operation. Also, when the PLL circuit operation
enable bit (bit 1 at address BC16) = “1,” the PLL frequency multiplier starts its operation. Simultaneously
with this, each supply of clocks fsys, φ1, f1 to f4096, Wf32, Wf512 starts.
By start of oscillation in , the watchdog timer starts its operation. Regardless of the watchdog timer
frequency select bit (bit 0 at address 6116), the watchdog timer counts a count source (fX16 to fX128),
which is selected by the watchdog timer clock source select bits at STP termination (bits 6, 7 at address
6116). This counting is started from a value of “FFF16.”
When the most significant bit (MSB) of the watchdog timer becomes “0,” each supply of φCPU, φBIU starts.
(At this time, no watchdog timer interrupt request occurs.) Also, the count source of the watchdog timer
returns to the count source selected by the watchdog timer frequency select bit (Wf32 or Wf512).
The interrupt request which occurred in is accepted.
For the watchdog timer, refer to “CHAPTER 15. WATCHDOG TIMER.”
Table 16.3.1 lists the interrupts which can be used to terminate the stop mode.
Table 16.3.1 Interrupts which can be used to terminate stop mode
Usage condition for interrupt request occurrence
INT3 interrupt: when the key input interrupt is invalid.
When the key input interrupt is selected.
In event counter mode
When an external clock is selected.
Interrupt
NMI interrupt
INTi interrupt (i = 0 to 4)
Key input interrupt
Timer Ai interrupt (i = 0 to 4)
Timer Bi interrupt (i = 0 to 2)
UARTi transmit interrupt (i = 0, 1)
UARTi receive interrupt (i = 0, 1)
Notes 1:
When multiple interrupts are enabled, the stop mode is terminated owing to the interrupt request which occurs first.
2: For interrupts, refer to “CHAPTER 7. INTERRUPTS” and each peripheral device’s chapter.
STOP AND WAIT MODES
7902 Group User’s Manual 16-9
16.3 Stop mode
Before executing the STP instruction, be sure to enable an interrupt which is to be used for the stop mode
termination.
Also, make sure that the interrupt priority level of an interrupt to be used for the termination is higher than
the processor interrupt priority level (IPL) of a routine where the STP instruction is executed.
After oscillation starts (), there is a possibility that each interrupt request occurs until the supply of φCPU,
φBIU starts (). The interrupt requests which occurred during this period are accepted in order of priority
after the watchdog timer’s MSB becomes “0.” (When the level sense of an INTi interrupt is used, however,
no interrupt request is retained. Therefore, if pin INTi is at the invalid level when the watchdog timer’s MSB
becomes “0,” no interrupt request is accepted.) For an interrupt which has no need to be accepted, be sure
to set its interrupt priority level to “0” (Interrupt disabled) before executing the STP instruction.
16.3.2 Terminate operation at interrupt request occurrence (when not using watchdog timer)
At the stop mode termination, an instruction is executed without use of the watchdog timer. (See Figure
16.3.1.)
When an interrupt request occurs, clock input from pin XIN starts. Simultaneously, supply of clocks fsys,
φ1, f1 to f4096, Wf32, Wf512 starts.
Supply of φCPU, φBIU starts after the time listed in Table 16.3.2 has elapsed.
The interrupt request which occurred in is accepted.
Watchdog timer clock source
select bit at STP termination
(bits 7, 6 at address 6116)
00
01
10
11
fXIN 19 cycles
fXIN 11 cycles
fXIN 67 cycles
fXIN 35 cycles
Time until supply of
φCPU and φBIU starts
Table 16.3.2 Time after stop mode is terminated
until supply of φCPU, φBIU starts
Before executing the STP instruction, be sure to set as follows:
Enable an interrupt which is to be used for the stop mode termination.
Also, make sure that the interrupt priority level of an interrupt to be used for the termination is higher
than the processor interrupt priority level (IPL) of a routine where the STP instruction is executed.
The external clock input select bit (bit 1 at address 6216) = “1” (Note)
The system clock select bit (bit 5 at address BC16) = “0” (Note)
Note: Simultaneously, the oscillation driver circuit between pins XIN and XOUT stops, and the output level
at pin XOUT is kept “H.” (Refer to section “17.4 Stop of oscillation circuit.”)
STOP AND WAIT MODES
7902 Group User’s Manual
16-10
16.3 Stop mode
Fig. 16.3.1 Stop mode terminate sequence owing to interrupt request occurrence
Interrupt
request to
be used for
termination
occurs.
Clock input from pin X
IN
starts.
Watchdog timer starts counting.
Stop mode
φ
BIU
fX
IN
φ
1
Operating Stopped Operating
Operating Stopped Operating
CPU
Internal peripheral devices
STP instru-
ction is
executed.
Value of watchdog timer
7FF
16
Interrupt request to be
used for stop mode
termination
(Interrupt request bit)
FFF
16
Each supply of φ
CPU
, φ
BIU
starts.
Interrupt request which was used
for termination is accepted.
When not using watchdog timer
(Note)
Stopped
Operating
Note: Time listed in Table 16.3.2.
Operating Stopped Stopped Operating
Operating Stopped Operating Operating
CPU
Internal peripheral devices
Interrupt request to be used for
termination occurs.
Oscillation starts.
(When an external clock is input
from pin X
IN
, clock input starts.)
PLL frequency multiplier starts its
operation.
Watchdog timer starts counting.
Value of watchdog timer
7FF
16
Interrupt request to be
used for stop mode
termination
(Interrupt request bit)
FFF
16
Watchdog timer’s MSB = “0”
(However, watchdog timer interrupt
request does not occur.)
Each supply of φ
CPU
, φ
BIU
starts.
Interrupt request which was used for
termination is accepted.
Stop mode
φ
BIU
fX
IN
φ
1
STP instru-
ction is
executed.
When using watchdog timer
f
PLL
fX
i
2048 counts
(Note)
Note: This applies when the PLL circuit operation enable bit (bit 1 at address BC
16
) = “1.”
fX
i
: fX
16
, fX
32
, fX
64
, fX
128
.
These are clocks selected by the watchdog timer clock source select bits at STP termination (bits 7, 6 at address 61
16
.)
STOP AND WAIT MODES
7902 Group User’s Manual 16-11
16.3 Stop mode
16.3.3 Terminate operation at hardware reset
Although each of the CPU and SFR area is initialized, the contents of the internal RAM immediately before
the STP instruction execution are retained. The terminate sequence is the same as the internal processing
sequence after reset.
For reset, refer to “CHAPTER 4. RESET.”
Also, the STP-instruction-execution status bit is used for the following verification:
• Which of the power-on reset and hardware reset has been used to reset the system?
• Has the hardware reset been used for the stop mode termination?
STOP AND WAIT MODES
7902 Group User’s Manual
16-12
16.4 Wait mode
16.4 Wait mode
When the WIT instruction is executed, both of φCPU and φBIU become inactive. (The oscillation does not
become inactive.) This state is called “wait mode.” (See Table 16.1.1.)
In the wait mode, the power consumption can be saved with Vcc (the power source voltage) retained. When
using no internal peripheral device in the wait mode, the power consumption can be saved furthermore since
each of fsys and internal peripheral device’s operation clock can be inactive. (Refer to section “17.3 Stop
of system clock in wait mode.”) Also, in the wait mode, the state of each I/O pin of the external buses
and bus control signals can be set arbitrarily. Therefore, the power consumption of the whole system can
be saved. (Refer to section “17.2 Bus fixation in stop and wait modes.”)
The wait mode is terminated owing to an interrupt request occurrence or hardware reset.
The wait mode terminate operation is described below.
16.4.1 Terminate operation at interrupt request occurrence
When an interrupt request occurs, each supply of φCPU and φBIU starts.
The interrupt request which occurred in is accepted.
Table 16.4.1 lists the interrupts which can be used for the wait mode termination.
Table 16.4.1 Interrupts which can be used for wait mode termination
INT3 interrupt: when the key input interrupt is invalid.
When the key input interrupt is selected.
In event counter mode
When an external clock is selected.
Do not use.
NMI interrupt
INTi interrupt (i = 0 to 4)
Key input interrupt
Timer Ai interrupt (i = 0 to 4)
Timer Bi interrupt (i = 0 to 2)
UARTi transmit interrupt (i = 0, 1)
UARTi receive interrupt (i = 0, 1)
A-D conversion interrupt
Notes 1: When multiple interrupts are enabled, the wait mode is terminated owing to the interrupt request which
occurs first.
2: For interrupts, refer to “CHAPTER 7. INTERRUPTS” and each peripheral device’s chapter.
Interrupt System clock in active
Usage conditions for interrupt request occurrences
System clock stopped
Before executing the WIT instruction, be sure to enable an interrupt which is to be used for the wait mode
termination.
Also, make sure that the interrupt priority level of an interrupt to be used for termination is higher than the
processor interrupt priority level (IPL) of a routine where the WIT instruction is executed.
Also, when multiple interrupts in Table 16.4.1 are enabled, the wait mode is terminated owing to the
interrupt request which occurs first.
16.4.2 Terminate operation at hardware reset
Although each of the CPU and SFR area is initialized, the contents of the internal RAM immediately before
the WIT instruction execution are retained. The terminate sequence is the same as the internal processing
sequence after reset.
For reset, refer to “CHAPTER 4. RESET.”
Also, the WIT-instruction-execution status bit is used for the following verification:
• Which of the power-on reset and hardware reset has been used to reset the system?
• Has the hardware reset been used for the wait mode termination?
CHAPTER 17CHAPTER 17
POWER SAVING
FUNCTION
17.1 Overview
17.2
Bus fixation in stop and wait modes
17.3
Stop of system clock in wait mode
17.4 Stop of oscillation circuit
17.5 Pin VREF disconnection
POWER SAVING FUNCTIONS
7902 Group User’s Manual
17-2
17.1 Overview
CHAPTER 16. STOP
AND WAIT MODES
CHAPTER 5. CLOCK
GENERATING CIRCUIT,
Section 16.3 Stop mode
CHAPTER 13. A-D CONVERTER
CHAPTER 14. D-A CONVERTER
This chapter explains the functions to save the power consumption of the microcomputer and the total
system including the microcomputer.
17.1 Overview
Table 17.1.1 lists the overview of the power saving functions. Each of these functions saves the power
consumption of the total system. The registers related to the power saving functions are explained in the
following.
Table 17.1.1 Overview of power saving functions
Item
Bus fixation in stop and
wait modes
Stop of system clock in
wait mode
Stop of oscillation circuit
Pin VREF disconnection
In the stop and wait modes, by switching I/O pins of the
external bus and bus control signals to programmable
I/O port pins, the states of the I/O pins can arbitrary be set.
In the wait mode, operating clocks for the internal peripheral
devices and fsys can be stopped.
When a stable clock externally generated is used, the drive circuit
for oscillation between pins X IN and XOUT can be stopped. (The
output level at pin XOUT is fixed to “H.”)
When terminating the stop mode, the watchdog timer is not used.
The VREF input can be disconnected when the A-D converter
and D-A converter are not used.
Function Reference
POWER SAVING FUNCTIONS
7902 Group User’s Manual 17-3
17.1 Overview
RW
(Note)
RW
(Note)
RW
0
0
0
Bit nameBit
0
1
7 to 2
Particular function select register 0 (Address 6216)
Function
At reset
R/W
STP instruction invalidity select bit
External clcok input select bit
Fix this bit to “0.”
b7 b6 b5 b4 b3 b2 b1 b0
0 : STP instruction is valid.
1 : STP instruction is invalid.
0 : Oscillation circuit is active. (Oscillator is connected.)
Watchdog timer is used at stop mode termination.
1 : Oscillation circuit is inactive. (External clock is
input.)
When the system clock select bit (bit 5 at address BC
16
) = “0,”
watchdog timer is not used at stop mode termination.
When the system clock select bit = “1,”
watchdog timer is used at stop mode termination.
000000
17.1.1 Particular function select register 0
Figure 17.1.1 shows the structure of the particular function select register 0, and Figure 17.1.2 shows the
writing procedure for the particular function select register 0.
Fig. 17.1.1 Structure of particular function select register 0
Note: Writing to these bits requires the following procedure:
• Write “5516” to this register. (The bit status does not change only by this writing.)
• Succeedingly, write “0” or “1” to each bit.
Also, use the MOVMB (MOVM when m = 1) instruction or STAB (STA when m = 1) instruction.
If an interrupt occurs between writing of “5516” and next writing of “0” or “1,” latter writing may be ignored. When there is a
possibility that an interrupt occurs at the above timing, be sure to read this bit’s contents after writing of “0” or “1,” and verify
whether “0” or “1” has correctly been written or not.
POWER SAVING FUNCTIONS
7902 Group User’s Manual
17-4
17.1 Overview
(1) External clock input select bit (bit 1)
Setting this bit to “1” stops the oscillation driver circuit between pins XIN and XOUT and keeps the output
level of pin XOUT being “H.” (Refer to section “17.4 Stop of oscillation circuit.” At the stop mode
termination owing to an interrupt occurrence, the watchdog timer is not used if the system clock select
bit (bit 5 at address BC16) = “0,” whereas the watchdog timer is used if the system clock select bit =
“1.”
To rewrite this bit, write “0” or “1” just after writing of “5516” to address 6216. (See Figure 17.1.2.)
Note that if an interrupt occurs between writing of “5516” and next writing of “0” or “1,” latter writing
may be ignored. When there is a possibility that an interrupt occurs at the above timing, be sure to
read this bit’s contents after writing of “0” or “1,” and verify whether “0” or “1” has correctly been
written or not.
In addition, even when the watchdog timer is disabled by the particular function select register 2
(address 6416), the watchdog timer can be active only at the stop mode termination if this bit = “0.”
(Refer to section “16.3 Stop mode.")
Fig. 17.1.2 Writing procedure for particular function select register 0
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
00
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
0
Writing of “5516b0
Particular function select register 0 (Address 6216)
b7
1
Setting completed
AAA
AAA
AAA
10
Writing to bits 0, 1 b0
Particular function select register 0 (Address 6216)
b7
External clock input select bit
0 : Oscillation circuit is active. (Oscillator is connected.)
Watchdog timer is used at stop mode termination.
1 : Oscillation circuit is inactive. (External clock is input.)
When the system clock select bit (bit 5 at address BC16) = “0,”
watchdog timer is not used at stop mode termination.
When the system clock select bit = “1,”
watchdog timer is used at stop mode termination.
STP instruction invalidity select bit
0 : STP instruction is valid.
1 : STP instruction is invalid.
Next
instruction
Note: Bits’ state does not change only
by writing of “5516.”
000000
11
00
POWER SAVING FUNCTIONS
7902 Group User’s Manual 17-5
0
1
2
3
4
5
6
7
17.1.2 Particular function select register 1
Figure 17.1.3 shows the structure of the particular function select register 1.
Fig. 17.1.3 Structure of particular function select register 1
(1) Standby state select bit (bit 2)
Setting this bit to “1” allows the I/O pins of the external bus and bus control signals to be switched
to the programmable I/O port pins in the stop and wait modes. (Refer to section “17.2 Bus fixation
in stop and wait modes.”)
(2) Internal clock stop select bit at WIT (bit 3)
Setting this bit to “1” stops operating clocks for the internal peripheral devices and fsys in the wait
mode. (Refer to section “17.3 Stop of system clock in wait mode.”)
RW
(Note 2)
RW
(Note 2)
RW
RW
RW
RW
Notes 1: At power-on reset, this bit becomes “0.” At hardware reset or software reset, this bit retains the value just before reset.
2: Even when “1” is written, the bit status will not change.
3: Setting this bit to “1” must be performed just before execution of the WIT instruction. Also, after the wait state is termi-
nated, this bit must be cleared to “0” immediately.
(Note 1)
(Note 1)
0
0
0
0
0
0
Particular function select register 1 (Address 6316)b7 b6 b5 b4 b3 b2 b1 b0
Bit nameBit Function At reset R/W
STP-instruction-execution
status bit
WIT-instruction-execution
status bit
Standby state select bit
System clock stop select bit
at WIT (Note 3)
Address output select bit
The value is “0” at reading.
Timer B2 clock source select bit
(Valid in event counter mode.)
The value is “0” at reading.
0 : Address output changes at access to the inter-
nal area and external area.
1 : Address output changes only at access to the
external area.
0 : Normal operation.
1 : STP instruction has been executed.
0 : Normal operation.
1 : WIT instruction has been executed.
0 : External signal input to the TB2 IN pin is counted.
1 : fX32 is counted.
0 : External bus
1 : Programmable I/O port
0 : In the wait mode, system clock fsys is active.
1 : In the wait mode, system clock fsys is stopped.
17.1 Overview
POWER SAVING FUNCTIONS
7902 Group User’s Manual
17-6
17.2 Bus fixation in stop and wait modes
Setting the standby state select bit (See Figure 17.1.3.)
to “1” allows the I/O pins of the external bus and bus
control signals to be switched to the programmable
I/O port pins in stop and wait modes.
By setting the pins’ state not to generate unnecessary
currents between the microcomputer and external
devices, the power consumption of the total system
can be saved. (This pin’s state can be realized by
setting the corresponding port register and port direction
register.)
Table 17.2.1 lists the correspondences between I/O
pins of the external bus, bus control signals and
programmable I/O port pins, and Figure 17.2.1 shows
a setting example of bus fixation.
Also, pins ALE,
φ
1, CS1 to CS3 must be switched to programmable I/O port pins by clearing the following
bits to “0”:
• ALE : ALE output select bit (bit 3 at address 5F16)
φ
1: Clock
φ
1 output select bit (bit 7 at address 5E16)
• CS1 to CS3: Each of CS1 to CS3 output select bits (each of bit 7s at addresses 8216, 8416 and 8616)
17.2 Bus fixation in stop and wait modes
Standby state select bit
A0 to A7,
A8 to A 15,
A16 to A 23,
D0 to D 7,
D8 to D 15,
RD , BLW,
BHW
CS0 (Note 2)
A0 to A7,
A8 to A15,
A16 to A23,
D0 to D 7,
D8 to D15
(Note 1)
RD , BLW,
BHW (Note 1)
CS0
P100 to P107,
P110 to P117,
P00 to P07
P10 to P17,
P20 to P27
P31, P32,
P33
P44
01
External bus and
Bus control signals
Notes 1: When the external data bus width = 8 bits
(BYTE = Vcc level), these pins are forcibly
switched to be programmable I/O port pins,
regardless of the standby state select bit.
2: Only in the microprocessor mode, this pin can
be switched to a programmable I/O port pin
by using the standby state select bit. In the
memory expansion mode, be sure to switch
this pin to a programmable I/O port pin by
clearing the CS0 output select bit (bit 7 at
address 8016).
Table 17.2.1 Correspondences between I/O pins
of external bus, bus control signals
and programmable I/O port pins
POWER SAVING FUNCTIONS
7902 Group User’s Manual 17-7
17.2 Bus fixation in stop and wait modes
Fig. 17.2.1 Setting example of bus fixation
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
b7 b0
1
b7 b0b0b0 b7 b7
b7 b0b0 b7
b7 b0
RD
BLW
BHW
b7 b0
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
AAAAAAAAAAAA
b7 b0b0b0 b7 b7
b7 b0b0b7
b7 b0
RD
BLW
BHW
b7 b0
AAAA
AAAA
AAAA
Set the standby state select bit to “1.”
Particular function select register 1
(Address 63
16
)
Standby state select bit
1 : Programmable I/O port
Setting the I/O pins’ state of external bus and bus control signals.
Port P11 direction
register
(Address 19
16
)
Port P0 direction
register
(Address 4
16
)
Port P10 direction
register
(Address 18
16
)
A
23
to A
0
0: Input mode (Note 1)
1: Output mode
Port P2 direction
register
(Address 8
16
)
Port P1 direction
register
(Address 5
16
)
D
15
to D
0
0: Input mode (Note 1)
1: Output mode
Port P3 direction register
(Address 9
16
)
0: Input mode (Note 1)
1: Output mode
Port P4 direction register
(Address C
16
)
CS
0
(Note 2)
0: Input mode (Note 1)
1: Output mode
Setting the I/O pins’ output level of external bus and bus control
signals.
Port P0
register
(Address 2
16
)
Port P11
register
(Address 17
16
)
Port P10
register
(Address 16
16
)
A
23
to A
0
0: “L” level output
1: “H” level output
Port P2
register
(Address 6
16
)
Port P1
register
(Address 3
16
)
D
15
to D
0
0: “L” level output
1: “H” level output
Port P3 register (Address 7
16
)
0: “L” level output
1: “H” level output
Port P4 register (Address A
16
)
CS
0
(Note 2)
0: “L” level output
1: “H” level output
STP or WIT instruction executed.
Notes 1: Each of pins which have been set for the input mode must be connected to Vcc or Vss via a resistor; otherwise they are placed in the
floting state.
2: This pin can be switched to a programmable I/O port pin by the standby state select bit only in the microprocessor mode. In the memo-
ry expansion mode, be sure to switch this pin to a programmable I/O port pin by clearing the CS
0
output select bit (bit 7 at address
80
16
).
POWER SAVING FUNCTIONS
7902 Group User’s Manual
17-8
Operation after termination
17.3 Stop of system clock in wait mode
17.3 Stop of system clock in wait mode
In the wait mode, if there is not need to operate the internal peripheral devices, setting the system clock
stop select bit at WIT (See Figure 17.1.3.) to “1” stops the operating clocks for the internal peripheral
devices and fsys. This saves the power consumption of the microcomputer.
Table 17.3.1 lists the states and operations in the wait mode and after this mode is terminated.
Table 17.3.1 States and operations in wait mode and after this mode is terminated
Active.
Operates (Note 1).
Inactive.
Active.
Inactive.
Operates.
Operates.
Operates.
Operates.
Stopped.
Retains the state at the WIT instruction execution (Note 2).
Floating (Note 2).
Outputs “H” level (Note 2).
Outputs “L” level (Note 2).
Outputs clock φ1 (Note 2).
Retains the state at the WIT instruction execution.
System clock is inactive. (bit 3 at address 6316 = 1)
Inactive.
Can operate only in the event counter mode.
Can operate only when an external clock is selected.
Stopped.
Stopped.
Item
Termination due to
interrupt request
occurrence
Timers A, B
Serial I/O
A-D converter
D- A converter
Watchdog timer
A0 to A23
D0 to D15
States
Oscillation
PLL frequency multiplier
φCPU, φBIU
fsys, Clock φ1,
f1 to f4096
Wf32, Wf 512
System clock is active. (bit 3 at address 63
16
= 0)
Notes 1: This applies when the PLL circuit operation enable bit (bit 1 at address BC16) = “1.”
2: The I/O pins of the external buses and bus control signals can be switched to programmable I/O port
pins by software. (Refer to section “17.2 Bus fixation in stop and wait modes.”)
Internal peripheral devices
_____ ________
RD, BLW,
________ __________
BHW, HLDA,
______ ______
CS0 to CS3
ALE
φ1
The others
Termination due to
hardware reset
Supply of φCPU, φBIU starts immediately after termination.
Operation after hardware reset
Outputs “L” level (Note 2).
Pins
POWER SAVING FUNCTIONS
7902 Group User’s Manual 17-9
17.4 Stop of oscillation circuit, 17.5 Pin VREF disconnection
17.4 Stop of oscillation circuit
When a stable clock externally generated is input to pin XIN, power consumption can be saved by setting
the external clock input select bit to “1” to stop the drive circuit for oscillation between pins X IN and XOUT.
(See Figure 17.1.1.) At this time, the output level at pin XOUT is fixed to “H.” Also, if the system clock select
bit (bit 5 at address BC16) = “0,” the watchdog timer is not used when the stop mode is terminated owing
to an interrupt request occurrence; therefore, the microcomputer can start instruction execution just after
termination of the stop mode. When the system clock select bit = “1,” in this case, the watchdog timer is
used.
17.5 Pin VREF disconnection
When the A-D converter and D-A converter are not used, power consumption can be saved by setting the
VREF connection select bit to “1.” It is because the reference voltage input pin (VREF) is disconnected from
the ladder resistors of the A-D converter and D-A converter (See Figure 17.5.1.), and there is no current
flow between them.
When the VREF connection select bit has been cleared from “1” (VREF disconnected) to “0” (VREF connected),
be sure to start the A-D conversion or D-A conversion after an interval of 1 µs or more has elapsed.
Fig. 17.5.1 Structure of A-D control register 1
Notes 1: These bits are invalid in the one-shot and repeat modes. (They may be either “0” or “1.”)
2: When using pin AN4, be sure that the pin INT3 select bit (bit 5 at address 9416) = “0.”
3: When using pin AN5, be sure that the pin INT4 select bit (bit 6 at address 9416) = “0.”
4: When using pin AN6, be sure that the D-A0 output enable bit (bit 0 at address 9616) = “0” (output disabled).
5: When using pin AN7, be sure that the pin INT2 select bit (bit 4 at address 9416) = “0” and the D-A1 output enable bit (bit 1
at address 9616) = “0.” When an external trigger is selected, pin AN7 cannot be used as an analog input pin.
6: When this bit is cleared from “1” to “0,” be sure to start the A-D conversion or D-A conversion after an interval of 1 µs or
more has elapsed.
7: Writing to each bit of the A-D control register 1 must be performed while the A-D conversion halts.
1
1
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
A-D control register 1 (Address 1F16)
A-D sweep pin select bits
(Valid in the single sweep and repeat
sweep modes.) (Note 1)
Fix this bit to “0.”
Resolution select bit
A-D conversion frequency (
φ
AD) select
bit 1
External trigger polarity select bit
(Valid when external trigger selected.)
VREF connection select bit (Note 6)
The value is “0” at reading.
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : Pins AN0 and AN1 (2 pins)
0 1 : Pins AN0 to AN3 (4 pins)
1 0 : Pins AN0 to AN5 (6 pins) (Notes 2, 3)
1 1 : Pins AN0 to AN7 (8 pins) (Notes 2 to 5)
b1 b0
0 : 8-bit resolution mode
1 : 10-bit resolution mode
See Table 13.2.1.
0
0 : Falling edge of the pin ADTRG’s input signal
1 : Rising edge of the pin ADTRG’s input signal
0 : Pin VREF is connected.
1 : Pin VREF is disconnected.
Bit nameBit Function At reset R/W
0
1
2
3
4
5
6
7
POWER SAVING FUNCTIONS
7902 Group User’s Manual
17-10
17.5 Pin VREF disconnection
MEMORANDUM
CHAPTER 18CHAPTER 18
DEBUG FUNCTION
18.1 Overview
18.2 Block description
18.3 Address matching detection mode
18.4 Out-of-address-area detection mode
[Precautions for debug function]
DEBUG FUNCTION
7902 Group User’s Manual
18-2
18.1 Overview, 18.2 Block description
18.1 Overview
When the CPU fetches an op code (op-code fetch), the debug function generates an address matching
detection interrupt request if a selected condition is satisfied as a result of comparison between the address
where the op code to be fetched is stored (in other words, the contents of PG and PC) and the specified
address.
The debug function provides the following 2 modes:
(1) Address matching detection mode
When the contents of PG and PC match with the specified address, an address matching detection
interrupt request occurs. This mode can be used for avoiding or modifying a portion of a program.
(2) Out-of-address-area detection mode
When the contents of PG and PC go out of the specified area, an address matching detection interrupt
request occurs. This mode can be used for the program runaway detection by specifying the area
where a program exists.
Note that an address matching detection interrupt is a non-maskable software interrupt. For details of this
interrupt, refer to “CHAPTER 7. INTERRUPTS.”
In addition, the debug function cannot be evaluated by a debugger. Therefore, do not use a debugger when
using the debug function.
18.2 Block description
Figure 18.2.1 shows the block diagram of the debug function, and the registers relevant to this function are
described in the following.
Fig. 18.2.1 Block diagram of debug function
Address compare register 0 Address compare register 1
Debug control register 0
Matching • Compare register Matching • Compare register
Address matching
detect circuit
Debug control register 1
Internal data bus (DB0 to DB15)
CPU bus (Address)
Address matching
detection interrupt
DEBUG FUNCTION
7902 Group User’s Manual 18-3
18.2 Block description
18.2.1 Debug control register 0
Figure 18.2.2 shows the structure of the debug control register 0.
Note: At power-on reset, these bits become “0”; at hardware reset or software reset, these bits retain the value immediately before reset.
0
1
2
3
4
5
6
7
Bit nameBit
Debug control register 0 (Address 6616)
Function
Detect condition select bits
Fix these bits to “0.”
Detect enable bit
Fix this bit to “0.”
The value is “1” at reading.
RW
RW
RW
RW
RW
RW
RW
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 : Do not select.
0 0 1 : Address matching detection 0
0 1 0 : Address matching detection 1
0 1 1 : Address matching detection 2
1 0 0 : Do not select.
1 0 1 : Out-of-address-area detection
1 1 0 :
1 1 1 :
b2 b1b0
0 : Detection disabled.
1 : Detection enabled.
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
1
Do not select.
000
At reset R/W
(1) Detect condition select bits (bits 0 to 2)
These bits are used to select an occurrence condition for an address matching detection interrupt
request. This condition can be selected from the following:
Address matching detection 0
An address matching detection interrupt request occurs when the contents of PG and PC match
with the address being set in the address compare register 0 (addresses 6816 to 6A16); (Refer to
section “18.3 Address matching detection mode.”)
Address matching detection 1
An address matching detection interrupt request occurs when the contents of PG and PC match
with the address being set in the address compare register 1 (addresses 6B16 to 6D16); (Refer to
section “18.3 Address matching detection mode.”)
Address matching detection 2
An address matching detection interrupt request occurs when the contents of PG and PC match
with the address being set in the address compare register 0 (addresses 6816 to 6A16) or address
compare register 1 (addresses 6B16 to 6D16); (Refer to section “18.3 Address matching detection
mode.”)
Out-of-address-area detection
An address matching detection interrupt request occurs when the contents of PG and PC are less
than the address being set in the address compare register 0 (addresses 6816 to 6A16) or larger
than the address compare register 1 (addresses 6B16 to 6D16); (Refer to section “18.4 Out-of-
address-area detection mode.”)
(2) Detect enable bit (bit 5)
If any selected condition is satisfied when this bit = “1,” an address matching detection interrupt
request occurs.
Fig. 18.2.2 Structure of debug control register 0
DEBUG FUNCTION
7902 Group User’s Manual
18-4
18.2.2 Debug control register 1
Figure 18.2.3 shows the structure of the debug control register 1.
Fig. 18.2.3 Structure of debug control register 1
(1) Address compare register access enable bit (bit 2)
Setting this bit to “1” enables reading from or writing to the contents of address compare registers 0
and 1 (addresses 6816 to 6D16), while clearing this bit to “0” disables this reading or writing.
Be sure to set this bit to “1” immediately before reading from or writing to the address compare
registers 0 and 1, and then clear it to “0” immediately after this reading or writing.
(2) Address-matching-detection 2 decision bit (bit 6)
When the address matching detection 2 is selected, this bit is used to decide which of the addresses
being set in the address compare registers 0 and 1 matches with the contents of PG and PC.
This bit is cleared to “0” when the contents of PG and PC matches with the address being set in
address compare register 0 and set to “1” when the contents of PG and PC match with the one being
set in the address compare register 1.
This bit is invalid when the address matching detection 0 and 1 are selected.
(Note 1)
(Note 1)
0
0
(Note 1)
0
0
0
0
1
2
3
4
5
6
7
RW
RO
RW
RW
RW
RO
RO
Bit nameBit
Debug control register 1 (Address 6716)
Function
At reset
R/W
Fix this bit to “0.”
The value is “0” at reading.
Address compare register
access enable bit (Note 2)
Fix this bit to “1” when using the debug function.
Fix this bit to “0.”
While a debugger is not used, the value is “0” at reading.
While a debugger is used, the value is “1” at reading.
Address-matching-detection 2
decision bit
(Valid when the address match-
ing detection 2 is selected.)
The value is “0” at reading.
00
0 : Disabled.
1 : Enabled.
0 : Matches with the contents of the address com-
pare register 0.
1 : Matches with the contents of the address com-
pare register 1.
1
Notes 1: At power-on reset, these bits become “0”; at hardware reset or software reset, these bits retain the value immediately before reset.
2: Be sure to set this bit to “1” immediately before the access to the address compare registers 0 and 1 (addresses 6816 to
6D16). Then, be sure to clear this bit to “0” immediately after this access.
b7 b6 b5 b4 b3 b2 b1 b0
18.2 Block description
DEBUG FUNCTION
7902 Group User’s Manual 18-5
18.2 Block description
18.2.3 Address compare registers 0 and 1
Each of the address compare registers 0 and 1 consists of 24 bits, and the address to be detected is set
here.
Figure 18.2.4 shows the structures of the address compare registers 0 and 1.
At op-code fetch, the contents of PG and PC are compared with the addresses being set in the address
compare register 0 or 1. Therefore, be sure to set the start address of an instruction into the address
compare register 0 or 1. If such an address as in the middle of instructions or in the data table is set into
the address compare register 0 or 1, no address matching detection interrupt request occurs because this
address does not match with the contents of PG and PC.
Note that, before the instruction at the address being set in the address compare register 0 or 1 is
executed, an address matching detection interrupt request occurs and is accepted.
Fig. 18.2.4 Structures of address compare registers 0 and 1
Address compare register 0 (Addresses 6A16 to 6816)
Address compare register 1 (Addresses 6D16 to 6B16)
Undefined
23 to 0
Bit Function
At reset
R/W
The address to be detected (in other words, the start address of instructions) is set here. RW
b0
b7 b7b0b7
(b23) (b8)(b15)(b16)
b0
Note: When accessing to these registers, be sure to set the address compare register access enable bit (bit 2 at address 67 16) to “1”
immediately before the access. Then, be sure to clear this bit to “0” immediately after this access.
DEBUG FUNCTION
7902 Group User’s Manual
18-6
18.3 Address matching detection mode
18.3 Address matching detection mode
When the contents of PG and PC match with the specified address, an address matching detection interrupt
request occurs.
18.3.1 Setting procedure for address matching detection mode
Figure 18.3.1 shows an initial setting example for registers relevant to the address matching detection
mode.
Fig. 18.3.1 Initial setting example for registers relevant to address matching detection mode
Selection of detect condition
b7 b0
Debug control register 0 (Address 66
16
)
000
0 0 1 : Address matching detection 0
0 1 0 : Address matching detection 1
0 1 1 : Address matching detection 2
b1 b0
b2
Detect enable bit
0 : Detection disabled.
Detect condition select bits
Detection starts.
AAA
AAA
0
Processing for setting of address compare registers
b7 b0
Debug control register 1 (Address 67
16
)
11
Address compare register access enable bit
(Note 1)
1 : Enabled.
b23 b0
Address compare register 0
(Addresses 6A
16
to 68
16
)
Address compare register 1
(Addresses 6D
16
to 6B
16
)
The address to be detected is set here.
Setting of address compare registers
b7 b0
Debug control register 1 (Address 67
16
)
0
Address compare register access enable bit
(Note 1)
0 : Disabled.
Set the detect enable bit to “1.”
b7 b0
Debug control register 0 (Address 66
16
)
Detect enable bit
1 : Detection enabled.
1
00
Disables interrupts.
The interrupt disable flag (I) is set to “1.”
Clear the interrupt disable flag (I) to “0” (Note 2).
Notes 1: Be sure to set this bit to “1” immediately before reading from or
writing to the address compare registers 0, 1. Then, be sure to
clear this bit to “0” immediately after this reading or writing.
2: This processing is unnecessary when no maskable interrupt is
used.
DEBUG FUNCTION
7902 Group User’s Manual 18-7
18.3 Address matching detection mode
18.3.2 Operations in address matching detection mode
Setting the detect enable bit to “1” initiate to compare the contents of PG and PC with one of the con-
tents of the following registers. This comparison is performed at each op-code fetch:
• When the address matching detection 0 is selected, the contents of the address compare register 0
are used for the above comparison.
• When the address matching detection 1 is selected, the contents of the address compare register 1
are used for the above comparison.
• When the address matching detection 2 is selected, the contents of the address compare register 0
or 1 are used for the above comparison.
When the address which matches with the above register’s contents is detected, an address matching
detection interrupt request occurs, and then, this request will be accepted.
Perform the necessary processing with an address matching detection interrupt routine.
The contents of PG, PC, and PS at acceptance of the address matching detection interrupt request are
saved onto the stack area. Therefore, be sure to rewrite the above contents of PG and PC to a certain
return address, and return to the address by using the RTI instruction.
When an address matching detection interrupt request has been accepted, the interrupt disable flag (I) is
set to “1”; the processor interrupt priority level (IPL) does not change.
Figures 18.3.2 and 18.3.3 show the examples of the ROM correct processing using the address matching
detection mode.
DEBUG FUNCTION
7902 Group User’s Manual
18-8
18.3 Address matching detection mode
Fig. 18.3.2 Example of ROM correct processing using address matching detection mode (1)
Address matching
detection interrupt routine
Address matching detection 0 or 1 selected
Main routine
Defective
or
Former program
TOP_BUG
TOP_RTN
Modified
or
Updated program
The contents of PG and PC
saved onto the stack area
(address TOP_BUG) are
rewritten to address
TOP_RTN (Note 2).
RTI
TOP_BUG: The start address of defective or former program.
This address is to be set in the address compare register 0 or 1, in advance.
TOP_RTN : The address next to the defective or former program.
Notes 1: When an address matching detection interrupt request has been accepted, the interrupt
disable flag (I) is set to “1.” If another interrupt requests is required to be accepted under
the same conditions as those of the defective or former program, be sure to clear the
interrupt disable flag (I) to “0” at the start of an address matching detection interrupt
routine.
2: Each status of PG, PC, and PS immediately before acceptance of an address matching
detection interrupt request is saved onto the stack area. (The contents of PG, PC, and
PS are saved onto the stack area in this order.) Refer to section “7.7 Sequence from
acceptance of interrupt request until execution of interrupt routine.”
3: Make sure that this instruction is executed in the absolute long addressing mode. The
above is just an example. In an actual programming, be sure to refer to the format of the
assembler description to be used.
The interrupt disable flag (I)
is cleared to “0” (Note 1)
STAB A, LG : 0h (Note 3)
DEBUG FUNCTION
7902 Group User’s Manual 18-9
18.3 Address matching detection mode
Fig. 18.3.3 Example of ROM correct processing using address matching detection mode (2)
Address matching
detection interrupt routine
Address matching detection 2 selected
Main routine
Defective
or
Former program
TOP_BUG1
TOP_RTN1
Modified
or
Updated program
The contents of PG and PC
saved onto the stack area
(address TOP_BUG1) are
rewritten to address
TOP_RTN1 (Note 2).
RTI
TOP_BUG1 : The start address of defective or former program .
This address is to be set in the address compare register 0, in advance.
TOP_RTN1 : The address next to the defective or former program .
TOP_BUG2 : The start address of defective or former program .
This address is to be set in the address compare register 1, in advance.
TOP_RTN2 : The address next to the defective or former program .
Notes 1: When an address matching detection interrupt request has been accepted, the interrupt
disable flag (I) is set to “1.” If another interrupt requests is required to be accepted under
the same conditions as those of the defective or former program, be sure to clear the
interrupt disable flag (I) to “0” at the start of an address matching detection interrupt
routine.
2: Each status of PG, PC, and PS immediately before acceptance of an address matching
detection interrupt request is saved onto the stack area. (The contents of PG, PC, and
PS are saved onto the stack area in this order.) Refer to section “7.7 Sequence from
acceptance of interrupt request until execution of interrupt routine.”
3: Make sure that this instruction is executed in the absolute long addressing mode. The
above is just an example. In an actual programming, be sure to refer to the format of the
assembler description to be used.
Defective
or
Former program
TOP_BUG2
TOP_RTN2
Address-matching-
detection 2 decision bit?
Modified
or
Updated program
The contents of PG and PC
saved onto the stack area
(address TOP_BUG2) are
rewritten to address
TOP_RTN2 (Note 2).
1
0
The interrupt disable flag (I)
is cleared to “0” (Note 1)
STAB A, LG : 0h (Note 3)
DEBUG FUNCTION
7902 Group User’s Manual
18-10
18.4 Out-of-address-area detection mode
18.4 Out-of-address-area detection mode
When the contents of PG and PC go out of the range of the specified area, an address matching detection
interrupt request occurs.
18.4.1 Setting procedure for out-of-address-area detection mode
Figure 18.4.1 shows an initial setting example for registers relevant to the out-of-address-area detection
mode.
Fig. 18.4.1 Initial setting example for registers relevant to out-of-address-area detection mode
Notes 1: Be sure to set this bit to “1” immediately before reading from or
writing to the address compare registers 0, 1. Then, be sure to
clear this bit to “0” immediately after this reading or writing.
2: This processing is unnecessary when no maskable interrupt is
used.
Selection of detect condition
b7 b0
Debug control register 0 (Address 66
16
)
000
Detect enable bit
0 : Detection disabled.
Selection of out-of-address-area detection
Detection starts.
AAA
AAA
0
Processing for setting of address compare registers
b7 b0
Debug control register 1 (Address 67
16
)
11
Address compare register access enable bit
(Note 1)
1 : Enabled.
b23 b0
Address compare register 0
(Addresses 6A
16
to 68
16
)
The start address of the programming
area is set here.
Setting of address compare registers
b7 b0
Debug control register 1 (Address 67
16
)
0
Address compare register access enable bit
(Note 1)
0 : Disabled.
Set the detect enable bit to “1.”
b7 b0
Debug control register 0 (Address 66
16
)
Detect enable bit
1 : Detection enabled.
1
00
Disables interrupts.
The interrupt disable flag (I) is set to “1.”
Clear the interrupt disable flag (I) to “0” (Note 2).
011
b23 b0
Address compare register 1
(Addresses 6D
16
to 6B
16
)
The last address of the programming
area is set here.
DEBUG FUNCTION
7902 Group User’s Manual 18-11
18.4 Out-of-address-area detection mode
18.4.2 Operations in out-of-address-area detection mode
Setting the detect enable bit to “1” initiate to compare the contents of PG and PC with the contents of
the address compare registers 0 and 1.
When an address less than the contents of the address compare registers 0 or larger than the one of
the address compare register 1 is detected, an address matching detection interrupt request occurs, and
then, this request will be accepted.
Perform the necessary processing with an address matching detection interrupt routine.
The contents of PG, PC, and PS at acceptance of the address matching detection interrupt request are
saved onto the stack area. Therefore, be sure to rewrite the above contents of PG and PC to a certain
return address, and return there by using the RTI instruction.
When an address matching detection interrupt request has been accepted, the interrupt disable flag (I) is
set to “1”; the processor interrupt priority level (IPL) does not change.
By setting the start address of the programming area into the address compare register 0 and the last
address of the programming area into the address compare register 1, a program runaway (in other words,
fetching op codes from the area out of the programming area) can be detected. If any program runaway
is detected and reset of the microcomputer is required, be sure to write “1” into the software reset bit (bit
6 at address 5E16) within an address matching detection interrupt routine.
Figure 18.4.2 shows an example of program runaway detection using the out-of-address-area detection
mode.
Fig. 18.4.2 Example of program runaway detection using out-of-address-area detection mode
AAAA
A
AA
A
A
AA
A
AAAA
TOP_PRG : Start address of programming area This address is to be set into the address compare register 0,
in advance.
END_PRG : Last address of programming area This address is to be set into the address compare register 1,
in advance.
Note: A program runaway may affect the contents of the data bank register (DT), the direct page registers (DPRi) etc.
Therefore, the contents of these registers must be rewritten in order to write “1” to the software reset bit with an
addressing mode using DT, DPRi, etc.
Address matching detection
interrupt routine
RTI
Software reset bit 1
(bit 6 at address 5E
16
)The microcomputer
is reset.
000000
16
TOP_PRG
END_PRG
FFFFFF
16
Access to the area
out of the progra-
mming area
Access to the
area out of the
programming
area
Programming area
DEBUG FUNCTION
7902 Group User’s Manual
18-12
[Precautions for debug function]
[Precautions for debug function]
1. The debug function cannot be evaluated by a debugger. Therefore, do not use a debugger when using the debug
function.
2. When returning from an address matching detection interrupt routine, be sure to rewrite the saved contents of PG
and PC to a certain return address, and then return there by using the RTI instruction. However , this is unnecessary
processing when the software reset is performed within an address matching detection interrupt routine for
program runaway detection, etc.
3. Be sure to set the start address of an instruction into the address compare register 0 or 1.
CHAPTER 19CHAPTER 19
APPLICATIONS
19.1 Connection examples with external
devices
19.2 Examples of handling control pins
in flash memory serial I/O mode
APPLICATIONS
7902 Group User’s Manual
19-2
19.1 Connection examples with external devices
Some application examples are described below.
Each application described here is just an example. Therefore, before actual using it, be sure to properly
modify it according to the user’s system and sufficiently evaluate it.
19.1 Connection examples with external devices
Connection examples with the ready function used and those with memories and I/O devices are described
below. For the functions and operations of pins used in these connection examples, refer to “CHAPTER 3.
CONNECTION WITH EXTERNAL DEVICES.” Also for timing requirements, refer to sections “Appendix 9.
M37902FGCGP electrical characteristics” and “Appendix 10. M37902FGMHP electrical characteristics.”
APPLICATIONS
7902 Group User’s Manual 19-3
19.1 Connection examples with external devices
19.1.1 Examples with ready function used
(1) Example with ready function used when bus cycle = 1φ + 3φ
Figures 19.1.1 and 19.1.2 show examples with the ready function used when bus cycle = 1φ + 3φ.
Fig. 19.1.1 Example with ready function used when bus cycle = 1φ + 3φ (1)
RD
BLW
BHW
1
φ
1
M37902
φ
1
CS
i
RDY
1D 1Q
PR 2D 2Q
PR 3D
3Q
PR
24
3
Circuit conditions: f(f
sys
) = 26MHz, bus cycle = 1φ + 3φ
D-TYPE FLIP FLOP
1CK 2CK 3CK
φ
1
CS
i
RD
BLW
BHW
1Q
2Q
3Q
RDY
Bus cycle = 1φ + 3φReady
tc = 1/f(f
sys
)
AB
t
su(RDY-φ1)
< tc = 38 ns
t
su(RDY-φ1)
Sum of propagation delay
time of 2, 3, and 4
<Operations>
• A ready request is accepted at pin RDY’s input-level detection timing A .
• A ready-state-termination request is accepted at pin RDY’s input-level detection timing C .
When f(f
sys
) = 26 MHz, the ready-state-termination request is accepted at the next detection timing C because t
su(RDY-φ1)
(the setup time for ready state termination) for detection timing B is insufficient.
<Device conditions: f(f
sys
) = 26 MHz>
When the ready function is required to be used as shown above, be sure to satisfy all of the following conditions:
• (Propagation delay time of 1 (Max.) – Propagation delay time of 2 (Min.) + Setup time of 3) 19 ns (Note)
• (Propagation delay time of 1 (Min.) – Propagation delay time of 2 (Max.) + Setup time of 3) > 1 ns
• Sum of propagation delay time of 2, 3, and 4 (Max.) 36 ns
Note: If the above conditions are not satisfied, the rising edge of signal RDY shown above is delayed by 1 cycle of φ
1
.
Therefore, each of the rising edges of signals CS
i
, RD, BLW, BHW is delayed by 1 cycle of φ
1
.
C
t
d(φ1-RDH)
= –18 to 0 ns
t
su(RDY-φ1)
Insufficient
t
d(φ1-RDL)
= –18 to 0 ns
APPLICATIONS
7902 Group User’s Manual
19-4
19.1 Connection examples with external devices
Fig. 19.1.2 Example with ready function used when bus cycle = 1φ + 3φ (2)
<Device conditions>
When the ready function is required to be used as shown above, be sure to satisfy all of the following conditions with
adjusting f(fsys):
• (Propagation delay time of 1 (Max.) – Propagation delay time of 2 (Min.) + Setup time of 3) ns
• (Propagation delay time of 1 (Min.) – Propagation delay time of 2 (Max.) + Setup time of 3) > –18 ns
• Sum of propagation delay time of 2, 3, and 4 (Max.) –40 ns
1
2 f(fsys)
1
f(fsys)
1
2 f(fsys)
1
M37902
1D 1Q
PR 2D 2Q
PR 3D
3Q
PR
24
3
Circuit condition: Bus cycle = 1φ + 3φ
D-TYPE FLIP FLOP
1CK 2CK 3CK
<Operations>
• A ready request is accepted at pin RDY’s input-level detection timing A .
• A ready-state-termination request is accepted at pin RDY’s input-level detection timing B .
φ1
φ1
CSi
RD
BLW
BHW
1Q
2Q
3Q
RDY
Bus cycle = 1φ + 3φReady
tc = 1/f(fsys)
AB
tsu(RDY-φ1)
tsu(RDY-φ1)
Sum of propagation delay
time of 2, 3, and 4
td(φ1-RDL) = –18 to 0 ns td(φ1-RDH) = –18 to 0 ns
RD
BLW
BHW
φ1
CSi
RDY
APPLICATIONS
7902 Group User’s Manual 19-5
19.1 Connection examples with external devices
(2) Example with ready function used when bus cycle = 2φ + 2φ
Figures 19.1.3 shows an example with the ready function used when bus cycle = 2φ + 2φ.
Fig. 19.1.3 Example with ready function used when bus cycle = 2φ + 2φ
D-TYPE FLIP FLOP
<Device conditions>
When the ready function is required to be used as shown above, be sure to satisfy all of the following conditions with
adjusting f(f
sys
):
• (Propagation delay time of 1 (Max.) – Propagation delay time of 2 (Min.) + Setup time of 3) ns
• (Propagation delay time of 1 (Min.) – Propagation delay time of 2 (Max.) + Setup time of 3) > –18 ns
• Sum of propagation delay time of 2, 3, and 4 (Max.) –40 ns
• Sum of propagation delay time of 1 and 4 (Max.) –40 ns
2
1D 1Q
PR 2D
2Q
PR
1CK 2CK
φ
1
φ
1
CS
i
RD
BLW
BHW
1Q
2Q
RDY
Bus cycle = 2φ + 2φReady
AB
t
su(RDY-φ1)
t
su(RDY-φ1)
M37902
4
Circuit condition: Bus cycle = 2φ + 2φ
tc = 1/f(f
sys
)
<Operations>
• A ready request is accepted at pin RDY’s input-level detection timing A .
• A ready-state-termination request is accepted at pin RDY’s input-level detection timing B .
1
2 f(f
sys
)
1
f(f
sys
)
Sum of propagation delay
time of 2, 3, and 4
1
1
2 f(f
sys
)
3
2 f(f
sys
)
t
d(φ1-RDH)
= –18 to 0 ns
t
d(φ1-RDL)
= –18 to 0 ns
3
RD
BLW
BHW
φ
1
CS
i
RDY
APPLICATIONS
7902 Group User’s Manual
19-6
19.1 Connection examples with external devices
19.1.2 Connection examples with memories
Figures 19.1.4 and 19.1.5 show connection examples with memories, and Tables 19.1.1 to 19.1.5 list the
timing requirements of memories. For timing requirements not listed in these tables, be sure to refer to the
latest datasheet of each memory, also.
Fig. 19.1.4 Connection example with memories (1)
D
0
to D
15
A
1
to
D
0
to D
15
A
1
to
M37902
MD0
MD1
BYTE
CS
0
RD
BLW
BHW
A
1
to A
23
D
0
to D
15
CS
1
Flash memory ( 16)
CE
OE
W
BC
1
BC
2
A
0
to
DQ
1
to DQ
16
SRAM ( 16)
CE
OE
WE
A
0
to
D
0
to D
15
Circuit condition: f(f
sys
) = 26 MHz
1, 2 : See Table 19.1.3.
1
2
APPLICATIONS
7902 Group User’s Manual 19-7
19.1 Connection examples with external devices
Fig. 19.1.5 Connection example with memories (2)
D
0
to D
15
A
1
to
D
8
to D
15
A
1
to
D
0
to D
7
A
1
to
M37902
MD0
MD1
BYTE
CS
0
RD
BLW
BHW
A
0
to A
23
D
0
/LA
0
to D
7
/LA
7
D
8
to D
15
MASK ROM ( 16)
CE
OE
W
A
0
to
DQ
1
to DQ
8
SRAM ( 8)
CE
OE
W
A
0
to
DQ
1
to DQ
8
SRAM ( 8)
CE
OE
Circuit condition: f(f
sys
) = 26 MHz
For access to area CS
2
, the 8-bit external data bus and multiplexed
bus are selected.
D
0
/LA
0
to D
7
/LA
7
A
8
to
CE
OE
WE
A
8
to
DA
0
to DA
7
AS
MRDY
CD-ROM decorder
(Multiplexed-bus-type device)
CS
1
CS
2
ALE
RDY
A
0
to
D
0
to D
15
APPLICATIONS
7902 Group User’s Manual
19-8
19.1 Connection examples with external devices
69 ns or less
46 ns or less
60 ns or less
6 ns or more
0 ns or more
Table 19.1.1 Timing requirements of flash memory (f(fsys) = 26 MHz)
Address access time
OE access time
CE access time
Output disable time
Data setup time
Data hold time
CE setup time before write
Reading
Writing
Bus cycle = 2 φ + 2φ
107 ns or less
46 ns or less
98 ns or less
0ns or more
56 ns or less
9 ns or less
38 ns or less
145 ns or less
84 ns or less
136 ns or less
0ns or more
94 ns or less
9 ns or less
38 ns or less
Address access time
OE access time
CE access time
Output disable time
Reading 107 ns or less
84 ns or less
98 ns or less
0 ns or more
183 ns or less
122 ns or less
174 ns or less
0 ns or more
Conditions
Item
Address access time
OE access time
CE access time
BC1/BC2 access time
Output enable time after OE enabled
Output disable time
Data setup time
Data hold time
Reading
Writing
(46 ns propagation delay time of 2) or less
(56 ns + propagation delay time of 1) or less
Bus cycle = 2φ + 3φ
Bus cycle = 1φ + 1φConditions
Item Bus cycle = 1 φ + 2φ
Bus cycle = 1φ + 3φConditions
Item Bus cycle = 2 φ + 4φ
(Note 1)
(Note 2)
(Note 1)
(Note 2)
Notes 1: This applies when the address output select bit (bit 4 at address 63 16) = “0.”
2: Recovery insertion of 2 cycles allows “the data hold time” to be extended by 38 ns, moreover.
(Note) (Note)
Note: This applies when the address output select bit (bit 4 at address 6316) = “0.”
Notes 1: This applies when the address output select bit (bit 4 at address 63 16) = “0.”
2: Recovery insertion of 1 cycle allows “the output enable time after OE enabled” to be set to “0 ns or more.”
3: Recovery insertion of 2 cycles allows “the data hold time” to be extended by 38 ns, moreover.
(Note 1)
(Note 2)
(Note 3)
Table 19.1.2 Timing requirements of mask ROM (f(fsys) = 26 MHz)
Table 19.1.3 Timing requirements of SRAM ( 16) (f(fsys) = 26 MHz)
(Note 1)
(Note 2)
(Note 3)
31 ns or less
8 ns or less
22 ns or less
6 ns or more
0 ns or more
(8 ns propagation delay time of 2) or less
(18 ns + propagation delay time of 1) or less
(9 n s – propagation delay time of 1) or less (9 ns propagation delay time of 1) or less
APPLICATIONS
7902 Group User’s Manual 19-9
19.1 Connection examples with external devices
Notes 1: This applies when the address output select bit (bit 4 at address 6316) = “0.”
2: Recovery insertion of 1 cycle allows “the output enabled time after OE enabled” to be set to “0 ns or more.”
3: Recovery insertion of 2 cycles allows “the data hold time” to be extended by 38 ns, moreover.
AS pulse width
CE setup time for AS
Address setup time for AS
Address hold time for AS
Ready-input setup time
Ready-termination setup time
OE access time
WE pulse width
Data setup time
Data hold time
Reading
/Writing
Reading
Writing
Bus cycle = 2φ + 2φ
18 ns or less
38 ns or less
18 ns or less
0 ns or less
40 ns or more
40 ns or more
5 ns or more and 46 ns or less
61 ns or less
56 ns or less
9 ns or less
37 ns or less
53 ns or less
37 ns or less
23 ns or less
40 ns or more
40 ns or more
5 ns or more and 84 ns or less
99 ns or less
94 ns or less
9 ns or less
Conditions
Item Bus cycle = 3φ + 3φ
(Note) (Note)
Note: Recovery insertion of 2 cycles allows “the data hold time” to be extended by 38 ns, moreover.
Address access time
OE access time
CE access time
Output enable time after OE enabled
Output disable time
Data setup time
Data hold time
Reading
Writing
31 ns or less
8 ns or less
22 ns or less
6 ns or more
0 ns or more
18 ns or less
9 ns or less
69 ns or less
46 ns or less
60 ns or less
6 ns or more
0 ns or more
18 ns or less
9 ns or less
Bus cycle = 1 φ + 1φConditions
Item Bus cycle = 1 φ + 2φ
(Note 1)
(Note 2)
(Note 3)
(Note 1)
(Note 2)
(Note 3)
Table 19.1.4 Timing requirements of SRAM ( 8) (f(fsys) = 26 MHz)
Table 19.1.5 Timing requirements of CD-ROM decoder (f(fsys) = 26 MHz)
APPLICATIONS
7902 Group User’s Manual
19-10
19.1 Connection examples with external devices
19.1.3 I/O expansion examples
Figure 19.1.6 shows a port expansion example with the M66010FP used. The frequency of a transfer clock
for serial I/O must be 1.923 MHz or less in order to satisfy the requirements of the M66010FP’s CLK pulse
width.
Serial I/O control in this expansion example is described below.
In this expansion example, 8-bit data transmission/reception is performed three times by using UART0, and
so the port pins are expanded up to 24 bits.
Clock synchronous serial I/O mode is selected. Transmission/Reception is enabled.
An internal clock is selected. The frequency of a transfer clock = 1.85 MHz.
LSB first is selected.
The control procedure is as follows:
“L” level is output from port P51. (This signal makes the expanded I/O port pins of the M66010FP
floating.)
“H” level is output from port P51.
“L” level is output from port P50.
24-bit data is transmitted/received by using UART0.
“H” level is output from port P50.
Figure 19.1.7 shows the serial transfer timing between the M37902 and M66010FP.
APPLICATIONS
7902 Group User’s Manual 19-11
19.1 Connection examples with external devices
Fig. 19.1.6 Port expansion example with M66010FP used
M37902
TXD0
RXD0
CLK0
P50
P51
RTS0
CSi
A0 to A23
D0 to D15
RD
BLW
BHW
φ1
MD0
MD1
BYTE
DI
DO
CLK
CS
S
VCC
GND
Circuit conditions: f(fsys) = 26 MHz
• UART0 is used in the clock synchronous serial I/O mode.
• An internal clock is selected.
• The frequency of a transfer clock = = 1.85 MHz.
• The applies when the peripheral devices’ clock select bits 1, 0
(bits 7, 6 at address BC16) = “002.”
M66010FP
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
Left open
Expanded I/O
port pins
f2
6 + 1
APPLICATIONS
7902 Group User’s Manual
19-12
19.1 Connection examples with external devices
Fig. 19.1.7 Serial transfer timing between M37902 and M66010FP
AAA
AAA
AAA
AAA
DO1
S
CS
CLK
DI
DO
D1
D2
to
D24
P5
1
P5
0
CLK
0
T
X
D
0
R
X
D
0
Expanded I/O port pin
Expanded I/O port pin
Expanded I/O port pin
Expanded I/O port pins are released from the floating state.
Data of expanded I/O port pins is input to the shift register 1.
Serial data is input to the shift register 2.
Data of the shift register 1 is output in serial.
Data of the shift register 2 is
output to expanded I/O port pins.
: This indicates a pin name of the M37902.
The others are pins’ names or operations of the M66010FP.
Output structure of an expanded I/O port pin is the N-channel
open drain.
DO2 DO3 DO4 DO5 DO6 DO7 DO8 DO20 DO21 DO22 DO23 DO24
DO1
DI20 DI21 DI22 DI23 DI24DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8
DI1
DO2DI2
DO24
DI24
APPLICATIONS
7902 Group User’s Manual 19-13
19.2 Examples of handling control pins in flash memory serial I/O mode
19.2 Examples of handling control pins in flash memory serial I/O mode
Each of pins P41 to P43, MD0, and MD1 serves as an input/output pin for a control signal in the flash memory
serial I/O mode. Also, be sure to handle pin NMI for avoiding the interrupt occurrence in the flash memory
serial I/O mode. Examples of handling these pins and pin RESET on the board are described below.
19.2.1 With control signals not affecting user system circuit
When control signals in the flash memory serial I/O mode are not used in the user system circuit, or when
these signals do not affect that circuit, the connections shown in Figure 19.2.1 are available. When pin
NMI, however, is used in the user system circuit, see Figures 19.2.2 and 19.2.3.
Fig. 19.2.1 Example of handing control pins when control signals do not affect user system circuit
M37902F
User system board
RESET
MD1
SDA (P4
2
)
BUSY (P4
3
)
SCLK (P4
1
)
X
IN
X
OUT
User reset signal (Note)
Not used, or Connected to the user system circuit.
Note: When there is a possibility that the user reset signal becomes “L” level in the flash memory serial I/O
mode, be sure to cut the current flow between the user reset pin and pin RESET by using a jumper
switch, etc.
V
SS
V
CC
MD0
Connected to
serial progra-
mmer.
NMI Left
open.
: The flash memory version of the 7902 Group
APPLICATIONS
7902 Group User’s Manual
19-14
19.2 Examples of handling control pins in flash memory serial I/O mode
19.2.2 With control signals affecting user system circuit
In the flash memory serial I/O mode, be sure to cut the current flow toward the user system circuit if control
signals for this mode are also used in the user system circuit. Figure 19.2.2 shows an example of handling
pins with jumper switches used, and Figure 19.2.3 shows an example of handling pins with analog switches
used.
Fig. 19.2.2 Example of handling pins with jumper switches used
Fig. 19.2.3 Example of handling pins with analog switches used
M37902F
RESET
User reset signal (Note)
User system board
Connected to the user system circuit.
MD1
SDA (P4
2
)
BUSY (P4
3
)
SCLK (P4
1
)
X
IN
X
OUT
NMI
V
SS
V
CC
MD0
Connected to
serial progra-
mmer.
Note: When there is a possibility that the user reset signal becomes “L” level in the flash memory serial I/O
mode, be sure to cut the current flow between the user reset pin and pin RESET by using a jumper
switch, etc.
: The flash memory version of the 7902 Group
M37902F
RESET
User reset signal (Note)
User system board
Connected to the user system circuit.
MD1
SDA (P4
2
)
BUSY (P4
3
)
SCLK (P4
1
)
X
IN
X
OUT
NMI V
SS
V
CC
MD0
Connected to
serial progra-
mmer.
74HC4066
Note: When there is a possibility that the user reset signal becomes “L” level in the flash memory serial I/O
mode, be sure to cut the current flow between the user reset pin and pin RESET by using a jumper
switch, etc.
: The flash memory version of the 7902 Group
CHAPTER 20CHAPTER 20
FLASH MEMORY
VERSION
20.1 Overview
20.2
Flash memory CPU reprogramming mode
[Precautions for flash memory CPU
reprogramming mode]
20.3 Flash memory serial I/O mode
[Precautions for flash memory serial
I/O mode]
20.4 Flash memory parallel I/O mode
[Precautions for flash memory parallel
I/O mode]
FLASH MEMORY VERSION
7902 Group User’s Manual
20-2
20.1 Overview
20.1 Overview
The flash memory version is provided with the same function as that of the mask ROM version except that
the former includes the flash memory. Note that, however, part of the SFR area of the flash memory version
differs from that of the mask ROM or external ROM version. (Refer to section “20.1.1 Memory assignment.”)
In the flash memory version, its internal flash memory can be handled in the following three reprogramming
modes: flash memory CPU reprogramming mode, flash memory serial I/O mode, and flash memory parallel
I/O mode.
Table 20.1.1 lists the performance overview of the flash memory version. (For the items not listed in Table
20.1.1, see Table 1.1.1.)
Table 20.1.1 Performance overview of flash memory version
Item Performance
Power source voltage
Programming/Erase voltage
Programming
Erase method
Flash memory reprogramming modes
Maximum number of reprograms (programming
and erasure)
M37902FGCGP
M37902FGMHP
M37902FGCGP
M37902FGMHP
5 V ± 0.5 V
3.3 V ± 0.3 V
5 V ± 0.5 V(3.3 V ± 0.3 V only in flash memory parallel I/O mode)
3.3 V ± 0.3 V
Programmed in a unit of 128 ward (256 bytes)
Block erase or Total erase
Flash memory CPU reprogramming mode
Flash memory serial I/O mode
Flash memory parallel I/O mode
100
For the flash memory version, in addition to the same three processor modes as those of the mask ROM
version, any of the four operating modes listed in Table 20.1.2 can further be selected by the voltage level
applied to pin MD1. Table 20.1.3 also lists the overview of flash memory reprogramming modes.
Note: Do not switch the voltages applied to pins MD0 and MD1 while the microcomputer is active.
Table 20.1.2 Operating mode selection according to
voltages applied to pins MD0 and MD1
Single-chip mode,
Memory expansion mode,
Microprocessor mode (Note 1)
Microprocessor mode (Note 1)
Boot mode (Note 2)
Flash memory parallel I/O mode
(Note 3)
VSS
VCC
VSS
VCC
MD1
VSS
VSS
VCC
VCC
MD0 Operating modes
Notes 1: Refer to section “2.5 Processor modes.”
2: Refer to section “20.1.2 Boot mode.”
3: Refer to section “20.4 Flash memory parallel
I/O mode.”
FLASH MEMORY VERSION
7902 Group User’s Manual 20-3
20.1 Overview
Table 20.1.3 Overview of flash memory reprogramming modes
Flash memory
reprogramming mode
Functional overview
Reprogrammable
area
Operating mode
available
ROM programmer
available
Flash memory CPU
reprogramming mode Flash memory serial I/O mode Flash memory parallel I/O mode
User ROM area is reprogram-
med by using a dedicated serial
programmer.
User ROM area
Boot mode
Serial programmer
(For the serial programmer, re-
fer to the latest catalog.)
Boot ROM area and User ROM
area are reprogrammed by using
a dedicated parallel programmer.
User ROM area,
Boot ROM area
Flash memory parallel I/O mode
Parallel programmer
(For the parallel programmer , re-
fer to the latest catalog.)
User ROM area is reprogrammed
by the CPU executing software
commands.
User ROM area
Single-chip mode,
Memory expansion mode,
Boot mode
(Unnecessary)
FLASH MEMORY VERSION
7902 Group User’s Manual
20-4
20.1 Overview
20.1.1 Memory assignment
The flash memory version is provided with the internal flash memory as shown below:
• M37902FJCGP/HP, M37902FJMHP (hereafter referred to M37902FJ): 498 Kbytes
• M37902FHCGP/HP, M37902FHMHP (hereafter referred to M37902FH): 370 Kbytes
• M37902FGCGP/HP, M37902FGMHP (hereafter referred to M37902FG): 248 Kbytes
• M37902FECGP/HP, M37902FEMHP (hereafter referred to M37902FE): 184 Kbytes
• M37902FCCGP/HP, M37902FCMHP (hereafter referred to M37902FC): 120 Kbytes
• M37902F8CGP/HP, M37902F8MHP (hereafter referred to M37902F8): 60 Kbytes
Figures 20.1.1 to 20.1.6 show the memory assignments of the flash memory version. Also, for the flash
memory versions other than above, refer to the latest datasheets or catalogs.
Fig. 20.1.1 Memory assignment of flash memory version (M37902FJ)
Microprocessor mode
SFR area
Internal
RAM area
(12 Kbytes)
Single-chip mode
Internal
RAM area
(12 Kbytes)
(Note 1)
SFR area
Memory expansion mode
FEFFFF16
FFFFFF16
Internal
RAM area
(12 Kbytes)
SFR area
Internal flash
memory area
(User ROM area)
(498 Kbytes)
(Note 2)
: This is an external area. The access to this area enables the access to an
externally-connected device.
Unused area
FF16
Notes 1: When the internal RAM area is followed by an external area, do not assign a
program to the last 8 bytes of the internal RAM area.
2: Do not assign a program to the last 8 bytes of the internal ROM area.
3: Do not access this area.
Reserved area
(Note 3)
FF000016
10016
7FF16
80016
7FFFF16
Internal flash
memory area
(User ROM area)
(498 Kbytes)
(Note 2)
8000016
37FF16
380016
Reserved area
(Note 3)
016
FLASH MEMORY VERSION
7902 Group User’s Manual 20-5
20.1 Overview
Fig. 20.1.2 Memory assignment of flash memory version (M37902FH)
016 SFR area
Internal
RAM area
(12 Kbytes)
Internal
RAM area
(12 Kbytes)
(Note 1)
SFR area
FEFFFF16
FFFFFF16
Internal
RAM area
(12 Kbytes)
SFR area
Internal flash
memory area
(User ROM area)
(370 Kbytes)
(Note 2)
Unused area
FF16
FF000016
10016
7FF16
80016
5FFFF16
Internal flash
memory area
(User ROM area)
(370 Kbytes)
(Note 2)
6000016
37FF16
380016
Microprocessor modeSingle-chip mode Memory expansion mode
Reserved area
(Note 3)
Reserved area
(Note 3)
: This is an external area. The access to this area enables the access to an
externally-connected device.
Notes 1: When the internal RAM area is followed by an external area, do not assign a
program to the last 8 bytes of the internal RAM area.
2: Do not assign a program to the last 8 bytes of the internal ROM area.
3: Do not access this area.
FLASH MEMORY VERSION
7902 Group User’s Manual
20-6
20.1 Overview
Fig. 20.1.3 Memory assignment of flash memory version (M37902FG)
016 SFR area
Internal
RAM area
(6 Kbytes)
Internal RAM area
(6 Kbytes)
(Note 1)
SFR area
FEFFFF16
FFFFFF16
Internal
RAM area
(6 Kbytes)
SFR area
Internal flash
memory area
(User ROM area)
(248 Kbytes)
(Note 2)
Unused area
FF16
FF000016
10016
7FF16
80016
1FFF16
200016
3FFFF16
Internal flash
memory area
(User ROM area)
(248 Kbytes)
(Note 2)
4000016
Microprocessor modeSingle-chip mode Memory expansion mode
Reserved area
(Note 3)
Reserved area
(Note 3)
: This is an external area. The access to this area enables the access to an
externally-connected device.
Notes 1: When the internal RAM area is followed by an external area, do not assign a
program to the last 8 bytes of the internal RAM area.
2: Do not assign a program to the last 8 bytes of the internal ROM area.
3: Do not access this area.
FLASH MEMORY VERSION
7902 Group User’s Manual 20-7
20.1 Overview
Fig. 20.1.4 Memory assignment of flash memory version (M37902FE)
016 SFR area
Internal
RAM area
(6 Kbytes)
Internal RAM area
(6 Kbytes)
(Note 1)
SFR area
FEFFFF16
FFFFFF16
Internal
RAM area
(6 Kbytes)
SFR area
Internal flash
memory area
(User ROM area)
(184 Kbytes)
(Note 2)
Unused area
FF16
FF000016
10016
7FF16
80016
1FFF16
200016
2FFFF16
Internal flash
memory area
(User ROM area)
(184 Kbytes)
(Note 2)
3000016
Microprocessor modeSingle-chip mode Memory expansion mode
Reserved area
(Note 3)
Reserved area
(Note 3)
: This is an external area. The access to this area enables the access to an
externally-connected device.
Notes 1: When the internal RAM area is followed by an external area, do not assign a
program to the last 8 bytes of the internal RAM area.
2: Do not assign a program to the last 8 bytes of the internal ROM area.
3: Do not access this area.
FLASH MEMORY VERSION
7902 Group User’s Manual
20-8
20.1 Overview
Fig. 20.1.5 Memory assignment of flash memory version (M37902FC)
016 SFR area
Internal RAM area
(4 Kbytes)(Note 1) Internal RAM area
(4 Kbytes)(Note 1)
SFR area
FEFFFF16
FFFFFF16
Internal RAM area
(4 Kbytes)(Note 1)
SFR area
Internal flash
memory area
(User ROM area)
(120 Kbytes)
(Note 2)
Unused area
FF16
FF000016
10016
7FF16
80016
17FF16
180016
1FFFF16
Internal flash
memory area
(User ROM area)
(120 Kbytes)
(Note 2)
2000016
Unused area
1FFF16
200016
Microprocessor modeSingle-chip mode Memory expansion mode
Reserved area
(Note 3)
Reserved area
(Note 3)
: This is an external area. The access to this area enables the access to an
externally-connected device.
Notes 1: When the internal RAM area is followed by an unused area or an external area,
do not assign a program to the last 8 bytes of the internal RAM area.
2: Do not assign a program to the last 8 bytes of the internal ROM area.
3: Do not access this area.
FLASH MEMORY VERSION
7902 Group User’s Manual 20-9
20.1 Overview
Fig. 20.1.6 Memory assignment of flash memory version (M37902F8)
0
16
SFR area
Internal RAM area
(2 Kbytes) Internal RAM area
(2 Kbytes)(Note 1)
SFR area
FEFFFF
16
FFFFFF
16
Internal RAM area
(2 Kbytes)
SFR area
Internal flash
memory area
(User ROM area)
(60 Kbytes)
(Note 2)
Unused area
FF
16
FF0000
16
100
16
7FF
16
800
16
FFF
16
1000
16
FFFF
16
Internal flash
memory area
(User ROM area)
(60 Kbytes)
(Note 2)
10000
16
Microprocessor mode
Single-chip mode Memory expansion mode
Reserved area
(Note 3)
Reserved area
(Note 3)
: This is an external area. The access to this area enables the access to an
externally-connected device.
Notes 1: When the internal RAM area is followed by an external area, do not assign a
program to the last 8 bytes of the internal RAM area.
2: Do not assign a program to the last 8 bytes of the internal ROM area.
3: Do not access this area.
FLASH MEMORY VERSION
7902 Group User’s Manual
20-10
20.1 Overview
In addition to the internal flash memory area (in other words, user ROM area) shown in Figures 20.1.1 to
20.1.6, the flash memory version has the boot ROM area of 16 Kbytes.
Figure 20.1.7 shows the internal flash memory assignment.
The user ROM area is divided into several blocks, and each block can individually be inhibited from being
programmed or erased (i.e. be locked). The user ROM area is reprogrammed in the flash memory CPU
reprogramming mode, serial I/O mode, and parallel I/O mode.
The boot ROM area is located at addresses where a part of the user ROM area resides and can be
reprogrammed only in the flash memory parallel I/O mode. (Refer to section “20.4 Flash memory parallel
I/O mode.”). When being reset with pin MD1 tied to Vcc level and pin MD0 to Vss level, the software in
the boot ROM area is executed after reset. (Refer to section “20.1.2 Boot mode.”) When pin MD1 = Vss
level, however, the contents of the boot ROM area cannot be read out.
FLASH MEMORY VERSION
7902 Group User’s Manual 20-11
20.1 Overview
Fig. 20.1.7 Internal flash memory assignment
M37902FC
M37902FE
Word
addresses Word
addresses
Word
addresses
6FFFF
16
70000
16
37FFF
16
38000
16
M37902FG
Byte
addresses
2000
16
8 Kbytes
8 Kbytes
8 Kbytes
32 Kbytes
(Note 1)
64 Kbytes
64 Kbytes
64 Kbytes
3FFF
16
4000
16
5FFF
16
6000
16
7FFF
16
8000
16
FFFF
16
10000
16
1FFFF
16
20000
16
2FFFF
16
30000
16
3FFFF
16
1000
16
1FFF
16
2000
16
2FFF
16
3000
16
3FFF
16
4000
16
7FFF
16
8000
16
FFFF
16
10000
16
17FFF
16
18000
16
1FFFF
16
User ROM area
C000
16
FFFF
16
Byte addresses
Boot ROM area
16 Kbytes
(In boot mode)
0
16
1FFF
16
Word addresses
(In flash memory
parallel I/O mode)
Notes 1: The area from addresses FFB0
16
to FFBF
16
is the reserved area for a serial
programmer. Therefore, in the flash memory serial I/O mode, do not program
to this area.
2: Do not program to the last 8 bytes of the user ROM area.
M37902F8
Byte
addresses
1000
16
12 Kbytes
8 Kbytes
8 Kbytes
32 Kbytes
(Note 1)
3FFF
16
4000
16
5FFF
16
6000
16
7FFF
16
8000
16
FFFF
16
800
16
1FFF
16
2000
16
2FFF
16
3000
16
3FFF
16
4000
16
7FFF
16
User ROM area
M37902FJ
Byte
addresses
3800
16
2 Kbytes
8 Kbytes
8 Kbytes
32 Kbytes
(Note 1)
64 Kbytes
64 Kbytes
64 Kbytes
3FFF
16
4000
16
5FFF
16
6000
16
7FFF
16
8000
16
FFFF
16
10000
16
1FFFF
16
20000
16
2FFFF
16
30000
16
3FFFF
16
1C00
16
1FFF
16
2000
16
2FFF
16
3000
16
3FFF
16
4000
16
7FFF
16
8000
16
FFFF
16
10000
16
17FFF
16
18000
16
1FFFF
16
64 Kbytes
64 Kbytes
64 Kbytes
40000
16
4FFFF
16
50000
16
5FFFF
16
60000
16
7FFFF
16
20000
16
27FFF
16
28000
16
2FFFF
16
30000
16
3FFFF
16
User ROM area
64 Kbytes
M37902FH
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
FLASH MEMORY VERSION
7902 Group User’s Manual
20-12
20.1 Overview
20.1.2 Boot mode
When being reset with pin MD1 tied to Vcc level and pin MD0 to Vss level, the flash memory version enters
the boot mode. In the boot mode, the software in the boot ROM area is executed after reset.
In the boot mode, either the boot ROM area or the user ROM area can be selected with the user ROM
area select bit (bit 5 at address 9E16). The boot ROM area is located at addresses C00016 to FFFF16 (byte
addresses) in the boot mode.
A reprogramming control firmware used in the flash memory serial I/O mode has been stored in the boot
ROM area on shipment. (Refer to section “20.3 Flash memory serial I/O mode.”) Therefore, when being
reset in the boot mode, the flash memory version enters the flash memory serial I/O mode, allowing the
user ROM area to be reprogrammed with a dedicated serial programmer.
Also the boot ROM area can be reprogrammed in the flash memory parallel I/O mode. If an appropriate
reprogramming control software using the CPU reprogramming mode has been stored in the boot ROM
area, reprogramming suitable for the user’s system is enabled.
Note that if the boot ROM area has been reprogrammed in the flash memory parallel I/O mode, the flash
memory serial I/O mode cannot be used.
FLASH MEMORY VERSION
7902 Group User’s Manual 20-13
20.2 Flash memory CPU reprogramming mode
WD
20.2 Flash memory CPU reprogramming mode
In this mode, the user ROM area can be reprogrammed by the central processing unit (CPU) executing
software commands. Therefore, this mode allows the user to reprogram the contents of the user ROM area
with the microcomputer mounted on the final printed circuit board, without using any ROM programmer.
Be sure to store the reprogramming control software into the user ROM area or the boot ROM area in
advance. In the flash memory CPU reprogramming mode, however, opcodes cannot be fetched for the
internal flash memory. Accordingly, be sure to transfer the reprogramming control software to an area other
than the internal flash memory area (e.g. the internal RAM area) and then execute the software in this area.
The flash memory CPU reprogramming mode is available in any of the single-chip, memory expansion, and
boot modes.
The software commands listed in Table 20.2.1 can be used in the flash memory CPU reprogramming mode.
For details of each command, refer to section “20.2.5 Software commands.”
Note that commands and data must be read from and written into even-numbered addresses within the user
ROM area, 16 bits at a time. At writing of command codes, the high-order 8 bits (D8 to D15) are ignored.
Table 20.2.1 Software commands
Write
Write
Write
Write
Write
Write
Write
Write
FF16
7016
5016
4116
2016
A716
7716
7116
Read
Write
Write
Write
Write
Read
SRD
WD
D016
D016
D016
D6
Read Array
Read Status Register
Clear Status Register
Page Programming
Block Erase
Erase All Unlocked Block
Lock Bit Programming
Read Lock Bit Status
WA
BA
BA
BA
Write WA + 2
Mode
Address
Data
(D0 to D7)Mode
Address
Mode
Address
1st cycle 2nd cycle 3rd cycle
SRD : Status register data (D0 to D7)
WA : Write address (A7 to A0 to be incremented by 2 from “0016” to “FE16”)
WD : Write data (16 bits)
BA : The highest address of a block (Note that A0 = 0.)
D6: Indicates the lock bit status. (Unlocked state when D6 = 1; Locked state when D6 = 0.)
: Arbitrary even-numbered address in user ROM area (A0 = 0)
Data Data
Commands
FLASH MEMORY VERSION
7902 Group User’s Manual
20-14
20.2 Flash memory CPU reprogramming mode
20.2.1 Flash memory control register
Figure 20.2.1 shows the structure of the flash memory control register.
0
1
2
3
4
5
7, 6
RY/BY status bit
CPU reprogramming mode select bit
Lock bit invalidity select bit
Flash memory reset bit (Note 5)
Fix this bit to “0.”
User ROM area select bit
(Valid in boot mode) (Note 7)
The value is “0” at reading.
RO
RW
(Notes 1, 2)
RW
(Notes 1, 4)
RW
(Note 6)
RW
RW
(Note 2)
1
0
0
0
0
0
0
0 : Lock bit is valid.
1 : Lock bit is invalid (Note 3).
Bit nameBit
Flash memory control register (Address 9E16)
Function At reset R/W
b7 b6 b5 b4 b3 b2 b1 b0
0 : BUSY (Automatic programming or erase operation
is active.)
1 : READY (Automatic programming or erase operation
has been completed.)
0 : Flash memory CPU reprogramming mode is invalid.
1 : Flash memory CPU reprogramming mode is valid.
Notes 1: In order to set this bit to “1,” write “0” followed with “1” successively; while in order to clear this bit “0,” write “0.”
2: Writing to this bit must be performed in an area other than the internal flash memory.
3: Simultaneously with the CPU reprogramming mode select bit (bit 1) cleared “0,” this bit is also cleared to “0.”
4: Only when the CPU reprogramming mode select bit (bit 1) = “1,” writing to this bit is available.
5: This bit is valid only when the CPU reprogramming mode select bit = “1”: on the other hand, when the CPU reprogra-
mming mode select bit = “0,” be sure to fix this bit to “0.”
6: After writing of “1” to this bit, be sure to write “0” successively.
7: When MD1 = Vss level, this bit is invalid. (It may be either “0” or “1.”)
0 : Access to boot ROM area
1 : Access to user ROM area
Writing “1” followed with “0” into this bit discontinues
the access to the internal flash memory. This causes
the built-in flash memory circuit being reset.
0
(1) RY/BY status bit (bit 0)
This bit is used to indicate the operating status of the write state machine (hereafter referred to WSM)
as well as the WSM status bit (SR.7 of the status register; refer to section “20.2.2 Status register.”).
This bit is “0” during the automatic programming or erase operation is active and becomes “1” upon
completion of them. This bit also changes during the execution of the page programming, block erase,
erase all unlocked block, or the lock bit programming command, but does not change owing to the
execution of another command.
(2) CPU reprogramming mode select bit (bit 1)
Setting this bit to “1” allows the microcomputer to enter the flash memory CPU reprogramming mode
to accept commands. In order to set this bit to “1,” write “1” followed with “0” successively; while to
clear this bit to “0,” write “0.”
Since the microcomputer enters the flash memory CPU reprogramming mode after setting this bit to
“1,” opcodes cannot be fetched for the internal flash memory. Accordingly, be sure to execute the
instruction to be used for writing to this bit in an area other than the internal flash memory area (e.g.
the internal RAM area).
When executing commands of the flash memory CPU reprogramming mode in the boot mode, be sure
to set the user ROM area select bit (bit 5) to “1.”
Fig. 20.2.1 Structure of flash memory control register
FLASH MEMORY VERSION
7902 Group User’s Manual 20-15
20.2 Flash memory CPU reprogramming mode
(3) Lock bit invalidity select bit (bit 2)
Setting this bit to “1” invalidates each lock bit for each block. (Refer to section “20.2.3 Data protect
function.”) and clearing it to “0” validates the lock bit. Writing to this bit is valid when the CPU
reprogramming mode select bit (bit 1) = “1.” In order to set the lock bit invalidity select bit to “1,” write
“1” followed with “0” successively; while in order to clear this bit “0,” write “0.”
(4) Flash memory reset bit (bit 3)
Writing “1” followed with “0” to this bit discontinues the access to the user ROM area and causes the
built-in flash memory control circuit to be reset. After this reset, the microcomputer enters the read
array mode to set the RY/BY status bit (bit 0) to “1” and the status register to “8016.” (Refer to section
“20.2.2 Status register.”)
When this flash memory control circuit is reset with the flash memory reset bit during programming
(automatic programming) or erase (automatic erase) operation, that programming or erase operation
is discontinued to invalidate the data in the working block.
In order to write to this bit, write “1” followed with “0” using successive instructions.
(5) User ROM area select bit (bit 5)
This bit is used to select either the boot ROM area or the user ROM area in the boot mode. In order
to access the boot ROM area (read out), clear this bit to “0.” On the other hand, in order to access
the user ROM area (reading out, programming, or erase), set it to “1.” Instructions for writing into this
bit must be executed in an area other than the internal flash memory (e.g. the internal RAM area).
Note that when MD1 = Vss level, the user ROM area is accessed (being read out) regardless of the
contents of this bit.
FLASH MEMORY VERSION
7902 Group User’s Manual
20-16
20.2 Flash memory CPU reprogramming mode
20.2.2 Status register
The programming and erase operations for the internal flash memory are controlled by the write state
machine in the internal flash memory (hereafter referred to WSM). The status register indicates the operating
status of the WSM and the completion states (normal or abnormal) of the programming and erase operations.
For details of abnormal endings (errors), refer to section “20.2.6 Full status check.”
Table 20.2.2 lists the bit definition of the status register.
The contents of the status register can be read out by the read status register command. (Refer to section
“20.2.5 Software commands.”)
Symbol
(Data bus) Status Definition
“0” “1”
Error <Excessive programming error>
Error<Programming error>
Error<Erase error>
READY
SR.0 (D0)
SR.1 (D1)
SR.2 (D2)
SR.3 (D3)
SR.4 (D4)
SR.5 (D5)
SR.6 (D6)
SR.7 (D7)
Block Status After Programming
Block Status
Erase Status
Write State Machine (WSM) Status
Terminated normally.
Terminated normally.
Terminated normally.
BUSY
Data bus: Indicates the data bus to be read out when the read status register command has been executed.
Table 20.2.2 Bit definition of status register
(1) Block status after programming bit (SR.3)
When an excessive programming error has occurred, this bit is set to “1” upon completion of the page
programming. Additionally, this bit is cleared to “0” by executing the clear status register command.
This bit is also cleared to “0” at reset.
(2) Programming status bit (SR.4)
This bit is set to “1” if a programming error has occurred during the automatic programming (the page
programming or lock bit programming) operation and cleared to “0” by executing the clear status
register command. This bit is also cleared to “0” at reset.
(3) Erase status bit (SR.5)
This bit is set to “1” if an erase error has occurred during the automatic erase (the block erase or
erase all unlocked block) operation and cleared to “0” by executing the clear status register command.
This bit is also cleared to “0” at reset.
(4) Write state machine (WSM) bit (SR.7)
This bit is used to indicate the operating status of the WSM. It is “0” during the automatic programming
or erase operation and set to “1” upon completion of these operations.
This bit also changes during the execution of the page programming, block erase, erase all unlocked
block, or the lock bit programming command, but this bit does not change by another command. This
bit is set to “1” at reset.
FLASH MEMORY VERSION
7902 Group User’s Manual 20-17
20.2 Flash memory CPU reprogramming mode
20.2.3 Data protect function
Each block of the internal flash memory is provided with a nonvolatile lock bit and can individually be
inhibited from being programmed or erased (i.e. be locked) according to the state of the corresponding lock
bit. Thus, this function prevents data from being inadvertently programmed or erased. The block states are
described below according to the contents of their lock bits:
• When lock bit = “0”
Locked state. The corresponding block cannot be programmed or erased.
• When lock bit = “1”
Unlocked state. The corresponding block can be programmed or erased.
Each lock bit is cleared to “0” (locked state) by executing the lock bit programming command and set to
“1” (unlocked state) by erasing the corresponding block. The lock bit cannot be set to “1” by any software
command.
The state of a lock bit can be read out with the read lock bit status command.
Setting the lock bit invalidity select bit (bit 2 at address 9E16) to “1” invalidates the functions of each lock
bit to put all the blocks into the unlocked state. (The contents of all lock bits do not change.) On the other
hand, clearing the lock bit invalidity select bit to “0” validates the functions of each lock bit. (The contents
of all lock bits are maintained.)
When the block erase or the erase all unlocked block command is executed with the lock bit invalidity
select bit = “1,” the corresponding block or all the blocks are erased regardless of the contents of their lock
bits. Upon completion of this erasure, the corresponding lock bit is set to “1” (unlocked state).
For details of each command, refer to section “20.2.5 Software commands.”
20.2.4 Setting and Terminate procedure for flash memory CPU reprogramming mode
Figure 20.2.2 shows the setting and terminate procedures for the flash memory CPU reprogramming mode.
In the flash memory CPU reprogramming mode, opcodes cannot be fetched for the internal flash memory.
Therefore, be sure to transfer the reprogramming control software to an area other than the internal flash
memory and then execute the software in that area.
Moreover, in order to prevent any interrupt occurrence during the flash memory CPU reprogramming mode,
the following procedures must be taken before selecting this mode:
• Set the interrupt disable flag (I) to “1” or set the interrupt priority level to “0002” (interrupts disabled)
• Apply the Vcc level voltage to pin NMI; or open pin NMI with the pin NMI pullup select bit (bit 7 at address
9216) = “0.”
Even in the flash memory CPU reprogramming mode, periodically writing to the watchdog timer is required
in order to prevent the watchdog timer interrupt occurrence.
At the same time, it is necessary to write to the watchdog timer before executing the page programming,
block erase, erase all unlocked block, or lock bit programming command in order to prevent the watchdog
timer interrupt occurrence during the automatic programming and erase operation.
Interrupt requests or resets generated in the flash memory CPU reprogramming mode bring about the
following results:
• Maskable interrupts make program runaway. If a program runaway has occurred, be sure to push the
microcomputer into the power-on reset state.
• Each of NMI and watchdog timer interrupts pushes the built-in flash memory control circuit and flash
memory control register into the reset state. This enables any of these interrupt requests to be accepted.
• Each of hardware and software resets pushes the built-in flash memory control circuit and flash memory
control register into the reset state. Additionally, this causes the microcomputer to be reset. (Refer to
“CHAPTER 4. RESET.”)
When the above interrupts or resets are generated during the programming or erase operation, the contents
of the corresponding block becomes invalidated.
FLASH MEMORY VERSION
7902 Group User’s Manual
20-18
20.2 Flash memory CPU reprogramming mode
20.2.5 Software commands
Software commands are described below.
Software commands and data must be read from and written into even-numbered addresses in the user
ROM area, 16 bits at a time. At writing of a command code, the high-order 8 bits (D8 to D15) are ignored.
(1) Read array command
Writing command code “FF16” at the 1st bus cycle pushes the microcomputer into the read array mode.
When an address to be read is input at the next and the following bus cycles, the contents at the
specified address are output to the data bus (D0 to D15), 16 bits at a time.
The read array mode is maintained until another software command is written.
(2) Read status register command
Writing command code “7016” at the 1st bus cycle outputs the contents of the status register to the
data bus (D0 to D7) by a read at the 2nd bus cycle. (See Table 20.2.2.)
(3) Clear status register command
Writing command code “5016” at the 1st bus cycle clears three bits (SR.3 to SR.5) of the status register
to “0.” (See Table 20.2.2.)
Fig. 20.2.2 Setting and Terminate procedures for flash memory CPU reprogramming mode
Jump to the control software transferred in the
above procedure.
(The subsequent procedures will be executed
by the reprogramming control software trans-
ferred in the above procedure.)
User ROM area select bit “1”
(Only in the boot mode)
CPU reprogramming mode select bit “0”
User ROM area select bit “0”
(Only in the boot mode ) (Note 2)
Jump to an arbitrary address in the
internal flash memory area.
The reprogramming control software for the flash
memory CPU reprogramming mode is transferred
to an area other than the internal flash memory.
Software command is executed.
Read array command is executed,
or Flash memory reset bit “1”
Flash memory reset bit “0”
(Note 1)
CPU reprogramming mode select bit “0”
CPU reprogramming mode select bit “1”
Notes 1: Before termination of the flash memory CPU reprogramming mode, be sure to execute the read array
command or flash memory reset.
2: When the flash memory CPU reprogramming mode has been terminated with the user ROM area select
bit = “1,” the access to the user ROM area is selected.
Reprogramming control
software
Internal ROM bus cycle select bit “0”
(bit 7 at address 5F
16
)
Interrupt disable flag (I) = “1”
or Interrupt priority level of each interrupt = “000
2
Pin NMI pullup select bit “0”
(bit 7 at address 92
16
)
Single-chip mode,
Memory expansion mode,
or Boot mode
FLASH MEMORY VERSION
7902 Group User’s Manual 20-19
20.2 Flash memory CPU reprogramming mode
(4) Page programming command
This command executes programming, 128
words (256 bytes) at a time. Write command
code “4116” at the 1st bus cycle and then write
data from the 2nd to the 129th bus cycles, 16
bits at a time. Additionally, increment the low-
order 8 bits (A7 to A0) of the write addresses
(in other words, addresses to which data will
be written) by 2 from “0016” to “FE16.” After writing
of 128 words has been completed, the automatic
programming (programming and verification of
data) operation is initiated. The completion of
the automatic programming can be recognized
by the WSM status bit (SR.7 of the status
register) or the RY/BY status bit (bit 0 at address
9E16).
Simultaneously with the start of the automatic
programming operation, the microcomputer
enters the read status register mode, allowing
the contents of the status register to be read.
The read status register mode is maintained
until the read array command (FF16) or read
lock bit status command (7116) is written or until
the flash memory reset bit is set to “1.”
After the automatic programming operation has
been completed, the result of it can be
recognized by reading out the status register.
(Refer to section “20.2.6 Full status check.”)
Figure 20.2.3 shows the page programming
operation flowchart.
Note that, for the pages having already been
Fig. 20.2.3 Page programming operation flowchart
programmed, be sure to program after an erase (block erase) operation. If the page programming
command is executed for the pages having already been programmed, no programming error will
occur, but the contents of the pages become undefined.
Full status check
Start
Command code
“4116” is written.
n = 0
Data is written to an
arbitrary write address. Write address
Write address + 2,
n n + 2
Page programming
operation is completed.
n = FE16 NO
YES
YES
••• See Figure 20.2.8.
RY/BY status bit = “1”?
(bit 0 at address 9E16)NO
FLASH MEMORY VERSION
7902 Group User’s Manual
20-20
20.2 Flash memory CPU reprogramming mode
(5) Block erase command
Writing of command code “2016” at the 1st bus
cycle and “D016” to the highest address (here,
A0 = 0) of the block to be erased at the 2nd
bus cycle initiate the automatic erase (erase
and erase-verify) operation for the specified
block. The completion of the automatic erase
operation can be recognized by the WSM status
bit (SR.7 of the status register) or the RY/BY
status bit (bit 0 at address 9E16).
Simultaneously with the start of the automatic
erase operation, the microcomputer enters the
read status register mode, allowing the contents
of the status register to be read. The read status
register mode is maintained until the read array
command (FF16) or the read lock bit status
command (7116) is written or until the flash
memory reset bit is set to “1.”
After the automatic erase operation is completed,
the result of it can be recognized by reading
out the status register. (Refer to section “20.2.6
Full status check.”)
Figure 20.2.4 shows the block erase operation
flowchart.
(6) Erase-all-unlocked-blocks command
When the lock bit invalidity select bit = “0,”
writing of command code “A716” at the 1st bus
cycle and “D016” at the 2nd bus cycle initiate
the automatic erase (erase and erase-verify)
operation for all the blocks whose lock bits are
“1” (unlocked state). The completion of the
automatic erase operation can be recognized
by the WSM status bit (SR.7 of the status
register) or the RY/BY status bit (bit 0 at address
9E16).
Simultaneously with the start of the automatic
erase operation, the microcomputer enters the
read status register mode, allowing the contents
of the status register to be read. The read status
register mode is maintained until the read array
command (FF16) or the read lock bit status
command (7116) is written or until the flash
memory reset bit is set to “1.”
After the automatic erase operation is completed,
the result of it can be recognized by reading
out the status register. (Refer to section “20.2.6
Full status check.”)
Figure 20.2.5 shows the erase-all-unlocked-
blocks operation flowchart.
Fig. 20.2.4 Block erase operation flowchart
Fig. 20.2.5
Erase-all-unlocked-blocks operation flowchart
Full status check
Start
Command code
“20
16
” is written.
“D0
16
” is written to the highest
address of the block.
Block erase operation is
completed.
YES
••• See Figure 20.2.8.
RY/BY status bit = “1”?
(bit 0 at address 9E
16
)NO
Lock bit invalidity select bit “0”
Lock bit invalidity select bit “1” Lock bit invalidity select bit “0”
Blocks in locked state are erased. Blocks in unlocked state are erased.
(Note)
Note: When the erase operation is performed with the lock bits invalida-
ted (the lock bit invalidity select bit = “1”), the lock bits of the blocks
to be erased become “1” (unlocked state) after the automatic erase
operation is completed.
Lock bit invalidity select bit “0”
Blocks in locked state are erased. Blocks in unlocked state are erased.
YES
RY/BY status bit = “1”?
(bit 0 at address 9E
16
)
NO
Full status check
Start
Command code
“A7
16
” is written.
“D0
16
” is written.
Erase-all-unlocked-blocks
operation is completed.
••• See Figure 20.2.8.
Lock bit invalidity select bit “0”
Lock bit invalidity select bit “1” Lock bit invalidity select bit “0”
All blocks are erased. Only blocks in unlocked state are erased.
Lock bit invalidity select bit “0”
All blocks are erased. Only blocks in unlocked state are erased.
(Note)
Note: When the erase operation is performed with the lock bits invalida-
ted (the lock bit invalidity select bit = “1”), the lock bits of all the
blocks become “1” (unlocked state) after the automatic erase
operation is completed.
FLASH MEMORY VERSION
7902 Group User’s Manual 20-21
20.2 Flash memory CPU reprogramming mode
(7) Lock bit programming command
Writing of command code “7716” at the 1st bus
cycle and “D016” to the highest address (here,
A0 = 0) of a block at the 2nd bus cycle initiate
writing “0” to the lock bit of the specified block
(locked state). The completion of this writing
can be recognized by the WSM status bit (SR.7
of the status register) or the RY/BY status bit
(bit 0 at address 9E16).
Simultaneously with writing to the lock bit, the
microcomputer enters the read status register
mode, allowing the contents of the status register
to be read. The read status register mode is
maintained until the read array command (FF16)
or the read lock bit status command (7116) is
written or until the flash memory reset bit is
set to “1.”
After writing is completed, the result of it can
be recognized by reading out the status register.
(Refer to section “20.2.6 Full status check.”)
Figure 20.2.6 shows the lock bit programming
operation flowchart.
(8) Read lock bit status command
Writing of command code “7116” at the 1st bus
cycle and reading of the highest address of a
block (here, A0 = 0) at the 2nd bus cycle allow
the state of the lock bit of the specified block
to be read onto the data bus (D6).
Figure 20.2.7 shows the read lock bit status
operation flowchart.
Fig. 20.2.6 Lock bit programming operation flowchart
Fig. 20.2.7 Read lock bit status operation flowchart
YES
RY/BY status bit = “1”?
(bit 0 at address 9E16)NO
SR.4 = 0?
Lock bit programming
operation is completed.
NO
YES
Lock bit programming
error
Start
Command code
“7716” is written.
“D016” is written to the highest
address of a block.
Locked state
D6 = 0? NO
YES
Unlocked state
Start
Command code
“7116” is written.
The highest address of
the block is read out.
FLASH MEMORY VERSION
7902 Group User’s Manual
20-22
20.2 Flash memory CPU reprogramming mode
20.2.6 Full status check
If an error has occurred, bits SR.3 to SR.5 of the status register are set to “1” upon completion of the
programming or erase operation. Therefore, the result of the programming or erase operation can be
recognized by checking these status (in other words, full status check).
Table 20.2.3 lists the errors and the states of bits SR.3 to SR.5, and Figure 20.2.8 shows the full status
check flowchart and the action to be taken if any error has occurred.
Table 20.2.3 Errors and States of bits SR.3 to SR.5
1
1
0
0
1
0
1
0
0
0
0
1
Command sequen-
ce error
Erase error
Programming error
Excessive progra-
mming error
• Commands are not correctly written.
• Data other than “D016” and “FF16” is written at the 2nd bus cycle of the
lock bit programming, block erase, or erase-all-unlocked-blocks
command (Note 1).
• The block erase command is executed for locked blocks (Note 2).
• Although the block erase or erase-all-unlocked-blocks command is
executed for unlocked blocks, these blocks are not correctly erased.
The page programming command is executed for pages in locked blocks (Note 2).
• Although the programming command is executed for pages in unlocked
blocks, these pages are not correctly programmed.
• Although the lock bit programming command is executed, programming
is not correctly performed.
• Excessive programming has occurred upon completion of the page
programming operation.
Error occurrence conditions
Status register
SR.5 SR.4 SR.3 Error
Notes 1: When “FF16” is written at the 2nd bus cycle of any of these commands, the microcomputer enters the read
array mode. Simultaneously with this, the command code written at the 1st bus cycle is cancelled.
2: While the lock bit is invalid (the lock bit invalidity select bit = “1”), no error will occur even if one of these
conditions is satisfied.
FLASH MEMORY VERSION
7902 Group User’s Manual 20-23
20.2 Flash memory CPU reprogramming mode
Fig. 20.2.8 Full status check flowchart and actions to be taken if any error has ocurred
Read status register
SR.5 = 0?
Completed.
NO
NO
YES
Erase error
YES Command sequence
error
SR.4 = 1
and
SR.5 = 1
?
SR.4 = 0? NO
YES
Programming error
SR.3 = 0? NO
YES
Excessive
programming error
Execute the clear status command to clear SR.4 and SR.5 to “0.”
Execute the correct command again.
Note: If the same error occurs, however, the block cannot be used.
• • • •
• • • •
• • • •
• • • •
Note: Under the condition that any of SR.5, SR.4, and SR.3 = “1,” none of the page programming, block erase, erase-all-unlocked-blocks,
and lock bit programming commands can be accepted. To execute any of these commands, in advance, execute the clear status
register command.
Execute the clear status command to clear SR.5 to “0.”
Execute the read lock bit status command. If the lock bit of the block
where an error has occurred, be sure to set the lock bit invalidity select
bit (bit 2 at address 9E16) to “1.”
Execute the block erase or erase-all-unlocked-blocks command again.
Note: If the same error occurs, however, the block cannot be used.
Also, when the lock bit in = “1,” the block cannot be used.
[At page programming command execution]
Execute the clear status command to clear SR.4 to “0.”
Execute the read lock bit status command. If the lock bit of the block
where an error has occurred, be sure to set the lock bit invalidity select
bit (bit 2 at address 9E16) to “1.”
Execute the page programming command again.
Note: If the same error occurs, however, the block cannot be used.
Also, when the lock bit in = “1,” the block cannot be used.
[At lock bit programming command execution]
Execute the clear status command to clear SR.4 to “0.”
Set the lock bit invalidity select bit (bit 2 at address 9E16) to “1.”
Execute the block erase command to erase the block where an error has
occurred.
Execute the lock bit programming command again.
Note: If the same error occurs, however, the block cannot be used.
Execute the clear status command to clear SR.3 to “0.”
Execute the block erase command to erase the block where an error has
occurred.
Execute the page programming command again.
Note: If the same error occurs, however, the block cannot be used.
FLASH MEMORY VERSION
7902 Group User’s Manual
20-24
20.2 Flash memory CPU reprogramming mode
20.2.7 Electrical characteristics
(1) M37902FGCGP
VCC power source current (at read)
VCC power source current (at write)
VCC power source current (at programming)
VCC power source current (at erasing)
ICC1
ICC2
ICC3
ICC4
mA
mA
mA
mA
Limits
Parameter Max.Min. UnitSymbol
48
48
54
54
Typ.
30
Page programming time
Block erase time
Erase all unlocked blocks time
Lock bit programming time
ms
ms
ms
ms
Limits
Parameter Max.Min. Unit
120
600
600 n
120
Typ.
8
50
50 n
8
AC Electrical Characteristics (VCC = 5 V ± 0.5 V, Ta = 0 to 60 °C, f(fsys) = 26 MHz)
DC Electrical Characteristics (VCC = 5 V ± 0.5 V, Ta = 0 to 60 °C, f(fsys) = 26 MHz)
n = Number of blocks to be erased
For the limits of parameters other than the above, refer to section “Appendix 9. M37902FGCGP
electrical characteristics.”
(2) M37902FGMHP
VCC power source current (at read)
VCC power source current (at write)
VCC power source current (at programming)
VCC power source current (at erasing)
ICC1
ICC2
ICC3
ICC4
mA
mA
mA
mA
Limits
Parameter Max.Min. UnitSymbol
40
40
48
48
Typ.
19
Page programming time
Block erase time
Erase all unlocked blocks time
Lock bit programming time
ms
ms
ms
ms
Limits
Parameter Max.Min. Unit
120
600
600 n
120
Typ.
8
50
50 n
8
AC Electrical Characteristics (VCC = 3.3 V ± 0.3 V, Ta = 0 to 60 °C, f(fsys) = 26 MHz)
DC Electrical Characteristics (VCC = 3.3 V ± 0.3 V, Ta = 0 to 60 °C, f(fsys) = 26 MHz)
n = Number of blocks to be erased
For the limits of parameters other than the above, refer to section “Appendix 10. M37902FGMHP
electrical characteristics.”
FLASH MEMORY VERSION
7902 Group User’s Manual 20-25
[Precautions for flash memory CPU reprogramming mode]
[Precautions for flash memory CPU reprogramming mode]
1. In the flash memory CPU reprogramming mode, an opcode cannot be fetched for the internal flash memory.
Accordingly, be sure to transfer the reprogramming control software to an area other than the internal flash memory
area, and then execute it in this area. (See Figure 20.2.2.)
Also, take consideration for instruction description (such as specified addresses, addressing modes) in the repro-
gramming control software since this software is to be executed in an area other than the internal flash memory
area.
2. In order to prevent any interrupt occurrence during the flash memory CPU reprogramming mode, the following
procedures must be taken before selecting this mode:
• Set the interrupt disable flag (I) to “1”; or set the interrupt priority level to “0002” (interrupts disabled)
Apply the Vcc level voltage to pin NMI; or open pin NMI with the pin NMI pullup select bit (bit 7 at address 9216) =
“0.”
Even in the flash memory CPU reprogramming mode, periodically writing to the watchdog timer is required.
3. Commands and data must be read from and written into even-numbered addresses in the user ROM area, 16 bits
at a time.
4. Addresses FFB016 to FFBF16 (the user ROM area) are reserved for serial programmers. Therefore, when there is a
possibility that the flash memory serial I/O mode is used, be sure not to program to this area.
FLASH MEMORY VERSION
7902 Group User’s Manual
20-26
20.3 Flash memory serial I/O mode
20.3 Flash memory serial I/O mode
In the flash memory serial I/O mode, by using a dedicated serial programmer, the contents of the user ROM
area can be reprogrammed with the microcomputer mounted on the final printed circuit board. About the
serial programmer concerned, consult its manufacturer, and for more information on using it, refer to the
user’s manual of the serial programmer.
Note that if the boot ROM area has been reprogrammed in the flash memory parallel I/O mode, the flash
memory serial I/O mode cannot be used. (Refer to section “20.4 Flash memory parallel I/O mode.”)
Addresses FFB016 to FFBF16 (the user ROM area) are reserved for serial programmers. Therefore, be sure
not to program to this area.
20.3.1 Pin description
Table 20.3.1 lists the pin description in the flash memory serial I/O mode, and Figures 20.3.1 and 20.3.2
show the pin configuration in this mode.
FLASH MEMORY VERSION
7902 Group User’s Manual 20-27
20.3 Flash memory serial I/O mode
Table 20.3.1 Pin description in flash memory serial I/O mode
Supply VCC level voltage to pin Vcc.
Supply VSS level voltage to pin Vss.
Connect this pin to VSS.
Connect this pin to VSS via a resistor (about 10 k to 100 k).
The BYTE pin. (Not used in this mode.)
The reset input pin (Note 1).
Connect a ceramic resonator or quartz-crystal oscillator between
XIN and X OUT pins. When using an external clock, the clcok source
must be input to X IN pin and XOUT pin must be left open.
Connect this pin to VCC, or leave it open.
The VCONT pin. (Not used in this mode.)
Connect this pin to VCC.
Connect this pin to VSS.
The VREF pin. (Not used in this mode.)
Input port pins. (Not used in this mode.)
The input pin for a serial clock.
The I/O pin for serial data. This pin must be connected to an external
pullup resistor (about 1 k).
The BUSY signal output pin.
Input port pins. (Not used in this mode.)
VCC
VSS
MD0
MD1
BYTE
RESET
XIN
XOUT
NMI
VCONT
AVCC
AVSS
VREF
P00 to P07
P10 to P17
P20 to P27
P30 to P33
P40,
P44 to P47
P41
P42
P43
P50 to P57
P60 to P67
P70 to P77
P80 to P87
P100 to P107
P110 to P117
Input
Input
Input
Input
Input
Output
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Output
Input
Input
Input
Input
Input
Input
Pin Name
Input/Output
Functions
Power supply input
MD0
MD1
External data bus
width select input
Reset input
Clock input
Clock output
NMI interrupt input
Filter circuit connection
Analog supply input
Reference voltage input
Input port P0
Input port P1
Input port P2
Input port P3
Input port P4
SCLK input
SDA I/O
BUSY output
Input port P5
Input port P6
Input port P7
Input port P8
Input port P10
Input port P11
Notes 1: When there is a possibility that the user reset signal becomes “L” level in the flash memory serial I/O
mode, be sure to cut off the current flow between the user reset signal and pin RESET by using a
jumper switch, etc. (Refer to section “19.2 Examples of handling control pins in flash memory
serial I/O mode.”)
2: For pins not used in the flash memory serial I/O mode, properly connect to somewhere in the user
system. For pins not used in the user system, handle them with reference to section “6.3 Examples of
handling unused pins.” For pins used in the flash memory serial I/O mode, handle them with reference
to section “19.2 Examples of handling control pins in flash memory serial I/O mode.”
FLASH MEMORY VERSION
7902 Group User’s Manual
20-28
20.3 Flash memory serial I/O mode
Fig. 20.3.1 Pin connection in flash memory serial I/O mode (Outline: 100P6S-A)
SCLK
403736 38
3534333231 39
64
63
62
61
30
29
28
27
26
25
24
23
22
21
3
2
1
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20 60
59
58
57
56
55
54
53
52
51
504948474644434241
100
79
78
77
76
75
74
73
72
71
69
68
67
66
65
70
80
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
P4
1
/φ
1
P8
1
/CTS
0
/CLK
0
P8
2
/R
X
D
0
P8
3
/T
X
D
0
V
SS
AV
SS
V
REF
V
CC
AV
CC
V
SS
P7
3
/AN
3
P8
4
/CTS
1
/RTS
1
/INT
4
P8
5
/CTS
1
/CLK
1
P8
6
/R
X
D
1
MD1
V
CC
V
SS
X
OUT
X
IN
P4
0
/ALE
P4
2
/HLDA
V
CONT
RESET
MD0
P10
3
/A
3
P10
4
/A
4
P10
5
/A
5
P10
6
/A
6
P10
7
/A
7
P10
1
/A
1
P10
2
/A
2
P11
0
/A
8
P11
1
/A
9
P11
2
/A
10
P11
3
/A
11
P11
4
/A
12
P11
5
/A
13
P11
6
/A
14
P11
7
/A
15
P0
0
/A
16
P0
1
/A
17
P0
2
/A
18
P0
3
/A
19
P0
4
/A
20
P0
5
/A
21
P0
7
/A
23
P0
6
/A
22
P1
0
/D
0
/LA
0
P1
1
/D
1
/LA
1
P1
2
/D
2
/LA
2
P1
5
/D
5
/LA
5
P2
5
/D
13
P2
4
/D
12
P2
3
/D
11
P2
0
/D
8
P1
7
/D
7
/LA
7
P2
2
/D
10
P2
1
/D
9
P1
6
/D
6
/LA
6
P3
3
/BHW
P3
1
/RD
P3
2
/BLW
P4
5
/CS
1
P6
0
/TA4
OUT
P6
1
/TA4
IN
P6
2
/INT
0
P6
3
/INT
1
P6
4
/INT
2
P6
5
/TB0
IN
P6
6
/TB1
IN
P5
0
/TA0
OUT
/RTP0
0
P5
1
/TA0
IN
/RTP0
1
P5
2
/TA1
OUT
/RTP0
2
P5
3
/TA1
IN
/RTP0
3
P5
4
/TA2
OUT
/RTP1
0
/KI
0
P5
5
/TA2
IN
/RTP1
1
/KI
1
P5
6
/TA3
OUT
/RTP1
2
/KI
2
P5
7
/TA3
IN
/RTP1
3
/KI
3
P4
6
/CS
2
P4
4
/CS
0
P4
3
/HOLD
M37902FGCGP
V
CC
V
SS
RESET
BUSY
SDA MD1
P2
7
/D
15
P2
6
/D
14
P4
7
/CS
3
P6
7
/TB2
IN
P7
0
/AN
0
P7
4
/AN
4
/(INT
3
)
P7
5
/AN
5
/(INT
4
)
P7
6
/AN
6
/DA
0
P7
7
/AN
7
/AD
TRG
/DA
1
/(INT
2
)
P8
0
/CTS
0
/RTS
0
/DA
2
/INT
3
NMI
P7
1
/AN
1
P7
2
/AN
2
P8
7
/TxD
1
P10
0
/A
0
P1
3
/D
3
/LA
3
P1
4
/D
4
/LA
4
P3
0
/RDY
BYTE
❈❈
: Connected to the oscillation circuit.
: Connected to V
CC
or kept open.
: Connected to a serial programmer.
Outline 100P6S-A
FLASH MEMORY VERSION
7902 Group User’s Manual 20-29
20.3 Flash memory serial I/O mode
Fig. 20.3.2 Pin connection in flash memory serial I/O mode (Outline: 100P6Q-A)
P4
1
/φ
1
P4
0
/ALE
P4
2
/HLDA
P4
5
/CS
1
P6
0
/TA4
OUT
P6
1
/TA4
IN
P6
2
/INT
0
P6
3
/INT
1
P6
4
/INT
2
P6
5
/TB0
IN
P6
6
/TB1
IN
P5
0
/TA0
OUT
/RTP0
0
P5
1
/TA0
IN
/RTP0
1
P5
2
/TA1
OUT
/RTP0
2
P5
3
/TA1
IN
/RTP0
3
P5
4
/TA2
OUT
/RTP1
0
/KI
0
P5
5
/TA2
IN
/RTP1
1
/KI
1
P5
6
/TA3
OUT
/RTP1
2
/KI
2
P5
7
/TA3
IN
/RTP1
3
/KI
3
P4
6
/CS
2
P4
4
/CS
0
P4
3
/HOLD
P4
7
/CS
3
P6
7
/TB2
IN
P7
0
/AN
0
100 99 98 97 96
59
58
57
56
55
54
53
52
51
95
74
73
72
71
70
69
68
67
66
64
63
62
61
60
65
75
94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
V
CC
3029282726 403736 383534333231 39 50494847464544434241
V
SS
RESET
25
24
23
22
21
3
2
1
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SCLK
BUSY
SDA MD1
V
CC
V
SS
X
OUT
X
IN
V
CONT
RESET
MD0
P1
3
/D
3
/LA
3
P1
4
/D
4
/LA
4
P1
5
/D
5
/LA
5
P2
5
/D
13
P2
4
/D
12
P2
3
/D
11
P2
0
/D
8
P1
7
/D
7
/LA
7
P2
2
/D
10
P2
1
/D
9
P1
6
/D
6
/LA
6
P2
7
/D
15
P2
6
/D
14
P3
3
/BHW
P3
1
/RD
P3
2
/BLW
P3
0
/RDY
BYTE
V
SS
MD1
P10
4
/A
4
P10
5
/A
5
P10
6
/A
6
P10
7
/A
7
P11
0
/A
8
P11
1
/A
9
P11
2
/A
10
P11
3
/A
11
P11
4
/A
12
P11
5
/A
13
P11
6
/A
14
P11
7
/A
15
P0
0
/A
16
P0
1
/A
17
P0
2
/A
18
P0
3
/A
19
P0
4
/A
20
P0
5
/A
21
P0
7
/A
23
P0
6
/A
22
P1
0
/D
0
/LA
0
P1
1
/D
1
/LA
1
P1
2
/D
2
/LA
2
P10
3
/A
3
P10
1
/A
1
P10
2
/A
2
P8
7
/T
X
D
1
P10
0
/A
0
P8
1
/CTS
0
/CLK
0
P8
2
/R
X
D
0
P8
3
/T
X
D
0
V
SS
AV
SS
V
REF
V
CC
AV
CC
P7
3
/AN
3
P7
2
/AN
2
P7
1
/AN
1
P8
4
/CTS
1
/RTS
1
/INT
4
P8
5
/CTS
1
/CLK
1
P8
6
/R
X
D
1
P7
4
/AN
4
/(INT
3
)
P7
5
/AN
5
/(INT
4
)
P7
6
/AN
6
/DA
0
P7
7
/AN
7
/AD
TRG
/DA
1
/(INT
2
)
P8
0
/CTS
0
/RTS
0
/DA
2
/INT
3
NMI
✼✼
M37902FGMHP
: Connected to the oscillation circuit.
: Connected to V
CC
or kept open.
: Connected to a serial programmer.
Outline 100P6Q-A
FLASH MEMORY VERSION
7902 Group User’s Manual
20-30
[Precautions for flash memory serial I/O mode]
[Precautions for flash memory serial I/O mode]
1. If the boot ROM area has been reprogrammed in the flash memory parallel I/O mode, the flash memory serial I/O
mode cannot be used.
2. In order to prevent any interrupt occurrence during the flash memory serial I/O mode, one of the following proce
dures must be taken:
• Connect pin NMI to Vcc.
• Leave pin NMI open.
(Refer to section “19.2 Examples of handling control pins in flash memory serial I/O mode.”)
3. When there is a possibility that the user reset signal becomes “L” level in the flash memory serial I/O mode, be sure
to cut the current flow between the user reset pin and pin RESET by using a jumper switch, etc. (Refer to
section “19.2 Examples of handling control pins in flash memory serial I/O mode.”)
4. Addresses FFB016 to FFBF16 (the user ROM area) are reserved for serial programmers. Therefore, be sure not to
program to this area.
FLASH MEMORY VERSION
7902 Group User’s Manual 20-31
20.4 Flash memory parallel I/O mode
20.4 Flash memory parallel I/O mode
In the flash memory parallel I/O mode, the contents of the user ROM area and boot ROM area can be
reprogrammed by using a dedicated parallel programmer. (See Figure 20.1.7.) About the parallel programmer
concerned, consult its manufacturer, and for more information on using it, refer to the user’s manual of the
parallel programmer.
In the flash memory parallel I/O mode, the boot ROM area is assigned to addresses 016 to 1FFFF16 (word
addresses).
Note that if the boot ROM area has been reprogrammed in the flash memory parallel I/O mode, the flash
memory serial I/O mode cannot be used. (Refer to section “20.3 Flash memory serial I/O mode.”)
In the flash memory parallel I/O mode, the programming and erase voltages = 3.3 V±0.3 V regardless of
the type of microcomputer.
For details of functions, refer to the corresponding latest datasheets.
FLASH MEMORY VERSION
7902 Group User’s Manual
20-32
[Precautions for flash memory parallel I/O mode]
[Precautions for flash memory parallel I/O mode]
1. If the boot ROM area has been reprogrammed in the flash memory parallel I/O mode, the flash memory serial I/O
mode cannot be used. (Refer to section “20.3 Flash memory serial I/O mode.”)
2. In the flash memory parallel I/O mode, only the word addresses are available.
3. Addresses FFB016 to FFBF16 (the user ROM area; byte addresses) are reserved for serial programmers. Therefore,
when there is a possibility that the flash memory serial I/O mode is used, be sure not to program to this area.
APPENDIXAPPENDIX
Appendix 1. Memory assignment in
SFR area
Appendix 2. Control registers
Appendix 3. Package outline
Appendix 4. Examples of handling
unused pins
Appendix 5. Hexadecimal instruction
code table
Appendix 6. Machine instructions
Appendix 7. Countermeasure against
noise
Appendix 8. 7902 Group Q & A
Appendix 9. M37902FGCGP electrical
characteristics
Appendix 10. M37902FGMHP electrical
characteristics
Appendix 11.Standard characteristics
Appendix 12.Memory assignment of
7902 Group
7902 Group User’s Manual
APPENDIX
21-2
Appendix 1. Memory assigment in SFR area
Appendix 1. Memory assigment in SFR area
0 1 1
0 00
?
0
?
: It is possible to read the bit state at reading. The written value becomes valid.
: It is possible to read the bit state at reading. The written value becomes invalid.
: The written value becomes valid. It is impossible to read the bit state.
: Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid.
RW
RO
WO
Access characteristics
0
1
?
: “0” immediately after reset.
: “1” immediately after reset.
: Undefined immediately after
reset.
: Always “0” at reading.
: Always “1” at reading.
: Always undefined at reading.
: “0” immediately after reset. Fix this bit to “0.”
0
?
1
State immediately after reset
1016
1116
1216
1316
1416
1516
1616
1716
1816
1916
1A16
1C16
1B16
1D16
1E16
1F16
016
116
216
316
416
516
616
716
816
916
B16
C16
D16
E16
F16
A16
Address
Port P8 direction register
Port P4 register
Port P5 register
Port P4 direction register
Port P5 direction register
Port P6 register
Port P7 register
Port P6 direction register
Port P7 direction register
Port P8 register
A-D control register 0
A-D control register 1
Register name
Port P10 register
Port P10 direction register
Port P0 register
Port P1 register
Port P0 direction register
Port P1 direction register
Port P2 register
Port P3 register
Port P2 direction register
Port P3 direction register
Port P11 register
Port P11 direction register 0016
?
Access characteristics
State immediately after reset
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
?
?
0016
0016
?
?
0016
0016
0016
?
?
?
0016
?
?
?
?
?
?
b7 b0 b7 b0
?
RW
RW
RW
RW
00
16
00
16
??
00
16
?
RW
RW
RW
RW
RW
RW
RW
RW RW
RW 0000
00000000
??00?000
(Note 1)
(Note 1)
Notes 1: Do not read and write.
0
0
7902 Group User’s Manual 21-3
APPENDIX
Appendix 1. Memory assigment in SFR area
000000
000000?
?
?
000000
?
000000
RORO
RORO
RORO
RORO
UART0 transmit/receive control register 0
UART0 transmit/receive mode register
UART0 baud rate register
UART0 transmit buffer register
UART1 receive buffer register
UART0 transmit/receive control register 1
UART0 receive buffer register
UART1 transmit/receive mode register
UART1 baud rate register
UART1 transmit buffer register
UART1 transmit/receive control register 0
UART1 transmit/receive control register 1
30
16
31
16
32
16
33
16
34
16
35
16
36
16
37
16
38
16
39
16
3A
16
3B
16
3C
16
3D
16
3E
16
28
16
29
16
2B
16
2C
16
2D
16
2E
16
2F
16
2A
16
20
16
21
16
22
16
23
16
24
16
25
16
26
16
27
16
3F
16
b7 b0
Register name
Address Access characteristics State immediately after reset
b7 b0
A-D register 5
A-D register 1
A-D register 3
A-D register 2
A-D register 4
A-D register 0
A-D register 6
A-D register 7
RW
RW
?
000000
?
000000
?
000000
RW
WO
WO
RO RO
WO
RWRO
RO RORW RW
RO RO
RW
WO
WO WO
RWRO
RO RORW RW
?
?
?
?
?
?
?
01000
?
?
?
00
16
?
?
?
?
0000000?
?
?
00
16
00000010
0000000?
1000
00000010
RO
RO
RO
RO
RO
RO
RO
RO
000
0000
?
RO
RO
RORO
RORO
RORO
000000
: It is possible to read the bit state at reading. The written value becomes valid.
: It is possible to read the bit state at reading. The written value becomes invalid.
: The written value becomes valid. It is impossible to read the bit state.
: Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid.
RW
RO
WO
Access characteristics
0
1
?
: “0” immediately after reset.
: “1” immediately after reset.
: Undefined immediately after
reset.
: Always “0” at reading.
: Always “1” at reading.
: Always undefined at reading.
: “0” immediately after reset. Fix this bit to “0.”
0
?
1
State immediately after reset
0
7902 Group User’s Manual
APPENDIX
21-4
Appendix 1. Memory assigment in SFR area
: It is possible to read the bit state at reading. The written value becomes valid.
: It is possible to read the bit state at reading. The written value becomes invalid.
: The written value becomes valid. It is impossible to read the bit state.
: Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid.
RW
RO
WO
Access characteristics
0
1
?
: “0” immediately after reset.
: “1” immediately after reset.
: Undefined immediately after
reset.
: Always “0” at reading.
: Always “1” at reading.
: Always undefined at reading.
: “0” immediately after reset. Fix this bit to “0.”
0
?
1
State immediately after reset
0
(Note 5)
0
0
0
0
00
1
00?? 000
00??000
Timer B2 register
4016
4116
4216
4316
4416
4516
4616
4716
4816
4916
5016
5116
5216
5316
5416
5516
5616
5716
5816
5916
5A16
5B16
5C16
5D16
5E16
5F16
4B16
4C16
4D16
4E16
4F16
4A16
Timer A2 register
Timer A3 register
Timer A4 register
Timer B0 register
Timer B1 register
Processor mode register 0
One-shot start register
Timer A0 register
Up-down register
Timer A1 register
Count start register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
WO
RW
b7 b0
RW
RW
RW
RW
RW
RW
RW
RWWO
??
?
?
?
?
?
?
?
?
?
?
?
?
0016
0016
0016
?
0016
b7 b0
?
?
0
WO RW
RW
RW
Timer A0 mode register
Timer A4 mode register
Processor mode register 1
(Note 7)
RW
RW
RW
(Note 4)
0000000
?
?
00?? 0000
(Note 5)
000
RW
00 0
(Note 4)
(Note 4)
0
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 3)
(Note 3)
0
0
0
000
000 0
0016
0016
(Note 5)
RWRW
Timer A clock division select register
(Note 6) (Note 6)
RW
RWRW 0
RW RW
RW
Register name
Address Access characteristics State immediately after reset
Notes 2: The access characteristics at addresses 46
16
to 4F
16
vary according to the timer A’s operating mode. (Refer to
“CHAPTER 9. TIMER A.”)
3: The access characteristics at addresses 50
16
to 55
16
vary according to the timer B’s operating mode. (Refer to
“CHAPTER 10. TIMER B.”)
4: The access characteristics for bit 5 at addresses 5B
16
and 5D
16
vary according to the timer B’s operating mode.
(Refer to “CHAPTER 10. TIMER B.”)
5: This bit is “0” when Vss-level voltage is applied to pin MD0; this bit is “1” when Vcc-level voltage is applied.
6: After reset, this bit can be set to “1” only once. Once this bit goes from “1” to “0,” it cannot be set to “1” again.
(This bit is fixed to “0.”)
7: In the external ROM version, for bit 7, nothing is assigned. This bit is “0” at reading.
0
7902 Group User’s Manual 21-5
APPENDIX
Appendix 1. Memory assigment in SFR area
: It is possible to read the bit state at reading. The written value becomes valid.
: It is possible to read the bit state at reading. The written value becomes invalid.
: The written value becomes valid. It is impossible to read the bit state.
: Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid.
RW
RO
WO
Access characteristics
0
1
?
: “0” immediately after reset.
: “1” immediately after reset.
: Undefined immediately after
reset.
: Always “0” at reading.
: Always “1” at reading.
: Always undefined at reading.
: “0” immediately after reset. Fix this bit to “0.”
0
?
1
State immediately after reset
0
00
?
?
?
?
0
RW
1
0(Note 12)
UART1 receive interrupt control register
60
16
61
16
62
16
63
16
64
16
65
16
66
16
67
16
68
16
69
16
70
16
71
16
72
16
73
16
74
16
75
16
76
16
77
16
78
16
79
16
7A
16
7B
16
7C
16
7D
16
7E
16
7F
16
6B
16
6C
16
6D
16
6E
16
6F
16
6A
16
A-D conversion interrupt control register
UART0 transmit interrupt control register
UART1 transmit interrupt control register
INT
2
interrupt control register
Watchdog timer frequency select register
Watchdog timer register
Timer A0 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT
0
interrupt control register
b7 b0 b7
UART0 receive interrupt control register
Timer A1 interrupt control register
Timer B0 interrupt control register
INT
1
interrupt control register
Debug control register 0
INT
4
interrupt control register
RW
RW
(Note 8)
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RWRWRW RW
b0
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
? (Note 9) 000
0000
0
0
0000
?000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
00
00
00
RW
RW
RW
RW
INT
3
interrupt control register
Debug control register 1
RW RWRO ?
?
(Note 12)
0000
0
?
Particular function select register 0
Particular function select register 1
000
(Note 12)
(Note 11)
RORO RW
RW
RWRWRW
RW
RW (Note 14)
RW (Note 14)
RW (Note 14)
RW (Note 14)
RW (Note 14)
RW (Note 14)
Address comparison register 0
Address comparison register 1
0
RW (Note 10)
0
(Note 13)
Particular function select register 2
Register name
Address Access characteristics State immediately after reset
Notes 8 : By writing dummy data to address 60
16
, a value of “FFF
16
” is set to the watchdog timer.
The dummy data is not retained anywhere.
9 : A value of “FFF
16
” is set to the watchdog timer. (Refer to “CHAPTER 15. WATCHDOG TIMER.”)
10 : After writing “55
16
” to address 62
16
, each bit must be set.
11 : It is possible to read the bit state at reading. By writing “0” to this bit, this bit becomes “0.”
But when writing “1” to this bit, this bit will not change.
12 : This bit becomes “0” at power-on reset. This bit retains the state immediately before reset in the case of
hardware reset and software reset.
13 : Do not write.
14 : When these registers are accessed, set the address comparison register access enable bit (bit 2 at address
67
16
) to “1.” (Refer to “CHAPTER 18. DEBUG FUNCTION.”)
0
000000
0
00 0
7902 Group User’s Manual
APPENDIX
21-6
Appendix 1. Memory assigment in SFR area
: It is possible to read the bit state at reading. The written value becomes valid.
: It is possible to read the bit state at reading. The written value becomes invalid.
: The written value becomes valid. It is impossible to read the bit state.
: Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid.
RW
RO
WO
Access characteristics
0
1
?
: “0” immediately after reset.
: “1” immediately after reset.
: Undefined immediately after
reset.
: Always “0” at reading.
: Always “1” at reading.
: Always undefined at reading.
: “0” immediately after reset. Fix this bit to “0.”
0
?
1
State immediately after reset
0
RO 0
1
1
1
RW
RW
RW
RW
0
0
0
0
?
?
1
000 000
00
000
10
00
00000
00
00 0
10
00
0000
00
00
1000
01
00
(Note 15)
1010
80
16
81
16
82
16
83
16
84
16
85
16
86
16
87
16
88
16
89
16
90
16
91
16
92
16
93
16
94
16
95
16
96
16
97
16
98
16
99
16
9A
16
9B
16
9C
16
9D
16
9E
16
9F
16
8B
16
8C
16
8D
16
8E
16
8F
16
8A
16
CS
0
control register H
CS
0
control register L b7 b0 b7
RW
RW RW
b0
RW
RW
RW
RW
RW
RW
RO
RW
?
?
CS
1
control register H
CS
1
control register L
CS
2
control register H
CS
2
control register L
CS
3
control register H
CS
3
control register L
Area CS
0
start address register
Area CS
1
start address register
Area CS
2
start address register
Area CS
3
start address register
RWRWRORWRW
RW
RW
RW
RW RW
RW
RW
RW
0000 0
10
000000
00
0000 000
?
0000 000
?
000
00
000
0000
00
0000
00
?
?
??
?
?
?
?
(Note 16)
RW
RW
(Note 17)
(Note 17)
Flash memory control register (Note 18)
D-A register 2
D-A register 1
D-A register 0
D-A control register
External interrupt input read-out register
External interrupt input control register
Port function control register
0
0001
RWRW RW
RW
Register name
Address Access characteristics State immediately after reset
Notes 15 : This bit is “0” when Vss-level voltage is applied to pin MD0; this bit is “1” when Vcc-level voltage is applied.
16 : This bit is “0” when Vss-level voltage is applied to pin BYTE; this bit is “1” when Vcc-level voltage is applied.
17 : Do not write.
18 : This register is allocated only to the flash memory version. (Refer to “CHAPTER 20. FLASH MEMORY
VERSION.”) Do not write to this register in the mask ROM and external ROM versions.
0 0
00
16
00
16
00
16
00
00
00
0
7902 Group User’s Manual 21-7
APPENDIX
Appendix 1. Memory assigment in SFR area
: It is possible to read the bit state at reading. The written value becomes valid.
: It is possible to read the bit state at reading. The written value becomes invalid.
: The written value becomes valid. It is impossible to read the bit state.
: Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid.
RW
RO
WO
Access characteristics
0
1
?
: “0” immediately after reset.
: “1” immediately after reset.
: Undefined immediately after
reset.
: Always “0” at reading.
: Always “1” at reading.
: Always undefined at reading.
: “0” immediately after reset. Fix this bit to “0.”
0
?
1
State immediately after reset
0
?
?
00000 000
00
?
?
00
A0
16
A1
16
A2
16
A3
16
A4
16
A5
16
A6
16
A7
16
A8
16
A9
16
B0
16
B1
16
B2
16
B3
16
B4
16
B5
16
B6
16
B7
16
B8
16
B9
16
BA
16
BB
16
BC
16
BD
16
BE
16
BF
16
AB
16
AC
16
AD
16
AE
16
AF
16
AA
16
Real-time output control register b7 b0 b7
WO
b0
Pulse output data register 0
Pulse output data register 1
Serial I/O pin control register
Clock control register
RW
WO
RWRWRWRW
?
?
?
?
?
?
?
?
0
?
?
?
?
0001
11
?
?
?
?
?
?
?
?
?
?
?
?
?
Notes 19 : Do not write to this register.
20 : After reset, these bits are allowed to be changed only once.
00000
(Note 19)
(Note 19)
(Note 19)
(Note 19)
(Note 19)
Register name
Address Access characteristics State immediately after reset
RWRW RWRW
(Note 20)
RW RW
7902 Group User’s Manual
APPENDIX
21-8
Appendix 2. Control registers
Appendix 2. Control registers
The control registers allocated in the SFR area are shown on the following pages.
Below is the structure diagram for all registers.
XXX register (address XX16)
0
1
2
3
4
5
6
7
• • • select bit
• • • select bit
• • • flag
Fix this bit to “0.”
This bit is invalid in … mode.
Nothing is assigned.
The value is “0” at reading.
b7 b6 b5 b4 b3 b2 b1 b0
0 : …
1 : …
0 : …
1 : …
The value is “0” at reading.
0X
0 0 : …
0 1 : …
1 0 : …
1 1 : …
b2 b1
123
5
Undefined
0
0
0
0
0
Undefined
0
6
WO
RW
RW
RO
RW
RW
1Blank : Set to “0” or “1” according to the usage.
0 : Set to “0” at writing.
1 : Set to “1” at writing.
: Invalid depending on the mode or state. It may be “0” or “1.”
: Nothing is assigned.
20 : “0” immediately after reset.
1 : “1” immediately after reset.
Undefined : Undefined immediately after reset.
3RW : It is possible to read the bit state at reading. The written value becomes valid.
RO : It is possible to read the bit state at reading. The written value becomes
invalid. Accordingly, the written
value may be “0” or “1.”
WO : The written value becomes valid. It is impossible to read the bit state. The value is undefined at reading.
However, when [“0” at reading”] is indicated in the “Function” or “Note” column, the bit is always “0” at
reading. (See5 above.)
: It is impossible to read the bit state. The value is undefined at reading.
However, when [“0” at reading”] is indicated in the “Function” or “Note” column, the bit is always “0” at
reading. (See6 above.)
The written value becomes invalid. Accordingly, the written value may be “0” or “1.”
4Reference page for each bit.
Bit nameBit Function At reset R/W
4
Reference
3-10
3-11
2-6
7902 Group User’s Manual 21-9
APPENDIX
Appendix 2. Control registers
RW
RW
RW
RW
RW
RW
RW
RW
Bit nameBit
0
1
2
3
4
5
6
7
Port Pi register (i = 0 to 8, 10, 11)
(Addresses 216, 316, 616, 716, A16, B16, E16, F16, 1216, 1616, 1716)
Funtion At reset R/W
Pin port Pi0
Pin port Pi1
Pin port Pi2
Pin port Pi3
Pin port Pi4
Pin port Pi5
Pin port Pi6
Pin port Pi7
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
b7 b6 b5 b4 b3 b2 b1 b0
Note: Nothing is assigned for bits 4 to 7 of the port P3 register. These bits are “0” at reading.
Data is input from or output to a pin by reading from
or writing to the corresponding bit.
0 : “L” level
1 : “H” level
Reference
6-4
0
1
2
3
4
5
6
7
Port Pi direction register (i = 0 to 8, 10, 11)
(Addresses 416, 516, 816, 916, C16, D16, 1016, 1116, 1416, 1816, 1916)
Port Pi0 direction bit
Port Pi1 direction bit
Port Pi2 direction bit
Port Pi3 direction bit
Port Pi4 direction bit
Port Pi5 direction bit
Port Pi6 direction bit
Port Pi7 direction bit
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
b7 b6 b5 b4 b3 b2 b1 b0
Note: Nothing is assigned for bits 4 to 7 of the port P3 direction register. These bits are “0” at reading.
0 : Input mode
(The port functions as an input port)
1 : Output mode
(The port functions as an output port)
Bit nameBit Function At reset R/W
Reference
6-3
Port
P5
8-6
9-8
11-6
Port
P6
7-19
9-8
10-6
Port
P7
7-19
13-10
Port
P8
7-19
12-18
7902 Group User’s Manual
APPENDIX
21-10
Appendix 2. Control registers
Undefined
Undefined
Undefined
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
(Note 7)
RW
Notes 1: These bits are invalid in the single sweep and repeat sweep modes. (They may be either “0” or “1.”)
2: When using pin AN4, be sure that the pin INT3 select bit (bit 5 at address 9416) = “0.”
3: When using pin AN5, be sure that the pin INT4 select bit (bit 6 at address 9416) = “0.”
4: When using pin AN6, be sure that the D-A0 output enable bit (bit 0 at address 9616) = “0” (output disabled).
5: When using pin AN7, be sure that the pin INT 2 select bit (bit 4 at address 9416) = “0” and the D-A1 output enable bit (bit 1
at address 9616) = “0.” When using an external trigger, pin AN7 cannot be used as an analog input pin.
6: When using an external trigger, be sure that the pin INT2 select bit (bit 4 at address 9416) = “0” and the D-A1 output enable
bit (bit 1 at address 9616) = “0.”
7: When writing to this bit, use the MOVM (MOVMB) or STA (STAB, STAD) instruction.
8: Writing to each bit (except bit 6) of the A-D control register 0 must be performed while the A-D converter halts.
0
1
2
3
4
5
6
7
A-D control register 0 (Address 1E16)
Analog input select bits
(Valid in the one-shot and repeat
modes.) (Note 1)
A-D operation mode select bits
Trigger select bit
A-D conversion start bit
A-D conversion frequency (
φ
AD)
select bit 0
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 : AN0 is selected.
0 0 1 : AN1 is selected.
0 1 0 : AN2 is selected.
0 1 1 : AN3 is selected.
1 0 0 : AN4 is selected. (Note 2)
1 0 1 : AN5 is selected. (Note 3)
1 1 0 : AN6 is selected. (Note 4)
1 1 1 : AN7 is selected. (Note 5)
b2 b1b0
0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode
b4 b3
0 : Internal trigger
1 : External trigger
(Note 6)
0 : A-D conversion halts.
1 : A-D conversion starts.
See Table 13.2.1.
Bit nameBit Function At reset R/W
Reference
13-6
7902 Group User’s Manual 21-11
APPENDIX
Appendix 2. Control registers
0
1
2
3
4
5
6
7
Reference
13-6
13-7
13-7
14-4
17-9
1
1
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
A-D control register 1 (Address 1F16)
A-D sweep pin select bits
(Valid in the single sweep and repeat
sweep modes.) (Note 1)
Fix this bit to “0.”
Resolution select bit
A-D conversion frequency (
φ
AD) select
bit 1
External trigger polarity select bit
(Valid when external trigger selected.)
VREF connection select bit (Note 6)
The value is “0” at reading.
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : Pins AN0 and AN1 (2 pins)
0 1 : Pins AN0 to AN3 (4 pins)
1 0 : Pins AN0 to AN5 (6 pins) (Notes 2, 3)
1 1 : Pins AN0 to AN7 (8 pins) (Notes 2 to 5)
b1 b0
0 : 8-bit resolution mode
1 : 10-bit resolution mode
See Table 13.2.1.
0
0 : Falling edge of the pin ADTRG’s input signal
1 : Rising edge of the pin ADTRG’s input signal
0 : Pin VREF is connected.
1 : Pin VREF is disconnected.
Bit nameBit Function At reset R/W
Notes 1: These bits are invalid in the one-shot and repeat modes. (They may be either “0” or “1.”)
2: When using pin AN4, be sure that the pin INT3 select bit (bit 5 at address 9416) = “0.”
3: When using pin AN5, be sure that the pin INT4 select bit (bit 6 at address 9416) = “0.”
4: When using pin AN6, be sure that the D-A0 output enable bit (bit 0 at address 9616) = “0” (output disabled).
5: When using pin AN7, be sure that the pin INT 2 select bit (bit 4 at address 9416) = “0” and the D-A1 output enable bit (bit 1
at address 9616) = “0.” When an external trigger is selected, pin AN7 cannot be used as an analog input pin.
6: When this bit is cleared from “1” to “0,” be sure to start the A-D conversion or D-A conversion after an interval of 1 µs or
more has elapsed.
7: Writing to each bit of the A-D control register 1 must be performed while the A-D conversion halts.
7902 Group User’s Manual
APPENDIX
21-12
Appendix 2. Control registers
Undefined
0
RO
Bit
7 to 0
15 to 8
Function At reset R/W
Reads an A-D conversion result.
The value is “0” at reading.
b0b7
A-D register 0 (Addresses 2116, 2016)
A-D register 1 (Addresses 2316, 2216)
A-D register 2 (Addresses 2516, 2416)
A-D register 3 (Addresses 2716, 2616)
A-D register 4 (Addresses 2916, 2816)
A-D register 5 (Addresses 2B16, 2A16)
A-D register 6 (Addresses 2D16, 2C16)
A-D register 7 (Addresses 2F16, 2E16)
b0
b7
(b15) (b8)
When 8-bit resolution mode is selected
A-D register 0 (Addresses 2116, 2016)
A-D register 1 (Addresses 2316, 2216)
A-D register 2 (Addresses 2516, 2416)
A-D register 3 (Addresses 2716, 2616)
A-D register 4 (Addresses 2916, 2816)
A-D register 5 (Addresses 2B16, 2A16)
A-D register 6 (Addresses 2D16, 2C16)
A-D register 7 (Addresses 2F16, 2E16)
When 10-bit resolution mode is selected
Undefined
0
RO
9 to 0
15 to 10
Reads an A-D conversion result.
The value is “0” at reading.
b0b7
b0
b7
(b15) (b8)
Bit Function At reset R/W
Reference
13-8
Reference
13-8
7902 Group User’s Manual 21-13
APPENDIX
Appendix 2. Control registers
8 to 0
15 to 9
Reference
12-5
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
UART0 transmit/receive mode register (Address 3016)
UART1 transmit/receive mode register (Address 3816)
Serial I/O mode select bits
Internal/External clock select bit
Stop bit length select bit
(Valid in UART mode) (Note)
Odd/Even parity select bit
(Valid in UART mode when parity
enable bit = “1.”) (Note)
Parity enable bit
(Valid in UART mode) (Note)
Sleep select bit
(Valid in UART mode) (Note)
RW
RW
RW
RW
RW
RW
RW
RW
b7 b6 b5 b4 b3 b2 b1 b0
Note: Bits 4 to 6 are invalid in the clock synchronous serial I/O mode. (They may be either “0” or “1.”) Additionally, fix bit 7 to “0.”
0 0 0 : Serial I/O is invalid.
(P8 functions as programmable I/O port pins.)
0 0 1 : Clock synchronous serial I/O mode
0 1 0 :
0 1 1 :
1 0 0 : UART mode (Transfer data length = 7 bits)
1 0 1 : UART mode (Transfer data length = 8 bits)
1 1 0 : UART mode (Transfer data length = 9 bits)
1 1 1 : Do not select.
b2 b1b0
0 : Internal clock
1 : External clock
0 : One stop bit
1 : Two stop bits
0 : Odd parity
1 : Even parity
0 : Parity disabled
1 : Parity enabled
0 : Sleep mode terminated (Invalid)
1 : Sleep mode selected
Do not select.
Bit nameBit Function At reset R/W
Undefined
7 to 0
UART0 baud rate register (BRG0) (Address 3116)
UART1 baud rate register (BRG1) (Address 3916)
Can be set to “0016” to “FF16.”
Assuming that the set value = n, BRGi divides the count source frequency by (n + 1). WO
b0
Note: Writing to this register must be performed while the transmission/reception halts.
Use the MOVM (MOVMB) or STA (STAB, STAD) instruction for writing to this register.
b7
Bit Function At reset R/W
UART0 transmit buffer register (Addresses
33
16
, 32
16
)
UART1 transmit buffer register (Addresses
3B
16
, 3A
16
)
b0
Note: Use the MOVM (MOVMB) or STA (STAB, STAD) instruction for writing to this register.
b7b0b7
(b15) (b8)
Transmit data is set.
Nothing is assigned.
Undefined
Undefined
WO
Bit Function At reset R/W
Reference
12-14
Reference
12-11
7902 Group User’s Manual
APPENDIX
21-14
Appendix 2. Control registers
UART0 transmit/receive control register 0 (Address 3416)
UART1 transmit/receive control register 0 (Address 3C16)
0
1
2
3
4
5
6
7
BRG count source select bits
CTS/RTS function select bit
(Note 1)
Transmit register empty flag
CTS/RTS enable bit
UARTi receive interrupt mode
select bit
CLK polarity select bit
(This bit is used in the clock
synchronous serial I/O mode.)
(Note 2)
Transfer format select bit
(This bit is used in the clock
synchronous serial I/O mode.)
(Note 2)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : Clock f2
0 1 : Clock f16
1 0 : Clock f64
1 1 : Clock f512
0 : The CTS function is selected.
1 : The RTS function is selected.
0 : Data is present in the transmit register.
(Transmission is in progress.)
1 : No data is present in the transmit register.
(Transmission is completed.)
0 : The CTS/RTS function is enabled.
1 : The CTS/RTS function is disabled.
0 : Reception interrupt
1 : Reception error interrupt
0 : At the falling edge of the transfer clock, transmit
data is output; at the rising edge of the transfer
clock, receive data is input.
When not in transferring, pin CLKi’s level is “H.”
1 : At the falling edge of the transfer clock, transmit
data is output; at the falling edge of the transfer
clock, receive data is input.
When not in transferring, pin CLKi’s level is “L.”
0 : LSB (Least Significant Bit) first
1 : MSB (Most Significant Bit) first
b1 b0
Notes 1: Valid when the CTS/RTS enable bit (bit 4) is “0” and CTSi/RTSi separate select bit (bit 0 or 1 at address AC16) is “0.”
2: Fix these bits to “0” in the UART mode or when serial I/O is disabled.
0
0
0
1
0
0
0
0
RW
RW
RW
RO
RW
RW
RW
RW
Bit nameBit Function At reset R/W
UART0 transmit/receive control register 1 (Address 3516)
UART1 transmit/receive control register 1 (Address 3D16)
0
1
2
3
4
5
6
7
Transmit enable bit
Transmit buffer empty flag
Receive enable bit
Receive complete flag
Overrun error flag
Framing error flag (Note)
(Valid in UART mode)
Parity error flag (Note)
(Valid in UART mode)
Error sum flag (Note)
(Valid in UART mode)
b7 b6 b5 b4 b3 b2 b1 b0
0 : Reception disabled
1 : Reception enabled
0 : No data is present in the receive buffer register
1 : Data is present in the receive buffer register
Note: Bits 5 to 7 are invalid in the clock synchronous serial I/O mode.
0 : Transmission disabled
1 : Transmission enabled
0 : Data is present in the transmit buffer register
1 : No data is present in the transmit buffer register
0 : No parity error
1 : Parity error detected
0 : No error
1 : Error detected
0 : No overrun error
1 : Overrun error detected
0 : No framing error
1 : Framing error detected
0
1
0
0
0
0
0
0
RW
RO
RW
RO
RO
RO
RO
RO
Bit nameBit Function At reset R/W
Reference
12-7
Reference
12-9
7902 Group User’s Manual 21-15
APPENDIX
Appendix 2. Control registers
0
1
2
3
4
6, 5
7
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
Count start register (Address 4016)
Timer A0 count start bit
Timer A1 count start bit
Timer A2 count start bit
Timer A3 count start bit
Timer A4 count start bit
Timer B0 count start bit
Timer B1 count start bit
Timer B2 count start bit
RW
RW
RW
RW
RW
RW
RW
RW
b7 b6 b5 b4 b3 b2 b1 b0
0 : Stop counting
1 : Start counting
Bit nameBit Function At reset R/W
WO
WO
WO
WO
WO
RW
0
0
0
0
0
Undefined
0
One-shot start register (Address 4216)b7 b6 b5 b4 b3 b2 b1 b0
1 : Start outputting one-shot pulse.
(Valid when an internal trigger is selected.)
The value is “0” at reading.
0
Timer A0 one-shot start bit
Timer A1 one-shot start bit
Timer A2 one-shot start bit
Timer A3 one-shot start bit
Timer A4 one-shot start bit
Nothing is assigned.
Fix this bit to “0.”
Bit nameBit Function At reset R/W
b7 b6 b5 b4 b3 b2 b1 b0
0
1
2
3
4
5
6
7
Up-down register (Address 4416)
Timer A0 up-down bit
Timer A1 up-down bit
Timer A2 up-down bit
Timer A3 up-down bit
Timer A4 up-down bit
Timer A2 two-phase pulse signal
processing select bit
Timer A3 two-phase pulse signal
processing select bit
Timer A4 two-phase pulse signal
processing select bit
0 : Countdown
1 : Countup
This function is valid when the contents of the up-
down register is selected as the up-down switching
factor.
0 : Two-phase pulse signal processing function disabled
1 : Two-phase pulse signal processing function enabled
When not using the two-phase pulse signal processing
function, clear the bit to “0.”
The value is “0” at reading.
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
WO
(Note)
WO
(Note)
WO
(Note)
Note: Use the MOVM(MOVMB) or STA(STAB, STAD) instruction for writing to bits 5 to 7.
Bit nameBit Function At reset R/W
Reference
9-6
10-4
Reference
9-22
9-23
Reference
9-30
8 to 0
15 to 9
UART0 transmit buffer register (Addresses
37
16
, 36
16
)
UART1 transmit buffer register (Addresses
3F
16
, 3E
16
)
b0b7b0b7
(b15) (b8)
Receive data is read out from here.
The value is “0” at reading.
Undefined
0
RO
Bit Function At reset R/W
Reference
12-13
7902 Group User’s Manual
APPENDIX
21-16
Appendix 2. Control registers
0
1
7 to 2
Timer A clock division select register (Address 4516)
Timer A clock division select bits
The value is “0” at reading.
0
0
0
RW
RW
b7 b6 b5 b4 b3 b2 b1 b0
See Table 9.2.3.
Bit nameBit Function At reset R/W
Timer A0 register (Addresses 4716, 4616)
Timer A1 register (Addresses 4916, 4816)
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
Undefined
15 to 0 These bits have different functions according to the operating mode. RW
b0b7
b0b7
(b15) (b8)
Note: Reading from or writing to this register must be performed in a unit of 16 bits.
Bit Function At reset R/W
Operating mode select bits
These bits have different functions according to the operating mode.
0
1
2
3
4
5
6
7
Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16)b7 b6 b5 b4 b3 b2 b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot pulse mode
1 1 : Pulse width modulation (PWM) mode.
b1 b0 0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
Bit nameBit Function At reset R/W
Reference
9-5
Reference
9-4
Reference
9-6
7902 Group User’s Manual 21-17
APPENDIX
Appendix 2. Control registers
0
1
2
3
4
5
6
7
Timer A0 register (Addresses 4716, 4616)
Timer A1 register (Addresses 4916, 4816)
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
Undefined
15 to 0 These bits to can be set to “000016” to “FFFF16.”
Assuming that the set value = n, the counter divides the count source frequency by (n + 1).
When reading, the register indicates the counter value.
RW
b0
b7
b0b7
(b15) (b8)
Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16)
Operating mode select bits
Pulse output function select bit
Gate function select bits
Fix this bit to “0” in timer mode.
Count source select bits
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : Timer mode
b1 b0
00
0 0 : No gate function
0 1 : (TAiIN pin functions as a programmable I/O
port pin.)
1 0 : Gate function
(Counter counts only while TAiIN pin’s input
signal is at “L” level.)
1 1 : Gate function
(Counter counts only while TAiIN pin’s input
signal is at “H” level.)
b4 b3
0 : No pulse output
(TAiOUT pin functions as a programmable I/O port
pin.)
1 : Pulse output
(TAiOUT pin functions as a pulse output pin.) (Note)
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
See Table 9.2.3.
0
Note: Reading from or writing to this register must be performed in a unit of 16 bits.
Bit nameBit Function At reset R/W
Bit Function At reset R/W
Note: In order to make the TA2OUT and TA3OUT pins serve as pulse output pins, be sure not to select the key input
interrupt pins (KI0 and KI2 pins), which are multiplexed with the above pins. (Refer to “CHAPTER 8. KEY INPUT
INTERRUPT.”)
Timer mode
Reference
9-10
Reference
9-10
9-14
9-13
9-5
7902 Group User’s Manual
APPENDIX
21-18
Appendix 2. Control registers
0
1
2
3
4
5
6
7
Event counter mode
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
15 to 0 RW
b0b7
Timer A0 register (Addresses 4716, 4616)
Timer A1 register (Addresses 4916, 4816)
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
b0
b7
(b15) (b8)
Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16)
Operating mode select bits
Pulse output function select bit
Count polarity select bit
Up-down switching factor select
bit
Fix this bit to “0” in event counter mode.
These bits are invalid in event counter mode.
b7 b6 b5 b4 b3 b2 b1 b0
0 1 : Event counter mode
b1 b0
01
0 : No pulse output (TAiOUT pin functions as a
programmable I/O port pin.)
1 : Pulse output (TAiOUT pin functions as a pulse
output pin.) (Note)
X : It may be either “0” or “1.”
Note: In order to make the TA2OUT and TA3OUT pins serve as pulse output pins, be sure not to select the key input
interrupt pins (KI0 and KI2 pins), which are multiplexed with the above pins. (Refer to “CHAPTER 8. KEY INPUT
INTERRUPT.”)
XX0
0 : Counts at falling edge of external signal
1 : Counts at rising edge of external signal
0 : Contents of up-down register
1 : Input signal to TAiOUT pin
Bit Function At reset R/W
Bit nameBit Function At reset R/W
Undefined
These bits to can be set to “000016” to “FFFF16.”
Assuming that the set value = n, the counter divides the count source frequency by (n + 1)
during countdown, or by (FFFF16 – n + 1) during countup.
When reading, the register indicates the counter value.
Note: Reading from or writing to this register must be performed in a unit of 16 bits.
Reference
9-18
Reference
9-18
9-23
9-18
9-22
7902 Group User’s Manual 21-19
APPENDIX
Appendix 2. Control registers
0
1
2
3
4
5
6
7
One-shot pulse mode
RW
RW
RW
RW
RW
RW
RW
RW
Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16)
Operating mode select bits
Fix this bit to “1” in one-shot pulse mode.
Trigger select bits
Fix this bit to “0” in one-shot pulse mode.
Count source select bits
b7 b6 b5 b4 b3 b2 b1 b0
1 0 : One-shot pulse mode
b1 b0
10
0
0 0 : Writing “1” to one-shot start bit
0 1 : (TAiIN pin functions as a programmable I/O
port pin.)
1 0 : Falling edge of TAiIN pin’s input signal
1 1 : Rising edge of TAiIN pin’s input signal
b4 b3
1
0
0
0
0
0
0
0
0
See Table 9.2.3.
Undefined
15 to 0 These bits can be set to “000016” to “FFFF16.”
Assuming that the set value = n, the “H” level width of the one-shot pulse which is
output from the TAiOUT pin is expressed as follows :
WO
b0
b7
Timer A0 register (Addresses 4716, 4616)
Timer A1 register (Addresses 4916, 4816)
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
b0b7
(b15) (b8)
fi: Frequency of count source
Note: Use the MOVM or STA(STAD) instruction for writing to this register.
Writing to this register must be performed in a unit of 16 bits.
n
fi.
Bit Function At reset R/W
Bit nameBit Function At reset R/W
Reference
9-27
Reference
9-27
9-30
9-5
7902 Group User’s Manual
APPENDIX
21-20
Appendix 2. Control registers
RW
RW
RW
RW
RW
RW
RW
RW
Pulse width modulator (PWM) mode
0
1
2
3
4
5
6
7
Timer Ai mode register (i = 0 to 4) (Addresses 5616 to 5A16)
Operating mode select bits
Fix this bit to “1” in PWM mode.
Trigger select bits
16/8-bit PWM mode select bit
Count source select bits
b7 b6 b5 b4 b3 b2 b1 b0
1 1 : PWM mode
b1 b0
11
0 0 : Writing “1” to count start bit
0 1 : (TAiIN pin functions as a programmable I/O
port pin.)
1 0 : Falling edge of TAiIN pin’s input signal
1 1 : Rising edge of TAiIN pin’s input signal
b4 b3
1
0 : 16-bit pulse width modulator
1 : 8-bit pulse width modulator
0
0
0
0
0
0
0
0
See Table 9.2.3.
Timer A0 register (Addresses 4716, 4616)
Timer A1 register (Addresses 4916, 4816)
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
Undefined
15 to 0 These bits can be set to “000016” to “FFFE16.”
Assuming that the set value = n, the “H” level width of the PWM pulse which is output
from the TAiOUT pin is expressed as follows :
(PWM pulse period = )
WO
b0b7b0b7
(b15) (b8)
fi: Frequency of count source
Note: Use the MOVM or STA(STAD) instruction for writing to this register.
Writing to this register must be performed in a unit of 16 bits.
n
fi
216–1
fi
<When operating as a 16-bit pulse width modulator>
Timer A0 register (Addresses 4716, 4616)
Timer A1 register (Addresses 4916, 4816)
Timer A2 register (Addresses 4B16, 4A16)
Timer A3 register (Addresses 4D16, 4C16)
Timer A4 register (Addresses 4F16, 4E16)
Undefined
Undefined
7 to 0
15 to 8
These bits can be set to “0016” to “FF16.”
Assuming that the set value = m, the period of the PWM pulse which is output from the
TAiOUT pin is expressed as follows:
WO
WO
b0b7b0b7
(b15) (b8)
(m + 1) (28 – 1)
fi
<When operating as an 8-bit pulse width modulator>
These bits can be set to “0016” to “FF16.”
Assuming that the set value = n, the “H” level width of the PWM pulse which is output
from the TAiOUT pin is expressed as follows: n(m + 1)
fi
fi: Frequency of count source
Note: Use the MOVM or STA(STAD) instruction for writing to this register.
Writing to this register must be performed in a unit of 16 bits.
Bit Function At reset R/W
Bit nameBit Function At reset R/W
Bit Function At reset R/W
Reference
9-35
Reference
9-35
9-38
9-39
9-5
Reference
9-35
7902 Group User’s Manual 21-21
APPENDIX
Appendix 2. Control registers
0
1
2
3
4
5
6
7
Reference
10-3
Reference
10-4
Undefined
15 to 0 These bits have different functions according to the operating mode. RW
b0b7b0b7
(b15) (b8)
Timer B0 register (Addresses 5116, 5016)
Timer B1 register (Addresses 5316, 5216)
Timer B2 register (Addresses 5516, 5416)
Note: Reading from or writing to this register must be performed in a unit of 16 bits.
Bit Function At reset R/W
Operating mode select bits
These bits have different functions according to the operating mode.
Nothing is assigned.
These bits have different functions according to the operating mode.
Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16)b7 b6 b5 b4 b3 b2 b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : Pulse period/Pulse width measurement mode
1 1 : Do not select.
b1 b0
Note: Bit 5 is invalid in the timer and event counter modes; its value is undefined at reading.
0
0
0
0
Undefined
Undefined
0
0
RW
RW
RW
RW
RO
(Note)
RW
RW
Bit nameBit Function At reset R/W
7902 Group User’s Manual
APPENDIX
21-22
Appendix 2. Control registers
0
1
2
3
4
5
6
7
Timer mode
Operating mode select bits
These bits are invalid in timer mode.
Nothing is assigned.
This bit is invalid in timer mode; its value is undefined at reading.
Count source select bits
Undefined
15 to 0 These bits can be set to “000016” to “FFFF16.”
Assuming that the set value = n, the counter divides the count source frequency by (n + 1).
When reading, the register indicates the counter value.
RW
b0b7b0b7
(b15) (b8)
Timer B0 register (Addresses 5116, 5016)
Timer B1 register (Addresses 5316, 5216)
Timer B2 register (Addresses 5516, 5416)
Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16)b7 b6 b5 b4 b3 b2 b1 b0
0 0 : Timer mode
b1 b0
00
0 0 : f2
0 1 : f16
1 0 : f64
1 1 : f512
b7 b6
X : It may be either “0” or “1.”
XXX
0
0
0
0
Undefined
Undefined
0
0
RW
RW
RW
RW
RO
RW
RW
Note: Reading from or writing to this register must be performed in a unit of 16 bits.
Bit Function At reset R/W
Bit nameBit Function At reset R/W
Reference
10-8
Reference
10-8
10-6
7902 Group User’s Manual 21-23
APPENDIX
Appendix 2. Control registers
0
1
2
3
4
5
6
7
Event counter mode
Operating mode select bits
Count polarity select bits
Nothing is assigned.
This bit is invalid in event counter mode; its value is undefined at reading.
These bits are invalid in event counter mode.
RW
RW
RW
RW
RO
RW
RW
Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16)b7 b6 b5 b4 b3 b2 b1 b0
0 1 : Event counter mode
b1 b0
01
0 0 : Count at falling edge of external signal
0 1 : Count at rising edge of external signal
1 0 : Count at both falling and rising edges of external
signal
1 1 : Do not select. (Note)
b3 b2
X : It may be either “0” or “1.”
Note: When the timer B2 clock source select bit (bit 6 at address 63 16) = “1,” be sure to fix these bits to “012” (count at the rising
edge of the external signal).
XXX
0
0
0
0
Undefined
Undefined
0
0
Bit nameBit Function At reset R/W
Undefined
15 to 0 These bits can be set to “000016” to “FFFF16.”
Assuming that the set value = n, the counter divides the count source frequency by (n + 1).
When reading, the register indicates the counter value.
RW
b0b7
b0b7
(b15) (b8)
Timer B0 register (Addresses 5116, 5016)
Timer B1 register (Addresses 5316, 5216)
Timer B2 register (Addresses 5516, 5416)
Note: Reading from or writing to this register must be performed in a unit of 16 bits.
Bit Function At reset R/W
Reference
10-13
Reference
10-13
7902 Group User’s Manual
APPENDIX
21-24
Appendix 2. Control registers
0
1
2
3
4
5
6
7
Pulse period/Pulse width measurement mode
Note: Reading from this register must be performed in a unit of 16 bits.
Undefined
15 to 0 The measurement result of pulse period or pulse width is read out. RO
Timer B0 register (Addresses 5116, 5016)
Timer B1 register (Addresses 5316, 5216)
Timer B2 register (Addresses 5516, 5416)
Timer Bi mode register (i = 0 to 2) (Addresses 5B16 to 5D16)
Operating mode select bits
Measurement mode select bits
Nothing is assigned.
Timer Bi overflow flag (Note)
Count source select bits
b7 b6 b5 b4 b3 b2 b1 b0
1 0 : Pulse period/Pulse width measurement mode
b1 b0
10
0 0 : Pulse period measurement
(Interval between falling edges of measurement pulse)
0 1 : Pulse period measurement
(Interval between rising edges of measurement pulse)
1 0 : Pulse width measurement
(Interval from a falling edge to a rising edge, and from
a rising edge to a falling edge of measurement pulse)
1 1 : Do not select.
b3 b2
0 0 : f2
0 1 : f16
1 0 : f64
1 1 : f512
b7 b6
Note: The timer Bi overflow flag is cleared to “0” when a value is written to the timer Bi mode register with the count start bit = “1.”
This flag cannot be set to “1” by software.
0 : No overflow
1 : Overflowed
0
0
0
0
Undefined
Undefined
0
0
RW
RW
RW
RW
RO
RW
RW
b0b7b0b7
(b15) (b8)
Bit Function At reset R/W
Bit nameBit Function At reset R/W
Reference
10-19
Reference
10-19
10-21
10-21
10-6
7902 Group User’s Manual 21-25
APPENDIX
Appendix 2. Control registers
0
1
2
3
4
5
6
7
Bit nameBit
Processor mode register 0 (Address 5E16)
Function
At reset
R/W
Processor mode bits
External bus cycle select bit 0
(Note 2)
Interrupt priority detection time
select bits
Software reset bit
Clock φ1 output select bit
b7 b6 b5 b4 b3 b2 b1 b0
Notes 1: When the Vss-level voltage is applied to pin MD0, this bit is “0”; when the Vcc-level voltage is applied to pin MD0, this bit
is “1.” (Fixed to “1.”)
2: These bits are valid for the external area except for area CSi. Regardless of these bits’ contents, the bus cycle of area CS i
is decided by the corresponding area CSi bus cycle select bits 0, 1 (bits 0, 1 at addresses 8016, 8216, 8416, 86 16, and bit 3
at addresses 8116, 8316, 8516, 8716).
3: When the Vss-level voltage is applied to pin MD0, this bit is “0”; when the Vcc-level voltage is applied to pin MD0, this bit
is “1.”
0 0 : Single-chip mode
0 1 : Memory expansion mode
1 0 : Microprocessor mode
1 1 : Do not select.
b1 b0
0 0 : 7 cycles of fsys
0 1 : 4 cycles of fsys
1 0 : 2 cycles of fsys
1 1 : Do not select.
b5 b4
The microcomputer is reset by writing “1” to this
bit. The value is “0” at reading.
0 : φ1 output is disabled. (P41 functions as a
programmable I/O port pin.)
1 : φ1 output is enabled. (P41 functions as a clock φ1
output pin.)
0
(Note 1)
0
1
0
0
0
(Note 3)
RW
RW
RW
RW
RW
RW
WO
RW
0 0 :
1φ + 1φ
0 1 :
1φ + 2φ
1 0 :
1φ + 3φ
1 1 :
2φ + 2φ
b2b3 0 0 :
2φ + 3φ
0 1 :
2φ + 4φ
1 0 :
3φ + 3φ
1 1 :
3φ + 4φ
b2b3
(External bus cycle select
bit 1 = 0) (External bus cycle select
bit 1 = 1)
Reference
2-25
3-8
7-13
4-3
3-5
7902 Group User’s Manual
APPENDIX
21-26
Appendix 2. Control registers
0
1
2
3
4
5
6
7
RW
RW
RW
RW
RW
RW
RW
RW
0
0
(Note 4)
(Note 4)
(Note 4)
(Note 4)
0
0
Processor mode register 1 (Address 5F16)
Bit nameBit Function
At reset
R/W
b7 b6 b5 b4 b3 b2 b1 b0
0 : Only DPR0 is used.
1 : DPR0 through DPR3 are used.
0 : RDY input is disabled.
(P30 functions as a programmable I/O port pin.)
1 : RDY input is enabled. (P30 functions as pin RDY.)
0 : ALE output is disabled.
(P40 functions as a programmable I/O port pin.)
1 : ALE output is enabled. (P40 functions as pin ALE.)
0 : No recovery cycle is inserted at access to external area.
1 : Recovery cycle is inserted at access to external area.
0 : HOLD input and HLDA output are disabled.
(P4 3 and P42 function as programmable I/O port pins.)
1 : HOLD input and HLDA output are enabled.
(P4 3 and P42 function as pins HOLD and HLDA.)
0 : 1 cycle
1 : 2 cycles
0 : 3φ
1 : 2φ
(Note 5)
(Note 5)
The combination of this bit and the external bus cycle
select bit 0 selects the bus cycle.
0 : 1φ + 1φ, 1φ + 2φ, 1φ + 3φ, or 2φ + 2φ
1 : 2φ + 3φ, 2φ + 4φ, 3φ + 3φ, or 3φ + 4φ
(Note 2)
External bus cycle select bit 1
(Note 1)
Direct page register switch bit
RDY input select bit (Note 3)
ALE output select bit (Note 3)
Recovery cycle insert select bit
(Note 3)
HOLD input, HLDA output select
bit (Note 3)
Recovery-cycle-insert number
select bit (Note 6)
Internal ROM bus cycle select bit
(Note 7)
Notes 1: This bit is valid for the external area except for area CSi. Regardless of these bits’ contents, the bus cycle of area CSi is
decided by the corresponding area CSi bus cycle select bits 0, 1 (bits 0, 1 at addresses 8016, 8216, 8416, 8616, and bit 3 at
addresses 8116, 8316, 8516, 8716).
2: After reset, this bit can be set only once. (During the software execution, be sure not to change this bit’s contents.)
3: In the single-chip mode, all of these bits’ functions are disabled regardless of these bits’ contents.
4: When the Vss-level voltage is applied to pin MD0, this bit is “0”; when the Vcc-level voltage is applied to pin MD0, this bit
is “1.”
5: After reset, this bit can be set to “0” only once. Once this bit has been cleared from “1” to “0,” it cannot be back to “1”
again. (Fixed to “0.”)
6: Make sure that a program to be used to change this bit’s contents is allocated in the internal area.
7: In the microprocessor mode, this bit is invalid. This bit is not assigned to the external ROM version. (“0” at reading.)
To reprogram the internal flash memory by using the CPU reprogramming mode, clear this bit to “0.” (Refer to section
“20.2 Flash memory CPU reprogramming mode.”)
Reference
3-9
2-6
3-5
3-9
3-5
3-9
3-5
3-9
2-14
7902 Group User’s Manual 21-27
APPENDIX
Appendix 2. Control registers
0
5 to 1
6
7
Undefined
7 to 0 Initializes the watchdog timer.
When dummy data has been written to this register, the watchdog timer’s value is
initialized to “FFF16” (dummy data: 0016 to FF16).
b0
b7
Watchdog timer register (Address 6016)
Bit Function At reset R/W
RW
RW
RW
Bit nameBit
Watchdog timer frequency select register (Address 6116)
Function
At reset
R/W
Watchdog timer frequency
select bit
Nothing is assigned.
Watchdog timer clock source
select bits at STP termination
0
Undefined
0
0
b7 b6 b5 b4 b3 b2 b1 b0
0 : Wf512
1 : Wf32
0 0 : fX32
0 1 : fX16
1 0 : fX128
1 1 : fX64
b7 b6
Reference
15-3
Reference
15-3
16-7
7902 Group User’s Manual
APPENDIX
21-28
Appendix 2. Control registers
0
1
2
3
4
5
6
7
0
1
7 to 2
RW
(Note)
RW
(Note)
RW
0
0
0
Bit nameBit
Particular function select register 0 (Address 6216)
Function
At reset
R/W
STP instruction invalidity select bit
External clcok input select bit
Fix this bit to “0.”
b7 b6 b5 b4 b3 b2 b1 b0
0 : STP instruction is valid.
1 : STP instruction is invalid.
0 : Oscillation circuit is active. (Oscillator is connected.)
Watchdog timer is used at stop mode termination.
1 : Oscillation circuit is inactive. (External clock is
input.)
When the system clock select bit (bit 5 at address BC
16
) = “0,”
watchdog timer is not used at stop mode termination.
When the system clock select bit = “1,”
watchdog timer is used at stop mode termination.
000000
Note: Writing to these bits requires the following procedure:
• Write “5516” to this register. (The bit status does not change only by this writing.)
• Succeedingly, write “0” or “1” to each bit.
Also, use the MOVMB (MOVM when m = 1) instruction or STAB (STA when m = 1) instruction.
If an interrupt occurs between writing of “5516” and next writing of “0” or “1,” latter writing may be ignored. When there is a
possibility that an interrupt occurs at the above timing, be sure to read this bit’s contents after writing of “0” or “1,” and verify
whether “0” or “1” has correctly been written or not.
RW
(Note 2)
RW
(Note 2)
RW
RW
RW
RW
Notes 1: At power-on reset, this bit becomes “0.” At hardware reset or software reset, this bit retains the value just before reset.
2: Even when “1” is written, the bit status will not change.
3: Setting this bit to “1” must be performed just before execution of the WIT instruction. Also, after the wait state is termi-
nated, this bit must be cleared to “0” immediately.
(Note 1)
(Note 1)
0
0
0
0
0
0
Particular function select register 1 (Address 6316)b7 b6 b5 b4 b3 b2 b1 b0
Bit nameBit Function At reset R/W
STP-instruction-execution
status bit
WIT-instruction-execution
status bit
Standby state select bit
System clock stop select bit
at WIT (Note 3)
Address output select bit
The value is “0” at reading.
Timer B2 clock source select bit
(Valid in event counter mode.)
The value is “0” at reading.
0 : Address output changes at access to the inter-
nal area and external area.
1 : Address output changes only at access to the
external area.
0 : Normal operation.
1 : STP instruction has been executed.
0 : Normal operation.
1 : WIT instruction has been executed.
0 : External signal input to the TB2IN pin is counted.
1 : fX32 is counted.
0 : External bus
1 : Programmable I/O port
0 : In the wait mode, system clock fsys is active.
1 : In the wait mode, system clock fsys is stopped.
Reference
16-4
5-10
16-5
17-4
Reference
16-6
17-5
3-31
10-14
7902 Group User’s Manual 21-29
APPENDIX
Appendix 2. Control registers
Undefined
7 to 0
Bit Function
At reset
R/W
Disables the watchdog timer.
When values of “7916” and “5016” succeedingly in this order, the watchdog timer will
stop its operation.
b0b7
Particular function select register 2 (Address 6416)
Note: After reset, this register can be set only once. Writing to this register requires the following procedure:
• Write values of “7916” and “5016” to this register succeedingly in this order.
• For the above writing, be sure to use the MOVMB (MOVM when m = 1) instruction or the STAB (STA when m = 1).
Note that the following: if an interrupt occurs between writing of “7916” and next writing of “5016,” the watchdog timer does not
stop its operation.
If any of the following has been performed after reset, writing to this register is disabled from that time:
• If this register is read out.
• If writing to this register is performed by the procedure other than the above procedure.
Reference
15-4
7902 Group User’s Manual
APPENDIX
21-30
Appendix 2. Control registers
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Note: At power-on reset, these bits become “0”; at hardware reset or software reset, these bits retain the value immediately before reset.
Bit nameBit
Debug control register 0 (Address 6616)
Function
Detect condition select bits
Fix these bits to “0.”
Detect enable bit
Fix this bit to “0.”
The value is “1” at reading.
RW
RW
RW
RW
RW
RW
RW
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 : Do not select.
0 0 1 : Address matching detection 0
0 1 0 : Address matching detection 1
0 1 1 : Address matching detection 2
1 0 0 : Do not select.
1 0 1 : Out-of-address-area detection
1 1 0 :
1 1 1 :
b2 b1b0
0 : Detection disabled.
1 : Detection enabled.
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
1
Do not select.
000
At reset R/W
(Note 1)
(Note 1)
0
0
(Note 1)
0
0
0
RW
RO
RW
RW
RW
RO
RO
Bit nameBit
Debug control register 1 (Address 6716)
Function
At reset
R/W
Fix this bit to “0.”
The value is “0” at reading.
Address compare register
access enable bit (Note 2)
Fix this bit to “1” when using the debug function.
Fix this bit to “0.”
While a debugger is not used, the value is “0” at reading.
While a debugger is used, the value is “1” at reading.
Address-matching-detection 2
decision bit
(Valid when the address match-
ing detection 2 is selected.)
The value is “0” at reading.
00
0 : Disabled.
1 : Enabled.
0 : Matches with the contents of the address com-
pare register 0.
1 : Matches with the contents of the address com-
pare register 1.
1
Notes 1: At power-on reset, these bits become “0”; at hardware reset or software reset, these bits retain the value immediately before reset.
2: Be sure to set this bit to “1” immediately before the access to the address compare registers 0 and 1 (addresses 6816 to
6D16). Then, be sure to clear this bit to “0” immediately after this access.
b7 b6 b5 b4 b3 b2 b1 b0
Address compare register 0 (Addresses 6A16 to 6816)
Address compare register 1 (Addresses 6D16 to 6B16)
Undefined
23 to 0
Bit Function
At reset
R/W
The address to be detected (in other words, the start address of instructions) is set here. RW
b0b7 b7b0b7
(b23) (b8)(b15)(b16)
b0
Note: When accessing to these registers, be sure to set the address compare register access enable bit (bit 2 at address 67 16) to “1”
immediately before the access. Then, be sure to clear this bit to “0” immediately after this access.
Reference
18-3
Reference
18-4
Reference
18-5
7902 Group User’s Manual 21-31
APPENDIX
Appendix 2. Control registers
0
1
2
3
7 to 4
0
1
2
3
4
7 to 5
INT3, INT4 interrupt control registers (Addresses 6E16, 6F16)
Interrupt priority level select bits
Interrupt request bit
Polarity select bit
Nothing is assigned.
b7 b6 b5 b4 b3 b2 b1 b0
Note: When writing to this bit, use the MOVM (MOVMB) or STA (STAB, STAD) instruction.
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1b0
0 : No interrupt requested
1 : Interrupt requested
0 : The interrupt request bit is set to “1” at the falling
edge.
1 : The interrupt request bit is set to “1” at the rising
edge.
0
0
0
0
0
Undefined
RW
RW
RW
RW
(Note)
RW
Bit nameBit Function At reset R/W
A-D conversion, UART0 and 1 transmit, UART0 and 1 receive,
timers A0 to A4, timers B0 to B2 interrupt control registers
(Addresses 7016 to 7C16)
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt priority level select bits
Interrupt request bit
Nothing is assigned.
Notes 1: The A-D conversion interrupt request bit is undefined after reset.
2: When writing to this bit, use the MOVM (MOVMB) or STA (STAB, STAD) instruction.
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1b0
0 : No interrupt requested
1 : Interrupt requested
0
0
0
0
(Note 1)
Undefined
RW
RW
RW
RW
(Note 2)
Bit nameBit Function At reset R/W
Reference
7-8
7-9
INT3
8-5
7-19
Reference
7-8
7-9
Timer Ai
9-7
Timer Bi
10-5
UART0
UART1
12-16
A-D
13-9
7902 Group User’s Manual
APPENDIX
21-32
Appendix 2. Control registers
0
1
2
3
4
5
7, 6
INT0 to INT2 interrupt control registers (Addresses 7D16 to 7F16)
Interrupt priority level select bits
Interrupt request bit (Note 1)
Polarity select bit
Level sense/Edge sense select
bit
Nothing is assigned.
b7 b6 b5 b4 b3 b2 b1 b0
Notes 1: The interrupt request bits of INT0 to INT2 interrupts are invalid when the level sense is selected.
2: When writing to this bit, use the MOVM (MOVMB) or STA (STAB, STAD) instruction.
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1b0
0 : No interrupt requested
1 : Interrupt requested
0 : The interrupt request bit is set to “1” at “H” level
when level sense is selected; this bit is set to “1”
at falling edge when edge sense is selected.
1 : The interrupt request bit is set to “1” at “L” level
when level sense is selected; this bit is set to “1”
at rising edge when edge sense is selected.
0 : Edge sense
1 : Level sense
0
0
0
0
0
0
Undefined
RW
RW
RW
RW
(Note 2)
RW
RW
Bit nameBit Function At reset R/W
Reference
7-8
7-9
7-19
7902 Group User’s Manual 21-33
APPENDIX
Appendix 2. Control registers
0
1
2
3
6 to 4
7
0
1
2
3
4
5
6
7
CS0 control register L (Address 8016)b7 b6 b5 b4 b3 b2 b1 b0
Notes 1: This bit is “0” when Vss-level voltage is applied to pin BYTE; this bit is “1” when Vcc-level voltage is applied.
2: This bit is valid when the RDY input select bit (bit 2 at address 5F16) is “1.”
3: When Vcc-level voltage is applied to pin BYTE, “normal access” is selected regardless of this bit’s value.
4: This bit’s contents are invalid in the single-chip mode. (CS0 output disabled)
5: This bit is “0” when Vss-level voltage is applied to pin MD0; this bit is “1” when Vcc-level voltage is applied. (Fixed to “1.”)
The input level at pin BYTE is read out.
0 : 16-bit width
1 : 8-bit width
0 : RDY control is valid.
1 : RDY control is invalid.
0 : Normal access
1 : Burst ROM access
0 : No recovery cycle is inserted at access to area CS0.
1 : Recovery cycle is inserted at access to area CS0.
0 : CS0 output is disabled. (P44 functions as a
programmable I/O port pin.)
1 : CS0 output is enabled. (P44 functions as pin CS0.)
Bit nameBit Function At reset R/W
Area CS0 bus cycle select bit 0
External data bus width select bit
RDY control bit (Note 2)
The value is “0” at reading.
Burst ROM access select bit
(Note 3)
Recovery cycle insert select bit
CS0 output select bit (Note 4)
RW
RW
RO
RW
RW
RW
RW
0
1
(Note 1)
0
0
0
1
(Note 5)
0 0 :
1φ + 1φ
0 1 :
1φ + 2φ
1 0 :
1φ + 3φ
1 1 :
2φ + 2φ
b0b1 0 0 :
2φ + 3φ
0 1 :
2φ + 4φ
1 0 :
3φ + 3φ
1 1 :
3φ + 4φ
b0b1
(Area CS0 bus cycle select
bit 1 = 0) (Area CS0 bus cycle select
bit 1 = 1)
0: Mode 0 (A block can be set to 16-Mbyte space.)
1: Mode 1 (Area CS0 start address is set in bank 0.)
CS0 control register H (Address 8116)
Bit nameBit Function
At reset
R/W
Area CS0 block size select bits
Area CS0 bus cycle select bit 1
The value is “0” at reading.
Area CS0 setting mode select bit
0 0 0 : 0 byte (Area CS0 is invalid.)
0 0 1 : 128 Kbytes
0 1 0 : 256 Kbytes
0 1 1 : 512 Kbytes
1 0 0 : 1 Mbytes
1 0 1 : 2 Mbytes
1 1 0 : 4 Mbytes
1 1 1 : 8 Mbytes
b2 b1b0
b7 b6 b5 b4 b3 b2 b1 b0
1
0
0
0
0
1
RW
RW
RW
RW
RW
The combination of this bit and the area CS0 bus cycle
select bit 0 selects the bus cycle.
0 : 1φ + 1φ, 1φ + 2φ, 1φ + 3φ, or 2φ + 2φ
1 : 2φ + 3φ, 2φ + 4φ, 3φ + 3φ, or 3φ + 4φ
Reference
3-12
3-5
3-12
Reference
3-13
7902 Group User’s Manual
APPENDIX
21-34
Appendix 2. Control registers
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
CS1 control register L (Address 8216)
CS2 control register L (Address 8416)
CS3 control register L (Address 8616)
Area CSj bus cycle select bit 0
(j = 1 to 3)
External data bus width select bit
RDY control bit (Note 2)
The value is “0” at reading.
Burst ROM access select bit
(Note 3)
Recovery cycle insert select bit
CSj output select bit
(j = 1 to 3) (Note 4)
RW
RW
RW
RW
RW
RW
RW
b7 b6 b5 b4 b3 b2 b1 b0
Notes 1: This bit is fixed to “1” (8-bit width) when Vcc-level voltage is applied to pin BYTE.
2: Valid when the RDY input select bit (bit 2 at 5F16) is “1.”
3: When the external data bus width select bit (bit 2) is “1” or when Vcc-level voltage is applied to pin BYTE, “normal access”
is selected regardless of this bit’s value.
4: This bit’s value is invalid in the single-chip mode. (CSj output is disabled.)
0 : 16-bit width
1 : 8-bit width (Note 1)
0 : RDY control is valid.
1 : RDY control is invalid.
0 : Normal access
1 : Burst ROM access
0 : No recovery cycle is inserted with area CSj selected.
1 : Recovery cycle is inserted with area CSj selected.
0 : CSj output is disabled. (P45 to P4 7 function as
programmable I/O port pins.)
1 :
CS
j
output is enabled. (P4
5
to P4
7
function as pin CS
j
.)
0
1
0
0
0
0
1
0
Bit nameBit Function At reset R/W
0 0 :
1φ + 1φ
0 1 :
1φ + 2φ
1 0 :
1φ + 3φ
1 1 :
2φ + 2φ
b0b1 0 0 :
2φ + 3φ
0 1 :
2φ + 4φ
1 0 :
3φ + 3φ
1 1 :
3φ + 4φ
b0b1
(Area CSj bus cycle select
bit 1 = 0) (Area CSj bus cycle select
bit 1 = 1)
CS1 control register H (Address 8316)
Area CS1 block size select bits
Area CS1 bus cycle select bit 1
The value is “0” at reading.
Fix this bit to “0.”
The value is “0” at reading.
Area CS1 setting mode select bit
0 0 0 : 0 byte
(Area CS
1
is invalid.)
0 0 1 : 128 Kbytes
0 1 0 : 256 Kbytes
0 1 1 : 512 Kbytes
1 0 0 : 1 Mbytes
1 0 1 : 2 Mbytes
1 1 0 : 4 Mbytes
1 1 1 : 8 Mbytes
b2 b1b0
b7 b6 b5 b4 b3 b2 b1 b0
0 : Mode 0 (A block can be set to 16-Mbyte space.)
1 : Mode 1 (A block can be set to bank 0.)
(Mode 0) 0 byte
(Area CS
1
is invalid.)
Do not select.
Do not select.
Do not select.
4 Kbytes
8 Kbytes
Do not select.
Do not select.
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
Bit nameBit Function At reset R/W
(Mode 1)
The combination of this bit and the area CS1 bus
cycle select bit 0 selects the bus cycle.
0 : 1φ + 1φ, 1φ + 2φ, 1φ + 3φ, or 2φ + 2φ
1 : 2φ + 3φ, 2φ + 4φ, 3φ + 3φ, or 3φ + 4φ
0
Reference
3-15
3-5
3-15
Reference
3-16
7902 Group User’s Manual 21-35
APPENDIX
Appendix 2. Control registers
0
1
2
3
4
5
6
7
0
1
2
3
7 to 4
CS2 control register H (Address 8516)
0 0 0 : 0 byte
(Area CS
2
is invalid.)
0 0 1 : 128 Kbytes
0 1 0 : 256 Kbytes
0 1 1 : 512 Kbytes
1 0 0 : 1 Mbytes
1 0 1 : 2 Mbytes
1 1 0 : 4 Mbytes
1 1 1 : 8 Mbytes
b2 b1b0
b7 b6 b5 b4 b3 b2 b1 b0
0 : Mode 0 (A block can be set to 16-Mbyte space.)
1 : Mode 1 (A block can be set to bank 0.)
(Mode 0) 0 byte
(Area CS
2
is invalid.)
Do not select.
Do not select.
Do not select.
4 Kbytes
8 Kbytes
Do not select.
Do not select.
Bit nameBit Function At reset R/W
(Mode 1)
The combination of this bit and the area CS2 bus
cycle select bit 0 selects the bus cycle.
0 : 1φ + 1φ, 1φ + 2φ, 1φ + 3φ, or 2φ + 2φ
1 : 2φ + 3φ, 2φ + 4φ, 3φ + 3φ, or 3φ + 4φ
Area CS2 block size select bits
Area CS2 bus cycle select bit 1
The value is “0” at reading.
Multiplexed bus select bit
The value is “0” at reading.
Area CS2 setting mode select bit
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
0 : Separated bus. Input/Output for D0–D7.
1 : Multiplexed bus. LA0/D0–LA7/D7 are input/output
when the external data bus = 8 bits (bit 2 at address
8416 = 1) with area CS2 accessed.
0 0 0 : 0 byte (Area CS3 is invalid.)
0 0 1 : 128 Kbytes
0 1 0 : 256 Kbytes
0 1 1 : 512 Kbytes
1 0 0 : 1 Mbytes
1 0 1 : 2 Mbytes
1 1 0 : 4 Mbytes
1 1 1 : 8 Mbytes
b2 b1b0
CS3 control register H (Address 8716)b7 b6 b5 b4 b3 b2 b1 b0
Bit nameBit Function At reset R/W
The combination of this bit and the area CS3 bus
cycle select bit 0 selects the bus cycle.
0 : 1φ + 1φ, 1φ + 2φ, 1φ + 3φ, or 2φ + 2φ
1 : 2φ + 3φ, 2φ + 4φ, 3φ + 3φ, or 3φ + 4φ
Area CS3 block size select bits
Area CS3 bus cycle select bit 1
The value is “0” at reading.
0
0
0
0
0
RW
RW
RW
RW
Reference
3-17
Reference
3-18
7902 Group User’s Manual
APPENDIX
21-36
Appendix 2. Control registers
Bit
0
1
2
3
4
5
6
7
Area CS0 start address register (Address 8A16)
Function
At reset
R/W
Mode 0
A16–A23 of the start address are set.
Mode 1
A8–A15 of the start address are set.
Any value of 1016, 2016, 4016, and 8016 can be set.
(Bit 0 is always “0” at reading.)
0
0
0
0
1
0
0
0
RW
RW
RW
RW
RW
RW
RW
b7 b6 b5 b4 b3 b2 b1 b0
Bit
0
1
2
3
4
5
6
7
Area CS1 start address register (Address 8C16)
Area CS2 start address register (Address 8E16)
Function
At reset
R/W
Mode 0
A16–A23 of the start address are set.
Mode 1
A8–A15 of the start address are set.
(Bit 0 is always “0” at reading.)
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
Bit
0
1
2
3
4
5
6
7
Area CS3 start address register (Address 9016)
Function
At reset
R/W
A16–A23 of the start address are set.
(Bit 0 is always “0” at reading.)
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
Note: Depending on the block size, which has been selected by the area CS0 block size select bits 0 to 2 at address 8116), the start
address which can be set is changed. (See Figures 3.2.10 and 3.2.11.)
Note: Depending on the block size, which has been selected by the area CS1/CS2 block size select bits (bits 0 to 2 at address 8316/
8516), the start address which can be set is changed. (See Figures 3.2.10 and 3.2.12.)
Note: Depending on the block size, which has been selected by the area CS3 block size select bits (bits 0 to 2 at address 8716), the
start address which can be set is changed. (See Figure 3.2.10.)
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
Reference
3-18
Reference
3-18
Reference
3-18
7902 Group User’s Manual 21-37
APPENDIX
Appendix 2. Control registers
0
1
2
3
4
5
6
7
0
1
2
3
4
6, 5
7
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
Port function control register (Address 9216)b7 b6 b5 b4 b3 b2 b1 b0
Bit nameBit Function
At reset
R/W
Address/Port switch bits
Port P0 input level select bit
Pins P44–P47 pullup select bit
Fix these bit s to “0.”
Pin NMI pullup select bit
0 0 0 : A0 to A23 (16 Mbytes)
0 0 1 : A0 to A21, P06, P07 (4 Mbytes)
0 1 0 : A0 to A19, P04 to P07 (1 Mbytes)
0 1 1 : A0 to A17, P02 to P07 (256 Kbytes)
1 0 0 : A0 to A15, P00 to P07 (64 Kbytes)
1 0 1 : Do not select.
1 1 0 : A0 to A11, P00 to P07, P114 to P117 (4 Kbytes)
1 1 1 : A0 to A7, P00 to P07, P110 to P117 (256 bytes)
b2 b1b0
Notes 1: For the M37902FxMHP (power source voltage = 3.3 V±0.3 V), VIH = 0.5 VCC.
2: When MD 1 = V CC and MD 0 = VCC (flash memory parallel I/O mode), pins P 44 to P47 and NMI are not pulled up, regardless of
these bits’ contents.
3: When MD1 = VSS and MD0 = VCC (microprocessor mode), pin CS0 (P44) is not pulled up, regardless of the bits’ contents.
0 : Pins P44–P47 are pulled up.
1 : Pins P44–P47 are not pulled up (Notes 2, 3).
0 : Pin NMI is pulled up.
1 : Pin NMI is not pulled up. (Note 2)
0 : VIH = 0.7 VCC, VIL = 0.2 VCC
1 : VIH = 0.43 VCC (Note 1), VIL = 0.16 VCC
00
Notes 1: When using pin KIi, do not select timer As output pins and pulse output pins which are multiplexed with pin KIi. Refer to
“CHAPTER 9. TIMER A” and “CHAPTER 11. REAL-TIME OUTPUT.”
2: When allocating pin INT 2 to P77, do not use pin AN7/ADTRG. Additionally, clear the D-A1 output enable bit (bit 1 at address
9616) to “0” (output disabled).
3: When allocating pin INT3 to P80, clear the D-A2 output enable bit (bit 2 at address 9616) to “0” (output disabled).
When allocating pin INT3 to P74, do not use pin AN4.
4: When allocating pin INT4 to P75, do not use pin AN5.
0
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
RW
External interrupt input control register (Address 9416)b7 b6 b5 b4 b3 b2 b1 b0
Bit nameBit Function At reset R/W
Key input interrupt select bit
Key input interrupt pin pullup
select bit
Key input interrupt pin select bits
Pin INT2 select bit
Pin INT3 select bit
Pin INT4 select bit
Fix this bit to “0”.
0 : Allocate pin INT2 to P64.
1 : Allocate pin INT2 to P77.(Note 2)
0 0 : Pins KI0 to KI3
0 1 : Pins KI0 to KI2
1 0 : Pins KI0 and KI1
1 1 : Pin KI0(Note 1)
0
0 : INT3 interrupt
1 : Key input interrupt
0 : Pins KI0 to KI3 are not pulled up.
1 : Pins KI0 to KI3 are pulled up.
b3 b2
0 : Allocate pin INT3 to P80.(Note 3)
1 : Allocate pin INT3 to P74.
0 : Allocate pin INT4 to P84.(Note 4)
1 : Allocate pin INT4 to P75.
Reference
3-5
6-7
3-5
6-7
7-19
Reference
8-4
7-19
7902 Group User’s Manual
APPENDIX
21-38
Appendix 2. Control registers
0
1
2
3
4
5
7, 6
0
1
2
7 to 3
Bit nameBit Function
At reset
R/W
External interrupt input read register (Address 9516)
INT0 read out bit
INT1 read out bit
INT2 read out bit
INT3 read out bit (Note)
INT4 read out bit
NMI read out bit
The value is undefined at reading.
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
RO
RO
RO
RO
RO
RO
RO
b7 b6 b5 b4 b3 b2 b1 b0
Note : When the key input interrupt select bit (bit 0 at address 9416) = “1,” the input level at pin INT3 cannot be read out.
The input level at the corresponding pin is read out.
0 : “L” level
1 : “H” level
Bit nameBit Function
At reset
R/W
D-A0 output enable bit
D-A1 output enable bit
D-A2 output enable bit
Nothing is assigned.
b7 b6 b5 b4 b3 b2 b1 b0
0: Output is disabled.
1: Output is enabled. (Notes 1, 2)
0: Output is disabled.
1: Output is enabled. (Notes 1, 2)
0: Output is disabled.
1: Output is enabled. (Notes 1, 2)
0
0
0
RW
RW
RW
D-A control register (Address 9616)
Notes 1: Pin DAi is multiplexed with analog input pin, serial I/O pin, and external interrupt input pin. When a D-Ai output enable bit =
“1” (in other words, output is enabled.), however, the corresponding pin cannot function as any other multiplexed input/
output pin (including programmable I/O port pin).
2: When not using the D-A converter, be sure to clear the contents of this bit to “0.”
Undefined
0
7 to 0
Bit
D-A register i (i = 0 to 2) (Addresses 9816 to 9A16)
Function
At reset
R/W
Any value from 0016 through FF16 can be set (Note), and this value is D-A
converted and is output. RW
b0b7
Reference
7-19
Reference
14-3
Reference
14-3
Note: When not using the D-A converter, be sure to clear the contents of these bits to “0016.”
7902 Group User’s Manual 21-39
APPENDIX
Appendix 2. Control registers
0
1
2
3
4
5
7, 6
RY/BY status bit
CPU reprogramming mode select bit
Lock bit invalidity select bit
Flash memory reset bit (Note 5)
Fix this bit to “0.”
User ROM area select bit
(Valid in boot mode) (Note 7)
The value is “0” at reading.
RO
RW
(Notes 1, 2)
RW
(Notes 1, 4)
RW
(Note 6)
RW
RW
(Note 2)
1
0
0
0
0
0
0
0 : Lock bit is valid.
1 : Lock bit is invalid (Note 3).
Bit nameBit
Flash memory control register (Address 9E16)
Function At reset R/W
b7 b6 b5 b4 b3 b2 b1 b0
0 : BUSY (Automatic programming or erase operation
is active.)
1 : READY (Automatic programming or erase operation
has been completed.)
0 : Flash memory CPU reprogramming mode is invalid.
1 : Flash memory CPU reprogramming mode is valid.
Notes 1: In order to set this bit to “1,” write “0” followed with “1” successively; while in order to clear this bit “0,” write “0.”
2: Writing to this bit must be performed in an area other than the internal flash memory.
3: Simultaneously with the CPU reprogramming mode select bit (bit 1) cleared “0,” this bit is also cleared to “0.”
4: Only when the CPU reprogramming mode select bit (bit 1) = “1,” writing to this bit is available.
5: This bit is valid only when the CPU reprogramming mode select bit = “1”: on the other hand, when the CPU reprogra-
mming mode select bit = “0,” be sure to fix this bit to “0.”
6: After writing of “1” to this bit, be sure to write “0” successively.
7: When MD1 = Vss level, this bit is invalid. (It may be either “0” or “1.”)
0 : Access to boot ROM area
1 : Access to user ROM area
Writing “1” followed with “0” into this bit discontinues
the access to the internal flash memory. This causes
the built-in flash memory circuit being reset.
0
Reference
20-14
20-15
7902 Group User’s Manual
APPENDIX
21-40
Appendix 2. Control registers
0
1
2
7 to 3
RW
RW
RW
0
0
0
0
Bit nameBit
Real-time output control register (Address A016)
Function At reset R/W
Waveform output select bits
Pulse output mode select bit
The value is “0” at reading.
b7 b6 b5 b4 b3 b2 b1 b0
See the table below.
Note: When using pins P50 to P57 as pulse output pins of the real-time output function, be sure to set the corresponding bits of the
port P5 direction register (address D16) to “1.” When using pins RTP10 to RTP1 3, do not select the key input interrupt pins (KI 0
to KI3) multiplexed with pins RTP10 to RTP13. (Refer to “CHAPTER 8. KEY INPUT INTERRUPT.”)
0 : Pulse mode 0
1 : Pulse mode 1
b1 b0
Pulse mode 0
00
P57/RTP13
P56/RTP12
P55/RTP11
P54/RTP10
P53/RTP03
P52/RTP02
P51/RTP01
P50/RTP00
Port
01
P57/RTP13
P56/RTP12
P55/RTP11
P54/RTP10
P53/RTP03
P52/RTP02
P51/RTP01
P50/RTP00
Port
Port
RTP
10
P57/RTP13
P56/RTP12
P55/RTP11
P54/RTP10
P53/RTP03
P52/RTP02
P51/RTP01
P50/RTP00
RTP
11
P57/RTP13
P56/RTP12
P55/RTP11
P54/RTP10
P53/RTP03
P52/RTP02
P51/RTP01
P50/RTP00
Port
RTP
RTP
P57/RTP13
P56/RTP12
P55/RTP11
P54/RTP10
P53/RTP03
P52/RTP02
P51/RTP01
P50/RTP00
Port
Port
Pulse mode 1
P57/RTP13
P56/RTP12
P55/RTP11
P54/RTP10
P53/RTP03
P52/RTP02
P51/RTP01
P50/RTP00
Port
RTP
P57/RTP13
P56/RTP12
P55/RTP11
P54/RTP10
P53/RTP03
P52/RTP02
P51/RTP01
P50/RTP00Port
RTP
P57/RTP13
P56/RTP12
P55/RTP11
P54/RTP10
P53/RTP03
P52/RTP02
P51/RTP01
P50/RTP00
RTP
RTP
Port : This functions as a programmable I/O port pin.
RTP : This functions as a pulse output pin.
Reference
11-4
7902 Group User’s Manual 21-41
APPENDIX
Appendix 2. Control registers
0
1
2
3
7 to 4
WO
WO
WO
WO
Undefined
Undefined
Undefined
Undefined
Undefined
Bit nameBit
Pulse output data register 0 (Address A216)
Function At reset R/W
RTP00 pulse output data bit
RTP01 pulse output data bit
RTP02 pulse output data bit
(Valid in pulse mode 0.)
RTP03 pulse output data bit
(Valid in pulse mode 0.)
Nothing is assigned.
0 : “L” level output
1 : “H” level output
Note: When writing to this register, use the MOVM (MOVMB) instruction or STA (STAB, STAD) instruction.
Bit nameBit
1, 0
2
3
4
5
6
7
Pulse output data register 1 (Address A416)
Function At reset R/W
Nothing is assigned.
RTP02 pulse output data bit
(Valid in pulse mode 1.)
RTP03 pulse output data bit
(Valid in pulse mode 1.)
RTP10 pulse output data bit
RTP11 pulse output data bit
RTP12 pulse output data bit
RTP13 pulse output data bit
0 : “L” level output
1 : “H” level output
Note: When writing to this register, use the MOVM (MOVMB) instruction or STA (STAB, STAD) instruction.
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
WO
WO
WO
WO
WO
WO
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
Reference
11-5
Reference
11-5
7902 Group User’s Manual
APPENDIX
21-42
Appendix 2. Control registers
0
1
2
3
4
5
6
7
Serial I/O pin control register (Address AC16)b7 b6 b5 b4 b3 b2 b1 b0
0
1
2
3
7 to 4
CTS0/RTS0 separate select bit
(Note)
CTS1/RTS1 separate select bit
(Note)
TxD0/P83 switch bit
TxD1/P87 switch bit
The value is “0” at reading.
0 : CTS0/RTS0 are used together.
1 : CTS0/RTS0 are separated.
0 : Functions as TxD1.
1 : Functions as P87.
RW
RW
RW
RW
Bit nameBit Function At reset R/W
0 : CTS1/RTS1 are used together.
1 : CTS1/RTS1 are separated.
0 : Functions as TxD0.
1 : Functions as P83.
0
0
0
0
0
1
1
1
0
0
0
0
0
Clock control register (Address BC16)
Bit nameBit Function
At reset
R/W
Fix this bit to “1.”
PLL circuit operation enable bit
(Note 1)
PLL multiplication ratio select bits
(Note 2)
Fix this bit to “0.”
System clock select bit (Note 3)
Peripheral device’s clock select bit 0
Peripheral device’s clock select bit 1
b7 b6 b5 b4 b3 b2 b1 b0
0 : PLL frequency muliplier is inactive, and pin VCONT
is invalid. (Floating)
1 : PLL frequency muliplier is active, and pin VCONT is
valid.
0 0 : Do not select.
0 1 : Double
1 0 : Triple
1 1 : Quadruple
b3 b2
See Table 5.2.2.
0 : fXIN
1 : fPLL
01
RW
RW
RW
RW
RW
RW
RW
RW
Reference
12-17
Reference
5-6
5-7
Notes 1: Clear this bit to “0” if the PLL frequency multiplier need not to be active.
In the stop and flash memory parallel I/O modes, the PLL frequency multiplier is inactive and pin VCONT is invalid regard-
less of the contents of this bit.
2: Rewriting of these bits must be performed simultaneously with clearance of the system clock select bit (bit 5). Then, set
bit 5 to “1” 2 ms after the rewriting of these bits. (After reset, these bits are allowed to be changed only once.)
3: Clearing the PLL circuit operation enable bit (bit 1) to “0” clears the system clock select bit to “0.” Also, while the PLL circuit
operation enable bit = “0,” nothing can be written to the system clock select bit. (Fixed to be “0.”)
In order to set the system clock select bit to “1” after reset, it is necessary to wait 2 ms after the stabilization of f(XIN).
Note: Valid when the CTS/RTS enable bit (bit 4 at addresses 3416 and 3C16) is “0.”
APPENDIX
Appendix 3. Package outline
7902 Group User’s Manual 21-43
Appendix 3. Package outline
QFP100-P-1420-0.65 1.58
Weight(g)
JEDEC Code
EIAJ Package Code Lead Material
Alloy 42
100P6S-A
Plastic 100pin 1420mm body QFP
0.1
––
0.2
––
Symbol Min Nom Max
A
A
2
b
c
D
E
H
E
L
L
1
y
b
2
Dimension in Millimeters
H
D
A
1
0.35
I
2
1.3
M
D
14.6
M
E
20.6
10°0°0.1
1.4 0.80.60.4 23.122.822.5 17.116.816.5 0.65 20.220.019.8 14.214.013.8 0.20.150.13 0.40.30.25 2.8
03.05
e
e
e
E
c
H
E
1
30
31
81
50
80
51
H
D
D
M
D
M
E
A
F
b
A
1
A
2
L
1
L
y
b
2
I
2
Recommended Mount Pad
Detail F
100
LQFP100-P-1414-0.50 Weight(g)
JEDEC Code
EIAJ Package Code Lead Material
Cu Alloy
100P6Q-A
Plastic 100pin 1414mm body LQFP
0.1
––
0.2
––
Symbol Min Nom Max
A
A
2
b
c
D
E
H
E
L
L
1
y
b
2
Dimension in Millimeters
H
D
A
1
0.225
I
2
1.0
M
D
14.4
M
E
14.4
10°0°0.1
1.0 0.70.50.3 16.216.015.8 16.216.015.8 0.5 14.114.013.9 14.114.013.9 0.1750.1250.105 0.280.180.13 1.4
01.7
e
e
e
E
c
H
E
1
76
75
51
50
26
25
H
D
D
M
D
M
E
A
F
b
A
1
A
2
L
1
L
y
b
2
I
2
Recommended Mount Pad
Detail F
100
7902 Group User’s Manual
21-44
Appendix 4. Examples of handling unused pins
APPENDIX
Appendix 4. Examples of handling unused pins
When unusing an I/O pin, some handling is necessary for this pin. Examples of handling unused pins are
described below.
The following are just examples. In actual use, the user shall modify them according to the user’s application
and properly evaluate their performance.
1. In the single-chip mode
Table 1 Example of handling unused pins in single-chip mode
Handling example
Set these pins to the input mode and connect each
pin to Vcc or Vss via a resistor; or set these pins to
the output mode and leave them open (Note 1).
Set these pins to the input mode and leave them open (Notes 2, 3)
Leave these pins open.
Connect this pin to Vcc.
Connect these pins to Vss.
Pin name
P0 to P3, P40 to P43, P5 to P8, P10, P11
P44 to P47
NMI (Notes 2, 4), XOUT (Note 5), VCONT (Note 6)
AVCC
AVSS, VREF, BYTE
Notes 1: When leaving these pins open after they have been set to the output mode, note the following:
these port pins are placed in the input mode from reset until they are switched to the output mode
by software. Therefore, voltage levels of these pins are undefined and the power source current
may increase while these port pins are placed in the input mode.
Software reliability can be enhanced by setting the contents of the above ports’ direction registers
periodically. This is because these contents may be changed by noise, a program runaway which
occurs owing to noise, etc.
For unused pins, use the shortest possible wiring (within 20 mm from the microcomputer’s pins).
2: Do not connect these pins to Vss.
3: Be sure that the pins P44–P47 pullup select bit (bit 4 at address 9216) = 0.
4: Be sure that the pin NMI pullup select bit (bit 7 at address 9216) = 0.
5: This applies when a clock externally generated is input to pin XIN.
6: Be sure that the PLL circuit operation enable bit (bit 1 at address BC16) = 0.
Fig. 1 Example of handling unused pins in single-chip mode
P0–P3, P4
0
–P4
3
,
P5–P8, P10, P11
M37902
Left open
When setting port pins to input mode
V
CC
P4
4
–P4
7
NMI
X
OUT
V
CONT
V
CC
V
SS
P0–P8, P10, P11
M37902
When setting port pins to output mode (Note)
AV
CC
AV
SS
V
REF
BYTE
AV
CC
AV
SS
V
REF
BYTE
NMI
X
OUT
V
CONT
Note: Be sure to set P44–P47 to the input mode.
V
SS
Left open
Left open
APPENDIX
7902 Group User’s Manual 21-45
Appendix 4. Examples of handling unused pins
2. In memory expansion and microprocessor modes
Table 2 Example of handling unused pins in memory expansion and microprocessor modes
Handling example
Set these pins to the input mode and connect each
pin to Vcc or Vss via a resistor; or set these pins to
the output mode and leave them open (Note 2).
Set these pins to the input mode and leave them open (Notes 3,4)
Leave these pins open.
Connect this pin to Vcc.
Connect these pins to Vss.
Leave these pins open.
Connect these pins to Vcc via a resistor.
Pin name
P2 (Note 1), P30, P33 (Note 1), P40 to P43, P5 to P8
P44 to P47
NMI (Notes 3, 5), XOUT (Note 6), VCONT (Note 7)
AVCC
AVSS, VREF
φ1 (Note 8), ALE (Note 8), HLDA (Note 8)
RDY (Note 8), HOLD (Note 8)
Notes 1: This applies when the VCC level voltage is applied to pin BYTE.
2: When leaving these pins open after they have been set to the output mode, note the following:
these port pins are placed in the input mode from reset until they are switched to the output mode
by software. Therefore, voltage levels of these pins are undefined and the power source current
may increase while these pins are placed in the input mode.
Software reliability can be enhanced by setting the contents of the above ports’ direction registers
periodically. This is because these contents may be changed by noise, a program runaway which
occurs owing to noise, etc.
3: Do not connect these pins to Vss.
4: Be sure that the pins P44–P47 pullup select bit (bit 4 at address 9216) = 0.
5: Be sure that the pin NMI pullup select bit (bit 7 at address 9216) = 0.
6: This applies when a clock externally generated is input to pin XIN.
7: Be sure that the PLL circuit operation enable bit (bit 1 at address BC16) = 0.
8: This applies when the Vcc-level voltage is applied to pin MD0. (It is also possible to disable these functions
by software and use these pins as programmable I/O port pins.)
Fig. 2 Example of handling unused pins in memory expansion and microprocessor modes
P2, P3
0
, P3
3
,
P4
0
–P4
3
, P5–P8
M37902
V
CC
P4
4
–P4
7
NMI
X
OUT
V
CONT
V
CC
V
SS
P2, P3
0
, P3
3
, P4–P8
M37902
AV
CC
AV
SS
V
REF
AV
CC
AV
SS
V
REF
V
SS
φ
1
ALE
HLDA
RDY
HOLD
V
CC
φ
1
ALE
HLDA
RDY
HOLD
NMI
X
OUT
V
CONT
V
CC
When setting port pins to input mode When setting port pins to output mode
Note: Be sure to set P4
4
–P4
7
to the input mode.
Left open Left open
Left open
Left open
Left open
APPENDIX
Appendix 5. Hexadecimal instruction code table
7902 Group User’s Manual
21-46
Appendix 5. Hexadecimal instruction code table
0123456789ABCDEF
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
0
0
00
0
0
10
0
1
00
0
1
10
1
0
00
1
0
10
1
1
00
1
1
11
0
0
01
0
0
11
0
1
01
0
1
11
1
0
01
1
0
11
1
1
01
1
1
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
D
3
–D
0
D
7
–D
4
I
N
S
T
R
U
C
T
I
O
N
C
O
D
E
T
A
B
L
E
0
N
O
P
I
M
P
A
S
L
AS
E
C
I
M
P
N
E
G
A
L
D
A
A
,
I
M
M
L
D
X
A
B
SL
D
A
B
A
,
A
B
S
,
X
B
P
L
R
E
L
T
a
b
l
e
2
L
D
Y
D
I
RR
O
L
AC
L
C
I
M
P
A
B
S
A
L
D
Y
A
B
S
T
a
b
l
e
3
C
P
X
D
I
R
P
S
H
S
T
K
S
E
I
I
M
P
E
X
T
Z
A
A
D
D
A
,
I
M
ML
D
X
B
I
M
M
B
M
I
R
E
L
T
a
b
l
e
4
C
P
Y
D
I
R
P
U
L
S
T
K
C
L
I
I
M
P
E
X
T
S
AS
U
B
A
,
I
M
ML
D
Y
B
I
M
M
B
G
T
U
R
E
L
T
a
b
l
e
5
L
S
R
A
S
E
M
I
M
P
C
L
R
B
AC
M
P
A
,
I
M
MB
B
S
B
A
B
S
,
b
,
R
E
L
B
V
C
R
E
L
T
a
b
l
e
6
B
B
C
B
D
I
R
,
b
,
R
E
LR
O
R
AC
L
R
AO
R
A
A
,
I
M
MB
B
C
B
A
B
S
,
b
,
R
E
L
C
L
M
I
M
P
B
L
E
U
R
E
L
T
a
b
l
e
7
C
B
E
Q
B
D
I
R
/
I
M
M
,
R
E
L
P
H
D
S
T
K
C
L
V
I
M
P
X
A
B
I
M
P
A
N
D
A
,
I
M
M
B
R
A
L
R
E
L
B
V
S
R
E
L
T
a
b
l
e
8
C
B
N
E
B
D
I
R
/
I
M
M
,
R
E
L
P
L
D
S
T
K
R
T
I
I
M
P
A
S
R
A
E
O
R
A
,
I
M
M
B
G
T
R
E
L
T
a
b
l
e
9
I
N
C
D
I
R
I
N
C
A
R
T
S
I
M
PP
H
A
S
T
KM
O
V
M
D
I
R
/
I
M
MI
N
C
A
B
S
B
C
C
R
E
L
T
a
b
l
e
1
0
D
E
C
D
I
R
D
E
C
A
R
T
L
I
M
PP
L
A
S
T
KM
O
V
M
A
B
S
/
I
M
MD
E
C
A
B
S
B
C
S
R
E
L
T
a
b
l
e
1
1
C
B
E
Q
B
A
/
I
M
M
,
R
E
L
S
E
P
I
M
M
T
X
A
I
M
PP
H
P
S
T
K
S
T
K
/
I
M
M
T
a
b
l
e
1
2
C
B
N
E
B
A
/
I
M
M
,
R
E
L
C
L
P
I
M
M
T
Y
A
I
M
PP
L
P
S
T
K
C
B
E
Q
A
/
I
M
M
,
R
E
L
B
L
E
R
E
L
L
D
A
A
,
A
B
S
,
X
A
D
D
A
,
A
B
S
,
X
S
U
B
A
,
A
B
S
,
X
C
M
P
A
,
A
B
S
,
X
O
R
A
A
,
A
B
S
,
X
A
N
D
A
,
A
B
S
,
X
E
O
R
A
,
A
B
S
,
X
C
L
R
M
B
D
I
R
S
T
X
D
I
R
L
D
A
D
E
,
A
B
S
,
X
A
D
D
D
E
,
A
B
S
,
X
S
U
B
D
E
,
A
B
S
,
X
C
M
P
D
E
,
A
B
S
,
X
S
T
A
B
A
,
A
B
S
,
X
S
T
A
A
,
A
B
S
,
X
S
T
A
D
E
,
A
B
S
,
X
B
G
E
R
E
L
T
a
b
l
e
1
3
I
N
X
I
M
PT
A
X
I
M
PP
H
X
S
T
KC
L
R
M
B
A
B
S
B
N
E
R
E
L
T
a
b
l
e
1
4
C
L
R
M
D
I
RI
N
Y
I
M
PT
A
Y
I
M
PP
L
X
S
T
K
L
D
X
I
M
M
C
L
R
M
A
B
S
B
L
T
R
E
LD
E
X
I
M
PC
L
R
X
I
M
PP
H
Y
S
T
KC
P
X
I
M
MS
T
X
A
B
S
B
E
Q
R
E
LS
T
Y
D
I
RD
E
Y
I
M
PC
L
R
Y
I
M
PP
L
Y
S
T
KC
P
Y
I
M
MS
T
Y
A
B
S
B
R
K
I
M
PL
D
X
D
I
R
B
B
S
B
D
I
R
,
b
,
R
E
L
C
B
N
E
A
/
I
M
M
,
R
E
L
L
D
Y
I
M
M
L
D
A
B
A
,
A
B
S
L
D
A
A
,
A
B
S
A
D
D
A
,
A
B
S
S
U
B
A
,
A
B
S
C
M
P
A
,
A
B
S
O
R
A
A
,
A
B
S
A
N
D
A
,
A
B
S
E
O
R
A
,
A
B
S
L
D
A
D
E
,
A
B
S
A
D
D
D
E
,
A
B
S
S
U
B
D
E
,
A
B
S
C
M
P
D
E
,
A
B
S
S
T
A
B
A
,
A
B
S
S
T
A
A
,
A
B
S
S
T
A
D
E
,
A
B
S
L
D
A
B
A
,
A
B
L
,
X
L
D
A
A
,
A
B
L
,
X
A
D
D
D
E
,
I
M
M
S
U
B
D
E
,
I
M
M
M
O
V
M
B
D
I
R
/
A
B
S
,
X
M
O
V
M
D
I
R
/
A
B
S
,
X
L
D
A
D
E
,
A
B
L
,
X
J
S
R
A
B
S
J
S
R
L
A
B
L
J
S
R
(
A
B
S
,
X
)
S
T
A
B
A
,
A
B
L
,
X
S
T
A
A
,
A
B
L
,
X
S
T
A
D
E
,
A
B
L
,
X
L
D
A
B
A
,
A
B
L
L
D
A
A
,
A
B
L
L
D
A
D
E
,
I
M
M
C
M
P
D
E
,
I
M
M
M
O
V
M
B
D
I
R
/
A
B
S
M
O
V
M
D
I
R
/
A
B
S
M
O
V
M
B
A
B
S
/
A
B
S
M
O
V
M
A
B
S
/
A
B
S
L
D
A
D
E
,
A
B
L
J
M
P
A
B
S
J
M
P
L
A
B
L
J
M
P
(
A
B
S
,
X
)
S
T
A
B
A
,
A
B
L
S
T
A
A
,
A
B
L
S
T
A
D
E
,
A
B
L
L
D
A
B
A
,
D
I
R
,
X
L
D
A
A
,
D
I
R
,
X
A
D
D
A
,
D
I
R
,
X
S
U
B
A
,
D
I
R
,
X
C
M
P
A
,
D
I
R
,
X
O
R
A
A
,
D
I
R
,
X
A
N
D
A
,
D
I
R
,
X
E
O
R
A
,
D
I
R
,
X
L
D
A
D
E
,
D
I
R
,
X
A
D
D
D
E
,
D
I
R
,
X
S
U
B
D
E
,
D
I
R
,
X
C
M
P
D
E
,
D
I
R
,
X
S
T
A
B
A
,
D
I
R
,
X
S
T
A
A
,
D
I
R
,
X
S
T
A
D
E
,
D
I
R
,
X
L
D
A
B
A
,
D
I
R
L
D
A
A
,
D
I
R
A
D
D
A
,
D
I
R
S
U
B
A
,
D
I
R
C
M
P
A
,
D
I
R
O
R
A
A
,
D
I
R
A
N
D
A
,
D
I
R
E
O
R
A
,
D
I
R
L
D
A
D
E
,
D
I
R
A
D
D
D
E
,
D
I
R
S
U
B
D
E
,
D
I
R
C
M
P
D
E
,
D
I
R
S
T
A
B
A
,
D
I
R
S
T
A
A
,
D
I
R
S
T
A
D
E
,
D
I
R
L
D
A
B
A
,
L
(
D
I
R
)
,
Y
L
D
A
A
,
L
(
D
I
R
)
,
Y
A
D
D
B
A
,
I
M
M
S
U
B
B
A
,
I
M
M
M
O
V
M
B
A
B
S
/
D
I
R
,
X
M
O
V
M
A
B
S
/
D
I
R
,
X
L
D
A
D
E
,
L
(
D
I
R
)
,
Y
B
R
A
R
E
L
M
O
V
M
B
D
I
R
/
I
M
M
M
O
V
M
B
A
B
S
/
I
M
M
S
T
A
B
A
,
L
(
D
I
R
)
,
Y
S
T
A
A
,
L
(
D
I
R
)
,
Y
S
T
A
D
E
,
L
(
D
I
R
)
,
Y
L
D
A
B
A
,
(
D
I
R
)
,
Y
L
D
A
A
,
(
D
I
R
)
,
Y
L
D
A
B
A
,
I
M
M
C
M
P
B
A
,
I
M
M
M
O
V
M
B
D
I
R
/
D
I
R
M
O
V
M
D
I
R
/
D
I
R
M
O
V
M
B
A
B
S
/
D
I
R
M
O
V
M
A
B
S
/
D
I
R
L
D
A
D
E
,
(
D
I
R
)
,
Y
O
R
A
B
A
,
I
M
M
A
N
D
B
A
,
I
M
M
E
O
R
B
A
,
I
M
M
S
T
A
B
A
,
(
D
I
R
)
,
Y
S
T
A
A
,
(
D
I
R
)
,
Y
S
T
A
D
E
,
(
D
I
R
)
,
Y
B
S
R
R
E
L
T
a
b
l
e
1
H
e
x
a
d
e
c
i
m
a
l
n
o
t
a
t
i
o
n
P
L
D
n
/
R
T
S
D
n
S
T
K
/
R
T
L
D
n
L
D
D
n
/
P
H
L
D
n
/
P
H
D
n
N
o
t
e
:
T
a
b
l
e
s
1
t
h
r
o
u
g
h
1
4
s
p
e
c
i
f
i
e
s
t
h
e
c
o
n
t
e
n
t
s
o
f
t
h
e
I
N
S
T
R
U
C
T
I
O
N
C
O
D
E
T
A
B
L
E
1
t
h
r
o
u
g
h
1
4
.
A
b
o
u
t
t
h
e
s
e
c
o
n
d
w
o
r
d
s
c
o
d
e
s
,
r
e
f
e
r
t
o
t
h
e
I
N
S
T
R
U
C
T
I
O
N
C
O
D
E
T
A
B
L
E
1
t
h
r
o
u
g
h
1
4
.
APPENDIX
Appendix 5. Hexadecimal instruction code table
7902 Group User’s Manual 21-47
0123456789ABCDEF
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
0
0
00
0
0
10
0
1
00
0
1
10
1
0
00
1
0
10
1
1
00
1
1
11
0
0
01
0
0
11
0
1
01
0
1
11
1
0
01
1
0
11
1
1
01
1
1
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
D
X
B
N
E
I
M
M
,
R
E
L
A
D
D
X
I
M
M
A
D
D
Y
I
M
M
S
U
B
X
I
M
M
S
U
B
Y
I
M
M
D
Y
B
N
E
I
M
M
,
R
E
L
B
S
S
A
,
b
,
R
E
L
B
S
C
A
,
b
,
R
E
L
D
3
–D
0
D
7
–D
4
I
N
S
T
R
U
C
T
I
O
N
C
O
D
E
T
A
B
L
E
1
(
T
h
e
f
i
r
s
t
w
o
r
d
s
c
o
d
e
o
f
e
a
c
h
i
n
s
t
r
u
c
t
i
o
n
i
s
0
1
1
6
)
H
e
x
a
d
e
c
i
m
a
l
n
o
t
a
t
i
o
n
0123456789ABCDEF
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
0
0
00
0
0
10
0
1
00
0
1
10
1
0
00
1
0
10
1
1
00
1
1
11
0
0
01
0
0
11
0
1
01
0
1
11
1
0
01
1
0
11
1
1
01
1
1
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
L
D
A
B
A
,
(
D
I
R
)
L
D
A
A
,
(
D
I
R
)
A
D
D
A
,
(
D
I
R
)
S
U
B
A
,
(
D
I
R
)
C
M
P
A
,
(
D
I
R
)
O
R
A
A
,
(
D
I
R
)
A
N
D
A
,
(
D
I
R
)
E
O
R
A
,
(
D
I
R
)
L
D
A
D
E
,
(
D
I
R
)
A
D
D
D
E
,
(
D
I
R
)
S
U
B
D
E
,
(
D
I
R
)
C
M
P
D
E
,
(
D
I
R
)
S
T
A
B
A
,
(
D
I
R
)
S
T
A
A
,
(
D
I
R
)
S
T
A
D
E
,
(
D
I
R
)
L
D
A
B
A
,
(
D
I
R
,
X
)
L
D
A
A
,
(
D
I
R
,
X
)
A
D
D
A
,
(
D
I
R
,
X
)
S
U
B
A
,
(
D
I
R
,
X
)
C
M
P
A
,
(
D
I
R
,
X
)
O
R
A
A
,
(
D
I
R
,
X
)
A
N
D
A
,
(
D
I
R
,
X
)
E
O
R
A
,
(
D
I
R
,
X
)
L
D
A
D
E
,
(
D
I
R
,
X
)
A
D
D
D
E
,
(
D
I
R
,
X
)
S
U
B
D
E
,
(
D
I
R
,
X
)
C
M
P
D
E
,
(
D
I
R
,
X
)
S
T
A
B
A
,
(
D
I
R
,
X
)
S
T
A
A
,
(
D
I
R
,
X
)
S
T
A
D
E
,
(
D
I
R
,
X
)
L
D
A
B
A
,
L
(
D
I
R
)
L
D
A
A
,
L
(
D
I
R
)
A
D
D
A
,
L
(
D
I
R
)
S
U
B
A
,
L
(
D
I
R
)
C
M
P
A
,
L
(
D
I
R
)
O
R
A
A
,
L
(
D
I
R
)
A
N
D
A
,
L
(
D
I
R
)
E
O
R
A
,
L
(
D
I
R
)
L
D
A
D
E
,
L
(
D
I
R
)
A
D
D
D
E
,
L
(
D
I
R
)
S
U
B
D
E
,
L
(
D
I
R
)
C
M
P
D
E
,
L
(
D
I
R
)
S
T
A
B
A
,
L
(
D
I
R
)
S
T
A
A
,
L
(
D
I
R
)
S
T
A
D
E
,
L
(
D
I
R
)
L
D
A
B
A
,
S
R
L
D
A
A
,
S
R
A
D
D
A
,
S
R
S
U
B
A
,
S
R
C
M
P
A
,
S
R
O
R
A
A
,
S
R
A
N
D
A
,
S
R
E
O
R
A
,
S
R
L
D
A
D
E
,
S
R
A
D
D
D
E
,
S
R
S
U
B
D
E
,
S
R
C
M
P
D
E
,
S
R
S
T
A
B
A
,
S
R
S
T
A
A
,
S
R
S
T
A
D
E
,
S
R
L
D
A
B
A
,
(
S
R
)
,
Y
L
D
A
A
,
(
S
R
)
,
Y
A
D
D
A
,
(
S
R
)
,
Y
S
U
B
A
,
(
S
R
)
,
Y
C
M
P
A
,
(
S
R
)
,
Y
O
R
A
A
,
(
S
R
)
,
Y
A
N
D
A
,
(
S
R
)
,
Y
E
O
R
A
,
(
S
R
)
,
Y
L
D
A
D
E
,
(
S
R
)
,
Y
A
D
D
D
E
,
(
S
R
)
,
Y
S
U
B
D
E
,
(
S
R
)
,
Y
C
M
P
D
E
,
(
S
R
)
,
Y
S
T
A
B
A
,
(
S
R
)
,
Y
S
T
A
A
,
(
S
R
)
,
Y
S
T
A
D
E
,
(
S
R
)
,
Y
L
D
A
B
A
,
A
B
S
,
Y
L
D
A
A
,
A
B
S
,
Y
A
D
D
A
,
A
B
S
,
Y
S
U
B
A
,
A
B
S
,
Y
C
M
P
A
,
A
B
S
,
Y
O
R
A
A
,
A
B
S
,
Y
A
N
D
A
,
A
B
S
,
Y
E
O
R
A
,
A
B
S
,
Y
L
D
A
D
E
,
A
B
S
,
Y
A
D
D
D
E
,
A
B
S
,
Y
S
U
B
D
E
,
A
B
S
,
Y
C
M
P
D
E
,
A
B
S
,
Y
S
T
A
B
A
,
A
B
S
,
Y
S
T
A
A
,
A
B
S
,
Y
S
T
A
D
E
,
A
B
S
,
Y
A
D
D
A
,
(
D
I
R
)
,
Y
S
U
B
A
,
(
D
I
R
)
,
Y
C
M
P
A
,
(
D
I
R
)
,
Y
O
R
A
A
,
(
D
I
R
)
,
Y
A
N
D
A
,
(
D
I
R
)
,
Y
E
O
R
A
,
(
D
I
R
)
,
Y
A
D
D
D
E
,
(
D
I
R
)
,
Y
S
U
B
D
E
,
(
D
I
R
)
,
Y
C
M
P
D
E
,
(
D
I
R
)
,
Y
A
D
D
A
,
L
(
D
I
R
)
,
Y
S
U
B
A
,
L
(
D
I
R
)
,
Y
C
M
P
A
,
L
(
D
I
R
)
,
Y
O
R
A
A
,
L
(
D
I
R
)
,
Y
A
N
D
A
,
L
(
D
I
R
)
,
Y
E
O
R
A
,
L
(
D
I
R
)
,
Y
A
D
D
D
E
,
L
(
D
I
R
)
,
Y
S
U
B
D
E
,
L
(
D
I
R
)
,
Y
C
M
P
D
E
,
L
(
D
I
R
)
,
Y
A
D
D
A
,
A
B
L
S
U
B
A
,
A
B
L
C
M
P
A
,
A
B
L
O
R
A
A
,
A
B
L
A
N
D
A
,
A
B
L
E
O
R
A
,
A
B
L
A
D
D
D
E
,
A
B
L
S
U
B
D
E
,
A
B
L
C
M
P
D
E
,
A
B
L
A
D
D
A
,
A
B
L
,
X
S
U
B
A
,
A
B
L
,
X
C
M
P
A
,
A
B
L
,
X
O
R
A
A
,
A
B
L
,
X
A
N
D
A
,
A
B
L
,
X
E
O
R
A
,
A
B
L
,
X
A
D
D
D
E
,
A
B
L
,
X
S
U
B
D
E
,
A
B
L
,
X
C
M
P
D
E
,
A
B
L
,
X
D
3
–D
0
D
7
–D
4
I
N
S
T
R
U
C
T
I
O
N
C
O
D
E
T
A
B
L
E
2
(
T
h
e
f
i
r
s
t
w
o
r
d
s
c
o
d
e
o
f
e
a
c
h
i
n
s
t
r
u
c
t
i
o
n
i
s
1
1
1
6
)
H
e
x
a
d
e
c
i
m
a
l
n
o
t
a
t
i
o
n
APPENDIX
Appendix 5. Hexadecimal instruction code table
7902 Group User’s Manual
21-48
0123456789ABCDEF
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
0
0
00
0
0
10
0
1
00
0
1
10
1
0
00
1
0
10
1
1
00
1
1
11
0
0
01
0
0
11
0
1
01
0
1
11
1
0
01
1
0
11
1
1
01
1
1
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
A
D
C
A
,
(
D
I
R
)
A
D
C
D
E
,
(
D
I
R
)
S
B
C
A
,
(
D
I
R
)
S
B
C
D
E
,
(
D
I
R
)
M
P
Y
(
D
I
R
)
M
P
Y
S
(
D
I
R
)
D
I
V
(
D
I
R
)
D
I
V
S
(
D
I
R
)
A
D
C
A
,
(
D
I
R
,
X
)
A
D
C
D
E
,
(
D
I
R
,
X
)
S
B
C
A
,
(
D
I
R
,
X
)
S
B
C
D
E
,
(
D
I
R
,
X
)
M
P
Y
(
D
I
R
,
X
)
M
P
Y
S
(
D
I
R
,
X
)
D
I
V
(
D
I
R
,
X
)
D
I
V
S
(
D
I
R
,
X
)
A
D
C
A
,
L
(
D
I
R
)
A
D
C
D
E
,
L
(
D
I
R
)
S
B
C
A
,
L
(
D
I
R
)
S
B
C
D
E
,
L
(
D
I
R
)
M
P
Y
L
(
D
I
R
)
M
P
Y
S
L
(
D
I
R
)
D
I
V
L
(
D
I
R
)
D
I
V
S
L
(
D
I
R
)
A
D
C
A
,
S
R
A
D
C
D
E
,
S
R
S
B
C
A
,
S
R
S
B
C
D
E
,
S
R
M
P
Y
S
R
M
P
Y
S
S
R
D
I
V
S
R
D
I
V
S
S
R
A
D
C
A
,
(
S
R
)
,
Y
A
D
C
D
E
,
(
S
R
)
,
Y
S
B
C
A
,
(
S
R
)
,
Y
S
B
C
D
E
,
(
S
R
)
,
Y
M
P
Y
(
S
R
)
,
Y
M
P
Y
S
(
S
R
)
,
Y
D
I
V
(
S
R
)
,
Y
D
I
V
S
(
S
R
)
,
Y
A
D
C
A
,
(
D
I
R
)
,
Y
A
D
C
D
E
,
(
D
I
R
)
,
Y
S
B
C
A
,
(
D
I
R
)
,
Y
S
B
C
D
E
,
(
D
I
R
)
,
Y
M
P
Y
(
D
I
R
)
,
Y
M
P
Y
S
(
D
I
R
)
,
Y
D
I
V
(
D
I
R
)
,
Y
D
I
V
S
(
D
I
R
)
,
Y
A
D
C
A
,
L
(
D
I
R
)
,
Y
A
D
C
D
E
,
L
(
D
I
R
)
,
Y
S
B
C
A
,
L
(
D
I
R
)
,
Y
S
B
C
D
E
,
L
(
D
I
R
)
,
Y
M
P
Y
L
(
D
I
R
)
,
Y
M
P
Y
S
L
(
D
I
R
)
,
Y
D
I
V
L
(
D
I
R
)
,
Y
D
I
V
S
L
(
D
I
R
)
,
Y
A
D
C
A
,
D
I
R
A
D
C
D
E
,
D
I
R
S
B
C
A
,
D
I
R
S
B
C
D
E
,
D
I
R
M
P
Y
D
I
R
M
P
Y
S
D
I
R
D
I
V
D
I
R
D
I
V
S
D
I
R
A
D
C
A
,
D
I
R
,
X
A
D
C
D
E
,
D
I
R
,
X
S
B
C
A
,
D
I
R
,
X
S
B
C
D
E
,
D
I
R
,
X
M
P
Y
D
I
R
,
X
M
P
Y
S
D
I
R
,
X
D
I
V
D
I
R
,
X
D
I
V
S
D
I
R
,
X
A
D
C
A
,
A
B
S
,
Y
A
D
C
D
E
,
A
B
S
,
Y
S
B
C
A
,
A
B
S
,
Y
S
B
C
D
E
,
A
B
S
,
Y
M
P
Y
A
B
S
,
Y
M
P
Y
S
A
B
S
,
Y
D
I
V
A
B
S
,
Y
D
I
V
S
A
B
S
,
Y
A
D
C
A
,
A
B
S
A
D
C
D
E
,
A
B
S
S
B
C
A
,
A
B
S
S
B
C
D
E
,
A
B
S
M
P
Y
A
B
S
M
P
Y
S
A
B
S
D
I
V
A
B
S
D
I
V
S
A
B
S
A
D
C
A
,
A
B
S
,
X
A
D
C
D
E
,
A
B
S
,
X
S
B
C
A
,
A
B
S
,
X
S
B
C
D
E
,
A
B
S
,
X
M
P
Y
A
B
S
,
X
M
P
Y
S
A
B
S
,
X
D
I
V
A
B
S
,
X
D
I
V
S
A
B
S
,
X
A
D
C
A
,
A
B
L
A
D
C
D
E
,
A
B
L
S
B
C
A
,
A
B
L
S
B
C
D
E
,
A
B
L
M
P
Y
A
B
L
M
P
Y
S
A
B
L
D
I
V
A
B
L
D
I
V
S
A
B
L
A
D
C
A
,
A
B
L
,
X
A
D
C
D
E
,
A
B
L
,
X
S
B
C
A
,
A
B
L
,
X
S
B
C
D
E
,
A
B
L
,
X
M
P
Y
A
B
L
,
X
M
P
Y
S
A
B
L
,
X
D
I
V
A
B
L
,
X
D
I
V
S
A
B
L
,
X
A
S
L
D
I
R
R
O
L
D
I
R
L
S
R
D
I
R
R
O
R
D
I
R
A
S
R
D
I
R
A
S
L
D
I
R
,
X
R
O
L
D
I
R
,
X
L
S
R
D
I
R
,
X
R
O
R
D
I
R
,
X
A
S
R
D
I
R
,
X
A
S
L
A
B
S
R
O
L
A
B
S
L
S
R
A
B
S
R
O
R
A
B
S
A
S
R
A
B
S
A
S
L
A
B
S
,
X
R
O
L
A
B
S
,
X
L
S
R
A
B
S
,
X
R
O
R
A
B
S
,
X
A
S
R
A
B
S
,
X
D
3
–D
0
D
7
–D
4
I
N
S
T
R
U
C
T
I
O
N
C
O
D
E
T
A
B
L
E
3
(
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h
e
f
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2
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6
)
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n
0123456789ABCDEF
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
0
0
00
0
0
10
0
1
00
0
1
10
1
0
00
1
0
10
1
1
00
1
1
11
0
0
01
0
0
11
0
1
01
0
1
11
1
0
01
1
0
11
1
1
01
1
1
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
W
I
T
I
M
P
S
T
P
I
M
P
P
H
T
S
T
K
P
L
T
S
T
K
P
H
G
S
T
K
N
E
G
D
E
A
B
S
D
E
E
X
T
Z
D
E
E
X
T
S
D
E
T
A
D
,
0
I
M
P
T
A
D
,
1
I
M
P
T
A
D
,
2
I
M
P
T
A
D
,
3
I
M
P
T
D
A
,
0
I
M
P
T
D
A
,
1
I
M
P
T
D
A
,
2
I
M
P
T
D
A
,
3
I
M
P
T
A
S
I
M
P
T
S
A
I
M
P
T
X
Y
I
M
P
T
Y
X
I
M
P
T
X
S
I
M
P
A
D
C
A
,
I
M
M
S
B
C
A
,
I
M
M
M
O
V
M
D
I
R
,
X
/
I
M
M
M
O
V
M
A
B
S
,
X
/
I
M
M
R
L
A
A
M
P
Y
I
M
M
M
P
Y
S
I
M
M
D
I
V
I
M
M
A
D
D
S
I
M
M
A
D
C
B
A
,
I
M
M
M
V
P
B
L
K
M
O
V
M
B
D
I
R
,
X
/
I
M
M
L
D
T
I
M
M
R
M
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A
M
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p
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M
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I
V
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I
M
M
S
U
B
S
I
M
M
S
B
C
B
A
,
I
M
M
M
V
N
B
L
K
M
O
V
M
B
A
B
S
,
X
/
I
M
M
P
E
I
S
T
K
A
D
C
D
E
,
I
M
M
P
E
A
S
T
K
J
M
P
(
A
B
S
)
S
B
C
D
E
,
I
M
M
P
E
R
S
T
K
J
M
P
L
L
(
A
B
S
)
T
D
S
I
M
P
T
S
D
I
M
P
D
3
–D
0
D
7
–D
4
I
N
S
T
R
U
C
T
I
O
N
C
O
D
E
T
A
B
L
E
4
(
T
h
e
f
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s
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3
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6
)
H
e
x
a
d
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c
i
m
a
l
n
o
t
a
t
i
o
n
APPENDIX
Appendix 5. Hexadecimal instruction code table
7902 Group User’s Manual 21-49
0123456789ABCDEF
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
0
0
00
0
0
10
0
1
00
0
1
10
1
0
00
1
0
10
1
1
00
1
1
11
0
0
01
0
0
11
0
1
01
0
1
11
1
0
01
1
0
11
1
1
01
1
1
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
B
B
S
D
I
R
,
b
,
R
E
L
B
B
C
D
I
R
,
b
,
R
E
L
C
B
E
Q
D
I
R
/
I
M
M
,
R
E
L
L
D
Y
D
I
R
,
X
I
N
C
D
I
R
,
X
D
E
C
D
I
R
,
X
C
P
X
A
B
S
B
B
S
A
B
S
,
b
,
R
E
L
B
B
C
A
B
S
,
b
,
R
E
L
L
D
Y
A
B
S
,
X
I
N
C
A
B
S
,
X
D
E
C
A
B
S
,
X
L
D
X
D
I
R
,
YL
D
X
A
B
S
,
Y
S
T
X
D
I
R
,
Y
S
T
Y
D
I
R
,
X
C
P
Y
A
B
S
C
B
N
E
D
I
R
/
I
M
M
,
R
E
L
D
3
–D
0
D
7
–D
4
I
N
S
T
R
U
C
T
I
O
N
C
O
D
E
T
A
B
L
E
5
(
T
h
e
f
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r
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w
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c
o
d
e
o
f
e
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t
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i
s
4
1
1
6
)
H
e
x
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m
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n
o
t
a
t
i
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n
0123456789ABCDEF
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
0
0
00
0
0
10
0
1
00
0
1
10
1
0
00
1
0
10
1
1
00
1
1
11
0
0
01
0
0
11
0
1
01
0
1
11
1
0
01
1
0
11
1
1
01
1
1
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
A
D
D
M
D
D
I
R
/
I
M
M
S
U
B
M
D
D
I
R
/
I
M
M
C
M
P
M
D
D
I
R
/
I
M
M
O
R
A
M
D
D
I
R
/
I
M
M
A
N
D
M
D
D
I
R
/
I
M
M
E
O
R
M
D
D
I
R
/
I
M
M
A
D
D
M
B
D
I
R
/
I
M
M
S
U
B
M
B
D
I
R
/
I
M
M
C
M
P
M
B
D
I
R
/
I
M
M
O
R
A
M
B
D
I
R
/
I
M
M
A
N
D
M
B
D
I
R
/
I
M
M
E
O
R
M
B
D
I
R
/
I
M
M
A
D
D
M
D
I
R
/
I
M
M
S
U
B
M
D
I
R
/
I
M
M
C
M
P
M
D
I
R
/
I
M
M
O
R
A
M
D
I
R
/
I
M
M
A
N
D
M
D
I
R
/
I
M
M
E
O
R
M
D
I
R
/
I
M
M
A
D
D
M
D
A
B
S
/
I
M
M
S
U
B
M
D
A
B
S
/
I
M
M
C
M
P
M
D
A
B
S
/
I
M
M
O
R
A
M
D
A
B
S
/
I
M
M
A
N
D
M
D
A
B
S
/
I
M
M
E
O
R
M
D
A
B
S
/
I
M
M
A
D
D
M
B
A
B
S
/
I
M
M
S
U
B
M
B
A
B
S
/
I
M
M
C
M
P
M
B
A
B
S
/
I
M
M
O
R
A
M
B
A
B
S
/
I
M
M
A
N
D
M
B
A
B
S
/
I
M
M
E
O
R
M
B
A
B
S
/
I
M
M
A
D
D
M
A
B
S
/
I
M
M
S
U
B
M
A
B
S
/
I
M
M
C
M
P
M
A
B
S
/
I
M
M
O
R
A
M
A
B
S
/
I
M
M
A
N
D
M
A
B
S
/
I
M
M
E
O
R
M
A
B
S
/
I
M
M
D
3
–D
0
D
7
–D
4
I
N
S
T
R
U
C
T
I
O
N
C
O
D
E
T
A
B
L
E
6
(
T
h
e
f
i
r
s
t
w
o
r
d
s
c
o
d
e
o
f
e
a
c
h
i
n
s
t
r
u
c
t
i
o
n
i
s
5
1
1
6
)
H
e
x
a
d
e
c
i
m
a
l
n
o
t
a
t
i
o
n
APPENDIX
Appendix 5. Hexadecimal instruction code table
7902 Group User’s Manual
21-50
0123456789ABCDEF
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
0
0
00
0
0
10
0
1
00
0
1
10
1
0
00
1
0
10
1
1
00
1
1
11
0
0
01
0
0
11
0
1
01
0
1
11
1
0
01
1
0
11
1
1
01
1
1
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
M
O
V
R
B
D
I
R
/
A
B
S
M
O
V
R
D
I
R
/
A
B
S
M
O
V
R
B
A
B
S
/
A
B
S
M
O
V
R
A
B
S
/
A
B
S
M
O
V
R
B
D
I
R
/
I
M
M
M
O
V
R
D
I
R
/
I
M
M
M
O
V
R
B
A
B
S
/
I
M
M
M
O
V
R
A
B
S
/
I
M
M
M
O
V
R
B
D
I
R
/
D
I
R
M
O
V
R
D
I
R
/
D
I
R
M
O
V
R
B
A
B
S
/
D
I
R
M
O
V
R
A
B
S
/
D
I
R
D
3
–D
0
D
7
–D
4
I
N
S
T
R
U
C
T
I
O
N
C
O
D
E
T
A
B
L
E
7
(
T
h
e
f
i
r
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t
w
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d
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c
o
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e
o
f
e
a
c
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s
t
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c
t
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i
s
6
11
6)
H
e
x
a
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c
i
m
a
l
n
o
t
a
t
i
o
n
0123456789ABCDEF
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
0
0
00
0
0
10
0
1
00
0
1
10
1
0
00
1
0
10
1
1
00
1
1
11
0
0
01
0
0
11
0
1
01
0
1
11
1
0
01
1
0
11
1
1
01
1
1
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
B
S
S
D
I
R
,
b
,
R
E
L
B
S
C
D
I
R
,
b
,
R
E
L
B
S
C
A
B
S
,
b
,
R
E
L
M
O
V
R
B
D
I
R
/
A
B
S
,
X
B
S
S
A
B
S
,
b
,
R
E
L
M
O
V
R
D
I
R
/
A
B
S
,
X
M
O
V
R
B
A
B
S
/
D
I
R
,
X
M
O
V
R
A
B
S
/
D
I
R
,
X
D
3
–D
0
D
7
–D
4
I
N
S
T
R
U
C
T
I
O
N
C
O
D
E
T
A
B
L
E
8
(
T
h
e
f
i
r
s
t
w
o
r
d
s
c
o
d
e
o
f
e
a
c
h
i
n
s
t
r
u
c
t
i
o
n
i
s
7
1
1
6
)
H
e
x
a
d
e
c
i
m
a
l
n
o
t
a
t
i
o
n
APPENDIX
Appendix 5. Hexadecimal instruction code table
7902 Group User’s Manual 21-51
0123456789ABCDEF
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
0
0
00
0
0
10
0
1
00
0
1
10
1
0
00
1
0
10
1
1
00
1
1
11
0
0
01
0
0
11
0
1
01
0
1
11
1
0
01
1
0
11
1
1
01
1
1
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
A
S
L
B
N
E
G
B
L
D
A
B
,
I
M
M
L
D
A
B
B
,
A
B
S
,
X
R
O
L
B
A
B
S
B
E
X
T
Z
B
A
D
D
B
,
I
M
M
E
X
T
S
BS
U
B
B
,
I
M
M
L
S
R
BC
L
R
B
BC
M
P
B
,
I
M
M
R
O
R
BC
L
R
BO
R
A
B
,
I
M
M
A
N
D
B
,
I
M
M
A
S
R
B
E
O
R
B
,
I
M
M
I
N
C
B
P
H
B
S
T
K
D
E
C
B
P
L
B
S
T
K
T
X
B
I
M
P
C
B
N
E
B
B
/
I
M
M
,
R
E
LT
Y
B
I
M
P
C
B
E
Q
B
/
I
M
M
,
R
E
L
L
D
A
B
,
A
B
S
,
X
A
D
D
B
,
A
B
S
,
X
S
U
B
B
,
A
B
S
,
X
C
M
P
B
,
A
B
S
,
X
O
R
A
B
,
A
B
S
,
X
A
N
D
B
,
A
B
S
,
X
E
O
R
B
,
A
B
S
,
X
S
T
A
B
B
,
A
B
S
,
X
S
T
A
B
,
A
B
S
,
X
T
B
X
I
M
P
T
B
Y
I
M
P
C
B
N
E
B
/
I
M
M
,
R
E
L
L
D
A
B
B
,
A
B
S
L
D
A
B
,
A
B
S
A
D
D
B
,
A
B
S
S
U
B
B
,
A
B
S
C
M
P
B
,
A
B
S
O
R
A
B
,
A
B
S
A
N
D
B
,
A
B
S
E
O
R
B
,
A
B
S
S
T
A
B
B
,
A
B
S
S
T
A
B
,
A
B
S
L
D
A
B
B
,
A
B
L
,
X
L
D
A
B
,
A
B
L
,
X
S
T
A
B
B
,
A
B
L
,
X
S
T
A
B
,
A
B
L
,
X
L
D
A
B
B
,
A
B
L
L
D
A
B
,
A
B
L
S
T
A
B
B
,
A
B
L
S
T
A
B
,
A
B
L
L
D
A
B
B
,
D
I
R
,
X
L
D
A
B
,
D
I
R
,
X
A
D
D
B
,
D
I
R
,
X
S
U
B
B
,
D
I
R
,
X
C
M
P
B
,
D
I
R
,
X
O
R
A
B
,
D
I
R
,
X
A
N
D
B
,
D
I
R
,
X
E
O
R
B
,
D
I
R
,
X
S
T
A
B
B
,
D
I
R
,
X
S
T
A
B
,
D
I
R
,
X
L
D
A
B
B
,
D
I
R
L
D
A
B
,
D
I
R
A
D
D
B
,
D
I
R
S
U
B
B
,
D
I
R
C
M
P
B
,
D
I
R
O
R
A
B
,
D
I
R
A
N
D
B
,
D
I
R
E
O
R
B
,
D
I
R
S
T
A
B
B
,
D
I
R
S
T
A
B
,
D
I
R
L
D
A
B
B
,
L
(
D
I
R
)
,
Y
L
D
A
B
,
L
(
D
I
R
)
,
Y
A
D
D
B
B
,
I
M
M
S
U
B
B
B
,
I
M
M
S
T
A
B
B
,
L
(
D
I
R
)
,
Y
S
T
A
B
,
L
(
D
I
R
)
,
Y
L
D
A
B
B
,
(
D
I
R
)
,
Y
L
D
A
B
,
(
D
I
R
)
,
Y
L
D
A
B
B
,
I
M
M
C
M
P
B
B
,
I
M
M
O
R
A
B
B
,
I
M
M
A
N
D
B
B
,
I
M
M
E
O
R
B
B
,
I
M
M
S
T
A
B
B
,
(
D
I
R
)
,
Y
S
T
A
B
,
(
D
I
R
)
,
Y
C
B
E
Q
B
B
/
I
M
M
,
R
E
L
D3–D0
D7–D4
I
N
S
T
R
U
C
T
I
O
N
C
O
D
E
T
A
B
L
E
9
(
T
h
e
f
i
r
s
t
w
o
r
d
s
c
o
d
e
o
f
e
a
c
h
i
n
s
t
r
u
c
t
i
o
n
i
s
8
11
6)
H
e
x
a
d
e
c
i
m
a
l
n
o
t
a
t
i
o
n
0123456789ABCDEF
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
0
0
00
0
0
10
0
1
00
0
1
10
1
0
00
1
0
10
1
1
00
1
1
11
0
0
01
0
0
11
0
1
01
0
1
11
1
0
01
1
0
11
1
1
01
1
1
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
L
D
A
B
B
,
(
D
I
R
)
L
D
A
B
,
(
D
I
R
)
A
D
D
B
,
(
D
I
R
)
S
U
B
B
,
(
D
I
R
)
C
M
P
B
,
(
D
I
R
)
O
R
A
B
,
(
D
I
R
)
A
N
D
B
,
(
D
I
R
)
E
O
R
B
,
(
D
I
R
)
S
T
A
B
B
,
(
D
I
R
)
S
T
A
B
,
(
D
I
R
)
L
D
A
B
B
,
(
D
I
R
,
X
)
L
D
A
B
,
(
D
I
R
,
X
)
A
D
D
B
,
(
D
I
R
,
X
)
S
U
B
B
,
(
D
I
R
,
X
)
C
M
P
B
,
(
D
I
R
,
X
)
O
R
A
B
,
(
D
I
R
,
X
)
A
N
D
B
,
(
D
I
R
,
X
)
E
O
R
B
,
(
D
I
R
,
X
)
S
T
A
B
B
,
(
D
I
R
,
X
)
S
T
A
B
,
(
D
I
R
,
X
)
L
D
A
B
B
,
L
(
D
I
R
)
L
D
A
B
,
L
(
D
I
R
)
A
D
D
B
,
L
(
D
I
R
)
S
U
B
B
,
L
(
D
I
R
)
C
M
P
B
,
L
(
D
I
R
)
O
R
A
B
,
L
(
D
I
R
)
A
N
D
B
,
L
(
D
I
R
)
E
O
R
B
,
L
(
D
I
R
)
S
T
A
B
B
,
L
(
D
I
R
)
S
T
A
B
,
L
(
D
I
R
)
L
D
A
B
B
,
S
R
L
D
A
B
,
S
R
A
D
D
B
,
S
R
S
U
B
B
,
S
R
C
M
P
B
,
S
R
O
R
A
B
,
S
R
A
N
D
B
,
S
R
E
O
R
B
,
S
R
S
T
A
B
B
,
S
R
S
T
A
B
,
S
R
L
D
A
B
B
,
(
S
R
)
,
Y
L
D
A
B
,
(
S
R
)
,
Y
A
D
D
B
,
(
S
R
)
,
Y
S
U
B
B
,
(
S
R
)
,
Y
C
M
P
B
,
(
S
R
)
,
Y
O
R
A
B
,
(
S
R
)
,
Y
A
N
D
B
,
(
S
R
)
,
Y
E
O
R
B
,
(
S
R
)
,
Y
S
T
A
B
B
,
(
S
R
)
,
Y
S
T
A
B
,
(
S
R
)
,
Y
L
D
A
B
B
,
A
B
S
,
Y
L
D
A
B
,
A
B
S
,
Y
A
D
D
B
,
A
B
S
,
Y
S
U
B
B
,
A
B
S
,
Y
C
M
P
B
,
A
B
S
,
Y
O
R
A
B
,
A
B
S
,
Y
A
N
D
B
,
A
B
S
,
Y
E
O
R
B
,
A
B
S
,
Y
S
T
A
B
B
,
A
B
S
,
Y
S
T
A
B
,
A
B
S
,
Y
A
D
D
B
,
(
D
I
R
)
,
Y
S
U
B
B
,
(
D
I
R
)
,
Y
C
M
P
B
,
(
D
I
R
)
,
Y
O
R
A
B
,
(
D
I
R
)
,
Y
A
N
D
B
,
(
D
I
R
)
,
Y
E
O
R
B
,
(
D
I
R
)
,
Y
A
D
D
B
,
L
(
D
I
R
)
,
Y
S
U
B
B
,
L
(
D
I
R
)
,
Y
C
M
P
B
,
L
(
D
I
R
)
,
Y
O
R
A
B
,
L
(
D
I
R
)
,
Y
A
N
D
B
,
L
(
D
I
R
)
,
Y
E
O
R
B
,
L
(
D
I
R
)
,
Y
A
D
D
B
,
A
B
L
S
U
B
B
,
A
B
L
C
M
P
B
,
A
B
L
O
R
A
B
,
A
B
L
A
N
D
B
,
A
B
L
E
O
R
B
,
A
B
L
A
D
D
B
,
A
B
L
,
X
S
U
B
B
,
A
B
L
,
X
C
M
P
B
,
A
B
L
,
X
O
R
A
B
,
A
B
L
,
X
A
N
D
B
,
A
B
L
,
X
E
O
R
B
,
A
B
L
,
X
D
3
–D
0
D
7
–D
4
I
N
S
T
R
U
C
T
I
O
N
C
O
D
E
T
A
B
L
E
1
0
(
T
h
e
f
i
r
s
t
w
o
r
d
s
c
o
d
e
o
f
e
a
c
h
i
n
s
t
r
u
c
t
i
o
n
i
s
9
1
1
6
)
H
e
x
a
d
e
c
i
m
a
l
n
o
t
a
t
i
o
n
APPENDIX
Appendix 5. Hexadecimal instruction code table
7902 Group User’s Manual
21-52
0123456789ABCDEF
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
0
0
00
0
0
10
0
1
00
0
1
10
1
0
00
1
0
10
1
1
00
1
1
11
0
0
01
0
0
11
0
1
01
0
1
11
1
0
01
1
0
11
1
1
01
1
1
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
A
D
C
B
,
(
D
I
R
)
S
B
C
B
,
(
D
I
R
)
A
D
C
B
,
(
D
I
R
,
X
)
S
B
C
B
,
(
D
I
R
,
X
)
A
D
C
B
,
L
(
D
I
R
)
S
B
C
B
,
L
(
D
I
R
)
A
D
C
B
,
S
R
S
B
C
B
,
S
R
A
D
C
B
,
(
S
R
)
,
Y
S
B
C
B
,
(
S
R
)
,
Y
A
D
C
B
,
(
D
I
R
)
,
Y
S
B
C
B
,
(
D
I
R
)
,
Y
A
D
C
B
,
L
(
D
I
R
)
,
Y
S
B
C
B
,
L
(
D
I
R
)
,
Y
A
D
C
B
,
D
I
R
S
B
C
B
,
D
I
R
A
D
C
B
,
D
I
R
,
X
S
B
C
B
,
D
I
R
,
X
A
D
C
B
,
A
B
S
,
Y
S
B
C
B
,
A
B
S
,
Y
A
D
C
B
,
A
B
S
S
B
C
B
,
A
B
S
A
D
C
B
,
A
B
S
,
X
S
B
C
B
,
A
B
S
,
X
A
D
C
B
,
A
B
L
S
B
C
B
,
A
B
L
A
D
C
B
,
A
B
L
,
X
S
B
C
B
,
A
B
L
,
X
D
3
–D
0
D
7
–D
4
I
N
S
T
R
U
C
T
I
O
N
C
O
D
E
T
A
B
L
E
1
1
(
T
h
e
f
i
r
s
t
w
o
r
d
s
c
o
d
e
o
f
e
a
c
h
i
n
s
t
r
u
c
t
i
o
n
i
s
A
1
1
6
)
H
e
x
a
d
e
c
i
m
a
l
n
o
t
a
t
i
o
n
0123456789ABCDEF
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
0
0
00
0
0
10
0
1
00
0
1
10
1
0
00
1
0
10
1
1
00
1
1
11
0
0
01
0
0
11
0
1
01
0
1
11
1
0
01
1
0
11
1
1
01
1
1
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
T
B
D
,
0
I
M
P
T
B
D
,
1
I
M
P
T
B
D
,
2
I
M
P
T
B
D
,
3
I
M
P
T
D
B
,
0
I
M
P
T
D
B
,
1
I
M
P
T
D
B
,
2
I
M
P
T
D
B
,
3
I
M
P
T
B
S
I
M
P
T
S
B
I
M
P
A
D
C
B
,
I
M
M
S
B
C
B
,
I
M
M
A
D
C
B
B
,
I
M
MS
B
C
B
B
,
I
M
M
D
3
–D
0
D
7
–D
4
I
N
S
T
R
U
C
T
I
O
N
C
O
D
E
T
A
B
L
E
12
(
T
h
e
f
i
r
s
t
w
o
r
d
s
c
o
d
e
o
f
e
a
c
h
i
n
s
t
r
u
c
t
i
o
n
i
s
B
1
1
6
)
H
e
x
a
d
e
c
i
m
a
l
n
o
t
a
t
i
o
n
APPENDIX
Appendix 5. Hexadecimal instruction code table
7902 Group User’s Manual 21-53
0123456789ABCDEF
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
0
0
00
0
0
10
0
1
00
0
1
10
1
0
00
1
0
10
1
1
00
1
1
11
0
0
01
0
0
11
0
1
01
0
1
11
1
0
01
1
0
11
1
1
01
1
1
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
D
E
B
N
E
D
I
R
/
I
M
M
,
R
E
L
A
S
R
,
#
n
A
A
S
L
,
#
n
A
R
O
L
,
#
n
A
L
S
R
,
#
n
A
R
O
R
,
#
n
A
D
3
–D
0
D
7
–D
4
I
N
S
T
R
U
C
T
I
O
N
C
O
D
E
T
A
B
L
E
1
3
(
T
h
e
f
i
r
s
t
w
o
r
d
s
c
o
d
e
o
f
e
a
c
h
i
n
s
t
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c
t
i
o
n
i
s
C
1
1
6
)
H
e
x
a
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c
i
m
a
l
n
o
t
a
t
i
o
n
0123456789ABCDEF
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
0
0
00
0
0
10
0
1
00
0
1
10
1
0
00
1
0
10
1
1
00
1
1
11
0
0
01
0
0
11
0
1
01
0
1
11
1
0
01
1
0
11
1
1
01
1
1
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
D
E
B
N
E
A
B
S
/
I
M
M
,
R
E
L
A
S
R
D
,
#
n
E
A
S
L
D
,
#
n
E
R
O
L
D
,
#
n
E
L
S
R
D
,
#
n
E
R
O
R
D
,
#
n
E
D
3
–D
0
D
7
–D
4
I
N
S
T
R
U
C
T
I
O
N
C
O
D
E
T
A
B
L
E
1
4
(
T
h
e
f
i
r
s
t
w
o
r
d
s
c
o
d
e
o
f
e
a
c
h
i
n
s
t
r
u
c
t
i
o
n
i
s
D
1
1
6
)
H
e
x
a
d
e
c
i
m
a
l
n
o
t
a
t
i
o
n
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual 21-55
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual
21-54
IMP
IMM
A
DIR
DIR, X
DIR, Y
(DIR)
(DIR, X)
(DIR), Y
L(DIR)
L(DIR), Y
ABS
ABS, X
ABS, Y
ABL
ABL, X
(ABS)
L(ABS)
(ABS, X)
STK
REL
DIR, b, R
ABS, b, R
SR
(SR), Y
BLK
Multiplied
accumulation
op
n
#
C
Z
I
D
x
m
V
N
IPL
+
÷
| |
Acc
AccH
AccL
A
AH
AL
B
BH
BL
E
EH
EL
X
XH
XL
Y
YH
YL
S
REL
PC
PCH
PCL
PG
DT
DPR0
DPR0H
DPR0L
DPRn
DPRnH
DPRnL
PS
PSH
PSL
PSL(bit n)
M
M(S)
M(bit n)
Mn
IMM
IMMn
IMMH
IMML
ADH
ADM
ADL
EAR
EARH
EARL
imm
immn
dd
i
i1, i2
source
dest
SymbolDescription Description
Implied addressing mode
Immediate addressing mode
Accumulator addressing mode
Direct addressing mode
Direct indexed X addressing mode
Direct indexed Y addressing mode
Direct indirect addressing mode
Direct indexed X indirect addressing mode
Direct indirect indexed Y addressing mode
Direct indirect long addressing mode
Direct indirect long indexed Y addressing mode
Absolute addressing mode
Absolute indexed X addressing mode
Absolute indexed Y addressing mode
Absolute long addressing mode
Absolute long indexed X addressing mode
Absolute indirect addressing mode
Absolute indirect long addressing mode
Absolute indexed X indirect addressing mode
Stack addressing mode
Relative addressing mode
Direct bit relative addressing mode
Absolute bit relative addressing mode
Stack pointer relative addressing mode
Stack pointer relative indirect indexed Y addressing
mode
Block transfer addressing mode
Multiplied accumulation addressing mode
Instruction code (Op code)
Number of cycles
Number of bytes
Carry flag
Zero flag
Interrupt disable flag
Decimal operation mode flag
Index register length selection flag
Data length selection flag
Overflow flag
Negative flag
Processor interrupt priority level
Addition
Subtraction
Multiplication
Division
Logical AND
Logical OR
Logical exclusive OR
Absolute value
Negation
Movement to the arrow direction
Movement to the arrow direction
Exchange
Accumulator
Accumulator’s high-order 8 bits
Accumulator’s low-order 8 bits
Accumulator A
Accumulator A’s high-order 8 bits
Accumulator A’s low-order 8 bits
Accumulator B
Accumulator B’s high-order 8 bits
Accumulator B’s low-order 8 bits
Accumulator E
Accumulator E’s high-order 16 bits (Accumulator B)
Accumulator E’s low-order 16 bits (Accumulator A)
Index register X
Index register X’s high-order 8 bits
Index register X’s low-order 8 bits
Index register Y
Index register Y’s high-order 8 bits
Index register Y’s low-order 8 bits
Stack pointer
Relative address
Program counter
Program counter’s high-order 8 bits
Program counter’s low-order 8 bits
Program bank register
Data back register
Direct page register 0
Direct page register 0’s high-order 8 bits
Direct page register 0’s low-order 8 bits
Direct page register n
Direct page register n’s high-order 8 bits
Direct page register n’s low-order 8 bits
Processor status register
Processor status register’s high-order 8 bits
Processor status register’s low-order 8 bits
nth bit in processor status register
Contents of memory
Contents of memory at address indicated by stack
pointer
nth bit of memory
n-bit memory’s address or contents
Immediate value (8 bits or 16 bits)
n-bit immediate value
16-bit immediate value’s high-order 8 bits
16-bit immediate value’s low-order 8 bits
Value of 24-bit address’s high-order 8 bits (A23–A16)
Value of 24-bit address’s middle-order 8 bits (A15–A8)
Value of 24-bit address’s low-order 8 bits (A7–A0)
Effective address (16 bits)
Effective address’s high-order 8 bits
Effective address’s low-order 8 bits
8-bit immediate value
n-bit immediate value
Displacement for DPR (8 bits or 16 bits)
Number of transfer bytes, rotation or repeated operations
Number of registers pushed or pulled
Operand to specify transfer source
Operand to specify transfer destination
Symbol
Appendix 6. Machine instructions
Note: For an instruction of which “Operation length (Bit)” = 16/8 is executed in the bit length described
below.
• 16-bit length when m = 0 or x = 0.
• 8-bit length when m = 1 or x = 1.
For an instruction of which “Operation length (Bit)” = 8 or 32 is executed in 8-bit or 32-bit length
regardless of the contents of flags m and x.
ABS
op n # op n #
ABS, X
op n #
ABS, Y
op n #
ABL
op n #
ABL, X
op n #
(ABS)
op n #
L(ABS)
op n #
(ABS, X) op n #
STK
op n #
REL
op n #
DIR, b, R
op n #
ABS, b, R
op n #
SR
op n #
(SR), Y
op n #
BLK
op n #
MAA
10 9 8 7 6
5 4 3 2 1
0
IPL
N
V
m x D
I Z C
Addressing Modes Processor Status register
L(DIR), Y
Function Operation
length (Bit)
Addressing Modes
op n #
IMP IMM A DIR DIR, X DIR, Y (DIR)
(DIR, X) (DIR), Y
Symbol
L(DIR)
op n #op n #op n # op n # op n #op n #op n #op n #op n #op n #
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual 21-57
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual
21-56
21 7 4
9E 21 8 4
96 21 8 5
9C 21 9 5
9D 21 8 3
93 21 11 3
94
2E 3 3 2F 4 3 11 5 4
26 11 6 5
2D
11 5 5
2C 11 5 3
93 11 8 3
24
81 4 4
2E 81 5 4
2F 91 5 4
26 91 6 5
2D
91 5 5
2C 91 5 3
23 91 8 3
24
•• •0V•• Z0
•• NV•• ZC
•• NV•• ZC
•• NV•• ZC
21 8 4
9F
•• NV•• ZC
21 5 4
8E 21 6 4
8F 21 6 4
86 21 7 5
8D
21 6 5
8C 21 6 3
83 21 9 3
84
A1 7 4
8E A1 8 4
8F A1 8 4
86 A1 9 5
8D
A1 8 5
8C A1 8 3
83 A1 11 3
84
•• 0V•• Z0
•• NV•• ZC
•• NV•• ZC
9E 6 3 9F 7 3 11 8 4
96 11 9 5
9D
11 8 5
9C 11 8 3
93 11 11 3
94
•• NV•• ZC
51 7 5
07
•• NV•• ZC
51 7 5
06
51 10 8
87
•• NV•• ZC
•• NV•• •ZC
•• NV•• ZC
•• NV•• •ZC
21 12 3
99
11 9 3
29
91 9 3
29
21 10 3
89
A1 12 3
89
7900 Series Machine Instructions
Acc| Acc |ABS
(Note 1)
E1 3 1
81 4 2
E1
31 4 6
1C 21 7 3
9A 21 8 3
9B 21 9 3
90 21 10 3
91 21 10 3
98 21 11 3
92
11 7 3
21
11 6 3
20
2B 4 226 1 2 2A 3 2 11 7 3
28 11 8 3
22
91 7 3
21
91 6 3
20
81 5 3
2B
81 2 3
26 81 4 3
2A 91 7 3
28 91 8 3
22
29 1 2
81 2 3
29
16/8
32
16/8
8
16/8
21 8 3
81
21 7 3
80
21 6 3
8B
31 3 3
87 21 5 3
8A 21 8 3
88 21 9 3
82
A1 10 3
81
A1 9 3
80
A1 8 3
8B
B1 3 3
87 A1 7 3
8A A1 10 3
88 A1 11 3
82
AccAcc + M + CADC
(Notes 1 and
2)
E| E |ABSD
AccLAccL + IMM8 + CADCB
(Note 1)
31 5 2
90
31 3 3
1A
B1 3 3
1A
32
8
AccLAccL + IMM8
EE + M32 + C
ADD
(Notes 1 and
2)
ADDB
(Note 1)
AccAcc + M
ADCD
11 12 3
99
SS + IMM8ADDS
M8M8 + IMM8ADDMB
MM + IMM
EE + M32ADDD
ADDM
(Note 3)
M32M32 + IMM32ADDMD
11 10 3
91
11 9 3
90
9B 7 22D 3 5
51 7 4
03
11 10 3
98 11 11 3
92
51 7 4
02
51 10 7
83
31 2 3
0A
9A 6 2
YY + IMM (IMM = 0 to 31)
ADDX
ADDY
(Note 4)
XX + IMM (IMM = 0 to 31)
01 2 2
01 2 2
20
+
imm
32
16/8
8
32
16
16/8
16/8
ABS
op n # op n #
ABS, X
op n #
ABS, Y
op n #
ABL
op n #
ABL, X
op n #
(ABS)
op n #
L(ABS)
op n #
(ABS, X) op n #
STK
op n #
REL
op n #
DIR, b, R
op n #
ABS, b, R
op n #
SR
op n #
(SR), Y
op n #
BLK
op n #
MAA
10 9 8 7 6
5 4 3 2 1
0
IPL
N
V
m x D
I Z C
Addressing Modes Processor Status register
L(DIR), Y
Function Operation
length (Bit)
Addressing Modes
op n #
IMP IMM A DIR DIR, X DIR, Y (DIR)
(DIR, X) (DIR), Y
Symbol
L(DIR)
op n #op n #op n # op n # op n #op n #op n #op n #op n #op n #
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual 21-59
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual
21-58
••N••••Z
6E 3 3 6F 4 3 11 5 4
66 11 6 5
6D
11 5 5
6C 11 5 3
63 11 8 3
64
81 4 4
6E 81 5 4
6F 91 5 4
66 91 6 5
6D
91 5 5
6C 91 5 3
63 91 8 3
64
21 7 4
0E 21 8 4
0F
••N••••ZC
••N••••Z
••N••••Z
••N••••Z
••N••••ZC
••N••••Z
51 7 5
67
51 7 5
66
51 10 8
E7
••N••••ZC
21 7 4
4E 21 8 4
4F
••N••••ZC
••N••••ZC
b15 … b0 C
b7 … b0 C
b15 … b0 C
b7 … b0 C
C b15 … b0 0
C b7 … b0 0
C b15 … b0 0
C b7 … b0 0
Arithmetic shift to the right by n bits
(n = 0 to 15)
m = 0
m = 1
Arithmetic shift to the right by 1 bit
m = 0
Acc or M16
m = 1
AccL or M8
Arithmetic shift to the left by n
bits (n = 0 to 31)
E
Arithmetic shift to the left by n
bits (n = 0 to 15)
m = 0 A
m = 1 AL
Arithmetic shift to the left by 1 bit
m = 0
Acc or M16
m = 1
AccL or M8
11
9 3
69
91
9
3
69
ASL
(Note 1)
M32M32 IMM32
ASL #n
(Note 4)
ANDMD
MM IMMANDM
(Note 3)
AccLAccL IMM8ANDB
(Note 1)
M8M8 IMM8ANDMB
81 4 3
6A
AccAcc M
11 7 3
61
11 6 3
60
66 1 2 11 7 3
68 11 8 3
62
91 7 3
61
91 6 3
60
81 5 3
6B
81 2 3
66 91 7 3
68
AND
(Notes 1 and
2)
91 8 3
62
6A 3 2 6B 4 2
23 1 2
81 2 3
23
51 7 4
63
51 7 4
62
51 10 7
E3
03 1 1
81 2 2
03
21 7 3
0A 21 8 3
0B
C1 6 2
40 +
+ imm
imm
ASLD #n
(Note 4)
64
1
121 7 3
4A 21 8 3
4B
81 2 2
64
ASR
(Note 1)
D1 8 2
40 +
+ imm
imm
C b31 … b0 0
ASR #n
(Note 4)
C1 6 2
80 +
+ imm
imm
16/8
8
16/8
8
32
16/8
16/8
32
16/8
16/8
A
AL
ABS
op n # op n #
ABS, X
op n #
ABS, Y
op n #
ABL
op n #
ABL, X
op n #
(ABS)
op n #
L(ABS)
op n #
(ABS, X) op n #
STK
op n #
REL
op n #
DIR, b, R
op n #
ABS, b, R
op n #
SR
op n #
(SR), Y
op n #
BLK
op n #
MAA
10 9 8 7 6
5 4 3 2 1
0
IPL
N
V
m x D
I Z C
Addressing Modes Processor Status register
L(DIR), Y
Function Operation
length (Bit)
Addressing Modes
op n #
IMP IMM A DIR DIR, X DIR, Y (DIR)
(DIR, X) (DIR), Y
Symbol
L(DIR)
op n #op n #op n # op n # op n #op n #op n #op n #op n #op n #
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual 21-61
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual
21-60
•• ••• ••
41 9 6
5E
41 9 5
5A
•• ••• ••
57 8 552 8 4
41 9 6
4E
41 9 5
4A
•• ••• ••
47 8 542 8 4
90 6 2
B0 6 2
•• ••• ••
F0 6 2
••N••••ZC
•• ••• ••
•• ••• ••
•• ••• ••
•• ••• ••
•• ••• ••
C0 6 2
80 6 2
40 6 2
•• ••• ••
•• ••• ••
A0 6 2
•• ••• ••
60 6 2
•• ••• ••
E0 6 2
Arithmetic shift to the right by n bits
(n = 0 to 31)
if C = 0
then PCPC + 2 + REL (–128 to
+127)
BCC
if M(bit n) = 0
then PCPC + cnt + REL (–128
to +127)
(cnt: Number of bytes of instruction)
BBC
(Note 3)
ASRD #n
(Note 4)
if M8(bit n) = 0
then PCPC + cnt + REL (–128
to +127)
(cnt: Number of bytes of instruction)
BBCB
if M(bit n) = 1
then PCPC + cnt + REL (–128
to +127)
(cnt: Number of bytes of instruction)
BBS
(Note 3)
if M8(bit n) = 1
then PCPC+cnt+REL (–128 to
+127)
(cnt: Number of bytes of instruction)
BBSB
if C = 1
then PCPC + 2 + REL (–128 to
+127)
BCS
if Z = 1
then PCPC + 2 + REL (–128 to
+127)
BEQ
D1 8 2
80 +
+ imm
imm
BGE
BGT
BGTU
BLE
BLEU
if Z = 0 and NV = 0
then PCPC + 2 + REL (–128 to
+127)
if C = 1 and Z = 0
then PCPC + 2 + REL (–128 to
+127)
BLT
32
16/8
8
16/8
8
if NV = 0
then PCPC + 2 + REL (–128 to
+127)
if Z = 1 or NV = 1
then PCPC + 2 + REL (–128 to
+127)
if C = 0 or Z = 1
then PCPC + 2 + REL(–128 to
+127)
if NV = 1
then PCPC + 2 + REL (–128 to
+127)
E
b31 … b0 C
ABS
op n # op n #
ABS, X
op n #
ABS, Y
op n #
ABL
op n #
ABL, X
op n #
(ABS)
op n #
L(ABS)
op n #
(ABS, X) op n #
STK
op n #
REL
op n #
DIR, b, R
op n #
ABS, b, R
op n #
SR
op n #
(SR), Y
op n #
BLK
op n #
MAA
10 9 8 7 6
5 4 3 2 1
0
IPL
N
V
m x D
I Z C
Addressing Modes Processor Status register
L(DIR), Y
Function Operation
length (Bit)
Addressing Modes
op n #
IMP IMM A DIR DIR, X DIR, Y (DIR)
(DIR, X) (DIR), Y
Symbol
L(DIR)
op n #op n #op n # op n # op n #op n #op n #op n #op n #op n #
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual 21-63
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual
21-62
•• ••• ••
D0 6 2
•• ••• ••
30 6 2
10 6 2
•• ••• ••
•• ••• ••
A7 5 3
20 5 2
•• ••• •• 1
50 6 2
•• ••• ••
70 6 2
•• ••• ••
71 10 5
E
+
n
71 10 5
C0
+
n
•• ••• ••
•• ••• ••
•• ••• ••
F8
7
2
|
FF
BMI
BNE
BPL
PCPC + cn t + REL
(BRA:–128 to +127,
BRAL: –32768 to +32767)
(cnt: Number of bytes of instruction)
PGPG + 1
(When carry occurs)
PGPG – 1
(When borrow occurs)
BRA/BRAL
(Note 5)
PCPC + 2
M(S)PG
SS – 1
M(S)PCH
SS – 1
M(S)PCL
SS – 1
M(S)PSH
SS – 1
M(S)PSL
SS – 1
I1
PCLADL
PCHADM
PG0016 or FF16
BRK
(Note 6)
00 15 2
74
BVC
BVS
BSR
BSS
(Note 7)
BSC
(Note 7)
01 7 3
A0
+
n
71 11 4
A0
+
n
01 7 3
80
+
n
71 11 4
80
+
n
(S)PC + 2
PCPC + 2 + REL (–1024 to
+1023)
16/8
16/8
if N = 1
then PCPC + 2 + REL (–128 to
+127)
if Z = 0
then PCPC + 2 + REL (–128 to
+127)
if N = 0
then PCPC + 2 + REL (–128 to
+127)
if A(bit n) or M(bit n) = 0
(n = 0 to 15), then PCPC + cnt +
REL (–128 to +127)
(cnt: Number of bytes of instruction)
if A(bit n) or M(bit n) = 1 (n = 0 to
15), then PCPC + cnt + REL
(–128 to +127)
(cnt: Number of bytes of instruction)
if V = 0
then PCPC + 2 + REL (–128 to
+127)
if V = 1
then PCPC + 2 + REL (–128 to
+127)
ABS
op n # op n #
ABS, X
op n #
ABS, Y
op n #
ABL
op n #
ABL, X
op n #
(ABS)
op n #
L(ABS)
op n #
(ABS, X) op n #
STK
op n #
REL
op n #
DIR, b, R
op n #
ABS, b, R
op n #
SR
op n #
(SR), Y
op n #
BLK
op n #
MAA
10 9 8 7 6
5 4 3 2 1
0
IPL
N
V
m x D
I Z C
Addressing Modes Processor Status register
L(DIR), Y
Function Operation
length (Bit)
Addressing Modes
op n #
IMP IMM A DIR DIR, X DIR, Y (DIR)
(DIR, X) (DIR), Y
Symbol
L(DIR)
op n #op n #op n # op n # op n #op n #op n #op n #op n #op n #
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual 21-65
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual
21-64
•• ••• •• 0
•• ••• •• 0•
•• •••0
•• NV•• Z C
•• NV•• Z C
•••
••0•••••1
••0••••1
••0••••1
••0••••1
D7 5 3
C7 5 3
•• ••• ••
•• ••• ••
•• NV•• Z C
•• NV•• Z C
Specified flag
becomes “0.”
C0CLC
I0CLI
m0CLM
45 3 1
14 1 1
15 3 1
CBNE
(Notes 1 and
3)
CBNEB
(Note 1)
B6 6 3 41 9 5
7A
81 7 4
B6
B2 6 3 72 8 4
81 7 4
B2
PSL(bit n)0
(n = 0 to 7. Multiple bits can
be specified.)
CLP
98 4 2
Acc0CLR
(Note 1)
AccL0016CLRB
(Note 1)
54 1 1
81 2
2
54
44 1 1
81 2 2
44
X0CLRX
Y0CLRY
E4 1 1
F4 1 1
M0CLRM
M80016CLRMB
D2 5 2
C2 5 2
A6 6 3 41 9 5
6A
81 7 4
A6
CBEQ
(Notes 1 and
3)
CBEQB
(Note 1)
A2 6 3 62 8 4
81 7 4
A2
16/8
8
16/8
8
16/8
8
16/8
8
16/8
16/8
if Acc = IMM or M = IMM
then PCPC + cnt + REL(–128 to
+127)
(cnt: Number of bytes of instruction)
if AccL = IMM8 or M8 = IMM8
then PCPC + cnt + REL (–128 to
+127)
(cnt: Number of bytes of instruction)
if Acc IMM or M IMM
then PCPC + cnt + REL (–128 to
+127)
(cnt: Number of bytes of instruction)
if AccL IMM8 or M8 IMM8
then PCPC+cnt+REL(–128 to
+127)
(cnt: Number of bytes of instruction)
ABS
op n # op n #
ABS, X
op n #
ABS, Y
op n #
ABL
op n #
ABL, X
op n #
(ABS)
op n #
L(ABS)
op n #
(ABS, X) op n #
STK
op n #
REL
op n #
DIR, b, R
op n #
ABS, b, R
op n #
SR
op n #
(SR), Y
op n #
BLK
op n #
MAA
10 9 8 7 6
5 4 3 2 1
0
IPL
N
V
m x D
I Z C
Addressing Modes Processor Status register
L(DIR), Y
Function Operation
length (Bit)
Addressing Modes
op n #
IMP IMM A DIR DIR, X DIR, Y (DIR)
(DIR, X) (DIR), Y
Symbol
L(DIR)
op n #op n #op n # op n # op n #op n #op n #op n #op n #op n #
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual 21-67
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual
21-66
11 5 4
46
•• ••0••
•• NV•• •Z C
11 6 5
4D 11 8 3
44
91 8 3
44
91 5 3
43
91 5 4
46 91 5 5
4C
81 5 4
4F
4F 4 34E 3 3
81 4 4
4E
11 5 5
4C
91 6 5
4D
11 5 3
43
•• NV•• Z C
•• NV•• Z C
•• NV•• Z C
•• NV•• Z C
•• NV•• Z C
11 8 4
B6 11 9 5
BD 11 11 3
B4
BF 7 3BE 6 3 11 8 5
BC 11 8 3
B3
51 5 5
27
51 5 5
26
51 7 8
A7
41 4 4
2E
•• NV•• Z C
41 4 4
3E
•• NV•• •Z C
••N••••Z
97 6 341 8 4
9F
••N••••Z
••N••••Z
•• NV•• IZ C
21 17 4
EF 21 17 4
E6 21 18 5
ED 21 17 3
E3 21 20 3
E4
21 16 4
EE 21 17 5
EC
•• ••• ••
D111 5
E0
+
imm
11 9 3
49
91 9 3
49
11 12 3
B9
V0CLV
65 1 1
Acc – MCMP
(Notes 1 and
2)
46 1 2 4A 3 2
81 4 3
4A
4B 4 2
81 5 3
4B
11 6 3
40
91 6 3
40
11 7 3
41
91 7 3
41
11 7 3
48
91 7 3
48
11 8 3
42
91 8 3
42
81 2 3
46
AccL – IMM8CMPB
(Note 1)
E – M32CMPD
M – IMMCMPM
(Note 3)
M8 – IMM8CMPMB
M32 – IMM32CMPMD
38 1 2
81 2 3
38
3C 3 5 BA 6 2 BB 7 2 11 9 3
B0 11 10 3
B1 11 10 3
B8 11 11 3
B2
51 5 4
23
51 5 4
22
51 7 7
A3
X – MCPX
(Note 8)
E6 1 2 22 3 2
Y – MCPY
(Note 8)
F6 1 2 32 3 2
21 21 3
E9
Acc
Acc – 1
or
M
M – 1
DEC
(Note 1)
B3 1 1 41 8 3
9B
81 2 2
B3
X
X – 1DEX
E3 1 1
92 6 2
MM – IMM(IMM = 0 to 31)
if M 0,
then PCPC + cnt + REL
(–128 to +127)
(cnt: Number of bytes of instruction)
DEBNE
(Note 4)
F3 1 1
Y
Y – 1DEY
31 15 3
E7 21 16 3
EA 21 17 3
EB 21 18 3
E0 21 19 3
E1 21 19 3
E8 21 20 3
E2
A (quotient) (B, A) ÷ M
B (remainder)
DIV
(Notes 2, 9,
and 10)
C112 4
A0
+
imm
16/8
8
32
16/8
8
32
16/8
16/8
16/8
16/8
16/8
16/8
16/8
ABS
op n # op n #
ABS, X
op n #
ABS, Y
op n #
ABL
op n #
ABL, X
op n #
(ABS)
op n #
L(ABS)
op n #
(ABS, X) op n #
STK
op n #
REL
op n #
DIR, b, R
op n #
ABS, b, R
op n #
SR
op n #
(SR), Y
op n #
BLK
op n #
MAA
10 9 8 7 6
5 4 3 2 1
0
IPL
N
V
m x D
I Z C
Addressing Modes Processor Status register
L(DIR), Y
Function Operation
length (Bit)
Addressing Modes
op n #
IMP IMM A DIR DIR, X DIR, Y (DIR)
(DIR, X) (DIR), Y
Symbol
L(DIR)
op n #op n #op n # op n # op n #op n #op n #op n #op n #op n #
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual 21-69
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual
21-68
•• NV•• IZ C
21 24 4
F6 21 25 5
FD 21 24 3
F3 21 27 3
F4
21 23 4
FE 21 24 5
FC
21 24 4
FF
•• ••• ••
•• ••• ••
••N••••Z
••N••••Z
••N••••Z
••N••••Z
51 7 5
77
51 7 5
76
51 10 8
F7
••N••••Z
7E 3 3 7F 4 3 11 5 4
76 11 5 5
7C 11 6 5
7D 11 5 3
73 11 8 3
74
81 4 4
7E 81 5 4
7F 91 5 4
76 91 5 5
7C 91 6 5
7D 91 5 3
73 91 8 3
74
•• •0 •• Z
••N••••Z
••N••••Z
•• •0 •• Z
21 28 3
F9
A (quotient) (B, A) ÷ M
B (remainder) (Signed)
DIVS
(Notes 2, 9,
and 10)
31 22 3
F7 21 23 3
FA 21 24 3
FB 21 25 3
F0 21 26 3
F1 21 26 3
F8 21 27 3
F2
XX – IMM (IMM = 0 to 31)
if X 0,
then PCPC + cnt + REL
(–128 to +127)
(cnt: Number of bytes of instruction)
DXBNE
(Note 4)
YY – IMM (IMM = 0 to 31)
if Y0,
then PCPC + cnt + REL
(–128 to +127)
(cnt: Number of bytes of instruction)
DYBNE
(Note 4)
01 7 3
C0
+
imm
01 7 3
E0
+
imm
11 9 3
79
91 9 3
79
AccLAccLIMMBEORB
(Note 1)
MMIMMEORM
(Note 3)
M8M8IMM8EORMB
M32M32IMM32EORMD
33 1 2
81 2 3
33
51 7 4
73
51 7 4
72
51 10 7
F3
91 8 3
72
11 8 3
72
AccAccMEOR
(Notes 1 and
2)
76 1 2 7A 3 2 7B 4 2 11 6 3
70 11 7 3
71 11 7 3
78
81 4 3
7A 81 5 3
7B 91 6 3
70 91 7 3
71 91 7 3
78
81 2 3
76
EXTZD
EXTZ
(Note 1)
81 2 2
34
34 1 1
00000000
b15 b8 b7b0
AccAccL (Extension sign)
(Bit 7 of AccL = 0)
EXTS
(Note 1)
(Bit 7 of AccL = 1)
35 1 1
00000000 0
b15 b7b0
11111111 1
b15 b7b0
81 2 2
35
EXTSD
31 5 2
B0
31 3 2
A0
EEL(= A) (Extension sign)
(Bit 15 of A = 0)
(Bit 15 of A = 1)
000016 0
b15 b0 b15 b0
FFFF16 1
b15 b0 b15 b0
000016
b15 b0 b15 b0
EH(B) EL(A)
EH(B) EL(A)
EH(B) EL(A)
16/8
16/8
16/8
16/8
8
16/8
8
32
16
32
16
32
AccAccL (Extension zero)
EEL(= A) (Extension zero)
AccHAccL
AccHAccL
AccHAccL
ABS
op n # op n #
ABS, X
op n #
ABS, Y
op n #
ABL
op n #
ABL, X
op n #
(ABS)
op n #
L(ABS)
op n #
(ABS, X) op n #
STK
op n #
REL
op n #
DIR, b, R
op n #
ABS, b, R
op n #
SR
op n #
(SR), Y
op n #
BLK
op n #
MAA
10 9 8 7 6
5 4 3 2 1
0
IPL
N
V
m x D
I Z C
Addressing Modes Processor Status register
L(DIR), Y
Function Operation
length (Bit)
Addressing Modes
op n #
IMP IMM A DIR DIR, X DIR, Y (DIR)
(DIR, X) (DIR), Y
Symbol
L(DIR)
op n #op n #op n # op n # op n #op n #op n #op n #op n #op n #
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual 21-71
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual
21-70
••N••••Z
41 8 4
8F
••N••••Z
••N••••Z
•• ••• •• ••
9C 4 3 AC 5 4 31 7 4
5C 31 9 4
5D BC 7 3
87 6 3
9D 6 3 AD 7 4 BD 8 3
•• ••• •• ••
1F 4 3
81 5 4
1F
1E 3 3
81 4 4
1E
1D 5 4
81 6 5
1D
1C 4 4
81 5 5
1C
11 5 4
16
91 5 4
16
11 8 3
14
91 8 3
14
11 5 3
13
91 5 3
13
••N••••Z
0F 4 30E 3 3 0D 5 40C 4 411 5 4
06 11 8 3
04
11 5 3
03
••0••••Z
81 5 5
0C
81 5 4
0F
81 4 4
0E 81 6 5
0D
91 5 4
06 91 8 3
04
91 5 3
03
INC
(Note 1) Acc
Acc + 1
or
M
M + 1
A3 1 1
81 2 2
A3
82 6 2 41 8 3
8B
C3 1 1
D3 1 1
INX X
X + 1
INY Y
Y + 1
JMP/JMPL When ABS specified
PCL
ADL
PCH
ADM
When ABL specified
PCL
ADL
PCH
ADM
PG
ADH
When (ABS) specified
PCL
(ADM, ADL)
PCH
(ADM, ADL + 1)
When L(ABS) specified
PCL
(ADM, ADL)
PCH
(ADM, ADL + 1)
PG
(ADM, ADL + 2)
When (ABS,X) specified
PCL
(ADM, ADL + X)
PCH
(ADM, ADL + X + 1)
When ABS specified
M(S)
PCH
S
S–1
M(S)
PCL
S
S–1
PCL
ADL
PCH
ADM
When ABL specified
M(S)
PG
S
S – 1
M(S)
PCH
S
S – 1
M(S)
PCL
S
S – 1
PCL
ADL
PCH
ADM
PG
ADH
When (ABS,X) specified
M(S)
PCH
S
S – 1
M(S)
PCL
S
S – 1
PCL
(ADM, ADL + X)
PCH
(ADM, ADL + X + 1)
JSR/JSRL
19 8 2
81 9 3
19
09 8 2
81 2 3
16
Acc
MLDA
(Notes 1 and
2)
1A 3 2
81 4 3
1A
1B 4 2
81 5 3
1B
11 6 3
10
91 6 3
10
11 7 3
11
91 7 3
11
18 6 2
81 7 3
18
11 8 3
12
91 8 3
12
16 1 2
Acc
M8 (Extension zero)LDAB
(Note 1)
0A 3 2 0B 4 2 11 6 3
00 11 7 3
01 08 6 2 11 8 3
02
28 1 2
81 9 3
09
81 7 3
08
91 7 3
01
81 2 3
28 81 4 3
0A 81 5 3
0B 91 6 3
00 91 8 3
02
16/8
16/8
16/8
16/8
16
ABS
op n # op n #
ABS, X
op n #
ABS, Y
op n #
ABL
op n #
ABL, X
op n #
(ABS)
op n #
L(ABS)
op n #
(ABS, X) op n #
STK
op n #
REL
op n #
DIR, b, R
op n #
ABS, b, R
op n #
SR
op n #
(SR), Y
op n #
BLK
op n #
MAA
10 9 8 7 6
5 4 3 2 1
0
IPL
N
V
m x D
I Z C
Addressing Modes Processor Status register
L(DIR), Y
Function Operation
length (Bit)
Addressing Modes
op n #
IMP IMM A DIR DIR, X DIR, Y (DIR)
(DIR, X) (DIR), Y
Symbol
L(DIR)
op n #op n #op n # op n # op n #op n #op n #op n #op n #op n #
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual 21-73
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual
21-72
•• ••• •• ••
07 3 3
••N••••Z
41 5 4
06
17 3 3
••N••••Z
41 5 4
1F
8F 7 38E 6 3 8D 8 48C 7 411 8 4
86 11 11 3
84
11 8 3
83
••N••••Z
•• ••• •• ••
•• •0 •• Z
••0••••Z
21 7 4
2E
••0••••ZC
21 8 4
2F
••0••••ZC
••0••••ZC
0 b15 … b0 C
0 b7 … b0 C
0 b15 … b0 C
0 b7 … b0 C
Logical shift to the right by n bits (n =
0 to 15)
m = 0 A
m = 1 AL
Logical shift to the right by 1 bit
m = 0
Acc or M16
m = 1
AccL or M8
89 11 2
DTIMM8LDT
31 4 3
4A
XMLDX
(Note 8)
C6 1 2 02 3 2 41 5 3
05
YMLDY
(Note 8)
D6 1 2 12 3 2 41 5 3
1B
EM32LDAD
LDD n
(Notes 11
and 12)
LDXB XIMM8 (Extension zero)
8A 6 2 8B 7 2 11 9 3
80 11 10 3
81 88 9 2 11 11 3
82
2C 3 5
B8 11 2
?0
+
+
2 i
2 i
B8 13 4
?0
27 1 2
DPRnIMM16
(n = 0 to 3. Multiple DPRs can
be specified.)
LDYB YIMM8 (Extension zero)
37 1 2
LSR
(Note 1)
21 8 3
2B
43 1 1 21 7 3
2A
81 2 2
43
LSR #n
(Note 4)
LSRD #n
(Note 4)
C1 6 2
+
imm
D1 8 2
+
imm
32
16
8
16/8
16
16/8
16
16/8
16/8
32Logical shift to the right by n bits (n =
0 to 31) E
0 b31 … b0 C
ABS
op n #op n #
ABS, X
op n #
ABS, Y
op n #
ABL
op n #
ABL, X
op n #
(ABS)
op n #
L(ABS)
op n #
(ABS, X)op n #
STK
op n #
REL
op n #
DIR, b, R
op n #
ABS, b, R
op n #
SR
op n #
(SR), Y
op n #
BLK
op n #
MAA
IPL
N
V
m x D
I Z C
Destination Processor Status register
10 9 8 7 6
5 4 3 2 1
0
Destination
op n #
IMP IMM A DIR
Symbol
op n #op n # op n #
DIR, X DIR, Y (DIR)
(DIR, X) (DIR), Y
L(DIR)
op n #op n #op n #op n #op n #op n # op n #
Function Operation
length (Bit)
L(DIR), Y
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual 21-75
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual
21-74
•• ••• •• ••
•• ••• •• ••
•• ••• ••
•• ••• ••
96 4 431 6 5
57
78 5 4
79 6 4
7C 5 5
B9 4 431 6 5
3B
68 5 4
69 6 4
6C 5 5
61
3
2
30
+
+
+
4n
3n
n
61
3
2
70
+
+
+
5n
3n
n
71
3
2
70
+
+
+
6n
3n
n
61
3
2
B0
+
+
+
5n
4n
n
61
3
2
20
+
+
+
4n
3n
n
61
3
2
60
+
+
+
5n
3n
n
71
3
2
60
+
+
+
6n
3n
n
61
3
2
A0
+
+
+
5n
4n
n
MOVR
(Notes 7 and
13)
MOVRB
(Note 7)
m = 0
M16(dest1)M16(source1)
M16(dest n)M16(source n)
m = 1
M8(dest1) M8(source1)
M8(dest n)M 8(source n)
(n = 0 to 15)
M8(dest1) M8(source1)
M8(dest n)M 8(source n)
(n = to 15)
m = 0
M16(dest)M16(source)
m = 1
M8(dest)M8(source)
MOVM
(Note 2)
M8(dest)M8(source)
MOVMB
86 5 3 31 7 4
47
58 6 3
5C 6 4
5D 7 4
A9 5 331 7 4
3A
48 6 3
4C 6 4
4D 7 4
61
3
2
10
+
+
+
5n
2n
n
61
3
2
50
+
+
+
6n
2n
n
61
3
2
90
+
+
+
6n
3n
n
71
3
2
10
+
+
+
6n
3n
n
61
3
2
00
+
+
+
5n
2n
n
61
3
2
40
+
+
+
6n
2n
n
61
3
2
80
+
+
+
6n
3n
n
71
3
2
00
+
+
+
6n
3n
n
IMM
DIR
DIR, X
ABS
ABS, X
IMM
DIR
DIR, X
ABS
ABS, X
IMM
DIR
DIR, X
ABS
ABS, X
IMM
DIR
DIR, X
ABS
ABS, X
Source
16/8
8
16/8
8
SourceSourceSource
ABS
op n # op n #
ABS, X
op n #
ABS, Y
op n #
ABL
op n #
ABL, X
op n #
(ABS)
op n #
L(ABS)
op n #
(ABS, X) op n #
STK
op n #
REL
op n #
DIR, b, R
op n #
ABS, b, R
op n #
SR
op n #
(SR), Y
op n #
BLK
op n #
MAA
10 9 8 7 6
5 4 3 2 1
0
IPL
N
V
m x D
I Z C
Addressing Modes Processor Status register
L(DIR), Y
Function Operation
length (Bit)
Addressing Modes
op n #
IMP IMM A DIR DIR, X DIR, Y (DIR)
(DIR, X) (DIR), Y
Symbol
L(DIR)
op n #op n #op n # op n # op n #op n #op n #op n #op n #op n #
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual 21-77
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual
21-76
•• ••• •• ••
••N••••Z0
21 9 4
CE 21 10 4
CF 21 10 4
C6 21 10 5
CC
21 11 5
CD 21 10 3
C3 21 13 3
C4
••N••••Z0
21 9 4
DE 21 10 4
DF 21 10 4
D6 21 10 5
DC 21 11 5
DD
•• ••• ••
21 10 3
D3 21 13 3
D4
31 5 4
2B +
5 i
31 9 4
2A +
5 i
•• ••• ••
•• NV•• ZC
•• NV•• ZC
•• ••• ••
31 5 4
4C
••N•••• Z
••N•••• Z
51 7 5
36
51 10 8
B7
••N•••• Z
5E 3 3
81 4 4
5E
5F 4 3
81 5 4
5F
11 5 4
56
91 5 4
56
11 5 5
5C
91 5 5
5C
11 6 5
5D
91 6 5
5D
11 8 3
54
91 8 3
54
11 5 3
53
91 5 3
53
••N•••• Z
••N•••• Z
51 7 5
37
•• ••• ••
31 7 3
4B
21 14 3
C9
21 14 3
D9
MVP
(Note 16)
(B, A)A MMPY
(Notes 2 and
14)
21 10 3
CB
31 8 3
C7 21 9 3
CA 21 11 3
C0 21 12 3
C1 21 12 3
C8 21 13 3
C2
(B, A)A M (Signed)MPYS
(Notes 2 and
14)
21 10 3
DB
31 8 3
D7 21 9 3
DA 21 11 3
D0 21 12 3
D1 21 12 3
D8 21 13 3
D2
MVN
(Note 15)
PCPC + 1
When catty occurs in PC
PGPG + 1
NOP
74 1 1
Acc–AccNEG
(Note 1)
E–ENEGD
24 1 1
81 2 2
24
31 4 2
80
i: Number of transfer bytes
specified by accumulator A
()
()
11 9 3
59
91 9 3
59
M(S)IMMH
SS – 1
M(S)IMML
SS – 1
PEA
M8M8IMM8ORAMB
M32M32IMM32ORAMD
51 7 4
32
51 10 7
B3
MMIMMORAM
(Note 3)
56 1 2
AccAccMORA
(Notes 1 and
2)
81 2 3
56
5A 3 2
81
4 3
5A
5B 4 2
81 5 3
5B
11 6 3
50
91 6 3
50
11 7 3
51
91 7 3
51
11 7 3
58
91 7 3
58
11 8 3
52
91 8 3
52
AccLAccLIMM8ORAB
(Note 1)
63 1 2
81 2 3
63
51 7 4
33
M(S)M((DPRn) + dd + 1)
SS + 1
M(S)M((DPRn)+dd)
SS – 1 (n = 0 to 3)
PEI
16/8
16/8
16/8
16/8
16/8
32
16/8
8
16/8
8
32
16
16
i: Number of transfer bytes
specified by accumulator A
M(Y + k)M(X + k)
k = 0 to i – 1
M(Y–k)M(X–k)
k = 0 to i–1
ABS
op n # op n #
ABS, X
op n #
ABS, Y
op n #
ABL
op n #
ABL, X
op n #
(ABS)
op n #
L(ABS)
op n #
(ABS, X) op n #
STK
op n #
REL
op n #
DIR, b, R
op n #
ABS, b, R
op n #
SR
op n #
(SR), Y
op n #
BLK
op n #
MAA
10 9 8 7 6
5 4 3 2 1
0
IPL
N
V
m x D
I Z C
Addressing Modes Processor Status register
L(DIR), Y
Function Operation
length (Bit)
Addressing Modes
op n #
IMP IMM A DIR DIR, X DIR, Y (DIR)
(DIR, X) (DIR), Y
Symbol
L(DIR)
op n #op n #op n # op n # op n #op n #op n #op n #op n #op n #
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual 21-79
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual
21-78
•• ••• •• ••
31 6 4
4D
•• ••• ••
85 4 1
•• ••• ••
81 5 2
85
•• ••• •• ••
83 4 1
B8 12 2
01
0F
B8 11 2
01
+
| i
0F
•• ••• ••
31 4 2
60
•• ••• •• ••
•• ••• ••
B8 14 4
01
|
0F
B8 11 2
01
+ +
|
3 i 2 i
0F
•• ••• •• ••
A5 4 1
•• ••• •• ••
31 4 2
40
EARPC + IMM16
M(S)EARH
SS – 1
M(S)EARL
SS – 1
PER
m = 0
M(S)AH
SS – 1
M(S)AL
SS – 1
m = 1
M(S)AL
SS – 1
PHA
m = 0
M(S)BH
SS – 1
M(S)BL
SS – 1
m=1
M(S)BL
SS – 1
PHB
M(S)DPR0H
SS – 1
M(S)DPR0
L
SS – 1
PHD
PHD n
(Note 11)
M(S)PG
SS – 1
PHG
PHLD n
(Note 11)
M(S)DPRnH
SS – 1
M(S)DPRn
L
SS – 1 (n = 0 to 3)
When multiple DPRs are
specified, the above
operations are repeated.
M(S)DPRnH
SS – 1
M(S)DPRnL
SS – 1
DPRnIMM16 (n = 0 to 3)
When multiple DPRs are
specified, the above
operations are repeated.
M(S)PSH
SS – 1
M(S)PSL
SS – 1
PHP
M(S)DT
SS – 1
PHT
16
16/8
16/8
16
16
8
16
16
8
ABS
op n # op n #
ABS, X
op n #
ABS, Y
op n #
ABL
op n #
ABL, X
op n #
(ABS)
op n #
L(ABS)
op n #
(ABS, X) op n #
STK
op n #
REL
op n #
DIR, b, R
op n #
ABS, b, R
op n #
SR
op n #
(SR), Y
op n #
BLK
op n #
MAA
10 9 8 7 6
5 4 3 2 1
0
IPL
N
V
m x D
I Z C
Addressing Modes Processor Status register
L(DIR), Y
Function Operation
length (Bit)
Addressing Modes
op n #
IMP IMM A DIR DIR, X DIR, Y (DIR)
(DIR, X) (DIR), Y
Symbol
L(DIR)
op n #op n #op n # op n # op n #op n #op n #op n #op n #op n #
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual 21-81
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual
21-80
E5 4 1
•• ••• •• ••
C5 4 1
•• ••• •• ••
••N••••Z
95 4 1
81 5 2
95
••N••••Z
93 5 1
•• ••• •• ••
77 11 2
?0
•• ••• •• ••
B5 5 1
31 6 2
50
••N••••Z
Value restored from
stack
77 8 2
?0
+
3 i
x = 0
M(S)XH
SS – 1
M(S)XL
SS – 1
x = 1
M(S)XL
SS – 1
PHX
x = 0
M(S)YH
SS – 1
M(S)YL
SS – 1
x = 1
M(S)YL
SS – 1
PHY
m = 0
SS + 1
ALM(S)
SS + 1
AHM(S)
m = 1
SS + 1
ALM(S)
PLA
m = 0
SS + 1
BLM(S)
SS + 1
BHM(S)
m = 1
SS + 1
BLM(S)
PLB
SS + 1
DPR0LM(S)
SS + 1
DPR0HM(S)
PLD
PLD n
(Notes 11 and
12)
SS + 1
DPRnLM(S)
SS + 1
DPRnHM(S) (n = 0 to 3)
When multiple DPRs are specified,
the above operations are
repeated.
PLP
(Note 22) SS + 1
PSLM(S)
SS + 1
PSHM(S)
PLT SS + 1
DTM(S)
16/8
16/8
16/8
16/8
16
16
16
8
ABS
op n # op n #
ABS, X
op n #
ABS, Y
op n #
ABL
op n #
ABL, X
op n #
(ABS)
op n #
L(ABS)
op n #
(ABS, X) op n #
STK
op n #
REL
op n #
DIR, b, R
op n #
ABS, b, R
op n #
SR
op n #
(SR), Y
op n #
BLK
op n #
MAA
10 9 8 7 6
5 4 3 2 1
0
IPL
N
V
m x D
I Z C
Addressing Modes Processor Status register
L(DIR), Y
Function Operation
length (Bit)
Addressing Modes
op n #
IMP IMM A DIR DIR, X DIR, Y (DIR)
(DIR, X) (DIR), Y
Symbol
L(DIR)
op n #op n #op n # op n # op n #op n #op n #op n #op n #op n #
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual 21-83
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual
21-82
••N••••Z
F5 4 1
•• ••• •• ••
A8 11 2
+
2i
1
+ i
2
When the contents of PS
is restored, this becomes
the value. In the other
cases, nothing changes.
D5 4 1
••N••••Z
•• ••• •• ••
•• NV•• •ZC
31 5 3
5A +
14 imm
b15 … b0
b7 … b0
Rotate to the left by n bits
m = 0 (n = 0 to 65535)
A
m = 1 (n = 0 to 255)
AL
x = 0
SS + 1
YLM(S)
SS + 1
YHM(S)
x = 1
SS + 1
YLM(S)
PLY
PSH
(Note 17) M(S to S – i + 1)A, B, X…
SS – i
i: Number of bytes corresponding
to register pushed on stack
PUL
(Notes 18
and 22)
A, B, X…M(S + 1 to S + i)
SS + i
i: Number of bytes corresponding
to register restored from stack
PLX x = 0
SS + 1
XLM(S)
SS + 1
XHM(S)
x = 1
SS + 1
XLM(S)
RLA
(Note 3)
RMPA
(Note 19) m = 0
Repeat
(B, A)(B, A) + M(DT:X)
M(DT:Y) (Signed)
XX + 2
YY + 2
ii – 1
Until i = 0
m = 1
Repeat
(BL, AL)(BL, AL)+M(DT,X)
M(DT,Y) (Signed)
XX + 1
YY + 1
ii – 1
Until i = 0
i: Numder of repetitions (0 to 255)
16/8
16/8
16/8
16/8
16/8
16/8
31 5 3
07 +
n
67 13 2
+
3 i
1
ABS
op n # op n #
ABS, X
op n #
ABS, Y
op n #
ABL
op n #
ABL, X
op n #
(ABS)
op n #
L(ABS)
op n #
(ABS, X) op n #
STK
op n #
REL
op n #
DIR, b, R
op n #
ABS, b, R
op n #
SR
op n #
(SR), Y
op n #
BLK
op n #
MAA
10 9 8 7 6
5 4 3 2 1
0
IPL
N
V
m x D
I Z C
Addressing Modes Processor Status register
L(DIR), Y
Function Operation
length (Bit)
Addressing Modes
op n #
IMP IMM A DIR DIR, X DIR, Y (DIR)
(DIR, X) (DIR), Y
Symbol
L(DIR)
op n #op n #op n # op n # op n #op n #op n #op n #op n #op n #
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual 21-85
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual
21-84
••N••••ZC
••N••••ZC
21 7 4
1E 21 8 4
1F
21 7 4
3E 21 8 4
3F
••N••••ZC
••N••••ZC
••N••••ZC
••N••••ZC
Rotate to the right by n bits (n = 0 to
31)
E
Rotate to the right by n bits (n = 0 to
15)
m = 0 A
C b15 … b0
m = 1 AL
C b7 … b0
Rotate to the left by n bits (n = 0 to
31)
E
b31 … b0 C
Rotate to the left by n bits (n = 0 to
15)
m = 0 A
b15 … b0 C
m = 1 AL
b7 … b0 C
Rotate to the right by 1 bit
m = 0 Acc or M16
C b15 … b0
m = 1 AccL or M8
C b7 … b0
ROL
(Note 1)
21 7 3
1A 21 8 3
1B
21 7 3
3A 21 8 3
3B
Rotate to the left by 1 bit
m = 0
Acc or M16
b15 … b0 C
m = 1
AccL or M8
b7 … b0 C
ROR
(Note 1)
13 1 1
81 2 2
13
53 1 1
81 2 2
53
ROL #n
(Note 4)
ROLD #n
(Note 4)
ROR #n
(Note 4)
C1 6 2
60 +
+ imm
imm
D1 8 2
60 +
+ imm
imm
C1 6 2
20 +
+ imm
imm
RORD #n
(Note 4)
D1 8 2
20 +
+ imm
imm
16/8
16/8
32
16/8
16/8
32
b31 … b0 C
ABS
op n # op n #
ABS, X
op n #
ABS, Y
op n #
ABL
op n #
ABL, X
op n #
(ABS)
op n #
L(ABS)
op n #
(ABS, X) op n #
STK
op n #
REL
op n #
DIR, b, R
op n #
ABS, b, R
op n #
SR
op n #
(SR), Y
op n #
BLK
op n #
MAA
10 9 8 7 6
5 4 3 2 1
0
IPL
N
V
m x D
I Z C
Addressing Modes Processor Status register
L(DIR), Y
Function Operation
length (Bit)
Addressing Modes
op n #
IMP IMM A DIR DIR, X DIR, Y (DIR)
(DIR, X) (DIR), Y
Symbol
L(DIR)
op n #op n #op n # op n # op n #op n #op n #op n #op n #op n #
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual 21-87
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual
21-86
•• ••• ••
Value restored from
stack
•• ••• •• ••
77 12 2
?C +
3 i
77 15 2
?C
•• ••• •• ••
•• NV•• •ZC
21 5 4
AE
A1 7 4
AE A1 8 4
AF A1 8 4
A6 A1 9 5
AD A1 11 3
A4
A1 8 3
A3
A1 8 5
AC
21 6 4
AF 21 6 4
A6 21 7 5
AD
21 6 5
AC 21 6 3
A3 21 9 3
A4
•• ••• •• ••
•• NV•• •ZC
77 11 2
?8
+
3 i
77 14 2
?8
•• ••• •• 1
•• ••• •• 1••
•• NV•• •ZC
21 7 4
BE 21 8 4
BF 21 8 4
B6 21 9 5
BD
21 8 5
BC 21 8 3
B3 21 11 3
B4
AccAcc – M – C
21 10 3
A9
A1 12 3
A9
SS + 1
PSLM(S)
SS + 1
PSHM(S)
SS + 1
PCLM(S)
SS + 1
PCHM(S)
SS + 1
PGM(S)
RTI
F1 12 1
SS + 1
PCLM(S)
SS + 1
PCHM(S)
SS + 1
PGM(S)
RTL
94 10 1
RTLD n
(Notes 11 and
12)
SS + 1
DPRnLM(S)
SS + 1
DPRnHM(S)
SS + 1
PCLM(S)
SS + 1
PCHM(S)
SS + 1
PGM(S).
(n = 0 to 3. Multiple DPRs
can be specified.)
B1 3 3
A7
SS + 1
PCLM(S)
SS + 1
PCHM(S)
RTS
84 7 1
SBC
(Notes 1 and
2)
31 3 3
A7 21 5 3
AA
A1 7 3
AA
21 6 3
AB
A1 8 3
AB
21 7 3
A0
A1 9 3
A0
21 8 3
A1
A1 10 3
A1
21 8 3
A8
A1 10 3
A8
21 9 3
A2
A1 11 3
A2
RTSD n
(Notes 11 and
12)
SBCB
(Note 1) AccLAccL – IMM8 – C
B1 3 3
1B
31 3 3
1B
SS + 1
DPRnLM(S)
SS + 1
DPRnHM(S)
SS + 1
PCLM(S)
SS + 1
PCHM(S),
(n = 0 to 3. Multiple DPRs
can be specified.)
21 12 3
B9
C1SEC
04 1 1
I1SEI
05 4 1
SBCD EE – M32 – C
31 4 6
1D 21 7 3
BA 21 8 3
BB 21 9 3
B0 21 10 3
B1 21 10 3
B8 21 11 3
B2
16
16
16/8
8
32
ABS
op n # op n #
ABS, X
op n #
ABS, Y
op n #
ABL
op n #
ABL, X
op n #
(ABS)
op n #
L(ABS)
op n #
(ABS, X) op n #
STK
op n #
REL
op n #
DIR, b, R
op n #
ABS, b, R
op n #
SR
op n #
(SR), Y
op n #
BLK
op n #
MAA
10 9 8 7 6
5 4 3 2 1
0
IPL
N
V
m x D
I Z C
Addressing Modes Processor Status register
L(DIR), Y
Function Operation
length (Bit)
Addressing Modes
op n #
IMP IMM A DIR DIR, X DIR, Y (DIR)
(DIR, X) (DIR), Y
Symbol
L(DIR)
op n #op n #op n # op n # op n #op n #op n #op n #op n #op n #
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual 21-89
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual
21-88
•• •••1 ••
••
Specified flag
becomes “1”
(Note 21).
•• ••• •• ••
81 5 4
DE 81 6 4
DF 91 6 4
D6 81 6 5
DC 81 7 5
DD
11 6 3
D3
91 6 3
D3
11 9 3
D4
91 9 3
D4
DE 4 3 DF 5 3 11 6 4
D6 DC 5 4 DD 6 4
•• ••• ••
81 5 4
CE 81 6 4
CF 91 6 4
C6 81 6 5
CC 81 7 5
CD
11 6 3
C3
91 6 3
C3
11 9 3
C4
91 9 3
C4
CE 4 3 CF 5 3 11 6 4
C6 CC 5 4 CD 6 4
•• ••• •• ••
11 8 3
E3 11 11 3
E4
EE 6 3 EF 7 3 11 8 4
E6 EC 7 4 ED 8 4
•••••• ••
•• ••• •• ••
E7 4 3
•• ••• •• ••
F7 4 3
•• NV•• •ZC
81 4 4
3E 81 5 4
3F 91 5 4
36 91 5 5
3C 91 6 5
3D
11 5 3
33
91 5 3
33
11 8 3
34
91 8 3
34
3E 3 3 3F 4 3 11 5 4
36 11 5 5
3C 11 6 5
3D
•• NV•• •ZC
•• NV•• •ZC
11 8 3
A3 11 11 3
A4
AE 6 3 AF 7 3 11 8 4
A6 11 8 5
AC 11 9 5
AD
•• NV•• •ZC
•• NV•• •ZC
•• NV•• •ZC
51 7 5
17
51 7 5
16
5110 8
97
81 10 3
D9
D9 9 2
81 10 3
C9
C9 9 2
E9 11 2
91 9 3
39
11 9 3
39
m1SEM
25 3 1
PSL(bit n)1
(n = 0, 1, 3 to 7. Multiple bits can
be specified.)
SEP
99 3 2
MAccSTA
(Note 1)
DA 4 2
81 5 3
DA 81 6 3
DB
11 7 3
D0
91 7 3
D0
11 8 3
D1
91 8 3
D1
D8 7 2
81 8 3
D8
11 9 3
D2
91 9 3
D2
STAB
(Note 1)
STAD
M8AccL
M32E
DB 5 2
CA 4 2
81 5 3
CA 81 6 3
CB
11 7 3
C0
91 7 3
C0
11 8 3
C1
91 8 3
C1
C8 7 2
81 8 3
C8
11 9 3
C2
91 9 3
C2
CB 5 2
EA 6 2 11 9 3
E0 11 10 3
E1 E8 9 2 11 11 3
E2
EB 7 2
STP
MXSTX
E2 4 2 41 6 3
F5
MYSTY
F2 4 2 41 6 3
FB
31 2
30
SUB
(Notes 1 and
2)
SUBB
(Note 1)
AccAcc – M
AccLAccL – IMM8
3A 3 2
81 4 3
3A 81 5 3
3B
11 6 3
30
91 6 3
30
11 7 3
31
91 7 3
31
11 7 3
38
91 7 3
38
11 8 3
32
91 8 3
32
3B 4 236 1 2
81 2 3
36
39 1 2
81 2 3
39
11 12 3
A9
SUBD
SUBM
(Note 3)
SUBMB
SUBMD
EE – M32
MM – IMM
M8M8 – IMM8
M32M32 – IMM32
AA 6 2 11 9 3
A0 11 10 3
A1 11 10 3
A8 11 11 3
A2
AB 7 2
3D 3 5
51 7 4
13
51 7 4
12
51 10 7
93
16/8
8
32
16/8
16/8
16/8
8
32
16/8
8
32
Oscillation stopped
ABS
op n # op n #
ABS, X
op n #
ABS, Y
op n #
ABL
op n #
ABL, X
op n #
(ABS)
op n #
L(ABS)
op n #
(ABS, X) op n #
STK
op n #
REL
op n #
DIR, b, R
op n #
ABS, b, R
op n #
SR
op n #
(SR), Y
op n #
BLK
op n #
MAA
10 9 8 7 6
5 4 3 2 1
0
IPL
N
V
m x D
I Z C
Addressing Modes Processor Status register
L(DIR), Y
Function Operation
length (Bit)
Addressing Modes
op n #
IMP IMM A DIR DIR, X DIR, Y (DIR)
(DIR, X) (DIR), Y
Symbol
L(DIR)
op n #op n #op n # op n # op n #op n #op n #op n #op n #op n #
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual 21-91
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual
21-90
•• NV•• •ZC
•• NV•• •ZC
•• NV•• •ZC
•• ••• •• ••
•• ••• ••
••N••••Z
••N••••Z
•• ••• •• ••
•••••• ••
••N••••Z
••N••••Z
••N••••Z
••N••••Z
•• ••• •• ••
SUBS
SUBX
(Note 4)
SS – IMM8
XX – IMM (IMM = 0 to 31)
31 2 3
0B
SUBY
(Note 4) YY – IMM (IMM = 0 to 31)
01 2 2
40
+
imm
01 2 2
60
+
imm
DPRnA (n = 0 to 3)TAD n
(Note 20)
SATAS
SB
DPRnB (n = 0 to 3)
XATAX
YA
XB
YB
ADPRn (n = 0 to 3)
TBS
TBD n
(Note 20)
TBX
TBY
TDA n
(Note 20)
TAY
31 3 2
n2
31 2 2
82
C4 1 1
D4 1 1
B1 3 2
n2
B1 2 2
82
81 2 2
C4
81 2 2
D4
BDPRn (n = 0 to 3)TDB n
(Note 20)
SDPR0TDS
31 2 2
73
B1 2 2
40
+
n2
31 2 2
40
+
n2
16
16/8
16/8
16
16
16/8
16/8
16
16
16/8
16/8
16/8
16/8
16
ABS
op n # op n #
ABS, X
op n #
ABS, Y
op n #
ABL
op n #
ABL, X
op n #
(ABS)
op n #
L(ABS)
op n #
(ABS, X) op n #
STK
op n #
REL
op n #
DIR, b, R
op n #
ABS, b, R
op n #
SR
op n #
(SR), Y
op n #
BLK
op n #
MAA
10 9 8 7 6
5 4 3 2 1
0
IPL
N
V
m x D
I Z C
Addressing Modes Processor Status register
L(DIR), Y
Function Operation
length (Bit)
Addressing Modes
op n #
IMP IMM A DIR DIR, X DIR, Y (DIR)
(DIR, X) (DIR), Y
Symbol
L(DIR)
op n #op n #op n # op n # op n #op n #op n #op n #op n #op n #
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual 21-93
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual
21-92
••N••••Z
••N••••Z
••N••••Z
••N••••Z
••N••••Z
•• ••• •• ••
••N••••Z
•• ••• •• ••
••N••••Z
••N••••Z
••N••••Z
••N••••Z
•• ••• •• ••
A B
AS
BS
XS
TSA
TSB
TSX
AXTXA
BXTXB
SXTXS
YXTXY
DPR0STSD
31 2 2
92
B1 2 2
92
31 4 2
70
31 2 2
F2
A4 1 1
81 2 2
A4
31 2 2
E2
31 2 2
C2
AYTYA
BYTYB
XY
TYX
WIT
XAB
B4 1 1
81 2 2
B4
31 2 2
D2
31 2
10
55 2 1
16/8
16/8
16
16/8
16/8
16/8
16/8
16/8
16/8
16/8
16/8
16/8
CPU clock stopped
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual 21-95
APPENDIX
Appendix 6. Machine instructions
7902 Group User’s Manual
21-94
Note 15. The number of cycles is the case where the number of bytes to be transferred (i) is even.
When the number of bytes to be transferred (i) is odd, the number is calculated as;
5 i + 10
Note 16. The number of cycles is the case where the number of bytes to be transferred (i) is even.
When the number of bytes to be transferred (i) is odd, the number is calculated as;
5 i + 14
Note that it is 10 cycles in the case of 1-byte thanster.
Note 17. i1 is the number of registers to be stored among A, B, X, Y, DPR0, and PS. i2 is the number of
registers to be stored between DT and PG.
Note 18. Letter “i1” indicates the number of registers to be restored.
Note 19. The number of cycles is applied when flag m = “1.” When flag m=“0,” the number is calculated
as; 18 imm + 5
Note 20. Any value from 0 through 3 is placed in an “n” in op code.”
Note 21. Do not use the SEP instruction to specify flag I. (When setting flag I to “1,” be sure to use the
SEI instruction.)
Note 22. Be sure to keep flag I = “1” when executing the PLP or PUL instruction. Also, be sure to use the
SEI instruction when setting flag I to “1.”
Notes for machine instructions table
The table lists the minimum number of instruction cycles for each instruction. The number of cycle is
changed by the following condition.
• The value of the low-order bytes of DPR (DPRnL)
The number of cycle of the addressing mode related with DPRn (n = 0 to 3) is applied when DPRn = 0.
When DPRn 0, add 1 to the number of cycles.
• The number of bytes of instruction which fetched into the instruction queue buffer
• The address at read and write of memory (either even or odd)
• When the external area accessed in BYTE = Vcc level (at external data bus width 8 bits)
• The number of wait
Note 1. The op code at the upper row is used for accumulator A, and the op code at the lower row is
used for accumulator B.
Note 2. When handing 16-bit data with flag m = 0 in the immediate addressing mode, add 1 to the numder
of bytes.
Note 3. When handing 16-bit data with flag m = 0, add 1 to the numder of bytes.
Note 4. Imm is the immediate value specified with an operand (imm = 0–31).
Note 5. The op code at the upper row is used for branching in the range of –128 to +127, and the op
code at the lower row is used for branching in the range of –32768 to +32767.
Note 6. The BRK instruction is a instruction for debugger; it cannot be used.
Note 7. Any value from 0 through 15 is placed in an “n.”
Note 8. When handling 16-bit data with flag x = 0 in the immediate addressing mode, add 1 to the numder
of bytes.
Note 9. The number of cycles is the case of the 16-bit ÷ 8-bit operation. In the case of the 32-bit ÷
16-bit operation, add 8 to the number of cycles.
Note 10. When a zero division interrupt occurs, the number of cycles is 16 cycles. It is regardless of the
data length.
Note 11. When placing a value in any of DPRs, the op code at the upper row is applied. When placing
values to multiple DPRs, the op code at the lower row is applied. The letter “i” represents the
number of DPRn specified: 1 to 4.
Note 12. A “?” indicates to the value of 4 bits which the bit corressing to the specified DPRn becomes “1.”
Note 13. When the source is in the immediate addressing mode and flag m = 0, add n (n = 0 to 15) to
the number of bytes.
Note 14. The number of cycles of the case of the 8-bit 8-bit operation. In the case of the 16-bit
16-bit operation, add 4 to the number of cycles.
APPENDIX
Appendix 7. Countermeasure against noise
7902 Group User’s Manual
21-96
______
Fig. 3 Wiring for RESET pin
(2) Wiring for clock input/output pins
Make the length of wiring connected to the clock input/output pins as short as possible.
Make the length of wiring between the grounding lead of the capacitor, which is connected to
the oscillator, and the Vss pin of the microcomputer, as short as possible (within 20 mm).
Separate the Vss pattern for oscillation from all other Vss patterns. (Refer to “Figure 11.”)
Reason: The microcomputer’s operation
synchronizes with a clock generated
by the oscillation circuit.
If noise enters clock I/O pins, clock
waveforms may be deformed. This
may cause a malfunction or a
program runaway.
Also, if the noise causes a potential
difference between the Vss level of
the microcomputer and the Vss level
of an oscillator, the correct clock
will not be input in the
microcomputer.
Appendix 7. Countermeasure against noise
General countermeasure examples against noise are described below. Although the effect of these
countermeasure depends on each system.
The user shall modify them according to the actual application and test them.
1. Short wiring length
The wiring on a printed circuit board may function as an antenna which feeds noise into the microcomputer.
The shorter the total wiring length (by mm unit), the less possibility of noise insertion into the microcomputer.
(1)
______
Wiring for RESET pin
______
Make the length of wiring connected to the RESET pin as short as possible.
______
In particular, connect a capacitor between the RESET pin and the Vss pin with the shortest possible
wiring (within 20 mm).
Reason:
______
If noise is input to the RESET pin, the microcomputer restarts operation before the internal
state of the microcomputer is completely initialized. This may cause a program runaway.
Noise
XIN
XOUT
Vss
XIN
XOUT
Vss
M37902 M37902
Not acceptable Acceptable
Fig. 4 Wiring for clock input/output pins
Reset
circuit
Vss
RESET
Vss
M37902
Acceptable
RESET
Reset
circuit
Noise
VssVss
M37902
Not acceptable
APPENDIX
Appendix 7. Countermeasure against noise
7902 Group User’s Manual 21-97
(3) Wiring for MD0 and MD1 pins
Connect MD0 and MD1 pins to the Vss pin (or Vcc pin) with the shortest possible wiring.
Reason: The processor mode of the
microcomputer is influenced by a
potential at the MD0 and MD1 pins
when the MD0 and MD1 pins and
the Vss pin (or Vcc pin) are
connected.
If the noise causes a potential
difference between the MD0 and
MD1 pins and the Vss pin (or Vcc
pin), the processor mode may
become unstable. This may cause
a microcomputer malfunction or
a program runaway.
Noise
MD0
Vss
M37902
Vss
M37902
Acceptable
Not Acceptable
MD1
MD0
MD1
Fig. 5 Wiring for MD0 and MD1 pins
2. Connection of bypass capacitor between Vss and Vcc lines
Connect an approximate 0.1
µ
F bypass capacitor as follows:
Connect a bypass capacitor between the Vss and Vcc pins, at equal lengths.
The wiring connecting the bypass capacitor between the Vss and Vcc pins should be as short as
possible.
Use thicker wiring for the Vss and Vcc lines than that for the other signal lines.
Fig. 6 Bypass capacitor between Vss and Vcc lines
Bypass capacitor
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
Vcc
Vss
M37902
Wiring pattern Wiring pattern
APPENDIX
Appendix 7. Countermeasure against noise
7902 Group User’s Manual
21-98
3. Wiring for analog input pins, analog power source pins, etc.
(1) Processing for analog input pins
Connect a resistor to the analog signal line, which is connected to an analog input pin, in series.
Additionally, connect the resistor to the microcomputer as close as possible.
Connect a capacitor between the analog input pin and the AVss pin, as close to the AVss pin as
possible.
Reason: A signal which is input to the analog input pin is usually an output signal from a sensor.
The sensor, which detects changes in status, is installed far from the microcomputer’s
printed circuit board. Therefore, this long wiring between them becomes an antenna which
picks up noise and feeds it into the microcomputer’s analog input pin.
If a capacitor between an analog input pin and the AVss pin is grounded far away from the
AVss pin, noise on the GND line may enter the microcomputer through the capacitor.
Fig. 7 Countermeasure example against noise for analog input pin using thermistor
ANi
AVss
Thermistor
Noise
M37902
RI
CI Reference values
RI : Approximate 100 to 1000
CI : Approximate 100 pF to 1000 pF
Notes 1: Design an external circuit for the ANi pin so that charge/discharge is available within 1
cycle of φAD.
2: This resistor and thermistor are used to divide resistance.
(Note 2)
Acceptable
Acceptable
Not
acceptable
APPENDIX
Appendix 7. Countermeasure against noise
7902 Group User’s Manual 21-99
(2) Processing for analog power source pins, etc.
Use independent power sources for the Vcc, AVcc and VREF pins.
Insert capacitors between the AVcc and AVss pins, and between the VREF and AVss pins.
Reasons: Prevents the A-D converter from noise on the Vcc line.
Fig. 8 Processing for analog power source pins, etc.
AVcc
AVss
M37902
Reference values
C1 0.47 µF C2 0.47 µF
Note : Connect capacitors using the
thickest, shortest wiring possible.
VREF
ANi
C1 C2
(sensor, etc.)
APPENDIX
Appendix 7. Countermeasure against noise
7902 Group User’s Manual
21-100
4. Oscillator protection
The oscillator, which generates the basic clock for the microcomputer operations, must be protected from
the affect of other signals.
(1) Distance oscillator from signal lines with large current flows
Install the microcomputer, especially the oscillator, as far as possible from signal lines which handle
currents larger than the microcomputer current value tolerance.
Reason: The microcomputer is used in
systems which contain signal lines
for controlling motors, LEDs,
thermal heads, etc. Noise occurs
due to mutual inductance when a
large current flows through the signal
lines.
(2) Distance oscillator from signal lines with frequent potential level changes
Install an oscillator and its wiring pattern away from signal lines where potential levels change
frequently.
Do not cross these signal lines over the clock-related or noise-sensitive signal lines.
Reason: Signal lines with frequently changing
potential levels may affect other
signal lines at a rising or falling edge.
In particular, if the lines cross over
a clock-related signal line, clock
waveforms may be deformed, which
causes a microcomputer malfunction
or a program runaway.
X
IN
X
OUT
Vss
M
M37902
Mutual inductance
Large current
X
IN
X
OUT
V
SS
Do not cross.
M37902
I/O pin for signal with frequently
chan
g
in
g
potential levels
Fig. 10 Wiring for signal lines where potential levels
frequently change
(3) Oscillator protection using Vss pattern
Print a Vss pattern on the bottom (soldering
side) of a double-sided printed circuit board,
under the oscillator mount position.
Connect the Vss pattern to the Vss pin of the
microcomputer with the shortest possible wiring,
separating it from other Vss patterns.
AAA
AAA
AAA
AAA
AA
AA
AA
AAA
A
A
A
A
AA
X
IN
X
OUT
Vss
An example of Vss pattern on the
underside of an oscillator.
Mounted pattern
example of
oscillator unit.
Separate Vss lines for oscillation and supply.
M37902
Fig. 11 Vss pattern underneath mounted oscillator
Fig. 9 Wiring for signal lines where large current
flows
APPENDIX
Appendix 7. Countermeasure against noise
7902 Group User’s Manual 21-101
5. Setup for I/O ports
Setup I/O ports by hardware and software as follows:
<Hardware protection>
Connect a resistor of 100 or more to an I/O port in series.
<Software protection>
Read the data of an input port several times to confirm that input levels are equal.
Since the output data may reverse because of noise, rewrite data to the output port’s Pi register
periodically.
Rewrite data to port Pi direction registers periodically.
6. Reinforcement of the power source line
For the Vss and Vcc lines, use thicker wiring than that of other signal lines.
When using a multilayer printed circuit board, the Vss and Vcc patterns must each be one of the middle
layers.
The following is necessary for double-sided printed circuit boards:
•On one side, the microcomputer is installed at the center, and the Vss line is looped or meshed around
it. The vacant area is filled with the Vss line.
•On the opposite side, the Vcc line is wired the same as the Vss line.
•The power source lines of external devices which are connected by bus to the microcomputer must be
connected to the microcomputer's power source lines with the shortest possible wiring.
Reasons: With external devices connected to the microcomputer, the levels of many of the signal lines
(total external address buses: 24 bits) may change simultaneously, causing noise on the power
source line.
Noise
Direction register
Port latch
Data bus
Port
Fig. 12 Setup for I/O ports
APPENDIX
Appendix 8. 7902 Group Q & A
7902 Group User’s Manual
21-102
Appendix 8. 7902 Group Q & A
Information which may be helpful in fully utilizing the 7902 Group is provided in Q & A format.
In Q & A, as a rule, one question and its answer are summarized within one page. The upper box on each
page is a question, and a box below the question is its answer. (If a question or an answer extends to two
or more pages, there is a page number at the lower right corner.)
At the upper right corner of each page, the main function related to the contents of description in that page
is listed.
APPENDIX
7902 Group User’s Manual 21-103
Appendix 8. 7902 Group Q & A
Interrupts
Q
If an interrupt request (b) occurs while an interrupt routine (a) is executed, is it true that the main
routine is not executed at all after the execution of the interrupt routine (a) is completed until the
execution of the INTACK sequence for the next interrupt (b) starts?
(2) If the next interrupt request (b) occurs immediately after sampling pulse is generated, the
microcomputer executes one instruction of the main routine before executing the INTACK
sequence for (b). It is because that the interrupt request is sampled by the next sampling
pulse .
An interrupt request is sampled by a sampling pulse generated synchronously with the CPU’s op-code
fetch cycle.
(1) If the next interrupt request (b) occurs before sampling pulse for the RTI instruction is gener-
ated, the microcomputer executes the INTACK sequence for (b) without executing the main routine.
(No instruction of the main routine is executed.) It is because that sampling is completed while
executing the RTI instruction.
A
Conditions:
Flag I is cleared to “0” by executing the RTI instruction.
The interrupt priority level of interrupt (b) is higher than IPL of the main routine.
The interrupt priority detection time = 2 cycles of fsys
.
Interrupt routine (a) Main routine INTACK sequence
for interrupt (b)
Sequence of
execution
RTI instruction ?
INTACK sequence for interrupt (b)
Interrupt request (b)
Interrupt routine (a)
Sampling pulse RTI instruction
Main routine
Interrupt request (b)
Sampling pulse
INTACK sequence
for interrupt (b)
One instruction executed
Interrupt routine (a)
RTI instruction
APPENDIX
Appendix 8. 7902 Group Q & A
7902 Group User’s Manual
21-104
Interrupts
Suppose that there is a routine which should not accept a certain interrupt request. (This routine can
accept any of the other interrupt request.)
Although the interrupt priority level select bits for a certain interrupt are set to “0002” (in other words,
although this interrupt is set to be disabled), this interrupt request is actually accepted immediately
after the change of the priority level. Why did this occur, and what should I do about it?
As for the change of the interrupt priority level, if the following are met, the microcomputer may
pretend to accept an interrupt request immediately after this interrupt is set to be disabled:
•The next instruction (in the above example, it is the LDA instruction) is already stored into a instruc-
tion queue buffer of the BIU.
•Requirements for accepting the interrupt request which should not be accepted are satisfied immediately
before the next instruction in the instruction queue buffer is executed.
When writing to a memory or an I/O, the CPU passes an address and data to the BIU. Then, the CPU
executes the next instruction in the instruction queue buffer while the BIU is writing data into the
actual address. Detection of the interrupt priority level is performed at the beginning of each instruction.
In the above case, the CPU executes the next instruction before the BIU completes the change of
the interrupt priority level. Therefore, in the detection of the interrupt priority level performed synchronously
with the execution of the next instruction, actually, the interrupt priority level before the change is
used to detection, and its interrupt request is accepted.
Q
A
(1/2)
Interrupt request is
accepted in this
interval
:
MOVMB XXXIC, #00H ; Writes “0002” to the interrupt priority level select bits.
; Clears the interrupt request bit to “0.”
LDA A,DATA ; Instruction at the beginning of the routine which
should not accept a certain interrupt request.
:;
Previous instruction
executed
(Instruction prefetched)
CPU operation
BIU operation
Interrupt priority detection time
Sequence of execution
Writing to interrupt priority level select bits.
Change of interrupt priority level
completed
Interrupt request accepted
Interrupt request generated
MOVMB instruction
executed LDA instruction
executed
APPENDIX
7902 Group User’s Manual 21-105
Appendix 8. 7902 Group Q & A
Interrupts
(2/2)
A
To prevent this problem, make sure that the routine which should not accept a certain interrupt
request will be executed after the change of the interrupt priority level (IPL) has been completed.
(This is to be made by software.)
The following is a sample program.
[Sample program]
After writing “0002” to the interrupt priority level select bits, the instruction queue buffer is filled with
several NOP instructions to make the next instruction not to be executed before this writing is
completed.
:
MOVMB XXXIC, #00H ; Writes “0002” to the interrupt priority level select bits.
NOP ; Inserts ten NOP instructions.
:
NOP ;
LDA A,DATA ; Instruction at the beginning of the routine that should not accept a
: certain interrupt request
APPENDIX
Appendix 8. 7902 Group Q & A
7902 Group User’s Manual
21-106
Q
After execution of the SEI instruction, a branch is made in an interrupt routin.
Why did this occur?
A
SEI
LDAB A, #00H
CLI
Interrupt routine
RTI
SEI
LDAB A, #00H
CLI
Interrupt routine
RTI
Interrupt request
generated
a
When an interrupt request is generated before the SEI instruction is executed, this interrupt request
may be accepted immediately before the execution of the SEI instruction. (This acceptance occurs
depending on the timing when that interrupt request occurs.) In this case, a branch to the interrupt
routine is made immediately after execution of the SEI instruction.
Accordingly, the interrupt routine which is executed immediately after the SEI instruction is due to an
interrupt request generated before execution of the SEI instruction. Note that, in the routine ( a ) which
should not accept the interrupt request, the following occur. (This routine follows the SEI instruction.):
• No interrupt request is accepted.
• No interrupt routine is made.
Note: “Interrupt” described here means “maskable interrupt” which can be disabled by the SEI instruction.
(Refer to section “7.2 Interruput source.”)
Interrupts
APPENDIX
7902 Group User’s Manual 21-107
Appendix 8. 7902 Group Q & A
Interrupts
Q
(1) In both of the edge sense and level sense, an external interrupt request occurs when the
input signal to the INTi pin changes its level. This is independent of clock
φ
1.
In the edge sense, also, the interrupt request bit is set to “1” at this time.
(2) There are two methods: one uses external interrupt’s level sense, and the other uses the
timer’s event counter mode.
Method using external interrupt’s level sense
As for hardware, input a logical sum of multiple interrupt signals (e.g., ‘a’, ‘b’, and ‘c’) to the
INTi pin, and input each signal to each corresponding port pin.
As for software, check the port pin’s input levels in the INTi interrupt routine in order to detect
which signal (‘a’, ‘b’, or ‘c’) was input.
A
(1) Which timing of clock
φ
1 is the external interrupts (input signals to the INTi pin) detected?
(2) When external interrupt input (INTi) pins are not enough, what should I do?
Method using timer’s event counter mode
As for hardware, input an interrupt signal to the TAiIN pin or TBiIN pin.
As for software, set the timer’s operating mode to the event counter mode. Then, set a value
of “000016” into the timer register and select the valid edge.
A timer’s interrupt request occurs when an interrupt signal (selected valid edge) is input.
a
M37902
Port pin
Port pin
Port pin
INTi
b
c
Also, this can be realized by using the key input interrupt’s function.
For details, refer to “CHAPTER 8. KEY INPUT INTERRUPT.”
APPENDIX
Appendix 8. 7902 Group Q & A
7902 Group User’s Manual
21-108
Processor mode
If the processor mode is switched as described below by using the processor mode bits (bits 1 and
0 at address 5E16) during program execution, is there any precaution in programming?
Single-chip mode Microprocessor mode
Memory expansion mode Microprocessor mode
Q
A
If the processor mode is set to be switched as described above by using the processor mode bits,
the mode is actually switched simultaneously when a write cycle for the processor mode bits is
completed.
Then, the program counter indicates the address next to the address (address XXXX16) that stores
a write instruction for the processor mode bits. Additionally, access to the internal ROM area is
disabled. However, since the instruction queue buffer can prefetch instructions up to 10 bytes, the
external ROM area’s address which will be accessed first after the mode has been switched is one
of addresses “XXXX16 + 1” to “XXXX16 + 11.” Also, there is a possibility that each instruction at
addresses “XXXX16 + 1” to “XXXX16 + 10” is executed. To prevent a problem, be sure to do as follows
by software.
Transfer a write instruction for the processor mode bits to an internal RAM area, and make a
branch to there in order to execute the write instruction. After that, make a branch to the programming
address in the external ROM area. (The contents of the instruction queue buffer are initialized
by a branch instruction.)
Program a write instruction for the processor mode bits and the following instructions (10 bytes
or more) to a certain address in the internal ROM area and the same one in the external ROM
area. (See below.)
:
:
MOVMB PMR, #00000010B
NOP
:
NOP
:
:
:
MOVMB PMR, #00000010B
NOP
:
NOP
:
XXXX16
External ROM area
Internal ROM area
XXXX16
10 bytes
or more
APPENDIX
7902 Group User’s Manual 21-109
Appendix 8. 7902 Group Q & A
Watchdog timer
In detection of a program runaway with usage of the watchdog timer, if the same value as that
at the reset vector address is set to the watchdog timer interrupt’s vector address, not performing
software reset, how does it occur?
When a branch is made to the branch destination address for reset within the watchdog timer
interrupt routine, how does it occur?
A
The CPU registers and the SFR are not initialized in the above-mentioned way. Accordingly,
the user must initialize all of them by software.
Note that the processor interrupt priority level (IPL) retains “7” and is not initialized. Consequently,
all interrupt requests cannot be accepted.
When rewriting the IPL by software, be sure to save the 16-bit immediate value to the stack
area, and then restore that 16-bit immediate value to all bits of the processor status register
(PS).
When a program runaway occurs, we recommend to perform software reset in order to
initialize the microcomputer.
Q
APPENDIX
7902 Group User’s Manual
21-110
Appendix 9. M37902FGCGP electrical characteristics
Appendix 9. M37902FGCGP electrical characteristics
The electrical characteristics of the M37902FGCGP are described below.
For the electrical characteristics, be sure to refer to the latest datasheets.
ABSOLUTE MAXIMUM RATINGS
Parameter
Power source voltage
Analog power source voltage
Input voltage P00–P07, P10–P17, P20–P27, P30–P33, P40–P47, P50–P57,
P60–P67, P70–P77, P80–P87, P100–P107, P110–P117,
VREF, XIN, RESET, BYTE, MD0, MD1, NMI, VCONT
Output voltage P00–P07, P10–P17, P20–P27, P30–P33, P40–P47, P50–P57,
P60–P67, P70–P77, P80–P87, P100–P107, P110–P117,
XOUT
Power dissipation
Operating ambient temperature
Storage temerature
Symbol
VCC
AVCC
VI
VO
Pd
Topr
Tstg
Unit
V
V
V
V
mW
°C
°C
Ratings
–0.3 to 6.5
–0.3 to 6.5
–0.3 to VCC+0.3
–0.3 to VCC+0.3
300
–20 to 85
–40 to 150
7902 Group User’s Manual 21-111
APPENDIX
Appendix 9. M37902FGCGP electrical characteristics
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
MHz
MHz
Max.
5.5
Vcc
VCC
Vcc
Vcc
Vcc
Vcc
Vcc
0.2 VCC
0.2 VCC
0.2 VCC
0.16 VCC
0.16 VCC
0.16 VCC
0.16 VCC
–10
–5
10
5
26
26
Parameter
Power source voltage
Analog power source voltage
Power source voltage
Analog power source voltage
High-level input voltage XIN, RESET, BYTE, MD0, MD1
High-level input voltage P10–P17, P20–P27, P30–P33, P40–P47, P50–P57,
P60–P67, P70–P77, P80–P87, P100–P107, P110–P117
High-level input voltage P00–P07 (When the port P0 input level select bit = “0”)
High-level input voltage P00–P07 (When the port P0 input level select bit = “1”)
High-level input voltage D0–D7, D8–D15
High-level input voltage RDY, HOLD, TA0IN–TA4IN, TA0OUT–TA4OUT,
TB0IN–TB2IN, KI0–KI3, INT0–INT4, NMI, ADTRG, CTS0,
CTS1, CLK0, CLK1, RxD0, RxD1
High-level input voltage SCLK, SDA (Note 1)
Low-level input voltage XIN, RESET, BYTE, MD0, MD1
Low-level input voltage P10–P17, P20–P27, P30–P33, P40–P47, P50–P57,
P60–P67, P70–P77, P80–P87, P100–P107, P110–P117
Low-level input voltage P00–P07 (When the port P0 input level select bit = “0”)
Low-level input voltage P00–P07 (When the port P0 input level select bit = “1”)
Low-level input voltage D0–D7, D8–D15
Low-level input voltage RDY, HOLD, TA0IN–TA4IN, TA0OUT–TA4OUT,
TB0IN–TB2IN, KI0–KI3, INT0–INT4, NMI, ADTRG, CTS0,
CTS1, CLK0, CLK1, RxD0, RxD1
Low-level input voltage SCLK, SDA (Note 1)
High-level peak output current P00–P07, P10–P17, P20–P27, P30–P33, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87,
P100–P107, P110–P117
High-level average output current P00–P07, P10–P17, P20–P27, P30–P33,
P40–P47, P50–P57, P60–P67, P70–P77,
P80–P87, P100–P107, P110–P117
Low-level peak output current P00–P07, P10–P17, P20–P27, P30–P33,
P40–P47, P50–P57, P60–P67, P70–P77,
P80–P87, P100–P107, P110–P117
Low-level average output current P00–P07, P10–P17, P20–P27, P30–P33,
P40–P47, P50–P57, P60–P67, P70–P77,
P80–P87, P100–P107, P110–P117
External clock input frequency (Note 2)
System clock frequency
Symbol
VCC
AVCC
VSS
AVSS
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
VIL
VIL
IOH(peak)
IOH(avg)
IOL(peak)
IOL(avg)
f(XIN)
f(fsys)
RECOMMENDED OPERATING CONDITIONS (Vcc = 5 V, Ta = –20 to 85 °C, unless otherwise noted)
Notes 1: Pins SCLK and SDA are used only in the flash memory serial I/O mode.
2: When using the PLL frequency multiplier, be sure that f(fsys) = 26 MHz or less.
3: Average output current is the average value of an interval of 100 ms.
4: The sum of IOL(peak) for ports P0–P2, P8, P10, and P11 must be 80 mA or less, the sum of I OH(peak) for ports P0–P2, P8, P10, and P11 must be 80
mA or less, the sum of IOL(peak) for ports P3–P7 must be 80 mA or less, the sum of I OH(peak) for ports P3–P7 must be 80 mA or less.
Limits
Min.
4.5
0.8 Vcc
0.7 VCC
0.7 Vcc
0.43 Vcc
0.43 Vcc
0.43 Vcc
0.43 Vcc
0
0
0
0
0
0
0
Typ.
5.0
VCC
0
0
APPENDIX
7902 Group User’s Manual
21-112
Appendix 9. M37902FGCGP electrical characteristics
Parameter
High-level output voltage P00–P07, P10–P17,
P20–P27, P30, P40–P47,
P50–P57, P60–P67,
P70–P77, P80–P87,
P100–P107, P110–P117
High-level output voltage P00–P07, P10–P17,
P2
0
–P2
7
, P4
0
, P4
2
, P4
4
–P4
7
,
P100–P107, P110–P117
High-level output voltage P31–P33
Low-level output voltage P00–P07, P10–P17,
P20–P27, P30, P40–P47,
P50–P57, P60–P67,
P70–P77, P80–P87,
P100–P107, P110–P117
Low-level output voltage P00–P07, P10–P17,
P20–P27, P40, P42,
P44–P47, P100–P107,
P110–P117
Low-level output voltage P31–P33
Hysteresis RDY, HOLD, TA0IN–TA4IN,
TA0OUT–TA4OUT, TB0IN–TB2IN,
KI0–KI3, INT0–INT4, NMI, ADTRG,
CTS0, CTS1, CLK0, CLK1, RxD0, RxD1
Hysteresis RESET
Hysteresis XIN
High-level input current
P00–P07, P10–P17,
P2
0
–P2
7
, P3
0
–P3
3
, P4
0
–P4
7
,
P5
0
–P5
7
, P6
0
–P6
7
, P7
0
–P7
7
,
P80–P87, P100–P107,
P110–P117, XIN, RESET,
BYTE, MD0, MD1, NMI
Low-level input current
P00–P07, P10–P17,
P2
0
–P2
7
, P3
0
–P3
3
, P4
0
–P4
3
,
P5
0
–P5
3
, P6
0
–P6
7
, P7
0
–P7
7
,
P80–P87, P100–P107,
P110–P117, XIN, RESET,
BYTE, MD0, MD1
Low-level input current
P4
4
–P4
7
,
P54–P57, NMI
RAM hold voltage
Power source current
DC ELECTRICAL CHARACTERISTICS (VCC = 5 V, VSS = 0 V, Ta = –20 to 85 °C, f(fsys) = 26 MHz, unless otherwise noted)
Unit
V
V
V
V
V
V
V
V
V
µ
A
µ
A
µ
A
mA
V
mA
µ
A
f(fsys) = 26 MHz.
CPU operates.
Ta = 25 °C when
clock is stopped.
Ta = 85 °C when
clock is stopped.
Test conditions
IOH = –10 mA
IOH = –400
µ
A
IOH = –10 mA
IOH = –400
µ
A
IOL = 10 mA
IOL = 2 mA
IOL = 10 mA
IOL = 2 mA
VI = 5.0 V
VI = 0 V
VI = 0 V, No pullup transistor
VI = 0 V, Pullup transistor used
When clock is stoped.
Symbol
VOH
VOH
VOH
VOL
VOL
VOL
VT+ —VT
VT+ —VT
VT+ —VT
IIH
IIL
IIL
VRAM
ICC
Min.
3
4.7
3.4
4.8
0.2
0.5
0.1
–0.4
2
Limits
Typ.
–0.7
30
Max.
2
0.45
1.6
0.4
0.7
1.5
0.3
5
–5
–5
–1.1
54
1
20
Output-only pins
are open, and the
other pins are con-
nected to Vss or
Vcc. An external
square-waveform
clock is input. (Pin
X
OUT
is open.) The
PLL frequency
multiplier stops its
operation.
7902 Group User’s Manual 21-113
APPENDIX
Appendix 9. M37902FGCGP electrical characteristics
Bits
%
µ
s
k
mA
Resolution
Absolute accuracy
Ladder resistance
Conversion time
Reference voltage
Analog input voltage
—————
—————
RLADDER
tCONV
VREF
VIA
VREF = V CC
VREF = V CC
VREF = V CC
f(fsys) 26 MHz
Max.
A-D CONVERTER CHARACTERISTICS (VCC = AVCC = 5 V ± 0.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
UnitParameterSymbol Test conditions Limits
Min.
10-bit resolution mode
8-bit resolution mode
10-bit resolution mode
8-bit resolution mode
5
4.54
1.89 (Note)
2.7
0
10
± 3
± 2
VCC
VREF
Bits
LSB
LSB
k
µ
s
V
V
Note: This is applied when A-D conversion freguency (
φ
AD) = f1.
D-A CONVERTER CHARACTERISTICS (VCC = 5 V, VSS = AVSS = 0 V, VREF = 5 V, Ta = –20 to 85 °C, unless otherwise noted)
UnitParameterSymbol Limits
Typ.Min. Max.
Test conditions
Resolution
Absolute accuracy
Set time
Output resistance
Reference power source input current
——
——
tsu
RO
IVREF (Note) 1 2.5
8
± 1.0
3
4
3.2
Note: The test conditions are as follows:
• One D-A converter is used.
• The D-A register value of the unused D-A converter is “0016.”
• The reference power source input current for the ladder resistance of the A-D converter is excluded.
µ
s
RESET input low-level pulse width
tw(RESETL)
Symbol Parameter Min. Limits Unit
RESET INPUT
Reset input timing requirements (VCC = 5 V ± 0.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted)
2
Max.Typ.
RESET input tw(RESETL)
APPENDIX
7902 Group User’s Manual
21-114
Appendix 9. M37902FGCGP electrical characteristics
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tc(TA)
tw(TAH)
tw(TAL)
f(fsys)
26 MHz
f(fsys)
26 MHz
f(fsys)
26 MHz
PERIPHERAL DEVICE INPUT/OUTPUT TIMING
(VCC = 5 V±0.5 V, VSS = 0 V, Ta = –20 to 85 °C, f(fsys) = 26 MHz unless otherwise noted)
For limits depending on f(fsys), their calculation formulas are shown below. Also, the values at f(fsys) = 26 MHz are shown in ( ).
Timer A input (Up-down input and Count input in event counter mode)
tc(UP)
tw(UPH)
tw(UPL)
tsu(UP-TIN)
th(TIN-UP)
Symbol
TAiOUT input cycle time
TAiOUT input high-level pulse width
TAiOUT input low-level pulse width
TAiOUT input setup time
TAiOUT input hold time
Parameter Limits
Min.
2000
1000
1000
400
400
Max. Unit
Timer A input (External trigger input in pulse width modulation mode)
tw(TAH)
tw(TAL)
Symbol
TAiIN input high-level pulse width
TAiIN input low-level pulse width
Parameter Min.
80
80
LimitsMax. Unit
Limits
Symbol Parameter Min. Max. Unit
8 × 109
f(fsys)(307)
TAiIN input cycle time
TAiIN input high-level pulse width
TAiIN input low-level pulse width 80
80
Timer A input (External trigger input in one-shot pulse mode)
Limits
Symbol Parameter Min. Max. Unit
16 × 109
f(fsys)
8 × 109
f(fsys)
8 × 109
f(fsys)
(615)
(307)
(307)
tc(TA)
tw(TAH)
tw(TAL)
TAiIN input cycle time
TAiIN input high-level pulse width
TAiIN input low-level pulse width
Timer A input (Gating input in timer mode)
Note :The TAiIN input cycle time requires 4 or more cycles of a count source. The TAiIN input high-level pulse width and the TAiIN input low-level pulse width
respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(f sys)
26 MHz.
Timer A input (Count input in event counter mode)
tc(TA)
tw(TAH)
tw(TAL)
Symbol
TAiIN input cycle time
TAiIN input high-level pulse width
TAiIN input low-level pulse width
Parameter Min.
80
40
40
LimitsMax. Unit
f(fsys) 26 MHz
7902 Group User’s Manual 21-115
APPENDIX
Appendix 9. M37902FGCGP electrical characteristics
ns
ns
ns
tc(TA)
tsu(TAjIN-TAjOUT)
tsu(TAjOUT-TAjIN)
Symbol Parameter Min.
800
200
200
LimitsMax. Unit
Timer A input (Two-phase pulse input in event counter mode)
TAiIN input cycle time
TAjIN input setup time
TAjOUT input setup time
TAi
IN
input
TAi
OUT
input
(Up-down input)
TAi
OUT
input
(Up-down input)
TAi
IN
input
(When count by falling)
TAi
IN
input
(When count by rising)
TAj
IN
input
TAj
OUT
input
Test conditions
• V
CC
= 5 V±0.5 V, Ta = –20 to 85 °C
• Input timing voltage : V
IL
= 0.8 V, V
IH
= 2.15 V
• Up-down and Count input in event counter mode
• Two-phase pulse input in event counter mode
• Gating input in timer mode
• Count input in event counter mode
• External trigger input in one-shot pulse mode
• External trigger input in pulse width modulation mode tc
(TA)
t
w(TAH)
t
w(TAL)
t
c(UP)
t
w(UPH)
t
w(UPL)
t
h(T
IN
-UP)
t
su(TAj
IN
-TAj
OUT
)
t
su(TAj
IN
-TAj
OUT
)
t
su(TAj
OUT
-TAj
IN
)
t
su(TAj
OUT
-TAj
IN
)
t
c(TA)
t
su(UP-T
IN
)
APPENDIX
7902 Group User’s Manual
21-116
Appendix 9. M37902FGCGP electrical characteristics
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
f(fsys) 26 MHz
f(fsys) 26 MHz
f(fsys) 26 MHz
f(fsys) 26 MHz
f(fsys) 26 MHz
f(fsys) 26 MHz
tc(TB)
tw(TBH)
tw(TBL)
tc(TB)
tw(TBH)
tw(TBL)
Timer B input (Count input in event counter mode)
Symbol
TBiIN input cycle time (one edge count)
TBiIN input high-level pulse width (one edge count)
TBiIN input low-level pulse width (one edge count)
TBiIN input cycle time (both edge count)
TBiIN input high-level pulse width (both edge count)
TBiIN input low-level pulse width (both edge count)
Parameter Limits
Min.
80
40
40
160
80
80
Max. Unit
Limits
Symbol Parameter Min. Max. Unit
16 × 109
f(fsys)
8 × 109
f(fsys)
8 × 109
f(fsys)
(615)
(307)
(307)
tc(TB)
tw(TBH)
tw(TBL)
TBiIN input cycle time
TBiIN input high-level pulse width
TBiIN input low-level pulse width
Timer B input (Pulse period measurement mode)
Note: The TBiIN input cycle time requires 4 or more cycles of a count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width
respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f 2 at f(fsys) 26 MHz.
Limits
Symbol Parameter Min. Max. Unit
16 × 109
f(fsys)
8 × 109
f(fsys)
8 × 109
f(fsys)
(615)
(307)
(307)
tc(TB)
tw(TBH)
tw(TBL)
TBiIN input cycle time
TBiIN input high-level pulse width
TBiIN input low-level pulse width
Timer B input (Pulse width measurement mode)
Note: The TBiIN input cycle time requires 4 or more cycles of a count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width
respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f 2 at f(fsys) 26 MHz.
tc(AD)
tw(ADL)
Symbol
ADTRG input cycle time (minimum allowable trigger)
ADTRG input low-level pulse width
Parameter Min.
1000
125
LimitsMax. Unit
A-D trigger input
7902 Group User’s Manual 21-117
APPENDIX
Appendix 9. M37902FGCGP electrical characteristics
ns
ns
ns
ns
ns
ns
ns
ns
ns
tc(CK)
tw(CKH)
tw(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
Serial I/O
Symbol
CLKi input cycle time
CLKi input high-level pulse width
CLKi input low-level pulse width
TXDi output delay time
TXDi hold time
RXDi input setup time
RXDi input hold time
Parameter Limits
Min.
200
100
100
0
20
90
Max.
80
Unit
tw(INH)
tw(INL)
Symbol
INTi input/NMI input/KIi input high-level pulse width
INTi input/NMI input/KIi input low-level pulse width
Parameter Min.
250
250
LimitsMax. Unit
External interrupt (INTi) input, NMI input, Key input interrupt (KIi) input
t
c(TB)
t
w(TBH)
t
w(TBL)
t
c(CK)
t
w(CKH)
t
w(CKL)
t
h(C - Q)
t
d(C - Q)
t
su(D - C)
t
w(INH)
t
w(INL)
t
h(C - D)
t
c(AD)
t
w(ADL)
TBi
IN
input
INTi input,
AD
TRG
input
CLKi input
TxDi output
RxDi input
NMI input,
KIi input
Test conditions
• Vcc = 5 V ± 0.5 V, Ta = –20 to 85 °C
• Input timing voltage : V
IL
= 0.8 V, V
IH
= 2.15 V
• Output timing voltage : V
OL
= 0.8 V, V
OH
= 2.0 V, C
L
= 50 pF
APPENDIX
7902 Group User’s Manual
21-118
Appendix 9. M37902FGCGP electrical characteristics
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
td(
φ
1-HLDAL)
td(RDH-HLDAL)
t
d(BXWH-HLDAL)
t
pxz(HLDAL-RDZ)
t
pxz(HLDAL-BXWZ)
t
pxz(HLDAL-CSiZ)
t
pxz(HLDAL-ALEZ)
tpxz(HLDAL-AZ)
t
pzx(HLDAL-RDZ)
t
pzx(HLDAL-BXWZ)
t
pzx(HLDAL-CSiZ)
t
pzx(HLDAL-ALEZ)
tpzx(HLDAL-AZ)
READY, HOLD TIMING
Timing requirements (VCC = 5 V±0.5 V, VSS = 0 V, Ta = –20 to 85 °C, f(fsys) = 26 MHz, unless otherwise noted)
tsu(RDY-
φ
1)
tsu(HOLD-
φ
1)
th(
φ
1-RDY)
th(
φ
1-HOLD)
Symbol
RDY input setup time
HOLD input setup time
RDY input hold time
HOLD input hold time
Parameter Limits
Min.
40
40
0
0
Max. Unit
Switching characteristics (VCC = 5 V±0.5 V, VSS = 0 V, Ta = –20 to 85 °C, f(f sys) = 26 MHz, unless otherwise noted)
Symbol
HLDA output delay time
HLDA low-level output delay time after read
HLDA low-level output delay time after write
Floating start delay time
Floating start delay time
Floating start delay time
Floating start delay time
Floating start delay time
Floating release delay time
Floating release delay time
Floating release delay time
Floating release delay time
Floating release delay time
Parameter Min.
tc –15 (Note)
tc –15 (Note)
–15
–15
–15
–15
–15
0
0
0
0
0
Limits Max.
20
10
10
10
10
10
Unit
Note: tc = 1/f(fsys).
7902 Group User’s Manual 21-119
APPENDIX
Appendix 9. M37902FGCGP electrical characteristics
φ
1
RDY input
tsu (RDY-φ
1
)
RD,
BLW,
BHW
: Wait inserted by software (The above is applied when bus cycle = 1φ + 2φ)
: Wait inserted by ready function
RDY input
th (φ
1
-RDY)
Test conditions
• VCC = 5 V ± 0.5 V, Ta= –20 to 85 °C
• RDY input, HOLD input : VIL = 0.8V, VIH = 2.15 V
• HLDA output : VOL = 0.8V, VOH = 2.0 V, CL = 50 pF
φ
1
HOLD input
tsu (HOLD-φ1)
td (φ1-HLDAL)
tpxz (HLDAL-RDZ)
tpxz (HLDAL-BXWZ)
tpxz (HLDAL-CSiZ)
tpxz (HLDAL-AZ)
th (φ1-HOLD)
td (φ1-HLDAL)
tpzx (HLDAL-RDZ)
tpzx (HLDAL-BXWZ)
tpzx (HLDAL-CSiZ)
tpzx (HLDAL-ALEZ)
tpzx (HLDAL-AZ)
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
HOLD input
HLDA output
RD
BLW
BHW
CSi
A0–A23 output
td (RDH-HLDAL)
t
d (BXWH-HLDAL)
tpxz (HLDAL-ALEZ)
ALE
APPENDIX
7902 Group User’s Manual
21-120
Appendix 9. M37902FGCGP electrical characteristics
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tc(in)
tw(harf)
tw(H)
tw(L)
tr
tf
ta(A-D)
ta(A-D)
ta(CSiL-D)
ta(RDL-D)
tsu(D-RDL)
th(RDH-D)
ta(BA-D)
th(BA-D)
ta(LA-D)
Max.
0.55 tc
(WH + WL) tc-45
(WH + WL-0.5) tc-35
(WH + WL-0.5) tc-35
WL tc-30
WL tc-35
Min.
38
0.45 tc
0.5 tc – 6
0.5 tc – 6
6
6
15
0
8
(W
H
+ W
L
-0.5)tc-35 (Note)
External clock input cycle time
External clock input pulse width with half input-volage
External clock input high-level pulse width
External clock input low-level pulse width
External clock input rise time
External clock input fall time
Address access time (the address output select bit = 0)
Address access time (the address output select bit = 1)
Chip select access time
Read access time
Read data setup time
Data input hold time after read
Address access time at burst ROM access
Data hold time after address at burst ROM access
Address access time (the multiplexed bus select bit = 1)
1
φ
+1
φ
1
φ
+2
φ
1
φ
+3
φ
2
φ
+2
φ
Limits
External bus timing
For limits depending on f(fsys), their calculation formulas are shown below.
Symbol Parameter Unit
External clock input trtf
tw(L) tw(H) tw(half)
XIN
tc(in)
Test conditions
• Vcc = 5 V ± 0.5 V, Ta = –20 to 85 °C
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V (tw(H), tw(L), tr, tf)
• Output timing voltage : 2.5 V (tc(in), tw(half))
Bus cycle WHWL
1
1
1
2
1
2
3
2
Bus cycle WHWL
2
φ
+3
φ
2
φ
+4
φ
3
φ
+3
φ
3
φ
+4
φ
2
2
3
3
3
4
3
4
tc = 1/f(fsys).
Timing Requirements (VCC = 5 V±0.5 V, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 26 MHz, unless otherwise noted)
Note: This is independent of the address output select bit’s contents.
7902 Group User’s Manual 21-121
APPENDIX
Appendix 9. M37902FGCGP electrical characteristics
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Bus cycle = 2φ + 2φ
Bus cycle = 3φ + 3φ, 3φ + 4φ
td(φ1-RDL)
td(φ1-RDH)
td(φ1-BXWL)
td(φ1-BXWH)
td(φ1L-CSiL)
td(φ1L-CSiH)
td(φ1H-A)
td(φ1L-A)
tw(ALEH)
td(A-ALEL)
tw(RDL)
tw(RDH)
td(RDH-BXWH)
td(A-RDH)
td(A-RDH)
th(RDH-A)
th(RDH-A)
td(RDH-ALEL)
td(ALEL-RDH)
td(CSiL-RDH)
td(CSiL-RDL)
th(RDH-CSiL)
td(RDH-D)
tw(BXWL)
tw(BXWH)
td(BXWH-RDH)
td(A-BXWH)
td(A-BXWH)
th(BXWH-A)
th(BXWH-A)
td(BXWH-ALEL)
td(ALEL-BXWH)
td(CSiL-BXWH)
td(CSiL-BXWL)
th(BXWH-CSiL)
td(D-BXWL)
th(BXWH-D)
tpxz(BXWH-DZ)
Parameter
Switching characteristics (VCC = 5 V±0.5 V, VSS = 0 V, Ta = –20 to 85 °C, f(fsys) = 26 MHz, unless otherwise noted)
Max.
0
0
0
0
0
10
25
16
20
20
0.5tc + 10
Min.
–18
–18
–18
–18
–20
–22
–5
–20
0.5tc-19
tc-20
1.5tc-20
tc-30
1.5tc-30
2tc-30
0.5tc-19
tc-20
1.5tc-20
WL tc-15
WH tc-15
tc-15
WH tc-30
(WH-0.5)tc-19
8
0.5tc-10
0.5tc-19
tc-15
(WH-0.5)tc-19
(W
H
+ W
L
-0.5)tc-20
0.5tc-14
tc-15
WL tc-15
WH tc-15
tc-15
WH tc-30
(WH-0.5)tc-19
8
0.5tc-10
0.5tc-19
tc-15
(WH-0.5)tc-19
(WH + WL-0.5)tc-20
0.5tc-14
WL tc-20
0.5tc-10
Read low-level output delay time
Read high-level output delay time
Write low-level output delay time
Write high-level output delay time
Chip select low-level output delay time
Chip select high-level output delay time
Address output delay time (the address output select bit = 0)
Address output delay time (the address output select bit = 1)
ALE pulse width
ALE completion delay time
after address stabilization
(when the address output
select bit = 0)
ALE completion delay time
after address stabilization
(when the address output
select bit = 1)
Read output pulse width
Read output high-level width (Note 1)
Write disable valid time after read (Note 2)
Address valid time before read (when the address output select bit = 0)
Address valid time before read (when the address output select bit = 1)
Address hold time after read (when the address output select bit = 0) (Note 2)
Address hold time after read (when the address output select bit = 1) (Note 2)
ALE completion delay time after read start
Read disable valid time
after ALE completion
Chip select valid time before read
Chip select output valid time before read completion
Chip select hold time after read
Next write cycle data output delay time after read (Note 2)
Write output pulse width
Write output high-level width (Note 1)
Read disable valid time after write (Note 2)
Address valid time before write (when the address output select bit = 0)
Address valid time before write (when the address output select bit = 1)
Address hold time after write (when the address output select bit = 0) (Note 2)
Address hold time after write (when the address output select bit = 1) (Note 2)
ALE completion delay time after write start
Write disable valid time
after ALE completion
Chip select valid time before write
Chip select output valid time before write completion
Chip select hold time after write
Data output valid time before write completion
Data hold time after write (Note 3)
Floating start delay time after write (Note 3)
Limits
Symbol Unit
Bus cycle = 1φ + 1φ, 1φ + 2φ, 1φ + 3φ
Bus cycle = 2φ + 2φ
Bus cycle = 2φ + 3φ, 2φ + 4φ, 3φ + 3φ, 3φ + 4φ
Bus cycle = 1φ + 1φ, 1φ + 2φ, 1φ + 3φ
Bus cycle = 2φ + 2φ
Bus cycle = 2φ + 3φ, 2φ + 4φ, 3φ + 3φ, 3φ + 4φ
Bus cycle = 2φ + 2φ
Bus cycle = 2φ + 3φ, 2φ + 4φ, 3φ + 3φ, 3φ + 4φ
Notes 1: When the bus cycle just before this parameter is for the area where the recovery cycle insertion is selected, this parameter is extended by tc (ns: one reco-
very cycle is inserted.) or by 2tc (ns: two recovery cycles are inserted.).
2: When accessing the area where the recovery cycle insertion is selected, this parameter is extended by tc (ns: one recovery cycle is inserted.) or by 2tc (ns:
two recovery cycles are inserted.).
3: This parameter is extended by tc (ns) when both of the following conditions are satisfied:
• When accessing the area where the recovery cycle insertion is selected.
• When two recovery cycles are inserted.
Bus cycle = 1φ + 1φ, 1φ + 2φ, 1φ + 3φ
Bus cycle = 2φ + 2φ
Bus cycle = 2φ + 3φ, 2φ + 4φ, 3φ + 3φ, 3φ + 4φ
APPENDIX
7902 Group User’s Manual
21-122
Appendix 9. M37902FGCGP electrical characteristics
ns
ns
ns
ns
ns
ns
ns
ns
td(LA-RDH)
td(LA-ALEL)
th(ALEL-LA)
tpxz(RDH-LAZ)
td(LA-BXWH)
tpzx(RDH-DZ)
Address valid time before read
ALE completion delay time
after address stabilization
Address hold time after
ALE completion
Floating start delay time
Address valid time before write
Floating release delay time
Bus cycle = 2φ + 2φ
Bus cycle = 3φ + 3φ, 3φ + 4φ
Bus cycle = 2φ + 2φ
Bus cycle = 3φ + 3φ, 3φ + 4φ
Switching characteristics (VCC = 5 V±0.5 V, VSS = 0 V, Ta = –20 to 85 °C, f(fsys) = 26 MHz, unless otherwise noted)
Parameter Max.
5
Min.
(WH-0.5)tc-19 (Note)
tc-20 (Note)
1.5tc-20 (Note)
0.5tc-19
tc-15
(WH-0.5)tc-19 (Note)
0.5tc-19 (Note)
Limits
Symbol Unit
Note: This is independent of the address output select bit’s contents.
7902 Group User’s Manual 21-123
APPENDIX
Appendix 9. M37902FGCGP electrical characteristics
Bus cycle
th(RDH-D)
th(RDH-A)
tw(RDL)
ta(CSiL-D)
ta(RDL-D)
ta(A-D)
td(CSiL-RDL)
tsu(D-RDL)
tw(ALEH)
td(RDH-ALEL)
tc
td(A-ALEL)
tw(RDH)
td(RDH-D)
td(φ1-RDL)
th(RDH-A)
td(A-RDH)
td(CSiL-RDH)
ta(A-D)
td(A-ALEL)
td(φ1H-A) td(φ1L-A)
td(φ1L-CSiL) td(φ1L-CSiH)
td(φ1-RDH)
th(RDH-CSiL)
td(RDH-BXWH)
td(A-RDH)
CSi
RD
ALE
φ1
fsys
BLW
BHW
<At read>
Normal access: bus cycle = 1φ + 1φ, 1φ + 2φ, 1φ+ 3φ,
2φ + 3φ, or 2φ + 4φ
A0–A23
(when the address output select bit = 0)
A0–A23
(when the address output select bit = 1)
D0–D7, D8–D15
Test conditions
• VCC = 5 V ±0.5 V, Ta = –20 to 85 °C
• Input timing voltage : VIL=0.8 V, VIH=2.15 V
• Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=15 pF (CSi)
• Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=50 pF (except for CSi)
APPENDIX
7902 Group User’s Manual
21-124
Appendix 9. M37902FGCGP electrical characteristics
t
h(BXWH-A)
t
d(CSiL-BXWL)
t
w(BXWL)
t
d(BXWH-ALEL)
t
d(D-BXWL)
t
h(BXWH-D)
t
pxz(BXWH-DZ)
Bus cycle
t
d(φ1-BXWL)
t
h(BXWH-A)
t
d(A-BXWH)
t
d(CSiL-BXWH)
t
c
t
d(A-ALEL)
t
w(ALEH)
t
d(φ1H-A)
t
d(φ1L-CSiL)
t
d(φ1L-CSiH)
t
d(BXWH-RDH)
t
d(φ1-BXWH)
t
h(BXWH-CSiL)
t
d(A-ALEL)
t
w(BXWH)
t
d(A-BXWH)
t
d(φ1L-A)
CS
i
RD
ALE
BLW
BHW
φ
1
f
sys
<At write>
Normal access: bus cycle = 1φ + 1φ, 1φ + 2φ, 1φ + 3φ,
2φ + 3φ, or 2φ + 4φ
A
0
–A
23
(when the address output select bit = 0)
A
0
–A
23
(when the address output select bit = 1)
D
0
–D
7
, D
8
–D
15
Test conditions
• V
CC
= 5 V ±0.5 V, Ta = –20 to 85 °C
• Input timing voltage : V
IL
=0.8 V, V
IH
=2.15 V
• Output timing voltage: V
OL
=0.8 V, V
OH
=2.0 V, C
L
=15 pF (CS
i
)
• Output timing voltage: V
OL
=0.8 V, V
OH
=2.0 V, C
L
=50 pF (except for CS
i
)
7902 Group User’s Manual 21-125
APPENDIX
Appendix 9. M37902FGCGP electrical characteristics
t
d(A-RDH)
Bus cycle
t
d(CSiL-RDL)
t
d(A-ALEL)
t
h(RDH-D)
t
h(RDH-A)
t
w(RDL)
t
a(CSiL-D)
t
a(RDL-D)
t
a(A-D)
t
su(D-RDL)
t
w(ALEH)
t
c
t
w(RDH)
t
d(RDH-D)
t
d(ALEL-RDH)
t
d(φ1-RDL)
t
d(φ1-RDH)
t
h(RDH-D)
t
a(LA-D)
t
a(RDL-D)
t
d(LA-RDH)
t
su(D-RDL)
t
pzx(RDH-DZ)
t
d(LA-ALEL)
t
h(ALEL-LA)
t
pxz(RDH-LAZ)
t
h(RDH-A)
t
d(A-RDH)
t
d(CSiL-RDH)
t
a(A-D)
Address Input data Address
t
d(φ1H-A)
t
d(φ1L-CSiL)
t
d(φ1L-CSiH)
t
d(RDH-BXWH)
t
h(RDH-CSiL)
t
d(A-ALEL)
t
d(φ1L-A)
CS
i
RD
ALE
BLW
BHW
f
sys
φ
1
Note: Valid only when area CS
2
is accessed with the external data bus width = 8 bits.
<At read>
Normal access: bus cycle = 2φ + 2φ, 3φ + 3φ, 3φ + 4φ
A
0
–A
23
(when the address output
select bit = 0)
D
0
–D
7
, D
8
–D
15
(when the multiplexed
bus select bit = 0)
LA
0
/D
0
–LA
7
/D
7
(when the multiplexed
bus select bit = 1, Note)
A
0
–A
23
(when the address output
select bit = 1)
Test conditions
• V
CC
= 5 V ±0.5 V, Ta = –20 to 85 °C
• Input timing voltage : V
IL
=0.8 V, V
IH
=2.15 V
• Output timing voltage: V
OL
=0.8 V, V
OH
=2.0 V, C
L
=15 pF (CS
i
)
• Output timing voltage: V
OL
=0.8 V, V
OH
=2.0 V, C
L
=50 pF (except for CS
i
)
APPENDIX
7902 Group User’s Manual
21-126
Appendix 9. M37902FGCGP electrical characteristics
t
d(CSiL-BXWL)
t
h(BXWH-A)
t
d(A-BXWH)
t
w(ALEH)
t
w(BXWL)
t
d(D-BXWL)
t
h(BXWH-D)
t
pxz(BXWH-DZ)
t
d(A-ALEL)
t
w(BXWH)
t
d(ALEL-BXWH)
Bus cycle
t
d(φ1-BXWL)
t
h(BXWH-D)
t
pxz(BXWH-DZ)
t
d(D-BXWL)
t
h(ALEL-LA)
t
d(LA-ALEL)
t
d(LA-BXWH)
t
c
t
h(BXWH-A)
t
d(A-BXWH)
t
d(CSiL-BXWH)
Address Output data
t
d(φ1-BXWH)
t
d(φ1H-A)
t
d(φ1L-CSiL)
t
d(φ1L-CSiH)
t
d(A-ALEL)
t
h(BXWH-CSiL)
t
d(BXWH-RDH)
t
d(φ1L-A)
CS
i
RD
ALE
BLW
BHW
f
sys
φ
1
Note: Valid only when area CS
2
is accessed with the external data bus width = 8 bits.
<At write>
Normal access: bus cycle = 2φ + 2φ, 3φ + 3φ, 3φ + 4φ
A
0
–A
23
(when the address output
select bit = 0)
D
0
–D
7
, D
8
–D
15
(when the multiplexed
bus select bit = 0)
LA
0
/D
0
–LA
7
/D
7
(when the multiplexed
bus select bit = 1, Note)
A
0
–A
23
(when the address output
select bit = 1)
Test conditions
• V
CC
= 5 V ±0.5 V, Ta = –20 to 85 °C
• Input timing voltage : V
IL
=0.8 V, V
IH
=2.15 V
• Output timing voltage: V
OL
=0.8 V, V
OH
=2.0 V, C
L
=15 pF (CS
i
)
• Output timing voltage: V
OL
=0.8 V, V
OH
=2.0 V, C
L
=50 pF (except for CS
i
)
7902 Group User’s Manual 21-127
APPENDIX
Appendix 9. M37902FGCGP electrical characteristics
t
h(BA-D)
t
d(RDH-BXWH)
BLW
BHW
RD
t
a(RDL-D)
t
d(A-RDH)
CS
i
t
h(RDH-A)
t
a(CSiL-D)
t
a(A-D)
t
a(BA-D)
t
h(BA-D)
t
h(BA-D)
t
h(RDH-D)
t
a(BA-D)
t
a(BA-D)
t
h(RDH-CSiL)
t
d(CSiL-RDH)
t
d(A-ALEL)
t
w(ALEH)
ALE
t
d(RDH-ALEL)
t
w(RDH)
t
d(A-RDH)
t
h(RDH-A)
t
a(A-D)
Burst ROM access: bus cycle = 1φ + 1φ, 1φ + 2φ, 1φ + 3φ, 2φ + 3φ, 2φ + 4φ
D
0
–D
7
, D
8
–D
15
Test conditions
• V
CC
= 5 V ±0.5 V, Ta = –20 to 85 °C
• Input timing voltage : V
IL
=0.8 V, V
IH
=2.15 V
• Output timing voltage: V
OL
=0.8 V, V
OH
=2.0 V, C
L
=15 pF (CS
i
)
• Output timing voltage: V
OL
=0.8 V, V
OH
=2.0 V, C
L
=50 pF (except for CS
i
)
A
0
–A
23
(when the address output select bit = 0)
A
0
–A
23
(when the address output select bit = 1)
t
d(A-ALEL)
APPENDIX
7902 Group User’s Manual
21-128
Appendix 10. M37902FGMHP electrical characteristics
Unit
V
V
V
V
mW
°C
°C
Appendix 10. M37902FGMHP electrical characteristics
The electrical characteristics of the M37902FGMHP are described below.
For the electrical characteristics, be sure to refer to the latest datasheets.
Parameter
Power source voltage
Analog power source voltage
Input voltage P00–P07, P10–P17, P20–P27, P30–P33, P40–P47, P50–P57,
P60–P67, P70–P77, P80–P87, P100–P107, P110–P117,
VREF, XIN, RESET, BYTE, MD0, MD1, NMI, VCONT
Output voltage P00–P07, P10–P17, P20–P27, P30–P33, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87, P100–P107,
P110–P117, XOUT
Power dissipation
Operating ambient temperature
Storage temerature
Symbol
VCC
AVCC
VI
VO
Pd
Topr
Tstg
ABSOLUTE MAXIMUM RATINGS Ratings
–0.3 to 4.6
–0.3 to 4.6
–0.3 to VCC+0.3
–0.3 to VCC+0.3
300
–20 to 85
–40 to 150
7902 Group User’s Manual 21-129
APPENDIX
Appendix 10. M37902FGMHP electrical characteristics
Parameter
Power source voltage
Analog power source voltage
Power source voltage
Analog power source voltage
High-level input voltage XIN, RESET, BYTE, MD0, MD1
High-level input voltage P10–P17, P20–P27, P30–P33, P40–P47, P50–P57,
P60–P67, P70–P77, P80–P87, P100–P107, P110–P117
High-level input voltage P00–P07 (When the port P0 input level select bit = “0”)
High-level input voltage P00–P07 (When the port P0 input level select bit = “1”)
High-level input voltage D0–D7, D8–D15
High-level input voltage RDY, HOLD, TA0IN–TA4IN, TA0OUT–TA4OUT,
TB0IN–TB2IN, KI0–KI3, INT0–INT4, NMI, ADTRG, CTS0,
CTS1, CLK0, CLK1, RxD0, RxD1
High-level input voltage SCLK, SDA (Note 1)
Low-level input voltage XIN, RESET, BYTE, MD0, MD1
Low-level input voltage P10–P17, P20–P27, P30–P33, P40–P47, P50–P57,
P60–P67, P70–P77, P80–P87, P100–P107, P110–P117
Low-level input voltage P00–P07 (When the port P0 input level select bit = “0”)
Low-level input voltage P00–P07 (When the port P0 input level select bit = “1”)
Low-level input voltage D0–D7, D8–D15
Low-level input voltage RDY, HOLD, TA0IN–TA4IN, TA0OUT–TA4OUT,
TB0IN–TB2IN, KI0–KI3, INT0–INT4, NMI, ADTRG, CTS0,
CTS1, CLK0, CLK1, RxD0, RxD1
Low-level input voltage SCLK, SDA (Note 1)
High-level peak output current P00–P07, P10–P17, P20–P27, P30–P33, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87,
P100–P107, P110–P117
High-level average output current P00–P07, P10–P17, P20–P27, P30–P33,
P40–P47, P50–P57, P60–P67, P70–P77,
P80–P87, P100–P107, P110–P117
Low-level peak output current P00–P07, P10–P17, P20–P27, P30–P33,
P40–P47, P50–P57, P60–P67, P70–P77,
P80–P87, P100–P107, P110–P117
Low-level average output current P00–P07, P10–P17, P20–P27, P30–P33,
P40–P47, P50–P57, P60–P67, P70–P77,
P80–P87, P100–P107, P110–P117
External clock input frequency (Note 2)
System clock frequency
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
MHz
MHz
Max.
3.6
Vcc
VCC
Vcc
Vcc
Vcc
Vcc
Vcc
0.2 VCC
0.2 VCC
0.2 VCC
0.16 VCC
0.22 VCC
0.16 VCC
0.16 VCC
–10
–5
10
5
26
26
Symbol
VCC
AVCC
VSS
AVSS
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
VIL
VIL
IOH(peak)
IOH(avg)
IOL(peak)
IOL(avg)
f(XIN)
f(fsys)
RECOMMENDED OPERATING CONDITIONS (Vcc = 3.3 V, Ta = –20 to 85 °C, unless otherwise noted)
Notes 1: Pins SCLK and SDA are used only in the flash memory serial I/O mode.
2: When using the PLL frequency multiplier, be sure that f(fsys) = 26 MHz or less.
3: Average output current is the average value of an interval of 100 ms.
4: The sum of IOL(peak) for ports P0–P2, P8, P10, and P11 must be 80 mA or less, the sum of I OH(peak) for ports P0–P2, P8, P10, and P11 must be 80
mA or less, the sum of IOL(peak) for ports P3–P7 must be 80 mA or less, the sum of IOH(peak) for ports P3–P7 must be 80 mA or less.
Limits
Min.
3.0
0.8 Vcc
0.7 VCC
0.7 Vcc
0.5 Vcc
0.5 Vcc
0.5 Vcc
0.5 Vcc
0
0
0
0
0
0
0
Typ.
3.3
VCC
0
0
APPENDIX
7902 Group User’s Manual
21-130
Appendix 10. M37902FGMHP electrical characteristics
µ
A
mA
V
mA
µ
A
Unit
V
V
V
V
V
V
V
V
µ
A
f(fsys) = 26 MHz.
CPU operates.
Ta = 25 °C when
clock is stopped.
Ta = 85 °C when
clock is stopped.
Test conditions
IOH = –1 mA
IOH = –1 mA
IOL = 1 mA
IOL = 1 mA
VI = 3.3 V
VI = 0 V
VI = 0 V, No pullup transistor
VI = 0 V, Pullup transistor used
When clock is stoped.
Parameter
High-level output voltage P00–P07, P10–P17,
P20–P27, P30, P40–P47,
P50–P57, P60–P67,
P70–P77, P80–P87,
P100–P107, P110–P117
High-level output voltage P31–P33
Low-level output voltage P00–P07, P10–P17,
P20–P27, P30, P40–P47,
P50–P57, P60–P67,
P70–P77, P80–P87,
P100–P107, P110–P117
Low-level output voltage P31–P33
Hysteresis RDY, HOLD, TA0IN–TA4IN,
TA0OUT–TA4OUT, TB0IN–TB2IN,
KI0–KI3, INT0–INT4, NMI, ADTRG,
CTS0, CTS1, CLK0, CLK1, RxD0, RxD1
Hysteresis RESET
Hysteresis XIN
High-level input current
P00–P07, P10–P17,
P2
0
–P2
7
, P3
0
–P3
3
, P4
0
–P4
7
,
P5
0
–P5
7
, P6
0
–P6
7
, P7
0
–P7
7
,
P80–P87, P100–P107,
P110–P117, XIN, RESET,
BYTE, MD0, MD1, NMI
Low-level input current
P00–P07, P10–P17,
P2
0
–P2
7
, P3
0
–P3
3
, P4
0
–P4
3
,
P5
0
–P5
3
, P6
0
–P6
7
, P7
0
–P7
7
,
P80–P87, P100–P107,
P110–P117, XIN, RESET,
BYTE, MD0, MD1
Low-level input current
P4
4
–P4
7
,
P54–P57, NMI
RAM hold voltage
Power source current
Symbol
VOH
VOH
VOL
VOL
VT+ —VT
VT+ —VT
VT+ —VT
IIH
IIL
IIL
VRAM
ICC
Min.
2.5
2.6
0.08
Limits
Typ.
–0.36
15.6
Max.
0.5
0.4
0.5
1
0.26
4
–4
–4
–0.54
31.2
1
20
Output-only pins
are open, and the
other pins are con-
nected to Vss or
Vcc. An external
square-waveform
clock is input. (Pin
X
OUT
is open.) The
PLL frequency
multiplier stops its
operation.
DC ELECTRICAL CHARACTERISTICS (Vcc = 3.3 V, Vss = 0 V, Ta = –20 to 85 °C, f(fsys) = 26 MHz, unless otherwise noted)
–0.20
2
0.3
0.05
7902 Group User’s Manual 21-131
APPENDIX
Appendix 10. M37902FGMHP electrical characteristics
Bits
%
µ
s
k
mA
Bits
LSB
LSB
k
µ
s
V
V
Resolution
Absolute accuracy
Ladder resistance
Conversion time
Reference voltage
Analog input voltage
—————
—————
RLADDER
tCONV
VREF
VIA
VREF = VCC
VREF = VCC
VREF = VCC
f(fsys) 26 MHz
Max.
A-D CONVERTER CHARACTERISTICS
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
UnitParameterSymbol Test conditions Limits
Min.
10-bit resolution mode
8-bit resolution mode
10-bit resolution mode
8-bit resolution mode
5
4.54
1.89 (Note)
2.7
0
10
± 3
± 2
VCC
VREF
Note: This is applied when A-D conversion freguency (
φ
AD) = f1.
D-A CONVERTER CHARACTERISTICS
(VCC = 3.3 V, VSS = AVSS = 0 V, VREF = 3.3 V, Ta = –20 to 85 °C, unless otherwise noted)
Unit
ParameterSymbol Limits
Typ.Min. Max.
Test conditions
Resolution
Absolute accuracy
Set time
Output resistance
Reference power source input current
——
——
tsu
RO
IVREF (Note) 1 2.5
8
± 1.0
3
4
3.2
Note: The test conditions are as follows:
• One D-A converter is used.
• The D-A register value of the unused D-A converter is “0016.”
• The reference power source input current for the ladder resistance of the A-D converter is excluded.
µ
s
RESET input low-level pulse width
tw(RESETL)
Symbol Parameter Min. Limits Unit
RESET INPUT
Reset input timing requirements (VCC = 3.3 V ± 0.3 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted)
2
Max.Typ.
RESET input tw(RESETL)
APPENDIX
7902 Group User’s Manual
21-132
Appendix 10. M37902FGMHP electrical characteristics
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tc(TA)
tw(TAH)
tw(TAL)
f(fsys)
26 MHz
f(fsys)
26 MHz
f(fsys)
26 MHz
PERIPHERAL DEVICE INPUT/OUTPUT TIMING
(VCC = 3.3 V±0.3 V, VSS = 0 V, Ta = –20 to 85 °C, f(fsys) = 26 MHz unless otherwise noted)
For limits depending on f(fsys), their calculation formulas are shown below. Also, the values at f(fsys) = 26 MHz are shown in ( ).
Timer A input (Up-down input and Count input in event counter mode)
tc(UP)
tw(UPH)
tw(UPL)
tsu(UP-TIN)
th(TIN-UP)
Symbol
TAiOUT input cycle time
TAiOUT input high-level pulse width
TAiOUT input low-level pulse width
TAiOUT input setup time
TAiOUT input hold time
Parameter Limits
Min.
2000
1000
1000
400
400
Max. Unit
Timer A input (External trigger input in pulse width modulation mode)
tw(TAH)
tw(TAL)
Symbol
TAiIN input high-level pulse width
TAiIN input low-level pulse width
Parameter Min.
80
80
LimitsMax. Unit
Limits
Symbol Parameter Min. Max. Unit
8 × 109
f(fsys)(307)
TAiIN input cycle time
TAiIN input high-level pulse width
TAiIN input low-level pulse width 80
80
Timer A input (External trigger input in one-shot pulse mode)
Limits
Symbol Parameter Min. Max. Unit
16 × 109
f(fsys)
8 × 109
f(fsys)
8 × 109
f(fsys)
(615)
(307)
(307)
tc(TA)
tw(TAH)
tw(TAL)
TAiIN input cycle time
TAiIN input high-level pulse width
TAiIN input low-level pulse width
Timer A input (Gating input in timer mode)
Note :The TAiIN input cycle time requires 4 or more cycles of a count source. The TAiIN input high-level pulse width and the TAiIN input low-level pulse width
respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(f sys)
26 MHz.
Timer A input (Count input in event counter mode)
tc(TA)
tw(TAH)
tw(TAL)
Symbol
TAiIN input cycle time
TAiIN input high-level pulse width
TAiIN input low-level pulse width
Parameter Min.
80
40
40
LimitsMax. Unit
f(fsys) 26 MHz
7902 Group User’s Manual 21-133
APPENDIX
Appendix 10. M37902FGMHP electrical characteristics
ns
ns
ns
tc(TA)
tsu(TAjIN-TAjOUT)
tsu(TAjOUT-TAjIN)
Symbol Parameter Min.
800
200
200
LimitsMax. Unit
Timer A input (Two-phase pulse input in event counter mode)
TAiIN input cycle time
TAjIN input setup time
TAjOUT input setup time
TAiIN input
TAiOUT input
(Up-down input)
TAiOUT input
(Up-down input)
TAiIN input
(When count by falling)
TAiIN input
(When count by rising)
TAjIN input
TAjOUT input
Test conditions
• VCC = 3.3 V±0.3 V, Ta = –20 to 85 °C
• Input timing voltage : VIL = 0.53 V, VIH = 1.65 V
• Up-down and Count input in event counter mode
• Two-phase pulse input in event counter mode
• Gating input in timer mode
• Count input in event counter mode
• External trigger input in one-shot pulse mode
• External trigger input in pulse width modulation mode tc(TA)
tw(TAH)
tw(TAL)
tc(UP)
tw(UPH)
tw(UPL)
t
h(TIN-UP)
tsu(TAjIN-TAjOUT)tsu(TAjIN-TAjOUT)
tsu(TAjOUT-TAjIN)
tsu(TAjOUT-TAjIN)
tc(TA)
t
su(UP-TIN)
APPENDIX
7902 Group User’s Manual
21-134
Appendix 10. M37902FGMHP electrical characteristics
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
f(fsys) 26 MHz
f(fsys) 26 MHz
f(fsys) 26 MHz
f(fsys) 26 MHz
f(fsys) 26 MHz
f(fsys) 26 MHz
tc(TB)
tw(TBH)
tw(TBL)
tc(TB)
tw(TBH)
tw(TBL)
Timer B input (Count input in event counter mode)
Symbol
TBiIN input cycle time (one edge count)
TBiIN input high-level pulse width (one edge count)
TBiIN input low-level pulse width (one edge count)
TBiIN input cycle time (both edge count)
TBiIN input high-level pulse width (both edge count)
TBiIN input low-level pulse width (both edge count)
Parameter Limits
Min.
80
40
40
160
80
80
Max. Unit
Limits
Symbol Parameter Min. Max. Unit
16 × 109
f(fsys)
8 × 109
f(fsys)
8 × 109
f(fsys)
(615)
(307)
(307)
tc(TB)
tw(TBH)
tw(TBL)
TBiIN input cycle time
TBiIN input high-level pulse width
TBiIN input low-level pulse width
Timer B input (Pulse period measurement mode)
Note: The TBiIN input cycle time requires 4 or more cycles of a count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width
respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f 2 at f(fsys) 26 MHz.
Limits
Symbol Parameter Min. Max. Unit
16 × 109
f(fsys)
8 × 109
f(fsys)
8 × 109
f(fsys)
(615)
(307)
(307)
tc(TB)
tw(TBH)
tw(TBL)
TBiIN input cycle time
TBiIN input high-level pulse width
TBiIN input low-level pulse width
Timer B input (Pulse width measurement mode)
Note: The TBiIN input cycle time requires 4 or more cycles of a count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width
respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f 2 at f(fsys) 26 MHz.
tc(AD)
tw(ADL)
Symbol
ADTRG input cycle time (minimum allowable trigger)
ADTRG input low-level pulse width
Parameter Min.
1000
125
LimitsMax. Unit
A-D trigger input
7902 Group User’s Manual 21-135
APPENDIX
Appendix 10. M37902FGMHP electrical characteristics
ns
ns
ns
ns
ns
ns
ns
ns
ns
tc(CK)
tw(CKH)
tw(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
Serial I/O
Symbol
CLKi input cycle time
CLKi input high-level pulse width
CLKi input low-level pulse width
TXDi output delay time
TXDi hold time
RXDi input setup time
RXDi input hold time
Parameter Limits
Min.
200
100
100
0
20
90
Max.
80
Unit
tw(INH)
tw(INL)
Symbol
INTi input/NMI input/KIi input high-level pulse width
INTi input/NMI input/KIi input low-level pulse width
Parameter Min.
250
250
LimitsMax. Unit
External interrupt (INTi) input, NMI input, Key input interrupt (KIi) input
t
c(TB)
t
w(TBH)
t
w(TBL)
t
c(CK)
t
w(CKH)
t
w(CKL)
t
h(C - Q)
t
d(C - Q)
t
su(D - C)
t
w(INH)
t
w(INL)
t
h(C - D)
t
c(AD)
t
w(ADL)
TBi
IN
input
INTi input,
AD
TRG
input
CLKi input
TxDi output
RxDi input
NMI input,
KIi input
Test conditions
• Vcc = 3.3 V±0.3 V, Ta = –20 to 85°C
• Input timing voltage : V
IL
= 0.53 V, V
IH
= 1.65 V
•Output timing voltage : V
OL
= 0.8 V, V
OH
= 2.0 V, C
L
= 50 pF
APPENDIX
7902 Group User’s Manual
21-136
Appendix 10. M37902FGMHP electrical characteristics
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
td(
φ
1-HLDAL)
td(RDH-HLDAL)
t
d(BXWH-HLDAL)
t
pxz(HLDAL-RDZ)
t
pxz(HLDAL-BXWZ)
t
pxz(HLDAL-CSiZ)
t
pxz(HLDAL-ALEZ)
tpxz(HLDAL-AZ)
t
pzx(HLDAL-RDZ)
t
pzx(HLDAL-BXWZ)
t
pzx(HLDAL-CSiZ)
t
pzx(HLDAL-ALEZ)
tpzx(HLDAL-AZ)
tsu(RDY-
φ
1)
tsu(HOLD-
φ
1)
th(
φ
1-RDY)
th(
φ
1-HOLD)
Symbol
RDY input setup time
HOLD input setup time
RDY input hold time
HOLD input hold time
Parameter Limits
Min.
40
40
0
0
Max. Unit
Symbol
HLDA output delay time
HLDA low-level output delay time after read
HLDA low-level output delay time after write
Floating start delay time
Floating start delay time
Floating start delay time
Floating start delay time
Floating start delay time
Floating release delay time
Floating release delay time
Floating release delay time
Floating release delay time
Floating release delay time
Parameter Min.
tc –15 (Note)
tc –15 (Note)
–15
–15
–15
–15
–15
0
0
0
0
0
Limits Max.
20
10
10
10
10
10
Unit
Note: tc = 1/f(fsys).
Switching characteristics (VCC = 3.3 V±0.3 V, VSS = 0 V, Ta = –20 to 85 °C, f(fsys) = 26 MHz, unless otherwise noted)
READY, HOLD TIMING
Timing requirements (VCC = 3.3 V±0.3 V, VSS = 0 V, Ta = –20 to 85 °C, f(fsys) = 26 MHz, unless otherwise noted)
7902 Group User’s Manual 21-137
APPENDIX
Appendix 10. M37902FGMHP electrical characteristics
φ
1
RDY input
tsu (RDY-φ
1
)
RD,
BLW,
BHW
: Wait inserted by software (The above is applied when bus cycle = 1φ + 2φ)
: Wait inserted by ready function
RDY input
th (φ
1
-RDY)
Test conditions
• VCC = 3.3 V ± 0.3 V, Ta= –20 to 85 °C
• RDY input, HOLD input:VIL = 0.53 V, VIH = 1.65 V
• HLDA output : VOL = 0.8V, VOH = 2.0 V, CL = 50 pF
φ
1
HOLD input
tsu (HOLD-φ1)
td (φ1-HLDAL)
tpxz (HLDAL-RDZ)
tpxz (HLDAL-BXWZ)
tpxz (HLDAL-CSiZ)
tpxz (HLDAL-AZ)
th (φ1-HOLD)
td (φ1-HLDAL)
tpzx (HLDAL-RDZ)
tpzx (HLDAL-BXWZ)
tpzx (HLDAL-CSiZ)
tpzx (HLDAL-ALEZ)
tpzx (HLDAL-AZ)
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
HOLD input
HLDA output
RD
BLW
BHW
CSi
A0–A23 output
td (RDH-HLDAL)
t
d (BXWH-HLDAL)
tpxz (HLDAL-ALEZ)
ALE
APPENDIX
7902 Group User’s Manual
21-138
Appendix 10. M37902FGMHP electrical characteristics
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tc(in)
tw(harf)
tw(H)
tw(L)
tr
tf
ta(A-D)
ta(A-D)
ta(CSiL-D)
ta(RDL-D)
tsu(D-RDL)
th(RDH-D)
ta(BA-D)
th(BA-D)
ta(LA-D)
Max.
0.55 tc
(WH + WL) tc-45
(WH + WL-0.5) tc-35
(WH + WL-0.5) tc-35
WL tc-30
WL tc-35
Min.
38
0.45 tc
0.5 tc – 6
0.5 tc – 6
6
6
15
0
8
(W
H
+ W
L
-0.5)tc-35 (Note)
External clock input cycle time
External clock input pulse width with half input-volage
External clock input high-level pulse width
External clock input low-level pulse width
External clock input rise time
External clock input fall time
Address access time (the address output select bit = 0)
Address access time (the address output select bit = 1)
Chip select access time
Read access time
Read data setup time
Data input hold time after read
Address access time at burst ROM access
Data hold time after address at burst ROM access
Address access time (the multiplexed bus select bit = 1)
1
φ
+1
φ
1
φ
+2
φ
1
φ
+3
φ
2
φ
+2
φ
Limits
External bus timing
For limits depending on f(fsys), their calculation formulas are shown below.
Symbol Parameter Unit
External clock input trtf
tw(L) tw(H) tw(half)
XIN
tc(in)
Test conditions
• Vcc = 3.3 V ± 0.3 V, Ta = –20 to 85 °C
• Input timing voltage : VIL = 0.66 V, VIH = 2.64 V (tw(H), tw(L), tr, tf)
• Output timing voltage : 1.65 V (tc(in), tw(half))
Bus cycle WHWL
1
1
1
2
1
2
3
2
Bus cycle WHWL
2
φ
+3
φ
2
φ
+4
φ
3
φ
+3
φ
3
φ
+4
φ
2
2
3
3
3
4
3
4
tc = 1/f(fsys).
Timing Requirements (VCC = 3.3 V±0.3 V, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 26 MHz, unless otherwise noted)
Note: This is independent of the value of the address output select bit’s contents.
7902 Group User’s Manual 21-139
APPENDIX
Appendix 10. M37902FGMHP electrical characteristics
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Bus cycle = 2φ + 2φ
Bus cycle = 3φ + 3φ, 3φ + 4φ
td(φ1-RDL)
td(φ1-RDH)
td(φ1-BXWL)
td(φ1-BXWH)
td(φ1L-CSiL)
td(φ1L-CSiH)
td(φ1H-A)
td(φ1L-A)
tw(ALEH)
td(A-ALEL)
tw(RDL)
tw(RDH)
td(RDH-BXWH)
td(A-RDH)
td(A-RDH)
th(RDH-A)
th(RDH-A)
td(RDH-ALEL)
td(ALEL-RDH)
td(CSiL-RDH)
td(CSiL-RDL)
th(RDH-CSiL)
td(RDH-D)
tw(BXWL)
tw(BXWH)
td(BXWH-RDH)
td(A-BXWH)
td(A-BXWH)
th(BXWH-A)
th(BXWH-A)
td(BXWH-ALEL)
td(ALEL-BXWH)
td(CSiL-BXWH)
td(CSiL-BXWL)
th(BXWH-CSiL)
td(D-BXWL)
th(BXWH-D)
tpxz(BXWH-DZ)
Parameter
Switching characteristics (VCC = 3.3 V±0.3 V, VSS = 0 V, Ta = –20 to 85 °C, f(fsys) = 26 MHz, unless otherwise noted)
Max.
0
0
0
0
0
10
25
16
20
20
0.5tc + 10
Min.
–18
–18
–18
–18
–20
–22
–5
–20
0.5tc-19
tc-20
1.5tc-20
tc-30
1.5tc-30
2tc-30
0.5tc-19
tc-20
1.5tc-20
WL tc-15
WH tc-15
tc-15
WH tc-30
(WH-0.5)tc-19
8
0.5tc-10
0.5tc-19
tc-15
(WH-0.5)tc-19
(W
H
+ W
L
-0.5)tc-20
0.5tc-14
tc-15
WL tc-15
WH tc-15
tc-15
WH tc-30
(WH-0.5)tc-19
8
0.5tc-10
0.5tc-19
tc-15
(WH-0.5)tc-19
(WH + WL-0.5)tc-20
0.5tc-14
WL tc-20
0.5tc-10
Read low-level output delay time
Read high-level output delay time
Write low-level output delay time
Write high-level output delay time
Chip select low-level output delay time
Chip select high-level output delay time
Address output delay time (the address output select bit = 0)
Address output delay time (the address output select bit = 1)
ALE pulse width
ALE completion delay time
after address stabilization
(when the address output
select bit = 0)
ALE completion delay time
after address stabilization
(when the address output
select bit = 1)
Read output pulse width
Read output high-level width (Note 1)
Write disable valid time after read (Note 2)
Address valid time before read (when the address output select bit = 0)
Address valid time before read (when the address output select bit = 1)
Address hold time after read (when the address output select bit = 0) (Note 2)
Address hold time after read (when the address output select bit = 1) (Note 2)
ALE completion delay time after read start
Read disable valid time
after ALE completion
Limits
Symbol Unit
Bus cycle = 1φ + 1φ, 1φ + 2φ, 1φ + 3φ
Bus cycle = 2φ + 2φ
Bus cycle = 2φ + 3φ, 2φ + 4φ, 3φ + 3φ, 3φ + 4φ
Bus cycle = 1φ + 1φ, 1φ + 2φ, 1φ + 3φ
Bus cycle = 2φ + 2φ
Bus cycle = 2φ + 3φ, 2φ + 4φ, 3φ + 3φ, 3φ + 4φ
Bus cycle = 2φ + 2φ
Bus cycle = 2φ + 3φ, 2φ + 4φ, 3φ + 3φ, 3φ + 4φ
Notes 1: When the bus cycle just before this parameter is for the area where the recovery cycle insertion is selected, this parameter is extended by tc (ns: one reco-
very cycle is inserted.) or by 2tc (ns: two recovery cycles are inserted.).
2: When accessing the area where the recovery cycle insertion is selected, this parameter is extended by tc (ns: one recovery cycle is inserted.) or by 2tc (ns:
two recovery cycles are inserted.).
3: This parameter is extended by tc (ns) when both of the following conditions are satisfied:
• When accessing the area where the recovery cycle insertion is selected.
• When two recovery cycles are inserted.
Bus cycle = 1φ + 1φ, 1φ + 2φ, 1φ + 3φ
Bus cycle = 2φ + 2φ
Bus cycle = 2φ + 3φ, 2φ + 4φ, 3φ + 3φ, 3φ + 4φ
Chip select valid time before read
Chip select output valid time before read completion
Chip select hold time after read
Next write cycle data output delay time after read (Note 2)
Write output pulse width
Write output high-level width (Note 1)
Read disable valid time after write (Note 2)
Address valid time before write (when the address output select bit = 0)
Address valid time before write (when the address output select bit = 1)
Address hold time after write (when the address output select bit = 0) (Note 2)
Address hold time after write (when the address output select bit = 1) (Note 2)
ALE completion delay time after write start
Write disable valid time
after ALE completion
Chip select valid time before write
Chip select output valid time before write completion
Chip select hold time after write
Data output valid time before write completion
Data hold time after write (Note 3)
Floating start delay time after write (Note 3)
APPENDIX
7902 Group User’s Manual
21-140
Appendix 10. M37902FGMHP electrical characteristics
ns
ns
ns
ns
ns
ns
ns
ns
td(LA-RDH)
td(LA-ALEL)
th(ALEL-LA)
tpxz(RDH-LAZ)
td(LA-BXWH)
tpzx(RDH-DZ)
Address valid time before read
ALE completion delay time
after address stabilization
Address hold time after
ALE completion
Floating start delay time
Address valid time before write
Floating release delay time
Bus cycle = 2φ + 2φ
Bus cycle = 3φ + 3φ, 3φ + 4φ
Bus cycle = 2φ + 2φ
Bus cycle = 3φ + 3φ, 3φ + 4φ
Switching characteristics (VCC = 3.3 V±0.3 V, VSS = 0 V, Ta = –20 to 85 °C, f(fsys) = 26 MHz, unless otherwise noted)
Parameter Max.
5
Min.
(WH-0.5)tc-19 (Note)
tc-20 (Note)
1.5tc-20 (Note)
0.5tc-19
tc-15
(WH-0.5)tc-19 (Note)
0.5tc-19 (Note)
Limits
Symbol Unit
Note: This is independent of the address output select bit’s contents.
7902 Group User’s Manual 21-141
APPENDIX
Appendix 10. M37902FGMHP electrical characteristics
Bus cycle
t
h(RDH-D)
t
h(RDH-A)
t
w(RDL)
t
a(CSiL-D)
t
a(RDL-D)
t
a(A-D)
t
d(CSiL-RDL)
t
su(D-RDL)
t
w(ALEH)
t
d(RDH-ALEL)
t
c
t
d(A-ALEL)
t
w(RDH)
t
d(RDH-D)
t
d(φ1-RDL)
t
h(RDH-A)
t
d(A-RDH)
t
d(CSiL-RDH)
t
a(A-D)
t
d(A-ALEL)
t
d(φ1H-A)
t
d(φ1L-A)
t
d(φ1L-CSiL)
t
d(φ1L-CSiH)
t
d(φ1-RDH)
t
h(RDH-CSiL)
t
d(RDH-BXWH)
t
d(A-RDH)
CS
i
RD
ALE
φ
1
f
sys
BLW
BHW
<At read>
Normal access: bus cycle = 1φ + 1φ, 1φ + 2φ, 1φ+ 3φ,
2φ + 3φ, or 2φ + 4φ
A
0
–A
23
(when the address output select bit = 0)
A
0
–A
23
(when the address output select bit = 1)
D
0
–D
7
, D
8
–D
15
Test conditions
• V
CC
= 3.3 V ±0.3 V, Ta = –20 to 85 °C
• Input timing voltage : V
IL
=0.53 V, V
IH
=1.65 V
• Output timing voltage: V
OL
=0.8 V, V
OH
=2.0 V, C
L
=15 pF (CS
i
)
• Output timing voltage: V
OL
=0.8 V, V
OH
=2.0 V, C
L
=50 pF (except for CS
i
)
APPENDIX
7902 Group User’s Manual
21-142
Appendix 10. M37902FGMHP electrical characteristics
th(BXWH-A)
td(CSiL-BXWL)
tw(BXWL)
td(BXWH-ALEL)
td(D-BXWL) th(BXWH-D)
tpxz(BXWH-DZ)
Bus cycle
td(φ1-BXWL)
th(BXWH-A)
td(A-BXWH)
td(CSiL-BXWH)
tc
td(A-ALEL)
tw(ALEH)
td(φ1H-A)
td(φ1L-CSiL) td(φ1L-CSiH)
td(BXWH-RDH)
td(φ1-BXWH)
th(BXWH-CSiL)
td(A-ALEL)
tw(BXWH)
td(A-BXWH)
td(φ1L-A)
CSi
RD
ALE
BLW
BHW
φ1
fsys
<At write>
Normal access: bus cycle = 1φ + 1φ, 1φ + 2φ, 1φ + 3φ,
2φ + 3φ, or 2φ + 4φ
A0–A23
(when the address output select bit = 0)
A0–A23
(when the address output select bit = 1)
D0–D7, D8–D15
Test conditions
• VCC = 3.3 V ±0.3 V, Ta = –20 to 85 °C
• Input timing voltage : VIL=0.53 V, VIH=1.65 V
• Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=15 pF (CSi)
• Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=50 pF (except for CSi)
7902 Group User’s Manual 21-143
APPENDIX
Appendix 10. M37902FGMHP electrical characteristics
t
d(A-RDH)
Bus cycle
t
d(CSiL-RDL)
t
d(A-ALEL)
t
h(RDH-D)
t
h(RDH-A)
t
w(RDL)
t
a(CSiL-D)
t
a(RDL-D)
t
a(A-D)
t
su(D-RDL)
t
w(ALEH)
t
c
t
w(RDH)
t
d(RDH-D)
t
d(ALEL-RDH)
t
d(φ1-RDL)
t
d(φ1-RDH)
t
h(RDH-D)
t
a(LA-D)
t
a(RDL-D)
t
d(LA-RDH)
t
su(D-RDL)
t
pzx(RDH-DZ)
t
d(LA-ALEL)
t
h(ALEL-LA)
t
pxz(RDH-LAZ)
t
h(RDH-A)
t
d(A-RDH)
t
d(CSiL-RDH)
t
a(A-D)
Address Input data Address
t
d(φ1H-A)
t
d(φ1L-CSiL)
t
d(φ1L-CSiH)
t
d(RDH-BXWH)
t
h(RDH-CSiL)
t
d(A-ALEL)
t
d(φ1L-A)
CS
i
RD
ALE
BLW
BHW
f
sys
φ1
Note: Valid only when area CS
2
is accessed with the external data bus width = 8 bits.
<At read>
Normal access: bus cycle = 2φ + 2φ, 3φ + 3φ, 3φ + 4φ
A
0
–A
23
(when the address output
select bit = 0)
D
0
–D
7
, D
8
–D
15
(when the multiplexed
bus select bit = 0)
LA
0
/D
0
–LA
7
/D
7
(when the multiplexed
bus select bit = 1, Note)
A
0
–A
23
(when the address output
select bit = 1)
Test conditions
• V
CC
= 3.3 V ±0.3 V, Ta = –20 to 85 °C
• Input timing voltage : V
IL
=0.53 V, V
IH
=1.65 V
• Output timing voltage: V
OL
=0.8 V, V
OH
=2.0 V, C
L
=15 pF (CS
i
)
• Output timing voltage: V
OL
=0.8 V, V
OH
=2.0 V, C
L
=50 pF (except for CS
i
)
APPENDIX
7902 Group User’s Manual
21-144
Appendix 10. M37902FGMHP electrical characteristics
t
d(CSiL-BXWL)
t
h(BXWH-A)
t
d(A-BXWH)
t
w(ALEH)
t
w(BXWL)
t
d(D-BXWL)
t
h(BXWH-D)
t
pxz(BXWH-DZ)
t
d(A-ALEL)
t
w(BXWH)
t
d(ALEL-BXWH)
Bus cycle
t
d(φ1-BXWL)
t
h(BXWH-D)
t
pxz(BXWH-DZ)
t
d(D-BXWL)
t
h(ALEL-LA)
t
d(LA-ALEL)
t
d(LA-BXWH)
t
c
t
h(BXWH-A)
t
d(A-BXWH)
t
d(CSiL-BXWH)
Address Output data
t
d(φ1-BXWH)
t
d(φ1H-A)
t
d(φ1L-CSiL)
t
d(φ1L-CSiH)
t
d(A-ALEL)
t
h(BXWH-CSiL)
t
d(BXWH-RDH)
t
d(φ1L-A)
CS
i
RD
ALE
BLW
BHW
f
sys
φ
1
Note: Valid only when area CS
2
is accessed with the external data bus width = 8 bits.
<At write>
Normal access: bus cycle = 2φ + 2φ, 3φ + 3φ, 3φ + 4φ
A
0
–A
23
(when the address output
select bit = 0)
D
0
–D
7
, D
8
–D
15
(when the multiplexed
bus select bit = 0)
LA
0
/D
0
–LA
7
/D
7
(when the multiplexed
bus select bit = 1, Note)
A
0
–A
23
(when the address output
select bit = 1)
Test conditions
• V
CC
= 3.3 V ±0.3 V, Ta = –20 to 85 °C
• Input timing voltage : V
IL
=0.53 V, V
IH
=1.65 V
• Output timing voltage: V
OL
=0.8 V, V
OH
=2.0 V, C
L
=15 pF (CS
i
)
• Output timing voltage: V
OL
=0.8 V, V
OH
=2.0 V, C
L
=50 pF (except for CS
i
)
7902 Group User’s Manual 21-145
APPENDIX
Appendix 10. M37902FGMHP electrical characteristics
t
h(BA-D)
t
d(RDH-BXWH)
BLW
BHW
RD
t
a(RDL-D)
t
d(A-RDH)
CS
i
t
h(RDH-A)
t
a(CSiL-D)
t
a(A-D)
t
a(BA-D)
t
h(BA-D)
t
h(BA-D)
t
h(RDH-D)
t
a(BA-D)
t
a(BA-D)
t
h(RDH-CSiL)
t
d(CSiL-RDH)
t
d(A-ALEL)
t
w(ALEH)
ALE
t
d(RDH-ALEL)
t
w(RDH)
t
d(A-RDH)
t
h(RDH-A)
t
a(A-D)
Burst ROM access: bus cycle = 1φ + 1φ, 1φ + 2φ, 1φ + 3φ, 2φ + 3φ, 2φ + 4φ
D
0
–D
7
, D
8
–D
15
Test conditions
• V
CC
= 3.3 V±0.3 V, Ta = –20 to 85°C
• Input timing voltage : V
IL
=0.53 V, V
IH
=1.65 V
• Output timing voltage: V
OL
=0.8 V, V
OH
=2.0 V, C
L
=15 pF (CS
i
)
• Output timing voltage: V
OL
=0.8 V, V
OH
=2.0 V, C
L
=50 pF (except for CS
i
)
A
0
–A
23
(when the address output select bit = 0)
A
0
–A
23
(when the address output select bit = 1)
t
d(A-ALEL)
APPENDIX
Appendix 11. Standard characteristics
7902 Group User’s Manual
21-146
Appendix 11. Standard characteristics
Standard characteristics described below are just examples of the M37902’s characteristics and are not
guaranteed. For each parameter’s limits, refer to sections “Appendix 9. M37902FGCGP electrical
characteristics” and “Appendix 10. M37902FGMHP electrical characteristics.”
1. Programmable I/O port (CMOS output) standard characteristics: P0–P2, P30, P4, P10, P11
(1) P-channel IOH–VOH characteristics
M37902FGCGP (Power source voltage: Vcc = 5 V)
M37902FGMHP (Power source voltage: Vcc = 3.3 V)
5.0
0V
OH
[V]
I
OH
[mA]
4.03.02.01.0
15.0
30.0 Ta = 25 °C
Ta = 85 °C
V
OH
[V]
I
OH
[mA]
3.3
10.0
20.0
Ta = 25 °C
Ta = 85 °C
02.641.981.320.66
V
OL
[V]
I
OL
[mA]
4.03.02.01.0
15.0
30.0
Ta = 25 °C
Ta = 85 °C
05.0
V
OL
[V]
I
OL
[mA]
3.3
10.0
20.0
Ta = 25 °C
Ta = 85 °C
02.641.981.320.66
(2) N-channel IOL–VOL characteristics
M37902FGCGP (Power source voltage: Vcc = 5 V)
M37902FGMHP (Power source voltage: Vcc = 3.3 V)
APPENDIX
7902 Group User’s Manual 21-147
Appendix 11. Standard characteristics
5.0
0V
OH
[V]
I
OH
[mA]
4.03.02.01.0
15.0
30.0
Ta = 25 °C
Ta = 85 °C
V
OH
[V]
I
OH
[mA]
3.3
10.0
20.0
Ta = 25 °C
Ta = 85 °C
02.641.981.320.66
V
OL
[V]
I
OL
[mA]
4.03.02.01.0
15.0
30.0
Ta = 25 °C
Ta = 85 °C
05.0
V
OL
[V]
I
OL
[mA]
3.3
10.0
20.0 Ta = 25 °C
Ta = 85 °C
02.641.981.320.66
2. Programmable I/O port (CMOS output) standard characteristics: P31–P33
(1) P-channel IOH–VOH characteristics
M37902FGCGP (Power source voltage: Vcc = 5 V)
M37902FGMHP (Power source voltage: Vcc = 3.3 V)
(2) N-channel IOL–VOL characteristics
M37902FGCGP (Power source voltage: Vcc = 5 V)
M37902FGMHP (Power source voltage: Vcc = 3.3 V)
APPENDIX
Appendix 11. Standard characteristics
7902 Group User’s Manual
21-148
V
OH
[V]
I
OH
[mA]
4.03.02.01.0
15.0
30.0
Ta = 25 °C
Ta = 85 °C
05.0
V
OH
[V]
I
OH
[mA]
3.3
10.0
20.0
Ta = 25 °C
Ta = 85 °C
02.641.981.320.66
V
OL
[V]
I
OL
[mA]
4.03.02.01.0
15.0
30.0
Ta = 25 °C
Ta = 85 °C
05.0
V
OL
[V]
I
OL
[mA]
3.3
10.0
20.0
Ta = 25 °C
Ta = 85 °C
02.641.981.320.66
3. Programmable I/O port (CMOS output) standard characteristics: P5–P8
(1) P-channel IOH–VOH characteristics
M37902FGCGP (Power source voltage: Vcc = 5 V)
M37902FGMHP (Power source voltage: Vcc = 3.3 V)
(2) N-channel IOL–VOL characteristics
M37902FGCGP (Power source voltage: Vcc = 5 V)
M37902FGMHP (Power source voltage: Vcc = 3.3 V)
APPENDIX
7902 Group User’s Manual 21-149
Appendix 11. Standard characteristics
Icc [mA]
f(X
IN
) [MHz] 2520151050
5.0
25.0
30
10.0
15.0
20.0
0.0
30.0
35.0
In operating
At Wait mode
Icc [mA]
f(XIN) [MHz] 2520151050
20.0
30
5.0
10.0
15.0
0.0
25.0
35.0
In operating
At Wait mode
30.0
4. Icc–f(XIN) standard characteristics
M37902FGCGP
M37902FGMHP
Measurement condition
•Vcc = 5.0 V
•Ta = 25 °C
•f(XIN) : square waveform input
•single-chip mode
•PLL frequency multiplier is
stopped.
•CPU and peripheral device
is operated.
•External clock input select
bit = “1”
Measurement condition
•Vcc = 3.3 V
•Ta = 25 °C
•f(XIN) : square waveform input
•single-chip mode
•PLL frequency multiplier is
stopped.
•CPU and peripheral device
is operated.
•External clock input select
bit = “1”
APPENDIX
Appendix 11. Standard characteristics
7902 Group User’s Manual
21-150
5. A-D converter standard characteristics
The lower lines of the graph indicate the absolute precision errors. These are expressed as the deviation
from the ideal value when the output code changes. For example, the change in M37902FGCGP’s output
code from 159 to 160 should occur at 797.5 mV, but the measured value is +1.3 mV. Accordingly, the
measured point of change is 797.5 + 1.3 = 798.8 mV.
The upper lines of the graph indicate the input voltage width for which the output code is constant. For
example, the measured input voltage width for which the output code is 56 is 6.2 mV, so that the differential
non-linear error is 6.2 – 5 = 1.2 mV (0.24 LSB).
APPENDIX
7902 Group User’s Manual 21-151
Appendix 11. Standard characteristics
M37902FGCGP
(Measurement conditions Vcc = 5.0 V, VREF = 5.12 V, f(fsys) = 26 MHz, Ta = 25 °C,
φ
AD = f(fsys) divided by 2)
7.5
ERROR (mV)
STEP No.
5.0
2.5
0.0
7.5
1LSB WIDTH (mV)
5.0
2.5
7.5
5.0
2.5
7.5
5.0
2.5
7.5
5.0
2.5
0.0
–2.5
–5.0
–7.5
7.5
ERROR (mV)
5.0
2.5
0.0
–2.5
–5.0
–7.5
7.5
ERROR (mV)
5.0
2.5
0.0
–2.5
–5.0
–7.5
7.5
ERROR (mV)
5.0
2.5
0.0
–2.5
–5.0
–7.5
0 16 32 48 64 80 96 112 128
STEP No.
144 160 176 192 208 224 240 256
1LSB WIDTH (mV)
0.0
256 272 288 304 320 336 352 368 384
STEP No. : ERROR (mV)
: 1LSB WIDTH (mV)
400 416 432 448 464 480 496 512
1LSB WIDTH (mV)
0.0
512 528 544 560 576 592 608 624 656 672 688 704 720 736 752 768
1LSB WIDTH (mV)
0.0
768 784 800 816 832 848 864 880 896
STEP No.
640
912 928 944 960 976 992 1008 1024
APPENDIX
Appendix 11. Standard characteristics
7902 Group User’s Manual
21-152
M37902FGMHP
(Measurement conditions Vcc = 3.3 V, VREF = 3.3 V, f(fsys) = 26 MHz, Ta = 25 °C,
φ
AD = f(fsys) divided by 2)
4.8
ERROR (mV)
STEP No.
3.2
1.6
0.0
4.8
1LSB WIDTH (mV)
3.2
1.6
0.0
–1.6
–3.2
–4.8 0 16 32 48 64 80 96 112 128
STEP No.
144 160 176 192 208 224 240 256
4.8
ERROR (mV)
3.2
1.6
0.0
4.8
1LSB WIDTH (mV)
3.2
1.6
0.0
–1.6
–3.2
–4.8256 272 288 304 320 336 352 368 384
STEP No.
640
STEP No. : ERROR (mV)
: 1LSB WIDTH (mV)
400 416 432 448 464 480 496 512
4.8
ERROR (mV)
3.2
1.6
0.0
4.8
1LSB WIDTH (mV)
3.2
1.6
0.0
–1.6
–3.2
–4.8512 528 544 560 576 592 608 624 656 672 688 704 720 736 752 768
4.8
ERROR (mV)
3.2
1.6
0.0
4.8
1LSB WIDTH (mV)
3.2
1.6
0.0
–1.6
–3.2
–4.8768 784 800 816 832 848 864 880 896 912 928 944 960 976 992 1008 1024
APPENDIX
7902 Group User’s Manual 21-153
Appendix 12. Memory assignment of 7902 Group
Appendix 12. Memory assignment of 7902 Group
1. M37902FJCGP/HP, M37902FJMHP
Fig. 13 Memory assigment of M37902FJCGP/HP, M37902FJMHP
Microprocessor mode
SFR area
Internal
RAM area
(12 Kbytes)
Single-chip mode
Internal
RAM area
(12 Kbytes)
(Note 1)
SFR area
Memory expansion mode
FEFFFF
16
FFFFFF
16
Internal
RAM area
(12 Kbytes)
SFR area
Internal flash
memory area
(User ROM area)
(498 Kbytes)
(Note 2)
: This is an external area. The access to this area enables the access to an
externally-connected device.
Unused area
FF
16
Notes 1: When the internal RAM area is followed by an external area, do not assign a
program to the last 8 bytes of the internal RAM area.
2: Do not assign a program to the last 8 bytes of the internal ROM area.
3: Do not access this area.
Reserved area
(Note 3)
FF0000
16
100
16
7FF
16
800
16
7FFFF
16
Internal flash
memory area
(User ROM area)
(498 Kbytes)
(Note 2)
80000
16
37FF
16
3800
16
Reserved area
(Note 3)
0
16
APPENDIX
Appendix 12. Memory assignment of 7902 Group
7902 Group User’s Manual
21-154
Fig. 14 Memory assigment of M37902FHCGP/HP, M37902FHMHP
2. M37902FHCGP/HP, M37902FHMHP
0
16
SFR area
Internal
RAM area
(12 Kbytes)
Internal
RAM area
(12 Kbytes)
(Note 1)
SFR area
FEFFFF
16
FFFFFF
16
Internal
RAM area
(12 Kbytes)
SFR area
Internal flash
memory area
(User ROM area)
(370 Kbytes)
(Note 2)
Unused area
FF
16
FF0000
16
100
16
7FF
16
800
16
5FFFF
16
Internal flash
memory area
(User ROM area)
(370 Kbytes)
(Note 2)
60000
16
37FF
16
3800
16
Microprocessor modeSingle-chip mode Memory expansion mode
Reserved area
(Note 3)
Reserved area
(Note 3)
: This is an external area. The access to this area enables the access to an
externally-connected device.
Notes 1: When the internal RAM area is followed by an external area, do not assign a
program to the last 8 bytes of the internal RAM area.
2: Do not assign a program to the last 8 bytes of the internal ROM area.
3: Do not access this area.
APPENDIX
7902 Group User’s Manual 21-155
Appendix 12. Memory assignment of 7902 Group
Fig. 15 Memory assigment of M37902FGCGP/HP, M37902FGMHP
3. M37902FGCGP/HP, M37902FGMHP
0
16
SFR area
Internal
RAM area
(6 Kbytes)
Internal RAM area
(6 Kbytes)
(Note 1)
SFR area
FEFFFF
16
FFFFFF
16
Internal
RAM area
(6 Kbytes)
SFR area
Internal flash
memory area
(User ROM area)
(248 Kbytes)
(Note 2)
Unused area
FF
16
FF0000
16
100
16
7FF
16
800
16
1FFF
16
2000
16
3FFFF
16
Internal flash
memory area
(User ROM area)
(248 Kbytes)
(Note 2)
40000
16
Microprocessor modeSingle-chip mode Memory expansion mode
Reserved area
(Note 3)
Reserved area
(Note 3)
: This is an external area. The access to this area enables the access to an
externally-connected device.
Notes 1: When the internal RAM area is followed by an external area, do not assign a
program to the last 8 bytes of the internal RAM area.
2: Do not assign a program to the last 8 bytes of the internal ROM area.
3: Do not access this area.
APPENDIX
Appendix 12. Memory assignment of 7902 Group
7902 Group User’s Manual
21-156
Fig. 16 Memory assigment of M37902FECGP/HP, M37902FEMHP
4. M37902FECGP/HP, M37902FEMHP
016 SFR area
Internal
RAM area
(6 Kbytes)
Internal RAM area
(6 Kbytes)
(Note 1)
SFR area
FEFFFF16
FFFFFF16
Internal
RAM area
(6 Kbytes)
SFR area
Internal flash
memory area
(User ROM area)
(184 Kbytes)
(Note 2)
Unused area
FF16
FF000016
10016
7FF16
80016
1FFF16
200016
2FFFF16
Internal flash
memory area
(User ROM area)
(184 Kbytes)
(Note 2)
3000016
Microprocessor modeSingle-chip mode Memory expansion mode
Reserved area
(Note 3)
Reserved area
(Note 3)
: This is an external area. The access to this area enables the access to an
externally-connected device.
Notes 1: When the internal RAM area is followed by an external area, do not assign a
program to the last 8 bytes of the internal RAM area.
2: Do not assign a program to the last 8 bytes of the internal ROM area.
3: Do not access this area.
APPENDIX
7902 Group User’s Manual 21-157
Appendix 12. Memory assignment of 7902 Group
Fig. 17 Memory assigment of M37902FCCGP/HP, M37902FCMHP
5. M37902FCCGP/HP, M37902FCMHP
0
16
SFR area
Internal RAM area
(4 Kbytes)(Note 1) Internal RAM area
(4 Kbytes)(Note 1)
SFR area
FEFFFF
16
FFFFFF
16
Internal RAM area
(4 Kbytes)(Note 1)
SFR area
Internal flash
memory area
(User ROM area)
(120 Kbytes)
(Note 2)
Unused area
FF
16
FF0000
16
100
16
7FF
16
800
16
17FF
16
1800
16
1FFFF
16
Internal flash
memory area
(User ROM area)
(120 Kbytes)
(Note 2)
20000
16
Unused area
1FFF
16
2000
16
Microprocessor modeSingle-chip mode Memory expansion mode
Reserved area
(Note 3)
Reserved area
(Note 3)
: This is an external area. The access to this area enables the access to an
externally-connected device.
Notes 1: When the internal RAM area is followed by an unused area or an external area,
do not assign a program to the last 8 bytes of the internal RAM area.
2: Do not assign a program to the last 8 bytes of the internal ROM area.
3: Do not access this area.
APPENDIX
Appendix 12. Memory assignment of 7902 Group
7902 Group User’s Manual
21-158
Fig. 18 Memory assigment of M37902F8CGP/HP, M37902F8MHP
6. M37902F8CGP/HP, M37902F8MHP
0
16
SFR area
Internal RAM area
(2 Kbytes) Internal RAM area
(2 Kbytes)(Note 1)
SFR area
FEFFFF
16
FFFFFF
16
Internal RAM area
(2 Kbytes)
SFR area
Internal flash
memory area
(User ROM area)
(60 Kbytes)
(Note 2)
Unused area
FF
16
FF0000
16
100
16
7FF
16
800
16
FFF
16
1000
16
FFFF
16
Internal flash
memory area
(User ROM area)
(60 Kbytes)
(Note 2)
10000
16
Microprocessor mode
Single-chip mode Memory expansion mode
Reserved area
(Note 3)
Reserved area
(Note 3)
: This is an external area. The access to this area enables the access to an
externally-connected device.
Notes 1: When the internal RAM area is followed by an external area, do not assign a
program to the last 8 bytes of the internal RAM area.
2: Do not assign a program to the last 8 bytes of the internal ROM area.
3: Do not access this area.
MITSUBISHI SEMICONDUCTORS
USER’S MANUAL
7902 Group
Rev. 2.0, Dec., 1999
Editioned by
Committee of editing of Mitsubishi Semiconductor USER’S MANUAL
Published by
Mitsubishi Electric Corp., Semiconductor Marketing Division
This book, or parts thereof, may not be reproduced in any form without permission
of Mitsubishi Electric Corporation.
©1999 MITSUBISHI ELECTRIC CORPORATION
MITSUBISHI ELECTRIC CORPORATION
HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN
User’s Manual
7902 Group
© 1999 MITSUBISHI ELECTRIC CORPORATION. New publication, effective sep. 1999.
Specifications subject to change without notice.