7-1317
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
CD40105BMS
CMOS FIFO Register
Description
CD40105BMS is a low-power first-in-first-out (FIFO) “elastic”
storage register that can store 16 4-bit words. It is capable of
handling input and output data at different shifting rates. This
feature makes it particularly useful as a buffer between asyn-
chronous systems.
Each word position in the register is clocked by a control flip-
flop, which stores a marker bit. A “1” signifies that the posi-
tion’s data is filled and a “0” denotes a vacancy in that posi-
tion. The control flip-flop detects the state of the preceding
flip-flop and communicates its own status to the succeeding
flip-flop. When a control flip-flop is in the “0” state and sees a
“1” in the preceding flip-flop, it generates a clock pulse that
transfers data from the preceding four data latches into its
own four data latches and resets the preceding flip-flop to
“0”. The first and last control flip-flops have buffered outputs.
Since all empty locations “bubble” automatically to the input
end, and all valid data ripple through to the output end, the
status of the first control flip-flop (DATA-IN READY) indicates
if the FIFO is full, and the status of the last flip-flop (DATA-
OUT READY) indicates if the FIFO contains data. As the
earliest data are removed from the bottom of the data stack
(the output end), all data entered later will automatically
propagate (ripple) toward the output.
Loading Data - Data can be entered whenever the DATA-IN
READY (DIR) flag is high, by a low to high transition on the
SHIFT-IN (SI) input. This input must go low momentarily
before the next word is accepted by the FIFO. The DIR flag
will go low momentarily, until that data have been transferred
to the second location. The flag will remain low when all 16-
word locations are filled with valid data, and further pulses
on the SI input will be ignored until DIR goes high.
Features
• 4 Bits x 16 Words
• High Voltage Type (20V Rating)
• Independent Asynchronous Inputs and Outputs
• 3-State Outputs
• Expandable in Either Direction
• Status Indicators on Input and Output
• Reset Capability
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
• Bit Rate Smoothing
• CPU/Terminal Buffering
• Data Communications
• Peripheral Buffering
• Line Printer Input Buffers
• Auto Dialers
• CRT Buffer Memories
• Radar Data Acquisition
December 1992
File Number 3353
Continued on next page
Pinout CD40105BMS
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
3 - STATE
DIR
SI
D0
D1
D2
VSS
D3
VDD
DOR
Q0
Q1
Q2
Q3
MR
SO
CONTROL
Functional Diagram
13
12
11
10
14
2
Q0
Q1
Q2
Q3
DATA-OUT
READY
DATA-IN
READY
4
5
6
7
3
15
D0
D1
D2
D3
SHIFT IN
SHIFT OUT
1
9
3-STATE
CONTROL
MASTER
RESET VDD = 16
VSS = 8
7-1318
CD40105BMS
Unloading Data - As soon as the first word has rippled to
the output, DATA-OUT READY (DOR) goes high, and data
can be removed by a falling edge on the SO input. This fall-
ing edge causes the DOR signal to go low while the word on
the output is dumped and the next word moves to the output.
As long as valid data are available in the FIFO, the DOR sig-
nal will go high again signifying that the next word is ready at
the output. When the FIFO is empty, DOR will remain low,
and any further commands will be ignored until a “1” marker
ripples down to the last control register, when DOR goes
high. Unloading of data is inhibited while the 3-state control
input is high. The 3-state control signal should not be shifted
from high to low (data outputs turned on) while the SHIFT-
OUT is at logic 0. This level change would cause the first
word to be shifted out (unloaded) immediately and the data
to be lost.
Cascading - The CD40105BMS can be cascaded to form
longer registers simply by connecting the DIR to SO and
DOR to SI. In the cascaded mode, a MASTER RESET pulse
must be applied after the supply voltage is turned on. For
words wider than 4 bits, the DIR and the DOR outputs must
be gated together with AND gates. Their outputs drive the SI
and SO inputs in parallel, if expanding is done in both direc-
tions (see Figures 9 and 11).
3-State Outputs - In order to facilitate data busing, 3-state
outputs are provided on the data output lines, while the load
condition of the register can be detected by the state of the
DOR output.
Master Reset - A high on the MASTER RESET (MR) sets all
the control logic marker bits to “0”. DOR goes low and DIR
goes high. The contents of the data register are not
changed, only declared invalid, and will be superseded when
the first word is loaded. The shift-in must be low during Mas-
ter Reset.
The CD40105BMS is supplied in these 16-lead outline pack-
ages:
Braze Seal DIP H4X
Frit Seal DIP H1F
Ceramic Flatpack H6W
Logic Diagram
CL
CL
2 15 1
9
3
4
5
6
7
R
SQ
R
SQ
Q
1
R
SQ
Q
2
POSITIONS
4 - 15 R
SQ
Q
16
R
SQ
CL 4
LATCHES
CL CL 4
LATCHES
CL CL 4
LATCHES
CL CL 4
LATCHES
CL 3
STATE
OUTPUT
BUFFERS
13
12
11
10
*
*
*
*
*
*
*ALL INPUTS PROTECTED BY
COS/MOS PROTECTION
NETWORK
POS 1 POS 2 POS 3 POS 16
MASTER
RESET
SHIFT
IN
D0
D1
D2
D3
DATA IN READY
(DIR) SHIFT
OUT 3 - STATE
CONTROL
(OUTPUT
ENABLE)
DATA
READY
(DOR)
Q0
Q1
Q2
Q3
**
VDD
VSS
p
nCL
CL
p
n
DETAIL OF LATCHES
14
7-1319
Specifications CD40105BMS
Absolute Maximum Ratings Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG). . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Thermal Resistance . . . . . . . . . . . . . . . . θja θjc
Ceramic DIP and FRIT Package. . . . . 80oC/W 20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W
Maximum Package Power Dissipation (PD) at +125oC
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K). . . . . .Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS (NOTE 1) GROUP A
SUBGROUPS TEMPERATURE
LIMITS
UNITSMIN MAX
Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC-10µA
2 +125oC - 1000 µA
VDD = 18V, VIN = VDD or GND 3 -55oC-10µA
Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25oC -100 - nA
2 +125oC -1000 - nA
VDD = 18V 3 -55oC -100 - nA
Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA
2 +125oC - 1000 nA
VDD = 18V 3 -55oC - 100 nA
Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV
Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V
Functional
(Note 4) F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH >
VDD/2 VOL <
VDD/2 V
VDD = 20V, VIN = VDD or GND 7 +25oC
VDD = 18V, VIN = VDD or GND 8A +125oC
VDD = 3V, VIN = VDD or GND 8B -55oC
Input Voltage Low
(Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V
Input Voltage High
(Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V
Input V oltage Low (Note
2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC- 4 V
Input Voltage High
(Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC11 - V
Tri-State Output
Leakage IOZL VIN = VDD or GND
VOUT = 0V VDD = 20V 1 +25oC -0.4 - µA
2 +125oC -12 - µA
VDD = 18V 3 -55oC -0.4 - µA
7-1320
Specifications CD40105BMS
Tri-State Output
Leakage IOZH VIN = VDD or GND
VOUT = VDD VDD = 20V 1 +25oC - 0.4 µA
2 +125oC-12µA
VDD = 18V 3 -55oC - 0.4 µA
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs.
3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.
4. VDD = 2.8V/3.0V, RL = 100K to VDD
VDD = 20V/18V, RL = 10K to VDD
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS (NOTE 1) GROUP A
SUBGROUPS TEMPERATURE
LIMITS
UNITSMIN MAX
Propagation Delay
Shift Out or Reset to
Data-Out Ready
TPHL1 VDD = 5V, VIN = VDD or GND
(Note 1, 2) 9 +25oC - 370 ns
10, 11 +125oC, -55oC - 500 ns
Propagation Delay
Shift In to Data-In Ready TPHL2 VDD = 5V, VIN = VDD or GND
(Note 1, 2) 9 +25oC - 320 ns
10, 11 +125oC, -55oC - 432 ns
Propagation Delay
Ripple through Delay In-
put to Output
TPLH3 VDD = 5V, VIN = VDD or GND
(Note 1, 2) 9 +25oC-4µs
10, 11 +125oC, -55oC - 5.4 µs
Propagation Delay
3-State Control to Data
Out
TPZH VDD = 5V, VIN = VDD or GND
(Note 2, 3) 9 +25oC - 280 ns
10, 11 +125oC, -55oC - 378 ns
Transition Time TTHL
TTLH VDD = 5V, VIN = VDD or GND
(Note 1, 2) 9 +25oC - 200 ns
10, 11 +125oC, -55oC - 270 ns
Maximum Shift-In or
Shift-Out Rate FCL VDD = 5V (Note 1, 2),
VIN = VDD or GND 9 +25oC 1.5 - MHz
10, 11 +125oC, -55oC 1.11 - MHz
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
3. CL = 50pF, RL = 1K, Input TR, TF < 20ns.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
LIMITS
UNITSMIN MAX
Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC- 5 µA
+125oC - 150 µA
VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC- 10µA
+125oC - 300 µA
VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC- 10µA
+125oC - 600 µA
Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC,
-55oC-50mV
Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC,
-55oC-50mV
Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC,
-55oC4.95 - V
Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC,
-55oC9.95 - V
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS (NOTE 1) GROUP A
SUBGROUPS TEMPERATURE
LIMITS
UNITSMIN MAX
7-1321
Specifications CD40105BMS
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA
-55oC 0.64 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA
-55oC 1.6 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA
-55oC 4.2 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA
-55oC - -0.64 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA
-55oC - -2.0 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA
-55oC - -1.6 mA
Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA
-55oC - -4.2 mA
Input Voltage Low VIL VDD = 10V, VOH > 9V , VOL < 1V 1, 2 +25oC, +125oC,
-55oC-3V
Input Voltage High VIH VDD = 10V , VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC,
-55oC7-V
Propagation Delay
Shift or Reset to Data Out
Ready
TPHL1 VDD = 10V 1, 2, 3 +25oC - 180 ns
VDD = 15V 1, 2, 3 +25oC - 130 ns
Propagation Delay Ripple
through Delay Input to
Output
TPLH3 VDD = 10V 1, 2, 3 +25oC-2µs
VDD = 15V 1, 2, 3 +25oC - 1.4 µs
Propagation Delay
Shift-In to Data-In Ready TPHL2 VDD = 10V 1, 2, 3 +25oC - 130 ns
VDD = 15V 1, 2, 3 +25oC - 90 ns
Propagation Delay
Shift Out to QN Out TPHL4
TPLH4 VDD = 5V 1, 2, 3 +25oC - 420 ns
VDD = 10V 1, 2, 3 +25oC - 380 ns
VDD = 15V 1, 2, 3 +25oC - 250 ns
Propagation Delay
3-State Control to Data
Out
TPZH
TPZL VDD = 10V 1, 2, 4 +25oC - 120 ns
VDD = 15V 1, 2, 4 +25oC - 80 ns
Propagation Delay
3-State Control to Data
Out
TTHZ
TPLZ VDD = 10V 1, 2, 3 +25oC - 100 ns
VDD = 15V 1, 2, 3 +25oC - 80 ns
Maximum Shift-In or
Shift-Out Rate FCL VDD = 10V 1, 2 +25oC 3 - MHz
VDD = 15V 1, 2 +25oC 4 - MHz
Maximum Shift-In or
Shift-Out Rise Time TR VDD = 5V 3 +25oC-15µs
VDD = 10V 3 +25oC-15µs
VDD = 15V 3 +25oC-15µs
Maximum Shift-In Fall
Time TF VDD = 5V 3 +25oC-15µs
VDD = 10V 3 +25oC-15µs
VDD = 15V 3 +25oC-15µs
Maximum Shift-Out Fall
Time TF VDD = 5V 3 +25oC-15µs
VDD = 10V 3 +25oC-5µs
VDD = 15V 3 +25oC-5µs
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
LIMITS
UNITSMIN MAX
7-1322
Specifications CD40105BMS
Minimum Master Reset
Pulse Width TWH VDD = 5V 1, 2, 3 +25oC - 200 ns
VDD = 10V 1, 2, 3 +25oC - 90 ns
VDD = 15V 1, 2, 3 +25oC - 60 ns
Data-In Ready Pulse
Width TWL VDD = 5V 1, 2, 3 +25oC - 520 ns
VDD = 10V 1, 2, 3 +25oC - 200 ns
VDD = 15V 1, 2, 3 +25oC - 140 ns
Data-Out Ready Pulse
Width TWL VDD = 5V 1, 2, 3 +25oC - 440 ns
VDD = 10V 1, 2, 3 +25oC - 180 ns
VDD = 15V 1, 2, 3 +25oC - 130 ns
Minimum Shift Out Pulse
Width TWL VDD = 5V 1, 2, 3 +25oC - 180 ns
VDD = 10V 1, 2, 3 +25oC - 75 ns
VDD = 15V 1, 2, 3 +25oC - 55 ns
Minimum Data Setup
Time TSU VDD = 5V 1, 2, 3 +25oC-0ns
VDD = 10V 1, 2, 3 +25oC-0ns
VDD = 15V 1, 2, 3 +25oC-0ns
Minimum Data Hold Time TH VDD = 5V 1, 2, 3 +25oC - 350 ns
VDD = 10V 1, 2, 3 +25oC - 150 ns
VDD = 15V 1, 2, 3 +25oC - 120 ns
Minimum Shift In Pulse
Width TW VDD = 5V 1, 2, 3 +25oC - 200 ns
VDD = 10V 1, 2, 3 +25oC - 80 ns
VDD = 15V 1, 2, 3 +25oC - 60 ns
Input Capacitance CIN Any Input 1, 2 +25oC - 7.5 pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. CL = 50pF, RL = 1K, Input TR, TF < 20ns.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
LIMITS
UNITSMIN MAX
Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC-25µA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V
N Threshold V oltage Delta ∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC-±1V
P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V
P Threshold V oltage Delta ∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC-±1V
Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH >
VDD/2 VOL <
VDD/2 V
VDD = 3V, VIN = VDD or GND
Propagation Delay Time TPHL
TPLH VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x
+25oC
Limit
ns
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 3. See Table 2 for +25oC limit.
4. Read and Record
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
LIMITS
UNITSMIN MAX
7-1323
Specifications CD40105BMS
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC
PARAMETER SYMBOL DELTA LIMIT
Supply Current - MSI-2 IDD ± 1.0µA
Output Current (Sink) IOL5 ± 20% x Pre-Test Reading
Output Current (Source) IOH5A ± 20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP MIL-STD-883
METHOD GROUP A SUBGROUPS READ AND RECORD
Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Final Test 100% 5004 2, 3, 8A, 8B, 10, 11
Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11
Subgroup B-6 Sample 5005 1, 7, 9
Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUPS MIL-STD-883
METHOD
TEST READ AND RECORD
PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD
Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
FUNCTION OPEN GROUND VDD 9V ± -0.5V
OSCILLATOR
50kHz 25kHz
Static Burn-In 1 Note 1 2, 10 - 14 1, 3 - 9, 15 16
Static Burn-In 2 Note 1 2, 10 - 14 8 1, 3 - 7, 9, 15, 16
Dynamic Burn-In Note 1 - 1, 8, 9 16 2, 10 - 14 3, 15 4 - 7
Irradiation Note 2 2, 10 - 14 8 1, 3 - 7, 9, 15, 16
NOTES:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ±5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V ± 0.5V
7-1324
CD40105BMS
Typical Performance Characteristics
FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
FIGURE 6. TYPICAL TRANSITION TIME AS A FUNCTION OF
LOAD CAPACITANCE FIGURE 7. TYPICAL DYNAMIC POWER DISSIPATION AS A
FUNCTION OF FREQUENCY
10V
5V
AMBIENT TEMPERATURE (T A) = +25oC
GATE-TO-SOURCE VOLT AGE (VGS) = 15V
0 5 10 15
15
10
5
20
25
30
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
10V
5V
AMBIENT TEMPERATURE (T A) = +25oC
GATE-TO-SOURCE VOLT AGE (VGS) = 15V
0 5 10 15
7.5
5.0
2.5
10.0
12.5
15.0
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
-10V
-15V
AMBIENT TEMPERATURE (T A) = +25oC
GATE-TO-SOURCE VOLT AGE (VGS) = -5V
0
-5
-10
-15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-20
-25
-30
0-5-10-15
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
-10V
-15V
AMBIENT TEMPERATURE (T A) = +25oC0
-5
-10
-15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) 0-5-10-15
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
GATE-TO-SOURCE VOLT AGE (VGS) = -5V
AMBIENT TEMPERATURE (T A) = +25oC
LOAD CAPACITANCE (CL) (pF)
0 40 60 80 10020
0
50
100
150
200
SUPPLY VOLT AGE (VDD) = 5V
10V
15V
TRANSITION TIME (tTHL, tTLH) (ns)
10V
5V
10V
8642
INPUT FREQUENCY (fIN) (kHz)
11010
2103104
8
6
4
2
8
6
4
2
8
6
4
2
8
6
4
2
105
104
102
106
POWER DISSIPATION PER GATE (PD) (µW)
AMBIENT TEMPERATURE (TA) = +25oC
SUPPLY VOLTAGE (VDD) = 15V
(ALL Q OUTPUTS LOADED)
103
8642864286428642
CL = 15pF
CL = 50pF
7-1325
CD40105BMS
FIGURE 8. CD40105BMS FUNCTIONAL BLOCK DIAGRAM FIGURE 9. EXPANSION, 4-BITS WIDE-BY-16 N-BITS LONG
FIGURE 10. TIMING DIAGRAM FOR THE CD40105BMS
CONTROL LOGIC
4 x 16
DATA
REGISTER
13
12
11
10
1
14
15
9
4
5
6
7
2
3
INPUT
BUFFERS OUTPUT
BUFFERS
Q0
Q1
Q2
Q3
3-STATE
CONTROL
D0
D1
D2
D3
DATA-IN
READY (DIR)
SHIFT IN (SI) MASTER
RESET (MR)
DATA-OUT
READY (DOR)
SHIFT OUT (SO)
D0
D1
D2
D3
Q0
Q1
Q2
Q3
SI DOR
DIR MR SO
D0
D1
D2
D3
Q0
Q1
Q2
Q3
SI DOR
DIR MR SO
10 11 1 11 1 1 100 0 0 0 0
MASTER
RESET
SHIFT IN
(DATA VALID)
SHIFT OUT
INPUT READY
(CLEAR OUT)
OUTPUT READY
(CLEAR OUT)
DATA IN (Dn)
3-STATE
(OUTPUT
ENABLE)
DATA OUT*** (UNKNOWN)
SHIFT-OUT PULSES
HAVE NO EFFECT
≈ 2µs*
SHIFT-IN PULSES
HAVE NO EFFECT
≈ 2µs**
HIGH
Z
INVALID
10
111 0
*AT VDD =5V - RIPPLE TIME FROM POSITION 1 TO POSITION 16
**AT VDD = 5V - RIPPLE TIME FROM POSITION 16 TO POSITION 1
***DATA VALID goes to high level in advance of the DATA OUT
and 20ns at VDD = 15V for CL = 50pF and TA = 25oC
by maximum of 50ns at VDD = 5V, 25ns at VDD = 10V,
INPUTS
OUTPUTS
INPUTS
1326
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
CD40105BMS
Chip Dimensions and Pad Layout
FIGURE 11. EXPANSION, 8-BITS-WIDE-BY-16 N-BITS LONG USING CD40105BMS
SI
D0
D1
D2
D3
Q0
Q1
Q2
Q3
DIR
MRSO
DOR SI
D0
D1
D2
D3
Q0
Q1
Q2
Q3
DIR
MRSO
DOR
SI
D0
D1
D2
D3
Q0
Q1
Q2
Q3
DIR
MRSO
DORSI
D0
D1
D2
D3
Q0
Q1
Q2
Q3
DIR
MRSO
DOR
SHIFT
IN
DATA OUT
READY
8 BIT
DATA 8 BIT
DATA
SHIFT
OUT
DATA IN
READY
*MASTER
RESET *Pulse must be applied for cascading by 16 N bits.
Dimensions in parenthesis are in millimeters and are derived from the basic
inch dimensions as indicated. Grid graduations are in mils (10-3 inch).
METALLIZATION: Thickness: 11kÅ−14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
