Arria II GX Device Handbook Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com AIIGX5V1-1.1 Copyright (c) 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Contents Chapter Revision Dates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi Section I. Device Core Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-1 Chapter 1. Arria II GX Device Family Overview Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Highlights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Arria II GX Device Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 High-Speed Transceiver Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 PCI Express (PIPE) hard IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Logic Array Block and Adaptive Logic Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Embedded Memory Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 DSP Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 I/O Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 High-Speed LVDS I/O with DPA and Soft CDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 Auto-Calibrating External Memory Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 Nios II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 Configuration Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 SEU Mitigation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 JTAG Boundary Scan Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 Reference and Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 Chapter 2. Logic Array Blocks and Adaptive Logic Modules in Arria II GX Devices Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Logic Array Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 LAB Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 LAB Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Adaptive Logic Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 ALM Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Extended LUT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Arithmetic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Shared Arithmetic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 LUT-Register Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Register Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 ALM Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 Clear and Preset Logic Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 Chapter 3. Memory Blocks in Arria II GX Devices Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 1 iv Contents Memory Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Memory Block Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Parity Bit Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Byte Enable Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Packed Mode Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Address Clock Enable Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Mixed Width Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Asynchronous Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Memory Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Single-Port RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Simple Dual-Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 True Dual-Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Shift-Register Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 ROM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 FIFO Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 Clocking Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 Independent Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 Input and Output Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 Read and Write Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 Single Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 Memory Block Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 Conflict Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 Read-During-Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 Same-Port Read-During-Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 Mixed-Port Read-During-Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 Power-Up Conditions and Memory Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 Chapter 4. DSP Blocks in Arria II GX Devices Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 DSP Block Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Simplified DSP Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Operational Modes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 DSP Block Resource Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Input Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 Multiplier and First-Stage Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 Pipeline Register Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 Second-Stage Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 Round and Saturation Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 Second Adder and Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 Arria II GX Device Handbook Volume 1 (c) March 2009 Altera Corporation Contents v Operational Mode Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Independent Multiplier Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-, 12-, and 18-Bit Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-Bit Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Double Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Two-Multiplier Adder Sum Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 x 18 Complex Multiply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Four-Multiplier Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Precision Multiplier Adder Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiply Accumulate Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shift Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rounding and Saturation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Block Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Support for Arria II GX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 4-13 4-13 4-17 4-18 4-20 4-21 4-22 4-23 4-25 4-26 4-28 4-30 4-31 4-32 Chapter 5. Clock Networks and PLLs in Arria II GX Devices Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Clock Networks in Arria II GX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Global Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Regional Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Periphery Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 Clocking Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 Clock Network Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 Dedicated Clock Inputs Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 Logic Array Blocks (LABs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 PLL Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 Clock Input Connections to PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 Clock Output Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 Clock Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 Clock Enable Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 Clock Source Control for PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 Cascading PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 1 vi Contents PLLs in Arria II GX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arria II GX PLL Hardware Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Clock I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pfdena . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . areset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . locked . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Feedback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Source Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Source-Synchronous Mode for LVDS Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . No-Compensation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Zero-Delay Buffer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Multiplication and Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Post-Scale Counter Cascading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Phase-Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Spread-Spectrum Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Automatic Clock Switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Manual Clock Switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Reconfiguration Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Post-Scale Counters (C0 to C6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scan Chain Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Charge Pump and Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bypassing PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dynamic Phase-Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 5-15 5-15 5-16 5-17 5-17 5-17 5-17 5-18 5-19 5-19 5-20 5-21 5-21 5-22 5-23 5-23 5-24 5-25 5-25 5-26 5-28 5-29 5-30 5-30 5-32 5-33 5-34 5-35 5-36 5-38 5-38 Section II. I/O Interfaces Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-1 Chapter 6. I/O Features in Arria II GX Devices Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Arria II GX I/O Standards Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 Arria II GX I/O Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 Modular I/O Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 Arria II GX I/O Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 3.3-V I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 External Memory Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 High-Speed Differential I/O with DPA Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 Programmable Current Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 Programmable Slew Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 Open-Drain Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 Bus Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 Programmable Pull-Up Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 Programmable Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 Programmable Differential Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 MultiVolt I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 Arria II GX Device Handbook Volume 1 (c) March 2009 Altera Corporation Contents vii Arria II GX OCT Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Series (RS ) Termination without Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Series Termination with Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LVDS Input On-Chip Termination (RD ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arria II GX OCT Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCT Calibration Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arria II GX Termination Schemes for I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single-Ended I/O Standards Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential I/O Standards Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential LVPECL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RSDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mini-LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arria II GX Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single-Ended I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Bank Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-Voltage-Referenced Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage-Referenced Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mixing Voltage-Referenced and Non-Voltage-Referenced Standards . . . . . . . . . . . . . . . . . . . . . I/O Placement Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3-V, 3.0-V, and 2.5-V LVTTL/LVCMOS Tolerance Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Placement Guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 6-11 6-12 6-13 6-14 6-14 6-14 6-14 6-16 6-17 6-18 6-19 6-20 6-21 6-21 6-21 6-21 6-22 6-22 6-22 6-22 6-22 6-22 6-23 6-23 Chapter 7. External Memory Interfaces in Arria II GX Devices Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 Arria II GX Memory Interfaces Pin Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 Arria II GX External Memory Interface Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15 DQS Phase-Shift Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15 DLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17 Phase Offset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20 DQS Logic Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21 DQS Delay Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22 Update Enable Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23 DQS Postamble Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23 I/O Element Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26 Chapter 8. High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LVDS Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LVDS SERDES and DPA Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (c) March 2009 Altera Corporation 8-1 8-2 8-5 8-6 8-6 Arria II GX Device Handbook Volume 1 viii Contents Differential Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 Dynamic Phase Alignment (DPA) Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 Synchronizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 Data Realignment Block (Bit Slip) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 Deserializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 Receiver Data Path Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 Non-DPA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 DPA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13 Soft-CDR Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14 Programmable Pre-Emphasis and Programmable VOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 Differential I/O Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17 PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17 LVDS and DPA Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17 Source-Synchronous Timing Budget . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 Differential Data Orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19 Differential I/O Bit Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19 Receiver Skew Margin for Non-DPA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20 Differential Pin Placement Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21 DPA-Enabled Channels and Single-Ended I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22 Guidelines for DPA-Enabled Differential Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22 DPA-Enabled Channel Driving Distance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22 Using Center and Corner PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22 Using Both Center PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23 Using Both Corner PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25 Guidelines for DPA-Disabled Differential Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27 DPA-Disabled Channel Driving Distance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27 Using Corner and Center PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27 Using Both Center PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29 Using Both Corner PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-31 Setting Up an LVDS Transmitter or Receiver Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-31 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-31 Section III. System Integration Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-1 Chapter 9. Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Reset Circuit and Configuration Pins Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCCIO Pins for I/O Banks 3C and 8C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCCPD Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSEL Pin Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Raw Binary File Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arria II GX Device Handbook Volume 1 9-1 9-2 9-2 9-3 9-3 9-3 9-4 9-4 9-4 9-4 9-5 9-5 9-5 9-6 9-6 9-6 9-7 (c) March 2009 Altera Corporation Contents ix Fast Passive Parallel Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 FPP Configuration Using an External Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 FPP Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 Active Serial Configuration (Serial Configuration Devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 Estimating Active Serial Configuration Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19 Programming Serial Configuration Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20 Passive Serial Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-22 PS Configuration Using an External Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-22 PS Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25 PS Configuration Using a Download Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26 JTAG Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-28 Jam STAPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-34 Device Configuration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-34 Configuration Data Decompression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-40 Remote System Upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-42 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-43 Enabling Remote Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-44 Configuration Image Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-45 Remote System Upgrade Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-46 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-46 Remote Update Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-46 Dedicated Remote System Upgrade Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-48 Remote System Upgrade Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-49 Remote System Upgrade Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-50 Remote System Upgrade Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-51 Remote System Upgrade State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-52 User Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-52 Quartus II Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-53 ALTREMOTE_UPDATE Megafunction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-54 Design Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-54 Arria II GX Security Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-55 Security Against Copying . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-55 Security Against Reverse Engineering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-55 Security Against Tampering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-55 AES Decryption Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-56 Flexible Security Key Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-56 Arria II GX Design Security Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-57 Security Modes Available . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-58 Volatile Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-58 Non-Volatile Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-58 Volatile Key with Tamper Protection Bit Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-58 Non-Volatile Key with Tamper Protection Bit Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-58 Volatile or Non-Volatile Key with JTAG Anti-Tamper Protection Bit Set . . . . . . . . . . . . . . . . . . 9-58 No Key Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-59 Supported Configuration Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-59 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-61 Chapter 10. SEU Mitigation in Arria II GX Devices Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Detection Fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User Mode Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Automated Single Event Upset Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (c) March 2009 Altera Corporation 10-1 10-1 10-2 10-2 10-4 Arria II GX Device Handbook Volume 1 x Contents Error Detection Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 CRC_ERROR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 Error Detection Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 Error Detection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 Error Detection Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 Recovering From CRC Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 Chapter 11. JTAG Boundary-Scan Testing Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IEEE Std. 1149.6 Boundary-Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BST Operation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EXTEST_PULSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EXTEST_TRAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Voltage Support in a JTAG Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary-Scan Description Language Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11-1 11-3 11-4 11-4 11-5 11-6 11-6 Chapter 12. Power Requirements for Arria II GX Devices Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Power Supply Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Reset Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hot Socketing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Devices Can Be Driven before Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Pins Remain Tri-Stated During Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Insertion or Removal of an Arria II GX Device from a Powered-Up System . . . . . . . . . . . . . . . . . . Hot Socketing Feature Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12-1 12-2 12-2 12-3 12-3 12-3 12-3 12-4 Additional Information About this Handbook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info-1 How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info-1 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info-1 Arria II GX Device Handbook Volume 1 (c) March 2009 Altera Corporation Chapter Revision Dates The chapters in this book, Arria II GX Device Handbook Volume 1, were revised on the following dates. Where chapters or groups of chapters are available separately, part numbers are listed. Chapter 1 Arria II GX Device Family Overview Revised: February 2009 Part Number: AIIGX51001-1.0 Chapter 2 Logic Array Blocks and Adaptive Logic Modules in Arria II GX Devices Revised: February 2009 Part Number: AIIGX51002-1.0 Chapter 3 Memory Blocks in Arria II GX Devices Revised: February 2009 Part Number: AIIGX51003-1.0 Chapter 4 DSP Blocks in Arria II GX Devices Revised: February 2009 Part Number: AIIGX51004-1.0 Chapter 5 Clock Networks and PLLs in Arria II GX Devices Revised: February 2009 Part Number: AIIGX51005-1.0 Chapter 6 I/O Features in Arria II GX Devices Revised: February 2009 Part Number: AIIGX51006-1.0 Chapter 7 External Memory Interfaces in Arria II GX Devices Revised: March 2009 Part Number: AIIGX51007-1.1 Chapter 8 High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices Revised: February 2009 Part Number: AIIGX51008-1.0 Chapter 9 Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Revised: February 2009 Part Number: AIIGX51009-1.0 Chapter 10 SEU Mitigation in Arria II GX Devices Revised: February 2009 Part Number: AIIGX51010-1.0 Chapter 11 JTAG Boundary-Scan Testing Revised: February 2009 Part Number: AIIGX51011-1.0 (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 1 xii Chapter Revision Dates Chapter 12 Power Requirements for Arria II GX Devices Revised: February 2009 Part Number: AIIGX51012-1.0 Arria II GX Device Handbook Volume 1 (c) March 2009 Altera Corporation Section I. Device Core This section provides a complete overview of all features relating to the Arria (R) II GX device family, the industry's first cost-optimized 40 nm FPGA family. This section includes the following chapters: Chapter 1, Arria II GX Device Family Overview Chapter 2, Logic Array Blocks and Adaptive Logic Modules in Arria II GX Devices Chapter 3, Memory Blocks in Arria II GX Devices Chapter 4, DSP Blocks in Arria II GX Devices Chapter 5, Clock Networks and PLLs in Arria II GX Devices Revision History Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in this volume. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 I-2 Arria II GX Device Handbook Volume 1 Section I: Device Core (c) February 2009 Altera Corporation 1. Arria II GX Device Family Overview AIIGX51001-1.0 Introduction The Arria (R) II GX device family is designed specifically for ease-of-use. The cost-optimized, 40-nm device family architecture features a low-power, programmable logic engine, and streamlined transceivers and I/Os. Common interfaces, such as the PCI Express (PIPE), Ethernet, and DDR-2 memory is easily implemented in your design with the Quartus(R) II software, SOPC Builder design software, Altera's broad library of hard-IP and soft-IP solutions. The Arria II GX device family makes designing for applications requiring transceivers operating at up to 3.75 Gbps fast and easy. This chapter contains the following sections: "Highlights" on page 1-1 "Arria II GX Device Architecture" on page 1-4 "Reference and Ordering Information" on page 1-11 Highlights The Arria II GX device features consist of the following highlights: (c) February 2009 40 nm, low-power FPGA engine Adaptive logic module (ALM) offers the highest logic efficiency in the industry Eight-input fracturable look-up table (LUT) Memory logic array blocks (MLABs) for efficient implementation of small FIFOs High-performance digital signal processing (DSP) blocks up to 350 MHz Configurable as 9 x 9-bit, 12 x 12-bit, 18 x 18-bit, and 36 x 36-bit full precision multipliers Hardcoded adders, subtractors, accumulators, and summation functions Fully integrated design flow with MatLab and Altera's DSP Builder software Maximum system bandwidth Up to 16 full-duplex clock data recovery (CDR)-based transceivers supporting rates between 155 Mbps and 3.75 Gbps Dedicated circuitry to support physical layer functionality for popular serial protocols, including PCI Express (PIPE) Gen 1, Gigabit Ethernet, Serial RapidIO, Common Public Radio Interface (CPRI), Open Base Station Architecture Initiative (OBSAI), SD/HD/3G SDI, XAUI, HiGig/HiGig+, and SONET/SDH Complete PCI Express (PIPE) protocol solution with an embedded hard IP block that provides PHY-MAC layer, Data Link layer, and Transaction layer functionality Altera Corporation Arria II GX Device Handbook Volume 1 1-2 Chapter 1: Arria II GX Device Family Overview Highlights Optimized for high-bandwidth system interfaces Up to 612 user I/O pins arranged in up to 12 modular I/O banks that support a wide range of single-ended and differential I/O standards High-speed LVDS I/O support with serializer/deserializer (SERDES) and dynamic phase alignment (DPA) circuitry at data rates from 150 Mbps to 1 Gbps Low power Patented architectural power reduction techniques Per-channel transceiver power consumption is approximately 100 mW under typical conditions at 3.125 Gbps Power optimizations integrated into the Quartus II development software Advanced usability and security features Parallel and serial configuration options On-chip series and differential I/O termination 256-bit advanced encryption standard (AES) programming file encryption for design security with volatile and non-volatile key storage options Robust portfolio of IP for processing, serial protocols, and memory interfaces Low cost, easy-to-use development kits featuring high-speed mezzanine connectors (HSMC) Table 1-1 shows Arria II GX device features. Table 1-1. Arria II GX Device Features (Part 1 of 2) Feature EP2AGX20 EP2AGX30 EP2AGX45 EP2AGX65 ALMs 6,380 10,800 18,050 25,300 37,470 49,640 76,120 102,600 LEs 15,950 27,000 45,125 63,250 93,675 124,100 190,300 256,500 PCI Express hard IP Blocks 1 1 1 1 1 1 1 1 M9K Blocks 87 144 319 495 612 730 840 950 Total Embedded Memory in M9K Blocks (Kbits) 783 1296 2871 4455 5508 6570 7560 8550 Total On-Chip Memory (M9K + MLABs) (Kbits) 982 1,634 3,435 5,246 6,679 8,121 9,939 11,756 Embedded Multipliers (18 x 18) 56 128 232 312 448 576 656 736 General Purpose PLLs 4 4 4 4 6 6 6 6 Transceiver Tx PLLs (2) 2 2 2 or 4 (1) 2 or 4 (1) 4 or 6 (1) 4 or 6 (1) 6 or 8 (1) 6 or 8 (1) Arria II GX Device Handbook Volume 1 EP2AGX95 EP2AGX125 EP2AGX190 EP2AGX260 (c) February 2009 Altera Corporation Chapter 1: Arria II GX Device Family Overview Highlights 1-3 Table 1-1. Arria II GX Device Features (Part 2 of 2) Feature User I/O Banks EP2AGX20 EP2AGX30 EP2AGX45 EP2AGX65 6 6 6 6 EP2AGX95 EP2AGX125 EP2AGX190 EP2AGX260 8 8 12 12 Notes to Table 1-1: (1) The number of PLLs depends on package. Transceiver Tx PLL count = (number of transceiver blocks) x 2. (2) The FPGA fabric can use these PLLs if they are not being used by the transceiver. Table 1-2 lists Arria II GX device package options and user I/O pin counts, high-speed LVDS channel counts, and transceiver channel counts for micro BGA and FineLine BGA devices. Table 1-2. Arria II GX Device Package Options and I/O Information (Note 1), (2) 358-Pin Flip Chip UBGA 17 mm x 17 mm 572-Pin Flip Chip FBGA 25 mm x 25 mm 780-Pin Flip Chip FBGA 29 mm x 29 mm Device I/O LVDS (3) XCVRs I/O LVDS (3) XCVRs I/O EP2AGX20 156 33Rx + 32Tx 4 252 57Rx + 56Tx 4 -- -- -- -- -- -- EP2AGX30 156 33Rx + 32Tx 4 252 57Rx + 56Tx 4 -- -- -- -- -- -- EP2AGX45 156 33Rx + 32Tx 4 252 57Rx + 56Tx 8 364 85Rx + 84Tx 8 -- -- -- EP2AGX65 156 33Rx + 32Tx 4 252 57Rx + 56Tx 8 364 85Rx + 84Tx 8 -- -- -- EP2AGX95 -- -- -- 260 57Rx + 56Tx 8 372 85Rx + 84Tx 12 452 105Rx + 104Tx 12 EP2AGX125 -- -- -- 260 57Rx + 56Tx 8 372 85Rx + 84Tx 12 452 105Rx + 104Tx 12 EP2AGX190 -- -- -- -- -- -- 372 85Rx + 84Tx 12 612 145Rx + 144Tx 16 EP2AGX260 -- -- -- -- -- -- 372 85Rx + 84Tx 12 612 145Rx + 144Tx 16 LVDS (3) XCVRs 1152-Pin Flip Chip FBGA 35 mm x 35 mm I/O LVDS (3) XCVRs Notes to Table 1-2: (1) The user I/O counts include clock pins. (2) The arrows indicate packages vertical migration capability. Vertical migration allows you to migrate to devices whose dedicated pins, configuration pins, and power pins are the same for a given package across device densities. (3) Rx denotes LVDS input with OCT RD support or pseudo LVDS output. Tx denotes LVDS I/O without OCT RD support or pseudo LVDS output. Arria II GX devices are available in up to three speed grades: -4 (fastest), -5, and -6 (slowest). Table 1-3 shows Arria II GX devices speed grades. Table 1-3. Arria II GX FPGA Devices Speed Grades (Part 1 of 2) Device 358-Pin Flip Chip UBGA 572-Pin Flip Chip FBGA 780-Pin Flip Chip FBGA 1152-Pin Flip Chip FBGA EP2AGX20 C4, C5, C6, I5 C4, C5, C6, I5 -- -- EP2AGX30 C4, C5, C6, I5 C4, C5, C6, I5 -- -- EP2AGX45 C4, C5, C6, I5 C4, C5, C6, I5 C4, C5, C6, I5 -- EP2AGX65 C4, C5, C6, I5 C4, C5, C6, I5 C4, C5, C6, I5 -- (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 1-4 Chapter 1: Arria II GX Device Family Overview Arria II GX Device Architecture Table 1-3. Arria II GX FPGA Devices Speed Grades (Part 2 of 2) Device 358-Pin Flip Chip UBGA 572-Pin Flip Chip FBGA 780-Pin Flip Chip FBGA 1152-Pin Flip Chip FBGA EP2AGX95 -- C4, C5, C6, I5 C4, C5, C6, I5 C4, C5, C6, I5 EP2AGX125 -- C4, C5, C6, I5 C4, C5, C6, I5 C4, C5, C6, I5 EP2AGX190 -- -- C4, C5, C6, I5 C4, C5, C6, I5 EP2AGX260 -- -- C4, C5, C6, I5 C4, C5, C6, I5 Arria II GX Device Architecture Arria II GX FPGAs include a customer-defined feature set optimized for cost-sensitive applications and offer a wide range of density, memory, embedded multiplier, I/O, and packaging options. Arria II GX FPGAs support external memory interfaces and I/O protocols required by wireless, wireline, broadcast, computer, storage, and military markets. They inherit the 8-input advanced logic module, M9K embedded RAM block, and high-performance DSP blocks from the Stratix(R) IV device family with a cost-optimized I/O cell and a transceiver optimized for 3.75 Gbps speeds. Figure 1-1 shows an overview of the Arria II GX device architecture. Figure 1-1. Arria II GX Device Architecture Overview DLL PLL High-Speed Differential I/O, General Purpose I/O, and Memory Interface High-Speed Differential I/O, General Purpose I/O, and Memory Interface High-Speed Differential I/O with DPA, General Purpose I/O, and Memory Interface FPGA Fabric (Logic Elements, DSP, Embedded Memory, Clock Networks) Transceiver Blocks All the blocks in this graphic are for the largest density in the Arria II GX family. The number of blocks can vary based on the density of the device. Arria II GX Device Handbook Volume 1 PLL PLL High-Speed Differential I/O with DPA, General Purpose I/O, and Memory Interface Plug and Play PCIe hard IP x1, x4, and x8 PLL PLL High-Speed Differential I/O, General Purpose I/O, and Memory Interface High-Speed Differential I/O, General Purpose I/O, and Memory Interface PLL DLL (c) February 2009 Altera Corporation Chapter 1: Arria II GX Device Family Overview Arria II GX Device Architecture 1-5 High-Speed Transceiver Features Arria II GX devices integrate up to 16 transceivers on a single device. The transceiver block is optimized for cost and power consumption. Arria II GX transceivers support the following features: Configurable pre-emphasis and equalization, and adjustable output differential voltage Flexible and easy-to-configure transceiver data path to implement proprietary protocols Signal Integrity Features (c) February 2009 Programmable transmitter pre-emphasis to compensate for inter-symbol interference (ISI) User-controlled five-stage receiver equalization with up to 7 dB of high-frequency gain On-die power supply regulators for transmitter and receiver PLL charge pump and voltage-controlled oscillator (VCO) for superior noise immunity Calibration circuitry for transmitter and receiver on-chip termination (OCT) resistors Diagnostic Features Serial loopback from the transmitter serializer to the receiver CDR for transceiver PCS and PMA diagnostics Parallel loopback from the transmitter PCS to the receiver PCS with built-in self test (BIST) pattern generator and verifier Reverse serial loopback pre- and post-CDR to transmitter buffer for physical link diagnostics Loopback master and slave capability in PCI Express hard IP blocks Support for protocol features such as MSB-to-LSB transmission in SONET/SDH configuration and spread-spectrum clocking in PCI Express (PIPE) configuration Altera Corporation Arria II GX Device Handbook Volume 1 1-6 Chapter 1: Arria II GX Device Family Overview Arria II GX Device Architecture Table 1-4 shows some common protocols and the Arria II GX dedicated circuitry and features for implementing these protocols. Table 1-4. Sample of supported Protocols and Feature Descriptions Supported Protocols Feature Descriptions PCI Express (PIPE) Complete PCI Express (PIPE) Gen1 protocol stack solution compliant to PCI Express Base Specification 1.1 that includes PHY-MAC, Data Link, and Transaction layer circuitry embedded in PCI Express hard IP blocks x1, x4, and x8 lane configurations Built-in circuitry for electrical idle generation and detection, receiver detect, power state transitions, lane reversal, and polarity inversion 8B/10B encoder and decoder, receiver synchronization state machine, and 300 parts per million (ppm) clock compensation circuitry Options to use: XAUI/HiGig/HiGig+ GIGE CPRI/OBSAI 1 Hard IP Data Link Layer and Transaction Layer Hard IP Data Link Layer and custom Soft IP Transaction Layer Compliant to IEEE P802.3ae specification Embedded state machine circuitry to convert XGMII idle code groups (||I||) to and from idle ordered sets (||A||, ||K||, ||R||) at the transmitter and receiver, respectively 8B/10B encoder and decoder, receiver synchronization state machine, lane deskew, and 100 ppm clock compensation circuitry Compliant to IEEE 802.3 specification Automatic idle ordered set (/I1/, /I2/) generation at the transmitter, depending on the current running disparity 8B/10B encoder and decoder, receiver synchronization state machine, and 100 ppm clock compensation circuitry Reverse bit slipper eliminates latency uncertainty to comply with CPRI/OBSAI specifications Optimized for power and cost for remote radio heads and RF modules For other protocols supported by Arria II GX devices, such as SONET/SDH, SDI and Serial RapidIO, refer to the Arria II GX Transceiver Architecture chapter in volume 2 of the Arria II GX Device Handbook. The following sections provide an overview of the various features of the Arria II GX FPGA. PCI Express (PIPE) hard IP Every Arria II GX device includes an integrated hard IP block which implements PCI Express (PIPE) PHY-MAC, data link, and transaction layers. This PCI Express hard IP block is highly configurable to meet the requirements of the majority of PCI Express applications. PCI Express (PIPE) hard IP makes implementing a PCI Express (PIPE) Gen 1 solution in your Arria II GX design simple and easy. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 1: Arria II GX Device Family Overview Arria II GX Device Architecture 1-7 PCI Express hard IP is instantiated using the PCI Compiler MegaWizardTM Plug-In Manager, similar to soft IP functions, but does not consume core FPGA resources or require placement, routing, and timing analysis to insure correct operation of the core. The Arria II GX hard IP for PCI Express (PIPE) includes support for: x1, x4, and x8 lane configurations Root port and endpoint configurations 512 byte payload Compliant to PCI Express (PIPE) 1.1 at 2.5 Gbps Logic Array Block and Adaptive Logic Modules Logic array blocks (LABs) consists of 10 adaptive logic modules (ALMs), carry chains, shared arithmetic chains, LAB control signals, local interconnect, and register chain connection lines ALMs expand the traditional four-input LUT architecture to eight-inputs, increasing performance by reducing LEs, logic levels, and associated routing LABs have a derivative called memory LAB (MLAB), that adds SRAM-memory capability to the LAB MLAB and LAB blocks always coexist as pairs, allowing up to 50% of the logic (LABs) to be traded for memory (MLABs) Embedded Memory Blocks M9K embedded memory blocks provide up to 8,550 Kbits of on-chip memory capable of up to 390-MHz performance. The embedded memory structure consists of columns of M9K memory blocks that you can configure as RAM, FIFO buffers, and ROM Optimized for applications such as high-throughput packet processing, high-definition (HD) line buffers for video processing functions, and embedded processor program and data storage Quartus II software allows you to take advantage of M9K memory blocks by instantiating memory using a dedicated megafunction wizard or by inferring memory directly from VHDL or Verilog source code Table 1-5 shows Arria II GX device memory modes. Table 1-5. Arria II GX Memory Modes (c) February 2009 Port Mode Port Width Configuration Single Port x1, x2, x4, x8, x9, x16, x18, x32, and x36 Simple Dual Port x1, x2, x4, x8, x9, x16, x18, x32, and x36 True Dual Port x1, x2, x4, x8, x9, x16, and x18 Altera Corporation Arria II GX Device Handbook Volume 1 1-8 Chapter 1: Arria II GX Device Family Overview Arria II GX Device Architecture DSP Resources Fulfills the digital signal processing requirements of 3G and LTE wireless infrastructure applications, video processing applications, and voice processing applications DSP block input registers efficiently implement shift registers for finite impulse response (FIR) filter applications Quartus II software includes megafunctions that are used to control the mode of operation of the DSP blocks based on user-parameter settings Multipliers can also be inferred directly from VHDL or Verilog HDL source code Contains up to 12 modular I/O banks All I/O banks support a wide range of single-ended and differential I/O standards, as listed in Table 1-6 I/O Features Table 1-6. Arria II GX FPGA I/O Standards Support Type I/O Standard Single-Ended I/O LVTTL, LVCMOS, SSTL, HSTL, PCI, and PCI-X Differential I/O SSTL, HSTL, LVPECL, LVDS, mini-LVDS, and RSDS Supports programmable bus hold, programmable weak pull-up resistors, and programmable slew rate control Calibrates OCT or driver impedance matching for single-ended I/O standards with one OCT calibration block on the top-left, top-right, and bottom-left corners of the device Dedicated configuration banks at Bank 3C and 8C which support dedicated configuration pins and dual-function pins with a configuration scheme at 1.8, 2.5, 3.0, and 3.3 V Dedicated VREF pin per I/O bank to allow voltage-referenced I/O standards. Each I/O bank can operate at independent V CCIO and VREF levels High-Speed LVDS I/O with DPA and Soft CDR Dedicated circuitry for implementing LVDS interfaces at speeds from 150 Mbps to 1 Gbps On-chip differential termination for high-speed LVDS interfacing DPA circuitry and soft-CDR circuitry at the receiver automatically compensates for channel-to-channel and channel-to-clock skew in source-synchronous interfaces and allows for implementation of asynchronous serial interfaces with embedded clocks at data rates from 150 Mbps to 1 Gbps Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 1: Arria II GX Device Family Overview Arria II GX Device Architecture 1-9 Clock Management Provides dedicated global clock networks (GCLKs), regional clock networks (RCLKs), and periphery clock networks (PCLKs) that are organized into a hierarchical structure that provides up to 148 unique clock domains Up to six PLLs with seven outputs per PLL to provide robust clock management and synthesis Independently programmable PLL outputs, creating a unique and customizable clock frequency with no fixed relation to any other clock Inherent jitter filtration and fine granularity control over multiply and divide ratios Supports spread-spectrum input clocking and counter cascading with PLL input clock frequencies ranging from 5 to 500 MHz to support both low-cost and high-end clock performance Unused transceiver PLLs can be used by the FPGA fabric to provide more flexibility Auto-Calibrating External Memory Interfaces I/O structure enhanced to provide flexible and cost-effective support for different types of memory interfaces Contains features such as on-chip termination and DQS/DQ pin groupings to enable rapid and robust implementation of different memory standards An auto-calibrating megafunction is available in the Quartus II software for DDR SDRAM, DDR2 SDRAM, and DDR3 SDRAM memory interface PHYs; the megafunction takes advantage of the PLL dynamic reconfiguration feature to calibrate based on the changes of process, voltage, and temperature Table 1-7 lists preliminary external memory support. Memory maximum performance is pending device characterization. Table 1-7. Arria II GX Device External Memory Interface Maximum Performance (c) February 2009 Memory Type Maximum Performance DDR SDRAM 200 MHz DDR2 SDRAM 300 MHz DDR3 SDRAM 300 MHz QDRII SRAM 250 MHz 1 Arria II GX devices feature I/O capable of electrical support for QDRII SRAM, but Altera does not currently supply a controller or PHY megafunction for QDRII SRAM interfaces. f For more information regarding the external memory interfaces support, refer to the External Memory Interfaces in Arria II GX Devices chapter in volume 1 in the Arria II GX Device Handbook. Altera Corporation Arria II GX Device Handbook Volume 1 1-10 Chapter 1: Arria II GX Device Family Overview Arria II GX Device Architecture Nios II Arria II GX devices support all variants of the NIOS II processor Nios II processors are supported by an array of software tools from Altera and leading embedded partners and are used by more designers than any other configurable processor Configuration Features Configuration Meets the 200 ms wake-up time requirement for PCI Express (PIPE) Design Security Supports programming file encryption using 256-bit volatile and non-volatile security keys to protect designs from copying, reverse engineering, and tampering in fast passive parallel (FPP) configuration mode with an external host (such as a MAX(R) II device or microprocessor), or when using fast active serial (AS) or passive serial (PS) configuration scheme Decrypts an encrypted configuration bitstream using the AES algorithm, an industry standard encryption algorithm that is FIPS-197 certified and requires a 256-bit security key Remote System Upgrade Allows error-free deployment of system upgrades from a remote location securely and reliably without an external controller Soft logic (either the Nios II embedded processor or user logic) implementation in the device helps download a new configuration image from a remote location, store it in configuration memory, and direct the dedicated remote system upgrade circuitry to start a reconfiguration cycle Dedicated circuitry in the remote system upgrade helps to avoid system down time by performing error detection during and after the configuration process, and recover from an error condition by reverting back to a safe configuration image, and provides error status information SEU Mitigation Offers built-in error detection circuitry to detect data corruption due to soft errors in the configuration random access memory (CRAM) cells Allows all CRAM contents to be read and verified to match a configuration-computed cyclical redundancy check (CRC) value The bit location and the type of soft error can be identified and read-out through the Joint Test Action Group (JTAG) or the core interface Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 1: Arria II GX Device Family Overview Reference and Ordering Information 1-11 JTAG Boundary Scan Testing Supports JTAG IEEE Std. 1149.1 and IEEE Std. 1149.6 specifications IEEE Std. 1149.6 supports high-speed serial interface (HSSI) transceivers and performs boundary scan on alternating current (AC)-coupled transceiver channels Boundary-scan test (BST) architecture offers the capability to test pin connections without using physical test probes and capture functional data while a device is operating normally Reference and Ordering Information Figure 1-2 describes the ordering codes for Arria II GX devices. Figure 1-2. Arria II GX Device Packaging Ordering Information EP2AGX 30 C F 17 C 4 Family Signature N Optional Suffix EP2AGX Indicates specific device shipment method ES: Engineering sample N: Lead-free devices Device Density Speed Grade 20, 30, 45, 65, 95 125, 190, 260 4, 5, or 6, with 4 being the fastest Transceiver Count Operating Temperature C: 4 D: 8 E: 12 F:16 Package Type F: FineLine BGA (FBGA) U: Micro BGA (UFBGA) C: Commercial temperature (tJ = 0C to 85C) I: Industrial temperature (tJ = -40C to 100C) Ball Array Dimension Corresponds to pin count 17 = 358 pins 25 = 572 pins 29 = 780 pins 35 = 1152 pins Document Revision History Table 1-8 shows the revision history for this document. Table 1-8. Document Revision History Date and Document Version February 2009, v1.0 (c) February 2009 Changes Made Initial Release. Altera Corporation Summary of Changes -- Arria II GX Device Handbook Volume 1 1-12 Arria II GX Device Handbook Volume 1 Chapter 1: Arria II GX Device Family Overview Document Revision History (c) February 2009 Altera Corporation 2. Logic Array Blocks and Adaptive Logic Modules in Arria II GX Devices AIIGX51002-1.0 Introduction This chapter describes the features of the logic array block (LAB) in the Arria(R) II GX core fabric. The logic array block is composed of basic building blocks known as adaptive logic modules (ALMs) that you can configure to implement logic functions, arithmetic functions, and register functions. This chapter contains the following sections: "Logic Array Blocks" on page 2-1 "Adaptive Logic Modules" on page 2-4 Logic Array Blocks Figure 2-1 shows the Arria II GX LAB structure and the LAB interconnects. Figure 2-1. Arria II GX LAB Structure C4 C12 Row Interconnects of Variable Speed & Length R20 R4 ALMs Direct link interconnect from adjacent block Direct link interconnect from adjacent block Direct link interconnect to adjacent block Direct link interconnect to adjacent block Local Interconnect (c) February 2009 Altera Corporation LAB MLAB Column Interconnects of Local Interconnect is Driven Variable Speed & Length from Either Side by Column Interconnect & LABs, & from Above by Row Interconnect Arria II GX Device Handbook Volume 1 2-2 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II GX Devices Logic Array Blocks Half of the available LABs in Arria II GX devices can be used as a memory LAB (MLAB). The MLAB supports a maximum of 640 bits of simple dual-port static random access memory (SRAM). You can configure each ALM in an MLAB as either a 64 x 1 or 32 x 2 block, resulting in a configuration of 64 x 10 or 32 x 20 simple dual-port SRAM blocks. MLAB and LAB blocks always coexist as pairs in all Arria II GX device families. MLAB is a superset of the LAB and includes all LAB features. Figure 2-2 shows an overview of LAB and MLAB topology. f MLAB is described in detail in the Memory Blocks in Arria II GX Devices chapter in volume 1 of the Arria II GX Device Handbook. Figure 2-2. Arria II GX LAB and MLAB Structure (1) LUT-based-64 x 1 Simple dual port SRAM ALM LUT-based-64 x 1 (1) Simple dual port SRAM ALM LUT-based-64 x 1 (1) Simple dual port SRAM ALM LUT-based-64 x 1 (1) Simple dual port SRAM ALM LUT-based-64 x 1 (1) Simple dual port SRAM ALM LAB Control Block LAB Control Block (1) LUT-based-64 x 1 Simple dual port SRAM ALM LUT-based-64 x 1 (1) Simple dual port SRAM ALM LUT-based-64 x 1 (1) Simple dual port SRAM ALM (1) LUT-based-64 x 1 Simple dual port SRAM ALM LUT-based-64 x 1 Simple dual port SRAM ALM MLAB (1) LAB Note to Figure 2-2: (1) You can use an MLAB ALM as a regular LAB ALM or configure it as a dual-port SRAM, as shown. LAB Interconnects The LAB local interconnect is used to drive ALMs in the same LAB. Each LAB can drive 30 ALMs through fast local and direct link interconnects. Ten ALMs are in any given LAB and ten ALMs are in each of the adjacent LABs. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II GX Devices Logic Array Blocks 2-3 Figure 2-3 shows the direct link connection, which connects adjacent LABs, memory blocks, DSP blocks, or I/O element (IOE) outputs. Figure 2-3. Direct Link Connection Direct link interconnect from left LAB, memory block, DSP block, or IOE output Direct link interconnect from right LAB, memory block, DSP block, or IOE output ALMs ALMs Direct link interconnect to right Direct link interconnect to left Local Interconnect MLAB (c) February 2009 Altera Corporation LAB Arria II GX Device Handbook Volume 1 2-4 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II GX Devices Adaptive Logic Modules LAB Control Signals Each LAB contains dedicated logic for driving control signals to its ALMs, and has two unique clock sources and three clock enable signals, as shown in Figure 2-4. The LAB control block can generate up to three clocks using the two clock sources and three clock enable signals. Each LAB's clock and clock enable signals are linked. De-asserting the clock enable signal turns off the corresponding LAB-wide clock. Figure 2-4. LAB-Wide Control Signals There are two unique clock signals per LAB. 6 Dedicated Row LAB Clocks 6 6 Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect labclk0 labclk1 labclkena0 or asyncload or labpreset labclk2 labclkena1 labclkena2 labclr1 syncload labclr0 synclr Adaptive Logic Modules The ALM is the basic building block of logic in the Arria II GX architecture, providing advanced features with efficient logic utilization. One ALM can implement any function of up to six inputs and certain seven-input functions. Each ALM drives all types of interconnects: local, row, column, carry chain, shared arithmetic chain, register chain, and direct link interconnects. Figure 2-5 shows a high-level block diagram of the Arria II GX ALM. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II GX Devices Adaptive Logic Modules 2-5 Figure 2-5. High-Level Block Diagram of the Arria II GX ALM shared_arith_in carry_in Combinational/Memory ALUT0 reg_chain_in labclk To general or local routing dataf0 datae0 6-Input LUT adder0 D Q dataa To general or local routing reg0 datab datac datad datae1 adder1 D Q 6-Input LUT To general or local routing reg1 dataf1 To general or local routing Combinational/Memory ALUT1 reg_chain_out shared_arith_out (c) February 2009 Altera Corporation carry_out Arria II GX Device Handbook Volume 1 2-6 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II GX Devices Adaptive Logic Modules Figure 2-6 shows a detailed view of all the connections in an ALM. row, column direct link routing sclr carry_out shared_arith_out dataf1 datae1 3-INPUT LUT 3-INPUT LUT + 3-INPUT LUT 3-INPUT LUT 4-INPUT LUT datad datac dataa datab datae0 dataf0 4-INPUT LUT shared_arith_in + carry_in VCC GND clk[2:0] syncload aclr[1:0] reg_chain_in D D CLR CLR Q row, column direct link routing local interconnect row, column direct link routing row, column direct link routing Q local interconnect Figure 2-6. Arria II GX ALM Details The clock and clear control signals of an ALM's register can be driven by global signals, general-purpose I/O pins, or any internal logic. General-purpose I/O pins or internal logic can drive the clock enable. For combinational functions, the register is bypassed and the output of the look-up table (LUT) drives directly to the outputs of an ALM. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II GX Devices Adaptive Logic Modules 2-7 Each ALM has two sets of outputs that drive the local, row, and column routing resources. The LUT, adder, or register output can drive these outputs (refer to Figure 2-6). For each set of output drivers, two ALM outputs can drive column, row, or direct link routing connections, and one of these ALM outputs can also drive local interconnect resources. This allows the LUT or adder to drive one output while the register drives another output. This feature, called register packing, improves device utilization by allowing the device to use the register and combinational logic for unrelated functions. Another mechanism to improve fitting is to allow the register output to feed back into the LUT of the same ALM so that the register is packed with its own fan-out LUT. The ALM can also drive out registered and unregistered versions of the LUT or adder output. The Quartus(R) II software automatically configures the ALMs for optimized performance. ALM Operating Modes The Arria II GX ALM can operate in any of the following modes: Normal Extended LUT Arithmetic Shared Arithmetic LUT-Register The Quartus II software and supported third-party synthesis tools, in conjunction with parameterized functions such as the library of parameterized modules (LPM) functions, automatically choose the appropriate mode for common functions such as counters, adders, subtractors, and arithmetic functions. Normal Mode Normal mode is suitable for general logic applications and combinational functions. In this mode, up to eight data inputs from the LAB local interconnect are inputs to the combinational logic. Normal mode allows two functions to be implemented in one Arria II GX ALM, or an ALM to implement a single function of up to six inputs. The ALM can support certain combinations of completely independent functions and various combinations of functions that have common inputs. The Quartus II Compiler automatically searches for functions of common inputs or completely independent functions to be placed into one ALM and to make efficient use of the device resources. Extended LUT Mode Use extended LUT mode to implement a specific set of seven-input functions. The set must be a 2-to-1 multiplexer fed by two arbitrary five-input functions sharing four inputs. Figure 2-7 shows the template of supported seven-input functions utilizing extended LUT mode. In this mode, if the seven-input function is unregistered, the unused eighth input is available for register packing. Functions that fit into the template shown in Figure 2-7 often appear in designs as "if-else" statements in Verilog HDL or VHDL code. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 2-8 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II GX Devices Adaptive Logic Modules Figure 2-7. Template for Supported Seven-Input Functions in Extended LUT Mode datae0 datac dataa datab datad dataf0 5-Input LUT To general or local routing combout0 D 5-Input LUT Q To general or local routing reg0 datae1 dataf1 (1) This input is available for register packing. Note to Figure 2-7: (1) If the seven-input function is unregistered, the unused eighth input is available for register packing. The second register, reg1, is not available. Arithmetic Mode Arithmetic mode is ideal for implementing adders, counters, accumulators, wide parity functions, and comparators. The ALM in arithmetic mode uses two sets of 2 four-input LUTs along with two dedicated full adders. The dedicated adders allow the LUTs to be available to perform pre-adder logic; therefore, each adder can add the output of 2 four-input functions. Figure 2-8 shows an ALM in arithmetic mode. Figure 2-8. ALM in Arithmetic Mode carry_in datae0 adder0 4-Input LUT To general or local routing D dataf0 datac datab dataa datad datae1 Q To general or local routing reg0 4-Input LUT adder1 4-Input LUT To general or local routing D 4-Input LUT Q To general or local routing reg1 dataf1 carry_out Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II GX Devices Adaptive Logic Modules 2-9 In arithmetic mode, the ALM support simultaneous use of the adder 's carry output along with combinational logic outputs. In this operation, the adder output is ignored. This usage of the adder with the combinational logic output provides resource savings of up to 50%. Arithmetic mode also offers clock enable, counter enable, synchronous up and down control, add and subtract control, synchronous clear, and synchronous load. The LAB local interconnect data inputs generate the clock enable, counter enable, synchronous up and down, and add and subtract control signals. These control signals are good candidates for the inputs that are shared between the four LUTs in the ALM. The synchronous clear and synchronous load options are LAB-wide signals that affect all registers in the LAB. These signals can also be individually disabled or enabled per register. The Quartus II software automatically places any registers that are not used by the counter into other LABs. Carry Chain The carry chain provides a fast carry function between the dedicated adders in arithmetic or shared arithmetic mode. The two-bit carry select feature in Arria II GX devices halves the propagation delay of carry chains within the ALM. Carry chains can begin in either the first ALM or the fifth ALM in a LAB. The final carry-out signal is routed to an ALM, where it is fed to local, row, or column interconnects. The Quartus II Compiler automatically creates carry chain logic during design processing, or you can create it manually during design entry. Parameterized functions such as library of parameterized modules (LPM) automatically take advantage of carry chains for the appropriate functions. The Quartus II Compiler creates carry chains longer than 20 ALMs (10 ALMs in arithmetic or shared arithmetic mode) by linking LABs together automatically. For enhanced fitting, a long carry chain runs vertically, allowing fast horizontal connections to TriMatrix memory and DSP blocks. A carry chain can continue as far as a full column. To avoid routing congestion in one small area of the device when a high fan-in arithmetic function is implemented, the LAB can support carry chains that only use either the top half or bottom half of the LAB before connecting to the next LAB. This leaves the other half of the ALMs in the LAB available for implementing narrower fan-in functions in normal mode. Carry chains that use the top five ALMs in the first LAB carry into the top half of the ALMs in the next LAB in the column. Carry chains that use the bottom five ALMs in the first LAB carry into the bottom half of the ALMs in the next LAB within the column. In every alternate LAB column, the top half can be bypassed; in the other MLAB columns, the bottom half can be bypassed. 1 (c) February 2009 For more information on carry chain interconnect, refer to "ALM Interconnects" on page 2-13. Altera Corporation Arria II GX Device Handbook Volume 1 2-10 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II GX Devices Adaptive Logic Modules Shared Arithmetic Mode In shared arithmetic mode, the ALM can implement a three-input add in an ALM. In this mode, the ALM is configured with 4 four-input LUTs. Each LUT either computes the sum of three inputs or the carry of three inputs. The output of the carry computation is fed to the next adder using a dedicated connection called the shared arithmetic chain. This shared arithmetic chain can significantly improve the performance of an adder tree by reducing the number of summation stages required to implement an adder tree. Figure 2-9 shows the ALM using this feature. Figure 2-9. ALM in Shared Arithmetic Mode shared_arith_in carry_in labclk 4-Input LUT To general or local routing D datae0 datac datab dataa Q reg0 4-Input LUT 4-Input LUT datad datae1 To general or local routing To general or local routing D 4-Input LUT Q To general or local routing reg1 carry_out shared_arith_out Shared Arithmetic Chain The shared arithmetic chain available in enhanced arithmetic mode allows the ALM to implement a three-input add. This significantly reduces the resources necessary to implement large adder trees or correlator functions. The shared arithmetic chains can begin in either the first or sixth ALM in an LAB. The Quartus II Compiler creates shared arithmetic chains longer than 20 ALMs (10 ALMs in arithmetic or shared arithmetic mode) by linking LABs together automatically. For enhanced fitting, a long shared arithmetic chain runs vertically, allowing fast horizontal connections to memory and DSP blocks. A shared arithmetic chain can continue as far as a full column. Similar to the carry chains, the top and bottom half of shared arithmetic chains in alternate LAB columns can be bypassed. This capability allows the shared arithmetic chain to cascade through half of the ALMs in an LAB while leaving the other half available for narrower fan-in functionality. Every other LAB column is top-half bypassable, while the other LAB columns are bottom-half bypassable. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II GX Devices Adaptive Logic Modules 1 2-11 For more information on shared arithmetic chain interconnect, refer to "ALM Interconnects" on page 2-13. LUT-Register Mode LUT-Register mode allows third register capability in an ALM. Two internal feedback loops allow combinational ALUT1 to implement the master latch and combinational ALUT0 to implement the slave latch needed for the third register. The LUT register shares its clock, clock enable, and asynchronous clear sources with the top dedicated register. Figure 2-10 shows the register constructed using two combinational blocks in the ALM. Figure 2-10. LUT Register from Two Combinational Blocks sumout clk LUT regout 4-input LUT aclr combout Master latch sumout 5-input LUT datain(datac) combout sclr Slave latch Figure 2-11 shows the ALM in LUT-Register mode. Figure 2-11. ALM in LUT-Register Mode with 3-Register Capability clk [2:0] aclr [1:0] reg_chain_in Third register DC1 datain lelocal 0 aclr aclr sclr regout datain latchout sdata leout 0 a regout leout 0 b E0 F1 lelocal 1 aclr datain E1 sdata F0 leout 1 a regout leout 1 b reg_chain_out (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 2-12 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II GX Devices Adaptive Logic Modules Register Chain In addition to general routing outputs, the ALMs in any given LAB have register chain outputs. This allows registers in the same LAB to be cascaded together. The register chain interconnect allows a LAB to use LUTs for a single combinational function and the registers to be used for an unrelated shift register implementation. These resources speed up connections between ALMs while saving local interconnect resources (refer to Figure 2-12). The Quartus II Compiler automatically takes advantage of these resources to improve utilization and performance. Figure 2-12. Register Chain in an LAB (Note 1) From previous ALM in the LAB reg_chain_in labclk To general or local routing adder0 D Q To general or local routing reg0 Combinational Logic adder1 D Q To general or local routing reg1 To general or local routing To general or local routing adder0 D Q To general or local routing reg0 Combinational Logic adder1 D Q To general or local routing reg1 To general or local routing reg_chain_out To next ALM in the LAB Note to Figure 2-12: (1) You can use the combinational or adder logic to implement an unrelated, un-registered function. 1 For more information about register chain interconnect, refer to "ALM Interconnects" on page 2-13. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II GX Devices Document Revision History 2-13 ALM Interconnects There are three dedicated paths between ALMs: Register Cascade, Carry-chain, and Shared Arithmetic chain. Arria II GX devices include an enhanced interconnect structure in LABs for routing shared arithmetic chains and carry chains for efficient arithmetic functions. The register chain connection allows the register output of one ALM to connect directly to the register input of the next ALM in the LAB for fast shift registers. These ALM-to-ALM connections bypass the local interconnect. Figure 2-13 shows the shared arithmetic chain, carry chain, and register chain interconnects. Figure 2-13. Shared Arithmetic Chain, Carry Chain, and Register Chain Interconnects Local interconnect routing among ALMs in the LAB ALM 1 Carry chain & shared arithmetic chain routing to adjacent ALM Register chain routing to adjacent ALM's register input ALM 2 Local interconnect ... ... ALM 3 ALM 10 Clear and Preset Logic Control The ALM directly supports an asynchronous clear function. You can achieve the register preset through the Quartus II software's NOT-gate push-back logic option. Each LAB supports up to two clears. Arria II GX devices provide a device-wide reset pin (DEV_CLRn) that resets all registers in the device. An option set before compilation in the Quartus II software enables this pin. This device-wide reset overrides all other control signals. Document Revision History Table 2-1 shows the revision history for this document. Table 2-1. Document Revision History Date and Document Version February 2009, v1.0 (c) February 2009 Changes Made Initial Release. Altera Corporation Summary of Changes -- Arria II GX Device Handbook Volume 1 2-14 Arria II GX Device Handbook Volume 1 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II GX Devices Document Revision History (c) February 2009 Altera Corporation 3. Memory Blocks in Arria II GX Devices AIIGX51003-1.0 Introduction Arria(R) II GX memory blocks include 640-bit memory logic array blocks (MLABs) and 9-Kbit M9K blocks. You can configure each embedded memory block independently to be a single- or dual-port RAM, FIFO, ROM, or shift register using the Quartus(R) II MegaWizardTM Plug-In Manager. You can stitch together multiple blocks of the same type to produce larger memories with minimal timing penalty. This chapter describes memory blocks, modes, features, and design considerations. This chapter contains the following sections: "Memory Features" on page 3-1 "Memory Modes" on page 3-7 "Clocking Modes" on page 3-14 "Design Considerations" on page 3-15 Memory Features Table 3-1 summarizes the features supported by the memory blocks. Table 3-1. Summary of Memory Features (Part 1 of 2) Feature Maximum performance Total RAM bits (including parity bits) Configurations (depth x width) MLABs M9K Blocks 360 MHz (1) 390 MHz (1) 640 9,216 64 x 8 8K x 1 64 x 9 4K x 2 64 x 10 2K x 4 32 x 16 1K x 8 32 x 18 1K x9 32 x 20 512 x 16 512 x 18 256 x 32 256 x 36 (c) February 2009 Parity bits v v Byte enable v v Packed mode -- v Address clock enable v v Single-port memory v v Simple dual-port memory v v True dual-port memory -- v Altera Corporation Arria II GX Device Handbook Volume 1 3-2 Chapter 3: Memory Blocks in Arria II GX Devices Memory Features Table 3-1. Summary of Memory Features (Part 2 of 2) Feature MLABs M9K Blocks Embedded shift register v v ROM v v FIFO buffer v v Simple dual-port mixed width support -- v True dual-port mixed width support -- v Memory initialization file (.mif) v v Mixed-clock mode v v Power-up condition Outputs cleared if registered, otherwise reads memory contents. Outputs cleared Register clears Output registers Output registers Write/Read operation triggering Write: Falling clock edges Read: Rising clock edges Write and Read: Rising clock edges Same-port read-during-write Outputs set to old data or don't care Outputs set to old data, new data, or don't care Mixed-port read-during-write Outputs set to old data or don't care Outputs set to old data or don't care ECC Support Soft IP support using Quartus II software Soft IP support using Quartus II software Note to Table 3-1: (1) These numbers are preliminary until characterization is final. Table 3-2 shows the capacity and distribution of the memory blocks in each Arria II GX family member. Table 3-2. Memory Capacity and Distribution in Arria II GX Devices Device MLABs M9K Blocks Total RAM Bits (including MLABs) (Kbits) EP2AGX20 319 87 982 EP2AGX30 540 144 1,634 EP2AGX45 903 319 3,435 EP2AGX65 1,265 495 5,246 EP2AGX95 1,874 612 6,679 EP2AGX125 2,482 730 8,121 EP2AGX190 3,806 840 9,939 EP2AGX260 5,130 950 11,756 Memory Block Types M9K memory blocks are dedicated resource; MLABs are dual-purpose blocks. They can be configured as regular LABs or as MLABs. Ten ALMs make up one MLAB. You can configure each ALM in an MLAB as either a 64 x 1 or a 32 x 2 block, resulting in a 64 x 10 or 32 x 20 simple dual-port SRAM block in a single MLAB. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 3: Memory Blocks in Arria II GX Devices Memory Features 3-3 Parity Bit Support All memory blocks have built-in parity bit support. The ninth bit associated with each byte can store a parity bit or serve as an additional data bit. No parity function is actually performed on the ninth bit. Byte Enable Support All memory blocks support byte enables that mask the input data so that only specific bytes of data are written. The unwritten bytes retain the previous written value. The write enable (wren) signals, along with the byte enable (byteena) signals, control the RAM blocks' write operations. The default value for the byte enable signals is high (enabled), in which case writing is controlled only by the write enable signals. The byte enable registers have no clear port. When using parity bits on the M9K blocks, the byte enable controls all nine bits (eight bits of data plus one parity bit). When using parity bits on the MLAB, the byte-enable controls all 10 bits in the widest mode. Byte enables operate in a one-hot fashion, with the LSB of the byteena signal corresponding to the LSB of the data bus. For example, if using a RAM block in x18 mode, byteena = 01, data[8..0] is enabled and data[17..9] is disabled. Similarly, if byteena = 11, both data[8..0] and data[17..9] are enabled. Byte enables are active high. Figure 3-1 shows how the write enable (wren) and byte enable (byteena) signals control the operations of the RAM. When a byte-enable bit is de-asserted during a write cycle, the corresponding data byte output can appear as either a "don't care" value or the current data at that location. The output value for the masked byte is controllable using the Quartus II software. When a byte-enable bit is asserted during a write cycle, the corresponding data byte output also depends on the setting chosen in the Quartus II software. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 3-4 Chapter 3: Memory Blocks in Arria II GX Devices Memory Features Figure 3-1. Arria II GX Byte Enable Functional Waveform inclock wren address data byteena contents at a0 a0 an a1 a2 a0 a1 ABCD XXXX 10 XX XXXX 01 11 FFFF XX ABFF FFFF contents at a1 a2 FFCD FFFF contents at a2 ABCD don't care: q (asynch) doutn ABXX XXCD ABCD ABFF FFCD ABCD current data: q (asynch) doutn ABFF FFCD ABCD ABFF FFCD ABCD Packed Mode Support Arria II GX M9K blocks support packed mode. The packed mode feature packs two independent single-port RAMs into one memory block. The Quartus II software automatically implements packed mode where appropriate by placing the physical RAM block into true dual-port mode and using the MSB of the address to distinguish between the two logical RAMs. The size of each independent single-port RAM must not exceed half of the target block size. Address Clock Enable Support All Arria II GX memory blocks support address clock enable, which holds the previous address value for as long as the signal is enabled (addressstall = 1). When you configure the memory blocks in dual-port mode, each port has its own independent address clock enable. The default value for the address clock enable signals is low (disabled). Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 3: Memory Blocks in Arria II GX Devices Memory Features 3-5 Figure 3-2 shows an address clock enable block diagram. The address clock enable is referred to by the port name addressstall. Figure 3-2. Arria II GX Address Clock Enable Block Diagram address[0] 1 0 address[N] 1 0 address[0] register address[0] address[N] register address[N] addressstall clock Figure 3-3 shows the address clock enable waveform during the read cycle. Figure 3-3. Arria II GX Address Clock Enable during Read Cycle Waveform inclock rdaddress a0 a1 a2 a3 a4 a5 a6 rden addressstall latched address (inside memory) an q (synch) doutn-1 q (asynch) (c) February 2009 Altera Corporation doutn doutn dout0 a4 a1 a0 dout0 dout4 dout1 dout1 a5 dout4 dout5 Arria II GX Device Handbook Volume 1 3-6 Chapter 3: Memory Blocks in Arria II GX Devices Memory Features Figure 3-4 shows the address clock enable waveform during write cycle. Figure 3-4. Arria II GX Address Clock Enable during Write Cycle Waveform inclock wraddress a0 a1 a2 a3 a4 a5 a6 00 01 02 03 04 05 06 data wren addressstall latched address (inside memory) contents at a0 contents at a1 an a1 a0 a5 00 XX XX 01 02 contents at a2 XX contents at a3 XX contents at a4 a4 04 XX contents at a5 03 XX 05 Mixed Width Support M9K memory blocks support mixed data widths inherently. MLABs can support mixed data widths through emulation using the Quartus II software. When using simple dual-port, true dual-port, or FIFO modes, mixed width support allows you to read and write different data widths to a memory block. For more information about the different widths supported per memory mode, refer to "Memory Modes" on page 3-7. Asynchronous Clear Arria II GX memory blocks support asynchronous clears on the output latches and output registers. Therefore, if your RAM is not using output registers, you can still clear the RAM outputs using the output latch asynchronous clear. Figure 3-5 shows a functional waveform showing this functionality. Figure 3-5. Output Latch Asynchronous Clear Waveform outclk aclr aclr at latch q Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 3: Memory Blocks in Arria II GX Devices Memory Modes 3-7 You can selectively enable asynchronous clears per logical memory using the Quartus II RAM MegaWizard Plug-In Manager. f For more information about the RAM MegaWizard Plug-In Manager, refer to the RAM Megafunction User Guide. Memory Modes Arria II GX memory blocks allow you to implement fully synchronous SRAM memory in multiple modes of operation. M9K blocks do not support asynchronous memory (unregistered inputs). MLABs support asynchronous (flow-through) read operations. Depending on which memory block you target, you can use the following modes: Single-port Simple dual-port True dual-port Shift-register ROM FIFO 1 To choose the desired read-during-write behavior, set the read-during-write behavior to either new data, old data, or don't care in the RAM MegaWizard Plug-In Manager in the Quartus II software. For more information about this behavior, refer to "Read-During-Write" on page 3-15. 1 When using the memory blocks in ROM, single-port, simple dual-port, or true dual-port mode, you can corrupt the memory contents if you violate the setup or hold time on any of the memory block input registers. This applies to both read and write operations. Single-Port RAM All memory blocks support single-port mode. Single-port mode allows you to do either one-read or one-write operation at a time. Simultaneous reads and writes are not supported in single-port mode. Figure 3-6 shows the single-port RAM configuration. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 3-8 Chapter 3: Memory Blocks in Arria II GX Devices Memory Modes Figure 3-6. Single-Port Memory (Note 1) data[ ] address[ ] wren byteena[] addressstall inclock clockena rden aclr q[] outclock Note to Figure 3-6: (1) You can implement two single-port memory blocks in a single M9K block. For more information, refer to "Packed Mode Support" on page 3-4. During a write operation, behavior of the RAM outputs is configurable. If you use the read-enable signal and perform a write operation with the read enable de-activated, the RAM outputs retain the values they held during the most recent active read enable. If you activate read enable during a write operation, or if you are not using the read-enable signal at all, the RAM outputs either show the new data being written, the old data at that address, or a don't care value. Table 3-3 shows the possible port width configurations for memory blocks in single-port mode. Table 3-3. Arria II GX Port Width Configurations for MLABs and M9K Blocks Port Width Configurations MLABs M9K Blocks 64 x 8 8K x 1 64 x 9 4K x 2 64 x 10 2K x 4 32 x 16 1K x 8 32 x 18 1K x 9 32 x 20 512 x 16 512 x 18 256 x 32 256 x 36 Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 3: Memory Blocks in Arria II GX Devices Memory Modes 3-9 Figure 3-7 shows timing waveforms for read and write operations in single-port mode with unregistered outputs. Registering the RAM's outputs would simply delay the q output by one clock cycle. Figure 3-7. Timing Waveform for Read-Write Operations (Single-Port Mode) clk_a wrena rdena address_a a0 data_a A q_a (asynch) a1 B a0(old data) C A D B E a1(old data) F D E Simple Dual-Port Mode All memory blocks support simple dual-port mode. Simple dual-port mode allows you to perform one-read and one-write operation to different locations at the same time. Figure 3-8 shows a simple dual-port configuration. Figure 3-8. Arria II GX Simple Dual-Port Memory (Note 1) data[ ] wraddress[ ] wren byteena[] wr_addressstall wrclock wrclocken aclr rdaddress[ ] rden q[ ] rd_addressstall rdclock rdclocken Note to Figure 3-8: (1) Simple dual-port RAM supports input and output clock mode in addition to the read and write clock mode shown. Simple dual-port mode supports different read and write data widths (mixed width support). Table 3-4 shows the mixed width configurations for the M9K blocks in simple dual-port mode. MLABs do not have native support for mixed width operation. The Quartus II software can implement mixed width memories in MLABs with more than one MLAB. Table 3-4. Arria II GX M9K Block Mixed-Width Configurations (Part 1 of 2) Write Port Read Port 8Kx1 4Kx2 2Kx4 1Kx8 512x16 256x32 1Kx9 512x18 256x36 8Kx1 v v v v v v -- -- -- 4Kx2 v v v v v v -- -- -- (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 3-10 Chapter 3: Memory Blocks in Arria II GX Devices Memory Modes Table 3-4. Arria II GX M9K Block Mixed-Width Configurations (Part 2 of 2) Write Port Read Port 8Kx1 4Kx2 2Kx4 1Kx8 512x16 256x32 1Kx9 512x18 256x36 2Kx4 v v v v v v -- -- -- 1Kx8 v v v v v v -- -- -- 512x16 v v v v v v -- -- -- 256x32 v v v v v v -- -- -- 1Kx9 -- -- -- -- -- -- v v v 512x18 -- -- -- -- -- -- v v v 256x36 -- -- -- -- -- -- v v v In simple dual-port mode, M9K blocks support separate write-enable and read-enable signals. Read-during-write operations to the same address can either output a don't care value or old data. MLABs only support a write-enable signal. Read-during-write behavior for the MLABs can be either don't care, new data, or old data. The available choices depend on the configuration of the MLAB. Figure 3-9 shows timing waveforms for read and write operations in simple dual-port mode with unregistered outputs. Registering the RAM's outputs would simply delay the q output by one clock cycle. Figure 3-9. Arria II GX Simple Dual-Port Timing Waveforms wrclock wren wraddress an-1 data din-1 a0 an a1 a2 din a3 a4 a5 din4 din5 a6 din6 rdclock rden rdaddress q (asynch) bn doutn-1 b0 doutn b1 b2 b3 dout0 True Dual-Port Mode Arria II GX M9K blocks support true dual-port mode. Sometimes called bi-directional dual-port, this mode allows you to perform any combination of two port operations: two reads, two writes, or one read and one write at two different clock frequencies. Figure 3-10 shows the true dual-port RAM configuration. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 3: Memory Blocks in Arria II GX Devices Memory Modes 3-11 Figure 3-10. Arria II GX True Dual-Port Memory (Note 1) data_a[ ] address_a[ ] wren_a byteena_a[] addressstall_a clock_a rden_a aclr_a q_a[] data_b[ ] address_b[] wren_b byteena_b[] addressstall_b clock_b rden_b aclr_b q_b[] Note to Figure 3-10: (1) True dual-port memory supports input and output clock mode in addition to the independent clock mode shown. The widest bit configuration of the M9K blocks in true dual-port mode is 512 x 16-bit (x18-bit with parity). Wider configurations are unavailable because the number of output drivers is equivalent to the maximum bit width of the respective memory block. Because true dual-port RAM has outputs on two ports, its maximum width equals half of the total number of output drivers. Table 3-5 lists the possible M9K block mixed-port width configurations in true dual-port mode. Table 3-5. Arria II GX M9K Block Mixed-Width Configuration Write Port Read Port 8Kx1 4Kx2 2Kx4 1Kx8 512x16 1Kx9 512x18 8Kx1 v v v v v -- -- 4Kx2 v v v v v -- -- 2Kx4 v v v v v -- -- 1Kx8 v v v v v -- -- 512x16 v v v v v -- -- 1Kx9 -- -- -- -- -- v v 512x18 -- -- -- -- -- v v In true dual-port mode, M9K blocks support separate write-enable and read-enable signals. Read-during-write operations to the same address can either output new data at that location or old data. In true dual-port mode, you can access any memory location at any time from either port. When accessing the same memory location from both ports, you must avoid possible write conflicts. A write conflict happens when you attempt to write to the same address location from both ports at the same time. This results in unknown data being stored to that address location. No conflict resolution circuitry is built into the Arria II GX memory blocks. You must handle address conflicts external to the RAM block. Figure 3-11 shows true dual-port timing waveforms for the write operation at port A and read operation at port B with the Read-During-Write behavior set to new data. Registering the RAM's outputs would simply delay the q outputs by one clock cycle. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 3-12 Chapter 3: Memory Blocks in Arria II GX Devices Memory Modes Figure 3-11. Arria II GX True Dual-Port Timing Waveform clk_a wren_a address_a data_a an-1 an din-1 din q_a (asynch) din-1 a0 din a1 dout0 a2 dout1 a3 dout2 a4 a5 a6 din4 din5 din6 dout3 din5 din4 clk_b wren_b address_b q_b (asynch) bn doutn-1 b0 b1 b2 b3 doutn dout0 dout1 dout2 Shift-Register Mode All Arria II GX memory blocks support shift register mode. Embedded memory block configurations can implement shift registers for digital signal processing (DSP) applications, such as finite impulse response (FIR) filters, pseudo-random number generators, multi-channel filtering, and auto- and cross-correlation functions. These and other DSP applications require local data storage, traditionally implemented with standard flipflops that quickly exhaust many logic cells for large shift registers. A more efficient alternative is to use embedded memory as a shift-register block, which saves logic cell and routing resources. The size of a shift register (w x m x n) is determined by the input data width (w), the length of the taps (m), and the number of taps (n). You can cascade memory blocks to implement larger shift registers. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 3: Memory Blocks in Arria II GX Devices Memory Modes 3-13 Figure 3-12 shows the memory block in shift-register mode. Figure 3-12. Arria II GX Shift-Register Memory Configuration w x m x n Shift Register m-Bit Shift Register W W m-Bit Shift Register W W n Number of Taps m-Bit Shift Register W W m-Bit Shift Register W W ROM Mode All Arria II GX memory blocks support ROM mode. A memory initialization file (.mif) initializes the ROM contents of these blocks. The address lines of the ROM are registered on M9K blocks, but can be unregistered on MLABs. The outputs can be registered or unregistered. Output registers can be asynchronously cleared. The ROM read operation is identical to the read operation in the single-port RAM configuration. FIFO Mode All memory blocks support FIFO mode. MLABs are ideal for designs with many small, shallow FIFO buffers. To implement FIFO buffers in your design, you can use the FIFO MegaWizard Plug-In Manager in the Quartus II software. Both single- and dual-clock (asynchronous) FIFOs are supported. f (c) February 2009 For more information about implementing FIFO buffers, refer to the Single- and Dual-Clock FIFO Megafunctions User Guide. Altera Corporation Arria II GX Device Handbook Volume 1 3-14 Chapter 3: Memory Blocks in Arria II GX Devices Clocking Modes Clocking Modes Arria II GX memory blocks support the following clocking modes: 1 Independent Input and output Read and write Single clock Violating the setup or hold time on the memory block address registers could corrupt the memory contents. This applies to both read and write operations. Table 3-6 shows the clocking mode versus memory mode support matrix. Table 3-6. Arria II GX Memory Clock Modes True Dual-Port Mode Simple Dual-Port Mode Single-Port Mode ROM Mode FIFO Mode Independent v -- -- v -- Input and output v v v v -- Read and write -- v -- -- v Single clock v v v v v Clocking Mode Independent Clock Mode Arria II GX memory blocks can implement independent clock mode for true dual-port memories. In this mode, a separate clock is available for each port (A and B). Clock A controls all registers on the port A side, while clock B controls all registers on the port B side. Each port also supports independent clock enables for port A and port B registers. Asynchronous clears are supported only for output latches and output registers on both ports. Input and Output Clock Mode Arria II GX memory blocks can implement input and output clock mode for true and simple dual-port memories. In this mode, an input clock controls all registers related to the data input to the memory block including data, address, byte enables, read enables, and write enables. An output clock controls the data output registers. Asynchronous clears are available on output latches and output registers only. Read and Write Clock Mode Arria II GX memory blocks can implement read and write clock mode for simple dual-port memories. In this mode, a write clock controls the data-input, write-address, and write-enable registers. Similarly, a read clock controls the data-output, read-address, and read-enable registers. The memory blocks support independent clock enables for both the read and write clocks. Asynchronous clears are available on data output latches and registers only. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 3: Memory Blocks in Arria II GX Devices Design Considerations 3-15 Single Clock Mode Arria II GX memory blocks can implement single-clock mode for true dual-port, simple dual-port, and single-port memories. In this mode, a single clock, together with a clock enable, is used to control all registers of the memory block. Asynchronous clears are available on output latches and output registers only. Design Considerations This section describes guidelines for designing with memory blocks. Memory Block Selection The Quartus II software automatically partitions user-defined memory into embedded memory blocks by taking into account both speed and size constraints placed on your design. For example, the Quartus II software may spread out memory across multiple memory blocks when resources are available to increase the performance of your design. You can manually assign memory to a specific block size using the RAM MegaWizard Plug-In Manager. MLABs can implement single-port SRAM through emulation using the Quartus II software. Emulation results in minimal additional logic resources being used. Because of the dual-purpose architecture of the MLAB, it only has data input registers and output registers in the block. MLABs gain input address registers and additional optional data output registers from adjacent ALMs with register packing. f For more information about register packing, refer to the Logic Array Blocks and Adaptive Logic Modules in Arria II GX Devices chapter in volume 1 of the Arria II GX Device Handbook. Conflict Resolution When using the memory blocks in true dual-port mode, it is possible to attempt two write operations to the same memory location (address). Because there is no conflict resolution circuitry built into the memory blocks, this results in unknown data being written to that location. Therefore, you must implement conflict resolution logic external to the memory block to avoid address conflicts. Read-During-Write You can customize the read-during-write behavior of the Arria II GX memory blocks to suit your design needs. Two types of read-during-write operations are available: same port and mixed port. Figure 3-13 shows the difference between the two types. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 3-16 Chapter 3: Memory Blocks in Arria II GX Devices Design Considerations Figure 3-13. Arria II GX Read-During-Write Data Flow Port A data in Port B data in Mixed-port data flow Same-port data flow Port A data out Port B data out Same-Port Read-During-Write Mode This mode applies to either a single-port RAM or the same port of a true dual-port RAM. In same-port read-during-write mode, three output choices are available: new data mode (or flow-through), old data mode, or don't care mode. In new data mode, the new data is available on the rising edge of the same clock cycle on which it was written. In old data mode, the RAM outputs reflect the old data at that address before the write operation proceeds. In don't care mode, the RAM outputs don't care values for a read-during-write operation. Figure 3-14 shows sample functional waveforms of same-port read-during-write behavior in new data mode. Figure 3-14. Same Port Read-During Write: New Data Mode clk_a wrena rdena address_a data_a q_a (asynch) Arria II GX Device Handbook Volume 1 a0 A a1 B A C B D C E D F E F (c) February 2009 Altera Corporation Chapter 3: Memory Blocks in Arria II GX Devices Design Considerations 3-17 Figure 3-15 shows sample functional waveforms of same-port read-during-write behavior in old data mode. Figure 3-15. Same Port Read-During-Write: Old Data Mode clk_a wrena rdena address_a data_a q_a (asynch) a0 A a0(old data) a1 B C A D B a1(old data) E F D E Mixed-Port Read-During-Write Mode This mode applies to a RAM in simple or true dual-port mode which has one port reading and the other port writing to the same address location with the same clock. In this mode, you also have two output choices: old data or don't care. In old data mode, a read-during-write operation to different ports causes the RAM outputs to reflect the old data at that address location. In don't care mode, the same operation results in a "don't care" or "unknown" value on the RAM outputs. 1 (c) February 2009 Read-during-write behavior is controlled using the RAM MegaWizard Plug-In Manager. For more information about how to implement the desired behavior, refer to the RAM Megafunction User Guide. Altera Corporation Arria II GX Device Handbook Volume 1 3-18 Chapter 3: Memory Blocks in Arria II GX Devices Design Considerations Figure 3-16 shows a sample functional waveform of mixed-port read-during-write behavior in old data mode. In don't care mode, the old data shown in the figure is simply replaced with "don't care". Figure 3-16. Mixed Port Read During Write: Old Data Mode clk_a&b wrena address_a a b A data_a B C D E F rdena address_b a a (old data) q_b (asynch) b A B b (old data) D E Mixed-port read-during-write is not supported when two different clocks are used in a dual-port RAM. The output value is unknown during a dual-clock mixed-port read-during-write operation. Power-Up Conditions and Memory Initialization M9K memory block outputs power up to zero (cleared), regardless of whether the output registers are used or bypassed. MLABs power up to zero if output registers are used and power up reading the memory contents if output registers are not used. The Quartus II software initializes the RAM cells to zero unless there is an MIF file (.mif) specified. All memory blocks support initialization using a .mif file. You can create .mif files in the Quartus II software and specify their use with the RAM MegaWizard Plug-In Manager when instantiating a memory in your design. Even if a memory is pre-initialized (for example, using a .mif file), it still powers up with its outputs cleared. f For more information about .mif files, refer to the RAM Megafunction User Guide and the Quartus II Handbook. Power Management Arria II GX memory block clock-enables allow you to control clocking of each memory block to reduce AC-power consumption. Use the read-enable signal to ensure that read operations only occur when you need them to. If your design does not require read-during-write, you can reduce your power consumption by de-asserting the read-enable signal during write operations or any period when no memory operations occur. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 3: Memory Blocks in Arria II GX Devices Document Revision History 3-19 The Quartus II software automatically places any unused memory blocks in low power mode to reduce static power. Document Revision History Table 3-7 shows the revision history for this chapter. Table 3-7. Document Revision History Date and Document Version February 2009, v1.0 (c) February 2009 Changes Made Initial Release. Altera Corporation Summary of Changes -- Arria II GX Device Handbook Volume 1 3-20 Arria II GX Device Handbook Volume 1 Chapter 3: Memory Blocks in Arria II GX Devices Document Revision History (c) February 2009 Altera Corporation 4. DSP Blocks in Arria II GX Devices AIIGX51004-1.0 Introduction The Arria (R) II GX family of devices have dedicated high-performance digital signal processing (DSP) blocks optimized for DSP applications. These DSP blocks are the fourth generation of hardwired, fixed-function silicon blocks dedicated to maximizing signal processing capability and ease-of-use at the lowest silicon cost. Many complex systems, such as WiMAX, 3GPP WCDMA, high-performance computing (HPC), voice over Internet protocol (VoIP), H.264 video compression, medical imaging, and HDTV, use sophisticated DSP techniques. Arria II GX devices are ideally suited as the DSP blocks consist of a combination of dedicated elements that perform multiplication, addition, subtraction, accumulation, summation, and dynamic shift operations. This chapter contains the following sections: "DSP Block Overview" on page 4-1 "Simplified DSP Operation" on page 4-3 "Operational Modes Overview" on page 4-5 "DSP Block Resource Descriptions" on page 4-6 "Operational Mode Descriptions" on page 4-13 "Software Support for Arria II GX Devices" on page 4-31 DSP Block Overview Each Arria II GX device has two to four columns of DSP blocks that implement multiplication, multiply-add, multiply-accumulate (MAC), and dynamic shift functions. Architectural highlights of the Arria II GX DSP block include: (c) February 2009 High-performance, power-optimized, fully registered and pipelined multiplication operations High-performance DSP blocks up to 350 MHz Natively supported 9-bit, 12-bit, 18-bit, 36-bit word lengths Natively supported 18-bit complex multiplications Efficiently supported floating-point arithmetic formats (24-bits for single precision and 53-bits for double precision) Signed and unsigned input support Built-in addition, subtraction, and accumulation units to combine multiplication results efficiently Cascading 18-bit input bus to form tap-delay line for filtering applications Cascading 44-bit output bus to propagate output results from one block to the next block without external logic support Altera Corporation Arria II GX Device Handbook Volume 1 4-2 Chapter 4: DSP Blocks in Arria II GX Devices DSP Block Overview Rich and flexible arithmetic rounding and saturation units Efficient barrel shifter support Loopback capability to support adaptive filtering Table 4-1 shows the number of DSP blocks in Arria II GX devices. Table 4-1. Number of DSP Blocks in Arria II GX Devices Device DSP Blocks Independent Input and Output Multiplication Operators High Precision Multiplier Adder Mode Four Multiplier Adder Mode 9x9 Multipliers 12 x 12 Multipliers 18 x 18 Multipliers 18 x 18 Complex 36 x 36 Multipliers 18 x 36 18 x 18 2AGX20 7 56 42 28 14 14 28 56 2AGX30 16 128 96 64 32 32 64 128 2AGX45 29 232 174 116 58 58 116 232 2AGX65 39 312 234 156 78 78 156 312 2AGX95 56 448 336 224 112 112 224 448 2AGX125 72 576 432 288 144 144 288 576 2AGX190 82 656 492 328 164 164 328 656 2AGX260 92 736 552 368 184 184 368 736 Each DSP block occupies four logic array blocks (LABs) in height and can be divided further into two half-blocks that share some common clocks. Figure 4-1 shows the layout of each block. Figure 4-1. Overview of DSP Block Signals 34 Control 144 Input Data Half-DSP Block 72 Output Data 72 Output Data 288 144 Half-DSP Block Full DSP Block Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 4: DSP Blocks in Arria II GX Devices Simplified DSP Operation 4-3 Simplified DSP Operation The fundamental building block of Arria II GX devices is a pair of 18 x 18-bit multipliers followed by a first-stage 37-bit addition/subtraction unit, as shown in Equation 4-1 and Figure 4-2. For all signed numbers, input and output data is represented in 2's complement format only. Equation 4-1. Multiplier Equation P[36..0] = A0[17..0] x B0[17..0] A1 [17..0] x B1 [17..0] Figure 4-2. Basic Two-Multiplier Adder Building Block A0[17..0] B0[17..0] +/- A1[17..0] D Q B1[17..0] D Q P[36..0] The structure shown in Figure 4-2 is useful for building more complex structures, such as complex multipliers and 36 x 36 multipliers, as described in later sections. Each Arria II GX DSP block contains four two-multiplier adder units (2 two-multiplier adder units per half-block). Therefore, there are eight 18 x 18 multiplier functionalities per DSP block. For a detailed diagram of the DSP block, refer to Figure 4-4 on page 4-7. Following the two-multiplier adder units are the pipeline registers, the second-stage adders, and an output register stage. You can configure the second-stage adders to provide the alternative functions shown in Equation 4-1 and Equation 4-2 per half-block. Equation 4-2. Four-Multiplier Adder Equation Z[37..0] = P0 [36..0] + P1[36..0] (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 4-4 Chapter 4: DSP Blocks in Arria II GX Devices Simplified DSP Operation Equation 4-3. Four-Multiplier Adder Equation (44-Bit Accumulation) Wn[43..0] = Wn-1[43..0] Zn[37..0] In these equations, n denotes sample time and P[36..0] are the results from the two-multiplier adder units. Equation 4-2 provides a sum of four 18 x 18-bit multiplication operations (four-multiplier adder), and Equation 4-3 provides a four 18 x 18-bit multiplication operation, but with a maximum of a 44-bit accumulation capability by feeding the output from the output register bank back to the adder/accumulator block. For the output register bank and adder/accumulator block, refer to Figure 4-3. You can bypass all register stages depending on which mode you select. To support finite impulse response (FIR)-like structures efficiently, a major addition to the DSP block in Arria II GX devices is the ability to propagate the result of one half-block to the next half-block completely in the DSP block without additional soft logic overhead. This is achieved by the inclusion of a dedicated addition unit and routing that adds the 44-bit result of a previous half-block with the 44-bit result of the current block. The 44-bit result is either fed to the next half-block or out of the DSP block using the output register stage. This is shown in Figure 4-3. Detailed examples are described in later sections. To support single-channel type FIR filters efficiently, you can configure one of the multiplier input's registers to form a tap delay line input, saving resources and providing higher system performance. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 4: DSP Blocks in Arria II GX Devices Operational Modes Overview 4-5 Figure 4-3. Output Cascading Feature for FIR Structures From Previous Half-Block DSP Output Register Bank Round/Saturate Adder/ Accumulator + 44 Result[] + Input Register Bank 144 Input Data Pipeline Register Bank + 44 Half DSP Block 44 To Next Half-Block DSP Operational Modes Overview You can use each Arria II GX DSP block in one of five basic operational modes. Table 4-2 shows the five basic operational modes and the number of multipliers that you can implement in a single DSP block, depending on the mode. Table 4-2. Arria II GX DSP Block Operation Modes (Part 1 of 2) Multiplier in Width Number of Multiplier # per Block Signed or Unsigned RND, SAT In Shift Register Chainout Adder 1st Stage Add/Sub 2nd Stage Add/Acc 9-bits 1 8 Both No No No -- -- 12-bits 1 6 Both No No No -- -- 18-bits 1 4 Both Yes Yes No -- -- 36-bits 1 2 Both No No No -- -- Double 1 2 Both No No No -- -- Two-Multiplier Adder (1) 18-bits 2 4 Signed (4) Yes No No Both -- Four-Multiplier Adder 18-bits 4 2 Both Yes Yes Yes Both Add Only Multiply Accumulate 18-bits 4 2 Both Yes Yes Yes Both Both Mode Independent Multiplier (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 4-6 Chapter 4: DSP Blocks in Arria II GX Devices DSP Block Resource Descriptions Table 4-2. Arria II GX DSP Block Operation Modes (Part 2 of 2) Mode Shift (2) Multiplier in Width 36-bits (3) High Precision 18x36 Multiplier Adder Number of Multiplier # per Block Signed or Unsigned RND, SAT In Shift Register Chainout Adder 1st Stage Add/Sub 2nd Stage Add/Acc 1 2 Both No No -- -- -- 2 2 Both No No No -- Add Only Notes to Table 4-2: (1) This mode also supports loopback mode. In loopback mode, the number of loopback multipliers per DSP block is two. You can use the remaining multipliers in regular two-multiplier adder mode. (2) Dynamic shift mode supports arithmetic shift left, arithmetic shift right, logical shift left, logical shift right, and rotation operation. (3) Dynamic shift mode operates on a 32-bit input vector but the multiplier width is configured as 36 bits. (4) Unsigned value is also supported but you must ensure that the result can be contained in 36 bits. The DSP block consists of two identical halves: top-half and bottom-half. Each half has four 18 x 18 multipliers. Arria II GX DSP blocks can operate in different modes simultaneously. Each half-block is fully independent except for the sharing of the four clock, ena, and the aclr signals. For example, you can break down a single DSP block to operate a 9 x 9 multiplier in one half-block and an 18 x 18 two-multiplier adder in the other half-block. This increases DSP block resource efficiency and allows you to implement more multipliers in an Arria II GX device. The Quartus II software automatically places multipliers that can share the same DSP block resources in the same block. DSP Block Resource Descriptions The DSP block consists of the following elements: Input register bank Four two-multiplier adders Pipeline register bank Two second-stage adders Four round and saturation logic units Second adder register and output register bank Figure 4-4 shows a detailed overall architecture of the top half of the DSP block. Table 4-9 on page 4-30 shows a list of DSP block dynamic signals. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 4: DSP Blocks in Arria II GX Devices DSP Block Resource Descriptions 4-7 Figure 4-4. Half-DSP Block Architecture clock[3..0] ena[3..0] alcr[3..0] chainin[ ] signa signb output_round output_saturate rotate shift_right zero_loopback accum_sload zero_chainout chainout_round chainout_saturate overflow (1) chainout_sat_overflow (2) scanina[ ] datab_3[ ] Multiplexer Shift/Rotate Output Register Bank Second Round/Saturate dataa_3[ ] Chainout Adder datab_2[ ] Second Adder Register Bank dataa_2[ ] First Round/Saturate datab_1[ ] First Stage Adder Input Register Bank datab_0[ ] dataa_1[ ] Second Stage Adder/Accumulator loopback Pipeline Register Bank First Stage Adder dataa_0[ ] result[ ] Half-DSP Block scanouta chainout Notes to Figure 4-4: (1) Block output for accumulator overflow and saturate overflow. (2) Block output for saturation overflow of chainout. (3) When the chainout adder is not in use, the second adder register banks are known as output register banks. Input Registers All DSP block registers are triggered by the positive edge of the clock signal and are cleared upon power up. Each multiplier operand can feed an input register or feed directly to the multiplier, bypassing the input registers. The following DSP block signals control the input registers in the DSP block: (c) February 2009 clock[3..0] ena[3..0] aclr[3..0] Altera Corporation Arria II GX Device Handbook Volume 1 4-8 Chapter 4: DSP Blocks in Arria II GX Devices DSP Block Resource Descriptions Every DSP block has nine 18-bit data input register banks per half DSP block. Every half DSP block has the option to use the eight data register banks as inputs to the four multipliers. The special ninth register bank is a delay register required by modes that use both the cascade and chainout features of the DSP block for balancing the latency requirements. A feature of the input register bank is to support a tap delay line. Therefore, the top leg of the multiplier input (A) can be driven from general routing or from the cascade chain, as shown in Figure 4-5. Table 4-9 on page 4-30 shows a list of DSP block dynamic signals. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 4: DSP Blocks in Arria II GX Devices DSP Block Resource Descriptions 4-9 Figure 4-5. Input Register of Half-DSP Block (Note 1) clock[3..0] ena[3..0] aclr[3..0] signa signb scanina[17..0] dataa_0[17..0] loopback datab_0[17..0] +/- dataa_1[17..0] datab_1[17..0] dataa_2[17..0] datab_2[17..0] +/- dataa_3[17..0] datab_3[17..0] Delay Register scanouta Note to Figure 4-5: (1) The scanina signal originates from the previous DSP block, while the scanouta signal goes to the next DSP block. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 4-10 Chapter 4: DSP Blocks in Arria II GX Devices DSP Block Resource Descriptions You must select the incoming data for multiplier input (A) from either general routing or from the cascade chain at compile time. In cascade mode, the dedicated shift outputs from one multiplier block directly feeds input registers of the adjacent multiplier below it (in the same half DSP block) or the first multiplier in the next half DSP block, to form an 8-tap shift register chain per DSP Block. The DSP block can increase the length of the shift register chain by cascading to the lower DSP blocks. The dedicated shift register chain spans a single column, but you can implement longer shift register chains requiring multiple columns using the regular FPGA routing resources. Shift registers are useful in DSP functions such as FIR filters. When implementing 18 x 18 or smaller width multipliers, you do not require external logic to create the shift register chain because the input shift registers are internal to the DSP block. This implementation significantly reduces the logical element (LE) resources required, avoids routing congestion, and results in predictable timing. The first multiplier in every half DSP block (top- and bottom-half) in Arria II GX devices has a multiplexer for the first multiplier B-input (lower-leg input) register to select between general routing and loopback, as shown in Figure 4-4 on page 4-7. In loopback mode, the most significant 18-bit registered outputs are connected as feedback to the multiplier input of the first top multiplier in each half DSP block. Loopback modes are used by recursive filters where the previous output is required to compute the current output. Loopback mode is described in detail in "Two-Multiplier Adder Sum Mode" on page 4-20. Table 4-3 shows the summary of input register modes for the DSP block. Table 4-3. Input Register Modes Register Input Mode (1) 9x9 12 x 12 18 x 18 36 x 36 Double Parallel input v v v v v Shift register input (2) -- -- v -- -- Loopback input (3) -- -- v -- -- Notes to Table 4-3: (1) The multiplier operand input wordlengths are statically configured at compile time. (2) Available only on the A-operand. (3) Only one loopback input is allowed per half-block. For details, refer to Figure 4-12 on page 4-21. Multiplier and First-Stage Adder The multiplier stage supports 9 x 9, 12 x 12, 18 x 18, or 36 x 36 multipliers. Other wordlengths are padded up to the nearest appropriate native wordlength; for example, 16 x 16 would be padded up to use 18 x 18. For more information, refer to "Independent Multiplier Modes" on page 4-13. Depending on the data width of the multiplier, a single DSP block can perform many multiplications in parallel. Each multiplier operand can be a unique signed or unsigned number. Two dynamic signals, signa and signb, control the representation of each operand, respectively. A logic 1 value on the signa/signb signal indicates that data A/data B is a signed number; a logic 0 value indicates an unsigned number. Table 4-4 shows the sign of the multiplication result for the various operand sign representations. The result of the multiplication is signed if any one of the operands is a signed value. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 4: DSP Blocks in Arria II GX Devices DSP Block Resource Descriptions 4-11 Table 4-4. Multiplier Sign Representation Data A (signa Value) Data B (signb Value) Result Unsigned (logic 0) Unsigned (logic 0) Unsigned Unsigned (logic 0) Signed (logic 1) Signed Signed (logic 1) Unsigned (logic 0) Signed Signed (logic 1) Signed (logic 1) Signed Each half-block has its own signa and signb signal. Therefore, all data A inputs feeding the same DSP half-block must have the same sign representation. Similarly, all data B inputs feeding the same DSP half-block must have the same sign representation. The multiplier offers full precision regardless of the sign representation in all operational modes except for full precision 18 x 18 loopback and two-multiplier adder modes. For more information, refer to "Two-Multiplier Adder Sum Mode" on page 4-20. 1 When signals signa and signb are unused, the Quartus II software sets the multiplier to perform unsigned multiplication by default. The outputs of the multipliers are the only outputs that can feed into the first-stage adder, as shown in Figure 4-4 on page 4-7. There are four first-stage adders in a DSP block (two adders per half DSP block). The first-stage adder block has the ability to perform addition and subtraction. The control signal for addition or subtraction is static and has to be configured upon compile time. The first-stage adders are used by the sum modes to compute the sum of two multipliers, 18 x 18-complex multipliers, and to perform the first stage of a 36 x 36 multiply and shift operation. Depending on your specifications, the output of the first-stage adder has the option to feed into the pipeline registers, second-stage adder, round and saturation unit, or the output registers. Pipeline Register Stage The output from the first-stage adder can either feed or bypass the pipeline registers, as shown in Figure 4-4 on page 4-7. Pipeline registers increase the DSP block's maximum performance (at the expense of extra cycles of latency), especially when using the subsequent DSP block stages. Pipeline registers split up the long signal path between the input-registers/multiplier/first-stage adder and the second-stage adder/round-and-saturation/output-registers, creating two shorter paths. Second-Stage Adder There are four individual 44-bit second-stage adders per DSP block (two adders per half DSP block). You can configure the second-stage adders as follows: (c) February 2009 The final stage of a 36-bit multiplier A sum of four (18 x 18) An accumulator (44-bits maximum) A chained output summation (44-bits maximum) Altera Corporation Arria II GX Device Handbook Volume 1 4-12 Chapter 4: DSP Blocks in Arria II GX Devices DSP Block Resource Descriptions 1 You can use the chained-output adder at the same time as a second-level adder in chained output summation mode. The output of the second-stage adder has the option to go into the round and saturation logic unit or the output register. 1 You cannot use the second-stage adder independently from the multiplier and first-stage adder. Round and Saturation Stage Round and saturation logic units are located at the output of the 44-bit second-stage adder (the round logic unit followed by the saturation logic unit). There are two round and saturation logic units per half DSP block. The input to the round and saturation logic unit can come from one of the following stages: Output of the multiplier (independent multiply mode in 18 x 18) Output of the first-stage adder (two-multiplier adder) Output of the pipeline registers Output of the second-stage adder (four-multiplier adder, multiply-accumulate mode in 18 x 18) These stages are described in detail in "Operational Mode Descriptions" on page 4-13. The round and saturation logic unit is controlled by the dynamic round and saturate signals, respectively. A logic 1 value on the round and/or saturate enables the round and/or saturate logic unit, respectively. 1 You can use the round and saturation logic units together or independently. Second Adder and Output Registers The second adder register and output register banks are two banks of 44-bit registers that can also be combined to form larger 72-bit banks to support 36 x 36 output results. The outputs of the different stages in the Arria II GX devices are routed to the output registers through an output selection unit. Depending on the operational mode of the DSP block, the output selection unit selects whether the outputs of the DSP blocks comes from the outputs of the multiplier block, first-stage adder, pipeline registers, second-stage adder, or the round and saturation logic unit. The output selection unit is set automatically by the software, based on the DSP block operational mode you specified, and has the option to either drive or bypass the output registers. The exception is when the block is used in shift mode, in which case you dynamically controls the output-select multiplexer directly. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 4: DSP Blocks in Arria II GX Devices Operational Mode Descriptions 4-13 When the DSP block is configured in chained cascaded output mode, both of the second-stage adders are used. The first adder is used for performing four-multiplier adder and the second is used for the chainout adder. The outputs of the four-multiplier adder are routed to the second-stage adder registers before it enters the chainout adder. The output of the chainout adder goes to the regular output register bank. Depending on the configuration, the chainout results can be routed to the input of the next half-block's chainout adder input or to the general fabric (functioning as regular output registers). The second-stage and output registers are triggered by the positive edge of the clock signal and are cleared on power up. The following DSP block signals control the output registers in the DSP block: clock[3..0] ena[3..0] aclr[3..0] Operational Mode Descriptions This section describes the operation modes of Arria II GX devices. Independent Multiplier Modes In independent input and output multiplier mode, the DSP block performs individual multiplication operations for general-purpose multipliers. 9-, 12-, and 18-Bit Multiplier You can configure each DSP block multiplier for 9-, 12-, or 18-bit multiplication. A single DSP block can support up to eight individual 9 x 9 multipliers, six 12 x 12 multipliers, or up to four individual 18 x 18 multipliers. For operand widths up to 9-bits, a 9 x 9 multiplier is implemented. For operand widths from 10 to 12 bits, a 12 x 12 multiplier is implemented and for operand widths from 13 to 18 bits, an 18 x 18 multiplier is implemented. This is done by the Quartus II software by zero-padding the LSBs. Figure 4-6, Figure 4-7, and Figure 4-8 show the DSP block in the independent multiplier operation mode. A list of DSP block dynamic signals is shown in Table 4-9 on page 4-30. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 4-14 Chapter 4: DSP Blocks in Arria II GX Devices Operational Mode Descriptions Figure 4-6. 18-Bit Independent Multiplier Mode Shown for Half-DSP Block signa clock[3..0] signb overflow (1) 18 datab_1[17..0] Pipeline Register Bank 18 dataa_1[17..0] Input Register Bank 18 datab_0[17..0] 36 result_0[ ] Output Register Bank 18 dataa_0[17..0] Round/Saturate output_round output_saturate Round/Saturate ena[3..0] aclr[3..0] 36 result_1[ ] Half-DSP Block Note to Figure 4-6: (1) Block output for accumulator overflow and saturate overflow. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 4: DSP Blocks in Arria II GX Devices Operational Mode Descriptions 4-15 Figure 4-7. 12-Bit Independent Multiplier Mode Shown for Half-DSP Block clock[3..0] ena[3..0] aclr[3..0] signa signb 12 dataa_0[11..0] 24 result_0[ ] 12 Output Register Bank 12 datab_1[11..0] Pipeline Register Bank 12 dataa_1[11..0] Input Register Bank datab_0[11..0] 24 result_1[ ] 12 dataa_2[11..0] 24 result_2[ ] 12 datab_2[11..0] Half-DSP Block (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 4-16 Chapter 4: DSP Blocks in Arria II GX Devices Operational Mode Descriptions Figure 4-8. 9-Bit Independent Multiplier Mode Shown for Half-Block clock[3..0] ena[3..0] aclr[3..0] signa signb 9 dataa_0[8..0] 18 result_0[ ] 9 datab_0[8..0] 9 dataa_1[8..0] Output Register Bank 9 dataa_2[8..0] Pipeline Register Bank 9 datab_1[8..0] Input Register Bank 18 result_1[ ] 18 result_2[ ] 9 datab_2[8..0] 9 dataa_3[8..0] 18 result_3[ ] 9 datab_3[8..0] Half-DSP Block The multiplier operands can accept signed integers, unsigned integers, or a combination of both. You can change the signa and signb signals dynamically and can be registered in the DSP block. Additionally, the multiplier inputs and result can be registered independently. You can use the pipeline registers in the DSP block to pipeline the multiplier result, increasing the performance of the DSP block. 1 The round and saturation logic unit is supported for 18-bit independent multiplier mode only. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 4: DSP Blocks in Arria II GX Devices Operational Mode Descriptions 4-17 36-Bit Multiplier You can construct a 36 x 36 multiplier using four 18 x 18 multipliers. This simplification fits into one half-DSP block and is implemented in the DSP block automatically by selecting 36 x 36 mode. The 36-bit multiplier is also under the independent multiplier mode but uses the entire half DSP block, including the dedicated hardware logic after the pipeline registers to implement the 36 x 36-bit multiplication operation, as shown in Figure 4-9. The 36-bit multiplier is useful for applications requiring more than 18-bit precision; for example, for the mantissa multiplication portion of single precision and extended single precision floating-point arithmetic applications. Figure 4-9. 36-Bit Independent Multiplier Mode Shown for Half-DSP Block clock[3..0] ena[3..0] aclr[3..0] signa signb dataa_0[35..18] datab_0[35..18] datab_0[17..0] + Output Register Bank dataa_0[35..18] Input Register Bank datab_0[35..18] Pipeline Register Bank + dataa_0[17..0] 72 result[ ] + dataa_0[17..0] datab_0[17..0] Half-DSP Block (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 4-18 Chapter 4: DSP Blocks in Arria II GX Devices Operational Mode Descriptions Double Multiplier You can configure the Arria II GX DSP block to support an unsigned 54 x 54-bit multiplier that is required to compute the mantissa portion of an IEEE double precision floating point multiplication. You can build a 54 x 54-bit multiplier using basic 18 x 18 multipliers, shifters, and adders. To efficiently use the Arria II GX DSP block's built in shifters and adders, a special double mode (partial 54 x 54 multiplier) is available that is a slight modification to the basic 36 x 36 multiplier mode. Figure 4-10 shows a 54 x 54-bit multiplier which include the special double mode multiplier. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 4: DSP Blocks in Arria II GX Devices Operational Mode Descriptions 4-19 Figure 4-10. Unsigned 54 x 54-Bit Multiplier clock[3..0] ena[3..0] aclr[3..0] "0" "0" dataa[53..36] signa signb Two Multiplier Adder Mode + 36 datab[53..36] dataa[35..18] Double Mode 55 datab[35..18] dataa[53..36] datab[17..0] dataa[35..18] Final Adder (implemented with ALUT logic) datab[53..36] dataa[53..36] Shifters and Adders datab[53..36] dataa[17..0] 108 result[ ] 36 x 36 Mode datab[35..18] dataa[35..18] Shifters and Adders datab[35..18] dataa[17..0] 72 datab[17..0] dataa[17..0] datab[17..0] Unsigned 54 X 54 Multiplier (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 4-20 Chapter 4: DSP Blocks in Arria II GX Devices Operational Mode Descriptions Two-Multiplier Adder Sum Mode In the two-multiplier adder configuration, the DSP block can implement four 18-bit two-multiplier adders (2 two-multiplier adders per half DSP block). You can configure the adders to take the sum or difference of two multiplier outputs. Summation or subtraction has to be selected at compile time. The two-multiplier adder function is useful for applications such as FFTs, complex FIR, and IIR filters. Figure 4-11 shows the DSP block configured in the two-multiplier adder mode. Figure 4-11. Two-Multiplier Adder Mode Shown for Half-DSP Block (Note 2) signa clock[3..0] ena[3..0] aclr[3..0] signb output_round output_saturate overflow (1) Output Register Bank + Round/Saturate dataa_1[17..0] Pipeline Register Bank datab_0[17..0] Input Register Bank dataa_0[17..0] result[ ] datab_1[17..0] Half-DSP Block Notes to Figure 4-11: (1) Block output for accumulator overflow and saturate overflow. (2) In a half-DSP block, you can implement 2 two-multiplier adders. The loopback mode is a sub-feature of the two-multiplier adder mode. Figure 4-12 shows the DSP block configured in the loopback mode. This mode takes the 36-bit summation result of the two multipliers and feeds back the most significant 18-bits to the input. The lower 18-bits are discarded. You have the option to disable or zero-out the loopback data with the dynamic zero_loopback signal. A logic 1 value on the zero_loopback signal selects the zeroed data or disables the looped back data, while a logic 0 selects the looped back data. 1 The option to use the loopback mode or the general two-multiplier adder mode must be selected at compile time. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 4: DSP Blocks in Arria II GX Devices Operational Mode Descriptions 4-21 Figure 4-12. Loopback Mode for Half-DSP Block clock[3..0] ena[3..0] aclr[3..0] signa signb output_round output_saturate zero_loopback overflow (1) Output Register Bank dataa_1[17..0] + Round/Saturate datab_0[17..0] Pipeline Register Bank loopback Input Register Bank dataa_0[17..0] result[ ] datab_1[17..0] Half-DSP Block Note to Figure 4-12: (1) Block output for accumulator overflow and saturate overflow. For two-multiplier adder mode, if all the inputs are full 18-bit and unsigned, the result requires 37 bits. As the output data width in two-multiplier adder mode is limited to 36 bits, this 37-bit output requirement is not allowed. Any other combination that does not violate the 36-bit maximum result is permitted; for example, two 16 x 16 signed two-multiplier adders is valid. 1 Two-multiplier adder mode supports the round and saturation logic unit. You can use pipeline registers and output registers in the DSP block to pipeline the multiplier-adder result, increasing the performance of the DSP block. 18 x 18 Complex Multiply You can configure the DSP block to implement complex multipliers using the two-multiplier adder mode. A single-half DSP block can implement one 18-bit complex multiplier. A complex multiplication can be written as shown in Equation 4-4. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 4-22 Chapter 4: DSP Blocks in Arria II GX Devices Operational Mode Descriptions Equation 4-4. Complex Multiplication Equation (a + jb) x (c + jd) = ((a x c)) - (b x d)) + j((a x d) + (b x c)) To implement this complex multiplication in the DSP block, the real part ((a x c) - (b x d)) is implemented using two multipliers feeding one subtractor block while the imaginary part ((a x d) + (b x c)) is implemented using another two multipliers feeding an adder block. This mode automatically assumes all inputs are using signed numbers. Four-Multiplier Adder In the four-multiplier adder configuration shown in Figure 4-13, the DSP block can implement 2 four-multiplier adders (1 four-multiplier adder per half DSP block). These modes are useful for implementing one-dimensional and two-dimensional filtering applications. The four-multiplier adder is performed in two addition stages. The outputs of two of the four multipliers are initially summed in the two first-stage adder blocks. The results of these two adder blocks are then summed in the second-stage adder block to produce the final four-multiplier adder result, as shown in Equation 4-2 on page 4-3 and Equation 4-3 on page 4-4. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 4: DSP Blocks in Arria II GX Devices Operational Mode Descriptions 4-23 Figure 4-13. Four-Multiplier Adder Mode Shown for Half-DSP Block signa signb output_round output_saturate clock[3..0] ena[3..0] aclr[3..0] overflow (1) dataa_0[ ] datab_0[ ] + dataa_2[ ] + Output Register Bank datab_1[ ] Round/Saturate Input Register Bank Pipeline Register Bank dataa_1[ ] result[ ] datab_2[ ] + dataa_3[ ] datab_3[ ] Half-DSP Block Note to Figure 4-13: (1) Block output for accumulator overflow and saturate overflow. High-Precision Multiplier Adder Mode In the high-precision multiplier adder, the DSP block can implement 2 two-multiplier adders, with multiplier precision of 18 x 36 (one two-multiplier adder per DSP half block). This mode is useful in filtering or fast Fourier transform (FFT) applications where a data path greater than 18 bits is required, yet 18 bits is sufficient for coefficient precision. This can occur in cases where that data has a high dynamic range. If the coefficients are fixed, as in FFT and most filter applications, the precision of 18 bits provides a dynamic range over 100 dB, if the largest coefficient is normalized to the maximum 18-bit representation. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 4-24 Chapter 4: DSP Blocks in Arria II GX Devices Operational Mode Descriptions In these situations, the data path can be up to 36 bits, allowing sufficient capacity for bit growth or gain changes in the signal source without loss of precision, which is useful in single precision block floating point applications. As shown in Figure 4-14, the high-precision multiplier is performed in two stages. The sum of the results of the two adders produce the final result: Z[54..0] = P 0[53..0] + P1[53..0] where: P0 = A[17..0] x B[35..0] and P1 = C[17..0] x D[35..0] Figure 4-14. High-Precision Multiplier Adder Configuration for Half-DSP Block signa signb clock[3..0] ena[3..0] aclr[3..0] overflow (1) dataA[0:17] dataB[0:17] dataC[0:17] Pipeline Register Bank Input Register Bank dataB[18:35] P0 <<18 + Output Register Bank + dataA[0:17] result[ ] dataD[0:17] + P1 dataC[0:17] <<18 dataD[18:35] Half-DSP Block Note to Figure 4-14: (1) Block output for accumulator overflow and saturate overflow. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 4: DSP Blocks in Arria II GX Devices Operational Mode Descriptions 4-25 Multiply Accumulate Mode In multiply accumulate mode, the second-stage adder is configured as a 44-bit accumulator or subtractor. The output of the DSP block is looped back to the second-stage adder and added or subtracted with the two outputs of the first-stage adder block according to Equation 4-3 on page 4-4. Figure 4-15 shows the DSP block configured to operate in multiply accumulate mode. Figure 4-15. Multiply Accumulate Mode Shown for Half-DSP Block clock[3..0] ena[3..0] aclr[3..0] signa signb output_round output_saturate chainout_sat_overflow (1) accum_sload dataa_0[ ] datab_0[ ] + Output Register Bank dataa_2[ ] + Round/Saturate datab_1[ ] Second Register Bank Input Register Bank Pipeline Register Bank dataa_1[ ] 44 result[ ] datab_2[ ] + dataa_3[ ] datab_3[ ] Half-DSP Block Note to Figure 4-15: (1) Block output for saturation overflow of chainout. A single DSP block can implement up to two independent 44-bit accumulators. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 4-26 Chapter 4: DSP Blocks in Arria II GX Devices Operational Mode Descriptions The dynamic accum_sload control signal is used to clear the accumulation. A logic 1 value on the accum_sload signal synchronously loads the accumulator with the multiplier result only, while a logic 0 enables accumulation by adding or subtracting the output of the DSP block (accumulator feedback) to the output of the multiplier and first-stage adder. 1 The control signal for the accumulator and subtractor is static and therefore has to be configured at compile time. This mode supports the round and saturation logic unit as it is configured as an 18-bit multiplier accumulator. Shift Modes Arria II GX devices support the following shift modes for 32-bit input only: 1 Arithmetic shift left, ASL[N] Arithmetic shift right, ASR[32-N] Logical shift left, LSL[N] Logical shift right, LSR[32-N] 32-bit rotator or Barrel shifter, ROT[N] You can switch the shift mode between these modes using the dynamic rotate and shift control signals. Shift mode in an Arria II GX device can be easily used by a soft embedded processor such as the Nios(R) II processor to perform the dynamic shift and rotate operation. Figure 4-16 shows the shift mode configuration. Shift mode makes use of the available multipliers to logically or arithmetically shift left, right, or rotate the desired 32-bit data. The DSP block is configured like the independent 36-bit multiplier mode to perform the shift mode operations. The arithmetic shift right requires a signed input vector. During arithmetic shift right, the sign is extended to fill the MSB of the 32-bit vector. The logical shift right uses an unsigned input vector. During logical shift right, zeros are padded in the most significant bits shifting the 32-bit vector to the right. The barrel shifter uses an unsigned input vector and implements a rotation function on a 32-bit word length. Two control signals, rotate and shift_right, together with the signa and signb signals, determine the shifting operation. Examples of shift operations are shown in Table 4-5. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 4: DSP Blocks in Arria II GX Devices Operational Mode Descriptions 4-27 Figure 4-16. Shift Operation Mode Shown for Half-DSP Block signa signb rotate shift_right clock[3..0] ena[3..0] aclr[3..0] dataa_0[35..18] datab_0[35..18] + dataa_0[35..18] + Shift/Rotate datab_0[35..18] Output Register Bank Input Register Bank Pipeline Register Bank dataa_0[17..0] 32 result[ ] datab_0[17..0] + dataa_0[17..0] datab_0[17..0] Half-DSP Block Table 4-5. Examples of Shift Operations Example Signa Signb Shift Rotate A-input B-input Result Logical Shift Left LSL[N] Unsigned Unsigned 0 0 0xAABBCCDD 0x0000100 0xBBCCDD00 Logical Shift Right LSR[32-N] Unsigned Unsigned 1 0 0xAABBCCDD 0x0000100 0x000000AA Arithmetic Shift Left ASL[N] Signed Unsigned 0 0 0xAABBCCDD 0x0000100 0xBBCCDD00 Arithmetic Shift Right ASR[32-N] Signed Unsigned 1 0 0xAABBCCDD 0x0000100 0xFFFFFFAA Unsigned Unsigned 0 1 0xAABBCCDD 0x0000100 0xBBCCDDAA Rotation ROT[N] (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 4-28 Chapter 4: DSP Blocks in Arria II GX Devices Operational Mode Descriptions Rounding and Saturation Mode Round and saturation functions are often required in DSP arithmetic. Rounding is used to limit bit growth and its side effects; saturation is used to reduce overflow and underflow side effects. Two rounding modes are supported in Arria II GX devices: Round-to-nearest-integer mode Round-to-nearest-even mode You must select one of the two options at compile time. Round-to-nearest-integer provides the biased rounding support and is the simplest form of rounding commonly used in DSP arithmetic. The round-to-nearest-even method provides unbiased rounding support and is used where DC offsets are a concern. Table 4-6 shows how round-to-nearest-even works. Examples of the difference between the two modes are shown in Table 4-7. In this example, a 6-bit input is rounded to 4 bits. You can observe from Table 4-7 that the main difference between the two rounding options is when the residue bits are exactly half way between its nearest two integers and the LSB is zero (even). Table 4-6. Example of Round-To-Nearest-Even Mode 6- to 4-bits Rounding Odd/Even (Integer) Fractional Add to Integer Result 010111 x > 0.5 (11) 1 0110 001101 x < 0.5 (01) 0 0011 001010 Even (0010) = 0.5 (10) 0 0010 001110 Odd (0011) = 0.5 (10) 1 0100 110111 x > 0.5 (11) 1 1110 101101 x < 0.5 (01) 0 1011 110110 Odd (1101) = 0.5 (10) 1 1110 110010 Even (1100) = 0.5 (10) 0 1100 Table 4-7. Comparison of Round-to-Nearest-Integer and Round-to-Nearest-Even Arria II GX Device Handbook Volume 1 Round-To-Nearest-Integer Round-To-Nearest-Even 010111 0110 010111 0110 001101 0011 001101 0011 001010 0011 001010 0010 001110 0100 001110 0100 110111 1110 110111 1110 101101 1011 101101 1011 110110 1110 110110 1110 110010 1101 110010 1100 (c) February 2009 Altera Corporation Chapter 4: DSP Blocks in Arria II GX Devices Operational Mode Descriptions 4-29 Two saturation modes are supported in Arria II GX devices: Asymmetric saturation mode Symmetric saturation mode You must select one of the two options at compile time. In 2's complement format, the maximum negative number that can be represented is -2(n-1),while the maximum positive number is 2(n-1) - 1. Symmetrical saturation limits the maximum negative number to -2(n-1) + 1. For example, for 32 bits: Asymmetric 32-bit saturation: Max = 0x7FFFFFFF, Min = 0x80000000 Symmetric 32-bit saturation: Max = 0 x7FFFFFFF, Min = 0 x80000001 Table 4-8 shows how the saturation works. In this example, a 44-bit input is saturated to 36-bits. Table 4-8. Examples of Saturation 44 to 36 Bits Saturation Symmetric SAT Result Asymmetric SAT Result 5926AC01342h 7FFFFFFFFh 7FFFFFFFFh ADA38D2210h 800000001h 800000000h Arria II GX devices have up to 16 configurable bit positions out of the 44-bit bus ([43:0]) for the round and saturate logic unit providing higher flexibility. You must select the 16 configurable bit positions at compile time. These 16-bit positions are located at bits [21:6] for rounding and [43:28] for saturation, as shown in Figure 4-17. Figure 4-17. Round and Saturation Locations 16 User defined SAT Positions (bit 43-28) 43 42 29 28 1 0 16 User defined RND Positions (bit 21-6) 43 42 1 (c) February 2009 21 20 7 6 0 For symmetric saturation, the RND bit position is also used to determine where the LSP for the saturated data is located. Altera Corporation Arria II GX Device Handbook Volume 1 4-30 Chapter 4: DSP Blocks in Arria II GX Devices Operational Mode Descriptions You can use the rounding and saturation function as described in regular supported multiplication operations shown in Table 4-2 on page 4-5. However, for accumulation type operations, the following convention is used. The functionality of the round logic unit is in the format of: Result = RND[ (A x B)], when used for an accumulation type of operation. Likewise, the functionality of the saturation logic unit is in the format of: Result = SAT[ (A x B)], when used for an accumulation type of operation. If both the round and saturation logic units are used for an accumulation type of operation, the format is: Result = SAT[RND[ (A x B)]] DSP Block Control Signals The Arria II GX DSP block is configured using a set of static and dynamic signals. At run time, you can configure the DSP block dynamic signals to toggled or not. Table 4-9 and Table 4-10 show a list of dynamic signals for the DSP block. Table 4-9. DSP Block Dynamic Signals per Half-DSP Block (Part 1 of 2) Signal Name Function Count signa Signed/unsigned control for all multipliers and adders. signb signa for "multiplicand" input bus to dataa[17:0] each multiplier. 2 signb for "multiplier" input bus datab[17:0] to each multiplier. signa = 1, signb = 1 for signed-signed multiplication signa = 1, signb = 0 for signed-unsigned multiplication signa = 0, signb = 1 for unsigned-signed multiplication signa = 0, signb = 0 for unsigned-unsigned multiplication output_round Round control for first stage round/saturation block. output_round = 1 for rounding on multiply output 1 output_round = 0 for normal multiply output chainout_round Round control for second stage round/saturation block. chainout_round = 1 for rounding on multiply output 1 chainout_round = 0 for normal multiply output output_saturate Saturation control for first stage round/saturation block for Q-format multiply. If both rounding and saturation is enabled, saturation is done on the rounded result. 1 output_saturate = 1 for saturation support output_saturate = 0 for no saturation support chainout_saturate Saturation control for second stage round/saturation block for Q-format multiply. If both rounding and saturation's enabled, saturation is done on the rounded result. 1 chainout_saturate = 1 for saturation support chainout_saturate = 0 for no saturation support Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 4: DSP Blocks in Arria II GX Devices Software Support for Arria II GX Devices 4-31 Table 4-9. DSP Block Dynamic Signals per Half-DSP Block (Part 2 of 2) Signal Name Function Count Dynamically specifies whether the accumulator value is zero. accum_sload = 0, accumulation input is from the output registers accum_sload 1 accum_sload = 1, accumulation input is set to be zero zero_chainout Dynamically specifies whether the chainout value is zero. 1 zero_loopback Dynamically specifies whether the loopback value is zero. 1 rotate rotation = 1, rotation feature is enabled 1 shift_right shift_right = 1, shift right feature is enabled 1 Total Signals per Half-block 11 -- Table 4-10. DSP Block Dynamic Signals per Full-DSP Block Signal Name Function clock0 Count DSP-block-wide clock signals 4 Input and Pipeline Register enable signals 4 DSP block-wide asynchronous clear signals (active low). 4 Total Count per Full Block 34 clock1 clock2 clock3 ena0 ena1 ena2 ena3 aclr0 aclr1 aclr2 aclr3 -- Software Support for Arria II GX Devices Altera provides two distinct methods for implementing various modes of the DSP block in a design: instantiation and inference. Both methods use the following Quartus II megafunctions: LPM_MULT ALTMULT_ADD ALTMULT_ACCUM ALTFP_MULT You can instantiate the megafunctions in the Quartus II software to use the DSP block. Alternatively, with inference, you can create an HDL design and synthesize it using a third-party synthesis tool (such as LeonardoSpectrum, Synplify, or Quartus II Native Synthesis) that infers the appropriate megafunction by recognizing multipliers, multiplier adders, multiplier accumulators, and shift functions. Using either method, the Quartus II software maps the functionality to the DSP blocks during compilation. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 4-32 Chapter 4: DSP Blocks in Arria II GX Devices Document Revision History f Refer to the Quartus II Software Help for instructions about using the megafunctions and the MegaWizard Plug-In Manager. f For more information, refer to Section III: Synthesis in volume 1 of the Quartus II Handbook. Document Revision History Table 4-11 shows the revision history for this chapter. Table 4-11. Document Revision History Date and Document Version February 2009, v1.0 Changes Made Summary of Changes Initial Release. Arria II GX Device Handbook Volume 1 -- (c) February 2009 Altera Corporation 5. Clock Networks and PLLs in Arria II GX Devices AIIGX51005-1.0 Introduction Arria(R) II GX devices provide a hierarchical clock structure and multiple PLLs with advanced features. Arria II GX devices provide dedicated global clock networks (GCLKs), regional clock networks (RCLKs), and periphery clock networks (PCLKs). This chapter contains the following sections: "Clock Networks in Arria II GX Devices" on page 5-1 "PLLs in Arria II GX Devices" on page 5-14 Clock Networks in Arria II GX Devices The GCLKs, RCLKs, and PCLKs available in Arria II GX devices are organized into hierarchical clock structures that provide up to 148 unique clock domains (16 GCLK + 48 RCLK + 84 PCLK) in the Arria II GX device and allows up to 52 unique GCLK, RCLK, and PCLK clock sources (16 GCLK + 12 RCLK + 24 PCLK) per device quadrant. Table 5-1 shows the clock resources available in Arria II GX devices. Table 5-1. Clock Resources in Arria II GX Devices Number of Resources Available Clock Resource Clock input pins 12 Single-ended (6 Differential) Source of Clock Resource CLK[4..15] DIFFCLK_[0..5]p/n pins Global clock networks 16 CLK[4..15] pins, PLL clock outputs, PLD-transceiver interface clocks, and logic array Regional clock networks 48 CLK[4..15] pins, PLL clock outputs, PLD-transceiver interface clocks, and logic array Periphery clock networks 84 (24 per device quadrant) (1) DPA clock outputs, PLD-transceiver interface clocks, horizontal I/O pins, and logic array GCLKs/RCLKs per quadrant 28 16 GCLKs + 12 RCLKs GCLKs/RCLKs per device 64 16 GCLKs + 48 RCLKs Note to Table 5-1: (1) There are 33 PCLKs in the EP2AGX20 and EP2AGX30 devices, where 9 are on the left side and 24 on the right side. There are 50 PCLKs in the EP2AGX45 and EP2AGX65 devices, where 18 are on the left side and 32 on the right side. There are 59 PCLKs in the EP2AGX95 and EP2AGX125 device, where 27 are on the left side and 32 on the right side. There are 84 PCLKS in the EP2AGX190 and EP2AGX260 devices, where 36 are on the left side and 48 on the right side. Arria II GX devices have up to 12 dedicated single-ended clock pins or 6 dedicated differential clock pins (DIFFCLK_[0..5]p and DIFFCLK_[0..5]n) that can drive either the GCLK or RCLK networks. These clock pins are arranged on the three sides (top, bottom, and right sides) of the Arria II GX device, as shown in Figure 5-1 and Figure 5-2. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 5-2 Chapter 5: Clock Networks and PLLs in Arria II GX Devices Clock Networks in Arria II GX Devices Global Clock Networks Arria II GX devices provide up to 16 GCLKs that can drive throughout the entire device, serving as low-skew clock sources for functional blocks like adaptive logic modules (ALMs), digital signal processing (DSP) blocks, embedded memory blocks, and PLLs. Arria II GX I/O elements (IOEs) and internal logic can also drive GCLKs to create internally generated global clocks and other high fan-out control signals; for example, synchronous or asynchronous clears and clock enables. Figure 5-1 shows CLK pins and PLLs that can drive GCLK networks in Arria II GX devices. Figure 5-1. Global Clock Networks CLK[12..15] Top Left PLL Top Right PLL PLL_1 PLL_2 GCLK[12..15] GCLK[0..3] (2) GCLK[8..11] PLL_5 (1) PLL_6 (1) Center PLLs CLK[8..11] GCLK[4..7] PLL_4 PLL_3 CLK[4..7] Bottom Left PLL Bottom Right PLL Notes to Figure 5-1: (1) PLL_5 and PLL_6 are only available in EP2AGX95, EP2AGX125, EP2AGX190, and EP2AGX260 devices. (2) Because there are no dedicated clock pins on the left side of an Arria II GX device, GCLK[0..3] are not driven by any clock pins. Regional Clock Networks The regional clock (RCLK) networks only pertain to the quadrant they drive into. Arria II GX devices contain 48 RCLK networks that provide the lowest clock delay and skew for logic contained in a single device quadrant. Arria II GX I/O elements and internal logic in a given quadrant can also drive RCLKs to create internally generated regional clocks and other high fan-out control signals; for example, synchronous or asynchronous clears and clock enables. Figure 5-2 shows CLK pins and PLLs that can drive RCLK networks in Arria II GX devices. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 5: Clock Networks and PLLs in Arria II GX Devices Clock Networks in Arria II GX Devices 5-3 Figure 5-2. Regional Clock Networks in Arria II GX Devices Top Left PLL CLK[12..15] Top Right PLL PLL_1 PLL_2 RCLK[42..47] RCLK[36..41] RCLK[30..35] RCLK[0..5] (2) Q1 Q2 PLL_5 (1) Q4 Q3 PLL_6 RCLK[6..11] (2) Center PLLs CLK[8..11] RCLK[24..29] RCLK[12..17] RCLK[18..23] PLL_4 Bottom Left PLL (1) PLL_3 CLK[4..7] Bottom Right PLL Notes to Figure 5-2: (1) PLL_5 and PLL_6 are only available in EP2AGX95, EP2AGX125, EP2AGX190, and EP2AGX260 devices. (2) RCLK[0..11] is not driven by any clock pins because there are no dedicated clock pins on the left side of the Arria II GX devices. Periphery Clock Networks Periphery clock (PCLK) networks are a collection of individual clock networks driven from the periphery of the Arria II GX device. Clock outputs from the DPA block, PLD-transceiver interface clocks, horizontal I/O pins, and internal logic can drive the PCLK networks. The EP2AGX20 and EP2AGX30 devices contain 33 PCLKs; the EP2AGX45 and EP2AGX65 devices contain 50 PCLKs; the EP2AGX95 and EP2AGX125 devices contain 59 PCLKs; the EP2AGX190 and EP2AGX260 devices contain 84 PCLKs. These PCLKs have higher skew compared to GCLK and RCLK networks and can be used instead of general purpose routing to drive signals into the Arria II GX device. 1 (c) February 2009 The legal clock sources for PCLK networks are clock outputs from the DPA block, PLD-transceiver interface clocks, horizontal I/O pins, and internal logic. Altera Corporation Arria II GX Device Handbook Volume 1 5-4 Chapter 5: Clock Networks and PLLs in Arria II GX Devices Clock Networks in Arria II GX Devices Clocking Regions Arria II GX devices provide up to 64 distinct clock domains (16 GCLKs + 48 RCLKs) in the entire device. You can use these clock resources to form the following four different types of clock regions: Entire device clock region Regional clock region Dual-regional clock region Sub-regional clock region (only available in the EP2AGX190 and EP2AGX260 devices) To form the entire device clock region, a source (not necessarily a clock signal) drives a global clock network that can be routed through the entire device. This clock region has a higher skew compared to other clock regions, but allows the signal to reach every destination in the device. This is a good option for routing global reset/clear signals or routing clocks throughout the device. To form a regional clock region, a source drives a single-quadrant of the device. This clock region provides the lowest skew in a quadrant and is a good option if all destinations are in a single device quadrant. To form a dual-regional clock region, a single source (a clock pin or PLL output) generates a dual-regional clock by driving two regional clock networks (one from each quadrant). This technique allows destinations across two device quadrants to use the same low-skew clock. The routing of this signal on an entire side has approximately the same delay as in a regional clock region. Internal logic can also drive a dual-regional clock network. Corner PLL outputs generate a dual-regional clock network through clock multiplexers that serve the two immediate quadrants of the device. Figure 5-3 shows the dual-regional clock region. Figure 5-3. Arria II GX Device Dual-Regional Clock Region Regional clock multiplexers PLL_1 PLL_2 PLL_4 PLL_3 Arria II GX Device Handbook Volume 1 Clock pins or PLL outputs can drive half of the device to create side-wide clocking regions for improved interface timing. (c) February 2009 Altera Corporation Chapter 5: Clock Networks and PLLs in Arria II GX Devices Clock Networks in Arria II GX Devices 5-5 The sub-regional clock scheme allows the formation of independent sub-regional clock regions for optimal and efficient use of global and regional clock resources. You can partition the device into a maximum of 16 sub-regional clock regions. Each region is driven by a global or regional clock or by an adjacent ALM. This technique allows the formation of optimally sized synchronous clock regions for the best utilization of clock network resources. Figure 5-4, Figure 5-5, and Figure 5-6 show that you can divide the device into 16, 8, or 12 independent sub-regions. Figure 5-4. Sixteen Independent Sub-Regional Clock Regions (Note 1) Note to Figure 5-4: (1) The sub-regional clock region is only applicable to the EP2AGX190 and EP2AGX260 devices. Figure 5-5. Eight Independent Sub-Regional + One Dual-Regional Clock Region (Note 1) Note to Figure 5-5: (1) The sub-regional clock region is only applicable to the EP2AGX190 and EP2AGX260 devices. Figure 5-6. Twelve Independent Sub-Regional + One Regional Clock Region (Note 1) Note to Figure 5-6: (1) The sub-regional clock region is only applicable to the EP2AGX190 and EP2AGX260 devices. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 5-6 Chapter 5: Clock Networks and PLLs in Arria II GX Devices Clock Networks in Arria II GX Devices Clock Network Sources In Arria II GX devices, clock input pins, internal logic, transceiver clocks, and PLL outputs can drive the global and regional clock networks. See Table 5-2 to Table 5-3 for the connectivity between dedicated CLK[4..15] pins and the global and regional clock networks. Dedicated Clock Inputs Pins The CLK pins can either be differential clocks or single-ended clocks. Arria II GX devices supports 6 differential clock inputs or 12 single-ended clock inputs. You can also use the dedicated clock input pins CLK[4..15] for high fan-out control signals such as asynchronous clears, presets, and clock enables for protocol signals such as TRDY and IRDY for PCI through global or regional clock networks. Logic Array Blocks (LABs) You can drive up to four signals into each global and regional clock network using LAB-routing to enable internal logic to drive a high fan-out, low-skew signal. 1 Arria II GX PLLs cannot be driven by internally generated GCLKs or RCLKs. The input clock to the PLL has to come from dedicated clock input pins or pin/PLL-fed GCLKs or RCLKs only. PLL Clock Outputs Arria II GX PLLs can drive both GCLK and RCLK networks, as shown in Table 5-5 and Table 5-6. Table 5-2 shows the connection between the dedicated clock input pins and GCLKs. Table 5-2. Clock Input Pin Connectivity to Global Clock Networks CLK (Pins) Clock Resources 4 5 6 7 8 9 10 11 12 13 14 15 GCLK[0..3] (1) -- -- -- -- -- -- -- -- -- -- -- -- GCLK[4..7] v v v v -- -- -- -- -- -- -- -- GCLK[8..11] -- -- -- -- v v v v -- -- -- -- GCLK[12..15] -- -- -- -- -- -- -- -- v v v v Note to Table 5-2: (1) GCLK[0..3] is not driven by any clock pins because there are no dedicated clock pins on the left side of the Arria II GX devices. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 5: Clock Networks and PLLs in Arria II GX Devices Clock Networks in Arria II GX Devices 5-7 Table 5-3 shows the connectivity between the dedicated clock input pins and RCLKs in devices. A given clock input pin can drive two adjacent regional clock networks to create a dual-regional clock network. Table 5-3. Clock Input Pin Connectivity to Regional Clock Networks CLK (Pins) Clock Resource 4 5 6 7 8 9 10 11 RCLK [12, 14, 16, 18, 20, 22] v -- v -- -- -- -- -- RCLK [13, 15, 17, 19, 21, 23] -- v -- v -- -- -- -- RCLK [24..35] -- -- -- -- v v v RCLK [36, 38, 40, 42, 44, 46] -- -- -- -- -- -- RCLK [37, 39, 41, 43, 45, 47] -- -- -- -- -- -- 12 13 14 15 -- -- -- -- -- -- -- v -- -- -- -- -- -- v -- v -- -- -- -- v -- v Clock Input Connections to PLLs Dedicated clock input pin connectivity to Arria II GX PLLs is shown in Table 5-4. Table 5-4. Arria II GX Device PLLs and PLL Clock Pin Drivers Dedicated Clock Input Pin (CLK pins) (Note 1) PLL Number 1 2 3 4 5 6 CLK[4..7] -- -- v v -- -- CLK[8..11] -- v v -- v v CLK[12..15] v v -- -- -- -- Note to Table 5-4: (1) PLL_5 and PLL_6 are connected directly to CLK[8..11]. PLL_1, PLL_2, PLL_3 and PLL_4 are driven by the clock input pins through a 4:1 multiplexer. Clock Output Connections PLLs in Arria II GX devices can drive up to 24 regional clock networks and 8 global clock networks. Refer to Table 5-5 for Arria II GX PLL connectivity to GCLK networks. The Quartus II(R) software automatically assigns PLL clock outputs to regional or global clock networks. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 5-8 Chapter 5: Clock Networks and PLLs in Arria II GX Devices Clock Networks in Arria II GX Devices Table 5-5 shows how the PLL clock outputs connect to GCLK networks. Table 5-5. Arria II GX PLL Connectivity to GCLKs PLL Number Clock Network 1 2 3 4 5 6 GCLK[0..3] v -- -- v -- -- GCLK[4..7] -- -- v v -- -- GCLK[8..11] -- v v -- v v GCLK[12..15] v v -- -- -- -- Table 5-6 shows how the PLL clock outputs connect to RCLK networks. Table 5-6. Arria II GX Regional Clock Outputs From PLLs PLL Number Clock Resource 1 2 3 4 5 6 RCLK[0..11] v -- -- v -- -- RCLK[12..23] -- -- v v -- -- RCLK[24..35] -- v v -- v v RCLK[36..47] v v -- -- -- -- Clock Control Block Every global and regional clock network has its own clock control block. The control block provides the following features: Clock source selection (dynamic selection for global clocks) Global clock multiplexing Clock power down (static or dynamic clock enable or disable) Figure 5-7 and Figure 5-8 show the global clock and regional clock select blocks, respectively. Select the clock source for the global clock select block either statically or dynamically. You can either statically select the clock source using a setting in the Quartus II software, or you can dynamically select the clock source using internal logic to drive the multiplexer select inputs. When selecting the clock source dynamically, you can either select two PLL outputs (such as C0 or C1), or a combination of clock pins or PLL outputs. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 5: Clock Networks and PLLs in Arria II GX Devices Clock Networks in Arria II GX Devices 5-9 Figure 5-7. Arria II GX Global Clock Control Block CLK Pin PLL Counter Outputs (3) CLKSELECT[1..0] (1) 2 2 CLK Pin Inter-Transceiver Block Clock Lines (4) Internal Logic 2 Static Clock Select (2) This multiplexer supports user-controllable dynamic switching Enable/ Disable Internal Logic GCLK Notes to Figure 5-7: (1) These clock select signals can only be dynamically controlled through internal logic when the device is operating in user mode. (2) These clock select signals can only be set through a configuration file (.sof or .pof) and cannot be dynamically controlled during user mode operation. (3) The left side of the Arria II GX device only allows PLL counter outputs as the dynamic clock source selection to the global clock network. (4) This is only available on the left side of the Arria II GX device. The mapping between input clock pins, PLL counter outputs, and clock control block inputs is shown in Table 5-7. Table 5-7. Mapping between Input Clock Pins, PLL Counter Outputs, and Clock Control Block Inputs Clock Control Block Inputs Description inclk[0], inclk[1] (1) Can be fed by any of the 4 dedicated clock pins on the same side inclk[2] Can be fed by PLL counters C0 and C2 from the two corner PLLs on the same side of the Arria II GX device inclk[3] Can be fed by PLL counters C1 and C3 from the two corner PLLs on the same side of the Arria II GX device Note to Table 5-7: (1) The left side of the Arria II GX device only allows PLL counter outputs as the dynamic clock source selection to the global clock network. Hence, inclk[0] can be fed by PLL counters C4 or C6 while inclk[1] can only be fed by PLL counter C5. (c) February 2009 1 When combining the PLL outputs and clock pins in the same clock control block, you need to ensure that these clock sources are implemented on the same side of the device. f For all possible legal inclk sources for each global and regional clock network, refer to Table 5-2 on page 5-6 through Table 5-6 on page 5-8. Altera Corporation Arria II GX Device Handbook Volume 1 5-10 Chapter 5: Clock Networks and PLLs in Arria II GX Devices Clock Networks in Arria II GX Devices Figure 5-8. Regional Clock Control Block CLK Pin PLL Counter Outputs 2 Internal Logic Static Clock Select (1) Enable/ Disable Internal Logic RCLK Note to Figure 5-8: (1) This clock select signal can only be statically controlled through a configuration file (.sof or .pof) and cannot be dynamically controlled during user mode operation. The clock source selection for the regional clock select block can only be controlled statically using configuration bit settings in the configuration file (.sof or .pof) generated by the Quartus II software. The Arria II GX clock networks can be powered down by both static and dynamic approaches. When a clock net is powered down, all the logic fed by the clock net is in an off-state, thereby reducing the overall power consumption of the device. The unused global and regional clock networks are automatically powered down through configuration bit settings in the configuration file (.sof or .pof) generated by the Quartus II software. The dynamic clock enable or disable feature allows the internal logic to control power-up or power-down synchronously on GCLK and RCLK networks, including dual-regional clock regions. This function is independent of the PLL and is applied directly on the clock network, as shown in Figure 5-7 and Figure 5-8. You can set the input clock sources and the clkena signals for the global and regional clock network multiplexers through the Quartus II software using the ALTCLKCTRL megafunction. You can also enable or disable the dedicated external clock output pins using the ALTCLKCTRL megafunction. Figure 5-9 shows the external PLL output clock control block. 1 When using the ALTCLKCTRL megafunction to implement dynamic clock source selection in the Arria II GX devices, the inputs from the clock pins, except for the left side of device, feed the inclk[0..1] ports of the multiplexer, while the PLL outputs feed the inclk[2..3] ports. You can choose from among these inputs using the CLKSELECT[1..0] signal. Refer to Table 5-7 for the connections between the PLL counter outputs to the clock control block on the left side of the Arria II GX device. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 5: Clock Networks and PLLs in Arria II GX Devices Clock Networks in Arria II GX Devices 5-11 Figure 5-9. Arria II GX External PLL Output Clock Control Block PLL Counter Outputs and m Counter 8 Static Clock Select (1) Enable/ Disable Internal Logic IOE (2) Internal Logic Static Clock Select (1) PLL<#>_CLKOUT pin Notes to Figure 5-9: (1) This clock select signal can only be set through a configuration file (.sof or .pof) and cannot be dynamically controlled during user mode operation. (2) The clock control block feeds to a multiplexer in the PLL<#>_CLKOUT pin's IOE. The PLL<#>_CLKOUT pin is a dual-purpose pin. Therefore, this multiplexer selects either an internal signal or the output of the clock control block. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 5-12 Chapter 5: Clock Networks and PLLs in Arria II GX Devices Clock Networks in Arria II GX Devices Clock Enable Signals Figure 5-10 shows how the clock enable/disable circuit of the clock control block is implemented in Arria II GX devices. Figure 5-10. clkena Implementation (1) (1) clkena output of clock select multiplexer Q D R1 (2) Q D R2 GCLK/ RCLK/ PLL_<#>_CLKOUT (1) Notes to Figure 5-10: (1) The R1 and R2 bypass paths are not available for PLL external clock outputs. (2) The select line is statically controlled by a bit setting in the configuration file (.sof or .pof). In Arria II GX devices, the clkena signals are supported at the clock network level instead of at the PLL output counter level. This allows you to gate off the clock even when a PLL is not being used. You can also use the clkena signals to control the dedicated external clocks from the PLLs. Figure 5-11 shows the waveform example for a clock output enable. The clkena signal is synchronous to the falling edge of the clock output. Arria II GX devices also have an additional metastability register that aids in asynchronous enable/disable of the GCLK/RCLK networks. This register can be optionally bypassed in the Quartus II software. Figure 5-11. clkena Signals output of clock select multiplexer clkena output of AND gate with R2 bypassed output of AND gate with R2 not bypassed Note to Figure 5-11: (1) You can use the clkena signals to enable or disable the global and regional networks or the PLL<#>_CLKOUT pins. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 5: Clock Networks and PLLs in Arria II GX Devices Clock Networks in Arria II GX Devices 5-13 The PLL can remain locked independent of the clkena signals because the loop-related counters are not affected. This feature is useful for applications that require a low power or sleep mode. The clkena signal can also disable clock outputs if the system is not tolerant of frequency over-shoot during resynchronization. Clock Source Control for PLLs The clock input to Arria II GX PLLs comes from clock input multiplexers. The clock multiplexer inputs come from dedicated clock input pins, PLLs through the GCLK and RCLK networks, or from dedicated connections between adjacent corner and center PLLs. The clock input sources to corner (PLL_1, PLL_2, PLL_3, PLL_4) and center PLLs (PLL_5 and PLL_6) are shown in Figure 5-12. The multiplexer select lines are set in the configuration file (SRAM object file [.sof] or programmer object file [.pof]) only. Once configured, this block cannot be changed without loading a new.sof or .pof. The Quartus II software automatically sets the multiplexer select signals depending on the clock sources selected in your design. f For more information on the clock control block and its supported features in the Quartus II software, refer to the ALTCLKCTRL Megafunction User Guide. Figure 5-12. Clock Input Multiplexer Logic for Arria II GX PLLs (1) CLK[n+3..n] (2) GCLK / RCLK input (3) 4 inclk0 To the clock switchover block Adjacent PLL output (1) 4 inclk1 Notes to Figure 5-12: (1) The input clock multiplexing is controlled through a configuration file (.sof or .pof) only and cannot be dynamically controlled in user mode operation. (2) Dedicated clock input pins to PLLs. n=4 for PLL_4; n=4 or 8 for PLL_3; and n=8 or 12 for PLL_2; and n=12 for PLL_1. (3) The global (GCLK) or regional (RCLK) clock input can be driven by an output from another PLL, a pin-driven global or regional clock, or through a clock control block provided the clock control block is fed by an output from another PLL or a pin-driven dedicated global or regional clock. An internally generated global signal or general purpose I/O pin cannot drive the PLL. Cascading PLLs The corner and center PLLs can be cascaded through the GCLK/RCLK networks. In addition, where two PLLs exist next to each other, there is a direct connection between them that does not require the GCLK/RCLK network. Using this path reduces clock jitter when cascading PLLs. The direct PLL cascading feature is available in PLL_5 and PLL_6 on the right side of the EP2AGX95, EP2AGX125, EP2AGX190, and EP2AGX260 devices. Arria II GX devices allow cascading of PLL_1 and PLL_4 to transceiver PLLs (CMU PLLs and receiver CDRs). (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 5-14 Chapter 5: Clock Networks and PLLs in Arria II GX Devices PLLs in Arria II GX Devices f For more information, refer to the "FPGA Fabric PLLs -Transceiver PLLs Cascading" section in the Arria II GX Transceiver Clocking chapter in volume 2 of the Arria II GX Device Handbook. PLLs in Arria II GX Devices Arria II GX devices offer up to 6 PLLs per device and 7 outputs per PLL that provide robust clock management and synthesis for device clock management, external system clock management, and high-speed I/O interfaces. The nomenclature for the PLLs follows their geographical location in the device floor plan. Refer to Figure 5-1 and Figure 5-2 for the location and number of PLLs in Arria II GX devices. 1 f Depending on package, Arria II GX devices offer up to 8 transceiver TX PLLs per device that can be used by the FPGA fabric if they are not being used by the transceiver. For more details on the number of general-purpose and transceiver TX PLLs in each device density, refer to the Arria II GX Device Family Overview chapter in volume 1 of the Arria II GX Device Handbook. For more information on the usage of the transceiver TX PLLs in the transceiver block, refer to the Arria II GX Transceiver Clocking chapter in volume 2 of the Arria II GX Device Handbook. All Arria II GX PLLs have the same core analog structure and support features. Table 5-8 highlights the features of PLLs in Arria II GX devices. Table 5-8. Arria II GX PLL Features (Part 1 of 2) Feature Arria II GX PLLs C (output) counters 7 M, N, C counter sizes 1 to 512 Dedicated clock outputs (1) 1 single-ended or 1 differential pair 3 single-ended or 3 differential pairs (2) Clock input pins 4 single-ended or 2 differential pin pairs External feedback input pin No Spread-spectrum input clock tracking Yes (3) PLL cascading Through GCLK and RCLK and dedicated path between adjacent PLLs. Cascading between the general-purpose PLL and transceiver PLL is supported in PLL_1 and PLL_4. Compensation modes All except external feedback mode when using differential I/Os PLL drives DIFFCLK and LOADEN Yes VCO output drives DPA clock Yes Phase shift resolution Down to 96.125 ps (4) Programmable duty cycle Yes Output counter cascading Yes Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 5: Clock Networks and PLLs in Arria II GX Devices PLLs in Arria II GX Devices 5-15 Table 5-8. Arria II GX PLL Features (Part 2 of 2) Feature Arria II GX PLLs Input clock switchover Yes Notes to Table 5-8: (1) PLL_5 and PLL_6 do not have dedicated clock outputs. (2) The same PLL clock output drives 3 single-ended or 3 differential I/O pairs. This is only supported in PLL_1 and PLL_3 of the EP2AGX95, EP2AGX125, EP2AGX190, and EP2AGX260 devices. (3) This is applicable only if input clock jitter is in input jitter tolerance specifications. (4) The smallest phase shift is determined by the voltage-controlled oscillator (VCO) period divided by eight. For degree increments, the Arria II GX device can shift all output frequencies in increments of at least 45. Smaller degree increments are possible depending on the frequency and C counter value. Arria II GX PLL Hardware Overview Figure 5-13 shows a simplified block diagram of the major components of the Arria II GX PLL. Figure 5-13. Arria II GX PLL Block Diagram To DPA block on Left/Right PLLs Lock Circuit Dedicated clock inputs 4 /n inclk0 inclk1 GCLK/RCLK Clock Switchover Block PFD Casade output to adjacent PLL locked CP LF VCO 8 /2 (2) /2, /4 /C0 8 /C1 8 /C2 clkswitch clkbad0 clkbad1 activeclock /C3 Cascade input from adjacent PLL PLL Output Multiplexer pfdena /Cn (1) /m no compensation mode ZDB mode LVDS Compensation mode Source Synchronous, normal modes GCLKs RCLKs External clock outputs DIFFCLK from Right PLLs LOAD_EN from Right PLLs External memory interface DLL External clock outputs DIFFCLK network GCLK/RCLK network Notes to Figure 5-13: (1) There are 7 PLL output counters in Arria II GX devices. (2) This is the VCO post-scale counter K. 1 The global (GCLK) or regional (RCLK) clock input can be driven by an output from another PLL, a pin-driven global or regional clock, or through a clock control block, provided the clock control block is fed by an output from another PLL or a pin driven dedicated global or regional clock. An internally generated global signal or general purpose I/O pin cannot drive the PLL. PLL Clock I/O Pins Each PLL supports one of the following clock I/O pin configurations: (c) February 2009 1 single-ended I/O or 1 differential I/O pair. 3 single-ended I/O pairs or 3 differential I/O pairs (this is only supported in PLL_1 and PLL_3 of the EP2AGX95, EP2AGX125, EP2AGX190, and EP2AGX260 devices). Altera Corporation Arria II GX Device Handbook Volume 1 5-16 Chapter 5: Clock Networks and PLLs in Arria II GX Devices PLLs in Arria II GX Devices Figure 5-14 shows the clock I/O pins associated with Arria II GX PLLs. Figure 5-14. External Clock Outputs for Arria II GX PLLs Internal Logic C0 C1 C2 C3 Arria II GX PLLs C4 C5 C6 m clkena0 (3) PLL<#>_CLKOUT<#> (1), (2) Notes to Figure 5-14: (1) These clock output pins can be fed by any one of the C[6..0], m counters. (2) The PLL<#>_CLKOUT<#>p and PLL<#>_CLKOUT<#>n pins can be either single-ended or differential clock outputs. The Arria II GX PLL only routes single-ended I/Os to PLL<#>CLKOUT<#>p pins, while PLL<#>_CLKOUT<#>n pins can be used as user I/Os. (3) These external clock enable signals are available only when using the ALTCLKCTRL megafunction. Any of the output counters (C[6..0] or the M counter can feed the dedicated external clock outputs, as shown in Figure 5-15. Therefore, one counter or frequency can drive all output pins available from a given PLL. Each pin of a single-ended output pair can either be in-phase or 180-degrees out-of-phase. The Quartus II software places the NOT gate in your design into the IOE to implement 180 phase with respect to the other pin in the pair. The clock output pin pairs support the same I/O standards as standard output pins, as well as LVDS, LVPECL, differential HSTL, and differential SSTL. f To determine which I/O standards are supported by the PLL clock input and output pins, refer to the I/O Features in Arria II GX Devices chapter in volume 1 of the Arria II GX Device Handbook. Arria II GX PLLs can also drive out to any regular I/O pin through the global or regional clock network. You can also use the external clock output pins as user I/O pins if external PLL clocking is not needed. PLL Control Signals You can use the three signals, pfdena, areset, and locked, to observe and control the PLL operation and resynchronization. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 5: Clock Networks and PLLs in Arria II GX Devices PLLs in Arria II GX Devices 5-17 pfdena Use the pfdena signal to maintain the most recent locked frequency to enable your system to store its current settings before shutting down. The pfdena signal controls the PFD output with a programmable gate. If you disable the PFD, the VCO operates at its most recent set value of control voltage and frequency with some long-term drift to a lower frequency. areset The areset signal is the reset or resynchronization input for each PLL. The device input pins or internal logic can drive these input signals. When areset is driven high, the PLL counters reset, clearing the PLL output and placing the PLL out-of-lock. The VCO is then set back to its nominal setting. When areset is driven low again, the PLL resynchronizes to its input as it re-locks. You should include the areset signal in designs if any of the following conditions are true: 1 PLL reconfiguration or clock switchover is enabled in your design. Phase relationships between the PLL input and output clocks need to be maintained after a loss-of-lock condition If the input clock to the PLL is not toggling or is unstable upon power up, assert the areset signal after the input clock is stable and in specifications. locked The locked output of the PLL indicates that the PLL has locked onto the reference clock and the PLL clock outputs are operating at the desired phase and frequency set in the Quartus II software MegaWizardTM Plug-In Manager. 1 f Altera recommends that you use the areset and locked signals in your designs to control and observe the status of your PLL. For more information about the PLL control signals, refer to the ALTPLL Megafunction User Guide. Clock Feedback Modes Arria II GX PLLs support up to five different clock feedback modes. Each mode allows clock multiplication and division, phase shifting, and programmable duty cycle. Table 5-9 shows the clock feedback modes supported by Arria II GX PLLs. Table 5-9. Clock Feedback Mode Availability (Part 1 of 2) Clock Feedback Mode (c) February 2009 Availability in Arria II GX Devices Source-synchronous mode Yes No-compensation mode Yes Normal mode Yes Zero-delay buffer (ZDB) mode (1) Yes Altera Corporation Arria II GX Device Handbook Volume 1 5-18 Chapter 5: Clock Networks and PLLs in Arria II GX Devices PLLs in Arria II GX Devices Table 5-9. Clock Feedback Mode Availability (Part 2 of 2) Clock Feedback Mode LVDS compensation Availability in Arria II GX Devices Yes (2) Notes to Table 5-9: (1) The ZDB mode is using 8 ns delay for compensation in Arria II GX devices. (2) LVDS compensation mode is only supported on the PLL_2, PLL_3, PLL_5, and PLL_6. 1 The input and output delays are fully compensated by a PLL only when using the dedicated clock input pins associated with a given PLL as the clock sources. For example, when using PLL_1 in normal mode, the clock delays from the input pin to the PLL clock output-to-destination register are fully compensated, provided the clock input pin is one of the following four pins: CLK12, CLK13, CLK14, or CLK15. When an RCLK or GCLK network drives the PLL, the input and output delays may not be fully compensated in the Quartus II software. Another example is when PLL_1 is configured in zero delay buffer mode and the PLL input is driven by a dedicated clock input pin, a fully compensated clock path results in zero delay between the clock input and one of the output clocks from the PLL. If the PLL input is instead fed by a non-dedicated input (using the GCLK network), then the output clock may not be perfectly aligned with the input clock. Source Synchronous Mode If data and clock arrive at the same time on the input pins, the same phase relationship is maintained at the clock and data ports of any IOE input register. Figure 5-15 shows an example waveform of the clock and data in this mode. This mode is recommended for source-synchronous data transfers. Data and clock signals at the IOE experience similar buffer delays as long as you use the same I/O standard. Figure 5-15. Phase Relationship Between Clock and Data in Source-Synchronous Mode Data pin PLL reference clock at input pin Data at register Clock at register The source-synchronous mode compensates for the delay of the clock network used plus any difference in the delay between these two paths: Data pin to IOE register input Clock input pin to the PLL PFD input Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 5: Clock Networks and PLLs in Arria II GX Devices PLLs in Arria II GX Devices 5-19 You can use the PLL Compensation assignment in the Quartus II software Assignment Editor to select which input pins will be used as the PLL compensation targets. You can include your entire data bus, provided the input registers are clocked by the same output of a source-synchronous compensated PLL. In order for the clock delay to be properly compensated, all input pins need to be on the same side of the device. The PLL will compensate for the input pin with the longest pad-to-register delay among all input pins in the compensated bus. If you do not assign the PLL Compensation assignment, the Quartus II software will automatically select all pins driven by the compensated output of the PLL as the compensation target. Source-Synchronous Mode for LVDS Compensation The goal of this mode is to maintain the same data and clock timing relationship seen at the pins at the internal SERDES capture register, except that the clock is inverted (180 phase shift), as shown in Figure 5-16. Thus, this mode ideally compensates for the delay of the LVDS clock network plus any difference in delay between these two paths: Data pin-to-SERDES capture register Clock input pin-to-SERDES capture register. In addition, the output counter needs to provide the 180 phase shift. Figure 5-16. Source-Synchronous Mode for LVDS Compensation Data pin PLL reference clock at input pin Data at register Clock at register No-Compensation Mode In the no-compensation mode, the PLL does not compensate for any clock networks. This mode provides better jitter performance because the clock feedback into the PFD passes through less circuitry. Both the PLL internal- and external-clock outputs are phase-shifted with respect to the PLL clock input. Figure 5-17 shows an example waveform of the PLL clocks' phase relationship in this mode. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 5-20 Chapter 5: Clock Networks and PLLs in Arria II GX Devices PLLs in Arria II GX Devices Figure 5-17. Phase Relationship Between PLL Clocks in No Compensation Mode Phase Aligned PLL Reference Clock at the Input Pin PLL Clock at the Register Clock Port (1) External PLL Clock Outputs (1) Note to Figure 5-17: (1) The PLL clock outputs will lag the PLL input clocks depending on routine delays. Normal Mode An internal clock in normal mode is phase-aligned to the input clock pin. The external clock-output pin has a phase delay relative to the clock input pin if connected in this mode. The Quartus II software timing analyzer reports any phase difference between the two. In normal mode, the delay introduced by the GCLK or RCLK network is fully compensated. Figure 5-18 shows an example waveform of the PLL clocks' phase relationship in this mode. Figure 5-18. Phase Relationship Between PLL Clocks in Normal Mode Phase Aligned PLL Reference Clock at the Input Pin PLL Clock at the Register Clock Port Dedicated PLL Clock Outputs (1) Note to Figure 5-18: (1) The external clock output can lead or lag the PLL internal clock signals. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 5: Clock Networks and PLLs in Arria II GX Devices PLLs in Arria II GX Devices 5-21 Zero-Delay Buffer Mode In zero-delay buffer (ZDB) mode, the external clock output pin is phase-aligned with the clock input pin for zero delay through the device. When using this mode, you must use the same I/O standard on the input clocks and output clocks to guarantee clock alignment at the input and output pins. This mode is supported on all Arria II GX PLLs. Figure 5-19 shows an example waveform of the PLL clocks' phase relationship in ZDB mode. Figure 5-19. Phase Relationship Between PLL Clocks in Zero Delay Buffer Mode Phase Aligned PLL Reference Clock at the Input Pin PLL Clock at the Register Clock Port Dedicated PLL Clock Outputs (1) Note to Figure 5-19: (1) The internal PLL clock output can lead or lag the external PLL clock outputs. Clock Multiplication and Division Each Arria II GX PLL provides clock synthesis for PLL output ports using m/(n* post-scale counter) scaling factors. The input clock is divided by a pre-scale factor, n, and is then multiplied by the m feedback factor. The control loop drives the VCO to match fin (m/n). Each output port has a unique post-scale counter that divides down the high-frequency VCO. For multiple PLL outputs with different frequencies, the VCO is set to the least common multiple of the output frequencies that meets its frequency specifications. For example, if output frequencies required from one PLL are 33 and 66 MHz, then the Quartus II software sets the VCO to 660 MHz (the least common multiple of 33 and 66 MHz in the VCO range). Then the post-scale counters scale down the VCO frequency for each output port. The VCO frequency reported by the Quartus II software is the value after the post-scale counter divider, k. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 5-22 Chapter 5: Clock Networks and PLLs in Arria II GX Devices PLLs in Arria II GX Devices Each PLL has one pre-scale counter, n, and one multiply counter, m, with a range of 1 to 512 for both m and n. The n counter does not use duty-cycle control because the only purpose of this counter is to calculate frequency division. There are seven generic post-scale counters in each PLL that can feed GCLKs, RCLKs, or external clock outputs. These post-scale counters range from 1 to 512 with a 50% duty cycle setting. The high- and low-count values for each counter range from 1 to 256. The sum of the high- and low-count values chosen for a design selects the divide value for a given counter. The Quartus II software automatically chooses the appropriate scaling factors according to the input frequency, multiplication, and division values entered into the ALTPLL megafunction. Post-Scale Counter Cascading The Arria II GX PLLs support post-scale counter cascading to create counters larger than 512. This is automatically implemented in the Quartus II software by feeding the output of one C counter into the input of the next C counter as shown in Figure 5-20. Figure 5-20. Counter Cascading VCO Output C0 VCO Output C1 VCO Output C2 VCO Output C3 VCO Output C4 from preceding post-scale counter VCO Output Cn (1) Note to Figure 5-20: (1) n = 6 When cascading post-scale counters to implement a larger division of the high-frequency VCO clock, the cascaded counters behave as one counter with the product of the individual counter settings. For example, if C0 = 40 and C1 = 20, then the cascaded value is C0*C1 = 800. 1 Post-scale counter cascading is set in the configuration file. It cannot be done using PLL reconfiguration. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 5: Clock Networks and PLLs in Arria II GX Devices PLLs in Arria II GX Devices 5-23 Programmable Duty Cycle The programmable duty cycle allows PLLs to generate clock outputs with a variable duty cycle. This feature is supported on the PLL post-scale counters. The duty-cycle setting is achieved by a low and high time-count setting for the post-scale counters. The Quartus II software uses the frequency input and the required multiply or divide rate to determine the duty cycle choices. The post-scale counter value determines the precision of the duty cycle. The precision is defined by 50% divided by the post-scale counter value. For example, if the C0 counter is 10, then steps of 5% are possible for duty-cycle choices between 5% to 90%. Combining the programmable duty cycle with programmable phase shift allows the generation of precise non-overlapping clocks. Programmable Phase-Shift Phase shift is used to implement a robust solution for clock delays in Arria II GX devices. Phase shift is implemented with a combination of the VCO phase output and the counter starting time. The VCO phase output and counter starting time is the most accurate method of inserting delays, because it is purely based on counter settings, which are independent of process, voltage, and temperature. You can phase-shift the output clocks from the Arria II GX PLLs in either of these two resolutions: Fine resolution using VCO phase taps Coarse resolution using counter starting time Fine-resolution phase shifts are implemented by allowing any of the output counters (C[n..0]) or the m counter to use any of the eight phases of the VCO as the reference clock. This allows you to adjust the delay time with a fine resolution. The minimum delay time that you can insert using this method is defined by: Equation 5-1. Fine-Resolution Phase Shifts fine = 1 T = 8 VCO N 1 = 8fVCO 8MfREF where fREF is the input reference clock frequency. For example, if fREF is 100 MHz, n is 1, and m is 8, then fVCO is 800 MHz and fine equals 156.25 ps. This phase shift is defined by the PLL operating frequency, which is governed by the reference clock frequency and the counter settings. Coarse-resolution phase shifts are implemented by delaying the start of the counters for a predetermined number of counter clocks. You can express coarse phase shift as: Equation 5-2. Coarse-Resolution Phase Shifts coarse = (c) February 2009 Altera Corporation C - 1 (C - 1)N = fVco MfREF Arria II GX Device Handbook Volume 1 5-24 Chapter 5: Clock Networks and PLLs in Arria II GX Devices PLLs in Arria II GX Devices where C is the count value set for the counter delay time, (this is the initial setting in the PLL usage section of the compilation report in the Quartus II software). If the initial value is 1, C - 1 = 0 phase shift. Figure 5-21 shows an example of phase-shift insertion with the fine resolution using the VCO phase taps method. The eight phases from the VCO are shown and labeled for reference. For this example, CLK0 is based off the 0phase from the VCO and has the C value for the counter set to one. The CLK1 signal is divided by four, two VCO clocks for high time and two VCO clocks for low time. CLK1 is based off the 135x phase tap from the VCO and also has the C value for the counter set to one. The CLK1 signal is also divided by 4. In this case, the two clocks are offset by 3 fine . CLK2 is based off the 0phase from the VCO but has the C value for the counter set to three. This arrangement creates a delay of 2 COARSE (two complete VCO periods). Figure 5-21. Delay Insertion Using VCO Phase Output and Counter Delay Time 1/8 tVCO tVCO 0 45 90 135 180 225 270 315 CLK0 td0-1 CLK1 td0-2 CLK2 You can use the coarse- and fine-phase shifts to implement clock delays in Arria II GX devices. The ALTPLL megafunction allows you to enter the desired VCO phase taps and initial counter value settings through the Quartus II Megawizard Plug-In Manager. Arria II GX devices support dynamic phase-shifting of VCO phase taps only. The phase shift is reconfigurable any number of times, and each phase shift takes about one scanclk cycle, allowing you to implement large phase shifts quickly. Programmable Bandwidth PLL bandwidth is the measure of the PLL's ability to track the input clock and its associated jitter. Arria II GX PLLs provide advanced control of the PLL bandwidth using the PLL loop's programmable characteristics, including loop filter and charge pump. The closed-loop gain 3-dB frequency in the PLL determines the PLL bandwidth. The bandwidth is approximately the unity gain point for open loop PLL response. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 5: Clock Networks and PLLs in Arria II GX Devices PLLs in Arria II GX Devices 5-25 Spread-Spectrum Tracking Arria II GX devices can accept a spread-spectrum input with typical modulation frequencies. However, the device cannot automatically detect that the input is a spread-spectrum signal. Instead, the input signal looks like deterministic jitter at the input of PLL. Arria II GX PLLs can track a spread-spectrum input clock as long as the input jitter is in the PLL input jitter tolerance specification. Arria II GX devices cannot internally generate spread-spectrum clocks. Clock Switchover The clock switchover feature allows the PLL to switch between two reference input clocks. Use this feature for clock redundancy or for a dual-clock domain application such as in a system that turns on the redundant clock if the previous clock stops running. Your design can perform clock switchover automatically, when the clock is no longer toggling or based on a user control signal, clkswitch. The following clock switchover modes are supported in Arria II GX PLLs: Automatic switchover: The clock sense circuit monitors the current reference clock and if it stops toggling, automatically switches to the other clock inclk0 or inclk1. Manual clock switchover: Clock switchover is controlled using the clkswitch signal in this mode. When the clkswitch signal goes from logic low to logic high, and stays high for at least three clock cycles, the reference clock to the PLL is switched from inclk0 to inclk1, or vice-versa. Automatic switchover with manual override: This mode combines modes 1 and 2. When the clkswitch signal goes high, it overrides automatic clock switchover mode. Arria II GX PLLs support a fully configurable clock switchover capability. Figure 5-22 shows the block diagram of the switchover circuit built into the PLL. When the current reference clock is not present, the clock sense block automatically switches to the backup clock for PLL reference. The clock switchover circuit also sends out three status signals--clkbad[0], clkbad[1], and activeclock--from the PLL to implement a custom switchover circuit in the logic array. You can select a clock source as the backup clock by connecting it to the inclk1 port of the PLL in your design. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 5-26 Chapter 5: Clock Networks and PLLs in Arria II GX Devices PLLs in Arria II GX Devices Figure 5-22. Automatic Clock Switchover Circuit Block Diagram clkbad0 clkbad1 activeclock Switchover State Machine Clock Sense clksw Clock Switch Control Logic clkswitch inclk0 n Counter inclk1 muxout PFD refclk fbclk Automatic Clock Switchover Use the switchover circuitry to automatically switch between inclk0 and inclk1 when the current reference clock to the PLL stops toggling. For example, in applications that require a redundant clock with the same frequency as the reference clock, the switchover state machine generates a signal (clksw) that controls the multiplexer select input as shown in Figure 5-22. In this case, inclk1 becomes the reference clock for the PLL. When using the automatic switchover mode, you can switch back and forth between the inclk0 and inclk1 clocks any number of times, when one of the two clocks fails and the other clock is available. When using the automatic clock switchover mode, the following requirements need to be satisfied: Both clock inputs need to be running. The period of the two clock inputs can differ by no more than 100% (2x). If the current clock input stops toggling while the other clock is also not toggling, switchover will not be initiated and the clkbad[0:1] signals will not be valid. Also, if both clock inputs are not the same frequency, but their period difference is in 100%, the clock sense block will detect when a clock stops toggling, but the PLL may lose lock after the switchover is completed and need time to relock. 1 Altera recommends resetting the PLL using the areset signal to maintain the phase relationships between the PLL input and output clocks when using clock switchover. When using automatic switchover mode, the clkbad[0] and clkbad[1] signals indicate the status of the two clock inputs. When they are asserted, the clock sense block has detected that the corresponding clock input has stopped toggling. These two signals are not valid if the frequency difference between inclk0 and inclk1 is greater than 20%. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 5: Clock Networks and PLLs in Arria II GX Devices PLLs in Arria II GX Devices 5-27 The activeclock signal indicates which of the two clock inputs (inclk0 or inclk1) is being selected as the reference clock to the PLL. When the frequency difference between the two clock inputs is more than 20%, the activeclock signal is the only valid status signal. Figure 5-23 shows an example waveform of the switchover feature when using the automatic switchover mode. In this example, the inclk0 signal is stuck low. After the inclk0 signal is stuck at low for approximately two clock cycles, the clock sense circuitry drives the clkbad[0] signal high. Also, because the reference clock signal is not toggling, the switchover state machine controls the multiplexer through the clksw signal to switch to the backup clock, inclk1. Figure 5-23. Automatic Switchover Upon Loss of Clock Detection inclk0 inclk1 (1) muxout clkbad0 clkbad1 activeclock Note to Figure 5-23: (1) Switchover is enabled on the falling edge of inclk0 or inclk1, depending on which clock is available. In this figure, switchover is enabled on the falling edge of inclk1. Manual Override In the automatic switchover with manual override mode, you can use the clkswitch input for user- or system-controlled switch conditions. You can use this mode for same-frequency switchover or to switch between inputs of different frequencies. For example, if inclk0 is 66 MHz and inclk1 is 200 MHz, you must control the switchover using clkswitch because the automatic clock-sense circuitry cannot monitor clock input (inclk0, inclk1) frequencies with a frequency difference of more than 100% (2x). This feature is useful when the clock sources originate from multiple cards on the backplane, requiring a system-controlled switchover between the frequencies of operation. You should choose the backup clock frequency and set the m, n, c, and k counters accordingly so the VCO operates in the recommended operating frequency range of 600 to 1,300 MHz. The ALTPLL Megawizard Plug-In Manager notifies you if a given combination of inclk0 and inclk1 frequencies cannot meet this requirement. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 5-28 Chapter 5: Clock Networks and PLLs in Arria II GX Devices PLLs in Arria II GX Devices Figure 5-24 shows an example of a waveform illustrating the switchover feature when controlled by clkswitch. In this case, both clock sources are functional and inclk0 is selected as the reference clock. The clkswitch signal goes high, which starts the switchover sequence. On the falling edge of inclk0, the counter's reference clock, muxout, is gated off to prevent any clock glitching. On the falling edge of inclk1, the reference clock multiplexer switches from inclk0 to inclk1 as the PLL reference, and the activeclock signal changes to indicate which clock is currently feeding the PLL. Figure 5-24. Clock Switchover Using the clkswitch (Manual) Control (Note 1) inclk0 inclk1 muxout clkswitch activeclock clkbad0 clkbad1 Note to Figure 5-24: (1) Both inckl0 and inclk1 must be running when the clkswitch signal goes high to start a manual clock switchover event. In this mode, the activeclock signal mirrors the clkswitch signal. As both clocks are still functional during the manual switch, neither clkbad signal goes high. Because the switchover circuit is positive-edge sensitive, the falling edge of the clkswitch signal does not cause the circuit to switch back from inclk1 to inclk0. When the clkswitch signal goes high again, the process repeats. The clkswitch signal and automatic switch only work if the clock being switched to is available. If the clock is not available, the state machine waits until the clock is available. Manual Clock Switchover In manual clock switchover mode, the clkswitch signal controls whether inclk0 or inclk1 is selected as the input clock to the PLL. By default, inclk0 is selected. A low-to-high transition on clkswitch and clkswitch being held high for at least three inclk cycles begins a clock switchover event. You must bring clkswitch back low again to perform another switchover event in the future. If you do not require another switchover event in the future, you can leave clkswitch in a logic high state after the initial switch. Pulsing clkswitch high for at least three inclk cycles performs another switchover event. If inclk0 and inclk1 are different frequencies and are always running, the clkswitch minimum high time must be greater than or equal to three of the slower frequency inclk0/inclk1 cycles. Figure 5-25 shows the block diagram of the manual switchover circuit. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 5: Clock Networks and PLLs in Arria II GX Devices PLLs in Arria II GX Devices 5-29 Figure 5-25. Manual Clock Switchover Circuitry in Arria II GX PLLs clkswitch Clock Switch Control Logic inclk0 n Counter PFD inclk1 muxout refclk fbclk f For more information about PLL software support in the Quartus II software, refer to the ALTPLL Megafunction User Guide. Guidelines Use the following guidelines when implementing clock switchover in Arria II GX PLLs. Automatic clock switchover requires that the inclk0 and inclk1 frequencies be in 100% (2x) of each other. Failing to meet this requirement causes the clkbad[0] and clkbad[1] signals to not function properly. When using manual clock switchover, the difference between inclk0 and inclk1 can be more than 100% (2x). However, differences in frequency and/or phase of the two clock sources will likely cause the PLL to lose lock. Resetting the PLL ensures that the correct phase relationships are maintained between the input and output clocks. 1 (c) February 2009 Both inclk0 and inclk1 must be running when the clkswitch signal goes high to start the manual clock switchover event. Failing to meet this requirement causes the clock switchover to not function properly. Applications that require a clock switchover feature and a small frequency drift should use a low-bandwidth PLL. The low bandwidth PLL reacts more slowly than a high-bandwidth PLL to reference input clock changes. When the switchover happens, a low bandwidth PLL propagates the stopping of the clock to the output more slowly than a high-bandwidth PLL. However, be aware that the low-bandwidth PLL also increases lock time. After a switchover occurs, there may be a finite resynchronization period for the PLL to lock onto a new clock. The exact amount of time it takes for the PLL to re-lock depends on the PLL configuration. If the phase relationship between the input clock to the PLL and the output clock from the PLL is important in your design, assert areset for at least 10 ns after performing a clock switchover. To prevent clock glitches from propagating through your design during PLL resynchronization or after areset is applied, use the clock enable feature of the clock control block to disable the clock network. Wait for the locked signal to assert and be stable before re-enabling the output clocks from the PLL at the clock control block. Altera Corporation Arria II GX Device Handbook Volume 1 5-30 Chapter 5: Clock Networks and PLLs in Arria II GX Devices PLLs in Arria II GX Devices Figure 5-26 shows how the VCO frequency gradually decreases when the current clock is lost and then increases as the VCO locks on to the backup clock. Figure 5-26. VCO Switchover Operating Frequency Primary Clock Stops Running Switchover Occurs VCO Tracks Secondary Clock Fvco Disable the system during clock switchover if it is not tolerant of frequency variations during the PLL resynchronization period. You can use the clkbad[0] and clkbad[1] status signals to turn off the PFD (PFDENA = 0) so the VCO maintains its most recent frequency. You can also use the state machine to switch over to the secondary clock. When the PFD is re-enabled, output clock-enable signals (clkena) can disable clock outputs during the switchover and resynchronization period. Once the lock indication is stable, the system can re-enable the output clocks. PLL Reconfiguration Phase-locked loops (PLLs) use several divide counters and different voltage-controlled oscillator (VCO) phase taps to perform frequency synthesis and phase shifts. In Arria II GX PLLs, you can reconfigure both the counter settings and phase-shift the PLL output clock in real time. You can also change the charge pump and loop-filter components, which dynamically affect the PLL bandwidth. You can use these PLL components to update the output-clock frequency and the PLL bandwidth and to phase-shift in real time, without reconfiguring the entire Arria II GX device. The ability to reconfigure the PLL in real time is useful in applications that operate at multiple frequencies. It is also useful in prototyping environments, allowing you to sweep PLL output frequencies and adjust the output-clock phase dynamically. For instance, a system generating test patterns is required to generate and transmit patterns at 75 or 150 MHz, depending on the requirements of the device under test. Reconfiguring the PLL components in real time allows you to switch between two such output frequencies in a few microseconds. You can also use this feature to adjust clock-to-out (tCO) delays in real time by changing the PLL output clock phase shift. This approach eliminates the need to regenerate a configuration file with the new PLL settings. PLL Reconfiguration Hardware Implementation The following PLL components are reconfigurable in real time: Pre-scale counter (n) Feedback counter (m) Post-scale output counters (C0 - C6) Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 5: Clock Networks and PLLs in Arria II GX Devices PLLs in Arria II GX Devices 5-31 Post VCO divider (K) Dynamically adjust the charge-pump current (Icp) and loop-filter components (R, C) to facilitate reconfiguration of the PLL bandwidth Figure 5-27 shows how PLL counter settings can be dynamically adjusted by shifting their new settings into a serial shift-register chain or scan chain. Serial data is input to the scan chain using the scandataport and shift registers are clocked by scanclk. The maximum scanclk frequency is 100 MHz. Serial data is shifted through the scan chain as long as the scanclkena signal stays asserted. After the last bit of data is clocked, asserting the configupdate signal for at least one scanclk clock cycle causes the PLL configuration bits to be synchronously updated with the data in the scan registers. f For more information about the PLL reconfiguration port signals, refer to the ALTPLL_RECONFIG Megafunction User Guide. Figure 5-27. PLL Reconfiguration Scan Chain from m counter from n counter LF/K/CP (3) PFD VCO scandata scanclkena configupdate /Ci (2) inclk scandataout /Ci-1 /C2 /C1 /C0 /m /n scandone scanclk Notes to Figure 5-27: (1) The Arria II GX PLLs support C0 - C6 counters. (2) i = 6 (3) This figure shows the corresponding scan register for the K counter in between the scan registers for the charge pump and loop filter. The K counter is physically located after the VCO. 1 The counter settings are updated synchronously to the clock frequency of the individual counters. Therefore, all counters are not updated simultaneously. The procedure to reconfigure the PLL counters is shown below: 1. The scanclkena signal is asserted at least one scanclk cycle prior to shifting in the first bit of scandata (Dn). 2. Serial data (scandata) is shifted into the scan chain on the 2nd rising edge of scanclk. 3. After all 180 bits are scanned into the scan chain, the scanclkena signal is deasserted to prevent inadvertent shifting of bits in the scan chain. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 5-32 Chapter 5: Clock Networks and PLLs in Arria II GX Devices PLLs in Arria II GX Devices 4. The configupdate signal is asserted for one scanclk cycle to update the PLL counters with the contents of the scan chain. 5. The scandone signal goes high indicating the PLL is being reconfigured. A falling edge indicates the PLL counters are updated with new settings. 6. Reset the PLL using the areset signal if you make any changes to the M or N counters or the Icp, R, or C settings. 7. Steps 1-5 can be repeated to reconfigure the PLL any number of times. Figure 5-28 shows a functional simulation of the PLL reconfiguration feature. Figure 5-28. PLL Reconfiguration Waveform Dn SCANDATA D0 SCANCLK SCANCLKENA Dn_old SCANDATAOUT D0_old Dn CONFIGUPDATE SCANDONE ARESET 1 When you reconfigure the counter clock frequency, you cannot reconfigure the corresponding counter phase shift settings using the same interface. Instead, reconfigure the phase shifts in real time using the dynamic phase shift reconfiguration interface. If you reconfigure the counter frequency, but wish to keep the same non-zero phase shift setting (for example, 90) on the clock output, you must reconfigure the phase shift immediately after reconfiguring the counter clock frequency. Post-Scale Counters (C0 to C6) The multiply or divide values and duty cycle of post-scale counters can be reconfigured in real time. Each counter has an 8-bit high-time setting and an 8-bit low-time setting. The duty cycle is the ratio of output high- or low-time to the total cycle time, which is the sum of the two. Additionally, these counters have two control bits, rbypass, for bypassing the counter, and rselodd, to select the output clock duty cycle. When the rbypass bit is set to 1, it bypasses the counter, resulting in a divide by 1. When this bit is set to 0, the high- and low-time counters are added to compute the effective division of the VCO output frequency. For example, if the post-scale divide factor is 10, the high- and low-count values could be set to 5 and 5, respectively, to achieve a 50-50% duty cycle. The PLL implements this duty cycle by transitioning the output clock from high to low on the rising edge of the VCO output clock. However, a 4 and 6 setting for the high- and low-count values, respectively, would produce an output clock with a 40-60% duty cycle. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 5: Clock Networks and PLLs in Arria II GX Devices PLLs in Arria II GX Devices 5-33 The rselodd bit indicates an odd divide factor for the VCO output frequency along with a 50% duty cycle. For example, if the post-scale divide factor is 3, the high- and low-time count values could be set to 2 and 1, respectively, to achieve this division. This implies a 67%-33% duty cycle. If you need a 50%-50% duty cycle, you can set the rselodd control bit to 1 to achieve this duty cycle despite an odd division factor. The PLL implements this duty cycle by transitioning the output clock from high to low on a falling edge of the VCO output clock. When you set rselodd = 1, you subtract 0.5 cycles from the high time and you add 0.5 cycles to the low time. For example: High-time count = 2 cycles Low-time count = 1 cycle rselodd = 1 effectively equals: High-time count = 1.5 cycles Low-time count = 1.5 cycles Duty cycle = (1.5/3) % high-time count and (1.5/3) % low-time count Scan Chain Description Arria II GX PLLs have a 180-bit scan chain. Table 5-10 shows the number of bits for each component of an Arria II GX PLL. Table 5-10. Arria II GX PLL Reprogramming Bits Number of Bits Block Name Counter Other (1) Total C6 (2) 16 2 18 C5 16 2 18 C4 16 2 18 C3 16 2 18 C2 16 2 18 C1 16 2 18 C0 16 2 18 M 16 2 18 N 16 2 18 Charge Pump Current 0 3 3 VCO Post-Scale divider (K) 1 0 1 Loop Filter Capacitor (3) 0 2 2 Loop Filter Resistor 0 5 5 Unused CP/LF 0 7 7 Total number of bits -- -- 180 Notes to Table 5-10: (1) Includes two control bits, rbypass, for bypassing the counter, and rselodd, to select the output clock duty cycle. (2) LSB bit for C6 low-count value is the first bit shifted into the scan chain for Left/Right PLLs. (3) MSB bit for loop filter is the last bit shifted into the scan chain. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 5-34 Chapter 5: Clock Networks and PLLs in Arria II GX Devices PLLs in Arria II GX Devices Figure 5-29 shows the scan chain order of Arria II GX PLL components which have 7 post-scale counters. The reconfiguration bits start with the C6 post-scale counter. Figure 5-29. Scan-Chain Order of PLL Components for Arria II GX PLLs DATAIN K LF CP LSB MSB C6 C4 C5 N M C0 C3 C2 C1 DATAOUT Figure 5-30 shows the scan-chain bit-order sequence for post-scale counters in all Arria II GX PLLs. Figure 5-30. Scan-Chain Bit-Order Sequence for Post-Scale Counters in Arria II GX PLLs DATAOUT HB HB HB HB HB HB HB HB 0 1 2 3 4 5 6 7 LB LB LB LB LB LB LB LB 0 1 2 3 4 5 6 7 DATAIN rbypass rselodd Charge Pump and Loop Filter You can reconfigure the charge-pump and loop-filter settings to update the PLL bandwidth in real time. Table 5-11 through Table 5-13 show the possible settings for charge pump current (Icp), loop-filter resistor (R), and capacitor (C) values for Arria II GX PLLs. Table 5-11. charge_pump_current Bit Settings CP[2] CP[1] CP[0] Decimal Value for Setting 0 0 0 0 0 0 1 1 0 1 1 3 1 1 1 7 Table 5-12. loop_filter_r Bit Settings (Part 1 of 2) LFR[4] LFR[3] LFR[2] LFR[1] LFR[0] Decimal Value for Setting 0 0 0 0 0 0 0 0 0 1 1 3 0 0 1 0 0 4 Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 5: Clock Networks and PLLs in Arria II GX Devices PLLs in Arria II GX Devices 5-35 Table 5-12. loop_filter_r Bit Settings (Part 2 of 2) LFR[4] LFR[3] LFR[2] LFR[1] LFR[0] Decimal Value for Setting 0 1 0 0 0 8 1 0 0 0 0 16 1 0 0 1 1 19 1 0 1 0 0 20 1 1 0 0 0 24 1 1 0 1 1 27 1 1 1 0 0 28 1 1 1 1 0 30 Table 5-13. loop_filter_c Bit Settings LFC[1] LFC[0] Decimal Value for Setting 0 0 0 0 1 1 1 1 3 Bypassing PLL Bypassing a PLL counter results in a multiply (m counter) or a divide (n and C0 to C6 counters) factor of one. Table 5-14 shows the settings for bypassing the counters in Arria II GX PLLs. Table 5-14. PLL Counter Settings PLL Scan Chain Bits [0..8] Settings LSB (2) MSB (1) Description 0 X X X X X X X 1 (3) PLL counter bypassed X X X X X X X X 0 (3) PLL counter not bypassed because bit 8 (MSB) is set to 0 Notes to Table 5-14: (1) Most significant bit (MSB) (2) Least significant bit (LSB). (3) Counter-bypass bit. f 1 (c) February 2009 For more information on how to use the PLL scan chain bit settings, refer to the ALTPLL_RECONFIG Megafunction User Guide. To bypass any of the PLL counters, set the bypass bit to 1, causing the values on the other bits to be ignored. To bypass the VCO post-scale counter (K), set the corresponding bit to 0. Altera Corporation Arria II GX Device Handbook Volume 1 5-36 Chapter 5: Clock Networks and PLLs in Arria II GX Devices PLLs in Arria II GX Devices Dynamic Phase-Shifting The dynamic phase-shifting feature allows the output phases of individual PLL outputs to be dynamically adjusted relative to each other and to the reference clock without the need to send serial data through the scan chain of the corresponding PLL. This feature simplifies the interface and allows you to quickly adjust clock-to-out (tCO) delays by changing the output clock phase-shift in real time. This adjustment is achieved by incrementing or decrementing the VCO phase-tap selection to a given C counter or to the M counter. The phase is shifted by 1/8 of the VCO frequency at a time. The output clocks are active during this phase-reconfiguration process. Table 5-15 shows the control signals that are used for dynamic phase-shifting. Table 5-15. Dynamic Phase-Shifting Control Signals Signal Name Description Source Destination PHASECOUNTER SELECT[3:0] Counter select. Four bits decoded to select either the M or one of the C counters for phase adjustment. One address maps to select all C counters. This signal is registered in the PLL on the rising edge of scanclk. Logic array or I/O pins PLL reconfiguration circuit PHASEUPDOWN Selects dynamic phase shift direction; 1= UP; 0= DOWN. Signal is registered in the PLL on the rising edge of scanclk. Logic array or I/O pin PLL reconfiguration circuit PHASESTEP Logic high enables dynamic phase shifting. Logic array or I/O pin PLL reconfiguration circuit SCANCLK Free running clock from core used in combination with PHASESTEP to enable/disable dynamic phase shifting. Shared with scanclk for dynamic reconfiguration. GCLK/RCLK or I/O pin PLL reconfiguration circuit PHASEDONE When asserted, it indicates to core-logic that the phase adjustment is complete and PLL is ready to act on a possible second adjustment pulse. Asserts based on internal PLL timing. De-asserts on rising edge of scanclk. PLL reconfiguration circuit Logic array or I/O pins Table 5-16 shows the PLL counter selection based on the corresponding PHASECOUNTERSELECT setting. Table 5-16. Phase Counter Select Mapping PHASECOUNTERSELECT[3] [2] [1] [0] Selects 0 0 0 0 All Output Counters 0 0 0 1 M Counter 0 0 1 0 C0 Counter 0 0 1 1 C1 Counter 0 1 0 0 C2 Counter 0 1 0 1 C3 Counter 0 1 1 0 C4 Counter 0 1 1 1 C5 Counter 1 0 0 0 C6 Counter Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 5: Clock Networks and PLLs in Arria II GX Devices PLLs in Arria II GX Devices 5-37 The procedure to perform one dynamic phase-shift step is as follows: 1. Set phaseupdown and phasecounterselect as required. 2. Assert phasestep for at least two scanclk cycles. Each phasestep pulse enables one phase shift. 3. De-assert phasestep. 4. Wait for phasedone to go high. 5. Repeat steps 1-4 as many times as required to perform multiple phase-shifts. All signals are synchronous to scanclk and must meet tsu/th requirements with respect to scanclk edges. They are latched on scanclk edges and must meet tsu/th requirements with respect to scanclk edges. Figure 5-31. Dynamic Phase Shifting Waveform SCANCLK PHASESTEP PHASEUPDOWN PHASECOUNTERSELECT PHASEDONE a b c d PHASEDONE goes low synchronous with SCANCLK 1 Dynamic phase-shifting can be repeated indefinitely. For example, in a design where the VCO frequency is set to 1000 MHz and the output clock frequency is 100 Mhz, performing 40 dynamic phase shifts (each one yields 125 ps phase shift) results in shifting the output clock by 180, in other words, a phase shift of 5 ns. The phasestep signal is latched on the negative edge of scanclk. In Figure 5-31, this is shown by the second scanclk falling edge. phasestep must stay high for at least two scanclk cycles. On the second scanclk rising edge after phasestep is latched (the fourth scanclk rising edge in Figure 5-31), the values of phaseupdown and phasecounterselect are latched and the PLL starts dynamic phase-shifting for the specified counters and in the indicated direction. On the fourth scanclk rising edge, phasedone goes high to low and remains low until the PLL finishes dynamic phase-shifting. You can perform another dynamic phase-shift after the phasedone signal goes from low to high. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 5-38 Chapter 5: Clock Networks and PLLs in Arria II GX Devices Document Revision History Depending on the VCO and scanclk frequencies, phasedone low time may be greater than or less than one scanclk cycle. f For details about the ALTPLL_RECONFIG Megawizard Plug-In Manager, refer to the ALTPLL_RECONFIG Megafunction User Guide. PLL Specifications f Refer to the Arria II GX Device Data Sheet chapter in volume 3 of the Arria II GX Device Handbook for information about PLL timing specifications. Document Revision History Table 5-17 shows the revision history for this document. Table 5-17. Document Revision History Date and Document Version February 2009, v1.0 Changes Made Summary of Changes Initial Release. Arria II GX Device Handbook Volume 1 -- (c) February 2009 Altera Corporation Section II. I/O Interfaces This section provides information on Arria(R) II GX device I/O features, external memory interfaces, and high-speed differential interfaces with DPA. This section includes the following chapters: Chapter 6, I/O Features in Arria II GX Devices Chapter 7, External Memory Interfaces in Arria II GX Devices Chapter 8, High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices Revision History Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in this volume. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 1 II-2 Arria II GX Device Handbook Volume 1 Section II: I/O Interfaces (c) March 2009 Altera Corporation 6. I/O Features in Arria II GX Devices AIIGX51006-1.0 This chapter provides guidelines for using industry I/O standards in Arria(R) II GX devices, including I/O features, I/O standards and structure, I/O banks, and design considerations. This chapter includes the following sections: "Arria II GX I/O Standards Support" on page 6-2 "Arria II GX I/O Banks" on page 6-3 "Arria II GX I/O Structure" on page 6-5 "Arria II GX OCT Support" on page 6-11 "Arria II GX OCT Calibration" on page 6-14 "Arria II GX Termination Schemes for I/O Standards" on page 6-14 "Arria II GX Design Considerations" on page 6-21 Introduction This chapter contains feature definitions of Arria II GX I/O elements (IOEs). It provides details about how an IOE works and its features. Arria II GX I/Os support a wide range of features: (c) February 2009 Up to 16 full-duplex CDR-based transceivers supporting data rates between 155 Mbps and 3.75 Gbps Dedicated circuitry to support physical layer functionality for popular serial protocols, such as PCI Express (PIPE) Gen1, Serial RapidIO (R) , SATA/SAS, SD/HD/3G SDI, ASI, CPRI/OBSAI, Gigabit Ethernet, XAUI/HiGig/HiGig+, SONET/SDH, GPON and Seriallite II Complete PIPE protocol solution with embedded PCI Express hard IP blocks that implement PHY-MAC layer, data link layer, and transaction layer functionality Single-ended, non-voltage-referenced and voltage-referenced I/O standards Low-voltage differential signaling (LVDS), reduced swing differential signal (RSDS), mini-LVDS, high-speed transceiver logic (HSTL), and SSTL Hard DPA block with serializer/deserializer (SERDES) Programmable output current strength Programmable slew rate Programmable bus-hold Programmable pull-up resistor Open-drain output Serial on-chip termination (OCT) Differential OCT Altera Corporation Arria II GX Device Handbook Volume 1 6-2 Chapter 6: I/O Features in Arria II GX Devices Arria II GX I/O Standards Support Programmable pre-emphasis Programmable voltage output differential (VOD) Arria II GX I/O Standards Support Table 6-1 shows the supported I/O standards for Arria II GX devices and the typical values for input and output VCCIO, VCCPD, VREF, and board VTT. Table 6-1. Arria II GX I/O Standards and Voltage Levels (Note 1), (2) VCC IO (V) I/O Standard Standard Support Input Operation Output Operation VC CP D (V) VREF (V) VTT (V) 3.3-V LVTTL/3.3-V LVCMOS JESD8-B 3.3/3.0/2.5 3.3 3.3 -- -- 3.0-V LVTTL/3.0-V LVCMOS JESD8-B 3.3/3.0/2.5 3.0 3.0 -- -- 2.5-V LVTTL/LVCMOS JESD8-5 3.3/3.0/2.5 2.5 2.5 -- -- 1.8-V LVTTL/LVCMOS JESD8-7 1.8/1.5 1.8 2.5 -- -- 1.5-V LVCMOS JESD8-11 1.8/1.5 1.5 2.5 -- -- 1.2-V LVCMOS JESD8-12 1.2 1.2 2.5 -- -- PCI Rev 2.2 3.0 3.0 3.0 -- -- PCI-X Rev 1.0 3.0 3.0 3.0 -- -- SSTL-2 Class I and Class II JESD8-9B (2) 2.5 2.5 1.25 1.25 SSTL-18 Class I and Class II JESD8-15 (2) 1.8 2.5 0.90 0.90 -- (2) 1.5 2.5 0.75 0.75 HSTL-18 Class I and Class II JESD8-6 (2) 1.8 2.5 0.90 0.90 HSTL-15 Class I and Class II JESD8-6 (2) 1.5 2.5 0.75 0.75 HSTL-12 Class I and Class II JESD8-16A (2) 1.2 2.5 0.6 0.6 Differential SSTL-2 JESD8-9B (2), (3) 2.5 2.5 -- 1.25 Differential SSTL-18 JESD8-15 (2), (3) 1.8 2.5 -- 0.90 Differential SSTL-15 -- (2), (3) 1.5 2.5 -- 0.75 Differential HSTL-18 JESD8-6 (2), (3) 1.8 2.5 -- 0.90 Differential HSTL-15 JESD8-6 (2), (3) 1.5 2.5 -- 0.75 Differential HSTL-12 JESD8-16A (2), (3) 1.2 2.5 -- 0.60 LVDS ANSI/TIA/ EIA-644 (2) 2.5 2.5 -- -- RSDS and mini-LVDS -- -- 2.5 2.5 -- -- LVPECL -- 2.5 -- 2.5 -- -- BLVDS -- 2.5 2.5 2.5 -- -- 3.0-V PCI 3.0-V PCI-X (1) SSTL-15 Class I Notes to Table 6-1: (1) PCI-X does not meet the PCI-X IV curve requirement at the linear region. (2) Single-ended SSTL/HSTL, differential SSTL/HSTL, and LVDS input buffers are powered by VCCPD. (3) Differential SSTL/HSTL inputs use LVDS differential input buffers without on-chip RD support. f For detailed electrical characteristics of each I/O standard, refer to the Device Data Sheet chapter in volume 3 of the Arria II GX Device Handbook. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 6: I/O Features in Arria II GX Devices Arria II GX I/O Banks 6-3 Arria II GX I/O Banks Arria II GX devices contain up to 16 I/O banks, as shown in Figure 6-1. The left side I/O banks contain high-speed transceiver banks, with dedicated configuration banks at banks 3C and 8C. The rest of the banks are user I/O banks. All user I/O banks support all single-ended and differential I/O standards. Figure 6-1. Arria II GX Devices I/0 Banks (Note 1), (2), (3), (4), (5), (6) Bank 8B Bank 8A Bank 7A Bank 7B GXB3 Bank 6B Bank 8C Bank 6A Bank 5A GXB0 Bank 5B GXB1 GXB2 These I/O Banks Support: 3.3-V LVTTL/LVCMOS, 3.0-V LVTTL/LVCMOS, 2.5-V LVTTL/LVCMOS, 1.8-V LVTTL/LVCMOS, 1.5-V LVCMOS, 1.2-V LVCMOS, Dedicated LVDS, Pseudo LVDS, RSDS, mini-LVDS, SSTL-2, SSTL-18, SSTL-15, HSTL-18, HSTL-15, HSTL-12, Differential SSTL-2, Differenital SSTL-18, Differential SSTL-15, Differential HSTL-18, Differential HSTL-15, and Differential HSTL-12 Bank 3C Bank 3B Bank 3A Bank 4A Bank 4B Notes to Figure 6-1: (1) (2) (3) (4) (5) Banks GXB0, GXB1, GXB2, and GXB3 are dedicated banks for high-speed transceiver I/Os. Banks 3C and 8C are dedicated configuration banks and do not have user I/O pins. LVDS with DPA is supported at banks 5A, 5B, 6A, and 6B. Differential HSTL and SSTL inputs use LVDS differential input buffers without differential OCT support. Differential HSTL and SSTL outputs are not true differential outputs. They use two single-ended outputs with the second output programmed as inverted. (6) Figure 6-1 is a top view of the silicon die that corresponds to a reverse view for flip chip packages. It is a graphical representation only. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 6-4 Chapter 6: I/O Features in Arria II GX Devices Arria II GX I/O Banks Modular I/O Banks The I/O pins in Arria II GX devices are arranged in groups called modular I/O banks. Depending on device densities, the number of I/O banks range from 6 to 12, while the number of transceiver banks range from 1 to 4. Table 6-2 shows the number of I/O pins available in each I/O bank. Table 6-2. Arria II GX Available I/O Pins in Each I/O Bank (Note 1) Bank Package Device 3A 3B 4A 4B 5A 5B 6A 6B 7A 7B 8A 8B Total 2AGX20 22 -- 38 -- 18 -- 18 -- 38 -- 22 -- 156 2AGX30 22 -- 38 -- 18 -- 18 -- 38 -- 22 -- 156 2AGX45 22 -- 38 -- 18 -- 18 -- 38 -- 22 -- 156 2AGX65 22 -- 38 -- 18 -- 18 -- 38 -- 22 -- 156 2AGX20 38 -- 38 -- 50 -- 50 -- 38 -- 38 -- 252 2AGX30 38 -- 38 -- 50 -- 50 -- 38 -- 38 -- 252 2AGX45 38 -- 38 -- 50 -- 50 -- 38 -- 38 -- 252 2AGX65 38 -- 38 -- 50 -- 50 -- 38 -- 38 -- 252 2AGX95 38 -- 42 -- 50 -- 50 -- 38 -- 42 -- 260 2AGX125 38 -- 42 -- 50 -- 50 -- 38 -- 42 -- 260 2AGX45 54 -- 70 -- 66 -- 50 -- 70 -- 54 -- 364 2AGX65 54 -- 70 -- 66 -- 50 -- 70 -- 54 -- 364 2AGX95 54 -- 74 -- 66 -- 50 -- 70 -- 58 -- 372 2AGX125 54 -- 74 -- 66 -- 50 -- 70 -- 58 -- 372 2AGX190 54 -- 74 -- 66 -- 50 -- 70 -- 58 -- 372 2AGX260 54 -- 74 -- 66 -- 50 -- 70 -- 58 -- 372 2AGX95 70 -- 74 16 66 -- 66 -- 70 16 74 -- 452 2AGX125 70 -- 74 16 66 -- 66 -- 70 16 74 -- 452 2AGX190 70 32 74 32 66 32 66 32 70 32 74 32 612 2AGX260 70 32 74 32 66 32 66 32 70 32 74 32 612 358-pin Flip Chip UBGA 572-pin Flip Chip FBGA 780-pin Flip Chip FBGA 1152-pin Flip Chip FBGA Note to Table 6-2: (1) The number of I/O pins do not include transceiver pins. In Arria II GX devices, the maximum number of I/O banks per side is four, excluding the configuration banks. All Arria II GX devices support migration across device density and package. When migrating between devices with a different number of I/O banks per side, it is the "B" bank which is removed or inserted. For example, when moving from a 12-bank device to an 8-bank device, the banks that are dropped are "B" banks, namely: 3B, 5B, 6B, and 8B. Similarly, when moving from an 8-bank device to a 12-bank device, the banks that are added are "B" banks, namely: 3B, 5B, 6B, and 8B. During migration from a smaller device to a larger device, the bank size increases or remains the same but never decreases. Figure 6-3 shows pin migration across device densities and packages. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 6: I/O Features in Arria II GX Devices Arria II GX I/O Structure 6-5 Table 6-3. Arria II GX Pin Migration across Densities Package 358-pin Flip Chip UBGA 572-pin Flip Chip FBGA 780-pin Flip Chip FBGA 1152-pin Flip Chip FBGA Device Pin Type 2AGX20 2AGX30 2AGX45 2AGX65 2AGX95 2AGX125 2AGX190 2AGX260 I/O 144 144 144 144 -- -- -- -- Clock 12 12 12 12 -- -- -- -- XCVR channel 4 4 4 4 -- -- -- -- I/O 240 240 240 240 248 248 -- -- Clock 12 12 12 12 12 12 -- -- XCVR channel 4 4 8 8 8 8 -- -- I/O -- -- 352 352 360 360 360 360 Clock -- -- 12 12 12 12 12 12 XCVR channel -- -- 8 8 12 12 12 12 I/O -- -- -- -- 440 440 600 600 Clock -- -- -- -- 12 12 12 12 XCVR channel -- -- -- -- 12 12 16 16 Note to Table 6-3: (1) Each transceiver channel consists of two Tx pins, two Rx pins and a transceiver clock pin. Arria II GX I/O Structure The I/O element in Arria II GX devices contains a bidirectional I/O buffer and I/O registers to support a completely embedded bidirectional SDR or DDR transfer. The IOEs are located in I/O blocks around the periphery of the Arria II GX device. There are up to four IOEs per row I/O block and four IOEs per column I/O block. The Arria II GX bidirectional IOE supports these features: (c) February 2009 Programmable input delay Programmable output current strength Programmable slew rate Programmable bus-hold Programmable pull-up resistor Open-drain output On-chip series termination with or without calibration On-chip differential termination PCI clamping diode Altera Corporation Arria II GX Device Handbook Volume 1 6-6 Chapter 6: I/O Features in Arria II GX Devices Arria II GX I/O Structure Figure 6-2 shows the Arria II GX IOE structure. Figure 6-2. Arria II GX IOE Structure OE Register OE from Core D PRN Q OE Register VCCIO PRN D Q VCCIO PCI Clamp Programmable Pull-Up Resistor Programmable Current Strength and Slew Rate Control Output Register PRN D Q Write Data from Core From OCT Calibration Block Output Buffer Output Register D On-Chip Termination Open Drain PRN Q Input Buffer clkout To Core Bus-Hold Circuit Input Register To Core PRN D Read Data to Core Synchronization Registers Q Input Register Input Register PRN D PRN Q D Q DQS CQn clkin f For more information about I/O registers and how they are used for memory applications, refer to the External Memory Interfaces in Arria II GX Devices chapter in volume 1 of the Arria II GX Device Handbook. 3.3-V I/O Interface Arria II GX I/O buffers are fully compatible with 3.3-V I/O standards. You can use them as transmitters or receivers in your system. The output high voltage (VOH ), output low voltage (V OL), input high voltage (VIH), and input low voltage (VIL ) levels meet the 3.3-V I/O standard specifications defined by EIA/JEDEC Standard JESD8-B with margin when the Arria II GX VCCIO voltage is powered by 3.3 V or 3.0 V. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 6: I/O Features in Arria II GX Devices Arria II GX I/O Structure 6-7 To ensure device reliability and proper operation when interfacing with a 3.3-V I/O system using Arria II GX devices, it is important to ensure that the absolute maximum ratings are not violated. Altera recommends performing IBIS simulation to determine that the overshoot and undershoot voltages are in the guidelines. There are several techniques that you can use to limit overshoot and undershoot voltages, though none are required. When using the Arria II GX device as a transmitter, techniques to limit overshoot and undershoot at the I/O pins include using slow slew rate and series termination. Transmission line effects that cause large voltage deviations at the receiver are associated with an impedance mismatch between the driver and transmission line. By matching the impedance of the driver to the characteristic impedance of the transmission line, you can significantly reduce overshoot voltage. You can use a series termination resistor placed physically close to the driver to match the total driver impedance to transmission line impedance. Other than 3.3-V LVTTL and 3.3-V LVCMOS I/O standards, Arria II GX devices support series on-chip termination for all LVTTL/LVCMOS I/O standards in all I/O banks. When using the Arria II GX device as a receiver, a technique you can use to limit overshoot, though not required, is using a clamping diode (on-chip or off-chip termination). Arria II GX devices provide an optional on-chip PCI clamp diode for I/O pins. You can use this diode to protect I/O pins against overshoot voltage. Another method for limiting overshoot is reducing the bank supply voltage (VCCIO) to 3.0 V. In this method, the clamp diode (on-chip or off-chip termination), though not required, can sufficiently clamp overshoot voltage to in the DC- and AC-input voltage specification. The clamped voltage can be expressed as the sum of the supply voltage (VCCIO ) and the diode forward voltage. By lowering VCCIO to 3.0 V, you can reduce overshoot and undershoot for all I/O standards, including 3.3-V LVTTL/LVCMOS, 3.0-V LVTTL/LVCMOS, and 3.0-V PCI/PCI-X. Additionally, lowering V CCIO to 3.0 V reduces power consumption. f For more information about absolute maximum rating and maximum allowed overshoot during transitions, refer to the Device Data Sheet chapter in volume 3 of the Arria II GX Device Handbook. External Memory Interfaces In addition to I/O registers in each IOE, Arria II GX devices also have dedicated registers and phase-shift circuitry on all I/O banks for interfacing with external memory interfaces. f For more information about external memory interfaces, refer to the External Memory Interfaces in Arria II GX Devices chapter in volume 1 of the Arria II GX Device Handbook. High-Speed Differential I/O with DPA Support Arria II GX devices have the following dedicated circuitry for high-speed differential I/O support: (c) February 2009 Differential I/O buffer Transmitter serializer Receiver deserializer Altera Corporation Arria II GX Device Handbook Volume 1 6-8 Chapter 6: I/O Features in Arria II GX Devices Arria II GX I/O Structure f Data realignment circuitry Dynamic phase aligner (DPA) Synchronizer (FIFO buffer) Phase-locked loops (PLLs) For more information about DPA support, refer to the High-Speed Differential I/O Interfaces with DPA in Arria II GX Devices chapter in volume 1 of the Arria II GX Device Handbook. Programmable Current Strength The output buffer for each Arria II GX device I/O pin has a programmable current-strength control for certain I/O standards. You can use programmable current strength to mitigate the effects of high signal attenuation due to a long transmission line or a legacy backplane. The LVTTL, LVCMOS, SSTL, and HSTL standards have several levels of current strength that you can control. Table 6-4 lists the programmable current strength settings. Table 6-4. Programmable Current Strength Settings (Note 1) I/O Standard IOL / IOH Current Strength Setting (mA) for Top, Bottom, and Right I/O Pins 3.3-V LVTTL (2) 12, [8], 4 3.3-V LVCMOS (2) [2] 3.0-V LVTTL 16, 12, 8, 4 3.0-V LVCMOS 16, 12, 8, 4 2.5-V LVTTL/LVCMOS 16, 12, 8, 4 1.8-V LVTTL/LVCMOS 16, 12, 10, 8, 6, 4, 2 1.5-V LVCMOS 16, 12, 10, 8, 6, 4, 2 1.2-V LVCMOS 12, 10, 8, 6, 4, 2 SSTL-2 Class I 12, 8 SSTL-2 Class II 16 SSTL-18 Class I 12, 10, 8 SSTL-18 Class II 16, 12 SSTL-15 Class I 12, 10, 8 HSTL-18 Class I 12, 10, 8 HSTL-18 Class II 16 HSTL-15 Class I 12, 10, 8 HSTL-15 Class II 16 HSTL-12 Class I 12, 10, 8 HSTL-12 Class II 16 Notes to Table 6-4: (1) The default current strength setting in the Quartus(R) II software is 50- OCT RS without calibration for all non-voltage reference and HSTL/SSTL Class I I/O standards. The default setting is 25- OCT RS without calibration for HSTL/SSTL Class II I/O standards. (2) The default current strength setting in the Quartus II software is the current strength, shown in brackets []. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 6: I/O Features in Arria II GX Devices Arria II GX I/O Structure 1 6-9 Altera recommends performing IBIS or SPICE simulations to determine the right current strength setting for your specific application. Programmable Slew Rate Control The output buffer for each Arria II GX device regular- and dual-function I/O pin has a programmable output slew rate control that you can configure for low-noise or high-speed performance. A faster slew rate provides high-speed transitions for high-performance systems. A slow slew rate can help reduce system noise, but adds a nominal delay to the rising and falling edges. Each I/O pin has an individual slew rate control, allowing you to specify the slew rate on a pin-by-pin basis. 1 You cannot use the programmable slew rate feature when using OCT RS. The Quartus II software allows two settings for programmable slew rate control: fast and slow. In the Quartus II Assignment Editor, setting 2 = fast, and 0 = slow. Programmable slew rate is available for 8 mA current strength and above. You can use faster slew rates to improve the available timing margin in memory-interface applications or when the output pin has high-capacitive loading. Altera recommends performing IBIS or SPICE simulations to determine the right slew rate setting for your specific application. Open-Drain Output Arria II GX devices provide an optional open-drain output (equivalent to an open collector output) for each I/O pin. When configured as open drain, the logic value of the output is either high-Z or 0. Typically, an external pull-up resistor is needed to provide logic high. Bus Hold Each Arria II GX device I/O pin provides an optional bus-hold feature. Bus-hold circuitry can weakly hold the signal on an I/O pin at its last-driven state. Because the bus-hold feature holds the last-driven state of the pin until the next input signal is present, you do not need an external pull-up or pull-down resistor to hold a signal level when the bus is tri-stated. Bus-hold circuitry also pulls non-driven pins away from the input threshold voltage where noise can cause unintended high-frequency switching. You can select this feature individually for each I/O pin. The bus-hold output drives no higher than VCCIO to prevent over-driving signals. If you enable the bus-hold feature, you cannot use the programmable pull-up option. The bus-hold feature is disabled if the I/O pin is configured for differential signals. Bus-hold circuitry uses a resistor with a nominal resistance to weakly pull the last-driven state. Bus-hold circuitry is active only after configuration. When going into user mode, the bus-hold circuit captures the value on the pin present at the end of configuration. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 6-10 Chapter 6: I/O Features in Arria II GX Devices Arria II GX I/O Structure Programmable Pull-Up Resistor Each Arria II GX device I/O pin provides an optional programmable pull-up resistor during user mode. If you enable this feature for an I/O pin, the pull-up resistor weakly holds the I/O to the VCCIO level. Programmable pull-up resistors are only supported on user I/O pins and are not supported on dedicated configuration pins, JTAG pins, or dedicated clock pins. If you enable the programmable pull-up option, you cannot use the bus-hold feature. Programmable Pre-Emphasis Arria II GX IV LVDS transmitters support programmable pre-emphasis to compensate the frequency dependent attenuation of the transmission line. The Quartus II software allows two settings for programmable pre-emphasis control--0 and 1--where 0 is pre-emphasis off and 1 is pre-emphasis on. The default setting is 1. f For more information about programmable pre-emphasis, refer to the High-Speed Differential I/O Interfaces with DPA in the Arria II GX Devices chapter in volume 1 of the Arria II GX Device Handbook. Programmable Differential Output Voltage Arria II GX LVDS transmitters support programmable VOD. Programmable V OD settings allow you to adjust output eye height to optimize trace length and power consumption. A higher VOD swing improves voltage margins at the receiver end, while a smaller VOD swing reduces power consumption. The Quartus II software allows three settings for programmable V OD: low, medium, and high. f For more information about programmable VOD, refer to the High-Speed Differential I/O Interfaces with DPA in the Arria II GX Devices chapter in volume 1 of the Arria II GX Device Handbook. MultiVolt I/O Interface Arria II GX architecture supports the MultiVolt I/O interface feature that allows Arria II GX devices in all packages to interface with systems of different supply voltages. You can connect the VCCIO pins to a 1.2-, 1.5-, 1.8-, 2.5-, 3.0-, or 3.3-V power supply, depending on the output requirements. The output levels are compatible with systems of the same voltage as the power supply. (For example, when VCCIO pins are connected to a 1.5-V power supply, the output levels are compatible with 1.5-V systems). Arria II GX VCCPD power pins must be connected to a 2.5-, 3.0-, or 3.3-V power supply. Using these power pins to supply pre-driver power to the output buffers increases the performance of the output pins. Table 6-5 summarizes Arria II GX MultiVolt I/O support. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 6: I/O Features in Arria II GX Devices Arria II GX OCT Support 6-11 Table 6-5. Arria II GX MultiVolt I/O Support (Note 1), (2) Input Signal (V) VCCIO (V) Output Signal (V) 1.2 1.5 1.8 2.5 3.0 3.3 1.2 1.5 1.8 2.5 3.0 3.3 1.2 v -- -- -- -- -- v -- -- -- -- -- 1.5 -- v v -- -- -- -- v -- -- -- -- 1.8 -- v v -- -- -- -- -- v -- -- -- 2.5 -- -- -- v v -- -- -- -- v -- -- 3.0 -- -- -- v v -- -- -- -- -- v -- 3.3 -- -- -- v v v -- -- -- -- -- v Notes to Table 6-5: (1) The pin current may be slightly higher than the default value. You must verify that the driving device's VOL maximum and VOH minimum voltages do not violate the applicable Arria II GX VIL maximum and VIH minimum voltage specifications. (2) Altera recommends that you use an external clamp diode on the column I/O pins when the input signal is 3.0 V or 3.3 V. Arria II GX OCT Support Arria II GX devices feature series on-chip termination to provide I/O impedance matching and termination capabilities. On-chip termination maintains signal quality, saves board space, and reduces external component costs. Arria II GX devices support on-chip series (RS) with or without calibration and on-chip differential termination (R D) for differential LVDS I/O standards. Arria II GX devices support OCT in all user I/O banks by selecting one of the OCT I/O standards. Arria II GX devices support OCT RS in the same I/O bank with different I/O standards if they use the same VCCIO supply voltage. You can independently configure each I/O in an I/O bank to support OCT R S or programmable current strength. 1 You cannot configure both OCT R S and programmable current strength for the same I/O buffer. A pair of RUP and RDN pins are available in a given I/O bank for series calibrated termination. RUP and R DN pins share the same V CCIO and GND, respectively, with the I/O bank where they are located. RUP and RDN pins are dual-purpose I/Os, and function as regular I/Os if you do not use the calibration circuit. When used for calibration, RUP and RDN pins are connected to VCCIO or GND, respectively, through an external 25- 1% or 50-1% resistor for an on-chip series termination value of 25 or 50 , respectively. On-Chip Series (RS) Termination without Calibration Arria II GX devices support driver-impedance matching to provide the I/O driver with controlled output impedance that closely matches the impedance of the transmission line. As a result, you can significantly reduce reflections. Arria II GX devices support on-chip series termination for single-ended I/O standards (see Figure 6-3). The R S shown in Figure 6-3 is the intrinsic impedance of output transistors. The typical RS values are 25 and 50 . (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 6-12 Chapter 6: I/O Features in Arria II GX Devices Arria II GX OCT Support Figure 6-3. Arria II GX On-Chip Series Termination without Calibration Arria II GX Driver Series Termination Receiving Device VCCIO RS ZO = 50 RS GND To use on-chip termination for: SSTL Class I standard, you must select the 50- on-chip series termination setting, thus eliminating the external 25- RS (to match the 50- transmission line). SSTL Class II standard, you must select the 25- on-chip series termination setting (to match the 50- transmission line and the near-end external 50- pull-up to VTT ). On-Chip Series Termination with Calibration Arria II GX devices support on-chip series termination with calibration in all banks. The on-chip series termination calibration circuit compares the total impedance of the I/O buffer to the external 25- 1% or 50- 1% resistors connected to the RUP and RDN pins, and dynamically enables or disables the transistors until they match. The R S shown in Figure 6-4 is the intrinsic impedance of transistors. Calibration occurs at the end of device configuration. When the calibration circuit finds the correct impedance, it powers down and stops changing the characteristics of the drivers. Figure 6-4. Arria II GX On-Chip Series Termination with Calibration Arria II GX Driver Series Termination Receiving Device VCCIO RS ZO = 50 RS GND Table 6-6 lists the I/O standards that support on-chip series termination with calibration. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 6: I/O Features in Arria II GX Devices Arria II GX OCT Support 6-13 Table 6-6. Selectable I/O Standards with On-Chip Series Termination with Calibration On-Chip Series Termination Setting I/O Standard Right I/O Top and Bottom I/O Unit 50 50 25 25 50 50 25 25 50 50 25 25 50 50 25 25 50 50 25 25 SSTL-2 Class I 50 50 SSTL-2 Class II 25 25 SSTL-18 Class I 50 50 SSTL-18 Class II 25 25 3.0-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS 1.2-V LVCMOS SSTL-15 Class I 50 50 HSTL-18 Class I 50 50 HSTL-18 Class II 25 25 HSTL-15 Class I 50 50 HSTL-15 Class II 25 25 HSTL-12 Class I 50 50 HSTL-12 Class II 25 25 LVDS Input On-Chip Termination (RD) All I/O banks in Arria II GX devices support input differential on-chip termination R D with a nominal resistance value of 100 , as shown in Figure 6-5. However, not all input differential pins support on-chip termination RD. Figure 6-5. Differential Input On-Chip Termination Transmitter Receiver ZO = 50 100 ZO = 50 (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 6-14 Chapter 6: I/O Features in Arria II GX Devices Arria II GX OCT Calibration f For more information about differential on-chip termination, refer to the High-Speed Differential I/O Interfaces with DPA in Arria II GX Devices chapter in volume 1 of the Arria II GX Device Handbook. Arria II GX OCT Calibration Arria II GX devices support calibrated on-chip series termination (R S) on all I/O pins. You can calibrate the Arria II GX I/O bank with any of the three OCT calibration blocks (CB) available in the devices. OCT Calibration Block The three OCT calibration blocks reside in the top-left, top-right, and bottom-left corners of the device. An OCT calibration block has the same VCCIO as the I/O bank that contains the block. OCT RS calibration is supported on all user I/O banks with different VCCIO voltage standards, up to the number of available OCT calibration blocks. You can configure I/O banks to receive calibrated codes from any OCT calibration block with the same VCCIO. All I/O banks with the same VCCIO can share one OCT calibration block, even if that particular I/O bank has an OCT calibration block. Arria II GX Termination Schemes for I/O Standards The following section describes the different termination schemes for I/O standards used in Arria II GX devices. Single-Ended I/O Standards Termination Voltage-referenced I/O standards require both an input reference voltage, VREF, and a termination voltage, VTT. The reference voltage of the receiving device tracks the termination voltage of the transmitting device. Figure 6-6 shows the details of SSTL I/O termination on Arria II GX devices. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 6: I/O Features in Arria II GX Devices Arria II GX Termination Schemes for I/O Standards 6-15 Figure 6-6. Arria II GX SSTL I/O Standard Termination Termination SSTL Class I SSTL Class II Arria II GX Arria II GX VTT External On-Board Termination 25 50 50 50 50 VREF VREF Receiver Transmitter Arria II GX Series OCT 50 OCT Transmit VTT VTT 50 25 VTT Arria II GX Series OCT 25 50 Receiver Transmitter VTT VTT 50 50 50 50 VREF VREF Transmitter Receiver Receiver Transmitter Figure 6-7 shows the details of HSTL I/O termination on Arria II GX devices. Figure 6-7. Arria II GX HSTL I/O Standard Termination Termination HSTL Class II HSTL Class I VTT Arria II GX Arria II GX External On-Board Termination VTT 50 50 VREF Transmitter Arria II GX Series OCT 50 Transmitter (c) February 2009 VREF Receiver Transmitter Arria II GX Series OCT 25 VTT 50 Altera Corporation Receiver VTT VTT 50 50 50 VREF 50 VREF OCT Transmit VTT 50 50 50 Receiver Transmitter Receiver Arria II GX Device Handbook Volume 1 6-16 Chapter 6: I/O Features in Arria II GX Devices Arria II GX Termination Schemes for I/O Standards Differential I/O Standards Termination Arria II GX devices support differential SSTL-2 and SSTL-18, differential HSTL-18, HSTL-15, HSTL-12, LVDS, LVPECL, RSDS, and mini-LVDS. Figure 6-8 through Figure 6-14 show the details of various differential I/O terminations on Arria II GX devices. Figure 6-8 shows the details of differential SSTL I/O standard termination on Arria II GX devices. Figure 6-8. Arria II GX Differential SSTL I/O Standard Termination Termination Differential SSTL Class II Differential SSTL Class I VTT VTT External On-Board Termination 50 Arria II GX 25 25 VTT VTT 50 Arria II GX Receiver 50 Receiver Transmitter Differential SSTL Class I Differential SSTL Class II Arria II GX Series OCT 50 Arria II GX Series OCT 25 VTT VTT 50 Z0= 50 OCT VTT 50 Z0= 50 Arria II GX Device Handbook Volume 1 50 Z0= 50 VTT Transmitter 50 50 50 25 50 Transmitter 50 50 25 50 VTT VTT 50 Z0= 50 Receiver Receiver Transmitter (c) February 2009 Altera Corporation Chapter 6: I/O Features in Arria II GX Devices Arria II GX Termination Schemes for I/O Standards 6-17 Figure 6-9 shows the details of differential HSTL I/O standard termination on Arria II GX devices. Figure 6-9. Arria II GX Differential HSTL I/O Standard Termination Termination Differential HSTL Class II Differential HSTL Class I VTT VTT 50 Arria II GX External On-Board Termination 50 Arria II GX 50 50 50 50 50 Receiver Receiver Transmitter Differential HSTL Class I Differential HSTL Class II Arria II GX Series OCT 50 Arria II GX Series OCT 25 VTT VTT 50 Z0= 50 Z0= 50 VTT OCT 50 VTT 50 50 Z0= 50 Z0= 50 Transmitter 50 50 50 Transmitter VTT VTT VTT VTT Receiver Transmitter Receiver LVDS The LVDS I/O standard is a differential high-speed, low-voltage swing, low-power, general-purpose I/O interface standard. In Arria II GX devices, the LVDS I/O standard requires a 2.5-V V CCIO level. The LVDS input buffer requires 2.5-V VCCPD. LVDS requires a 100- termination resistor between the two signals at the input buffer. Arria II GX devices provide an optional 100- differential termination resistor in the device using on-chip differential termination. The external-resistor topology is for a data rate of up to 700 Mbps. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 6-18 Chapter 6: I/O Features in Arria II GX Devices Arria II GX Termination Schemes for I/O Standards Figure 6-10 shows the details of LVDS termination in Arria II GX devices. Figure 6-10. Arria II GX LVDS I/O Standard Termination (Note 1) Termination LVDS Differential Outputs Differential Inputs External On-Board Termination 50 100 50 Differential Inputs Differential Outputs 50 OCT Receive (Dedicated LVDS Output) 100 50 Arria II GX OCT OCT Receive (Single-Ended LVDS Output with Three Resistor Network, LVDS_E_3R) (1) Single-Ended Outputs Differential Inputs 50 Rs 100 Rp Rs 50 External Resistor Arria II GX OCT Note to Figure 6-10: (1) Rp = 170 and Rs = 120 for LVDS_E_3R. Differential LVPECL Arria II GX devices support the LVPECL I/O standard on input clock pins only. LVPECL output operation is not supported. LVDS input buffers are used to support LVPECL input operation. AC-coupling is required when the LVPECL common mode voltage of the output buffer is higher than Arria II GX LVPECL input common mode voltage. Figure 6-11 shows the AC-coupled termination scheme. The 50- resistors used at the receiver end are external to the device. Figure 6-11. LVPECL AC-Coupled Termination LVPECL Output Buffer Arria II GX LVPECL Input Buffer 0.1 F 0.1 F Arria II GX Device Handbook Volume 1 ZO = 50 ZO = 50 VICM 50 50 (c) February 2009 Altera Corporation Chapter 6: I/O Features in Arria II GX Devices Arria II GX Termination Schemes for I/O Standards 6-19 Arria II GX devices support DC-coupled LVPECL if the LVPECL output common mode voltage is in the Arria II GX LVPECL input buffer specification (see Figure 6-12). Figure 6-12. LVPECL DC-Coupled Termination Arria II GX LVPECL Input Buffer LVPECL Output Buffer ZO = 50 100 ZO = 50 RSDS Arria II GX devices support the RSDS output standard with a data rate of up to 360 Mbps using LVDS output buffer types. Arria II GX devices supports dedicated RSDS, RSDS with a one-resistor network, and RSDS with a three-resistor network. Two single-ended output buffers are used for external one- or three-resistor networks, as shown in Figure 6-13. Figure 6-13. Arria II GX RSDS I/O Standard Termination (Note 1) One-Resistor Network (RSDS_E_1R) Termination Three-Resistor Network (RSDS_E_3R) 1 inch External On-Board Termination RP 1 inch 50 50 RS 100 RP 50 50 100 RS Receiver Transmitter OCT 50 50 Transmitter Receiver Arria II GX OCT 1 inch RS Arria II GX OCT 1 inch RP Transmitter RP 100 RS Receiver Transmitter 50 50 100 Receiver Note to Figure 6-13: (1) The RS and RP values are pending characterization. A resistor network is required to attenuate the LVDS output-voltage swing to meet RSDS specifications. You can modify the three-resistor network values to reduce power or improve the noise margin. The resistor values chosen should satisfy the equation shown in Equation 6-1. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 6-20 Chapter 6: I/O Features in Arria II GX Devices Arria II GX Termination Schemes for I/O Standards Equation 6-1. R RS x P 2 R RS + 1 f = 50 P 2 Altera recommends that you perform additional simulations using IBIS models to validate that custom resistor values meet the RSDS requirements. For more information about the RSDS I/O standard, refer to the RSDS Specification from the National Semiconductor website at www.national.com. Mini-LVDS Arria II GX devices support the mini-LVDS output standard with a data rate up to 400 Mbps using LVDS-type output buffers. Arria II GX devices support dedicated RSDS as well as RSDS with a one-resistor network or a three-resistor network. Two single-ended output buffers are used for external one- or three-resistor networks, as shown in Figure 6-14. Figure 6-14. Arria II GX mini-LVDS I/O Standard Termination (Note 1) One-Resistor Network (mini-LVDS_E_1R) Termination Three-Resistor Network (mini-LVDS_E_3R) 1 inch External On-Board Termination R P 50 50 1 inch RS 100 50 RS Transmitter Receiver 1 inch Arria II GX OCT Arria II GX OCT RS R 50 P 50 R P 100 RS OCT Transmitter 100 Transmitter Receiver 1 inch 50 R P 50 50 100 Transmitter Receiver Receiver Note to Figure 6-14: (1) The RS and RP values are pending characterization. A resistor network is required to attenuate the LVDS output voltage swing to meet mini-LVDS specifications. You can modify the three-resistor network values to reduce power or improve noise margin. The resistor values chosen should satisfy the equation shown in Equation 6-2. Equation 6-2. R RS x P 2 R RS + Arria II GX Device Handbook Volume 1 = 50 P 2 (c) February 2009 Altera Corporation Chapter 6: I/O Features in Arria II GX Devices Arria II GX Design Considerations 1 f 6-21 Altera recommends that you perform additional simulations using IBIS models to validate that custom resistor values meet the RSDS requirements. For more information about the mini-LVDS I/O standard, see the mini-LVDS Specification from the Texas Instruments website at www.ti.com. Arria II GX Design Considerations While Arria II GX devices feature various I/O capabilities for high-performance and high-speed system designs, the following items require attention to ensure the success of these designs: "I/O Termination" on page 6-21 "I/O Bank Restrictions" on page 6-22 "I/O Placement Guidelines" on page 6-22 I/O Termination This section describes I/O termination requirements for single-ended and differential I/O standards. Single-Ended I/O Standards Although single-ended, non-voltage-referenced I/O standards do not require termination, impedance matching is necessary to reduce reflections and improve signal integrity. Voltage-referenced I/O standards require both an input reference voltage, VREF and a termination voltage, VTT. The reference voltage of the receiving device tracks the termination voltage of the transmitting device. Each voltage-referenced I/O standard requires a specific termination setup. For example, a proper resistive signal termination scheme is critical in SSTL2 standards to produce a reliable DDR memory system with superior noise margin. Arria II GX on-chip series termination provides the convenience of no external components. When optimizing OCT for use in typical transmission line environments, the RS impedance must be equal to or less than the transmission line impedance for optimal performance. In ideal applications, setting the OCT impedance to match the transmission line impedance avoids reflections. Alternatively, you can use external pull-up resistors to terminate the voltage-referenced I/O standards such as SSTL and HSTL. Differential I/O Standards Differential I/O standards typically require a termination resistor between the two signals at the receiver. The termination resistor must match the differential load impedance of the signal line. Arria II GX devices provide an optional differential on-chip resistor when using LVDS. f (c) February 2009 For PCB layout guidelines, refer to AN 224: High-Speed Board Layout Guidelines and AN 315: Guidelines for Designing High Speed FPGA PCBs. Altera Corporation Arria II GX Device Handbook Volume 1 6-22 Chapter 6: I/O Features in Arria II GX Devices Arria II GX Design Considerations I/O Bank Restrictions Each I/O bank can simultaneously support multiple I/O standards. The following sections provide guidelines for mixing non-voltage-referenced and voltage-referenced I/O standards in Arria II GX devices. Non-Voltage-Referenced Standards Each Arria II GX device I/O bank has its own VCCIO pins and supports only one VCCIO, either 1.2, 1.5, 1.8, 2.5, 3.0, or 3.3 V. An I/O bank can simultaneously support any number of input signals with different I/O standard assignments, as shown in Table 6-1 on page 6-2. For output signals, a single I/O bank supports non-voltage-referenced output signals that drive at the same voltage as VCCIO. Because an I/O bank can only have one VCCIO value, it can only drive out the value for non-voltage-referenced signals. For example, an I/O bank with a 2.5-V VCCIO setting can support 2.5-V standard inputs and outputs and 3.0-V LVCMOS inputs (but not output or bidirectional pins). Voltage-Referenced Standards To accommodate voltage-referenced I/O standards, each Arria II GX device's user I/O bank has a dedicated VREF pin. Each bank can only have a single VCCIO voltage level and a single VREF voltage level at a given time. An I/O bank featuring single-ended or differential standards can support voltage-referenced standards as long as all voltage-referenced standards use the same VREF setting. Voltage-referenced bidirectional and output signals must be the same as the I/O bank's VCCIO voltage. For example, you can only place SSTL-2 output pins in an I/O bank with a 2.5-V VCCIO. Mixing Voltage-Referenced and Non-Voltage-Referenced Standards An I/O bank can support both non-voltage-referenced and voltage-referenced pins by applying each of the rule sets individually. For example, an I/O bank can support SSTL-18 inputs and 1.8-V inputs and outputs with a 1.8-V V CCIO and a 0.9-V VREF . Similarly, an I/O bank can support 1.5-V standards, 1.8-V inputs (but not outputs), and HSTL and HSTL-15 I/O standards with a 1.5-V VCCIO and 0.75-V VREF . I/O Placement Guidelines This section provides I/O placement guidelines for the programmable I/O standards supported by Arria II GX devices and includes essential information for designing systems using an Arria II GX device's selectable I/O capabilities. 3.3-V, 3.0-V, and 2.5-V LVTTL/LVCMOS Tolerance Guidelines Altera recommends the following techniques when you use 3.3-, 3.0-, and 2.5-V I/O standards to limit overshoot and undershoot at I/O pins: Low drive strength or series termination--The I/O driver's impedance must be equal to or greater than the board trace impedance to minimize overshoot and undershoot at the un-terminated receiver end. If high driver strength (lower driver impedance) is needed, Altera recommends series termination at the driver end (on-chip or off-chip). Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 6: I/O Features in Arria II GX Devices Document Revision History 6-23 Output slew rate--Arria II GX devices have two levels of slew rate control for single-ended output buffers. Slow slew rate can significantly reduce the overshoot and undershoot in the system at the cost of slightly slower performance. Input clamping diodes--Arria II GX I/Os have on-chip clamping diodes. When you use clamping diodes, the floating well of the I/O is clamped to V CCN . As a result, the Arria II GX device might draw extra input leakage current from the external input driver. This may violate the hot-socket DC- and AC-current specification and increase power consumption. With the clamping diode enabled, the Arria II GX device supports a maximum DC current of 8 mA. Pin Placement Guideline You are advised to create a Quartus II design, enter your device I/O assignments, and compile your design to validate your pin placement. The Quartus II software checks your pin connections with respect to I/O assignment and placement rules to ensure proper device operation. These rules are dependent on device density, package, I/O assignments, voltage assignments, and other factors that are not described in this chapter. f For information about pin placement with respect to VREF, LVDS, mini-LVDS, and RSDS, refer to the I/O Management chapter in volume 2 of the Quartus II Development Software Handbook. Document Revision History Table 6-7 shows the revision history for this document. Table 6-7. Document Revision History Date and Document Version February 2009, v1.0 (c) February 2009 Changes Made Initial release. Altera Corporation Summary of Changes -- Arria II GX Device Handbook Volume 1 6-24 Arria II GX Device Handbook Volume 1 Chapter 6: I/O Features in Arria II GX Devices Document Revision History (c) February 2009 Altera Corporation 7. External Memory Interfaces in Arria II GX Devices AIIGX51007-1.1 Introduction Altera's Arria (R) II GX FPGAs provide an efficient architecture to quickly and easily fit wide external memory interfaces with their small modular I/O bank structure. The I/Os are designed to provide flexible and high-performance support for existing and emerging external double data rate (DDR) memory standards, such as DDR3, DDR2, DDR SDRAM, and QDRII SRAM. The Arria II GX FPGA supports DDR external memory on the top, bottom, and right I/O banks. The high-performance memory interface solution includes a self-calibrating megafunction (ALTMEMPHY), optimized to take advantage of the Arria II GX I/O structure and the Quartus(R) II TimeQuest timing analyzer. The ALTMEMPHY megafunction provides the total solution for the highest reliable frequency of operation across process, voltage, and temperature (PVT) variations. This chapter includes the following sections: "Arria II GX Memory Interfaces Pin Support" on page 7-3 "Arria II GX External Memory Interface Features" on page 7-15 Table 7-1 summarizes the maximum clock rate Arria II GX devices support with external memory devices. Table 7-1. Arria II GX Maximum Clock Rate Support for External Memory Interfaces with Half-Rate PHY (Note 1), (2) C4 Speed Grade (MHz) C5 Speed Grade (MHz) C6 Speed Grade (MHz) Memory Standards Row/Column I/Os Hybrid Mode Row/Column I/Os Hybrid Mode Row/Column I/Os Hybrid Mode DDR3 SDRAM (3) 300 -- -- -- -- -- DDR2 SDRAM (4) 300 (5) 267 (6) 267 (7) 200 200 200 DDR SDRAM (4) 200 200 200 200 200 167 QDRII SRAM (8), (9) 250 200 250 200 200 200 Notes to Table 7-1: (1) These numbers are preliminary until characterization is final. The supported operating frequencies listed here are memory interface maximums for the FPGA device family. Your design's actual achievable performance is based on design- and system-specific factors, as well as static timing analysis of the completed design. (2) The maximum clock rates are applicable to Class I termination. The maximum clock rates are lower for Class II termination. (3) Arria II GX devices support DDR3 SDRAM components only as read and write leveling capability is not available in Arria II GX devices, hence DDR3 DIMMs cannot be supported. Interface with multiple DDR3 SDRAM components requires component arrangement according to the DDR2 DIMM tree topology. (4) This applies to interfaces with both components and single-rank, unbuffered modules. (5) The 300-MHz DDR2 interface requires the use of 400-MHz DDR2 SDRAM modules or components. (6) The 267-MHz DDR2 hybrid mode interface requires the use of 400-MHz DDR2 SDRAM modules or components. (7) The 267-MHz DDR2 interface requires the use of 333-MHz DDR2 SDRAM modules or components. (8) QDRII SRAM supports 1.8-V and 1.5-V HSTL I/O standards. However, Altera recommends using the 1.8-V HSTL I/O standard for maximum performance because of the higher I/O drive strength. (9) Arria II GX devices feature I/Os capable of electrical support for QDRII. However, Altera does not currently supply a controller or PHY megafunction for QDRII interfaces. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 1 7-2 Chapter 7: External Memory Interfaces in Arria II GX Devices Introduction Figure 7-1 shows a memory interface data path overview. Figure 7-1. External Memory Interface Data Path Overview (Note 1), (2) Memory Arria II GX FPGA Postamble Enable Postamble Clock Alignment Registers & DPRAM (3) DLL DQS Logic Block Postamble Control Circuit DQS Enable Circuit 2n DQS (Read) (4) 2n DDR Input Registers Synchronization Registers n DQ (Read) (4) n 2n Resynchronization Clock Clock Management & Reset DQ Write Clock DQS Write Clock 2 DQ (Write) (4) DDR Output and Output Enable Registers DQS (Write) (4) DDR Output and Output Enable Registers Notes to Figure 7-1: (1) (2) (3) (4) You can bypass each register block. Shaded blocks are implemented in the I/O element (IOE). The memory blocks used for each memory interface may differ slightly. The alignment register is implemented in the core logic. These signals may be bidirectional or unidirectional, depending on the memory standard. When bidirectional, the signal is active during both read and write operations. This chapter describes the hardware features in Arria II GX devices that facilitate high-speed memory interfacing for the DDR memory standard including delay-locked loops (DLLs). Memory interfaces also use I/O features such as on-chip termination (OCT), programmable input delay chains, programmable output delay, slew rate adjustment, and programmable drive strength. f For more information about any of the above-mentioned features, refer to the I/O Features in Arria II GX Devices chapter in volume 1 of the Arria II GX Device Handbook. The ALTMEMPHY megafunction instantiates a phase-locked loop (PLL) and PLL reconfiguration logic to adjust the phase shift based on VT variation. f For more information about the ALTMEMPHY support for Arria II GX devices, refer to the External Memory PHY Interface Megafunction User Guide (ALTMEMPHY). f For more information about the Arria II GX PLL, refer to the Clock Networks and PLLs in Arria II GX Devices chapter in volume 1 of the Arria II GX Device Handbook. Arria II GX Device Handbook Volume 1 (c) March 2009 Altera Corporation Chapter 7: External Memory Interfaces in Arria II GX Devices Arria II GX Memory Interfaces Pin Support 7-3 Arria II GX Memory Interfaces Pin Support A typical memory interface requires data (D, Q, or DQ), data strobe (DQS/CQ and DQSn/CQn), address, command, and clock pins. Some memory interfaces use data mask (DM or BWSn) pins to enable write masking. This section describes how Arria II GX devices support all these pins. Table 7-2 summarizes the pin connections between an Arria II GX device and an external memory device. Table 7-2. Arria II GX Memory Interfaces Pin Utilization Pin Description Memory Standard Arria II GX Pin Utilization Read Data All DQ Write Data All DQ (1) Parity, DM, BWSn, ECC All DQ (1), (2) DDR3 SDRAM DDR2 SDRAM (with differential DQS signaling) (3) Differential DQS/DQSn (also used as write data clock) DDR2 SDRAM (with single-ended DQS signaling) (3) Single-ended DQS (also used as write data clock) Read Data Strobes/Clocks DDR SDRAM QDRII SRAM Complementary CQ/CQn QDRII SRAM (4) Any DQS and DQSn pin pairs associated with the DQ groups used for the write data pins (1) Write Data Clocks Memory Clocks (for Address and Commands) (5) DDR3 SDRAM DDR2 SDRAM DDR SDRAM Any unused DQ or DQS pins with DIFFIO_RX or DIFFIN capability for the mem_clk[n:0] and mem_clk_n[n:0] signals. Notes to Table 7-2: (1) If the write data signals are unidirectional, connect them, including the data mask pins, to a separate DQS/DQ group other than the read DQS/DQ group. Connect the write clock to the DQS and DQSn pin-pair associated with that DQS/DQ group. Do not use the CQ and CQn pin-pair as write clocks. (2) The BWSn and DM pins need to be part of the write DQS/DQ group, while parity and ECC pins need to be part of the read DQS/DQ group. (3) DDR2 SDRAM supports either single-ended or differential DQS signaling. (4) QDRII SRAM devices use the K/K# clock pin-pair to latch write data, address, and command signals. The clocks must be part of the DQS/DQ group and follow the write data clock rules in this case. (5) ALTMEMPHY megafunction implementation for a DDR3, DDR2, or DDR SDRAM interface requires that you place all memory clock pin-pairs in a single DQ group of adequate width to minimize skew. For example, DIMMs requiring three memory clock pin-pairs need to use a x4 DQS/DQ group. DDR3, DDR2, and DDR SDRAM devices use CK and CK# signals to capture the address and command signals. Generate these signals to mimic the write-data strobe using Arria II GX DDR I/O registers (DDIOs) to ensure that timing relationships between CK/CK# and DQS signals (tDQSS, tDSS, and tDSH in DDR3, DDR2, and DDR SDRAM devices) are met. QDRII SRAM devices use the same clock (K/K#) to capture the write data, address, and command signals. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 1 7-4 Chapter 7: External Memory Interfaces in Arria II GX Devices Arria II GX Memory Interfaces Pin Support Memory clock pins in Arria II GX devices are generated using a DDIO register going to differential output pins (see Figure 7-2). The Arria II GX pins marked with DIFFIN or DIFFIO_RX prefixes in the pin table support the differential output function as well, therefore they can be used as memory clock pins, as mentioned in Table 7-2 on page 7-3. Figure 7-2. Memory Clock Generation (Note 1), (2), (3) FPGA LEs I/O Elements VCC D Q 1 D Q mem_clk (2) 0 mem_clk_n (2) System Clock (3) Notes to Figure 7-2: (1) Refer to Table 7-2 on page 7-3 for the pin location requirements for these pins. (2) The mem_clk[0] and mem_clk_n[0] pins for DDR3, DDR2, and DDR SDRAM interfaces use the I/O input buffer for feedback; therefore, bidirectional I/O buffers are used for these pins. For memory interfaces using a differential DQS input, the input feedback buffer is configured as differential input; for memory interfaces using a single-ended DQS input, the input buffer is configured as a single-ended input. Using a single-ended input feedback buffer requires that the I/O standard's VREF voltage is provided to that I/O bank's VREF pins. (3) Global or regional clock networks are required for memory output clock generation to minimize jitter. Arria II GX devices offer differential input buffers for differential read-data strobe and clock operations. In addition, Arria II GX devices also provide an independent DQS logic block for each CQn pin for complementary read-data strobe and clock operations. In the Arria II GX pin tables, the differential DQS pin pairs are denoted as DQS and DQSn pins, while the complementary CQ signals are denoted as CQ and CQn pins. DQSn and CQn pins are marked separately in the pin table. Each CQn pin connects to a DQS logic block and the shifted CQn signals go to the negative-edge input registers in the DQ I/O element registers. DQ pins can be bidirectional signals, as in DDR3, DDR2, and DDR SDRAM, or unidirectional signals, as in QDRII SRAM devices. Connect the unidirectional read-data signals to Arria II GX DQ pins and the unidirectional write-data signals to a different DQS/DQ group than the read DQS/DQ group. Furthermore, the write clocks must be assigned to the DQS/DQSn pins associated to this write DQS/DQ group. Do not use the CQ/CQn pin-pair for write clocks. 1 Using a DQS/DQ group for the write-data signals minimizes output skew and allows vertical migration. The DQS and DQ pin locations are fixed in the pin table. Memory interface circuitry is available in every Arria II GX I/O bank that does not support transceivers. All memory interface pins support the I/O standards required to support DDR3, DDR2, DDR SDRAM, and QDRII SRAM devices. Arria II GX Device Handbook Volume 1 (c) March 2009 Altera Corporation Chapter 7: External Memory Interfaces in Arria II GX Devices Arria II GX Memory Interfaces Pin Support 7-5 The Arria II GX device supports DQS and DQ signals with DQ bus modes of x4, x8/x9, x16/x18, or x32/x36. The DDR, DDR2, and DDR3 interfaces use one DQS pin for each x8 group; for example, an interface with a x72 DDR2 DIMM needs nine DQS pins. When any of these pins are not used for memory interfacing, you can use them as user I/Os. In addition, you can use any DQSn or CQn pins not used for clocking as DQ (data) pins. Table 7-3 lists pin support per DQS/DQ bus mode, including the DQS/CQ and DQSn/CQn pin pair. Table 7-3. Arria II GX DQS/DQ Bus Mode Pins Typical Number of Data Pins per Group Maximum Number of Data Pins per Group (1) DQSn Support CQn Support Parity or DM (Optional) x4 Yes No No (5) 4 5 x8/x9 (2) Yes Yes Yes 8 or 9 11 x16/x18 (3) Yes Yes Yes 16 or 18 23 x32/x36 (4) Yes Yes Yes 32 or 36 47 Mode Notes to Table 7-3: (1) This represents the maximum number of DQ pins (including parity and data mask pins) connected to the DQS bus network with single-ended DQS signaling. When you use differential or complementary DQS signaling, the maximum number of data-per-group decreases by one. This number may vary per DQS/DQ group in a particular device. For the DDR, DDR2, and DDR3 interface, the number of pins is further reduced for interfaces larger than x8 due to the need of one DQS pin for each x8 group. Check with the pin table for the accurate number per group. (2) Two x4 DQS/DQ groups are stitched together to make a x8/x9 group, so there are a total of 12 pins in this group. (3) Four x4 DQS/DQ groups are stitched together to make a x16/x18 group. (4) Eight x4 DQS/DQ groups are stitched together to make a x32/x36 group. (5) The DM pin can be supported if the differential DQS is not used and the group does not have additional signals. Figure 7-4 through Figure 7-9 show the maximum number of DQS/DQ groups per side of the Arria II GX device. These figures represent the die-top view of the Arria II GX device. Table 7-4 shows the number of I/O modules and DQS/DQ groups per side of the Arria II GX device. Table 7-4. Number of DQS/DQ Groups and I/O Modules in Arria II GX Devices per Side (Part 1 of 2) Device EP2AGX20 EP2AGX30 EP2AGX45 EP2AGX65 EP2AGX20 EP2AGX30 EP2AGX45 EP2AGX65 EP2AGX95 EP2AGX125 (c) March 2009 Package 358-Pin Ultra FineLine BGA 572-Pin FineLine BGA Altera Corporation DQS/DQ Groups I/O Module (1) x4 x8/x9 x16/x18 x32/x36 Top/Bottom 3 6 3 1 0 Right 2 4 2 2 0 Top/Bottom 4 8 4 2 0 Right 6 12 6 2 0 Side Arria II GX Device Handbook Volume 1 7-6 Chapter 7: External Memory Interfaces in Arria II GX Devices Arria II GX Memory Interfaces Pin Support Table 7-4. Number of DQS/DQ Groups and I/O Modules in Arria II GX Devices per Side (Part 2 of 2) Device Package Side DQS/DQ Groups I/O Module (1) x4 x8/x9 x16/x18 x32/x36 EP2AGX45 EP2AGX65 EP2AGX95 EP2AGX125 EP2AGX190 EP2AGX260 780-Pin FineLIne BGA Top/Bottom/ Right 7 14 7 3 1 EP2AGX95 EP2AGX125 1152-Pin FineLine BGA Top/Bottom 9 18 9 4 2 Right 8 16 8 4 2 EP2AGX190 EP2AGX260 1152-Pin FineLine BGA Top/Bottom/ Right 12 24 12 6 2 (c) March 2009 Altera Corporation Note to Table 7-4: (1) Each I/O module consists of 16 I/O pins. Twelve of the 16 pins are DQ/DSQ pins. Arria II GX Device Handbook Volume 1 Chapter 7: External Memory Interfaces in Arria II GX Devices Arria II GX Memory Interfaces Pin Support 7-7 Figure 7-3 shows the number of DQS/DQ groups per bank in EP2AGX20, EP2AGX30, EP2AGX45, and EP2AGX65 devices in the 358-pin Ultra FineLine BGA package. Figure 7-3. Number of DQS/DQ Groups per Bank in EP2AGX20, EP2AGX30, EP2AGX45, and EP2AGX65 Devices in the 358-Pin Ultra Fineline BGA Package (Note 1), (2), (3), (4) I/O Bank 8A I/O Bank 7A 22 User I/Os x4=2 x8/x9=1 x16/x18=0 x32/x36=0 38 User I/Os x4=4 x8/x9=2 x16/x18=1 x32/x36=0 I/O Bank 6A EP2AGX20, EP2AGX30, EP2AGX45, and EP2AGX65 Devices in the 358-Pin Ultra FineLine BGA 18 User I/Os x4=2 x8/x9=1 x16/x18=0 x32/x36=0 I/O Bank 5A 18 User I/Os x4=2 x8/x9=1 x16/x18=0 x32/x36=0 I/O Bank 3A I/O Bank 4A 22 User I/Os x4=2 x8/x9=1 x16/x18=0 x32/x36=0 38 User I/Os x4=4 x8/x9=2 x16/x18=1 x32/x36=0 Notes to Figure 7-3: (1) These numbers are preliminary until the devices are available. (2) All I/O pin counts include 12 dedicated clock inputs (CLK4 to CLK15) that you can use for data inputs. (3) Several configuration pins in Bank 6A are shared with DQS/DQ pins. You cannot use a x4 DQS/DQ group with any of its pin members used for configuration purposes. Ensure that the DQS/DQ groups you have chosen are not also used for configuration. (4) Arria II GX devices in the 358-pin Ultra FineLine BGA Package do not support x36 QDRII SRAM interface because x36 emulation mode (combining two x18 DQS/DQ groups to form a single x36 DQS/DQ group) is not supported. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 1 7-8 Chapter 7: External Memory Interfaces in Arria II GX Devices Arria II GX Memory Interfaces Pin Support Figure 7-4 shows the number of DQS/DQ groups per bank in Arria II GX EP2AGX20, EP2AGX30, EP2AGX45, and EP2AGX65 devices in the 572-pin FineLine BGA package. Figure 7-4. Number of DQS/DQ Groups per Bank in EP2AGX20, EP2AGX30, EP2AGX45, and EP2AGX65 Devices in the 572-Pin FineLine BGA Package (Note 1), (2), (3), (4) I/O Bank 8A I/O Bank 7A 38 User I/Os x4=4 x8/x9=2 x16/x18=1 x32/x36=0 38 User I/Os x4=4 x8/x9=2 x16/x18=1 x32/x36=0 I/O Bank 6A EP2AGX20, EP2AGX30, EP2AGX45, and EP2AGX65 Devices in the 572-Pin FineLine BGA 50 User I/Os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 I/O Bank 5A 50 User I/Os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 I/O Bank 3A I/O Bank 4A 38 User I/Os x4=4 x8/x9=2 x16/x18=1 x32/x36=0 38 User I/Os x4=4 x8/x9=2 x16/x18=1 x32/x36=0 Notes to Figure 7-4: (1) These numbers are preliminary until the devices are available. (2) All I/O pin counts include 12 dedicated clock inputs (CLK4 to CLK15) that you can use for data inputs. (3) Several configuration pins in Bank 6A are shared with DQS/DQ pins. You cannot use a x4 DQS/DQ group with any of its pin members used for configuration purposes. Ensure that the DQS/DQ groups you have chosen are not also used for configuration. (4) Arria II GX devices in the 572-pin FineLine BGA Package do not support x36 QDRII SRAM interface because x36 emulation mode (combining two x18 DQS/DQ groups to form a single x36 DQS/DQ group) is not supported. Arria II GX Device Handbook Volume 1 (c) March 2009 Altera Corporation Chapter 7: External Memory Interfaces in Arria II GX Devices Arria II GX Memory Interfaces Pin Support 7-9 Figure 7-5 shows the number of DQS/DQ groups per bank in Arria II GX EP2AGX95 and EP2AGX125 devices in the 572-pin FineLine BGA package. Figure 7-5. Number of DQS/DQ Groups per Bank in EP2AGX95 and EP2AGX125 Devices in the 572-Pin FineLine BGA Package (Note 1), (2), (3), (4) I/O Bank 8A I/O Bank 7A 42 User I/Os x4=4 x8/x9=2 x16/x18=1 x32/x36=0 38 User I/Os x4=4 x8/x9=2 x16/x18=1 x32/x36=0 I/O Bank 6A EP2AGX95 and EP2AGX125 Devices in the 572-Pin FineLine BGA 50 User I/Os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 I/O Bank 5A 50 User I/Os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 I/O Bank 3A I/O Bank 4A 38 User I/Os x4=4 x8/x9=2 x16/x18=1 x32/x36=0 42 User I/Os x4=4 x8/x9=2 x16/x18=1 x32/x36=0 Notes to Figure 7-5: (1) These numbers are preliminary until the devices are available. (2) All I/O pin counts include 12 dedicated clock inputs (CLK4 to CLK15) that you can use for data inputs. (3) Several configuration pins in Bank 6A are shared with DQS/DQ pins. You cannot use a x4 DQS/DQ group with any of its pin members used for configuration purposes. Ensure that the DQS/DQ groups you have chosen are not also used for configuration. (4) Arria II GX devices in the 572-pin FineLine BGA Package do not support x36 QDRII SRAM interface because x36 emulation mode (combining two x18 DQS/DQ groups to form a single x36 DQS/DQ group) is not supporte (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 1 7-10 Chapter 7: External Memory Interfaces in Arria II GX Devices Arria II GX Memory Interfaces Pin Support Figure 7-6 shows the number of DQS/DQ groups per bank in Arria II GX EP2AGX45 and EP2AGX65 devices in the 780-pin FineLine BGA package. Figure 7-6. Number of DQS/DQ Groups per Bank in EP2AGX45 and EP2AGX65 Devices in the 780-Pin FineLine BGA Package (Note 1), (2), (3) I/O Bank 8A I/O Bank 7A 54 User I/Os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 70 User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 I/O Bank 6A EP2AGX45 and EP2AGX65 Devices in the 780-Pin FineLine BGA 50 User I/Os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 I/O Bank 5A 66 User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 I/O Bank 3A I/O Bank 4A 54 User I/Os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 70 User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 Notes to Figure 7-6: (1) These numbers are preliminary until the devices are available. (2) All I/O pin counts include 12 dedicated clock inputs (CLK4 to CLK15) that you can use for data inputs. (3) Several configuration pins in Bank 6A are shared with DQS/DQ pins. You cannot use a x4 DQS/DQ group with any of its pin members used for configuration purposes. Ensure that the DQS/DQ groups you have chosen are not also used for configuration. Arria II GX Device Handbook Volume 1 (c) March 2009 Altera Corporation Chapter 7: External Memory Interfaces in Arria II GX Devices Arria II GX Memory Interfaces Pin Support 7-11 Figure 7-7 shows the number of DQS/DQ groups per bank in Arria II GX EP2AGX95, EP2AGX125, EP2AGX190, and EP2AGX260 devices in the 780-pin FineLine BGA package. Figure 7-7. Number of DQS/DQ Groups per Bank in EP2AGX95, EP2AGX125, EP2AGX190 and EP2AGX260 Devices in the 780-Pin FineLine BGA Package (Note 1), (2), (3) I/O Bank 8A I/O Bank 7A 58 User I/Os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 70 User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 I/O Bank 6A EP2AGX95, EP2AGX125, EP2AGX190, and EP2AGX260 Devices in the 780-Pin FineLine BGA 50 User I/Os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 I/O Bank 5A 66 User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 I/O Bank 3A I/O Bank 4A 54 User I/Os x4=6 x8/x9=3 x16/x18=1 x32/x36=0 74 User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 Notes to Figure 7-7: (1) These numbers are preliminary until the devices are available. (2) All I/O pin counts include 12 dedicated clock inputs (CLK4 to CLK15) that you can use for data inputs. (3) Several configuration pins in Bank 6A are shared with DQS/DQ pins. You cannot use a x4 DQS/DQ group with any of its pin members used for configuration purposes. Ensure that the DQS/DQ groups you have chosen are not also used for configuration. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 1 7-12 Chapter 7: External Memory Interfaces in Arria II GX Devices Arria II GX Memory Interfaces Pin Support Figure 7-8 shows the number of DQS/DQ groups per bank in Arria II GX EP2AGX95 and EP2AGX125 devices in the 1152-pin FineLine BGA package. Figure 7-8. Number of DQS/DQ Groups per Bank in EP2AGX95 and EP2AGX125 Devices in the 1152-Pin FineLine BGA Package (Note 1), (2), (3) I/O Bank 8A I/O Bank 7A I/O Bank 7B 74 User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 70 User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 16 User I/Os x4=2 x8/x9=1 x16/x18=0 x32/x36=0 I/O Bank 6A 66 User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 EP2AGX95 and EP2AGX125 Devices in the 1152-Pin FineLine BGA I/O Bank 5A 66 User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 I/O Bank 3A I/O Bank 4A I/O Bank 4B 70 User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 74 User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 16 User I/Os x4=2 x8/x9=1 x16/x18=0 x32/x36=0 Notes to Figure 7-8: (1) These numbers are preliminary until the devices are available. (2) All I/O pin counts include 12 dedicated clock inputs (CLK4 to CLK15) that you can use for data inputs. (3) Several configuration pins in Bank 6A are shared with DQS/DQ pins. You cannot use a x4 DQS/DQ group with any of its pin members used for configuration purposes. Ensure that the DQS/DQ groups you have chosen are not also used for configuration. Arria II GX Device Handbook Volume 1 (c) March 2009 Altera Corporation Chapter 7: External Memory Interfaces in Arria II GX Devices Arria II GX Memory Interfaces Pin Support 7-13 Figure 7-9 shows the number of DQS/DQ groups per bank in Arria II GX EP2AGX190 and EP2AGX260 devices in the 1152-pin FineLine BGA package. Figure 7-9. Number of DQS/DQ Groups per Bank in EP2AGX190 and EP2AGX260 Devices in the 1152-Pin FineLine BGA Package (Note 1), (2), (3) I/O Bank 8B I/O Bank 8A I/O Bank 7A I/O Bank 7B 32 User I/Os x4=4 x8/x9=2 x16/x18=1 x32/x36=0 74 User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 70 User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 32 User I/Os x4=4 x8/x9=2 x16/x18=1 x32/x36=0 I/O Bank 6B 32 User I/Os x4=4 x8/x9=2 x16/x18=1 x32/x36=0 I/O Bank 6A 66 User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 EP2AGX190 and EP2AGX260 Devices in the 1152-Pin FineLine BGA I/O Bank 5A 66 User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 I/O Bank 5B 32 User I/Os x4=4 x8/x9=2 x16/x18=1 x32/x36=0 I/O Bank 3B 32 User I/Os x4=4 x8/x9=2 x16/x18=1 x32/x36=0 I/O Bank 3A I/O Bank 4A I/O Bank 4B 70 User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 74 User I/Os x4=8 x8/x9=4 x16/x18=2 x32/x36=1 32 User I/Os x4=4 x8/x9=2 x16/x18=1 x32/x36=0 Notes to Figure 7-9: (1) These numbers are preliminary until the devices are available. (2) All I/O pin counts include 12 dedicated clock inputs (CLK4 to CLK15) that you can use for data inputs. (3) Several configuration pins in Bank 6A are shared with DQS/DQ pins. You cannot use a x4 DQS/DQ group with any of its pin members used for configuration purposes. Ensure that the DQS/DQ groups you have chosen are not also used for configuration. The DQS and DQSn pins are listed in the Arria II GX pin tables as DQSXY and DQSnXY, respectively, where X denotes the DQS/DQ grouping number and Y denotes whether the group is located on the top (T), bottom (B), or right (R) side of the device. The DQS/DQ pin numbering is based on x4 mode. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 1 7-14 Chapter 7: External Memory Interfaces in Arria II GX Devices Arria II GX Memory Interfaces Pin Support The corresponding DQ pins are marked as DQXY, where X indicates to which DQS group the pins belong to and Y indicates whether the group is located on the top (T), bottom (B), or right (R) side of the device. For example, DQS3B indicates a DQS pin that is located on the bottom side of the device. The DQ pins belonging to that group are shown as DQ3B in the pin table. See Figure 7-10 for illustrations. 1 The parity, DM, BWSn, and ECC pins are shown as DQ pins in the pin table. The numbering scheme starts from the top-left side of the device going clockwise in a die-top view. Figure 7-10 shows how the DQS/DQ groups are numbered in a die-top view of the largest Arria II GX device. Figure 7-10. DQS Pins in Arria II GX I/O Banks for EP2AGX260 with the F1152 Package DQS24T DQS1T DLL1 PLL2 PLL1 8B 8A 7A 7B DQS1R 6B 6A PLL5 Arria II GX Device PLL6 5A 5B DQS24R 3B 3A 4A 4B PLL3 PLL4 DLL2 DQS24B Arria II GX Device Handbook Volume 1 DQS1B (c) March 2009 Altera Corporation Chapter 7: External Memory Interfaces in Arria II GX Devices Arria II GX External Memory Interface Features 7-15 Arria II GX External Memory Interface Features Arria II GX devices are rich with features that allow robust high-performance external memory interfacing. The ALTMEMPHY megafunction allows you to use these external memory interface features and helps set up the physical interface (PHY) best suited for your system. This section describes each Arria II GX device feature that is used in external memory interfaces from the DQS phase-shift circuitry and DQS logic block. 1 When you use the Altera memory controller MegaCore functions, the ALTMEMPHY megafunction is instantiated for you. Table 7-5 shows the Quartus II megafunction/MegaCore support for the Arria II GX external memory interface. Table 7-5. Megafunction/MegaCore Support for the Arria II GX External Memory Interface Megafunction/IP Support Memory Standards High-Performance Controller Full Data Rate High-Performance Controller Half Data Rate ALTMEMPHY Full Data Rate ALTMEMPHY Half Data Rate ALTDLL and ALTDQ_DQS Megafunctions DDR SDRAM v v v v v DDR2 SDRAM v v v v v DDR3 SDRAM -- v -- v v QDRII SRAM -- -- -- -- v DQS Phase-Shift Circuitry Arria II GX phase-shift circuitry provides phase shift to the DQS/CQ and CQn pins on read transactions when the DQS/CQ and CQn pins are acting as input clocks or strobes to the FPGA. DQS phase-shift circuitry consists of DLLs that are shared between multiple DQS pins and the phase-offset control module to further fine-tune the DQS phase shift for different sides of the device. Figure 7-11 shows how the DQS phase-shift circuitry is connected to the DQS/CQ and CQn pins in the device where memory interfaces are supported on the top, bottom, and right sides of the Arria II GX device. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 1 7-16 Chapter 7: External Memory Interfaces in Arria II GX Devices Arria II GX External Memory Interface Features Figure 7-11. DQS/CQ and CQn Pins and DQS Phase-Shift Circuitry (Note 1) DQS/CQ Pin CQn Pin DLL Reference Clock (2) DQS/CQ Pin CQn Pin DQS Logic Blocks DQS Phase-Shift Circuitry t t t t to IOE to IOE to IOE to IOE 6 DQS Logic Blocks 6 to IOE t to IOE t to IOE t to IOE t CQn Pin DQS/CQ Pin CQn Pin DQS/CQ Pin 6 6 to IOE to IOE to IOE to IOE t t t t DQS Phase-Shift Circuitry DLL Reference Clock (2) CQn Pin DQS/CQ Pin CQn Pin DQS/CQ Pin Notes to Figure 7-11: (1) Refer to Table 7-6 on page 7-18 for possible reference input clock pins for each DLL. (2) You can configure each DQS/CQ and CQn pin with a phase shift based on one of two possible DLL output settings. DQS phase-shift circuitry is connected to DQS logic blocks that control each DQS/CQ or CQn pin. The DQS logic blocks allow the DQS delay settings to be updated concurrently at every DQS/CQ or CQn pin. Arria II GX Device Handbook Volume 1 (c) March 2009 Altera Corporation Chapter 7: External Memory Interfaces in Arria II GX Devices Arria II GX External Memory Interface Features 7-17 DLL DQS phase-shift circuitry uses a DLL to dynamically control the clock delay needed by the DQS/CQ and CQn pins. The DLL, in turn, uses a frequency reference to dynamically generate control signals for the delay chains in each of the DQS/CQ and CQn pins, allowing it to compensate for PVT variations. The DQS delay settings are Gray-coded to reduce jitter when the DLL updates the settings. Phase-shift circuitry needs a maximum of 1280 clock cycles to lock and calculate the correct input clock period. Do not send data during these clock cycles because there is no guarantee that it will be captured properly. As the settings from the DLL may not be stable until this lock period has elapsed, be aware that anything using these settings may be unstable during this period. 1 You can still use the DQS phase-shift circuitry for any memory interfaces that are operating at less than 100 MHz. However, the DQS signal may not shift over 2.5 ns. At less than 100 MHz, while the DQS phase shift may not be exactly centered to the data valid window, sufficient margin needs to still exist for reliable operation. There are two DLLs in an Arria II GX device, located in the top-left and bottom-right corners of the device. These two DLLs can support a maximum of two unique frequencies, with each DLL running at one frequency. Each DLL can have two outputs with different phase offsets, which allows one Arria II GX device to have four different DLL phase-shift settings. Each DLL can access the top, bottom, and right side of the device. This means that each I/O bank is accessible by two DLLs, giving more flexibility to create multiple frequencies and multiple-type interfaces. The DLL outputs the same DQS delay settings for the different sides of the device. 1 Interfaces that span two sides of the device are not recommended for high-performance memory interface applications. However, Arria II GX devices support interfaces with DQ/DQS groups wrapping over column and row I/Os from adjacent sides of the devices. Interfaces with DQ/DQS groups from both top and bottom I/O banks are not supported. Each bank can use settings from either one or both DLLs. For example, DQS1R can get its phase-shift settings from DLL1, while DQS2R can get its phase-shift settings from DLL2. The reference clock for each DLL might come from PLL output clocks or dedicated clock input pins, as specified in Table 7-6. (c) March 2009 1 When you have a dedicated PLL that only generates the DLL input reference clock, set the PLL mode to No Compensation or the Quartus II software changes it automatically. Because the PLL does not use any other outputs, it does not need to compensate for any clock paths. 1 Arria II GX devices support PLL cascading. When cascading PLLs, it is best to use PLLs adjacent to each other (for example, PLL5 and PLL6) so that the dedicated path between the two PLLs is used instead of using a GCLK or RCLK clock network that might be subjected to core noise. The TimeQuest timing analyzer takes PLL cascading into consideration for timing analysis. Altera Corporation Arria II GX Device Handbook Volume 1 7-18 Chapter 7: External Memory Interfaces in Arria II GX Devices Arria II GX External Memory Interface Features Table 7-6. DLL Reference Clock Input (Note 1) CLKIN (Top/Bottom) CLKIN (Right) PLL DLL1 CLK12 CLK13 CLK14 CLK15 Not Available PLL1 DLL2 CLK4 CLK5 CLK6 CLK7 CLK8 CLK9 CLK10 CLK11 PLL3 DLL Note to Table 7-6: (1) CLK4 to CLK7 are located on the bottom side, CLK8 to CLK11 are located on the right side, and CLK12 to CLK15 are located on the top side of the device. 1 When using the ALTMEMPHY megafunction, use the dedicated PLL input pin for the PLL reference clock. Figure 7-12 shows a simple block diagram of the DQS Phase-Shift Circuitry. The input reference clock goes into the DLL to a chain of up to 16 delay elements. The phase comparator compares the signal coming out of the end of the delay chain block to the input reference clock. The phase comparator then issues the upndn signal to the Graycoded counter. This signal increments or decrements a 6-bit delay setting (DQS delay settings) that increases or decreases the delay through the delay element chain to bring the input reference clock and the signals coming out of the delay element chain in phase. Arria II GX Device Handbook Volume 1 (c) March 2009 Altera Corporation Chapter 7: External Memory Interfaces in Arria II GX Devices Arria II GX External Memory Interface Features 7-19 Figure 7-12. Simplified Diagram of the DQS Phase-Shift Circuitry (Note 1) addnsub_a Phase offset settings from the logic array 6 Phase Offset Control DLL Input Reference Clock (2) addnsub_b Phase offset settings from the logic array upndn Phase Comparator clock enable 6 DLL1 phase offset settings to top and right side, DLL2 phase offset settings to bottom side of the device (3) Up/Down Counter 6 Phase Offset Control 6 DLL1 phase offset settings to bottom side, DLL2 phase offset settings to right and top side of the device (3) 6 Delay Chains 6 DQS Delay Settings (4) 6 Notes to Figure 7-12: (1) All features of the DQS phase-shift circuitry are accessible from the ALTMEMPHY megafunction in the Quartus II software. (2) The input reference clock for the DQS phase-shift circuitry can come from a PLL output clock or an input clock pin. Refer to Table 7-6 and Table 7-7 for the exact PLL and input clock pin. (3) Phase offset settings can only go to the DQS logic blocks. (4) DQS delay settings can go to the logic array and DQS logic block. You can reset the DLL from either the logic array or a user I/O pin. Each time the DLL is reset, you must wait for 1280 clock cycles for the DLL to lock before you can capture the data properly. Depending on the DLL frequency mode, the DLL can shift the incoming DQS signals by 0, 22.5, 30, 36, 45, 60, 67.5, 72, 90, 108, 120, 135, 144, or 180. The shifted DQS signal is then used as the clock for the DQ IOE input registers. All DQS/CQ and CQn pins, referenced to the same DLL, can have their input signal phase shifted by a different degree amount but all must be referenced at one particular frequency. For example, you can have a 90 phase shift on DQS1T and a 60 phase shift on DQS2T, referenced from a 200-MHz clock. Not all phase-shift combinations are supported. The phase shifts on the DQS pins referenced by the same DLL must all be a multiple of 22.5 (up to 90), 30 (up to 120), 36 (up to 144), or 45 (up to 180). There are six different frequency modes for the Arria II GX DLL, as shown in Table 7-7. Each frequency mode provides different phase-shift selections. In frequency mode 0, 1, 2, and 3, the 6-bit DQS delay settings vary with PVT to implement the phase-shift delay. In frequency modes 4 and 5, only 5 bits of the DQS delay settings vary with PVT to implement the phase-shift delay; the most significant bit of the DQS delay setting is set to 0. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 1 7-20 Chapter 7: External Memory Interfaces in Arria II GX Devices Arria II GX External Memory Interface Features Table 7-7. Arria II GX DLL Frequency Modes f Frequency Mode Available Phase Shift Number of Delay Chains 0 22.5, 45, 67.5, 90 16 1 30, 60, 90, 120 12 2 36, 72, 108, 144 10 3 45, 90, 135, 180 8 4 30, 60, 90, 120 12 5 36, 72, 108, 144 10 For the frequency range of each mode, refer to the Device Data Sheet chapter in volume 3 of the Arria II GX Device Handbook. For 0 shift, the DQS/CQ signal bypasses both the DLL and DQS logic blocks. The Quartus II software automatically sets the DQ input delay chains so that the skew between the DQ and DQS/CQ pin at the DQ IOE registers is negligible when the 0 shift is implemented. You can feed the DQS delay settings to the DQS logic block and the logic array. The shifted DQS/CQ signal goes to the DQS bus to clock the IOE input registers of the DQ pins. The signal can also go into the logic array for resynchronization if you are not using the IOE resynchronization registers. The shifted CQn signal can go to the negative-edge input register in the DQ IOE or the logic array and is only used for QDRII SRAM interfaces. Phase Offset Control Each DLL has two phase offset modules and can provide two separate DQS delay settings with independent offset; one offset goes clockwise half-way around the chip and the other goes counter-clockwise half-way around the chip. Even though you have independent phase offset control, the frequency of the interface using the same DLL has to be the same. Use the phase offset control module for making small shifts to the input signal and use the DQS phase-shift circuitry for larger signal shifts. For example, if the DLL only offers a multiple of 30 phase shift, but your interface needs a 67.5 phase shift on the DQS signal, you can use two delay chains in the DQS logic blocks to give you 60 phase shift and use the phase offset control feature to implement the extra 7.5 phase shift. You can either use a static phase offset or a dynamic phase offset to implement the additional phase shift. The available additional phase shift is implemented in 2s: complement in Gray-code between settings -64 to +63 for frequency mode 0, 1, 2, and 3, and between settings -32 to +31 for frequency modes 4, 5, and 6. An additional bit indicates whether the setting has a positive or negative value. The settings are linear, each phase offset setting adds a delay amount. f For more information about the specified phase-shift settings, refer to the Device Data Sheet chapter in volume 3 of the Arria II GX Device Handbook. Arria II GX Device Handbook Volume 1 (c) March 2009 Altera Corporation Chapter 7: External Memory Interfaces in Arria II GX Devices Arria II GX External Memory Interface Features 7-21 The DQS phase shift is the sum of the DLL delay settings and the user-selected phase offset settings whose top setting is 64 for frequency modes 0, 1, 2, and 3; and 32 for frequency modes 4, 5, and 6. Therefore, the actual physical offset setting range is 64 or 32 subtracted by the DQS delay settings from the DLL. 1 When you use this feature, monitor the DQS delay settings to know how many offsets you can add and subtract in the system. Note that the DQS delay settings output by the DLL are also Gray-coded For example, if the DLL determines that DQS delay settings of 28 are needed to achieve a 30 phase shift in DLL frequency mode 1, you can subtract up to 28 phase offset settings and you can add up to 35 phase offset settings to achieve the optimal delay that you need. However, if the same DQS delay settings of 28 is needed to achieve 30 phase shift in DLL frequency mode 4, you can still subtract up to 28 phase offset settings, but you can only add up to 3 phase offset settings before the DQS delay settings reach their maximum settings because DLL frequency mode 4 only uses 5-bit DLL delay settings. f For more information about the value for each step, refer to the Device Data Sheet chapter in volume 3 of the Arria II GX Device Handbook. DQS Logic Block Each DQS/CQ and CQn pin is connected to a separate DQS logic block, which consists of DQS delay chains, update enable circuitry, and DQS postamble circuitry (see Figure 7-13). (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 1 7-22 Chapter 7: External Memory Interfaces in Arria II GX Devices Arria II GX External Memory Interface Features Figure 7-13. Arria II GX DQS Logic Block reset DQS Enable gated_dqs control DFF B DQS Delay Chain VCC PRN A Q DQS' D CLR Bypass DQS bus DQS/CQ or CQn Pin dqsenable (2) 6 6 6 6 6 6 Phase offset settings from DQS phase-shift circuitry DQS delay settings from the DQS phase-shift circuitry 6 D Q D Q Update Enable Circuitry 6 Postamble Enable Postamble Control Clock Input Reference Clock (1) D Q D Q Notes to Figure 7-13: (1) The input reference clock for the DQS phase-shift circuitry can come from a PLL output clock or an input clock pin. Refer to Table 7-6 and Table 7-7 for the exact PLL and input clock pin. (2) The dqsenable signal can also come from the Arria II GX FPGA fabric. DQS Delay Chain DQS delay chains consist of a set of variable delay elements to allow the input DQS/CQ and CQn signals to be shifted by the amount specified by the DQS phase-shift circuitry or the logic array. There are four delay elements in the DQS delay chain; the first delay chain closest to the DQS/CQ or CQn pin can either be shifted by the DQS delay settings or by the sum of the DQS/CQ delay setting and the phase-offset setting. The number of delay chains required is transparent because the ALTMEMPHY megafunction automatically sets it when you choose the operating frequency. The DQS delay settings can come from the DQS phase-shift circuitry on either end of the I/O banks or from the logic array. The delay elements in the DQS logic block have the same characteristics as the delay elements in the DLL. When the DLL is not used to control the DQS delay chains, you can input your own Gray-coded 6-bit or 5-bit settings using the dqs_delayctrlin[5..0] signals available in the ALTMEMPHY megafunction. These settings control 1, 2, 3, or all 4 delay elements in the DQS delay chains. The ALTMEMPHY megafunction can also dynamically choose the number of DQS delay chains needed for the system. The amount of delay is equal to the sum of the delay element's intrinsic delay and the product of the number of delay steps and the value of the delay steps. You can also bypass the DQS delay chain to achieve 0 phase shift. Arria II GX Device Handbook Volume 1 (c) March 2009 Altera Corporation Chapter 7: External Memory Interfaces in Arria II GX Devices Arria II GX External Memory Interface Features 7-23 Update Enable Circuitry Both the DQS delay settings and the phase-offset settings pass through a register before going into the DQS delay chains. The registers are controlled by the update enable circuitry to allow enough time for any changes in the DQS delay setting bits to arrive at all the delay elements. This allows them to be adjusted at the same time. The update enable circuitry enables the registers to allow enough time for the DQS delay settings to travel from the DQS phase-shift circuitry or core logic to all the DQS logic blocks before the next change. It uses the input reference clock or a user clock from the core to generate the update enable output. The ALTMEMPHY megafunction uses this circuit by default. Figure 7-14 shows an example waveform of the update enable circuitry output. Figure 7-14. DQS Update Enable Waveform DLL Counter Update (Every 8 cycles) DLL Counter Update (Every 8 cycles) System Clock DQS Delay Settings (Updated every 8 cycles) 6 bit Update Enable Circuitry Output DQS Postamble Circuitry For external memory interfaces that use a bidirectional read strobe such as in DDR3, DDR2, and DDR SDRAM, the DQS signal is low before going to or coming from a high-impedance state. The state in which DQS is low, just after a high-impedance state, is called the preamble; the state in which DQS is low, just before it returns to a high-impedance state, is called the postamble. There are preamble and postamble specifications for both read and write operations in DDR3, DDR2, and DDR SDRAM. The DQS postamble circuitry, featured in Figure 7-15, ensures that data is not lost if there is noise on the DQS line at the end of a read postamble time. Arria II GX devices have dedicated postamble registers that can be controlled to ground the shifted DQS signal used to clock the DQ input registers at the end of a read operation. This ensures that any glitches on the DQS input signals at the end of the read postamble time do not affect the DQ IOE registers. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 1 7-24 Chapter 7: External Memory Interfaces in Arria II GX Devices Arria II GX External Memory Interface Features Figure 7-15. Arria II GX DQS Postamble Circuitry (Note 1) reset DQS Enable gated_dqs control B DFF PRN D Q A DQS' VCC CLR DQS Bus Postamble Enable Postamble Control Clock D Q D Q dqsenable (2) Notes to Figure 7-15: (1) The postamble clock can come from any of the delayed resynchronization clock taps although it is not necessarily of the same phase as the resynchronization clock. (2) The dqsenable signal can also come from the Arria II GX FPGA fabric. There is an AND gate after the postamble register outputs that is used to avoid postamble glitches from a previous read burst on a non-consecutive read burst. This scheme allows a half-a-clock cycle latency for dqsenable assertion and zero latency for dqsenable de-assertion, as shown in Figure 7-16. Figure 7-16. Avoiding Glitch on a Non-Consecutive Read Burst Waveform Postamble glitch Postamble Preamble DQS Postamble Enable dqsenable Delayed by 1/2T logic Arria II GX Device Handbook Volume 1 (c) March 2009 Altera Corporation Chapter 7: External Memory Interfaces in Arria II GX Devices Arria II GX External Memory Interface Features 7-25 I/O Element Registers IOE registers are expanded to allow source-synchronous systems to have faster register-to-register transfers and resynchronization. Both top, bottom, and right IOEs have the same capability. Right IOEs have extra features to support LVDS data transfer. Figure 7-17 shows the registers available in the Arria II GX input path. The input path consists of DDR input registers and resynchronization registers. You can bypass each block of the input path. Figure 7-17. Arria II GX IOE Input Registers (Note 1) Synchronization Registers Double Data Rate Input Registers To Core (rdata0) DQ D D Q Q DFF DFF Input Reg A I To Core (rdata1) D DQS (2) Q DFF Input Reg B Differential Input Buffer neg_reg_out D D Q DFF DFF I Input Reg C Q I DQSn 1 CQn (3) 0 Resynchronization Clock (resync_clk_2x) (3) Notes to Figure 7-17: (1) You can bypass each register block in this path. (2) The input clock can be from the DQS logic block (whether the postamble circuitry is bypassed or not) or from a global clock line. (3) This input clock comes from the CQn logic block. There are three registers in the DDR input registers block. Two registers capture data on the positive and negative edges of the clock, while the third register aligns the captured data. You can choose to use the same clock for the positive edge and negative edge registers, or two complementary clocks (DQS/CQ for positive-edge register and DQSn/CQn for negative-edge register). The third register that aligns the captured data uses the same clock as the positive edge registers. The resynchronization registers resynchronize the data to the resynchronization clock domain. These registers are clocked by the resynchronization clock that is generated by the PLL. The outputs of the resynchronization registers go straight to the core. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 1 7-26 Chapter 7: External Memory Interfaces in Arria II GX Devices Revision History Figure 7-18 shows the registers available in the Arria II GX output and output-enable paths. The device can bypass each block of the output and output-enable path. Figure 7-18. Arria II GX IOE Output and Output-Enable Path Registers (Note 1) Double Data Rate Output-Enable Registers DFF From Core D Q OE Reg A OE OR2 1 0 DFF D Q OE Reg B OE Double Data Rate Output Registers DFF From Core (wdata0) D Q TRI Output Reg Ao DQ or DQS 1 0 DFF From Core (wdata1) D Q Output Reg Bo Write Clock (2) Notes to Figure 7-18: (1) You can bypass each register block of the output and output-enable paths. (2) The write clock comes from the PLL. The DQ write clock and DQS write clock have a 90 offset between them. The output path is designed to route combinatorial or registered SDR outputs and DDR outputs from the FPGA core. The output-enable path has a structure similar to the output path. You can have a combinatorial or registered output in SDR applications. Revision History Table 7-8 shows the revision history for this chapter. Table 7-8. Document Revision History Date and Document Version Changes Made Summary of Changes March 2009, v1.1 Updated Table 7-1 and Table 7-2. -- February 2009, v1.0 Initial release. -- Arria II GX Device Handbook Volume 1 (c) March 2009 Altera Corporation 8. High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices AIIGX51008-1.0 Introduction This chapter describes the high-speed differential I/O features and resources, and the functionality of the serializer/deserializer (SERDES) and dynamic phase alignment (DPA) circuitry in Arria(R) II GX devices. The new modular I/O architecture in Arria II GX devices allows for high-speed LVDS interface on the top, bottom, and right sides of the device. The left side of the device is occupied by high-speed transceiver blocks. Dedicated SERDES and DPA circuitry are implemented on the right side of the device to further enhance LVDS interface performance in the device. This chapter contains the following sections: "LVDS Channels" on page 8-2 "LVDS SERDES and DPA Block Diagram" on page 8-5 "Differential Transmitter" on page 8-6 "Differential Receiver" on page 8-8 "Programmable Pre-Emphasis and Programmable VOD." on page 8-15 "Differential I/O Termination" on page 8-17 "PLLs" on page 8-17 "LVDS and DPA Clock Networks" on page 8-17 "Source-Synchronous Timing Budget" on page 8-18 "Differential Pin Placement Guidelines" on page 8-21 "Setting Up an LVDS Transmitter or Receiver Channel" on page 8-31 The Arria II GX device family has the following dedicated circuitry for high-speed differential I/O support: (c) February 2009 Differential I/O buffer Transmitter serializer Receiver deserializer Data realignment DPA Synchronizer (FIFO buffer) Phase-locked loops (PLLs) Altera Corporation Arria II GX Device Handbook Volume 1 8-2 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices LVDS Channels The Arria II GX family supports the following differential I/O standards: 1 LVDS mini-LVDS Reduced swing differential signaling (RSDS) Low-voltage positive emitter-coupled logic (LVPECL) Bus LVDS (BLVDS) Dedicated mini-LVDS and RSDS inputs are not supported. The LVPECL I/O standard is only for PLL clock inputs in differential mode. Table 8-1 shows the data rate range supported by LVDS, mini-LVDS, and RSDS. Table 8-1. Supported Data Rate Range I/O Standards Data Rate Range (Mbps) (Note 1) LVDS mini-LVDS RSDS 150-1000 (2) 150-400 150-360 Note to Table 8-1: (1) The maximum data rate supported subject to silicon characterization. (2) Dedicated SERDES and DPA circuitry on the right side of the device are required to achieve LVDS data rate at 1000 Mbps. f For specifications and features of the differential I/O standards supported in Arria II GX devices, refer to the I/O Features in Arria II GX Devices chapter in volume 1 of the Arria II GX Device Handbook. f For specifications of the differential I/O standards supported in Arria II GX devices, refer to the Device Data Sheet chapter in volume 3 of the Arria II GX Device Handbook. LVDS Channels In Arria II GX devices, there are dedicated LVDS input buffers and LVDS I/O buffers at the top, bottom, and right side of the device. The LVDS input buffers have 100- differential on-chip termination (OCT RD) support. You can configure the LVDS I/O buffers as either LVDS input (without OCT R D) or dedicated LVDS output buffers. Alternatively, you can configure the LVDS pins on the top, bottom, and right sides of the device, as pseudo-LVDS output buffers, which use two single-ended output buffers with an external resistor network to support LVDS, mini-LVDS and RSDS standards. Figure 8-1 shows a high-level chip overview of Arria II GX devices. The left side of the device is occupied by high-speed transceiver blocks. f For more details about I/O bank information, refer to the I/O Features in Arria II GX Devices chapter in volume 1 of the Arria II GX Device Handbook. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices LVDS Channels 8-3 Figure 8-1. High-Speed Differential I/Os with DPA Locations in an Arria II GX Device (Note 1), (2), (3) High-Speed Differential I/O, General Purpose I/O, and Memory Interface High-Speed Differential I/O, General Purpose I/O, and Memory Interface PLL PLL High-Speed Differential I/O with DPA, General Purpose I/O, and Memory Interface Transceiver Blocks FPGA Fabric PLL (Logic Elements, DSP, Embedded Memory, and Clock Networks) PLL High-Speed Differential I/O with DPA, General Purpose I/O, and Memory Interface PLL PLL High-Speed Differential I/O, General Purpose I/O, and Memory Interface High-Speed Differential I/O, General Purpose I/O, and Memory Interface Notes to Figure 8-1: (1) This is a top view of the silicon die, which corresponds to a reverse view for flip chip packages. It is a graphical representation only. (2) Applicable to EP2AGX95, EP2AGX125, EP2AGX190, and EP2AGX260 devices. (3) There are no center PLLs on the right I/O banks for EP2AGX20, EP2AGX30, EP2AGX45, and EP2AGX65 devices. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 8-4 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices LVDS Channels Table 8-2 and Table 8-3 show the maximum number of row and column LVDS I/Os supported in Arria II GX devices. You can design the LVDS I/Os as dedicated LVDS input, output buffers or pseudo-LVDS output buffers, as long as the combination does not exceed the maximum count. For example, there are a total of 56 LVDS pairs of I/Os in 780-pin EP2AGX45 device row (refer to Table 8-2). You can design up to a maximum of: 28 dedicated LVDS input buffers with OCT R D and 28 dedicated LVDS output buffers, or 56 LVDS input buffers of which 28 are dedicated LVDS input buffers with OCT RD and 28 need external 100- termination, or 28 dedicated LVDS output buffers and 28 emulated LVDS output buffers, or 56 emulated LVDS output buffers. Table 8-2. LVDS Channels Supported in Arria II GX Device Row I/O Banks (Note 1), (2), (3), (4) Device 358-Pin FlipChip UBGA 572-Pin FlipChip FBGA 780-Pin FlipChip FBGA 1152-Pin FlipChip FBGA EP2AGX20 8Rx or pTx + 8Tx or pTx 24Rx or pTx + 24Tx or pTx -- -- EP2AGX30 8Rx or pTx + 8Tx or pTx 24Rx or pTx + 24Tx or pTx -- -- EP2AGX45 8Rx or pTx + 8Tx or pTx 24Rx or pTx + 24Tx or pTx 28Rx or pTx + 28Tx or pTx -- EP2AGX65 8Rx or pTx + 8Tx or pTx 24Rx or pTx + 24Tx or pTx 28Rx or pTx + 28Tx or pTx -- EP2AGX95 -- 24Rx or pTx + 24Tx or pTx 28Rx or pTx + 28Tx or pTx 32Rx or pTx + 32Tx or pTx EP2AGX125 -- 24Rx or pTx + 24Tx or pTx 28Rx or pTx + 28Tx or pTx 32Rx or pTx + 32Tx or pTx EP2AGX190 -- -- 28Rx or pTx + 28Tx or pTx 48Rx or pTx + 48Tx or pTx EP2AGX260 -- -- 28Rx or pTx + 28Tx or pTx 48Rx or pTx + 48Tx or pTx Notes to Table 8-2: (1) (2) (3) (4) Rx = dedicated LVDS input buffers with OCT RD support. Tx = dedicated LVDS output buffers or LVDS input buffers without OCT RD support. pTx = pseudo-LVDS output buffers, either LVDS_E_3R or LVDS_E_1R. The LVDS channel count does not include dedicated clock input pins and PLL clock output pins. Table 8-3. LVDS Channels Supported in Arria II GX Device Column I/O Banks (Note 1), (2), (3), (4) Device 358-Pin FlipChip UBGA 572-Pin FlipChip FBGA 780-Pin FlipChip FBGA 1152-Pin FlipChip FBGA EP2AGX20 25Rx or pTx + 24Tx or pTx 33Rx or pTx + 32Tx or pTx -- -- EP2AGX30 25Rx or pTx + 24Tx or pTx 33Rx or pTx + 32Tx or pTx -- -- EP2AGX45 25Rx or pTx + 24Tx or pTx 33Rx or pTx + 32Tx or pTx 57Rx or pTx + 56Tx or pTx -- EP2AGX65 25Rx or pTx + 24Tx or pTx 33Rx or pTx + 32Tx or pTx 57Rx or pTx + 56Tx or pTx -- EP2AGX95 -- 33Rx or pTx + 32Tx or pTx 57Rx or pTx + 56Tx or pTx 73Rx or pTx + 72Tx or pTx EP2AGX125 -- 33Rx or pTx + 32Tx or pTx 57Rx or pTx + 56Tx or pTx 73Rx or pTx + 72Tx or pTx EP2AGX190 -- -- 57Rx or pTx + 56Tx or pTx 97Rx or pTx + 96Tx or pTx EP2AGX260 -- -- 57Rx or pTx + 56Tx or pTx 97Rx or pTx + 96Tx or pTx Notes to Table 8-3: (1) (2) (3) (4) Rx = dedicated LVDS input buffers with OCT RD support. Tx = dedicated LVDS output buffers or LVDS input buffers without OCT RD support. pTx = pseudo-LVDS output buffers, either LVDS_E_3R or LVDS_E_1R. The LVDS channel count does not include dedicated clock input pins and PLL clock output pins. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices LVDS SERDES and DPA Block Diagram 8-5 LVDS SERDES and DPA Block Diagram The Arria II GX device family has dedicated SERDES and DPA circuitry for LVDS transmitters and receivers on the right side of the device. Figure 8-2 shows the LVDS SERDES and DPA block diagram. This diagram shows the interface signals for the transmitter and receiver data paths. For more information, refer to "Differential Transmitter" on page 8-6 and "Differential Receiver" on page 8-8. Figure 8-2. LVDS SERDES and DPA Block Diagram (Note 1), (2), (3) Serializer tx_in 2 IOE Supports SDR, DDR, or Non-Registered Datapath IOE tx_out + - 10 DIN DOUT LVDS Transmitter tx_coreclock 3 (LVDS_LOAD_EN, diffioclk, tx_coreclock) IOE Supports SDR, DDR, or Non-Registered Datapath 10 rx_out 2 LVDS Receiver + - IOE rx_in Synchronizer FPGA Fabric Deserializer Bit Slip DOUT DIN DOUT DIN DPA Circuitry Retimed Data DOUT DIN DIN diffioclk 2 (LOAD_EN, diffioclk) Clock Multiplexer DPA_diffioclk LVDS_diffioclk DPA Clock 3 (DPA_LOAD_EN, DPA_diffioclk, rx_divfwdclk) rx_divfwdclk rx_outclock 3 (LVDS_LOAD_EN, LVDS_diffioclk, rx_outclock LVDS Clock Domain DPA Clock Domain 8 Serial LVDS Clock Phases Center/Corner PLL rx_inclock/tx_inclock Notes to Figure 8-2: (1) This diagram shows a shared PLL between the transmitter and receiver. If the transmitter and receiver are not sharing the same PLL, two PLLs on the right side of the device are required. (2) In SDR and DDR mode, the data width is 1 and 2, respectively. (3) The tx_in and rx_out ports have a maximum data width of 10. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 8-6 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices Differential Transmitter Differential Transmitter The serializer takes parallel data up to 10-bits wide from the FPGA fabric and converts the parallel data to serial data before sending the serial data to the differential output buffer. The differential output buffer supports programmable pre-emphasis and programmable VOD controls, and can drive out mini-LVDS and RSDS signaling levels. Figure 8-3 is a block diagram of the LVDS transmitter. Figure 8-3. Arria II GX LVDS Transmitter Block Diagram (Note 1), (2) Serializer tx_in 10 DIN 2 IOE IOE supports SDR, DDR, or Non-Registered Datapath + - DOUT tx_out FPGA Fabric LVDS Transmitter tx_coreclock 3 (LVDS_LOAD_EN, diffioclk, tx_coreclock) Center/Corner PLL tx_inclock LVDS Clock Domain Notes to Figure 8-3: (1) In SDR and DDR mode, the data width is 1 and 2, respectively. (2) The tx_in port has a maximum data width of 10. Serializer The serializer takes parallel data from the FPGA fabric, clocks it into the parallel load registers, and serializes it using the shift registers before sending the data to the differential output buffer. The MSB of the parallel data is transmitted first. The parallel load and shift registers are clocked by the high-speed clock running at the serial data rate (diffioclk) and controlled by the load enable signal (LVDS_LOAD_EN) generated from the PLL. You can statically set the serialization factor to x4, x6, x7, x8, or x10 using the ALTLVDS megafunction. The load enable signal is derived from the serialization factor setting. The serializer can be bypassed to support DDR (x2) and SDR (x1) operations to achieve a serialization factor of 2 and 1, respectively. The I/O element (IOE) contains two data output registers that can each operate in either DDR or SDR mode. Figure 8-4 shows the serializer bypass path. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices Differential Transmitter 8-7 Figure 8-4. Arria II GX Serializer Bypass (Note 1), (2), (3) Serializer tx_in 10 DIN 2 IOE supports SDR, DDR, or Non-Registered Datapath IOE + - DOUT tx_out FPGA Fabric LVDS Transmitter tx_coreclock 3 (LVDS_LOAD_EN, diffioclk, tx_coreclock) Center/Corner PLL tx_inclock LVDS Clock Domain Notes to Figure 8-4: (1) All disabled blocks and signals are grayed out. (2) In DDR mode, tx_inclock clocks the IOE register. In SDR mode, data is directly passed through the IOE. (3) In SDR and DDR mode, the data width to the IOE is 1 and 2, respectively. Differential applications often require specific clock-to-data alignments or specific data rate to clock rate factors. You can configure any Arria II GX LVDS transmitter to generate a source-synchronous transmitter clock output. This flexibility allows the placement of the output clock near the data outputs to simplify board layout and reduce clock-to-data skew. The output clock can also be divided by a factor of 1, 2, 4, 6, 8, or 10, depending on the serialization factor. The phase of the clock in relation to the data can be set at 0 or 180 (edge or center aligned). The center and corner PLLs provide additional support for other phase shifts in 45 increments. Figure 8-5 shows the Arria II GX LVDS transmitter in clock output mode. In clock output mode, you can use an LVDS data channel as a clock output channel. Figure 8-5. Arria II GX LVDS Transmitter in Clock Output Mode Transmitter Circuit Parallel Series txclkout+ txclkout- FPGA Fabric center/ corner PLL diffioclk LVDS_LOAD_EN (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 8-8 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices Differential Receiver Differential Receiver Figure 8-6 shows a block diagram of an LVDS receiver in the right I/O bank. Figure 8-6. LVDS Receiver Block Diagram (Note 1), (2) LVDS Receiver IOE Supports SDR, DDR, or Non-Registered Datapath 2 rx_out + IOE 10 rx_in Synchronizer Deserializer Bit Slip DOUT DIN DOUT DIN DPA Circuitry Retimed Data DOUT DIN DIN FPGA Fabric 2 DPA Clock Clock Multiplexer rx_divfwdclk DPA_diffioclk LVDS_diffiioclk diffioclk (LOAD_EN, diffioclk) 3 (DPA_LOAD_EN, DPA_diffioclk, rx_divfwdclk) rx_outclock 3 (LVDS_LOAD_EN, LVDS_diffioclk, rx_outclk) LVDS Clock Domain DPA Clock Domain 8 Serial LVDS Clock Phases Center/Corner PLL rx_inclock Notes to Table 8-6: (1) In SDR and DDR mode, the data width from the IOE is 1 and 2, respectively. (2) The rx_out port has a maximum data width of 10. The center/corner PLL receives the external reference clock input (rx_inclock) and generates eight different phases of the same clock. The DPA block chooses one of the eight clock phases from the center/corner PLL and aligns to the incoming data to maximize receiver skew margin. The synchronizer circuit is a 1-bit wide by 6-bit deep FIFO buffer that compensates for any phase difference between the DPA block and the deserializer. If necessary, the user-controlled data realignment circuitry inserts a single bit of latency in the serial bit stream to align to the word boundary. The deserializer converts the serial data to parallel data, and sends the parallel data to the FPGA fabric. The physical medium connecting the LVDS transmitter and the receiver channels may introduce skew between the serial data and the source synchronous clock. The instantaneous skew between each LVDS channel and the clock also varies with the jitter on the data and clock signals, as seen by the receiver. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices Differential Receiver 8-9 The Arria II GX family supports the following receiver modes to overcome skew between the source-synchronous or reference clock and the received serial data: 1 Non-DPA mode DPA mode Soft-clock data recovery (CDR) mode Dedicated SERDES and DPA circuitry only exist on the right side of the device. Top and bottom IO banks only support non-DPA mode, in which the serializer and deserializer are implemented in the core logic. Dynamic Phase Alignment (DPA) Block The DPA block takes in high-speed serial data from the differential input buffer and selects the optimal phase from one of the eight clock phases generated by the center/corner PLL to sample the data. The eight phases of the clock are equally divided, giving a 45 resolution. The maximum phase offset between the received data and the selected phase is 1/8 unit interval (UI), which is the maximum quantization error of the DPA. The optimal clock phase selected by the DPA block (DPA_diffioclk) is also used to write data into the FIFO buffer or to clock the SERDES for soft-CDR operation. Figure 8-7 shows the possible phase relationships between the DPA clocks and the incoming serial data. Figure 8-7. DPA Clock Phase to Serial Data Timing Relationship (Note 1) rx_in D0 D1 D2 D3 D4 Dn 0 45 90 135 180 225 270 315 Tvco 0.125Tvco Note to Figure 8-7: (1) TVCO is defined as the PLL serial clock period. The DPA block requires a training pattern and a training sequence of at least 256 repetitions. The training pattern is not fixed, so you can use any training pattern with at least one transition. An optional user controlled signal (rx_dpll_hold) freezes the DPA on its current phase when asserted. This is useful if you do not want the DPA to continuously adjust phase after initial phase selection. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 8-10 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices Differential Receiver The DPA loses lock when it switches phases to maintain an optimal sampling phase. Once locked, the DPA can lose lock under either of the following conditions: One phase change (adjacent to the current phase) Two phase changes in the same direction An independent reset signal (rx_reset) is routed from the FPGA fabric to reset the DPA circuitry in user mode. The DPA circuitry must be retrained after reset. Synchronizer The synchronizer is a 1-bit wide and 6-bit deep FIFO buffer that compensates for the phase difference between the DPA_diffioclk and the high-speed clock (LVDS_diffioclk) produced by the center/corner PLL. Because every DPA channel might have a different phase selected to sample the data, the FIFO buffer is needed to synchronize the data to the high-speed LVDS clock domain. The synchronizer can only compensate for phase differences, not frequency differences between the data and the receiver's input reference clock, and is automatically reset when the DPA first locks to the incoming data. An optional signal (rx_fifo_reset) is available to the FPGA fabric to reset the synchronizer. Altera(R) recommends using rx_fifo_reset to reset the synchronizer when the DPA signal is in a loss-of-lock condition and data checker indicates corrupted received data. Data Realignment Block (Bit Slip) Skew in the transmitted data along with skew added by the link causes channel-to-channel skew on the received serial data streams. If DPA is enabled, the received data is captured with different clock phases on each channel. This might cause the received data to be misaligned from channel to channel. To compensate for this channel-to-channel skew and establish the correct received word boundary at each channel, each receiver channel has a dedicated data realignment circuit that realigns the data by inserting bit latencies into the serial stream. An optional signal (rx_channel_data_align) controls the bit insertion of each receiver independently controlled from the internal logic. The data slips one bit on the rising edge of rx_channel_data_align. The following are requirements for the rx_channel_data_align signal: An edge-triggered signal The minimum pulse width is one period of the parallel clock in the logic array The minimum low time between pulses is one period of the parallel clock Holding rx_channel_data_align does not result in extra slips Valid data is available two parallel clock cycles after the rising edge of the rx_channel_data_align signal Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices Differential Receiver 8-11 Figure 8-8 shows receiver output after one bit-slip pulse with the deserialization factor set to 4. Figure 8-8. Data Realignment Timing rx_inclock rx_in 3 2 1 0 3 2 1 0 3 2 1 0 rx_outclock rx_channel_data_align rx_out 3210 321x xx21 0321 The data realignment circuit can have up to 11 bit-times of insertion before a rollover occurs. The programmable bit rollover point can be from 1 to 11 bit-times, independent of the deserialization factor. The programmable bit rollover point needs to be set to equal to or greater than the deserialization factor, allowing enough depth in the word alignment circuit to slip through a full word. You can set the value of the bit rollover point using the ALTLVDS megafunction. An optional status signal (rx_cda_max) is available to the FPGA fabric from each channel to indicate when the preset rollover point is reached. Figure 8-9 shows a preset value of four-bit times before rollover occurs. The rx_cda_max signal pulses for one rx_outclock cycle to indicate that the rollover has occurred. Figure 8-9. Receiver Data Re-Alignment Rollover rx_inclock rx_channel_data_align rx_outclock rx_cda_max Deserializer The deserializer, which includes shift registers and parallel load registers, converts the serial data from the bit slip to parallel data before sending the data to the FPGA fabric. The deserialization factor supported is 4, 6, 7, 8, or 10. The deserializer can be bypassed to support DDR (x2) and SDR (x1) operations, as shown in Figure 8-10. The DPA and data realignment circuit cannot be used when the deserializer is bypassed. The IOE contains two data input registers that can operate in DDR or SDR mode. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 8-12 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices Differential Receiver Figure 8-10. Arria II GX Deserializer Bypass (Note 1), (2), (3) LVDS Receiver IOE Supports SDR, DDR, or Non-Registered Datapath 2 rx_out + IOE 2 rx_in Synchronizer Deserializ Deser Deserializer ializer er Bit Slip DOUT DIN DOUT DIN DPA P Circuitry Retimed Data DOUT DIN DIN FPGA Fabric 2 DPA P Clock rx_divfwdclk DPA_diffioclk P Clock Multiplexer p L LVDS_diffiioclk diffioclk (LOAD_EN, diffioclk) 3 (DPA_LO P AD_EN, DPA_diffioclk, P rx_divfwdclk) rx_outclock 3 (LVDS_LO L AD_EN, L LVDS_diffioclk, rx_outclk) 8 Serial LVDS L Clock Phases Center/Corner PLL Notes to Figure 8-10: (1) All disabled blocks and signals are grayed out. (2) In DDR mode, rx_inclock clocks the IOE register. In SDR mode, data is directly passed through the IOE. (3) In SDR and DDR mode, the data width from the IOE is 1 and 2, respectively. Receiver Data Path Modes The Arria II GX device family supports three receiver datapath modes: Non-DPA mode DPA mode soft-CDR mode Non-DPA Mode Non-DPA mode allows you to statically select the optimal phase between the source-synchronous reference clock and the input serial data to compensate for any skew between the two signals. The reference clock must be a differential signal. Figure 8-11 shows the non-DPA datapath block diagram. Input serial data is registered at the rising or falling edge of the LVDS_diffioclk clock produced by the center/corner PLL. You can select the rising/falling edge option using the ALTLVDS megafunction. Both data realignment and deserializer blocks are clocked by the LVDS_diffioclk clock. 1 Arria II GX Device Handbook Volume 1 You should perform board trace skew compensation at data rate above 840Mbps in non-DPA mode. (c) February 2009 Altera Corporation Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices Differential Receiver 8-13 Figure 8-11. Receiver Datapath in Non-DPA Mode (Note 1), (2), (3) LVDS Receiver IOE Supports SDR, DDR, or Non-Registered Datapath 2 rx_out + IOE 10 rx_in Synchronizer Deserializer Bit Slip DOUT DIN DOUT DIN DPA P Circuitry Retimed Data DOUT DIN N DIN FPGA Fabric 2 DPA P Clock Clock Multiplexer rx_divfwdclk DPA_diffioclk P L LVDS_diffiioclk diffioclk (LOAD_EN, diffioclk) 3 (DPA_LO P AD_EN, DPA_diffioclk, P rx_divfwdclk) rx_outclock 3 (LVDS_LOAD_EN, LVDS_diffioclk, rx_outclk) 8 Serial LVDS L Clock Phases Center/Corner PLL rx_inclock LVDS Clock Domain Notes to Figure 8-11: (1) All disabled blocks and signals are grayed out. (2) In SDR and DDR mode, the data width from the IOE is 1 and 2, respectively. (3) The rx_out port has a maximum data width of 10. DPA Mode In DPA mode, the DPA circuitry automatically chooses the optimal phase between the source synchronous reference clock and the input serial data to compensate for the skew between the two signals. The reference clock must be a differential signal. Figure 8-12 shows the DPA mode receiver datapath block diagram. The DPA_diffioclk clock is used to write serial data into the synchronizer. The LVDS_diffioclk clock is used to read the serial data from the synchronizer. The same LVDS_diffioclk clock is used in the data realignment and deserializer blocks. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 8-14 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices Differential Receiver Figure 8-12. Receiver Datapath in DPA Mode (Note 1), (2), (3) LVDS Receiver IOE Supports SDR, DDR, or Non-Registered Datapath 2 rx_out + IOE 10 rx_in Synchronizer Deserializer Bit Slip DOUT DIN DOUT DIN DPA Circuitry Retimed Data DOUT DIN DIN FPGA Fabric 2 DPA Clock Clock Multiplier rx_divfwdclk DPA_diffioclk LVDS_diffiioclk diffioclk (LOAD_EN, diffioclk) 3 (DPA_LOAD_EN, DPA_diffioclk, rx_divfwdclk) rx_outclock 3 (LVDS_LOAD_EN, LVDS_diffioclk, rx_outclk) LVDS Clock Domain DPA Clock Domain 8 Serial LVDS Clock Phases Center/Corner PLL rx_inclock Notes to Figure 8-12: (1) All disabled blocks and signals are grayed out. (2) In SDR and DDR mode, the data width from the IOE is 1 and 2, respectively. (3) The rx_out port has a maximum data width of 10. Soft-CDR Mode Figure 8-13 shows the soft-CDR mode datapath block diagram. In soft-CDR mode, the PLL uses the local clock source as the reference clock. The reference clock must be a differential signal. The DPA continuously changes its phase to track the parts-permillion (PPM) difference between the upstream transmitter and the local receiver reference input clocks. The DPA_diffioclk clock is used for bit-slip operation and deserialization. The DPA_diffioclk clock is divided by the deserialization factor to produce the rx_divfwdclk clock, which is then forwarded to the FPGA fabric. The receiver output data (rx_out) to the FPGA fabric is synchronized to this clock. The parallel clock rx_outclock, generated by the center/corner PLL, is also forwarded to the FPGA fabric. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices Programmable Pre-Emphasis and Programmable VOD. 8-15 Figure 8-13. Receiver Datapath in Soft-CDR Mode (Note 1), (2), (3) LVDS Receiver IOE Supports SDR, DDR, or Non-Registered Datapath 2 rx_out + IOE 10 rx_in Synchronizer Deserializer Bit Slip DOUT DIN DOUT DIN DPA Circuitry Retimed Data DOUT DIN DIN FPGA Fabric 2 DPA Clock Clock Multiplexer rx_divfwdclk DPA_diffioclk LVDS_diffiioclk diffioclk (LOAD_EN, diffioclk) 3 (DPA_LOAD_EN, DPA_diffioclk, rx_divfwdclk) rx_outclock 3 (LVDS_LOAD_EN, LVDS_diffioclk, rx_outclk) 8 Serial LVDS Clock Phases LVDS Clock Domain DPA Clock Domain Center/Corner PLL rx_inclock Notes to Figure 8-13: (1) All disabled blocks and signals are grayed out. (2) In SDR and DDR mode, the data width from the IOE is 1 and 2, respectively. (3) The rx_out port has a maximum data width of 10. Programmable Pre-Emphasis and Programmable V . OD Pre-emphasis increases the amplitude of the high frequency component of the output signal and thus helps to compensate for the frequency-dependent attenuation along the transmission line. Figure 8-14 shows the LVDS output single-ended waveform with and without pre-emphasis. The definition of VOD is also shown. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 8-16 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices Programmable Pre-Emphasis and Programmable VOD. Figure 8-14. LVDS Output Single-Ended Waveform with and without Programmable Pre-Emphasis (Note 1) OUT VOD OUT Without Programmable Pre-emphasis VP OUT VOD OUT VP With Programmable Pre-emphasis Note to Figure 8-14: (1) VP-- voltage boost from pre-emphasis. Pre-emphasis is an important feature for high-speed transmission. Without pre-emphasis, the output current is limited by the VOD setting and the output impedance of the driver. At high frequency, the slew rate may not be fast enough to reach the full VOD before the next edge, producing a pattern-dependent jitter. With pre-emphasis, the output current is boosted momentarily during switching to increase the output slew rate. The overshoot introduced by the extra current happens only during switching and does not ring, unlike the overshoot caused by signal reflection. This overshoot should not be included in the V OD voltage. There are two pre-emphasis settings for each LVDS output buffer: no pre-emphasis and medium. The default setting is medium. Table 8-4 shows the assignment name and its possible values for programmable pre-emphasis in the Quartus II software Assignment Editor. The setting of no pre-emphasis is 1 and the setting of medium is 0. Table 8-4. Programmable Pre-emphasis Settings in Quartus II Software Assignment Editor Assignment name Programmable Pre-emphasis Allowed values 0, 1 There is one VOD setting for each LVDS output buffer. Table 8-5 shows the assignment name and the value for programmable VOD in the Quartus II software Assignment Editor. Table 8-5. Programmable VOD Settings in Quartus II Software Assignment Editor Assignment name Programmable Differential Output Voltage (VOD) Allowed values 2 Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices Differential I/O Termination 8-17 Differential I/O Termination The Arria II GX device family provides 100- differential OCT support for LVDS input buffers in top, right, and bottom I/O banks. OCT saves board space by not adding external resistors on the board. You can enable OCT in the Quartus II software Assignment Editor. Figure 8-15 shows LVDS input OCT. Clock input pins (CLK[4..15]) do not support OCT. Figure 8-15. LVDS Input Buffer On-Chip Differential I/O Termination Arria II GX Differential Receiver with On-Chip 100 Termination LVDS Transmitter Z0 = 50 RD Z0 = 50 Table 8-6 shows the assignment name and its value for on-chip differential input termination in the Quartus II software Assignment Editor. Table 8-6. On-Chip Differential Input Termination in Quartus II Software Assignment Editor Assignment name Input Termination (Accepts wildcards/groups) Allowed values Differential PLLs The Arria II GX device family contains up to six PLLs with up to four center and corner PLLs located on the right side of the device. The center/corner PLL on the right side of the device is used to generate parallel clocks (rx_outclock and tx_outclock) and high-speed clocks (diffioclk) for the SERDES and DPA circuitry. Figure 8-1 on page 8-3 shows the locations of the PLLs for Arria II GX devices. Clock switchover and dynamic reconfiguration are allowed using the center/corner PLLs in high-speed differential I/O support mode. f For more information about PLLs, refer to the Clock Network and PLLs in Arria II GX Devices chapter in volume 1 of the Arria II GX Device Handbook. LVDS and DPA Clock Networks The Arria II GX device family only has LVDS and DPA clock networks on the right side of the device. The center/corner PLLs feed into the differential transmitter and receiver channels through the LVDS and DPA clock networks. Figure 8-16 and Figure 8-17 show the LVDS clock tree for family members without center PLLs and with center PLLs, respectively. The center PLLs can drive the LVDS clock tree above and below them. In Arria II GX devices with or without center PLLs, the corner PLLs can drive both top and bottom LVDS clock tree. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 8-18 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices Source-Synchronous Timing Budget Figure 8-16. LVDS and DPA Clock Networks in the Arria II GX Family without Center PLLs 4 Corner PLL Quadrant Quadrant No LVDS and DPA clock networks on the left side of the device 4 DPA Clock LVDS 8 Clock 4 Quadrant Quadrant Corner PLL 4 Figure 8-17. LVDS and DPA Clock Networks in the Arria II GX Family with Center PLLs Corner PLL 4 4 Quadrant Quadrant DPA Clock LVDS 8 Clock Center PLL No LVDS and DPA clock networks on the left side of the device Center PLL Quadrant Quadrant DPA Clock 4 4 LVDS 8 Clock 4 Corner PLL 4 Source-Synchronous Timing Budget This section describes the timing budget, waveforms, and specifications for source-synchronous signaling in the Arria II GX device family. Timing analysis for the differential block is different from traditional synchronous timing analysis techniques. Therefore, it is important to understand how to analyze timing for high-speed differential signals. This section defines the source-synchronous differential data orientation timing parameters, timing budget definitions, and how to use these timing parameters to determine your design's maximum performance. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices Source-Synchronous Timing Budget 8-19 Differential Data Orientation There is a set relationship between an external clock and the incoming data. For operation at 1 Gbps and a serialization factor of 10, the external clock is multiplied by 10. You can set the phase-alignment in the PLL to coincide with the sampling window of each data bit. The data is sampled on the falling edge of the multiplied clock. Figure 8-18 shows the data bit orientation of the x10 mode. Figure 8-18. Bit Orientation inclock/outclock 10 LVDS Bits MSB data in 9 8 7 6 5 4 LSB 3 2 1 0 Differential I/O Bit Position Data synchronization is necessary for successful data transmission at high frequencies. Figure 8-19 shows data bit orientation for a channel operation. These figures are based on the following: Serialization factor equals clock multiplication factor Edge alignment is selected for phase alignment Implemented in hard SERDES For other serialization factors, use the Quartus II software tools and find the bit position in the word. The bit positions after deserialization are listed in Table 8-7. Figure 8-19. Bit Order and Word Boundary for One Differential Channel (Note 1) Transmitter Channel Operation (x8 Mode) tx_outclock tx_out X Current Cycle Next Cycle Previous Cycle X X X X X X X 7 6 5 4 3 2 1 0 X X X X X X X X MSB LSB Receiver Channel Operation (x8 Mode) rx_inclock rx_in 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X X X X X X X X X rx_outclock XXXXXXXX rx_out [7..0] XXXXXXXX XXXX7654 3210XXXX Note to Figure 8-19: (1) These are only functional waveforms and are not intended to convey timing information. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 8-20 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices Source-Synchronous Timing Budget Table 8-7 shows the conventions for differential bit naming for 18 differential channels. The MSB and LSB positions increase with the number of channels used in a system. Table 8-7. Differential Bit Naming Internal 8-Bit Parallel Data Receiver Channel Data Number MSB Position LSB Position 1 7 0 2 15 8 3 23 16 4 31 24 5 39 32 6 47 40 7 55 48 8 63 56 9 71 64 10 79 72 11 87 80 12 95 88 13 103 96 14 111 104 15 119 112 16 127 120 17 135 128 18 143 136 Receiver Skew Margin for Non-DPA Mode Changes in system environment, such as temperature, media (cable, connector, or PCB), and loading, effect the receiver 's setup and hold times; internal skew affects the sampling ability of the receiver. Different modes of LVDS receivers use different specifications, which can help in deciding the ability to sample the received serial data correctly. In DPA mode, use DPA jitter tolerance instead of receiver skew margin (RSKM). In non-DPA mode, RSKM, transmitter channel-to-channel skew (TCCS), and sampling window (SW) specifications are used for high-speed source-synchronous differential signals in the receiver data path. The relationship between RSKM, TCCS, and SW can be expressed by the RSKM equation shown in Equation 8-1: Equation 8-1. RSKM = (TUI - SW - TCCS)/2 Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices Differential Pin Placement Guidelines 8-21 Where: TUI--the time period of the serial data. RSKM--the timing margin between the receiver's clock input and the data input SW. SW--the period of time that the input data must be stable to ensure that data is successfully sampled by the LVDS receiver. The sampling window is device property and varies with device speed grade. TCCS--the difference between the fastest and slowest data output transitions, including the tCO variation and clock skew. You must calculate the RSKM value to decide whether or not data can be sampled properly by the LVDS receiver with the given data rate and device. A positive RSKM value indicates the LVDS receiver can sample the data properly; a negative RSKM indicates the receiver cannot sample the data properly. Figure 8-20 shows the relationship between the RSKM, TCCS, and SW. Figure 8-20. Differential High-Speed Timing Diagram and Timing Budget for Non-DPA External Input Clock Time Unit Interval (TUI) Internal Clock Receiver Input Data TCCS RSKM RSKM TCCS Sampling Window (SW) For LVDS receivers, the Quartus II software provides the RSKM report showing SW, TUI, and RSKM values for non-DPA mode. You can generate the RSKM by executing the report_RSKM command in the TimeQuest Timing Analyzer. You can find the RSKM report in the Quartus II Compilation report under TimeQuest Timing Analyzer section. 1 To obtain the RSKM value, assign an appropriate input delay to the LVDS receiver through the TimeQuest Timing Analyzer constraints menu Differential Pin Placement Guidelines To ensure proper high-speed operation, differential pin placement guidelines are established. The Quartus II compiler automatically checks that these guidelines are followed and issues an error message if they are not adhered to. This section is divided into pin placement guidelines with and without DPA usage. 1 (c) February 2009 DPA-enabled differential channels refer to DPA mode or soft-CDR mode; DPA-disabled channels refer to non-DPA mode. Altera Corporation Arria II GX Device Handbook Volume 1 8-22 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices Differential Pin Placement Guidelines DPA-Enabled Channels and Single-Ended I/Os When single-ended I/Os and LVDS I/Os share the same I/O bank, the placement of single-ended I/O pins with respect to LVDS I/O pins is restricted. The constraints on single-ended I/Os placement with respect to DPA-enabled or DPA-disabled LVDS I/Os are the same. f For more information about pin placement with respect to LVDS, mini-LVDS, and RSDS, refer to the I/O Management chapter in volume 2 of the Quartus II Development Software Handbook. Guidelines for DPA-Enabled Differential Channels When you use DPA-enabled channels, you must adhere to the guidelines listed in the following sections. DPA-Enabled Channel Driving Distance If the number of DPA-enabled channels driven by each center or corner PLL exceeds 25 logic array blocks (LAB) rows, Altera recommends implementing data realignment (bit slip) circuitry for all the DPA channels. Using Center and Corner PLLs If the DPA-enabled channels in a bank are being driven by two PLLs, where the corner PLL is driving one group and the center PLL is driving another group, there must be at least one row of separation between the two groups of DPA-enabled channels, as shown in Figure 8-21. This is to prevent noise mixing because the two groups can operate at independent frequencies. No separation is necessary if a single PLL is driving both the DPA-enabled channels and DPA-disabled channels. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices Differential Pin Placement Guidelines 8-23 Figure 8-21. Center and Corner PLLs Driving DPA-Enabled Differential I/Os in the Same Bank Corner PLL Reference CLK DPA -enabled Diff I/O DPA - enabled Diff I/O DPA - enabled Diff I/O Channels driven by Corner PLL DPA - enabled Diff I/O DPA - enabled Diff I/O Diff I/O DPA-enabled Diff I/O DPA-enabled Diff I/O DPA -enabled Diff I/O Channels driven by Center PLL DPA-enabled Diff I/O Reference CLK Center PLL Using Both Center PLLs (c) February 2009 You can use both center PLLs to drive DPA-enabled channels simultaneously, as long as they drive these channels in their adjacent banks only, as shown in Figure 8-21. If one of the center PLLs drives the DPA-enabled channels in the upper and lower I/O banks, the other center PLL cannot be used for DPA, as shown in Figure 8-22. Altera Corporation Arria II GX Device Handbook Volume 1 8-24 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices Differential Pin Placement Guidelines Figure 8-22. Center PLLs Driving DPA-Enabled Differential I/Os DPA-enabled Diff I/O DPA-enabled Diff I/O DPA-enabled Diff I/O DPA-enabled Diff I/O DPA-enabled Diff I/O Reference CLK DPA-enabled Diff I/O DPA-enabled Diff I/O DPA-enabled Diff I/O Reference CLK Center PLL Center PLL Center PLL Center PLL Reference CLK DPA-enabled Diff I/O DPA-enabled Diff I/O DPA-enabled Diff I/O Reference CLK DPA-enabled Diff I/O DPA-enabled Diff I/O DPA-enabled Diff I/O DPA-enabled Diff I/O DPA-enabled Diff I/O Unused PLL If the upper center PLL drives DPA-enabled channels in the lower I/O bank, the lower center PLL cannot drive DPA enabled channels in the upper I/O bank, and vice versa. In other words, the center PLLs cannot drive cross-banks simultaneously, as shown in Figure 8-23. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices Differential Pin Placement Guidelines 8-25 Figure 8-23. Invalid Placement of DPA-Disabled Differential I/Os Driven by Both Center PLLs DPA-disabled Diff I/O DPA-disabled Diff I/O DPA-disabled Diff I/O DPA-disabled Diff I/O Reference CLK Center PLL Center PLL Reference CLK DPA-disabled Diff I/O DPA-disabled Diff I/O DPA-disabled Diff I/O DPA-disabled Diff I/O Using Both Corner PLLs (c) February 2009 You can use both corner PLLs to drive DPA-enabled channels simultaneously, as long as they drive the channels in their adjacent banks only. There must be at least one row of separation between the two groups of DPA-enabled channels. If one of the corner PLLs drives DPA-enabled channels in the upper and lower I/O banks, the center PLLs cannot be used. The other corner PLL can be used to drive DPA-enabled channels in their adjacent bank only. There must be at least one row of separation between the two groups of DPA-enabled channels. See Figure 8-24. Altera Corporation Arria II GX Device Handbook Volume 1 8-26 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices Differential Pin Placement Guidelines If the upper corner PLL drives DPA-enabled channels in the lower I/O bank, the lower corner PLL cannot drive DPA-enabled channels in the upper I/O bank, and vice versa. In other words, the corner PLLs cannot drive cross-banks simultaneously, as shown in Figure 8-24. Figure 8-24. Corner PLLs Driving DPA-Enabled Differential I/Os Upper Corner PLL Reference CLK DPA -enabled Diff I/O DPA - enabled Diff I/O Upper I/O Bank Diff I/O DPA - enabled Diff I/O DPA - enabled Diff I/O Center PLL Center PLL Unused PLLs DPA-enabled Diff I/O DPA -enabled Diff I/O Lower I/O Bank DPA- enabled Diff I/O Reference CLK Lower Corner PLL Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices Differential Pin Placement Guidelines 8-27 Guidelines for DPA-Disabled Differential Channels When you use DPA-disabled channels, you must adhere to the guidelines in the following sections. DPA-Disabled Channel Driving Distance Each PLL can drive all the DPA-disabled channels in the entire bank. Using Corner and Center PLLs (c) February 2009 You can use a corner PLL to drive all transmitter channels and you can use a center PLL to drive all DPA-disabled receiver channels in the same I/O bank. In other words, you can drive a transmitter channel and a receiver channel in the same LAB row by two different PLLs, as shown in Figure 8-25. A corner PLL and a center PLL can drive duplex channels in the same I/O bank, as long as the channels driven by each PLL are not interleaved. No separation is necessary between the group of channels driven by the corner and center PLLs. See Figure 8-25 and Figure 8-26. Altera Corporation Arria II GX Device Handbook Volume 1 8-28 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices Differential Pin Placement Guidelines Figure 8-25. Corner and Center PLLs Driving DPA-Disabled Differential I/Os in the Same Bank Corner PLL Reference CLK Corner PLL Reference CLK Diff RX Diff TX Diff RX Diff TX Diff RX Diff TX Diff RX Diff TX Diff RX Diff TX Diff RX Diff TX Diff RX Diff TX Diff RX Diff TX Diff RX Diff TX DPA-disabled Diff I/O Diff RX Diff TX DPA-disabled Diff I/O Reference CLK Center PLL Arria II GX Device Handbook Volume 1 DPA-disabled Diff I/O DPA-disabled Diff I/O DPA-disabled Diff I/O DPA-disabled Diff I/O DPA-disabled Diff I/O DPA-disabled Diff I/O DPA-disabled Diff I/O DPA-disabled Diff I/O Channels driven by Corner PLL No separation buffer needed Channels driven by Center PL Reference CLK Center PLL (c) February 2009 Altera Corporation Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices Differential Pin Placement Guidelines 8-29 Figure 8-26. Invalid Placement of DPA-Disabled Differential I/Os Due to Interleaving of Channels Driven by the Corner and Center PLLs Corner PLL Reference CLK DPA-disabled Diff I/O DPA-disabled Diff I/O DPA-disabled Diff I/O DPA-disabled Diff I/O DPA-disabled Diff I/O DPA-disabled Diff I/O DPA-disabled Diff I/O DPA-disabled Diff I/O DPA-disabled Diff I/O DPA-disabled Diff I/O Reference CLK Center PLL Using Both Center PLLs You can use both center PLLs simultaneously to drive DPA disabled channels on upper and lower I/O banks. Unlike DPA-enabled channels, the center PLLs can drive DPA-disabled channels cross-banks. For example, the upper center PLL can drive the lower I/O bank at the same time the lower center PLL is driving the upper I/O bank, and vice versa, as shown in Figure 8-27. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 8-30 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices Differential Pin Placement Guidelines Figure 8-27. Both Center PLLs Driving Cross-Bank DPA-Disabled Channels Simultaneously DPA-disabled Diff I/O DPA-disabled Diff I/O DPA-disabled Diff I/O DPA-disabled Diff I/O Reference CLK Center PLL Center PLL Reference CLK DPA-disabled Diff I/O DPA-disabled Diff I/O DPA-disabled Diff I/O DPA-disabled Diff I/O Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices Setting Up an LVDS Transmitter or Receiver Channel 8-31 Using Both Corner PLLs You can use both corner PLLs to drive DPA disabled channels simultaneously. Both corner PLLs can drive cross-banks. You can use a corner PLL to drive all the transmitter channels and you can use the other corner PLL to drive all DPA-disabled receiver channels in the same I/O bank. Both corner PLLs can drive duplex channels in the same I/O bank, as long as the channels driven by each PLL are not interleaved. No separation is necessary between the group of channels driven by both corner PLLs. Setting Up an LVDS Transmitter or Receiver Channel Altera's ALTLVDS megafunction offers you the ease of setting up an LVDS transmitter or receiver channel. You can control the settings of SERDES and DPA circuitry in the ALTLVDS megafunction. When you instantiate an ALTLVDS megafunction, the PLL is instantiated automatically and you can set the parameters of the PLL. This simplifies the clocking setup for the LVDS transmitter or receiver channels. However, the drawback is reduced flexibility in PLL utilization. The ALTLVDS megafunction provides an option for implementing the LVDS transmitter or receiver interfaces with external PLLs. With this option enabled, you can control the PLL settings, such as dynamically reconfiguring the PLLs to support different data rates, dynamic phase shift, and other settings. You also must instantiate an ALTPLL megafunction to generate the various clock and load enable signals. f For more information about how to control the PLL, SERDES, and DPA settings, and detail descriptions of the LVDS transmitter and receiver interface signals, refer to the ALTLVDS Megafunction User Guide. f For more information about the ALTPLL megafunction, refer to the ALTPLL Megafunction User Guide. Document Revision History Table 8-8 shows the revision history for this document. Table 8-8. Document Revision History Date and Document Version February 2009, v1.0 (c) February 2009 Changes Made Initial Release. Altera Corporation Summary of Changes -- Arria II GX Device Handbook Volume 1 8-32 Arria II GX Device Handbook Volume 1 Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices Document Revision History (c) February 2009 Altera Corporation Section III. System Integration This section provides information about Arria(R) II GX device configuration, design security, remote system upgrades, SEU mitigation, JTAG, and power requirements. This section includes the following chapters: Chapter 9, Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Chapter 10, SEU Mitigation in Arria II GX Devices Chapter 11, JTAG Boundary-Scan Testing Chapter 12, Power Requirements for Arria II GX Devices Revision History Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in this volume. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 III-2 Arria II GX Device Handbook Volume 1 Section III: System Integration (c) February 2009 Altera Corporation 9. Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices AIIGX51009-1.0 Introduction This chapter contains information about the Arria(R) II GX supported configuration schemes, instructions about how to execute the required configuration schemes, and all the necessary option pin settings. This chapter includes the following sections: "Configuration Features" on page 9-2 "Power-On Reset Circuit and Configuration Pins Power Supply" on page 9-3 "Configuration Process" on page 9-4 "Configuration Schemes" on page 9-6 "Fast Passive Parallel Configuration" on page 9-8 "Active Serial Configuration (Serial Configuration Devices)" on page 9-15 "Passive Serial Configuration" on page 9-22 "JTAG Configuration" on page 9-28 "Device Configuration Pins" on page 9-34 "Configuration Data Decompression" on page 9-40 "Remote System Upgrades" on page 9-42 "Remote System Upgrade Mode" on page 9-46 "Dedicated Remote System Upgrade Circuitry" on page 9-48 "Quartus II Software Support" on page 9-53 "Design Security" on page 9-54 Arria II GX devices use SRAM cells to store configuration data. As SRAM memory is volatile, you must download configuration data to the Arria II GX device each time the device powers up. You can configure Arria II GX devices using one of four configuration schemes: Fast passive parallel (FPP) Fast active serial (AS) Passive serial (PS) Joint Test Action Group (JTAG) All configuration schemes use either an external controller (for example, a MAX(R) II device or microprocessor), a configuration device, or a download cable. For more information about the configuration features, refer to "Configuration Features" on page 9-2. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 9-2 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Configuration Features Configuration Devices Altera(R) serial configuration devices support single-device and multi-device configuration solutions for Arria II GX devices and are used by the Fast AS configuration scheme. Serial configuration devices offer a low-cost, low pin-count configuration solution. f For information about serial configuration devices, refer to the Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet in volume 2 of the Configuration Handbook. 1 All minimum timing information in this chapter covers the entire Arria II GX device family. Some devices may work at less than the minimum timing stated in this chapter due to process variations Table 9-3 on page 9-7 shows the uncompressed raw binary file (.rbf) configuration file sizes for Arria II GX devices. Configuration Features Arria II GX devices offer decompression, design security, and remote system upgrade features. Arria II GX devices can receive a compressed configuration bitstream and decompress this data in real-time, reducing storage requirements and configuration time. Design security using configuration bitstream encryption is available in Arria II GX devices, which protects your designs. You can make real-time system upgrades of your Arria II GX designs from remote locations with the remote system upgrade feature. Table 9-1 summarizes which configuration features you can use in each configuration scheme. Table 9-1. Arria II GX Configuration Features Configuration Scheme Configuration Method Decompression Design Security Remote System Upgrade v (1) v (1) -- FPP MAX II device or a microprocessor with flash memory Fast AS Serial configuration device v v v (2) v v -- PS MAX II device or a microprocessor with flash memory Download cable v v -- MAX II device or a microprocessor with flash memory -- -- -- Download cable -- -- -- JTAG Notes to Table 9-1: (1) In these modes, the host system must send a DCLK that is x4 the data rate. (2) Remote system upgrade is only available in the Fast AS configuration scheme. Only remote update mode is supported when using the Fast AS configuration scheme. Local update mode is not supported. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Power-On Reset Circuit and Configuration Pins Power Supply 9-3 You can also refer to the following: For more information about the configuration data decompression feature, refer to "Configuration Data Decompression" on page 9-40. For more information about the remote system upgrade feature, refer to "Remote System Upgrades" on page 9-42. For more information about the design security feature, refer to the "Design Security" on page 9-54. For more information about the parallel flash loader (PFL), refer to AN 386: Using the MAX II Parallel Flash Loader with the Quartus II Software. If your system already contains a common flash interface (CFI) flash memory device, you can use it for the Arria II GX device configuration storage as well. The PFL feature in MAX II devices provides an efficient method to program CFI flash memory devices through the JTAG interface and logic to control configuration from the flash memory device to the Arria II GX device. Both PS and FPP configuration modes are supported using the PFL feature. For more information about programming Altera serial configuration devices, refer to "Programming Serial Configuration Devices" on page 9-20. Power-On Reset Circuit and Configuration Pins Power Supply The following section describes the power-on reset (POR) circuit and the power supply for the configuration pins. Power-On Reset Circuit The POR circuit keeps the entire system in reset mode until the power supply voltage levels have stabilized on power-up. Upon power-up, the device does not release nSTATUS until VCCCB, VCCA_PLL, VCC, VCCPD, and VCCIO for I/O banks 3C or 8C are above the device's POR trip point. On power down, brown-out occurs if VCC ramps down below the POR trip point and any of the VCC, VCCPD, or VCCIO for I/O banks 3C or 8C drops below the threshold level of the hot-socket circuitry. In Arria II GX devices, you can select between a fast POR time or a standard POR time, depending on the MSEL pin settings. The fast POR time is typically 4 ms for fast configuration time. The standard POR time is typically 100 ms, which has a lower power-ramp rate. VCCIO Pins for I/O Banks 3C and 8C In Arria II GX devices, all the dedicated configuration pins and some of the dual function pins are supplied by the VCCIO for I/O banks 3C and 8C in which they reside. The supported configuration voltages are 1.8, 2.5, 3.0, and 3.3 V. Arria II GX devices do not support the 1.5-V configuration. You must use VCCIO for I/O banks 3C and 8C to power all dedicated configuration inputs, dedicated configuration outputs, dedicated configuration bidirectional pins, and some of the dual functional pins that you use for configuration. With VCCIO for I/O banks 3C and 8C, configuration input buffers do not have to share power lines with the regular I/O buffer. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 9-4 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Configuration Process The operating voltage for the configuration input pin is independent of the I/O bank's power supply V CCIO during configuration. Therefore, no configuration voltage constraints on V CCIO are needed in Arria II GX devices. VCCPD Pins Arria II GX devices have a dedicated programming power supply, V CCPD, which must be connected to 3.3 V, 3.0 V, or 2.5 V to power the I/O pre-drivers, the JTAG output pin (TDO), and the MSEL[3..0] pins. 1 VCCPD and VCCIO for I/O banks 3C and 8C must ramp up from 0 V to the desired voltage level in 100 ms when you select standard POR time or 4 ms when you select fast POR time. If these supplies are not ramped up in this specified time, your Arria II GX device will not configure successfully. If your system cannot ramp up the power supplies in 100 ms or 4 ms, you must hold nCONFIG low until all the power supplies are stable. 1 You must connect VCCPD according to the I/O standard used in the same bank: For 3.3-V I/O standards, connect V CCPD to 3.3 V For 3.0-V I/O standards, connect V CCPD to 3.0 V For 2.5-V and below I/O standards, connect V CCPD to 2.5 V For more information about configuration pins power supply, refer to "Device Configuration Pins" on page 9-34. Configuration Process The following sections describe the general configuration process for FPP, Fast AS, and PS schemes. Power Up To begin the configuration process, you must fully power V CC, VCCCB, VCCA_PLL, VCCPD, and VCCIO (including I/O banks 3C and 8C where the configuration and JTAG pins reside) to the appropriate voltage levels. 1 For FPP configuration, pins DATA[7..1] will be used and they are supplied by the VCCIO for I/O bank 6A. This bank needs to be powered up when FPP configuration is used. Reset Upon power-up, the Arria II GX device goes through a POR. The POR delay is dependent on the MSEL pin settings. During POR, the device resets, holds nSTATUS low, clears configuration RAM bits, and tri-states all user I/O pins. Once the device successfully exits POR, all user I/O pins continue to be tri-stated. While nCONFIG is low, the device is in reset. When the device comes out of reset, nCONFIG must be at a logic-high level in order for the device to release the open-drain nSTATUS pin. After nSTATUS is released, it is pulled high by a pull-up resistor and the device is ready to receive configuration data. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Configuration Process 9-5 Before and during configuration, all user I/O pins are tri-stated. If nIO_pullup is driven low during power up and configuration, the user I/O pins and dual-purpose I/O pins have weak pull-up resistors, which are on (after POR) before and during configuration. If nIO_pullup is driven high, the weak pull-up resistors are disabled. Configuration nCONFIG and nSTATUS must be at a logic-high level in order for the configuration stage to begin. The device receives configuration data on its DATA pins and (for synchronous configuration schemes) the clock source on the DCLK pin. Configuration data is latched into the FPGA on the rising edge of DCLK. After the FPGA has received all the configuration data successfully, it releases the CONF_DONE pin, which is pulled high by a pull-up resistor. A low-to-high transition on CONF_DONE indicates configuration is complete and initialization of the device can begin. To ensure DCLK and DATA0 are not left floating at the end of configuration, they must be driven either high or low, whichever is convenient on your board. DATA[0] is a dedicated pin that is used for both passive and active configuration modes. It is not available as a user I/O pin after configuration. For FPP and PS configuration schemes, the configuration clock (DCLK) speed must be below the specified frequency to ensure correct configuration. No maximum DCLK period exists, which means you can pause the configuration by halting DCLK for an indefinite amount of time. A reconfiguration is initiated by toggling the nCONFIG pin from high to low and then back to high with a minimum tCFG low-pulse width either in the configuration, configuration error, initialization, or user mode stage. When nCONFIG is pulled low, nSTATUS and CONF_DONE are also pulled low and all I/O pins are tri-stated. Once nCONFIG and nSTATUS return to a logic-high level, configuration begins. Configuration Error If an error occurs during configuration, Arria II GX devices assert the nSTATUS signal low, indicating a data frame error; the CONF_DONE signal stays low. If the Auto-restart configuration after error option (available in the Quartus II software from the General tab of the Device and Pin Options dialog box) is turned on, the Arria II GX device resets the configuration device and retries the configuration. If this option is turned off, the system must monitor nSTATUS for errors and then pulse nCONFIG low to restart the configuration. Initialization In Arria II GX devices, the initialization clock source is either the internal oscillator or the optional CLKUSR pin. By default, the internal oscillator is the clock source for initialization. If you use the internal oscillator, the Arria II GX device provides itself with enough clock cycles for proper initialization. Therefore, if the internal oscillator is the initialization clock source, sending the entire configuration file to the device is sufficient to configure and initialize the device. Driving DCLK to the device after configuration is complete does not affect device operation. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 9-6 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Configuration Schemes You also have the flexibility to synchronize initialization of multiple devices or to delay initialization with the CLKUSR option. You can turn on the Enable user-supplied start-up clock (CLKUSR) option in the Quartus II software from the General tab of the Device and Pin Options dialog box. If you supply a clock on CLKUSR, it will not affect the configuration process. After all the configuration data is accepted and CONF_DONE goes high, CLKUSR is enabled after the time specified as tCD2CU. After this time period elapses, Arria II GX devices require a minimum number of clock cycles to initialize properly and enter user mode as specified in the t CD2UMC parameter. User Mode An optional INIT_DONE pin is available, which signals the end of initialization and the start of user-mode with a low-to-high transition. The Enable INIT_DONE Output option is available in the Quartus II software from the General tab of the Device and Pin Options dialog box. If you use the INIT_DONE pin, it is high due to an external 10-k pull-up resistor when nCONFIG is low and during the beginning of configuration. Once the option bit to enable INIT_DONE is programmed into the device (during the first frame of configuration data), the INIT_DONE pin goes low. When initialization is complete, the INIT_DONE pin is released and pulled high. When initialization is complete, the device enters user mode. In user-mode, the user I/O pins no longer have weak pull-up resistors and function as assigned in your design. Configuration Schemes The following sections describe configuration schemes for Arria II GX devices. MSEL Pin Settings Select the configuration scheme by driving the Arria II GX device MSEL pins either high or low, as shown in Table 9-2. The MSEL input buffers are powered by the VCCPD power supply. Altera recommends you hardwire the MSEL[] pins to VCCPD or GND. The MSEL[3..0] pins have 5-k internal pull-down resistors that are always active. During POR and during reconfiguration, the MSEL pins must be at LVTTL V IL and VIH levels to be considered logic low and logic high, respectively. 1 To avoid problems with detecting an incorrect configuration scheme, hardwire the MSEL[] pins to VCC PD or GND without pull-up or pull-down resistors. Do not drive the MSEL[] pins by a microprocessor or another device. Table 9-2. Arria II GX Configuration Schemes (Part 1 of 2) Configuration Scheme Fast passive parallel (FPP) FPP with design security feature and/or decompression enabled (2) Arria II GX Device Handbook Volume 1 MSEL3 MSEL2 MSEL2 MSEL0 POR Delay Configuration Voltage Standard (V) (1) 0 0 0 0 Fast 3.3, 3.0/2.5 0 1 1 1 Fast 1.8 0 0 0 1 Fast 3.3, 3.0/2.5 1 0 0 0 Fast 1.8 (c) February 2009 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Configuration Schemes 9-7 Table 9-2. Arria II GX Configuration Schemes (Part 2 of 2) Configuration Scheme Passive Serial (PS) Active Serial (AS) with or without remote system upgrade (3) JTAG-based configuration (4) MSEL3 MSEL2 MSEL2 MSEL0 POR Delay Configuration Voltage Standard (V) (1) 0 0 1 0 Fast 3.3, 3.0/2.5 1 0 0 1 Fast 1.8 1 0 1 0 Standard 3.3, 3.0/2.5 1 0 1 1 Standard 1.8 0 0 1 1 Fast 3.3 1 1 0 1 Fast 3.0/2.5 1 1 1 0 Standard 3.3 1 1 1 1 Standard 3.0/2.5 (5) (5) (5) (5) -- -- Notes to Table 9-2: (1) Configuration voltage standard applied to the VCCIO supply in which the configuration pins reside. (2) These modes are only supported when using a MAX II device or a microprocessor with flash memory for configuration. In these modes, the host system must output a DCLK that is x4 the data rate. (3) EPCS16, EPCS64, and EPCS128 support up to a 40 MHz DCLK and are supported in Arria II GX devices. Existing batches of EPCS4 manufactured on 0.15 m process geometry support up to a 40 MHz DCLK and are supported in Arria II GX devices. For information about product traceability and transition date to differentiate between the 0.15 m process geometry and the 0.18 m process geometry EPCS1 and EPCS4, refer to PCN 0514 Manufacturing Changes on EPCS Family process change notification on the Altera website at www.altera.com. (4) JTAG-based configuration takes precedence over other configuration schemes, which means MSEL pin settings are ignored. JTAG-based configuration does not support the design security or decompression features. (5) Do not leave MSEL pins floating. Connect them to VCCPD or GND. These pins support the non-JTAG configuration scheme used in production. If you only use the JTAG configuration, Altera recommends that you connect the MSEL pins to GND. Raw Binary File Size Table 9-3 shows the uncompressed raw binary file (.rbf) configuration file sizes for Arria II GX devices. Table 9-3. Arria II GX Uncompressed Raw Binary File (.rbf) Sizes (Note 1) Device Data Size (Mbits) Data Size (MBytes) EP2AGX20 -- -- EP2AGX30 -- -- EP2AGX45 -- -- EP2AGX65 -- -- EP2AGX95 -- -- EP2AGX125 -- -- EP2AGX190 -- -- EP2AGX260 -- -- Note to Table 9-3: (1) These values are not available until the Quartus II software can generate the finalized raw binary file (.rbf). (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 9-8 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Fast Passive Parallel Configuration Use the data in Table 9-3 to estimate the file size before design compilation. Different configuration file formats, such as a hexidecimal (.hex) or tabular text file (.ttf) format, have different file sizes. Refer to the Quartus II software for the different types of configuration file and file sizes. However, for any specific version of the Quartus II software, any design targeted for the same device will have the same uncompressed configuration file size. If you are using compression, the file size can vary after each compilation because the compression ratio is dependent on your design. f For more information about setting device configuration options or creating configuration files, refer to the Device Configuration Options and Configuration File Formats chapters in volume 2 of the Configuration Handbook. Fast Passive Parallel Configuration Fast passive parallel (FPP) configuration in Arria II GX devices is designed to meet the continuously increasing demand for faster configuration times. Arria II GX devices are designed with the capability of receiving byte-wide configuration data per clock cycle. You can perform FPP configuration of Arria II GX devices using an intelligent host such as a MAX II device or microprocessor. FPP Configuration Using an External Host FPP configuration using compression and an external host provides the fastest method to configure Arria II GX devices. In this configuration scheme, you can use a MAX II device or microprocessor as an intelligent host that controls the transfer of configuration data from a storage device, such as flash memory, to the target Arria II GX device. You can store configuration data in .rbf, .hex, or .ttf format. When using the MAX II device or microprocessor as an intelligent host, a design that controls the configuration process, such as fetching the data from flash memory and sending it to the device, must be stored in the MAX II device or microprocessor. 1 If you are using the Arria II GX decompression and/or design security features, the external host must be able to send a DCLK frequency that is x4 the data rate. The x4 DCLK signal does not require an additional pin and is sent on the DCLK pin. The maximum DCLK frequency is 125 MHz, which results in a maximum data rate of 250 Mbps. If you are not using the Arria II GX decompression or design security features, the data rate is x8 DCLK frequency. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Fast Passive Parallel Configuration 9-9 Figure 9-1 shows the configuration interface connections between the Arria II GX device and a MAX II device for single device configuration. Figure 9-1. Single Device FPP Configuration Using an External Host Memory ADDR DATA[7..0] VCCIO (1) 10 k VCCIO (1) 10 k Arria II GX Device MSEL[3..0] (3) CONF_DONE nSTATUS External Host (MAX II Device or Microprocessor) nCE GND nCEO N.C. (2) DATA[7..0] nCONFIG DCLK Notes to Figure 9-1: (1) Connect the resistor to a supply that provides an acceptable input signal for the Arria II GX device. VCCIO needs to be high enough to meet the V IH specification of the I/O on both the device and external host. Altera recommends that you power up the configuration system's I/Os with VCCIO for I/O bank 3C. (2) The nCEO pin can be left unconnected or used as a user I/O pin when it does not feed other device's nCE pin. (3) The MSEL pin settings vary for different configuration voltage standards and POR delay. To connect MSEL[3..0], refer to Table 9-2. 1 (c) February 2009 Arria II GX devices receive configuration data on the DATA[7..0] pins and the clock is received on the DCLK pin. Data is latched into the device on the rising edge of DCLK. If you are using the Arria II GX decompression and/or design security features, configuration data is latched on the rising edge of every fourth DCLK cycle. After the configuration data is latched in, it is processed during the following three DCLK cycles. Therefore, you can only stop DCLK after three clock cycles after the last data is latched into the Arria II GX Devices. Altera Corporation Arria II GX Device Handbook Volume 1 9-10 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Fast Passive Parallel Configuration Figure 9-2 shows how to configure multiple devices using a MAX II device. This circuit is similar to the FPP configuration circuit for a single device, except the Arria II GX devices are cascaded for multi-device configuration. Figure 9-2. Multi-Device FPP Configuration Using an External Host Memory ADDR DATA[7..0] VCCIO (1) 10 k VCCIO (1) 10 k MSEL[3..0] CONF_DONE nCE (2) Arria II GX Device 2 10 k MSEL[3..0] (2) CONF_DONE nSTATUS External Host (MAX II Device or Microprocessor) VCCIO (1) Arria II GX Device 1 nSTATUS nCEO nCE nCEO N.C. GND DATA[7..0] DATA[7..0] nCONFIG nCONFIG DCLK DCLK Notes to Figure 9-2: (1) Connect the pull-up resistor to a supply that provides an acceptable input signal for all Arria II GX devices in the chain. VCCIO needs to be high enough to meet the VIH specification of the I/O standard on the device and external host. Altera recommends you power up the configuration system's I/Os with VCCIO for I/O bank 3C. (2) The MSEL pin settings vary for different configuration voltage standards and POR delay. To connect MSEL[3..0], refer to Table 9-2. After the first device completes configuration in a multi-device configuration chain, its nCEO pin drives low to activate the second device's nCE pin, which prompts the second device to begin configuration. The second device in the chain begins configuration in one clock cycle; therefore, the transfer of data destinations is transparent to the MAX II device or microprocessor. All other configuration pins (nCONFIG, nSTATUS, DCLK, DATA[7..0], and CONF_DONE) are connected to every device in the chain. The configuration signals may require buffering to ensure signal integrity and prevent clock skew problems. Ensure that the DCLK and DATA lines are buffered for every fourth device. Because all device CONF_DONE pins are tied together, all devices initialize and enter user mode at the same time. All nSTATUS and CONF_DONE pins are tied together and if any device detects an error, configuration stops for the entire chain and you must reconfigure the entire chain. For example, if the first device flags an error on nSTATUS, it resets the chain by pulling its nSTATUS pin low. This behavior is similar to a single device detecting an error. If a system has multiple devices that contain the same configuration data, tie all device nCE inputs to GND and leave the nCEO pins floating. All other configuration pins (nCONFIG, nSTATUS, DCLK, DATA[7..0], and CONF_DONE) are connected to every device in the chain. Configuration signals may require buffering to ensure signal integrity and prevent clock skew problems. Ensure that the DCLK and DATA lines are buffered for every fourth device. Devices must be the same density and package. All devices start and complete configuration at the same time. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Fast Passive Parallel Configuration 9-11 Figure 9-3 shows a multi-device FPP configuration when both Arria II GX devices are receiving the same configuration data. Figure 9-3. Multiple-Device FPP Configuration Using an External Host When Both Devices Receive the Same Data Memory ADDR DATA[7..0] VCCIO (1) 10 k VCCIO (1) Arria II GX Device 1 10 k MSEL[3..0] Arria II GX Device 2 (2) MSEL[3..0] CONF_DONE nSTATUS nCE External Host (MAX II Device or Microprocessor) GND (2) CONF_DONE nCEO nSTATUS nCE N.C. nCEO N.C. GND DATA[7..0] DATA[7..0] nCONFIG nCONFIG DCLK DCLK Notes to Figure 9-3: (1) Connect the pull-up resistor to a supply that provides an acceptable input signal for all Arria II GX devices in the chain. VCCIO needs to be high enough to meet the VIH specification of the I/O standard on the device and external host. Altera recommends you power up all configuration system's I/Os with VCCIO for I/O banks 3C and 8C. (2) The MSEL pin settings vary for different configuration voltage standards and POR delay. To configure MSEL[3..0], refer to Table 9-2. You can use a single configuration chain to configure Arria II GX devices with other Altera devices that support FPP configuration. To ensure that all devices in the chain complete configuration at the same time, or that an error flagged by one device initiates reconfiguration in all devices, tie all device CONF_DONE and nSTATUS pins together. f (c) February 2009 For more information about configuring multiple Altera devices in the same configuration chain, refer to the Configuring Mixed Altera FPGA Chains chapter in volume 2 of the Configuration Handbook. Altera Corporation Arria II GX Device Handbook Volume 1 9-12 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Fast Passive Parallel Configuration FPP Configuration Timing Figure 9-4 shows the timing waveform for FPP configuration when using a MAX II device as an external host. This waveform shows timing when the decompression and design security features are not enabled. Figure 9-4. FPP Configuration Timing Waveform with Decompression and Design Security not Enabled (Note 1), (2) tCF2ST1 tCFG tCF2CK nCONFIG nSTATUS (3) tSTATUS tCF2ST0 t CLK CONF_DONE (4) tCF2CD tST2CK tCH tCL (5) DCLK tDH DATA[7..0] Byte 0 Byte 1 Byte 2 Byte 3 (6) Byte n-2 Byte n-1 User Mode Byte n tDSU High-Z User I/O User Mode INIT_DONE tCD2UM Notes to Figure 9-4: (1) Use this timing waveform when decompression and design security features are not used. (2) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic-high levels. When nCONFIG is pulled low, a reconfiguration cycle begins. (3) Upon power-up, the Arria II GX device holds nSTATUS low for the time of the POR delay. (4) Upon power-up, before and during configuration, CONF_DONE is low. (5) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient. (6) DATA[7..1] are available as user I/O pins after configuration. The state of these pins depends on the dual-purpose pin settings. DATA[0] is a dedicated pin that is used for both the passive and active configuration modes and is not available as a user I/O pin after configuration. Table 9-4 defines the timing parameters for Arria II GX devices for FPP configuration when the decompression and design security features are not enabled. Table 9-4. FPP Timing Parameters for Arria II GX Devices with Decompression and Design Security not Enabled (Note 1), (2) (Part 1 of 2) Symbol Parameter Minimum Maximum Units tCF2CD nCONFIG low to CONF_DONE low -- 800 ns tCF2ST0 nCONFIG low to nSTATUS low -- 800 ns tCFG nCONFIG low pulse width 2 -- s tSTATUS nSTATUS low pulse width 10 500 (3) s tCF2ST1 nCONFIG high to nSTATUS high -- 500 (3) s tCF2CK nCONFIG high to first rising edge on DCLK 500 -- s tST2CK nSTATUS high to first rising edge of DCLK 2 -- s tDSU Data setup time before rising edge on DCLK 4 -- ns tDH Data hold time after rising edge on DCLK 0 -- ns tCH DCLK high time 3.2 -- ns tCL DCLK low time 3.2 -- ns Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Fast Passive Parallel Configuration 9-13 Table 9-4. FPP Timing Parameters for Arria II GX Devices with Decompression and Design Security not Enabled (Note 1), (2) (Part 2 of 2) Symbol Parameter Minimum Maximum Units tCLK DCLK period 8 -- ns fMAX DCLK frequency -- 125 MHz tR Input rise time -- 40 ns t Input fall time -- 40 ns tCD2UM CONF_DONE high to user mode (4) 55 150 s tCD2CU CONF_DONE high to CLKUSR enabled 4 x maximum -- -- -- -- DCLK period tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (8532 x CLKUSR period) Notes to Table 9-4: (1) (2) (3) (4) This information is preliminary. Use these timing parameters when the decompression and design security features are not used. This value is obtainable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width. The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for starting up the device. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 9-14 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Fast Passive Parallel Configuration Figure 9-5 shows the timing waveform for FPP configuration when using a MAX II device or microprocessor as an external host. This waveform shows timing when the decompression and/or design security features are enabled. Figure 9-5. FPP Configuration Timing Waveform with Decompression or Design Security Enabled (Note 1), (2) tCF2ST1 tCFG tCF2CK nCONFIG nSTATUS (3) CONF_DONE (4) tSTATUS tCF2ST0 tCF2CD tCL tST2CK DCLK tCH 1 2 3 4 1 2 3 4 (7) 1 3 (5) 4 tCLK DATA[7..0] tDSU Byte 0 Byte 1 tDH tDH Byte (n-1) Byte 2 Byte n User Mode User Mode High-Z User I/O (6) INIT_DONE tCD2UM Notes to Figure 9-5: (1) Use this timing waveform when the decompression and/or design security features are used. (2) The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS, and CONF_DONE are at logic-high levels. When nCONFIG is pulled low, a reconfiguration cycle begins. (3) Upon power-up, the Arria II GX device holds nSTATUS low for the time of the POR delay. (4) Upon power-up, before and during configuration, CONF_DONE is low. (5) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient. (6) DATA[7..1] are available as user I/O pins after configuration. The state of these pins depends on the dual-purpose pin settings. DATA[0] is a dedicated pin that is used for both the passive and active configuration modes and is not available as a user I/O pin after configuration. (7) If needed, you can pause DCLK by holding it low. When DCLK restarts, the external host must provide data on the DATA[7..0] pins prior to sending the first DCLK rising edge. Table 9-5 defines the timing parameters for Arria II GX devices for FPP configuration when the decompression and/or the design security features are enabled. Table 9-5. FPP Timing Parameters for Arria II GX Devices with the Decompression or Design Security Features Enabled (Note 1), (2) (Part 1 of 2) Symbol Parameter Minimum Maximum Units tCF2CD nCONFIG low to CONF_DONE low -- 800 ns tCF2ST0 nCONFIG low to nSTATUS low -- 800 ns tCFG nCONFIG low pulse width 2 -- s tSTATUS nSTATUS low pulse width 10 500 (3) s tCF2ST1 nCONFIG high to nSTATUS high -- 500 (3) s tCF2CK nCONFIG high to first rising edge on DCLK 500 -- s tST2CK nSTATUS high to first rising edge of DCLK 2 -- s tDSU Data setup time before rising edge on DCLK 4 -- ns tDH Data hold time after rising edge on DCLK 24 -- ns tCH DCLK high time 3.2 -- ns Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Active Serial Configuration (Serial Configuration Devices) 9-15 Table 9-5. FPP Timing Parameters for Arria II GX Devices with the Decompression or Design Security Features Enabled (Note 1), (2) (Part 2 of 2) Symbol Parameter Minimum Maximum Units tCL DCLK low time 3.2 -- ns tCLK DCLK period 8 -- ns fMAX DCLK frequency -- 125 MHz tDATA Data rate -- 250 Mbps tR Input rise time -- 40 ns t Input fall time -- 40 ns tCD2UM CONF_DONE high to user mode (4) 55 150 s tCD2CU CONF_DONE high to CLKUSR enabled 4 x maximum DCLK period -- -- tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (8532 x CLKUSR period) -- -- Notes to Table 9-5: (1) (2) (3) (4) This information is preliminary. Use these timing parameters when the decompression and design security features are used. This value is obtainable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width. The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for starting up the device. f For more information about setting device configuration options or creating configuration files, refer to the Device Configuration Options and Configuration File Formats chapters in volume 2 of the Configuration Handbook. Active Serial Configuration (Serial Configuration Devices) In the Fast AS configuration scheme, Arria II GX devices are configured using a serial configuration device. These configuration devices are low-cost devices with non-volatile memory that feature a simple four-pin interface and a small form factor. These features make serial configuration devices an ideal low-cost configuration solution. f For more information about serial configuration devices, refer to the Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet chapter in volume 2 of the Configuration Handbook. Serial configuration devices provide a serial interface to access configuration data. During device configuration, Arria II GX devices read configuration data using the serial interface, decompress data if necessary, and configure their SRAM cells. This scheme is referred to as the AS configuration scheme because the Arria II GX device controls the configuration interface. This scheme contrasts with the PS configuration scheme, where the configuration device controls the interface. 1 (c) February 2009 The Arria II GX decompression and design security features are fully available when configuring your Arria II GX device using AS mode. Altera Corporation Arria II GX Device Handbook Volume 1 9-16 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Active Serial Configuration (Serial Configuration Devices) Serial configuration devices have a four-pin interface: serial clock input (DCLK), serial data output (DATA), AS data input (ASDI), and active-low chip select (nCS). This four-pin interface connects to the Arria II GX device pins, as shown in Figure 9-6. Figure 9-6. Single Device Fast AS Configuration VCCIO (1) VCCIO (1) 10 kW 10 kW VCCIO (1) 10 kW Serial Configuration Device Arria II GX FPGA nSTATUS CONF_DONE nCONFIG nCE nCEO N.C. GND DATA DATA0 DCLK DCLK nCS nCSO (3) ASDI ASDO (3) (2) CLKUSR MSEL [3..0] (5) (4) Notes to Figure 9-6: (1) Connect the pull-up resistors to the VCCIO supply of bank 3C. (2) Arria II GX devices use the ASDO-to-ASDI path to control the configuration device. (3) These are dual-purpose I/O pins. The FLASH_nCE pin functions as the nCSO pin in the AS configuration scheme. The DATA[1] pin functions as the ASDO pin in the AS configuration scheme. (4) The MSEL pin settings vary for different configuration voltage standards and POR delay. To configure MSEL[3..0], refer to Table 9-2. (5) Arria II GX devices have an option to select CLKUSR (40MHz maximum) as the external clock source for DCLK. The serial clock (DCLK) generated by the Arria II GX device controls the entire configuration cycle and provides timing for the serial interface. Arria II GX devices use an internal oscillator or an external clock source to generate DCLK. You can select to use a slow clock (20 MHz maximum) or a fast clock (40 MHz maximum) from the internal oscillator. Arria II GX devices have an option to select CLKUSR (40 MHz maximum) as the external clock source for DCLK. In AS configuration schemes, Arria II GX devices drive out control signals on the falling edge of DCLK. The serial configuration device responds to the instructions by driving out configuration data on the falling edge of DCLK. Then the data is latched into the Arria II GX device on the following falling edge of DCLK. In configuration mode, Arria II GX devices enable the serial configuration device by driving the nCSO output pin low, which connects to the chip select (nCS) pin of the configuration device. The Arria II GX device uses the serial clock (DCLK) and serial data output (ASDO) pins to send operation commands and/or read address signals to the serial configuration device. The configuration device provides data on its serial data output (DATA) pin, which connects to the DATA0 input of the Arria II GX devices. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Active Serial Configuration (Serial Configuration Devices) 9-17 You can configure multiple Arria II GX devices using a single serial configuration device. You can cascade multiple Arria II GX devices using the chip-enable (nCE) and chip-enable-out (nCEO) pins. The first device in the chain must have its nCE pin connected to GND. You must connect its nCEO pin to the nCE pin of the next device in the chain. When the first device captures all its configuration data from the bitstream, it drives the nCEO pin low, enabling the next device in the chain. You must leave the nCEO pin of the last device unconnected. The nCONFIG, nSTATUS, CONF_DONE, DCLK, and DATA0 pins of each device in the chain are connected (refer to Figure 9-7). The first Arria II GX device in the chain is the configuration master and controls configuration of the entire chain. You must connect its MSEL pins to select the AS configuration scheme. The remaining Arria II GX devices are configuration slaves. You must connect their MSEL pins to select the PS configuration scheme. Any other Altera device that supports PS configuration can also be part of the chain as a configuration slave. Figure 9-7 shows the pin connections for the multi-device AS configuration. Figure 9-7. Multi-Device AS Configuration VCCIO (1) VCCIO (1) 10 k 10 k VCCIO (1) 10 k Serial Configuration Device Arria II GX FPGA Master nSTATUS CONF_DONE nCONFIG nCE Arria II GX FPGA Slave nSTATUS CONF_DONE nCONFIG nCEO N.C. VCCIO (1) GND 10 k DATA DATA[0] DCLK DCLK nCS nCSO ASDI ASDO nCEO CLKUSR MSEL [3..0] (4) (2) nCE DATA[0] DCLK MSEL [3..0] (2) Buffers (3) Notes to Figure 9-7: (1) Connect the pull-up resistors to the VCCIO supply of the I/O bank 3C. (2) The MSEL pin settings vary for different configuration voltage standards and POR delay. To connect MSEL[3..0], refer to Table 9-2. (3) Connect the repeater buffers between the Arria II GX master and slave devices for DATA[0] and DCLK. This is to prevent any potential signal integrity and clock skew problems. (4) Arria II GX devices have an option to select CLKUSR (40MHz maximum) as the external clock source for DCLK. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 9-18 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Active Serial Configuration (Serial Configuration Devices) As shown in Figure 9-7, the nSTATUS and CONF_DONE pins on all target devices are connected together with external pull-up resistors. These pins are open-drain bidirectional pins on the devices. When the first device asserts nCEO (after receiving all its configuration data), it releases its CONF_DONE pin. But the subsequent devices in the chain keep this shared CONF_DONE line low until they have received their configuration data. When all target devices in the chain have received their configuration data and have released CONF_DONE, the pull-up resistor drives a high level on this line and all devices simultaneously enter initialization mode. 1 While you can cascade Arria II GX devices, you cannot cascade or chain together serial configuration devices. If the configuration bitstream size exceeds the capacity of a serial configuration device, you must select a larger configuration device and/or enable the compression feature. When configuring multiple devices, the size of the bitstream is the sum of the individual devices' configuration bitstreams. A system may have multiple devices that contain the same configuration data. In active serial chains, you can implement this by storing one copy of the SRAM object file (.sof) in the serial configuration device. The same copy of the .sof file configures the master Arria II GX device and all remaining slave devices concurrently. All Arria II GX devices must be the same density and package. To configure four identical Arria II GX devices with the same .sof file, you can set up the chain similar to the example shown in Figure 9-8. The first device is the master device and its MSEL pins need to be set to select AS configuration. The other three slave devices are set up for concurrent configuration and their MSEL pins need to be set to select PS configuration. The nCE input pins from the master and slave are connected to GND, and the DATA and DCLK pins connect in parallel to all four devices. During the configuration cycle, the master device reads its configuration data from the serial configuration device and transmits the configuration data to all three slave devices, configuring all of them simultaneously. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Active Serial Configuration (Serial Configuration Devices) 9-19 Figure 9-8 shows the multi-device AS configuration when the devices receive the same data using a single .sof file. Figure 9-8. Multi-Device AS Configuration When the Devices Receive the Same Data Using a Single .sof File Arria II GX FPGA Slave nSTATUS CONF_DONE nCONFIG nCE VCCIO (1) VCCIO (1) 10 k nCEO N.C. VCCIO (1) 10 k 10 k DATA[0] MSEL[3..0] DCLK Arria II GX FPGA Master Serial Configuration Device nSTATUS CONF_DONE nCONFIG nCE nCEO (2) Arria II GX FPGA Slave nSTATUS CONF_DONE nCONFIG nCE N.C. nCEO N.C. GND GND DATA DATA0 DCLK DCLK nCS nCSO ASDI ASDO DATA[0] CLKUSR MSEL[3..0] (4) DCLK (2) MSEL[3..0] (2) Arria II GX FPGA Slave nSTATUS CONF_DONE nCONFIG nCE Buffers (3) nCEO N.C. DATA[0] DCLK MSEL[3..0] (2) Notes to Figure 9-8: (1) Connect the pull-up resistors to the VCCIO supply of I/O bank 3C. (2) The MSEL pin settings vary for different configuration voltage standards and POR delay. To connect MSEL[3..0], refer to Table 9-2. (3) Connect the repeater buffers between the Arria II GX master and slave devices for DATA[0] and DCLK. This is to prevent any potential signal integrity and clock skew problems. (4) Arria II GX devices have an option to select CLKUSR (40MHz maximum) as the external clock source for DCLK. Estimating Active Serial Configuration Time Active serial configuration time is dominated by the time it takes to transfer data from the serial configuration device to the Arria II GX device. This serial interface is clocked by the Arria II GX DCLK output (generated from an internal oscillator or an option to select CLKUSR as external clock source). Arria II GX devices support DCLK up to 40 MHz (25 ns). Therefore, the minimum configuration time can be estimated as the following: RBF Size x (minimum DCLK period / 1 bit per DCLK cycle) = estimated minimum configuration time (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 9-20 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Active Serial Configuration (Serial Configuration Devices) Enabling compression reduces the amount of configuration data that is transmitted to the Arria II GX device, which also reduces configuration time. On average, compression reduces configuration time, depending on your design. Programming Serial Configuration Devices Serial configuration devices are non-volatile, flash-memory-based devices. You can program these devices in-system using an USB-BlasterTM, EthernetBlaster, or ByteBlasterTM II download cable. Alternatively, you can program them using the Altera programming unit (APU), supported third-party programmers, or a microprocessor with the SRunner software driver. You can perform in-system programming of serial configuration devices using the conventional AS programming interface or JTAG interface solution. Because serial configuration devices do not support the JTAG interface, the conventional method to program them is using the AS programming interface. The configuration data used to program serial configuration devices is downloaded using programming hardware. During in-system programming, the download cable disables device access to the AS interface by driving the nCE pin high. Arria II GX devices are also held in reset mode by a low level on nCONFIG. After programming is complete, the download cable releases nCE and nCONFIG, allowing the pull-down and pull-up resistors to drive GND and VCCIO, respectively. Altera has developed Serial FlashLoader (SFL); an in-system programming solution for serial configuration devices using the JTAG interface. This solution requires the Arria II GX device to be a bridge between the JTAG interface and the serial configuration device. f For more information about SFL, refer to AN 370: Using the Serial FlashLoader with Quartus II Software. f For more information about the USB-Blaster download cable, refer to the USB-Blaster Download Cable User Guide. For more information about the ByteBlaster II cable, refer to the ByteBlaster II Download Cable User Guide. For more information about the EthernetBlaster download cable, refer to the EthernetBlaster Communications Cable User Guide. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Active Serial Configuration (Serial Configuration Devices) 9-21 Figure 9-9 shows the download cable connections to the serial configuration device. Figure 9-9. In-System Programming of Serial Configuration Devices VCCIO (1) 10 k VCCIO (1) 10 k VCCIO (1) 10 k Arria II GX FPGA CONF_DONE nSTATUS Serial Configuration Device nCEO N.C. nCONFIG nCE 10 k DATA DATA0 DCLK DCLK nCS nCSO CLKUSR (4) ASDI ASDO MSEL[3..0] (3) Pin 1 3.3 V (2) USB-Blaster or ByteBlaser II (AS Mode) 10-Pin Male Header Notes to Figure 9-9: (1) Connect the pull-up resistors to the VCCIO supply of the I/O bank 3C. (2) Power up the USB-ByteBlaster, ByteBlaster II, or EthernetBlaster cable's VCC (TRGT) with 3.3 V. (3) The MSEL pin settings vary for different configuration voltage standards and POR delay. To connect MSEL[3..0], refer to Table 9-2. (4) Arria II GX devices have an option to select CLKUSR (40 MHz maximum) as the external clock source for DCLK. You can program serial configuration devices with the Quartus II software using the Altera programming hardware and the appropriate configuration device programming adapter. In production environments, you can program serial configuration devices using multiple methods. You can use Altera programming hardware or other third-party programming hardware to program blank serial configuration devices before they are mounted onto PCBs. Alternatively, you can use an on-board microprocessor to program the serial configuration device in-system using C-based software drivers provided by Altera. You can program a serial configuration device in-system by an external microprocessor using SRunner. SRunner is a software driver developed for embedded serial configuration device programming, which can be easily customized to fit in different embedded systems. SRunner is able to read a raw programming data (.rpd) file and write to serial configuration devices. The serial configuration device programming time using SRunner is comparable to the programming time with the Quartus II software. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 9-22 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Passive Serial Configuration f For more information about SRunner, refer to AN 418: SRunner: An Embedded Solution for EPCS Programming and the source code on the Altera website at www.altera.com. f For more information about programming serial configuration devices, refer to the Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet chapter in volume 2 of the Configuration Handbook. Passive Serial Configuration You can program PS configuration of Arria II GX devices using an intelligent host, such as a MAX II device or microprocessor with flash memory, or a download cable. In the PS scheme, an external host (a MAX II device, embedded processor, or host PC) controls configuration. Configuration data is clocked into the target Arria II GX device using the DATA0 pin at each rising edge of DCLK. 1 The Arria II GX decompression and design security features are fully available when configuring your Arria II GX device using PS mode. PS Configuration Using an External Host In this configuration scheme, you can use a MAX II device as an intelligent host that controls the transfer of configuration data from a storage device, such as flash memory, to the target Arria II GX device. You can store configuration data in .rbf, .hex, or .ttf format. Figure 9-10 shows the configuration interface connections between an Arria II GX device and a MAX II device for single device configuration. Figure 9-10. Single Device PS Configuration Using an External Host Memory ADDR VCCIO(1) VCCIO (1) DATA[0] 10 k 10 k Arria II GX Device MSEL[3..0] (3) CONF_DONE nSTATUS External Host (MAX II Device or Microprocessor) nCE nCEO GND N.C. (2) DATA[0] nCONFIG DCLK Note to Figure 9-10: (1) Connect the resistor to a supply that provides an acceptable input signal for the Arria II GX device. VCCIO needs to be high enough to meet the VIH specification of the I/O on the device and the external host. Altera recommends that you power up the configuration system's I/Os with VCCIO for I/O bank 3C. (2) The nCEO pin can be left unconnected or used as a user I/O pin when it does not feed other device's nCE pin. (3) The MSEL pin settings vary for different configuration voltage standards and POR delays. To connect MSEL[3..0], refer to Table 9-2. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Passive Serial Configuration 9-23 The Arria II GX device receives configuration data on the DATA0 pin and the clock is received on the DCLK pin. Data is latched into the device on the rising edge of DCLK. If you are using configuration data in .rbf, .hex, or .ttf format, you must send the LSB of each data byte first. For example, if the .rbf file contains the byte sequence 02 1B EE 01 FA, the serial bitstream you should transmit to the device is 0100-0000 1101-1000 0111-0111 1000-0000 0101-1111. Figure 9-11 shows how to configure multiple devices using an external host. This circuit is similar to the PS configuration circuit for a single device, except Arria II GX devices are cascaded for multi-device configuration. Figure 9-11. Multi-Device PS Configuration Using an External Host Memory VCCIO (1) ADDR VCCIO (1) DATA[0] 10 k 10 k Arria II GX Device 1 MSEL[3..0] nSTATUS External Host (MAX II Device or Microprocessor) nCEO Arria II GX Device 2 MSEL[3..0] 10 k CONF_DONE nCE VCCIO (1) (2) (2) CONF_DONE nSTATUS nCE nCEO N.C. GND DATA[0] DATA[0] nCONFIG nCONFIG DCLK DCLK Notes to Figure 9-11: (1) Connect the pull-up resistor to a supply that provides an acceptable input signal for all Arria II GX devices in the chain. VCCIO needs to be high enough to meet the VIH specification of the I/O standard on the device and the external host. Altera recommends you power up the configuration system's I/Os with VCCIO for I/O bank 3C. (2) The MSEL pin settings vary for different configuration voltage standards and POR delay. To connect MSEL[3..0], refer to Table 9-2. After the first device completes configuration in a multi-device configuration chain, its nCEO pin drives low to activate the second device's nCE pin, which prompts the second device to begin configuration. The second device in the chain begins configuration in one clock cycle. Therefore, the transfer of data destinations is transparent to the MAX II device or microprocessor. All other configuration pins (nCONFIG, nSTATUS, DCLK, DATA0, and CONF_DONE) are connected to every device in the chain. Configuration signals can require buffering to ensure signal integrity and prevent clock skew problems. Ensure that the DCLK and DATA lines are buffered for every fourth device. Because all device CONF_DONE pins are tied together, all devices initialize and enter user mode at the same time. Because all nSTATUS and CONF_DONE pins are tied together, if any device detects an error, configuration stops for the entire chain and you must reconfigure the entire chain. For example, if the first device flags an error on nSTATUS, it resets the chain by pulling its nSTATUS pin low. This behavior is similar to a single device detecting an error. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 9-24 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Passive Serial Configuration In your system, you can have multiple devices that contain the same configuration data. To support this configuration scheme, all device nCE inputs are tied to GND, while nCEO pins are left floating. All other configuration pins (nCONFIG, nSTATUS, DCLK, DATA0, and CONF_DONE) are connected to every device in the chain. Configuration signals can require buffering to ensure signal integrity and prevent clock skew problems. Ensure that the DCLK and DATA lines are buffered for every fourth device. Devices must be the same density and package. All devices will start and complete configuration at the same time. Figure 9-12 shows multi-device PS configuration when both Arria II GX devices are receiving the same configuration data. Figure 9-12. Multiple-Device PS Configuration When Both Devices Receive the Same Data Memory ADDR VCCIO (1) VCCIO (1) DATA[0] 10 k 10 k Arria II GX Device MSEL[3..0] External Host (MAX II Device or Microprocessor) Arria II GX Device MSEL[3..0] (2) CONF_DONE CONF_DONE nSTATUS nSTATUS nCE nCE GND nCEO N.C. nCEO (2) N.C. GND DATA[0] DATA[0] nCONFIG nCONFIG DCLK DCLK Notes to Figure 9-12: (1) Connect the pull-up resistor to a supply that provides an acceptable input signal for all Arria II GX devices in the chain. VCCIO needs to be high enough to meet the VIH specification of the I/O standard on the device and the external host. Altera recommends you power up all configuration systems I/Os with VCCIO for I/O bank 3C and 8C. (2) The MSEL pin settings vary for different configuration voltage standards and POR delays. To connect MSEL[3..0], refer to Table 9-2. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Passive Serial Configuration 9-25 PS Configuration Timing Figure 9-13 shows the timing waveform for PS configuration when using a MAX II device or microprocessor as an external host. Figure 9-13. PS Configuration Timing Waveform (Note 1) tCF2ST1 tCFG tCF2CK nCONFIG nSTATUS (2) tSTATUS tCF2ST0 t CLK CONF_DONE (3) tCF2CD tST2CK tCH tCL (4) DCLK tDH Bit 0 Bit 1 Bit 2 Bit 3 DATA (5) Bit n tDSU High-Z User I/O User Mode INIT_DONE tCD2UM Notes to Figure 9-13: (1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins. (2) Upon power-up, the Arria II GX device holds nSTATUS low for the time of the POR delay. (3) Upon power-up, before and during configuration, CONF_DONE is low. (4) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient. (5) DATA[0] is available as a user I/O pin after configuration. The state of this pin depends on the dual-purpose pin settings. Table 9-6 defines the timing parameters for Arria II GX devices for PS configuration. Table 9-6. PS Timing Parameters for Arria II GX Devices (Note 1) (Part 1 of 2) Symbol Parameter Minimum Maximum Units tCF2CD nCONFIG low to CONF_DONE low -- 800 ns tCF2ST0 nCONFIG low to nSTATUS low -- 800 (2) ns tCFG nCONFIG low pulse width 2 -- s tSTATUS nSTATUS low pulse width 10 500 (2) s tCF2ST1 nCONFIG high to nSTATUS high -- 500 s tCF2CK nCONFIG high to first rising edge on DCLK 500 -- s tST2CK nSTATUS high to first rising edge of DCLK 2 -- s tDSU Data setup time before rising edge on DCLK 4 -- ns tDH Data hold time after rising edge on DCLK 0 -- ns tCH DCLK high time 3.2 -- ns tCL DCLK low time 3.2 -- ns tCLK DCLK period 8 -- ns fMAX DCLK frequency -- 125 MHz tR Input rise time -- 40 ns (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 9-26 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Passive Serial Configuration Table 9-6. PS Timing Parameters for Arria II GX Devices (Note 1) (Part 2 of 2) Symbol Parameter Minimum Maximum Units t Input fall time -- 40 ns tCD2UM CONF_DONE high to user mode (3) 55 150 s tCD2CU CONF_DONE high to CLKUSR enabled 4 x maximum DCLK period -- -- tCD2UMC CONF_DONE high to user mode with CLKUSR option on t CD2CU + (8532 CLKUSR period) -- -- Notes to Table 9-6: (1) This information is preliminary. (2) This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width. (3) The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for starting the device. f For more information about device configuration options and how to create configuration files, refer to the Device Configuration Options and Configuration File Formats chapters in volume 2 of the Configuration Handbook. PS Configuration Using a Download Cable 1 In this section, the generic term "download cable" includes the Altera USB-Blaster universal serial bus (USB) port download cable, ByteBlaster II parallel port download cable, ByteBlasterMVTM parallel port download cable, and EthernetBlaster download cable. In a PS configuration with a download cable, an intelligent host (such as a PC) transfers data from a storage device to the Arria II GX device using the download cable. During configuration, the programming hardware or download cable places the configuration data one bit at a time on the device's DATA0 pin. The configuration data is clocked into the target device until CONF_DONE goes high. When using a download cable, setting the Auto-restart configuration after error option does not affect the configuration cycle because you must manually restart the configuration in the Quartus II software when an error occurs. Additionally, the Enable user-supplied start-up clock (CLKUSR) option has no affect on the device initialization because this option is disabled in the .sof file when programming the device using the Quartus II programmer and download cable. Therefore, if you turn on the CLKUSR option, you do not need to provide a clock on CLKUSR when you are configuring the device with the Quartus II programmer and a download cable. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Passive Serial Configuration 9-27 Figure 9-14 shows PS configuration for Arria II GX devices using a USB-Blaster, ByteBlaster II, ByteBlasterMV, or Ethernet Blaster cable. Figure 9-14. PS Configuration Using a USB-Blaster, EthernetBlaster, MasterBlaster, ByteBlaster II, or ByteBlasterMV Cable VCCIO (1) VCCIO (1) 10 k (2) VCCIO (1) 10 k 10 k Arria II GX Device VCCIO (1) 10 k CONF_DONE nSTATUS VCCIO (1) 10 k (2) (4) MSEL[3..0] nCE GND DCLK DATA0 nCONFIG nCEO N.C. Download Cable 10-Pin Male Header (PS Mode) Pin 1 VCCIO (1) GND VIO (3) Shield GND Notes to Figure 9-14: (1) Connect the pull-up resistor to the same supply voltage (VCCIO) as the USB-Blaster, ByteBlaster II, ByteBlasterMV, or EthernetBlaster cable. (2) You only need the pull-up resistors on DATA0 and DCLK if the download cable is the only configuration scheme used on your board. This ensures that DATA0 and DCLK are not left floating after configuration. For example, if you are also using a configuration device, you do not need the pull-up resistors on DATA0 and DCLK. (3) In the ByteBlasterMV cable, pin 6 is a no connect. In the USB-Blaster and ByteBlaster II cables, this pin is connected to nCE when it is used for active serial programming; otherwise, it is a no connect. (4) The MSEL pin settings vary for different configuration voltage standards and POR delays. To connect MSEL[3..0], refer to Table 9-2. You can use a download cable to configure multiple Arria II GX devices by connecting each device's nCEO pin to the subsequent device's nCE pin. The first device's nCE pin is connected to GND while its nCEO pin is connected to the nCE of the next device in the chain. The last device's nCE input comes from the previous device, while its nCEO pin is left floating. All other configuration pins (nCONFIG, nSTATUS, DCLK, DATA0, and CONF_DONE) are connected to every device in the chain. Because all CONF_DONE pins are tied together, all devices in the chain initialize and enter user mode at the same time. In addition, because the nSTATUS pins are tied together, the entire chain halts configuration if any device detects an error. The Auto-restart configuration after error option does not affect the configuration cycle because you must manually restart configuration in the Quartus II software when an error occurs. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 9-28 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices JTAG Configuration Figure 9-15 shows how to configure multiple Arria II GX devices with a download cable. Figure 9-15. Multi-Device PS Configuration Using a USB-Blaster, ByteBlaster II, ByteBlasterMV, or EthernetBlaster Cable VCCIO (1) 10 k 10 k (2) (4) nCE 10 k GND 10 k CONF_DONE nSTATUS DCLK MSEL[3..0] VCCIO (1) VCCIO (1) 10 k Arria II GX Device 1 VCCIO (1) Download Cable 10-Pin Male Header (PS Mode) VCCIO (1) (2) Pin 1 VCCIO (1) GND VIO (3) nCEO DATA0 nCONFIG GND Arria II GX Device 2 CONF_DONE MSEL[3..0] nSTATUS DCLK VCCIO (1) (4) 10 k nCEO N.C. nCE DATA0 nCONFIG Notes to Figure 9-15: (1) Connect the pull-up resistor to the same supply voltage (VCCIO) as the USB-Blaster, ByteBlaster II, ByteBlasterMV, or EthernetBlaster cable. (2) You only need the pull-up resistors on DATA0 and DCLK if the download cable is the only configuration scheme used on your board. This ensures that DATA0 and DCLK are not left floating after configuration. For example, if you are also using a configuration device, you do not need the pull-up resistors on DATA0 and DCLK. (3) In the ByteBlasterMV cable, pin 6 is a no connect. In the USB-Blaster and ByteBlaster II cables, this pin is connected to nCE when it is used for active serial programming; otherwise, it is a no connect. (4) The MSEL pin settings vary for different configuration voltage standards and POR delays. To connect MSEL[3..0], refer to Table 9-2. f For more information about how to use the USB-Blaster, ByteBlaster II, ByteBlasterMV, or EthernetBlaster cables, refer to the following user guides: USB-Blaster Download Cable User Guide ByteBlaster II Download Cable User Guide ByteBlasterMV Download Cable User Guide Ethernet Blaster Communications Cable User Guide JTAG Configuration The JTAG has developed a specification for boundary-scan testing. This boundary-scan test (BST) architecture offers the capability to efficiently test components on PCBs with tight lead spacing. The BST architecture can test pin connections without using physical test probes and capture functional data while a device is operating normally. You can also use JTAG circuitry to shift configuration data into the device. The Quartus II software automatically generates .sof files that you can use for JTAG configuration with a download cable in the Quartus II software programmer. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices JTAG Configuration f 9-29 For more information about JTAG boundary-scan testing and commands available using Arria II GX devices, refer to the following documents: JTAG Boundary Scan Testing chapter in volume 1 of the Arria II GX Device Handbook Programming Support for Jam STAPL Language Arria II GX devices are designed such that JTAG instructions have precedence over any device configuration modes. Therefore, JTAG configuration can take place without waiting for other configuration modes to complete. For example, if you attempt JTAG configuration of Arria II GX devices during PS configuration, PS configuration is terminated and JTAG configuration begins. 1 You cannot use the Arria II GX decompression or design security features if you are configuring your Arria II GX device using JTAG-based configuration. 1 A device operating in JTAG mode uses four required pins, TDI, TDO, TMS, and TCK. The TCK pin has an internal weak pull-down resistor, while the TDI and TMS pins have weak internal pull-up resistors (typically 25 k ). All JTAG input pins are powered by the VCCIO supply of I/O bank 8C. The TDO pin is powered up by the VCCIO and VCCPD power supply of I/O bank 8C. All the JTAG pins support only the LVTTL I/O standard. All user I/O pins are tri-stated during JTAG configuration. Table 9-7 explains each JTAG pin's function. f For recommendations about how to connect a JTAG chain with multiple voltages across the devices in the chain, refer to the JTAG Boundary Scan Testing chapter in volume 1 of the Arria II GX Device Handbook. Table 9-7. Dedicated JTAG Pins Pin Name Pin Type Description TDI Test data input Serial input pin for instructions as well as test and programming data. Data is shifted in on the rising edge of TCK. If the JTAG interface is not required on the board, you can disable the JTAG circuitry by connecting this pin to logic high. TDO Test data output Serial data output pin for instructions as well as test and programming data. Data is shifted out on the falling edge of TCK. The pin is tri-stated if data is not being shifted out of the device. If the JTAG interface is not required on the board, you can disable the JTAG circuitry by leaving this pin unconnected. TMS Test mode select Input pin that provides the control signal to determine the transitions of the TAP controller state machine. TMS is evaluated on the rising edge of TCK. Therefore, you must set up TMS before the rising edge of TCK. Transitions in the state machine occur on the falling edge of TCK after the signal is applied to TMS. If the JTAG interface is not required on the board, you can disable the JTAG circuitry by connecting this pin to logic high. TCK Test clock input Clock input to the BST circuitry. Some operations occur at the rising edge while others occur at the falling edge. If the JTAG interface is not required on the board, you can disable the JTAG circuitry by connecting this pin to GND. During JTAG configuration, you can download data to the device on the PCB through the USB-Blaster, ByteBlaster II, ByteBlasterMV, or EthernetBlaster download cable. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 9-30 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices JTAG Configuration Figure 9-16 shows the JTAG configuration of a single Arria II GX device. Figure 9-16. JTAG Configuration of a Single Device Using a Download Cable VCCIO (2) 10 k VCCIO (1) VCCIO (2) 10 k VCCIO (1) Arria II GX Device 10 k nCE (5) GND N.C. (3) (3) (3) nCE0 nSTATUS CONF_DONE nCONFIG MSEL[3..0] DCLK 10 kW TCK TDO TMS TDI Download Cable 10-Pin Male Header (JTAG Mode) (Top View) Pin 1 VCCIO (2) GND VIO (4) 1 k GND GND Notes to Figure 9-16: (1) Connect the pull-up resistors to the VCCIO supply of I/O bank 3C. (2) Connect the pull-up resistor to the same supply voltage as the USB-Blaster, ByteBlaster II, ByteBlasterMV, or EthernetBlaster cable. The voltage supply can be connected to the VCCIO supply of I/O bank 8C of the device. (3) Connect the nCONFIG and MSEL[3..0] pins to support a non-JTAG configuration scheme. If you only use the JTAG configuration, connect nCONFIG to VCCIO, and MSEL[3..0] to GND. Pull DCLK either high or low, whichever is convenient on your board. (4) In the USB-Blaster, ByteBlaster II, and ByteBlasterMV cables, this pin is a no connect. (5) You must connect nCE to GND or drive it low for successful JTAG configuration. To configure a single device in a JTAG chain, the programming software places all other devices in bypass mode. In bypass mode, devices pass programming data from the TDI pin to the TDO pin through a single bypass register without being affected internally. This scheme enables the programming software to program or verify the target device. Configuration data driven into the device appears on the TDO pin one clock cycle later. The Quartus II software verifies successful JTAG configuration upon completion. At the end of configuration, the software checks the state of CONF_DONE through the JTAG port. When the Quartus II software generates a JamTM file (.jam) for a multi-device chain, it contains instructions so that all the devices in the chain are initialized at the same time. If CONF_DONE is not high, the Quartus II software indicates that configuration has failed. If CONF_DONE is high, the software indicates that configuration was successful. After the configuration bitstream is transmitted serially using the JTAG TDI port, the TCK port is clocked an additional 1,094 cycles to perform device initialization. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices JTAG Configuration 9-31 Arria II GX devices have dedicated JTAG pins that always function as JTAG pins. Not only can you perform JTAG testing on Arria II GX devices before and after, but also during configuration. While other device families do not support JTAG testing during configuration, Arria II GX devices support the bypass, ID code, and sample instructions during configuration without interrupting configuration. All other JTAG instructions may only be issued by first interrupting configuration and reprogramming I/O pins using the CONFIG_IO instruction. The CONFIG_IO instruction allows I/O buffers to be configured using the JTAG port and when issued, interrupts configuration. This instruction allows you to perform board-level testing prior to configuring the Arria II GX device or waiting for a configuration device to complete configuration. Once configuration is interrupted and JTAG testing is complete, you must reconfigure the part using JTAG (PULSE_CONFIG instruction) or by pulsing nCONFIG low. The chip-wide reset (DEV_CLRn) and chip-wide output enable (DEV_OE) pins on Arria II GX devices do not affect JTAG boundary-scan or programming operations. Toggling these pins does not affect JTAG operations (other than the usual boundary-scan operation). When designing a board for JTAG configuration of Arria II GX devices, consider the dedicated configuration pins. Table 9-8 shows how these pins must be connected during JTAG configuration. Table 9-8. Dedicated Configuration Pin Connections During JTAG Configuration Signal (c) February 2009 Description nCE On all Arria II GX devices in the chain, nCE must be driven low by connecting it to ground, pulling it low using a resistor, or driving it by some control circuitry. For devices that are also in multi-device FPP, AS, or PS configuration chains, the nCE pins must be connected to GND during JTAG configuration, or JTAG must be configured in the same order as the configuration chain. nCEO On all Arria II GX devices in the chain, you can leave nCEO floating or connected to nCE of the next device. MSEL These pins must not be left floating. These pins support whichever non-JTAG configuration is used in production. If you only use JTAG configuration, tie these pins to GND. nCONFIG Driven high by connecting to the VCCIO supply of the bank in which the pin resides, pulling up using a resistor, or driven high by some control circuitry. nSTATUS Pull to the VCCIO supply of the bank in which the pin resides using a 10-k resistor. When configuring multiple devices in the same JTAG chain, each nSTATUS pin must be pulled up to VC CIO individually. CONF_DONE Pull to the VCCIO supply of the bank in which the pin resides using a 10-k resistor. When configuring multiple devices in the same JTAG chain, each CONF_DONE pin must be pulled up to the VCCIO supply of the bank in which the pin resides individually. CONF_DONE going high at the end of JTAG configuration indicates successful configuration. DCLK Do not leave floating. Drive low or high, whichever is more convenient on your board. Altera Corporation Arria II GX Device Handbook Volume 1 9-32 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices JTAG Configuration When programming a JTAG device chain, one JTAG-compatible header is connected to several devices. The number of devices in the JTAG chain is limited only by the drive capability of the download cable. When four or more devices are connected in a JTAG chain, Altera recommends buffering the TCK, TDI, and TMS pins with an on-board buffer. JTAG-chain device programming is ideal when the system contains multiple devices or when testing your system using JTAG BST circuitry. Figure 9-17 shows a multi-device JTAG configuration. Figure 9-17. JTAG Configuration of Multiple Devices Using a Download Cable Arria II GX Device Download Cable 10-Pin Male Header (JTAG Mode) VCCIO (1) (5) Pin 1 10 k VCCIO (2) VCCIO (2) 10 k (5) (5) 10 k nSTATUS nCONFIG 10 k (5) nSTATUS nCONFIG CONF_DONE CONF_DONE (5) DCLK (5) DCLK MSEL[3..0] (5) MSEL[3..0] (5) MSEL[3..0] TDI TMS (3) VCCIO (1) DCLK nCE (4) VIO VCCIO (1) 10 k 10 k nSTATUS nCONFIG CONF_DONE (5) VCCIO (1) VCCIO (1) 10 k 10 k VCCIO (2) Stratix II or Stratix II GX Arria Device II GX Device Arria II GX Device VCCIO (1) nCE (4) TDO TCK TDI TMS nCE (4) TDO TCK TDI TMS TDO TCK 1 k Notes to Figure 9-17: (1) Connect the pull-up resistors to the VCCIO supply of I/O bank 3C. (2) You must connect the pull-up resistor to the same supply voltage as the USB-Blaster, ByteBlaster II, ByteBlasterMV, or EthernetBlaster cable. You can connect the voltage supply to the VCCIO supply of I/O bank 8C of the device. (3) In the USB-Blaster, ByteBlaster II, and ByteBlasterMV cables, pin 6 is a no connect. (4) You must connect nCE to GND or drive it low for successful JTAG configuration. (5) You must connect the nCONFIG and MSEL[3..0] pins to support a non-JTAG configuration scheme. If you only use JTAG configuration, connect nCONFIG to the VCCIO supply of the bank in which the pin resides and MSEL[3..0] to GND. Pull DCLK either high or low, whichever is convenient on your board. You must connect the nCE pin to GND or drive it low during JTAG configuration. In multi-device FPP, AS, and PS configuration chains, the first device's nCE pin is connected to GND while its nCEO pin is connected to nCE of the next device in the chain. The last device's nCE input comes from the previous device, while its nCEO pin is left floating. In addition, the CONF_DONE and nSTATUS signals are all shared in multi-device FPP, AS, or PS configuration chains so the devices can enter user mode at the same time after configuration is complete. When the CONF_DONE and nSTATUS signals are shared among all the devices, you must configure every device when JTAG configuration is performed. 1 If you only use JTAG configuration, Altera recommends that you connect the circuitry as shown in Figure 9-17, where each of the CONF_DONE and nSTATUS signals are isolated to enable each device to enter user mode individually. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices JTAG Configuration 9-33 After the first device completes configuration in a multi-device configuration chain, its nCEO pin drives low to activate the second device's nCE pin, which prompts the second device to begin configuration. Therefore, if these devices are also in a JTAG chain, make sure the nCE pins are connected to GND during JTAG configuration or that the devices are JTAG configured in the same order as the configuration chain. As long as the devices are JTAG configured in the same order as the multi-device configuration chain, the nCEO of the previous device drives the nCE of the next device low when it has successfully been JTAG configured. You can place other Altera devices that have JTAG support in the same JTAG chain for device programming and configuration. 1 f JTAG configuration support is enhanced and allows more than 17 Arria II GX devices to be cascaded in a JTAG chain. For more information about configuring multiple Altera devices in the same configuration chain, refer to the Configuring Mixed Altera Device Chains chapter in volume 2 of the Configuration Handbook. You can configure Arria II GX devices using multiple configuration schemes on the same board. Combining JTAG configuration with passive serial or active serial configuration on your board is useful in the prototyping environment because it allows multiple methods to configure your FPGA. f For more information about combining JTAG configuration with other configuration schemes, refer to the Combining Different Configuration Schemes chapter in volume 2 of the Configuration Handbook. Figure 9-18 shows a JTAG configuration of an Arria II GX device using a microprocessor. Figure 9-18. JTAG Configuration of a Single Device Using a Microprocessor VCCIO (1) VCCIO (1) Memory ADDR Arria II GX Device 10 k 10 k DATA nSTATUS CONF_DONE Microprocessor TDI (4) TCK (4) TMS (4) TDO (4) DCLK nCONFIG MSEL[3..0] nCEO (2) (2) (2) N.C. (3) nCE GND Notes to Figure 9-18: (1) Connect the pull-up resistor to a supply that provides an acceptable input signal for all Arria II GX devices in the chain. The VCCIO supply of the bank in which the pin resides needs to be high enough to meet the VIH specification of the I/O on the device. (2) Connect the nCONFIG and MSEL[3..0] pins to support a non-JTAG configuration scheme. If you use only the JTAG configuration, connect nCONFIG to the VCCIO supply of the bank in which the pin resides and MSEL[3..0] to GND. Pull DCLK either high or low, whichever is convenient on your board. (3) You must connect nCE to GND or drive it low for successful JTAG configuration. (4) The microprocessor needs to use the same I/O standard as V CCIO to drive the JTAG pins. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 9-34 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Device Configuration Pins Jam STAPL Jam STAPL, JEDEC standard JESD-71, is a standard file format for in-system programmability (ISP) purposes. Jam STAPL supports programming or configuration of programmable devices and testing of electronic systems, using the IEEE 1149.1 JTAG interface. It is a freely licensed open standard. The Jam Player provides an interface for manipulating the IEEE Std. 1149.1 JTAG TAP state machine. f For more information about JTAG and Jam STAPL in embedded environments, refer to the AN 425: Using Command-Line Jam STAPL Solution for Device Programming. To download the jam player, visit the Altera website at www.altera.com. Device Configuration Pins The following tables describe the connections and functionality of all the configuration-related pins on the Arria II GX devices. Table 9-9 summarizes the Arria II GX configuration pins and their power supply. Table 9-9. Arria II GX Configuration Pin Summary Description Input/Output Dedicated Powered By Configuration Mode TDI Input Yes VCCIO JTAG TMS Input Yes VCCIO JTAG TCK Input Yes VCCIO JTAG TDO Output Yes VCCIO and VCCPD (2) JTAG CRC_ERROR Output -- Pull-up Optional, all modes DATA0 Input -- VCCIO All modes except JTAG DATA[7..1] Input -- VCCIO FPP INIT_DONE Output -- Pull-up Optional, all modes CLKUSR Input -- VCCIO Optional nSTATUS Bidirectional Yes Pull-up All modes nCE Input Yes VCCIO All modes CONF_DONE Bidirectional Yes Pull-up All modes nCONFIG Input Yes VCCIO All modes ASDO Output Yes VCCIO AS nCSO Output Yes VCCIO AS DCLK Input Yes VCCIO PS, FPP Output Yes VCCIO AS nIO_PULLUP Input Yes VCC (1) All modes nCEO Output Yes Pull-up All modes MSEL[3..0] Input Yes VC CPD All modes Notes to Table 9-9: (1) Although the nIO_PULLUP is powered up by V CC, Altera recommends you connect these pins to VCCIO or GND directly without using a pullup or pull-down resistor. (2) The TDO pin is powered up by the VCCIO and VCCPD power supply of I/O bank 8C. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Device Configuration Pins 9-35 Table 9-10 describes the dedicated configuration pins. You must connect these pins properly on your board for successful configuration. Some of these pins may not be required for your configuration schemes. Table 9-10. Dedicated Configuration Pins on the Arria II GX Device (Part 1 of 4) Pin Name VCCPD User Mode Configuratio n Scheme Pin Type N/A All Power Description Dedicated power pin. Use this pin to power the I/O pre-drivers, the JTAG output pin (TDO), and the MSEL[3..0]. You must connect VC CP D according to the I/O standard used in the same bank: For 3.3-V I/O standards, connect VC CP D to 3.3 V For 3.0-V I/O standards, connect VC CP D to 3.0 V For 2.5-V and below I/O standards, connect VCC PD to 2.5 V VCCPD must ramp-up from 0 V to 2.5 V, 3.0 V, or 3.3 V in 100 ms for standard POR or 4 ms for fast POR. If VCCPD is not ramped up in this specified time, your Arria II GX device will not configure successfully. If your system does not allow for a VCCPD to ramp-up time in 100 ms or 4 ms, you must hold nCONFIG low until all power supplies are stable. nIO_PULLUP N/A All Input Dedicated input that chooses whether the internal pull-up resistors on the user I/O pins and dual-purpose I/O pins (nCSO, nASDO, DATA[7..0], CLKUSR, INIT_DONE) are on or off before and during configuration. A logic high turns off the weak internal pull-up resistors, while a logic low turns them on. The nIO-PULLUP input buffer is powered by VCC and has an internal 5-k pull-down resistor that is always active. You can tie the nIO-PULLUP directly to the VCCIO supply of the bank in which the pin resides or GND. MSEL[3..0] N/A All Input Four-bit configuration input that sets the Arria II GX device configuration scheme. Refer to Table 9-2 on page 9-6 for the appropriate connections. You must hardwire these pins to the VC CP D or GND. The MSEL[3..0] pins have internal 5-k pull-down resistors that are always active. nCONFIG N/A All Input Configuration control input. Pulling this pin low during user-mode causes the device to lose its configuration data, enter a reset state, and tri-state all I/O pins. Returning this pin to a logic-high level starts a reconfiguration. Configuration is possible only if this pin is high, except in JTAG programming mode, when nCONFIG is ignored. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 9-36 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Device Configuration Pins Table 9-10. Dedicated Configuration Pins on the Arria II GX Device (Part 2 of 4) Pin Name nSTATUS User Mode Configuratio n Scheme N/A All Pin Type Description Bidirectional open-drain The device drives nSTATUS low immediately after power-up and releases it after the POR time. During user mode and regular configuration, this pin is pulled high by an external 10-k resistor. This pin, when driven low by the Arria II GX device, indicates that the device has encountered an error during configuration. Status output. If an error occurs during configuration, nSTATUS is pulled low by the target device. Status input. If an external source drives the nSTATUS pin low during configuration or initialization, the target device enters an error state. Driving nSTATUS low after configuration and initialization does not affect the configured device. If you use a configuration device, driving nSTATUS low causes the configuration device to attempt to configure the device, but because the device ignores transitions on nSTATUS in user mode, the device does not reconfigure. To begin a reconfiguration, nCONFIG must be pulled low. If the VCCIO supply of the bank in which the nSTATUS pin resides is not fully powered up, the following could occur: CONF_DONE N/A All Bidirectional open-drain VCCIO is powered high enough for the nSTATUS buffer to function properly and nSTATUS is driven low. When VCCIO is ramped up, POR trips and nSTATUS is released after POR expires. VCCIO is not powered high enough for the nSTATUS buffer to function properly. In this situation, nSTATUS might appear logic high, triggering a configuration attempt that would fail because POR did not yet trip. When VCCPD is powered up, nSTATUS is pulled low because POR did not yet trip. When POR trips after VCCIO is powered up, nSTATUS is released and pulled high. At that point, reconfiguration is triggered and the device is configured. Status output. The target device drives the CONF_DONE pin low before and during configuration. Once all configuration data is received without error and the initialization cycle starts, the target device releases CONF_DONE. Status input. After all data is received and CONF_DONE goes high, the target device initializes and enters user mode. The CONF_DONE pin must have an external 10-k pull-up resistor for the device to initialize. Driving CONF_DONE low after configuration and initialization does not affect the configured device. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Device Configuration Pins 9-37 Table 9-10. Dedicated Configuration Pins on the Arria II GX Device (Part 3 of 4) Pin Name nCE User Mode Configuratio n Scheme Pin Type Description N/A All Input Active-low chip enable. The nCE pin activates the device with a low signal to allow configuration. The nCE pin must be held low during configuration, initialization, and user mode. In single device configuration, it must be tied low. In multidevice configuration, nCE of the first device is tied low while its nCEO pin is connected to nCE of the next device in the chain. The nCE pin must also be held low for successful JTAG programming of the device. nCEO I/O All Output Output that drives low when device configuration is complete. In single-device configuration, this pin is left floating. In multi-device configuration, this pin feeds the next device's nCE pin. The nCEO of the last device in the chain is left floating. The nCEO pin is powered by the VCCIO supply of the bank in which the nCEO pin resides. After configuration, nCEO is available as user I/O pins. The state of the nCEO pin depends on the Dual-Purpose Pin settings. ASDO N/A AS Output Control signal from the Arria II GX device to the serial configuration device in AS mode used to read out configuration data. In AS mode, ASDO has an internal pull-up resistor that is always active. nCSO N/A AS Output Output control signal from the Arria II GX device to the serial configuration device in AS mode that enables the configuration device. In AS mode, nCSO has an internal pull-up resistor that is always active. DCLK N/A Synchronous configuration schemes (PS, FPP, AS) Input (PS, FPP) Output (AS) In PS and FPP configuration, DCLK is the clock input used to clock data from an external source into the target device. Data is latched into the device on the rising edge of DCLK. In AS mode, DCLK is an output from the Arria II GX device that provides timing for the configuration interface. In AS mode, DCLK has an internal pull-up resistor (typically 25 k) that is always active. After configuration, this pin is tri-stated. In schemes that use a configuration device, DCLK is driven low after configuration is done. In schemes that use a control host, DCLK must be driven either high or low, whichever is more convenient. Toggling this pin after configuration does not affect the configured device. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 9-38 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Device Configuration Pins Table 9-10. Dedicated Configuration Pins on the Arria II GX Device (Part 4 of 4) Pin Name DATA0 User Mode Configuratio n Scheme Pin Type N/A PS, FPP, AS Input Description Data input. In serial configuration modes, bit-wide configuration data is presented to the target device on the DATA0 pin. In AS mode, DATA0 has an internal pull-up resistor that is always active. The DATA[0] is a dedicated pin that is used for both passive and active configuration modes and it is not available as a user I/O pin after configuration. DATA[7..1] I/O Parallel configuration schemes (FPP) Inputs Data inputs. Byte-wide configuration data is presented to the target device on DATA[7..0]. In serial configuration schemes, they function as user I/O pins during configuration, which means they are tri-stated. After FPP configuration, DATA[7..1] are available as user I/O pins and the state of these pin depends on the DualPurpose Pin settings. Table 9-11 describes the optional configuration pins. If these optional configuration pins are not enabled in the Quartus II software, they are available as general-purpose user I/O pins. Therefore, during configuration, these pins function as user I/O pins and are tri-stated with weak pull-up resistors. Table 9-11. Optional Configuration Pins (Part 1 of 2) Pin Name User Mode Pin Type Description CLKUSR N/A if option is on. I/O if option is off. Input Optional user-supplied clock input synchronizes the initialization of one or more devices. Enable this pin by turning on the Enable user-supplied start-up clock (CLKUSR) option in the Quartus II software. INIT_DONE N/A if option is on. I/O if option is off. Output open-drain Use as Status pin to indicate when the device has initialized and is in user mode. When nCONFIG is low and during the beginning of configuration, the INIT_DONE pin is tri-stated and pulled high due to an external 10-k pull-up resistor. Once the option bit to enable INIT_DONE is programmed into the device (during the first frame of configuration data), the INIT_DONE pin goes low. When initialization is complete, the INIT_DONE pin is released and pulled high and the device enters user mode. Thus, the monitoring circuitry must be able to detect a low-to-high transition. This pin is enabled by turning on the Enable INIT_DONE output option in the Quartus II software. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Device Configuration Pins 9-39 Table 9-11. Optional Configuration Pins (Part 2 of 2) Pin Name User Mode Pin Type Description DEV_OE N/A if option is on. I/O if option is off. Input Optional pin that allows you to override all tri-states on the device. When this pin is driven low, all I/O pins are tri-stated. When this pin is driven high, all I/O pins behave as programmed. Enable this pin by turning on the Enable device-wide output enable (DEV_OE) option in the Quartus II software. DEV_CLRn N/A if option is on. I/O if option is off. Input Optional pin that allows you to override all clears on all device registers. When this pin is driven low, all registers are cleared. When this pin is driven high, all registers behave as programmed. This pin is enabled by turning on the Enable device-wide reset (DEV_CLRn) option in the Quartus II software. Table 9-12 describes the dedicated JTAG pins. JTAG pins must be kept stable before and during configuration to prevent accidental loading of JTAG instructions. TDI and TMS have weak internal pull-up resistors while TCK has a weak internal pull-down resistor (typically 25 k ). If you plan to use the SignalTap(R) embedded logic array analyzer, you must connect the JTAG pins of the Arria II GX device to a JTAG header on your board. Table 9-12. Dedicated JTAG Pins Pin Name TDI User Mode Pin Type Description N/A Input Serial input pin for instructions as well as test and programming data. Data is shifted on the rising edge of TCK. The TDI pin is powered by the VCCIO supply of I/O bank 8C. If the JTAG interface is not required on the board, you can disable the JTAG circuitry by connecting this pin to logic high. TDO N/A Output Serial data output pin for instructions as well as test and programming data. Data is shifted out on the falling edge of TCK. The pin is tri-stated if data is not being shifted out of the device. The TDO pin is powered up by the VCCIO and VCCPD power supply of I/O bank 8C. For recommendations about connecting a JTAG chain with multiple voltages across the devices in the chain, refer to the JTAG Boundary Scan Testing chapter in volume 1 of the Arria II GX Device Handbook. If the JTAG interface is not required on the board, you can disable the JTAG circuitry by leaving this pin unconnected. TMS N/A Input Input pin that provides the control signal to determine the transitions of the TAP controller state machine. TMS is evaluated on the rising edge of TCK. Therefore, you must set up TMS before the rising edge of TCK. Transitions in the state machine occur on the falling edge of TCK after the signal is applied to TMS. The TMS pin is powered by the VCCIO supply of I/O bank 8C. If the JTAG interface is not required on the board, you can disable the JTAG circuitry by connecting this pin to logic high. TCK N/A Input The clock input to the BST circuitry. Some operations occur at the rising edge, while others occur at the falling edge. The TCK pin is powered by the VCCIO supply of I/O bank 8C. It is expected that the clock input waveform have a nominal 50% duty cycle. If the JTAG interface is not required on the board, you can disable the JTAG circuitry by connecting TCK to GND. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 9-40 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Configuration Data Decompression Configuration Data Decompression Arria II GX devices support configuration data decompression, which saves configuration memory space and time. This feature allows you to store compressed configuration data in configuration or other memory devices and transmit this compressed bitstream to Arria II GX devices. During configuration, the Arria II GX device decompresses the bitstream in real time and programs its SRAM cells. 1 Preliminary data indicates that compression typically reduces the configuration bitstream size by 35 to 55% based on the designs used. Arria II GX devices support decompression in the FPP (when using a MAX II device or microprocessor + flash), AS, and PS configuration schemes. The Arria II GX decompression feature is not available in the JTAG configuration scheme. 1 When using FPP mode, the intelligent host must provide a DCLK that is x4 the data rate. Therefore, the configuration data must be valid for four DCLK cycles. In PS mode, use the Arria II GX decompression feature, because sending compressed configuration data reduces configuration time. When you enable compression, the Quartus II software generates configuration files with compressed configuration data. This compressed file reduces the storage requirements in the configuration device or flash memory, and decreases the time needed to transmit the bitstream to the Arria II GX device. The time required by a Arria II GX device to decompress a configuration file is less than the time needed to transmit the configuration data to the device. There are two ways to enable compression for Arria II GX bitstreams: before design compilation (in the Compiler Settings menu) and after design compilation (in the Convert Programming Files window). To enable compression in the project's Compiler Settings menu, perform the following steps: 1. On the Assignments menu, click Device to bring up the Settings dialog box. 2. After selecting your Arria II GX device, open the Device and Pin Options window. 3. In the Configuration settings tab, enable the check box for Generate compressed bitstreams (as shown in Figure 9-19). Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Configuration Data Decompression 9-41 Figure 9-19. Enabling Compression for Arria II GX Bitstreams in Compiler Settings You can also enable compression when creating programming files from the Convert Programming Files window. To do this, perform the following steps: 1. On the File menu, click Convert Programming Files. 2. Select the programming file type (.pof, .sram, .hex, .rbf, or .ttf). 3. For POF output files, select a configuration device. 4. In the Input files to convert box, select SOF Data. 5. Select Add File and add a Arria II GX device .sof files. 6. Select the name of the file you added to the SOF Data area and click Properties. 7. Check the Compression check box. When multiple Arria II GX devices are cascaded, you can selectively enable the compression feature for each device in the chain if you are using a serial configuration scheme. Figure 9-20 depicts a chain of two Arria II GX devices. The first Arria II GX device has compression enabled and therefore receives a compressed bitstream from the configuration device. The second Arria II GX device has the compression feature disabled and receives uncompressed data. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 9-42 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Remote System Upgrades In a multi-device FPP configuration chain (with a MAX II device or microprocessor + flash), all Arria II GX devices in the chain must either enable or disable the decompression feature. You cannot selectively enable the compression feature for each device in the chain because of the DATA and DCLK relationship. Figure 9-20. Compressed and Uncompressed Serial Configuration Data in the Same Configuration File Serial Configuration Data Serial Configuration Device Uncompressed Configuration Data Compressed Configuration Data Decompression Controller Arria II GX FPGA Arria II GX FPGA nCE nCEO nCE nCEO N.C. GND You can generate programming files for this setup by clicking Convert Programming Files on the File menu in the Quartus II software. Remote System Upgrades This section describes the functionality and implementation of the dedicated remote system upgrade circuitry. It also defines several concepts related to remote system upgrades, including factory configuration, application configuration, remote update mode, and user watchdog timer. Additionally, this section provides design guidelines for implementing remote system upgrades with the supported configuration schemes. System designers sometimes face challenges such as shortened design cycles, evolving standards, and system deployments in remote locations. Arria II GX devices help overcome these challenges with their inherent reprogrammability and dedicated circuitry to perform remote system upgrades. Remote system upgrades help deliver feature enhancements and bug fixes without costly recalls, reduce time-to-market, extend product life, and help to avoid system downtime. Arria II GX devices feature dedicated remote system upgrade circuitry. Soft logic (either the Nios(R) II embedded processor or user logic) implemented in an Arria II GX device can download a new configuration image from a remote location, store it in configuration memory, and direct the dedicated remote system upgrade circuitry to start a reconfiguration cycle. The dedicated circuitry performs error detection during and after the configuration process, recovers from any error condition by reverting back to a safe configuration image, and provides error status information. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Remote System Upgrades 9-43 Remote system upgrades are supported in fast active serial (AS) Arria II GX configuration schemes. You can also implement remote system upgrades in conjunction with advanced Arria II GX features such as real-time decompression of configuration data and design security using the advanced encryption standard (AES) for secure and efficient field upgrades. The largest serial configuration device currently supports 128 MBits of configuration bitstream. Functional Description The dedicated remote system upgrade circuitry in Arria II GX devices manages remote configuration and provides error detection, recovery, and status information. User logic or a Nios II processor implemented in the Arria II GX device logic array provides access to the remote configuration data source and an interface to the system's configuration memory. Arria II GX devices have remote system upgrade processes that involve the following steps: 1. A Nios II processor (or user logic) implemented in the Arria II GX device logic array receives new configuration data from a remote location. The connection to the remote source uses a communication protocol such as transmission control protocol/Internet protocol (TCP/IP), peripheral component interconnect (PCI), user datagram protocol (UDP), universal asynchronous receiver/transmitter (UART), or a proprietary interface. 2. The Nios II processor (or user logic) stores this new configuration data in non-volatile configuration memory. 3. The Nios II processor (or user logic) starts a reconfiguration cycle with the new or updated configuration data. 4. The dedicated remote system upgrade circuitry detects and recovers from any errors that might occur during or after the reconfiguration cycle and provides error status information to the user design. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 9-44 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Remote System Upgrades Figure 9-21 shows the steps required for performing remote configuration updates. (The numbers in Figure 9-21 coincide with the steps just mentioned.) Figure 9-21. Functional Diagram of Arria II GX Remote System Upgrade 1 2 Development Location Data Arria II GX Device Control Module Data Configuration Memory Data Arria II GX Configuration 3 1 Arria II GX devices only support remote system upgrade in the single device AS configuration scheme. Figure 9-22 shows a block diagram for implementing a remote system upgrade with the Arria II GX AS configuration scheme. Figure 9-22. Remote System Upgrade Block Diagram for Arria II GX AS Configuration Scheme Arria II GX Device Nios II Processor or User Logic Serial Configuration Device You must set the mode select pins (MSEL[3..0]) to AS mode to use the remote system upgrade in your system. 1 The MSEL pin settings vary for different configuration voltage standards and POR delays. To connect MSEL[3..0], refer to Table 9-2 on page 9-6. 1 When using fast AS mode, you must select remote update mode in the Quartus II software and insert the ALTREMOTE_UPDATE megafunction to access the circuitry. For more information, refer to "ALTREMOTE_UPDATE Megafunction" on page 9-54. Enabling Remote Update You can enable remote update for Arria II GX devices in the Quartus II software before design compilation (in the Compiler Settings menu). In remote update mode, the auto-restart configuration after error option is always enabled. To enable remote update in the project's compiler settings, perform the following steps in the Quartus II software: 1. On the Assignment menu, click Device. The Settings dialog box appears. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Remote System Upgrades 9-45 2. Click Device and Pin Options. The Device and Pin Options dialog box appears. 3. Click the Configuration tab. 4. From the Configuration scheme list, select Active Serial (you can also use Configuration Device) (Figure 9-23). 5. From the Configuration Mode list, select Remote (Figure 9-23). 6. Click OK. 7. In the Settings dialog box, click OK. Figure 9-23. Enabling Remote Update for Arria II GX Devices in the Compiler Settings Menu Configuration Image Types When performing a remote system upgrade, Arria II GX device configuration bitstreams are classified as factory configuration images or application configuration images. An image, also referred to as a configuration, is a design loaded into the Arria II GX device that performs certain user-defined functions. Each Arria II GX device in your system requires one factory image or the addition of one or more application images. The factory image is a user-defined fall-back, or safe configuration, and is responsible for administering remote updates in conjunction with the dedicated circuitry. Application images implement user-defined functionality in the target Arria II GX device. You may include the default application image functionality in the factory image. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 9-46 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Remote System Upgrade Mode A remote system upgrade involves storing a new application configuration image or updating an existing one using the remote communication interface. After an application configuration image is stored or updated remotely, the user design in the Arria II GX device starts a reconfiguration cycle with the new image. Any errors during or after this cycle are detected by the dedicated remote system upgrade circuitry and cause the device to automatically revert to the factory image. The factory image then performs error processing and recovery. The factory configuration is written to the serial configuration device only once by the system manufacturer and should not be remotely updated. On the other hand, application configurations may be remotely updated in the system. Both images can begin system reconfiguration. Remote System Upgrade Mode Remote system upgrade has only one mode of operation: remote update mode. Remote update mode allows you to determine the functionality of your system upon power-up and offers different features. Overview In remote update mode, Arria II GX devices load the factory configuration image upon power up. The user-defined factory configuration determines which application configuration is to be loaded and triggers a reconfiguration cycle. The factory configuration may also contain application logic. When used with serial configuration devices, remote update mode allows an application configuration to start at any flash sector boundary. For example, this translates to a maximum of 256 pages in the EPCS128 device and 64 pages in the EPCS32 device, where the minimum size of each page is 512 KBits. Altera does not recommend using the same page in the serial configuration device for two images. Additionally, remote update mode features a user watchdog timer that determines the validity of an application configuration. Remote Update Mode When an Arria II GX device is first powered up in remote update mode, it loads the factory configuration located at page zero (page registers PGM[23:0] = 24'b0). Always store the factory configuration image for your system at page address zero. This corresponds to the start address location 0x000000 in the serial configuration device. The factory image is user-designed and contains soft logic to: Process any errors based on status information from the dedicated remote system upgrade circuitry Communicate with the remote host and receive new application configurations and store this new configuration data in the local non-volatile memory device Determine which application configuration is to be loaded into the Arria II GX device Enable or disable the user watchdog timer and load its time-out value (optional) Instruct the dedicated remote system upgrade circuitry to start a reconfiguration cycle Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Remote System Upgrade Mode 9-47 Figure 9-24 shows the transitions between the factory and application configurations in remote update mode. Figure 9-24. Transitions between Configurations in Remote Update Mode Configuration Error Configuration Error Application 1 Configuration Set Control Register and Reconfigure Power Up Factory Configuration (page 0) Reload a Different Application Reload a Different Application Set Control Register and Reconfigure Application n Configuration Configuration Error After power up or a configuration error, the factory configuration logic is loaded automatically. The factory configuration also needs to specify whether to enable the user watchdog timer for the application configuration and if enabled, to include the timer setting information as well. The user watchdog timer ensures that the application configuration is valid and functional. The timer must be continually reset in a specific amount of time during user mode operation of an application configuration. Only valid application configurations contain the logic to reset the timer in user mode. This timer reset logic needs to be part of a user-designed hardware and/or software health monitoring signal that indicates error-free system operation. If the timer is not reset in a specific amount of time; for example, the user application configuration detects a functional problem or if the system hangs, the dedicated circuitry updates the remote system upgrade status register, triggering the loading of the factory configuration. 1 The user watchdog timer is automatically disabled for factory configurations. For more information about the user watchdog timer, refer to "User Watchdog Timer" on page 9-52. If there is an error while loading the application configuration, the cause of the reconfiguration is written by the dedicated circuitry to the remote system upgrade status register. Actions that cause the remote system upgrade status register to be written are: (c) February 2009 nSTATUS driven low externally Internal CRC error Altera Corporation Arria II GX Device Handbook Volume 1 9-48 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Dedicated Remote System Upgrade Circuitry User watchdog timer time-out A configuration reset (logic array nCONFIG signal or external nCONFIG pin assertion to low) Arria II GX devices automatically load the factory configuration located at page address zero. This user-designed factory configuration can read the remote system upgrade status register to determine the reason for the reconfiguration. The factory configuration then takes appropriate error recovery steps and writes to the remote system upgrade control register to determine the next application configuration to be loaded. When Arria II GX devices successfully load the application configuration, they enter into user mode. In user mode, the soft logic (Nios II processor or state machine and the remote communication interface) assists the Arria II GX device in determining when a remote system update is arriving. When a remote system update arrives, the soft logic receives the incoming data, writes it to the configuration memory device, and triggers the device to load the factory configuration. The factory configuration reads the remote system upgrade status register and control register, determines the valid application configuration to load, writes the remote system upgrade control register accordingly, and initiates system reconfiguration. Dedicated Remote System Upgrade Circuitry This section describes the implementation of the Arria II GX dedicated remote system upgrade circuitry. The remote system upgrade circuitry is implemented in hard logic. This dedicated circuitry interfaces with the user-defined factory and application configurations implemented in the Arria II GX device logic array to provide the complete remote configuration solution. The remote system upgrade circuitry contains the remote system upgrade registers, a watchdog timer, and a state machine that controls those components. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Dedicated Remote System Upgrade Circuitry 9-49 Figure 9-25 shows the remote system upgrade block's data path. Figure 9-25. Remote System Upgrade Circuit Data Path (Note 1) Internal Oscillator Status Register (SR) [4..0] Control Register [37..0] Logic Array Update Register [37..0] update Shift Register dout Bit [4..0] din dout capture RSU State Machine din Bit [37..0] capture time-out User Watchdog Timer clkout capture update Logic Array clkin RU_DOUT RU_SHIFTnLD RU_CAPTnUPDT RU_CLK RU_DIN RU_nCONFIG RU_nRSTIMER Logic Array Note to Figure 9-25: (1) The RU_DOUT, RU_SHIFTnLD, RU_CAPTnUPDT, RU_CLK, RU_DIN, RU_nCONFIG, and RU_nRSTIMER signals are internally controlled by the ALTREMOTE_UPDATE megafunction. Remote System Upgrade Registers The remote system upgrade block contains a series of registers that store the page addresses, watchdog timer settings, and status information. These registers are detailed in Table 9-13. Table 9-13. Remote System Upgrade Registers (Part 1 of 2) Register Description Shift register This register is accessible by the logic array and allows the update, status, and control registers to be written and sampled by user logic. Control register This register contains the current page address, user watchdog timer settings, and one bit specifying whether the current configuration is a factory configuration or an application configuration. During a read operation in an application configuration, this register is read into the shift register. When a reconfiguration cycle is initiated, the contents of the update register are written into the control register. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 9-50 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Dedicated Remote System Upgrade Circuitry Table 9-13. Remote System Upgrade Registers (Part 2 of 2) Register Description Update register This register contains data similar to that in the control register. However, it can only be updated by the factory configuration by shifting data into the shift register and issuing an update operation. When a reconfiguration cycle is triggered by the factory configuration, the control register is updated with the contents of the update register. During a capture in a factory configuration, this register is read into the shift register. Status register This register is written to by the remote system upgrade circuitry on every reconfiguration to record the cause of the reconfiguration. This information is used by the factory configuration to determine the appropriate action following a reconfiguration. During a capture cycle, this register is read into the shift register. The remote system upgrade control and status registers are clocked by the 10-MHz internal oscillator (the same oscillator that controls the user watchdog timer). However, the remote system upgrade shift and update registers are clocked by the user clock input (RU_CLK). Remote System Upgrade Control Register The remote system upgrade control register stores the application configuration page address and user watchdog timer settings. The control register functionality depends on the remote system upgrade mode selection. In remote update mode, the control register page address bits are set to all zeros (24'b0 = 0x000000) at power up to load the factory configuration. A factory configuration in remote update mode has write access to this register. The control register bit positions are shown in Figure 9-26 and defined in Table 9-14. In the figure, the numbers show the bit position of a setting in a register. For example, bit number 25 is the enable bit for the watchdog timer. Figure 9-26. Remote System Upgrade Control Register 37 36 35 34 33 32 31 30 29 28 27 26 Wd_timer[11..0] 25 Wd_en 24 23 22 .. 3 2 1 PGM[23..0] 0 AnF The application-not-factory (AnF) bit indicates whether the current configuration loaded in the Arria II GX device is the factory configuration or an application configuration. This bit is set low by the remote system upgrade circuitry when an error condition causes a fall-back to the factory configuration. When the AnF bit is high, the control register access is limited to read operations. When the AnF bit is low, the register allows write operations and disables the watchdog timer. In remote update mode, the factory configuration design sets this bit high (1'b1) when updating the contents of the update register with the application page address and watchdog timer settings. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Dedicated Remote System Upgrade Circuitry 9-51 Table 9-14 shows the remote system upgrade control register contents. Table 9-14. Remote System Upgrade Control Register Contents Remote System Upgrade Mode Value (2) AnF (1) Remote update 1'b0 PGM[23..0] Remote update 24'b0x000000 AS configuration start address (StAdd[23..0]) Wd_en Remote update 1'b0 User watchdog timer enable bit Wd_timer[11..0] Remote update 12'b000000000000 Control Register Bit Definition Application not factory User watchdog time-out value (most significant 12 bits of 29-bit count value: {Wd_timer[11..0], 17'b0}) Notes to Table 9-14: (1) In remote update mode, the remote configuration block does not update the AnF bit automatically (you can update it manually). (2) This is the default value of the control register bit. Remote System Upgrade Status Register The remote system upgrade status register specifies the reconfiguration trigger condition. The various trigger and error conditions include: Cyclical redundancy check (CRC) error during application configuration nSTATUS assertion by an external device due to an error Arria II GX device logic array triggered a reconfiguration cycle, possibly after downloading a new application configuration image External configuration reset (nCONFIG) assertion User watchdog timer time-out Figure 9-27 specifies the contents of the status register. The numbers in the figure show the bit positions in a 5-bit register. Figure 9-27. Remote System Upgrade Status Register 4 Wd 3 2 1 nCONFIG Core_nCONFIG nSTATUS 0 CRC Table 9-15 lists the status register contents for remote system upgrade. Table 9-15. Remote System Upgrade Status Register Contents (Part 1 of 2) (c) February 2009 Status Register Bit Definition POR Reset Value CRC (from configuration) CRC error caused reconfiguration 1 bit '0' nSTATUS nSTATUS caused reconfiguration 1 bit '0' CORE_nCONFIG (1) Device logic array caused reconfiguration 1 bit '0' nCONFIG nCONFIG caused reconfiguration 1 bit '0' Altera Corporation Arria II GX Device Handbook Volume 1 9-52 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Dedicated Remote System Upgrade Circuitry Table 9-15. Remote System Upgrade Status Register Contents (Part 2 of 2) Status Register Bit Definition POR Reset Value Wd Watchdog timer caused reconfiguration 1 bit '0' Note to Table 9-15: (1) Logic array reconfiguration forces the system to load the application configuration data into the Arria II GX device. This occurs after the factory configuration specifies the appropriate application configuration page address by updating the update register. Remote System Upgrade State Machine The remote system upgrade control and update registers have identical bit definitions, but serve different roles (refer to Figure 9-26 on page 9-50). While both registers can only be updated when the device is loaded with a factory configuration image, the update register writes are controlled by the user logic; the control register writes are controlled by the remote system upgrade state machine. In factory configurations, the user logic sends the AnF bit (set high), page address, and watchdog timer settings for the next application configuration bit to the update register. When the logic array configuration reset (RU_nCONFIG) goes low, the remote system upgrade state machine updates the control register with the contents of the update register and starts system reconfiguration from the new application page. If there is an error or reconfiguration trigger condition, the remote system upgrade state machine directs the system to load a factory or application configuration (page zero or page one, based on the mode and error condition) by setting the control register accordingly. Table 9-16 lists the contents of the control register after such an event occurs for all possible error or trigger conditions. The remote system upgrade status register is updated by the dedicated error monitoring circuitry after an error condition but before the factory configuration is loaded. Table 9-16. Control Register Contents after an Error or Reconfiguration Trigger Condition Reconfiguration Error/Trigger Control Register Setting Remote Update nCONFIG reset All bits are 0 nSTATUS error All bits are 0 CORE triggered reconfiguration Update register CRC error All bits are 0 Wd time out All bits are 0 Capture operations during factory configuration access the contents of the update register. This feature is used by the user logic to verify that the page address and watchdog timer settings were written correctly. Read operations in application configurations access the contents of the control register. This information is used by the user logic in the application configuration. User Watchdog Timer The user watchdog timer prevents a faulty application configuration from stalling the device indefinitely. The system uses the timer to detect functional errors after an application configuration is successfully loaded into the Arria II GX device. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Quartus II Software Support 9-53 The user watchdog timer is a counter that counts down from the initial value loaded into the remote system upgrade control register by the factory configuration. The counter is 29-bits wide and has a maximum count value of 229. When specifying the user watchdog timer value, specify only the most significant 12 bits. The granularity of the timer setting is 2 15 cycles. The cycle time is based on the frequency of the 10-MHz internal oscillator. Table 9-17 specifies the operating range of the 10-MHz internal oscillator. Table 9-17. 10-MHz Internal Oscillator Specifications (Note 1) Minimum Typical Maximum Units 4.3 5.3 10 MHz Note to Table 9-17: (1) These values are preliminary. The user watchdog timer begins counting once the application configuration enters device user mode. This timer must be periodically reloaded or reset by the application configuration before the timer expires by asserting RU_nRSTIMER. If the application configuration does not reload the user watchdog timer before the count expires, a time-out signal is generated by the remote system upgrade dedicated circuitry. The time-out signal tells the remote system upgrade circuitry to set the user watchdog timer status bit (Wd) in the remote system upgrade status register and reconfigures the device by loading the factory configuration. The user watchdog timer is not enabled during the configuration cycle of the device. Errors during configuration are detected by the CRC engine. Also, the timer is disabled for factory configurations. Functional errors should not exist in the factory configuration because it is stored and validated during production and is never updated remotely. 1 The user watchdog timer is disabled in factory configurations and during the configuration cycle of the application configuration. It is enabled after the application configuration enters user mode. Quartus II Software Support The Quartus II software provides the flexibility to include the remote system upgrade interface between the Arria II GX device logic array and the dedicated circuitry, generates configuration files for production, and allows remote programming of the system configuration memory. The ALTREMOTE_UPDATE megafunction is the implementation option in the Quartus II software that is used for the interface between the remote system upgrade circuitry and the device logic array interface. Using the megafunction block instead of creating your own logic saves design time and offers more efficient logic synthesis and device implementation. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 9-54 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Design Security ALTREMOTE_UPDATE Megafunction The ALTREMOTE_UPDATE megafunction provides a memory-like interface to the remote system upgrade circuitry and handles the shift register read and write protocol in the Arria II GX device logic. This implementation is suitable for designs that implement the factory configuration functions using a Nios II processor or user logic in the device. Figure 9-28 shows the interface signals between the ALTREMOTE_UPDATE megafunction and Nios II processor or user logic. Figure 9-28. Interface Signals between the ALTREMOTE_UPDATE Megafunction and the Nios II Processor ALTREMOTE_UPDATE read_param write_param param[2..0] data_in[23..0] Nios II Processor or User Logic reconfig reset_timer clock reset busy data_out[23..0] f For more information about the ALTREMOTE_UPDATE megafunction and the description of ports listed in Figure 9-28, refer to the ALTREMOTE_UPDATE Megafunction User Guide. Design Security This section provides an overview of the design security features and their implementation on Arria II GX devices using advanced encryption standard (AES). It also describes the security modes available in Arria II GX devices that allow you to use these new features in your designs. As Arria II GX devices start to play roles in larger and more critical designs in competitive commercial and military environments, it is increasingly important to protect your designs from copying, reverse engineering, and tampering. Arria II GX devices address these concerns with both volatile and non-volatile security feature support. Arria II GX devices have the ability to decrypt configuration bitstreams using the AES algorithm, an industry-standard encryption algorithm that is FIPS-197 certified. Arria II GX devices have a design security feature which uses a 256-bit security key. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Design Security 9-55 Arria II GX devices store configuration data in SRAM configuration cells during device operation. Because SRAM memory is volatile, the SRAM cells must be loaded with configuration data each time the device powers up. It is possible to intercept configuration data when it is being transmitted from the memory source (flash memory or a configuration device) to the device. The intercepted configuration data could then be used to configure another device. When using the Arria II GX design security feature, the security key is stored in the Arria II GX device. Depending on the security mode, you can configure the Arria II GX device using a configuration file that is encrypted with the same key, or for board testing, configured with a normal configuration file. The design security feature is available when configuring Arria II GX devices using the fast passive parallel configuration mode with an external host (such as a MAX II device or microprocessor), or when using active serial (AS) or passive serial (PS) configuration schemes. The design security feature is also available in remote update mode with AS configuration. The design security feature is not available when you are configuring your Arria II GX device using Joint Test Action Group (JTAG)-based configuration. For more details, refer to "Supported Configuration Schemes" on page 9-59. 1 When using a serial configuration scheme such as PS or fast AS, configuration time is the same whether or not the design security feature is enabled. If the FPP scheme is used with the design security or decompression feature, a x4 DCLK is required. This results in a slower configuration time when compared to the configuration time of an Arria II GX device that has neither the design security nor the decompression feature enabled. Arria II GX Security Protection Arria II GX device designs are protected from copying, reverse engineering, and tampering using configuration bitstream encryption. Security Against Copying The security key is securely stored in the Arria II GX device and cannot be read out through any interface. In addition, as configuration file read-back is not supported in Arria II GX devices, your design information cannot be copied. Security Against Reverse Engineering Reverse engineering from an encrypted configuration file is very difficult and time consuming because the Arria II GX configuration file formats are proprietary and the file contains millions of bits which require specific decryption. Reverse engineering the Arria II GX device is just as difficult because the device is manufactured on the most advanced 40-nm process technology. Security Against Tampering Once the Tamper Protection bit is set in the key programming file generated by the Quartus II software, the Arria II GX device can only be configured with configuration files encrypted with the same key. Tampering is prevented using both volatile and non-volatile keys. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 9-56 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Design Security AES Decryption Block The main purpose of the AES decryption block is to decrypt the configuration bitstream prior to entering data decompression or configuration. Prior to receiving encrypted data, you must enter and store the 256-bit security key in the device. You can choose between a non-volatile security key and a volatile security key with battery backup. The security key is scrambled prior to storing it in the key storage to make it more difficult for anyone to retrieve the stored key using de-capsulation of the device. Flexible Security Key Storage Arria II GX devices support two types of security key programming: volatile and non-volatile. Table 9-18 shows the differences between volatile keys and non-volatile keys. Table 9-18. Security Key Options Options Volatile Key Non-Volatile Key Key programmability Reprogrammable and erasable One-time programmable External battery Required Not required Key programming method (1) On-board On and off board Design protection Secure against copying and reverse engineering. Secure against copying and reverse engineering. Tamper resistant if volatile tamper protection bit is set. Tamper resistant if tamper protection bit is set. Note to Table 9-18: (1) Key programming is carried out using the JTAG interface. You can program the non-volatile key to the Arria II GX device without an external battery. Also, there are no additional requirements of any of the Arria II GX power supply inputs. VCCBAT is a dedicated power supply for volatile key storage and not shared with other on-chip power supplies, such as V CCIO or VCC. VCCBAT continuously supplies power to the volatile register regardless of the on-chip supply condition. 1 After power-up, wait 100 ms (standard POR delay) or 4 ms (fast POR delay) before beginning the key programming to ensure that VCCBAT is at its full rail. 1 As an example, the following are lithium coin-cell type batteries used for volatile key storage purposes: BR1220 (-30 to +80C) and BR2477A (-40C to +125C). f For more information about battery specifications, refer to the Device Data Sheet chapter in volume 3 of the Arria II GX Device Handbook. f For more information about the VCCBAT pin connection recommendations, refer to Arria II GX Device Family Pin Connection Guidelines. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Design Security 9-57 Arria II GX Design Security Solution Arria II GX devices are SRAM-based devices. To provide design security, Arria II GX devices require a 256-bit security key for configuration bitstream encryption. You can carry out secure configuration in the following three steps, as shown in Figure 9-29: 1. Program the security key into the Arria II GX device. Program the user-defined 256-bit AES keys to the Arria II GX device through the JTAG interface. 2. Encrypt the configuration file and store it in the external memory. Encrypt the configuration file with the same 256-bit keys used to program the Arria II GX device. Encryption of the configuration file is done using the Quartus II software. The encrypted configuration file is then loaded into the external memory, such as a configuration or flash device. 3. Configure the Arria II GX device. At system power-up, the external memory device sends the encrypted configuration file to the Arria II GX device. Figure 9-29. Design Security (Note 1) Arria II GX FPGA User-Defined Step 1 Key Storage AES Key AES Decryption Step 3 Encrypted Step 2 Memory or Configuration Configuration File Device Note to Figure 9-29: (1) Step 1, Step 2, and Step 3 correspond to the procedure detailed in "Design Security" on page 9-54. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 9-58 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Design Security Security Modes Available The following security modes are available on Arria II GX devices: Volatile Key Secure operation with volatile key programmed and required external battery--this mode accepts both encrypted and unencrypted configuration bitstreams. Use the unencrypted configuration bitstream support for board-level testing only. Non-Volatile Key Secure operation with one-time-programmable (OTP) security key programmed-- this mode accepts both encrypted and unencrypted configuration bitstreams. Use the unencrypted configuration bitstream support for board level testing only. Volatile Key with Tamper Protection Bit Set Secure operation in tamper resistant mode with volatile security key programmed-- only encrypted configuration bitstreams are allowed to configure the device. Tamper protection disables JTAG configuration with unencrypted configuration bitstream. 1 Enabling the Tamper Protection bit disables the test mode in Arria II GX devices. This process is irreversible and prevents Altera from carry-out failure analysis. Contact Altera Technical Support to enable the tamper protection bit. Non-Volatile Key with Tamper Protection Bit Set Secure operation in tamper resistant mode with OTP security key programmed--only encrypted configuration bitstreams are allowed to configure the device. Tamper protection disables JTAG configuration with unencrypted configuration bitstream. 1 Enabling the Tamper Protection bit disables the test mode in Arria II GX devices. This process is irreversible and prevents Altera from carry out failure analysis. Contact Altera Technical Support to enable the tamper protection bit. Volatile or Non-Volatile Key with JTAG Anti-Tamper Protection Bit Set All the JTAG instructions except PULSE_NCONFIG, BYPASS, KEY_VERIFY, KEY_CLR_VREG, and KEY_PROG_VOL are disabled. 1 Enabling the JTAG Anti-Tamper protection bit disables the boundary-scan test (BST) features in Arria II GX devices. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Design Security 9-59 No Key Operation Only unencrypted configuration bitstreams are allowed to configure the device. Table 9-19 summarizes the different security modes and configuration bitstream supported for each mode. Table 9-19. Security Modes Supported Mode (1) Function Configuration File Volatile key Secure Encrypted Board-level testing Unencrypted Secure Encrypted Board-level testing Unencrypted Non-volatile key Volatile key with tamper protection bit set Secure (tamper resistant) (2) Encrypted Non-volatile key with tamper protection bit set Secure (tamper resistant) (2) Encrypted Volatile or non-volatile key with JTAG anti-tamper protection bit set JTAG tamper resistant (3) Notes to Table 9-19: (1) In No key operation, only the unencrypted configuration file is supported. (2) The tamper protection bit setting does not prevent the device from being reconfigured. (3) It does not control the decryption data path. Supported Configuration Schemes The Arria II GX device supports only selected configuration schemes, depending on the security mode you select when you encrypt the Arria II GX device. Figure 9-30 shows the restrictions of each security mode when encrypting Arria II GX devices. Figure 9-30. Arria II GX Security Modes--Sequence and Restrictions No Key Volatile Key Unencrypted or Encrypted Configuration File Volatile Key with Tamper-Protection Bit Set Encrypted Configuration File (c) February 2009 Altera Corporation Unencrypted Configuration File Non-Volatile Key Unencrypted or Encrypted Configuration File Non-Volatile Key with Tamper-Protection Bit Set Encrypted Configuration File Arria II GX Device Handbook Volume 1 9-60 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Design Security Table 9-20 shows the configuration modes allowed in each of the security modes. Table 9-20. Allowed Configuration Modes for Various Security Modes (Note 1) Security Mode No key Secure with volatile key Configuration File Allowed Configuration Modes Unencrypted All configuration modes that do not engage the design security feature. Encrypted Board-level testing with volatile key Unencrypted Secure with non-volatile key Encrypted Board-level testing with nonvolatile key Unencrypted Secure in tamper resistant mode using volatile or non-volatile key with tamper protection set Encrypted Passive serial with AES (and/or with decompression) Fast passive parallel with AES (and/or with decompression) Remote update fast AS with AES (and/or with decompression) AS (and/or with decompression) All configuration modes that do not engage the design security feature. Passive serial with AES (and/or with decompression) Fast passive parallel with AES (and/or with decompression) Remote update fast AS with AES (and/or with decompression) AS (and/or with decompression) All configuration modes that do not engage the design security feature. Passive serial with AES (and/or with decompression) Fast passive parallel with AES (and/or with decompression) Remote update fast AS with AES (and/or with decompression) AS (and/or with decompression) Note to Table 9-20: (1) There is no impact to the configuration time required compared to unencrypted configuration modes except when using FPP with AES (and/or decompression), which requires DCLK that is 4x the data rate. 1 The design security feature is available in all configuration methods except JTAG. Therefore, you can use the design security feature in FPP mode (when using an external controller, such as a MAX II device or a microprocessor and flash memory), or in fast AS and PS configuration schemes. Table 9-21 summarizes the configuration schemes that support the design security feature both for volatile key and non-volatile key programming. Table 9-21. Design Security Configuration Schemes Availability (Part 1 of 2) Configuration Scheme FPP Design Security Configuration Method MAX II device or microprocessor and flash memory v (1) Enhanced configuration device -- Fast AS Serial configuration device v PS MAX II device or microprocessor and flash memory v Download cable v Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Document Revision History 9-61 Table 9-21. Design Security Configuration Schemes Availability (Part 2 of 2) Configuration Scheme JTAG (2) Design Security Configuration Method MAX II device or microprocessor and flash memory -- Download cable -- Notes to Table 9-21: (1) In this mode, the host system must send a DCLK that is 4x the data rate. (2) JTAG configuration supports only unencrypted configuration file. You can use the design security feature with other configuration features, such as compression and remote system upgrade features. When you use compression with the design security feature, the configuration file is first compressed and then encrypted using the Quartus II software. During configuration, the Arria II GX device first decrypts and then decompresses the configuration file. Document Revision History Table 9-22 shows the revision history for this document. Table 9-22. Document Revision History Date and Document Version February 2009, v1.0 (c) February 2009 Changes Made Initial release. Altera Corporation Summary of Changes -- Arria II GX Device Handbook Volume 1 9-62 Arria II GX Device Handbook Volume 1 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices Document Revision History (c) February 2009 Altera Corporation 10. SEU Mitigation in Arria II GX Devices AIIGX51010-1.0 Introduction In critical applications such as avionics, telecommunications, system control, and military applications, it is important to be able to do the following: Confirm that the configuration data stored in an Arria(R) II GX device is correct. Alert the system to the occurrence of a configuration error. The error detection feature is enhanced in the Arria II GX device family. This section describes how to activate and use the error detection cyclical redundancy check (CRC) feature when your Arria II GX device is in user mode and describes how to recover from configuration errors caused by CRC errors. 1 For Arria II GX devices, the error detection CRC feature is provided in the Quartus (R) II software starting with version 9.0. Using the error detection CRC feature for the Arria II GX device family has no impact on fitting or performance. This chapter contains the following sections: f "Error Detection Fundamentals" on page 10-1 "Configuration Error Detection" on page 10-2 "User Mode Error Detection" on page 10-2 "Error Detection Pin Description" on page 10-5 "Error Detection Block" on page 10-5 "Error Detection Timing" on page 10-8 "Recovering From CRC Errors" on page 10-11 For more information about CRC, refer to AN 357: Error Detection Using CRC in Altera FPGA Devices. Error Detection Fundamentals Error detection determines if the data received through a medium is corrupted during transmission. To accomplish this, the transmitter uses a function to calculate a checksum value for the data and appends the checksum to the original data frame. The receiver uses the same calculation methodology to generate a checksum for the received data frame and compares the received checksum to the transmitted checksum. If the two checksum values are equal, the received data frame is correct and no data corruption occurred during transmission or storage. The error detection CRC feature uses the same concept. When Arria II GX devices are successfully configured and are in user mode, the error detection CRC feature ensures the integrity of the configuration data. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 10-2 Chapter 10: SEU Mitigation in Arria II GX Devices Configuration Error Detection Configuration Error Detection In configuration mode, a frame-based CRC is stored in the configuration data and contains the CRC value for each data frame. During configuration, the Arria II GX device calculates the CRC value based on the frame of data that is received and compares it against the frame CRC value in the data stream. Configuration continues until either the device detects an error or configuration is complete. In Arria II GX devices, the CRC value is calculated during the configuration stage. A parallel CRC engine generates 16 CRC check bits per frame and then stores them into the configuration random access memory (CRAM). The CRAM chain used for storing CRC check bits is 16-bits wide; its length is equal to the number of frames in the device. User Mode Error Detection Arria II GX devices have built-in error detection circuitry to detect data corruption by soft errors in the CRAM cells. This feature allows all CRAM contents to be read and verified to match a configuration-computed CRC value. Soft errors are changes in a CRAM's bit state due to an ionizing particle. The error detection capability continuously computes the CRC of the configured CRAM bits and compares it with the pre-calculated CRC. If the CRCs match, there is no error in the current configuration CRAM bits. The process of error detection continues until the device is reset (by setting nCONFIG low). When the device transitions into user mode, the error detection process is enabled if you enabled the CRC error detection option in the Quartus II software. A single 16-bit CRC calculation is done on a per-frame basis. Once it has finished the CRC calculation for a frame, the resulting 16-bit signature is hex 0000 if there are no detected CRAM bit errors in a frame by the error detection circuitry and the output signal CRC_ERROR is 0. If a CRAM bit error is detected by the circuitry in a frame in the device, the resulting signature is non-zero. This causes the CRC engine to start searching the error bit location. The error detection logic in Arria II GX devices calculates CRC check bits for each frame and pulls the CRC_ERROR pin high when it detects bit errors in the chip. Within a frame, it can detect all single-bit, double-bit, and three-bit errors. The probability of more than three CRAM bits being flipped by an single event upset (SEU) is very low. In general, the probability of detection for all error patterns is 99.998%. The CRC engine reports the bit location and determines the type of error for all single-bit errors and over 99.641% of double-adjacent errors. The probability of other error patterns is very low and report of location of bit flips is not guaranteed by the CRC engine. You can also read-out the error bit location through the Joint Test Action Group (JTAG) and the core interface. You must shift these bits out from the error message register through either the JTAG instruction, SHIFT_EDERROR_REG, or the core interface, before the CRC detects the next error in another frame. The CRC circuit continues to run, and if an error is detected, you need to decide whether to complete a reconfiguration or to ignore the CRC error. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 10: SEU Mitigation in Arria II GX Devices User Mode Error Detection 1 10-3 For more information about the timing requirement to shift out error information from the error message register, refer to "Error Detection Timing" on page 10-8. The error detection logic continues to calculate the CRC_ERROR and 16-bit signatures for the next frame of data regardless of whether an error has occurred in the current frame or not. You need to monitor these signals and take the appropriate actions if a soft error occurs. The error detection circuitry in Arria II GX devices uses a 16-bit CRC-ANSI standard (16-bit polynomial) as the CRC generator. The computed 16-bit CRC signature for each frame is stored in the CRAM. The total storage size is 16 (number of bits per frame) x the number of frames. The Arria II GX device error detection CRC feature does not check memory blocks and I/O buffers. Thus, the CRC_ERROR signal may stay solid high or low, depending on the error status of the previously checked CRAM frame. The I/O buffers are not verified during error detection because these bits use flipflops as storage elements that are more resistant to soft errors compared to CRAM cells. MLAB and M9K memory blocks support parity bits that are used to check the contents of memory blocks for any error. f For more information about error detection in Arria II GX memory blocks, refer to the Embedded Memory Blocks in Arria II GX Devices chapter in volume 1 of the Arria II GX Device Handbook. To provide testing capability of the error detection block, a JTAG instruction, EDERROR_INJECT, is provided. This instruction is able to change the content of the 21-bit JTAG fault injection register, used for error injection in Arria II GX devices, thereby enabling testing of the error detection block. 1 You can only execute the EDERROR_INJECT JTAG instruction when the device is in user mode. Table 10-1 describes the EDERROR_INJECT JTAG instruction. Table 10-1. EDERROR_INJECT JTAG Instruction JTAG Instruction Instruction Code Description EDERROR_INJECT 00 0001 0101 This instruction controls the 21-bit JTAG fault injection register, which is used for error injection. You can create a JamTM file (.jam) to automate the testing and verification process. This allows you to verify the CRC functionality in-system and on-the-fly, without having to reconfigure the device. You can then switch to the CRC circuit to check for real errors induced by an SEU. You can introduce a single error or double errors adjacent to each other to the configuration memory. This provides an extra way to facilitate design verification and system fault tolerance characterization. Use the JTAG fault injection register with EDERROR_INJECT instruction to flip the readback bits. The Arria II GX device is then forced into error test mode. Altera recommends you reconfigure the device after the test completes. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 10-4 Chapter 10: SEU Mitigation in Arria II GX Devices User Mode Error Detection The content of the JTAG fault injection register is not loaded into the fault injection register during the processing of the last frame and the first frame. It is only loaded at the end of this period. 1 You can only introduce error injection in the first data frame, but you can monitor the error information at any time. For more information about the JTAG fault injection register and fault injection register, refer to "Error Detection Registers" on page 10-7. Table 10-2 shows how the fault injection register is implemented and describes error injection. Table 10-2. Fault Injection Register Bit Bit[20..19] Bit[18..8] Bit[7..0] Description Error Type Byte Location of the Injected Error Error Byte Value Depicts the location of the injected error in the first data frame. Depicts the location of the bit error and corresponds to the error injection type selection. Error Type (1) Bit[20] Bit[19] Content Error injection type 0 1 Single byte error injection 1 0 Double-adjacent byte error injection 0 0 No error injection Note to Table 10-2: (1) Bit[20] and Bit[19] cannot both be set to 1, as this is not a valid selection. The error detection circuitry decodes this as no error injection. Automated Single Event Upset Detection Arria II GX devices offer on-chip circuitry for automated checking of single event upset detection. Some applications that require the device to operate error-free in high-neutron flux environments require periodic checks to ensure continued data integrity. The error detection CRC feature ensures data reliability and is one of the best options for mitigating SEU. You can implement the error detection CRC feature with existing circuitry in Arria II GX devices, eliminating the need for external logic. The CRC_ERROR pin reports a soft error when configuration CRAM data is corrupted; you must decide whether to reconfigure the device or to ignore the error. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 10: SEU Mitigation in Arria II GX Devices Error Detection Pin Description 10-5 Error Detection Pin Description The following sections describe the CRC_ERROR pin. CRC_ERROR Pin Table 10-3 describes the CRC_ERROR pin. Table 10-3. CRC_ERROR Pin Description Pin Name CRC_ERROR Pin Type Description I/O, output open-drain Active high signal that indicates that the error detection circuit has detected errors in the configuration CRAM bits. This is an optional pin and is used when the error detection CRC circuit is enabled. When the error detection CRC circuit is disabled, it is a user I/O pin. The CRC error output, when using the WYSIWYG function, is a dedicated path to the CRC_ERROR pin. To use the CRC_ERROR pin, tie this pin to VCCPGM through a 10-k resistor. Alternatively, depending on the input voltage specification of the system receiving the signal, tie this pin to a different pull-up voltage. 1 WYSIWYG is an optimization technique that performs optimization on the Verilog Quartus Mapping (VQM) netlist within the Quartus II software. Error Detection Block The error detection block contains the logic necessary to calculate the 16-bit CRC signature for the configuration CRAM bits in the Arria II GX device. The CRC circuit continues running even if an error occurs. When a soft error occurs, the device sets the CRC_ERROR pin high. The two types of CRC detection that check the configuration bits are shown in Table 10-4. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 10-6 Chapter 10: SEU Mitigation in Arria II GX Devices Error Detection Block Table 10-4. Two Types of CRC Detection First Type of CRC Detection Second Type of CRC Detection This is the CRAM error checking ability (16-bit CRC) during user mode for use by the CRC_ERROR pin. This is the 16-bit CRC that is embedded in every configuration data frame. For each frame of data, the pre-calculated 16-bit CRC enters the CRC circuit at the end of the frame data and determines whether there is an error or not. During configuration, after a frame of data is loaded into the Arria II GX device, the pre-computed CRC is shifted into the CRC circuitry. If an error occurs, the search engine finds the location of the error. The error messages can be shifted out through the JTAG instruction or core interface logics while the error detection block continues running. The JTAG interface reads out the 16-bit CRC result for the first frame and also shifts the 16-bit CRC bits to the 16-bit CRC storage registers for test purposes. At the same time, the CRC value for the data frame shifted-in is calculated. If the pre-computed CRC and calculated CRC values do not match, nSTATUS is set low. Every data frame has a 16-bit CRC; therefore, there are many 16-bit CRC values for the whole configuration bitstream. Every device has different lengths of the configuration data frame. Single error, double errors, or double errors adjacent to each other can be deliberately introduced to configuration memory for testing and design verification. 1 The "Error Detection Block" section focuses on the first type, the 16-bit CRC only, when the device is in user mode. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 10: SEU Mitigation in Arria II GX Devices Error Detection Block 10-7 Error Detection Registers There is one set of 16-bit registers in the error detection circuitry that stores the computed CRC signature. A non-zero value on the syndrome register causes the CRC_ERROR pin to be set high. Figure 10-1 shows the block diagram of the error detection circuitry, syndrome registers, and error injection block. Figure 10-1. Error Detection Circuitry, Syndrome Registers, and Error Injection Block 16-Bit CRC Calculation and Error Readback bitstream with expected CRC included Syndrome Search Engine Error Detection State Machine 8 Register Control Signals 30 16 Error Message CRC_ERROR Register 46 Error Injection Block Fault Injection Register JTAG Update User Update Register Register JTAG Shift User Shift Register Register JTAG Fault Injection Register JTAG TDO General Routing Table 10-5 defines the registers shown in Figure 10-1. Table 10-5. Error Detection Registers (Part 1 of 2) Register Description Syndrome Register This register contains the CRC signature of the current frame through the error detection verification cycle. The CRC_ERROR signal is derived from the contents of this register. Error Message Register This 46-bit register contains information on the error type, location of the error, and the actual syndrome. The types of errors and location reported are single- and double-adjacent bit errors. The location bits for other types of errors are not identified by the error message register. The content of the register is shifted out through the JTAG SHIFT_EDERROR_REG instruction or to the core through the core interface. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 10-8 Chapter 10: SEU Mitigation in Arria II GX Devices Error Detection Timing Table 10-5. Error Detection Registers (Part 2 of 2) Register Description JTAG Update Register This register is automatically updated with the contents of the error message register one cycle after the 46-bit register content is validated. It includes a clock enable, which must be asserted prior to being sampled into the JTAG shift register. This requirement ensures that the JTAG Update Register is not being written into by the contents of the Error Message Register at exactly the same time that the JTAG shift register is reading its contents. User Update Register This register is automatically updated with the contents of the error message register one cycle after the 46-bit register content is validated. It includes a clock enable, which must be asserted prior to being sampled into the user shift register. This requirement ensures that the user update register is not being written into by the contents of the error message register at exactly the same time that the user shift register is reading its contents. JTAG Shift Register This register is accessible by the JTAG interface and allows the contents of the JTAG update register to be sampled and read out by JTAG instruction SHIFT_EDERROR_REG. User Shift Register This register is accessible by the core logic and allows the contents of the user update register to be sampled and read by user logic. JTAG Fault Injection Register This 21-bit register is fully controlled by the JTAG instruction EDERROR_INJECT. This register holds the information of the error injection that you want in the bitstream. Fault Injection Register The content of the JTAG fault injection register is loaded into this 21-bit register when it is being updated. Error Detection Timing When the error detection CRC feature is enabled through the Quartus II software, the device automatically activates the CRC process upon entering user mode, after configuration, and after initialization is complete. If an error is detected within a frame, CRC_ERROR is driven high at the end of the error location search after the error message register is updated. At the end of this cycle, the CRC_ERROR pin is pulled low for a minimum of 32 clock cycles. If the next frame contains an error, CRC_ERROR is driven high again after the error message register is overwritten by the new value. You can start to unload the error message on each rising edge of the CRC_ERROR pin. Error detection runs until the device is reset. The error detection circuitry runs off an internal configuration oscillator with a divisor that sets the maximum frequency. Table 10-6 shows the minimum and maximum error detection frequencies. Table 10-6. Minimum and Maximum Error Detection Frequencies Device Type Error Detection Frequency Maximum Error Detection Frequency Minimum Error Detection Frequency Valid Divisors (n) Arria II GX 100 MHz / 2n 50 MHz 390 kHz 1, 2, 3, 4, 5, 6, 7, 8 Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 10: SEU Mitigation in Arria II GX Devices Error Detection Timing 10-9 You can set a lower clock frequency by specifying a division factor in the Quartus II software (refer to "Software Support" on page 10-10). The divisor is a power of two (2), where n is between 1 and 8. The divisor ranges from 2 through 256. See the following equation: Equation 10-1. 100MHz error detection frequency = -------------------n 2 1 The error detection frequency reflects the frequency of the error detection process for a frame because the CRC calculation in Arria II GX devices is done on a per-frame basis. The error message register is updated whenever an error or errors occur. If the error location and message are not shifted out before the next error location is found, the previous error location and message is overwritten by the new information. To avoid this, you must shift these bits out within one frame CRC verification. The minimum interval time between each update for the error message register depends on the device and the error detection clock frequency. However, slowing down the error detection clock frequency slows down the error recovery time for the SEU event. Table 10-7 shows the estimated minimum interval time between each update for the error message register for Arria II GX devices. Table 10-7. Minimum Update Interval for Error Message Register (Note 1) Device Timing Interval (s) EP2AGX20 8.12 EP2AGX30 8.12 EP2AGX45 12.24 EP2AGX65 12.24 EP2AGX95 16.08 EP2AGX125 16.08 EP2AGX190 20.84 EP2AGX260 20.84 Note to Table 10-7: (1) These timing numbers are preliminary. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 10-10 Chapter 10: SEU Mitigation in Arria II GX Devices Error Detection Timing CRC calculation time for the error detection circuitry to check from the first until the last frame depends on the device and the error detection clock frequency. Table 10-8 shows the estimated time for each CRC calculation with minimum and maximum clock frequencies for Arria II GX devices. The minimum CRC calculation time is calculated with the maximum error detection frequency with divisor factor 1 while the maximum CRC calculation time is calculated with the minimum error detection frequency with divisor factor 8. Table 10-8. CRC Calculation Time Device Minimum Time (ms) Maximum Time (s) EP2AGX20 18.06 5.15 EP2AGX30 18.06 5.15 EP2AGX45 44.00 12.20 EP2AGX65 44.00 12.20 EP2AGX95 82.40 22.82 EP2AGX125 82.40 22.82 EP2AGX190 160.00 44.36 EP2AGX260 160.00 44.36 Software Support The Quartus II software, starting with version 8.1, supports the error detection CRC feature for Arria II GX devices. Enabling this feature in the Device and Pin Options dialog box generates the CRC_ERROR output to the optional dual purpose CRC_ERROR pin. Enable the error detection feature using CRC by performing the following steps: 1. Open the Quartus II software and load a project using an Arria II GX device. 2. On the Assignments menu, click Settings. The Settings dialog box appears. 3. In the Category list, select Device. The Device screen appears. 4. Click Device and Pin Options. The Device and Pin Options dialog box appears (see Figure 10-2). 5. In the Device and Pin Options dialog box, click the Error Detection CRC tab. 6. Turn on Enable error detection CRC (Figure 10-2). Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 10: SEU Mitigation in Arria II GX Devices Recovering From CRC Errors 10-11 Figure 10-2. Enabling the Error Detection CRC Feature in the Quartus II Software 7. In the Divide error check frequency by box, enter a valid divisor as documented in Table 10-6 on page 10-8. 8. Click OK. Recovering From CRC Errors The system that the Arria II GX device resides in must control device reconfiguration. After detecting an error on the CRC_ERROR pin, strobing the nCONFIG signal low directs the system to perform the reconfiguration at a time when it is safe. When the data bit is rewritten with the correct value by reconfiguring the device, the device functions correctly. While soft errors are uncommon in Altera devices, certain high-reliability applications may require a design to account for these errors. Document Revision History Table 10-9 shows the revision history for this chapter. Table 10-9. Document Revision History Date and Document Version February 2009, v1.0 (c) February 2009 Changes Made Initial release. Altera Corporation Summary of Changes -- Arria II GX Device Handbook Volume 1 10-12 Arria II GX Device Handbook Volume 1 Chapter 10: SEU Mitigation in Arria II GX Devices Document Revision History (c) February 2009 Altera Corporation 11. JTAG Boundary-Scan Testing AIIGX51011-1.0 Introduction This chapter describes the boundary-scan test (BST) features that are supported in Arria(R) II GX devices. The features are similar to Arria GX devices, unless stated in this document. Arria II GX devices support IEEE Std. 1149.1 and IEEE Std. 1149.6. The IEEE Std. 1149.6 is only supported on the high-speed serial interface (HSSI) transceivers in Arria II GX devices. The purpose of IEEE Std. 1149.6 is to enable board-level connectivity checking between transmitters and receivers that are AC coupled (connected with a capacitor in series between the source and destination). This chapter includes the following sections: f "IEEE Std. 1149.6 Boundary-Scan Register" on page 11-1 "BST Operation Control" on page 11-3 "I/O Voltage Support in a JTAG Chain" on page 11-5 "Boundary-Scan Description Language Support" on page 11-6 For information about the following topics, refer to the IEEE 1149.1 (JTAG) Boundary-Scan Testing for Arria GX Devices chapter in volume 2 of the Arria GX Device Handbook: IEEE Std. 1149.1 BST architecture and circuitry TAP controller state-machine IEEE Std. 1149.1 JTAG instructions JTAG instructions code with descriptions IEEE Std. 1149.1 BST guidelines IEEE Std. 1149.6 Boundary-Scan Register The boundary-scan cell (BSC) for HSSI transmitters (GXB_TX[p,n]) and receivers/input clock buffer (GXB_RX[p,n])/(REFCLK[0..7]) in Arria II GX devices are different from the BSCs for I/O pins. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 11-2 Chapter 11: JTAG Boundary-Scan Testing IEEE Std. 1149.6 Boundary-Scan Register Figure 11-1 shows the Arria II GX HSSI transmitter boundary-scan cell. Figure 11-1. Arria II GX HSSI Transmitter BSC with IEEE Std. 1149.6 BST Circuitry BSCAN PMA 0 BSTX1 SDOUT AC JTAG Output Buffer 0 OE D Q D Q 1 1 Pad Mission (DATAOUT) 0 D D Q Q Tx Output Buffer 0 1 BS0EB 1 nOE Pad OE Logic M0 RHZ 0 0 OE BSTX0 D D Q Q AC JTAG Output Buffer 1 1 MEM_INIT SDIN SHIFT CLK UPDATE HIGHZ AC_TEST AC_MODE MODE Capture Update Registers Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 11: JTAG Boundary-Scan Testing BST Operation Control 11-3 Figure 11-2 shows the Arria II GX HSSI receiver/input clock buffer BSC. Figure 11-2. Arria II GX HSSI Receiver/Input Clock Buffer BSC with IEEE Std. 1149.6 BST Circuitry BSCAN SDOUT PMA AC JTAG Test Receiver BSRX1 Hysteretic Memory 0 BSOUT1 D Q Pad Mission (DATAIN) Optional INTEST/RUNBIST not supported 1 0 Hysteretic Memory BSOUT0 Q Pad AC JTAG Test Receiver BSRX0 D Rx Input Buffer 1 HIGHZ SCIN SHIFT CLK UPDATE AC_TEST MEM_INIT MODE AC_MODE Capture Update Registers f For information about Arria II GX user I/O boundary-scan cells, refer to the IEEE 1149.1 (JTAG) Boundary-Scan Testing for Arria GX Devices chapter in volume 2 of the Arria GX Device Handbook. BST Operation Control Table 11-1 shows the boundary-scan register length for Arria II GX devices. Table 11-1. Arria II GX Boundary-Scan Register Length (c) February 2009 Altera Corporation Device Boundary-Scan Register Length EP2AGX20 819 EP2AGX30 819 EP2AGX45 1227 EP2AGX65 1227 EP2AGX95 1467 EP2AGX125 1467 EP2AGX190 1971 EP2AGX260 1971 Arria II GX Device Handbook Volume 1 11-4 Chapter 11: JTAG Boundary-Scan Testing BST Operation Control Table 11-2 shows the IDCODE information for Arria II GX devices. Table 11-2. 32-Bit Arria II GX Device IDCODE IDCODE (32 Bits) (1) Device Version (4 Bits) Part Number (16 Bits) Manufacturer Identity (11 Bits) LSB (1 Bit) (2) EP2AGX20 0000 0010010100010001 000 0110 1110 1 EP2AGX30 0000 0010010100000001 000 0110 1110 1 EP2AGX45 0000 0010010100010010 000 0110 1110 1 EP2AGX65 0000 0010010100000010 000 0110 1110 1 EP2AGX95 0000 0010010100010011 000 0110 1110 1 EP2AGX125 0000 0010010100000011 000 0110 1110 1 EP2AGX190 0000 0010010100010100 000 0110 1110 1 EP2AGX260 0000 0010010100000100 000 0110 1110 1 Notes to Table 11-2: (1) The MSB is on the left. (2) The IDCODE LSB is always 1. 1 To read IDCODE correctly, issue the IDCODE instruction after initialization, which is signaled by nSTATUS going high. IEEE Std.1149.6 mandates the addition of two new instructions: EXTEST_PULSE and EXTEST_TRAIN. These two instructions enable edge-detecting behavior on the signal path containing the AC pins. 1 When JTAG Anti Tamper mode is enabled, boundary scan test is disabled. EXTEST_PULSE The instruction code for EXTEST_PULSE is 0010001111. The EXTEST_PULSE instruction generates three output transitions: Driver drives data on the falling edge of TCK in UPDATE_IR/DR. Driver drives inverted data on the falling edge of TCK after entering the RUN_TEST/IDLE state. Driver drives data on the falling edge of TCK after leaving the RUN_TEST/IDLE state. EXTEST_TRAIN The instruction code for EXTEST_TRAIN is 0001001111. The EXTEST_TRAIN instruction behaves the same as the EXTEST_PULSE instruction with one exception. The output continues to toggle on the TCK falling edge as long as the TAP controller is in the RUN_TEST/IDLE state. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 11: JTAG Boundary-Scan Testing I/O Voltage Support in a JTAG Chain 11-5 I/O Voltage Support in a JTAG Chain An Arria II GX device operating in BST mode uses four required pins: TDI, TDO, TMS, and TCK. All JTAG input pins are powered by the VCCIO power supply. The TDO pin is powered up by the VCCIO and VCCPD power supply of I/O Bank 8C. You must connect VCCPD according to the I/O standard used in the same bank: For 3.3-V I/O standards, connect V CCPD to 3.3 V For 3.0-V I/O standards, connect V CCPD to 3.0 V For 2.5-V and below I/O standards, connect V CCPD to 2.5 V The JTAG chain supports several devices. However, use caution if the chain contains devices that have different VCCIO levels. Table 11-3 shows board design recommendations to ensure proper JTAG chain operation. Table 11-3. Supported TDO/TDI Voltage Combinations Device Arria II GX Arria II GX TDO VC CPD and VC CIO Voltage Level in I/O Bank 8C TDI Input Buffer Power VCC IO = 3.3 V VC CIO = 3.0 V VCC IO = 2.5 V VC CIO = 1.8 V VCC IO = 1.5 V VC CIO = 3.3 V v (1) v (1) v (2) v (3) Level shifter required VC CIO = 3.0 V v (1) v (1) v (2) v (3) Level shifter required VC CIO = 2.5 V v (1) v (1) v (2) v (3) Level shifter required VC CIO = 1.8 V v (1) v (1) v (2) v (3) Level shifter required VC CIO = 1.5 V v (1) v (1) v (2) v (3) v VCC = 3.3 V v (1) v (1) v (2) v (3) Level shifter required VCC = 2.5 V v (1), (4) v (1), (4) v (2) v (3) Level shifter required VCC = 1.8 V v (1), (4) v (1), (4) v (2), (5) v Level shifter required VCC = 1.5 V v (1), (4) v (1), (4) v (2), (5) v (6) v Non-Arria II GX Notes to Table 11-3: (1) (2) (3) (4) (5) (6) The TDO output buffer meets VOH (Min.) = 2.4 V. The TDO output buffer meets VOH (Min.) = 2.0 V. An external 250- pull-up resistor is not required; however, they are recommended if signal levels on the board are not optimal. The input buffer must be 3.0-V tolerant. The input buffer must be 2.5-V tolerant. The input buffer must be 1.8-V tolerant. f (c) February 2009 For more information about I/O voltage support in the JTAG chain, refer to the IEEE 1149.1 (JTAG) Boundary-Scan Testing for Arria GX Devices chapter in volume 2 of the Arria GX Device Handbook. Altera Corporation Arria II GX Device Handbook Volume 1 11-6 Chapter 11: JTAG Boundary-Scan Testing Boundary-Scan Description Language Support Boundary-Scan Description Language Support The boundary-scan description language (BSDL), a subset of VHDL, provides a syntax that allows you to describe the features of an IEEE Std. 1149.6 BST-capable device that can be tested. You can test software development systems then use the BSDL files for test generation, analysis, and failure diagnostics. f For more information about BSDL files for IEEE Std. 1149.6-compliant Arria II GX devices, visit the Altera(R) website at www.altera.com. f You can also generate BSDL files (pre-configuration and post-configuration) for IEEE std. 1149.6-compliant Arria II GX devices with the Quartus(R) II software version 9.1 and later. For the procedure for generating BSDL files using the Quartus II software, visit the Altera website at www.altera.com. Revision History Table 11-4 shows the revision history for this document. Table 11-4. Document Revision History Date and Document Version February 2009, v 1.0 Changes Made Summary of Changes Initial release. Arria II GX Device Handbook Volume 1 -- (c) February 2009 Altera Corporation 12. Power Requirements for Arria II GX Devices AIIGX51012-1.0 Introduction The total power of an Altera(R) Arria(R) II GX FPGA includes static power and dynamic power. Static power is the power consumed by the FPGA when it is configured, but no clocks are operating. Dynamic power is composed of switching power when the device is configured and running. The Quartus(R) II software optimizes all designs with Arria II GX power technology to ensure performance is met at the lowest power consumption. This automatic process allows you to concentrate on the functionality of your design instead of the power consumption of your design. This chapter includes the following sections: f "External Power Supply Requirements" on page 12-1 "Power-On Reset Circuitry" on page 12-2 "Hot Socketing" on page 12-2 For more information about using the PowerPlay Power Analyzer in the Quartus II software, refer to the Power Estimation and Power Analysis section in volume 3 of the Quartus II Handbook. External Power Supply Requirements This section describes the different external power supplies needed to power Arria II GX devices. Table 12-1 lists the external power supply pins for Arria II GX devices. You can supply some of the power supply pins with the same external power supply, provided they need the same voltage level. f For each Altera recommended power supply's operating conditions, refer to the Device Data Sheet chapter in volume 3 of the Arria II GX Device Handbook. f For power supply pin connection guidelines and power regulator sharing, refer to the Arria II GX Device Family Pin Connection Guidelines. Table 12-1. Arria II GX Power Supply Requirements (Part 1 of 2) Power Supply Pin Nominal Voltage Level (V) Description VCC 0.9 V Supplies power to the core, periphery, I/O registers, PCIe HIP block, and transceiver PCS VCCD_PLL 0.9 V Supplies power to the digital portions of the PLL VCCA_PLL (1) 2.5 V Supplies power to the analog portions of the PLL and device-wide power management circuitry VCCCB 1.5 V Supplies power to the configuration RAM bits VCCPD 2.5 V, 3.0 V, 3.3 V (c) February 2009 Altera Corporation Supplies power to the I/O pre-drivers, differential input buffers, and MSEL circuitry Arria II GX Device Handbook Volume 1 12-2 Chapter 12: Power Requirements for Arria II GX Devices Power-On Reset Circuitry Table 12-1. Arria II GX Power Supply Requirements (Part 2 of 2) Power Supply Pin Nominal Voltage Level (V) VCCIO 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.0 V, 3.3 V VREF 0.6 V, 0.75 V, 0.9 V, 1.25 V 1.2 V-3.3 V VCCBAT Description Supplies power to the I/O banks Reference voltage for the voltage-referenced I/O standards Battery back-up power supply for the design security volatile key register VCCA 2.5 V Supplies power to the transceiver PMA regulator VCCH_GXB 1.5 V Supplies power to the transceiver PMA output (TX) buffer VCCL_GXB 1.1 V Supplies power to the transceiver PMA TX, PMA RX, and clocking 0V GND Ground Note to Table 12-1: (1) VCCA_PLL must be powered up even if the PLL is not used. Power-On Reset Circuitry The Arria II GX power-on reset (POR) circuitry generates a POR signal to keep the device in reset state until the power supplies voltage levels have stabilized during power-up. The POR circuitry monitors V CC , VCCA_PLL, VCCCB, VCCPD, and VCCIO for I/O banks 3C and 8C, where the configuration pins are located. The POR circuitry tristates all user I/O pins until the power supplies reach the recommended operating levels. These power supplies are required to monotonically reach their full-rail values without plateaus and within the maximum power supply ramp time, tRAMP. The POR circuitry de-asserts the POR signal after the power supplies reach their full-rail values to release the device from reset state. POR circuitry is important to ensure that all the circuits in the Arria II GX device are at certain known states during power up. You can select the POR signal pulse width between fast POR time or standard POR time using the MSEL pin settings. For fast POR time, the POR signal pulse width is set to 4 ms for the power supplies to ramp up to full rail. For standard POR time, the POR signal pulse width is set to 100 ms for the power supplies to ramp up to full rail. In both cases, you can extend the POR time with an external component to assert the nSTATUS pin low. f For more information about the POR specification, refer to the Device Data Sheet chapter in volume 3 of the Arria II GX Device Handbook. f For more information about MSEL pin settings, refer to the Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices chapter in volume 1 of the Arria II GX Device Handbook. Hot Socketing Arria II GX device I/O pins are hot-socketing compliant without the need for external components or special design requirements. Hot-socketing support in Arria II GX devices has the following advantages: You can drive the device before power up without damaging it. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Chapter 12: Power Requirements for Arria II GX Devices Hot Socketing 12-3 I/O pins remain tri-stated during power up. The device does not drive out before or during power up, thereby not affecting other buses in operation. You can insert or remove an Arria II GX device from a powered-up system board without damaging or interfering with normal system and board operation. Devices Can Be Driven before Power Up You can drive signals into regular and transceiver Arria II GX I/O pins before or during power up or power down without damaging the device. Arria II GX devices also support power up or power down of the power supplies in any sequence to simplify system-level design. I/O Pins Remain Tri-Stated During Power Up A device that does not support hot socketing may interrupt system operation or cause contention by driving out before or during power up. In a hot-socketing situation, the Arria II GX device output buffers are turned off during system power up or power down. Also, the Arria II GX device does not drive out until the device is configured and working within recommended operating conditions. Insertion or Removal of an Arria II GX Device from a Powered-Up System Devices that do not support hot socketing can short power supplies when powered up through the device signal pins. This irregular power up can damage both the driving and driven devices and can disrupt card power up. An Arria II GX device may be inserted into (or removed from) a powered up system board without damaging or interfering with system-board operation. You can power up or power down the V CCIO, VCC, and VCCPD supplies in any sequence and at any time between them. The power supply ramp rates can range from 50 s to 100 ms. f For more information about the hot-socketing specification, refer to the Device Data Sheet chapter in volume 3 of the Arria II GX Device Handbook and the Hot-Socketing and Power-Sequencing Feature and Testing for Altera Devices White Paper. Hot Socketing Feature Implementation Arria II GX devices are immune to latch-up when hot socketing. The hot-socketing feature turns off the output buffer during power up and power down of the VCC, VCCIO, or VCCPD power supplies. Hot-socketing circuitry generates an internal HOTSCKT signal when the VCC, VCCIO, or V CCPD power supplies are below the threshold voltage. Hot-socketing circuitry is designed to prevent excess I/O leakage during power up. When the voltage ramps up very slowly, it is still relatively low, even after the POR signal is released and the configuration is completed. The CONF_DONE, nCEO, and nSTATUS pins fail to respond, as the output buffer cannot flip from the state set by the hot-socketing circuit at this low voltage. Therefore, the hot-socketing circuit is removed on these configuration pins to ensure that they are able to operate during configuration. Thus, it is expected behavior for these pins to drive out during power-up and power-down sequences. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 12-4 Chapter 12: Power Requirements for Arria II GX Devices Revision History Revision History Table 12-2 shows the revision history for this document. Table 12-2. Document Revision History Date and Document Version February 2009, v1.0 Changes Made Summary of Changes Initial release. Arria II GX Device Handbook Volume 1 -- (c) February 2009 Altera Corporation Additional Information About this Handbook This handbook provides comprehensive information about the Altera(R) Arria(R) II GX family of devices. How to Contact Altera For the most up-to-date information about Altera products, see the following table. Contact (Note 1) Contact Method Address Technical support Website www.altera.com/support Technical training Website www.altera.com/training Email custrain@altera.com Altera literature services Email literature@altera.com Non-technical support (General) Email nacomp@altera.com (Software Licensing) Email authorization@altera.com Note: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions The following table shows the typographic conventions that this document uses. Visual Cue Meaning Bold Type with Initial Capital Letters Indicates command names and dialog box titles. For example, Save As dialog box. bold type Indicates directory names, project names, disk drive names, file names, file name extensions, dialog box options, software utility names, and other GUI labels. For example, \qdesigns directory, d: drive, and chiptrip.gdf file. Italic Type with Initial Capital Letters Indicates document titles. For example, AN 519: Stratix IV Design Guidelines. Italic type Indicates variables. For example, n + 1. Variable names are enclosed in angle brackets (< >). For example, <file name> and <project name>.pof file. Initial Capital Letters Indicates keyboard keys and menu names. For example, Delete key and the Options menu. "Subheading Title" Quotation marks indicate references to sections within a document and titles of Quartus II Help topics. For example, "Typographic Conventions." (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 1 Info-2 Additional Information Visual Cue Courier type Meaning Indicates signal, port, register, bit, block, and primitive names. For example, data1, tdi, and input. Active-low signals are denoted by suffix n. For example, resetn. Indicates command line commands and anything that must be typed exactly as it appears. For example, c:\qdesigns\tutorial\chiptrip.gdf. Also indicates sections of an actual file, such as a Report File, references to parts of files (for example, the AHDL keyword SUBDESIGN), and logic function names (for example, TRI). 1., 2., 3., and a., b., c., and so on. Numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure. Bullets indicate a list of items when the sequence of the items is not important. 1 The hand points to information that requires special attention. c A caution calls attention to a condition or possible situation that can damage or destroy the product or your work. w A warning calls attention to a condition or possible situation that can cause you injury. r The angled arrow instructs you to press Enter. f The feet direct you to more information about a particular topic. Arria II GX Device Handbook Volume 1 (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 2 101 Innovation Drive San Jose, CA 95134 www.altera.com AIIGX5V2-1.1 Copyright (c) 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Contents Chapter Revision Dates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix Section I. Transceiver Architecture Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-1 Chapter 1. Arria II GX Transceiver Architecture Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Transceiver Channel Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Transceiver Block Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Dynamic Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Dynamic Reconfiguration Controller Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Dynamic Reconfiguration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 PMA Controls Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 Receiver Offset Cancellation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 Transceiver Channel Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 Transceiver Port List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 CMU Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 CMU0 Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 CMU0 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 Power Down CMU0 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24 CMU0 Clock Divider Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24 CMU1 Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 Power Down CMU1 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 Transceiver Channel Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26 Transmitter Channel Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 TX Phase Compensation FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 Input Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29 Output Data Destination Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29 TX Phase Compensation FIFO Status Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30 Byte Serializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30 Single-Width Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30 8B/10B Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31 Single-Width Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31 Controlling Running Disparity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-33 Transmitter Polarity Inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-34 Transmitter Bit Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-35 Serializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-36 Transmitter Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-38 Transmitter Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-38 Programmable Output Differential Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-39 Programmable Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-39 Transmitter Output Buffer Power (VCCH ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40 Common Mode Voltage (V CM ) Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40 PCI Express (PIPE) Receiver Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40 PCI Express (PIPE) Electrical Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41 Transmitter Local Clock Divider Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41 (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 iv Contents Receiver Channel Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41 Receiver Input Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-42 Differential On-Chip Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43 Programmable Common Mode Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-44 Link Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-44 Programmable Equalization and DC Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-50 Signal Threshold Detection Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-51 Clock and Data Recovery Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-51 Lock-to-Reference Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52 Lock-to-Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-53 LTR/LTD Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-54 Deserializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-56 Word Aligner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-57 Word Aligner in Single-Width Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-58 Manual Alignment Mode Word Aligner in 8-Bit PMA-PCS Interface Modes . . . . . . . . . . . . . . . 1-58 Bit-Slip Mode Word Aligner in 8-Bit PMA-PCS Interface Modes . . . . . . . . . . . . . . . . . . . . . . . . . 1-60 Automatic Synchronization State Machine Mode Word Aligner in 10-Bit PMA-PCS Interface Mode 1-61 Manual Alignment Mode Word Aligner in 10-Bit PMA-PCS Interface Mode . . . . . . . . . . . . . . . 1-62 Bit-Slip Mode Word Aligner in 10-Bit PMA-PCS Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . 1-64 Programmable Run Length Violation Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-64 Receiver Polarity Inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-65 Receiver Bit Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-65 Deskew FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-66 Rate Match (Clock Rate Compensation) FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-68 Rate Match FIFO in PCI Express (PIPE) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-69 Rate Match FIFO in XAUI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-71 Rate Match FIFO in GIGE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-73 Rate Match FIFO in Basic Single-Width Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-74 8B/10B Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-76 8B/10B Decoder in Single-Width Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-77 Byte Deserializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-79 Byte Deserializer in Single-Width Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-79 Byte Ordering Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-80 Byte Ordering Block in Single-Width Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-80 Word-Alignment-Based Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-81 User-Controlled Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-82 Receiver Phase Compensation FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-82 Receiver Phase Compensation FIFO Error Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-84 Offset Cancellation in the Receiver Buffer and Receiver CDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-84 Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Contents v Functional Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-84 Basic Functional Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-85 Low Latency PCS Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-85 Basic Single-Width Mode Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-86 Basic Double-Width Mode Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-88 PCI Express (PIPE) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-89 PCI Express (PIPE) Mode Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-89 PCI Express (PIPE) Mode Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-91 PCI Express (PIPE) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-92 Fast Recovery Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-98 Electrical Idle Inference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-99 PCI Express Cold Reset Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-100 XAUI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-102 XAUI Mode Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-107 XGMII-To-PCS Code Conversion at the Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-107 PCS-To-XGMII Code Conversion at the Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-109 Word Aligner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-110 Deskew FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-111 Rate Match FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-113 GIGE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-114 GIGE Mode Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-117 8B/10B Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-117 Word Aligner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-119 Rate Match FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-121 SONET/SDH Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-122 SONET/SDH Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-122 SONET/SDH OC-12 Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-124 SONET/SDH OC-48 Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-124 SONET/SDH Transmission Bit Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-125 Word Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-125 OC-48 Byte Serializer and Deserializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-125 OC-48 Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-126 SDI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-126 SDI Mode Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-129 Serial RapidIO Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-130 Synchronization State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-131 Loopback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-133 Serial Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-134 Reverse Serial Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-134 Reverse Serial Pre-CDR Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-135 PCI Express (PIPE) Reverse Parallel Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-136 Calibration Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-137 Calibration Block Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-137 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-139 Input Signals to the Calibration Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-139 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-140 Chapter 2. Arria II GX Transceiver Clocking Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CMU PLL and Receiver CDR Input Reference Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . refclk0 and refclk1 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inter-Transceiver Block (ITB) Clock Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dedicated CLK Input Pins on the FPGA Global Clock Network . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Output from Left PLLs in the FPGA Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (c) March 2009 Altera Corporation 2-1 2-1 2-3 2-5 2-6 2-6 Arria II GX Device Handbook Volume 2 vi Contents Transceiver Channel Datapath Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Transmitter Channel Datapath Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Non-Bonded Channel Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Bonded Channel Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 Receiver Channel Datapath Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 Non-Bonded Channel Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 Bonded Channel Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 FPGA Fabric-Transceiver Interface Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 Input Reference Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 Phase Compensation FIFO Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28 Other Transceiver Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28 FPGA Fabric-Transmitter Interface Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 Quartus II Software-Selected Transmitter Phase Compensation FIFO Write Clock . . . . . . . . . . 2-29 User-Selected Transmitter Phase Compensation FIFO Write Clock . . . . . . . . . . . . . . . . . . . . . . . 2-37 FPGA Fabric-Receiver Interface Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42 Quartus II Software-Selected Receiver Phase Compensation FIFO Read Clock . . . . . . . . . . . . . 2-42 User-Selected Receiver Phase Compensation FIFO Read Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51 FPGA Fabric PLLs-Transceiver PLLs Cascading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-56 Dedicated Left PLL Cascade Lines Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57 FPGA Fabric PLLs-Transceiver PLLs Cascading Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-65 Chapter 3. Configuring Multiple Protocols and Data Rates Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Transceiver PLL Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Creating Transceiver Channel Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 General Requirements to Combine Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Calibration Clock and Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Sharing CMU PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Multiple Channels Sharing a CMU PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Multiple Channels Sharing Two CMU PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Combining Receiver Only Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 Combining Transmitter Channel and Receiver Channel Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Multiple Transmitter Channel and Receiver Channel Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Example 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Combining Channels Configured in Protocol Functional Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Basic x4 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Combining Channels Using the PCI Express hard IP Block with Other Channels . . . . . . . . . . . . . 3-12 Combining Transceiver Instances Using PLL Cascade Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 Combining Transceiver Instances in Multiple Transceiver Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 Example 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 Chapter 4. Reset Control and Power Down Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 User Reset and Power-Down Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Blocks Affected by Reset and Power Down Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Contents vii Transceiver Reset Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 All Supported Functional Modes Except PCI Express (PIPE) Functional Mode . . . . . . . . . . . . . . . . 4-6 Bonded Channel Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Non-Bonded Channel Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 PCI Express (PIPE) Functional Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 PCI Express (PIPE) Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 Dynamic Reconfiguration Reset Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 Reset Sequence when Using Dynamic Reconfiguration with Data Rate Division in the TX Option . . . 4-17 Reset Sequence when Using Dynamic Reconfiguration with the Channel and TX PLL select/reconfig Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 Simulation Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 Additional Information About this Handbook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info-1 How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info-1 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info-1 (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 viii Arria II GX Device Handbook Volume 2 Contents (c) March 2009 Altera Corporation Chapter Revision Dates The chapters in this book, Arria II GX Device Handbook Volume 2, were revised on the following dates. Where chapters or groups of chapters are available separately, part numbers are listed. Chapter 1 Arria II GX Transceiver Architecture Revised: March 2009 Part Number: AIIGX52001-1.1 Chapter 2 Arria II GX Transceiver Clocking Revised: February 2009 Part Number: AIIGX52002-1.0 Chapter 3 Configuring Multiple Protocols and Data Rates Revised: February 2009 Part Number: AIIGX52003-1.0 Chapter 4 Reset Control and Power Down Revised: March 2009 Part Number: AIIGX52004-1.1 (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 x Arria II GX Device Handbook Volume 2 Chapter Revision Dates (c) March 2009 Altera Corporation Section I. Transceiver Architecture This section provides information about Arria(R) II GX transceiver architecture and clocking. It also describes configuring multiple protocols, data rates, and reset control and power down in the Arria II GX device family. This section includes the following chapters: Chapter 1, Arria II GX Transceiver Architecture Chapter 2, Arria II GX Transceiver Clocking Chapter 3, Configuring Multiple Protocols and Data Rates Chapter 4, Reset Control and Power Down Revision History Refer to each chapter for its own specific revision history. For information about when each chapter was updated, refer to the Chapter Revision Dates section, which appears in this volume. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 I-2 Arria II GX Device Handbook Volume 2 Section I. Transceiver Architecture (c) March 2009 Altera Corporation 1. Arria II GX Transceiver Architecture AIIGX52001-1.1 Introduction This chapter describes the Arria (R) II GX transceiver architecture. Arria II GX FPGAs deliver a breakthrough level of system bandwidth for mainstream applications. Arria II GX devices provide up to 16 full-duplex CDR-based transceivers with physical coding sublayer (PCS) and physical medium attachment (PMA), at serial data rates between 600 Mbps and 3.75 Gbps. This chapter includes the following sections: "Transceiver Channel Locations" on page 1-2 "Transceiver Block Architecture Overview" on page 1-5 "Dynamic Reconfiguration" on page 1-6 "Transceiver Port List" on page 1-9 "CMU Blocks" on page 1-20 "Transceiver Channel Architecture" on page 1-26 "Transmitter Channel Datapath" on page 1-28 "Transmitter Local Clock Divider Block" on page 1-41 "Receiver Channel Datapath" on page 1-41 "Functional Modes" on page 1-84 "Loopback Modes" on page 1-133 "Calibration Blocks" on page 1-137 Transceiver channels are designed to support the following serial protocols: PCI Express (PIPE) Serial RapidIO (1.25 Gbps, 2.5 Gbps, 3.125 Gbps) Serial ATA (SATA)/Serial attached SCSI (SAS) (c) March 2009 Gen1 (2.5 Gbps) SATA I (1.5 Gbps) SATA II (3.0 Gbps) SAS (1.5 Gbps, 3.0 Gbps) Serial Digital Interface (SDI) HD-SDI (1.485 Gbps, 1.4835 Gbps) 3G-SDI (2.97 Gbps, 2.967 Gbps) ASI (270 Mbps) CPRI (614.4 Mbps, 1228.8 Mbps, 2457.6 Mbps, 3072 Mbps) OBSAI (768 Mbps, 1536 Mbps, 3072 Mbps) Altera Corporation Arria II GX Device Handbook Volume 2 1-2 Chapter 1: Arria II GX Transceiver Architecture Transceiver Channel Locations Gigabit Ethernet (GIGE) (1.25 Gbps) XAUI (3.125 Gbps to 3.75 Gbps for HiGig/HiGig+ support) SONET/SDH OC-3 (155 Mbps) OC-12 (622 Mbps) OC-48 (2.488 Gbps) GPON (1.244 uplink, 2.488 downlink) SerialLite II (0.6 to 3.75 Gbps) Transceiver channels also support the following highly flexible functional mode to implement proprietary protocols: Basic single-width (600 Mbps to 3.75 Gbps) Transceiver Channel Locations Arria II GX transceivers are structured into full-duplex (transmitter and receiver) four-channel groups called transceiver blocks. The total number of transceiver channels and the location of transceiver blocks varies among different device members of the Arria II GX family. Table 1-1 summarizes the total number of transceiver channels and transceiver block locations in each Arria II GX device. Table 1-1. Number of Transceiver Channels and Transceiver Block Locations in Arria II GX Devices (Part 1 of 2) Device Member Total Number of Transceiver Channels EP2AGX20CU17 Transceiver Channel Arrangement (1) 4 Four transceiver channels located in one transceiver block; GXBL0 on the left side of the device. 8 Eight transceiver channels located in two transceiver blocks; GXBL0 and GXBL1, on the left side of the device, with GXBL0 at the bottom of the device progressing up to GXBL1. EP2AGX30CU17 EP2AGX45CU17 EP2AGX65CU17 EP2AGX20CF25 EP2AGX30CF25 EP2AGX45DF25 EP2AGX65DF25 EP2AGX95DF25 EP2AGX125DF25 EP2AGX45DF29 EP2AGX65DF29 Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Transceiver Channel Locations 1-3 Table 1-1. Number of Transceiver Channels and Transceiver Block Locations in Arria II GX Devices (Part 2 of 2) Device Member Total Number of Transceiver Channels EP2AGX95EF29 Transceiver Channel Arrangement (1) 12 Twelve transceiver channels located in three transceiver blocks; GXBL0, GXBL1, and GXBL2, on the left side of the device, with GXBL0 at the bottom of the device progressing up to GXBL2. 16 Sixteen transceiver channels located in four transceiver blocks; GXBL0, GXBL1, GXBL2, and GXBL3, on the left side of the device, with GXBL0 at the bottom of the device progressing up to GXBL3. EP2AGX125EF29 EP2AGX190EF29 EP2AGX260EF29 EP2AGX95EF35 EP2AGX125EF35 EP2AGX190FF35 EP2SGX260FF35 Note to Table 1-1: (1) Arrangement of the transceivers is shown in Figure 1-1 through Figure 1-4. Figure 1-1 shows a die-top view of the four transceiver channel locations in Arria II GX devices. Figure 1-1. Arria II GX Devices with Four Transceiver Channels EP2AGX20CU17 EP2AGX30CU17 EP2AGX45CU17 EP2AGX65CU17 EP2AGX20CF25 EP2AGX30CF25 Transceiver Block GXBL0 Channel3 Channel2 Channel1 Channel0 (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-4 Chapter 1: Arria II GX Transceiver Architecture Transceiver Channel Locations Figure 1-2 shows a die-top view of the eight transceiver channel locations in Arria II GX devices. Figure 1-2. Arria II GX Devices with Eight Transceiver Channels EP2AGX45DF25 EP2AGX65DF25 EP2AGX95DF25 EP2AGX125DF25 EP2AGX45DF29 EP2AGX65DF29 Transceiver Block GXBL1 Channel3 Channel2 Channel1 Channel0 Transceiver Block GXBL0 Channel3 Channel2 Channel1 Channel0 Figure 1-3 shows a die-top view of the twelve transceiver channel locations in Arria II GX devices. Figure 1-3. Arria II GX Devices with Twelve Transceiver Channels Transceiver Block GXBL2 Channel3 Channel2 Channel1 EP2AGX95EF29 EP2AGX125EF29 EP2AGX190EF29 EP2AGX260EF29 EP2AGX95EF35 EP2AGX125EF35 Channel0 Transceiver Block GXBL1 Channel3 Channel2 Channel1 Channel0 Transceiver Block GXBL0 Channel3 Channel2 Channel1 Channel0 Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Transceiver Block Architecture Overview 1-5 Figure 1-4 shows a die-top view of the sixteen transceiver channel locations in Arria II GX devices. Figure 1-4. Arria II GX Device with Sixteen Transceiver Channels Transceiver Block GXBL3 Channel3 Channel2 EP2AGX190FF35 EP4SGX260FF35 Channel1 Channel0 Transceiver Block GXBL2 Channel3 Channel2 Channel1 Channel0 Transceiver Block GXBL1 Channel3 Channel2 Channel1 Channel0 Transceiver Block GXBL0 Channel3 Channel2 Channel1 Channel0 Transceiver Block Architecture Overview Each transceiver block has: Two clock multiplier units (CMU)--CMU0 and CMU1 provide the high-speed serial and low-speed parallel clocks to the transceiver channels Four full-duplex (transmitter and receiver) transceiver channels that support serial data rates from 600 Mbps to 3.75 Gbps Central control unit (CCU) that implements a XAUI state machine for XGMII-to-PCS code group conversion, XAUI deskew state machine, shared control signal generation block, and reset control logic (c) March 2009 Altera Corporation The shared control signal generation block provides control signals to the transceiver channels in bonded functional modes such as XAUI, PCI Express (PIPE), and Basic x4 Arria II GX Device Handbook Volume 2 1-6 Chapter 1: Arria II GX Transceiver Architecture Dynamic Reconfiguration Figure 1-5 shows a block diagram of transceiver block architecture. Figure 1-5. Top-Level View of a Transceiver Block Transceiver Block Transceiver Channel 3 Transceiver Channel 2 Transceiver Block GXBL1 Channel3 Channel2 CMU1 Block Central Control Unit (CCU) Channel1 Channel0 Transceiver Block GXBL0 CMU0 Block Channel3 Channel2 Channel1 Channel0 Transceiver Channel 1 Transceiver Channel 0 1 For architecture details of CMU blocks and transceiver channels, refer to "CMU Blocks" on page 1-20 and "Transceiver Channel Architecture" on page 1-26. Dynamic Reconfiguration Dynamic reconfiguration is a unique feature that enables your end system's high-speed I/O frequency to be reconfigured in your system without reconfiguring the FPGA. For hot pluggable or open standard systems, this feature allows you to support multiple data rates or standards without reconfiguring the system. For all systems, it allows you to make changes to the bit error rate to compensate in-system for the effects of process and temperature. Each transceiver channel has multiple physical medium attachment controls that you can program to achieve the desired bit error ratio (BER) for your system. When you enable the dynamic reconfiguration feature, you can reconfigure dynamically without powering down other transceiver channels or the FPGA fabric of the device: Transmit and receive analog settings Transmit data rate in multiples of 1, 2, and 4 One channel at a time Channel and clock multiplier unit PLL CMU PLL only Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Dynamic Reconfiguration 1-7 Dynamic Reconfiguration Controller Architecture The dynamic reconfiguration controller is a soft IP which uses FPGA-fabric resources. You can use only one controller per transceiver block. You cannot use the dynamic reconfiguration controller to control multiple Arria II GX devices or any off-chip interfaces. Figure 1-6 shows the conceptual view of the dynamic reconfiguration controller architecture. Figure 1-6. Block Diagram of the Dynamic Reconfiguration Controller ALTGX_RECONFIG MegaWizard Plug-In Manager Instance reconfig_clk read write_all reconfig_fromgxb[] PMA controls reconfig inputs (1) reconfig_data[15:0] reset_reconfig_address PMA controls reconfiguration logic CMU PLL Reconfig control logic reconfig_togxb[3:0] Channel and CMU PLL Reconfiguration control logic logical_tx_pll_sel logical_tx_pll_sel_en Channel and CMU PLL Reconfiguration control logic data valid addr busy Parallel to Serial Converter Address Translation error data rate_switch_ctrl[1:0] Dynamic Rate Switch Offset Cancellation control logic rate_switch_out rx_tx_duplex_sel[] reconfig_address_out logical_channel_address[] reconfig_address_en reconfig_mode_sel[2:0] channel_reconfig_done Note to Figure 1-6: (1) The PMA control ports consist of the VOD controls, pre-emphasis controls, DC gain controls, and manual equalization controls. The dynamic reconfiguration controller is comprised of the following control logic modules: (c) March 2009 PMA controls reconfiguration control logic Channel reconfiguration with TX PLL select/reconfig control logic CMU PLL reconfiguration control logic Channel and CMU PLL reconfiguration control logic Channel reconfiguration with TX PLL select control logic Data rate division control logic to the TX local divider Offset cancellation control logic for receiver channels Altera Corporation Arria II GX Device Handbook Volume 2 1-8 Chapter 1: Arria II GX Transceiver Architecture Dynamic Reconfiguration The dynamic reconfiguration controller reads from its control inputs or from a Memory Initialization File (.mif) file. For PMA controls reconfiguration and data rate division using control logic, the input to the controller is translated to address and data bus within. The address and data bus are then converted into serial data and forwarded to the selected transceiver channel. When a .mif file is used for reconfiguration, the dynamic reconfiguration controller receives 16-bit words from the .mif that you generate and sends this information to the transceiver channel selected. 1 For more information, refer to AN 558: Implementing Dynamic Reconfiguration in Arria II GX Devices. Dynamic Reconfiguration Modes The different modes of dynamic reconfiguration are: PMA controls reconfiguration Receiver offset cancellation Transceiver channel reconfiguration PMA Controls Reconfiguration You can dynamically reconfigure the following PMA controls: Pre-emphasis settings Equalization settings DC gain settings Voltage output differential (V OD) settings Receiver Offset Cancellation Variations in process create offsets in analog circuit voltages, pushing them outside the expected range. The Arria II GX device provides an offset cancellation circuit per receiver channel to counter the offset variations due to process. Calibration of the offset cancellation circuit is done at power-up. The receiver buffer and receiver clock data recovery (CDR) require offset calibration. Offset cancellation is automatically executed once every time the device is powered on. The control logic for offset cancellation is integrated into the dynamic reconfiguration controller. The offset cancellation for receiver channels option is automatically enabled in both the ALTGX and ALTGX_RECONFIG MegaWizardTM Plug-In Managers for Receiver and Transmitter and Receiver only configurations. It is not available for Transmitter only configurations. For Receiver and Transmitter and Receiver only configurations, you must connect the ALTGX_RECONFIG instance to the ALTGX instances with receiver channels in your design. You must connect the reconfig_fromgxb, reconfig_togxb, and necessary clock signals to both the ALTGX_RECONFIG and ALTGX (with receiver channels) instances. 1 For proper device operation, you must always connect the ALTGX_RECONFIG and ALTGX (with receiver channels) instances. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Transceiver Port List f 1-9 Due to the offset cancellation process, the transceiver reset sequence has changed. For more information, refer to the Reset Control and Power Down chapter in volume 2 of the Arria II GX Device Handbook. Transceiver Channel Reconfiguration For transceiver channels, dynamic reconfiguration involves the reconfiguration of the following: Data Rate Reconfiguration. This can be achieved by: Switching between two TX PLLs set to different data rates and reconfiguring the RX PLLS Reconfiguring the local dividers in the transmit side Reconfiguring the CMU PLL Functional Mode Reconfiguration When reconfiguring data rates, ensure that the functional mode of the transceiver channel supports the reconfigured data rate. When reconfiguring the functional mode, ensure that the various clocks involved support the transition. f For more information, refer to AN 558: Implementing Dynamic Reconfiguration in Arria II GX Devices. Transceiver Port List You instantiate the Arria II GX transceivers using the ALTGX megafunction instance in the Quartus (R) II MegaWizard Plug-In Manager. The ALTGX megafunction instance allows you to configure the transceivers for your intended protocol and select optional control and status ports to and from the instantiated transceiver channels. Table 1-2 provides a description of all the ALTGX megafunction ports. Table 1-2. Arria II GX ALTGX Megafunction Ports (Part 1 of 12) Port Name Input/Output Description Scope Clock Multiplier Unit (CMU) pll_inclk Input Input reference clock for the CMU phase-locked loop (PLL). Transceiver block pll_locked Output CMU PLL lock indicator. A high level indicates that the CMU PLL is locked to the input reference clock; a low level indicates that the CMU PLL is not locked to the input reference clock. Transceiver block Asynchronous signal. pll_powerdown Input CMU PLL power down. When asserted high, the CMU PLL is powered down. When de-asserted low, the CMU PLL is active and locks to the input reference clock. Transceiver block Note: Assertion of the pll_powerdown signal does not power down the refclk buffers. Asynchronous signal. The minimum pulse-width is 1 s (pending characterization). (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-10 Chapter 1: Arria II GX Transceiver Architecture Transceiver Port List Table 1-2. Arria II GX ALTGX Megafunction Ports (Part 2 of 12) Port Name coreclkout Input/Output Description Scope Output FPGA fabric-transceiver interface clock. Generated by the CMU0 clock divider in the transceiver block in x4 bonded channel configurations. Generated by the CMU0 clock divider in the master transceiver block in x8 bonded channel configurations. Not available in non-bonded channel configurations. Transceiver block This clock is used to clock the write port of the transmitter phase compensation FIFOs in all bonded channels. Use this clock signal to clock parallel data tx_datain from the FPGA fabric into the transmitter phase compensation FIFO of all bonded channels. This clock is used to clock the read port of the receiver phase compensation FIFOs in all bonded channels with rate match FIFO enabled. Use this signal to clock parallel data rx_dataout from the receiver phase compensation FIFOs of all bonded channels (with rate match FIFO enabled) into the FPGA fabric. Receiver Physical Coding Sublayer (PCS) Ports Word Aligner rx_enapatternalign Input Channel Manual word alignment enable control. Enables word aligner configured in manual alignment mode to align to the word alignment pattern. In single-width modes (except SONET/SDH OC12 and OC48), this signal is level-sensitive. When high, the word aligner re-aligns if the word alignment pattern appears in a new word boundary. Asynchronous signal. The minimum pulse-width is 2 recovered clock cycles. rx_patterndetect Output Word alignment pattern detect indicator. A high level indicates that the word alignment pattern is found on the current word boundary. The width of this signal depends on the channel width shown below: Channel Width Arria II GX Device Handbook Volume 2 Channel rx_patterndetect width 8/10 1 16/20 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Transceiver Port List 1-11 Table 1-2. Arria II GX ALTGX Megafunction Ports (Part 3 of 12) Port Name rx_syncstatus Input/Output Description Scope Output Word alignment synchronization status indicator. For word aligner in automatic synchronization state machine mode. This signal is driven high if the conditions required to remain in synchronization are met. It is driven low if the conditions required to lose synchronization are met. Channel For word aligner in manual alignment mode, the behavior of this signal depends on whether the transceiver is configured in single-width mode. For more information, refer to "Word Aligner in SingleWidth Mode" on page 1-58. This signal is not available for word aligner in bit-slip mode. The width of this signal depends on the channel width shown below: Channel Width rx_bitslip Input rx_syncstatus width 8/10 1 16/20 2 Bit-slip control for word aligner configured in bit-slip mode. At every rising edge of this signal, word aligner slips one bit into the received data stream, effectively shifting the word boundary by 1 bit. Channel Asynchronous signal. The minimum pulse-width is 2 recovered clock cycles. rx_ bitslipboundary selectout rx_ala2size Output Channel Asynchronous signal. Input Output rx_rlv Indicates number of bits slipped in the word aligner when word aligner is configured in manual mode. Available only in SONET OC-12 and OC-48 modes to select between one of the following two word alignment options: 0 - 16-bit A1A2 1 - 32-bit A1A1A2A2 Run-length violation indicator. A high pulse is driven when the number of consecutive 1s or 0s in the received data stream exceeds the programmed run length violation threshold. Channel Channel Asynchronous signal. Driven for a minimum of 2 recovered clock cycles in configurations without byte serializer and a minimum of 3 recovered clock cycles in configurations with byte serializer. rx_invpolarity Input Generic receiver polarity inversion control. Useful feature for correcting situations where the positive and negative signals of the differential serial link are accidentally swapped during board layout. When asserted high the polarity of every bit of the 8-bit or 10-bit input data word to the word aligner gets inverted. Channel Asynchronous signal. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-12 Chapter 1: Arria II GX Transceiver Architecture Transceiver Port List Table 1-2. Arria II GX ALTGX Megafunction Ports (Part 4 of 12) Port Name rx_revbitorderwa Input/Output Input Description Scope Receiver bit reversal control. Available only in Basic single-width mode with word aligner configured in bit-slip mode. Useful feature where the link transmission order is MSB to LSB. Channel When asserted high in Basic single-width mode, the 8bit or 10-bit data D[7:0] or D[9:0] at the output of the word aligner gets rewired to D[0:7] or D[0:9], respectively. Asynchronous signal. Deskew FIFO rx_channelaligned Output 10-gigabit attachment unit interface (XAUI) deskew FIFO channel aligned indicator. Transceiver block Available only in XAUI mode. A high level indicates that the XAUI deskew state machine is either in ALIGN_ACQUIRED_1, ALIGN_ACQUIRED_2, ALIGN_ACQUIRED_3, or ALIGN_ACQUIRED_4 state, as specified in the PCS deskew state diagram in IEEE P802.3ae specification. A low level indicates that the XAUI deskew state machine is either in LOSS_OF_ALIGNMENT, ALIGN_DETECT_1, ALIGN_DETECT_2, or ALIGN_DETECT_3 state, as specified in the PCS deskew state diagram in IEEE P802.3ae specification. Rate Match (Clock Rate Compensation) FIFO rx_rmfifodata inserted Output Rate match FIFO insertion status indicator. A high level indicates that the rate match pattern byte was inserted to compensate for the parts-per-million (PPM) difference in reference clock frequencies between the upstream transmitter and the local receiver. Channel rx_rmfifodata deleted Output Rate match FIFO deletion status indicator. A high level indicates that the rate match pattern byte was deleted to compensate for the PPM difference in reference clock frequencies between the upstream transmitter and the local receiver. Channel rx_rmfifofull Output Rate match FIFO full status indicator. A high level indicates that the rate match FIFO is full. Channel Asynchronous signal. Driven for a minimum of 2 recovered clock cycles in configurations without byte serializer and a minimum of 3 recovered clock cycles in configurations with byte serializer. rx_rmfifoempty Output Rate match FIFO empty status indicator. A high level indicates that the rate match FIFO is empty. Channel Asynchronous signal. Driven for a minimum of 2 recovered clock cycles in configurations without byte serializer and a minimum of 3 recovered clock cycles in configurations with byte serializer. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Transceiver Port List 1-13 Table 1-2. Arria II GX ALTGX Megafunction Ports (Part 5 of 12) Port Name Input/Output Description Scope 8B/10B Decoder rx_ctrldetect Output Channel Receiver control code indicator. Available in configurations with 8B/10B decoder. A high level indicates that the associated received code group is a control (/Kx.y/) code group. A low level indicates that the associated received code group is a data (/Dx.y/) code group. The width of this signal depends on the channel width shown below: Channel Width rx_errdetect Output rx_ctrldetect width 8 1 16 2 8B/10B code group violation or disparity error indicator. Channel Available in configurations with 8B/10B decoder. A high level indicates that a code group violation or disparity error was detected on the associated received code group. Use with the rx_disperr signal to differentiate between a code group violation and/or a disparity error as follows: [rx_errdetect: rx_disperr] 2'b00 - no error 2'b10 - code group violation 2'b11 - disparity error or both The width of this signal depends on the channel width shown below: Channel Width rx_disperr Output rx_errdetect width 8 1 16 2 Channel 8B/10B disparity error indicator port. Available in configurations with 8B/10B decoder. A high level indicates that a disparity error was detected on the associated received code group. The width of this signal depends on the channel width shown below: Channel Width (c) March 2009 Altera Corporation rx_disperr width 8 1 16 2 Arria II GX Device Handbook Volume 2 1-14 Chapter 1: Arria II GX Transceiver Architecture Transceiver Port List Table 1-2. Arria II GX ALTGX Megafunction Ports (Part 6 of 12) Port Name rx_runningdisp Input/Output Output Description Scope Channel 8B/10B running disparity indicator. Available in configurations with the 8B/10B decoder. A high level indicates that data on the rx_dataout port was received with a negative running disparity. A low level indicates that data on the rx_dataout port was received with a positive running disparity. The width of this signal depends on the channel width shown below: Channel Width rx_runningdisp width 8 1 16 2 Byte Ordering Block rx_enabyteord Input Enable byte ordering control. Available in configurations with byte ordering block enabled. The byte ordering block is rising-edge sensitive to this signal. A low-to-high transition triggers the byte ordering block to restart the byte ordering operation. Channel Asynchronous signal. rx_ byteorderalign status Output Byte ordering status indicator. Available in configurations with byte ordering block enabled. A high level indicates that the byte ordering block has detected the programmed byte ordering pattern in the LSByte of the received data from the byte deserializer. Channel Receiver Phase Compensation FIFO rx_dataout Output Parallel data output from the receiver to the FPGA fabric. The bus width depends on the channel width multiplied by the number of channels per instance. rx_clkout Output Recovered clock from the receiver channel. Available only when the rate match FIFO is not used in the receiver datapath. Channel rx_coreclk Input Optional read clock port for the receiver phase compensation FIFO. If not selected, the Quartus II software automatically selects rx_clkout/tx_clkout/coreclkout as the read clock for the receiver phase compensation FIFO. If selected, you must drive this port with a clock that has 0 PPM difference with respect to rx_clkout/tx_clkout/ coreclkout. Channel Output Receiver phase compensation FIFO full or empty indicator. A high level indicates that the receiver phase compensation FIFO is either full or empty. Channel rx_phase_comp_fifo_ error Receiver Physical Media Attachment (PMA) rx_datain Input Receiver serial data input port. Channel rx_cruclk Input Input reference clock for the receiver clock and data recovery (CDR). Channel Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Transceiver Port List 1-15 Table 1-2. Arria II GX ALTGX Megafunction Ports (Part 7 of 12) Port Name rx_pll_locked Input/Output Description Scope Output Receiver CDR lock-to-reference (LTR) indicator. A high level indicates that the receiver CDR is locked to the input reference clock. A low level indicates that the receiver CDR is not locked to the input reference clock. Channel Asynchronous signal. rx_freqlocked Output Receiver CDR lock mode indicator. A high level indicates that the receiver CDR is in lock-to-data (LTD) mode. A low level indicates that the receiver CDR is in lock-toreference mode. Channel Asynchronous signal. rx_locktodata Input Receiver CDR lock-to-data mode control signal. When asserted high, the receiver CDR is forced to lock-to-data mode. When de-asserted low, the receiver CDR lock mode depends on the rx_locktorefclk signal level. Channel rx_locktorefclk Input Receiver CDR lock-to-reference mode control signal. Channel The rx_locktorefclk signal along with rx_locktodata signal controls whether the receiver CDR is in lock-to-reference or lock-to-data mode, as follows: rx_locktodata/ rx_locktorefclk 0/0 - receiver CDR is in automatic mode 0/1 - receiver CDR is in LTR mode 1/x - receiver CDR is in LTD mode Asynchronous Signal. rx_signaldetect Output Signal threshold detect indicator. Available only in PCI Express (PIPE) mode. A high level indicates that the signal present at the receiver input buffer is above the programmed signal detection threshold value. Channel If the electrical idle inference block is disabled in PCI Express (PIPE) mode, the rx_signaldetect signal is inverted and driven on the pipeelecidle port. Asynchronous signal. rx_seriallpbken Input Serial loopback control port. Channel 0 - normal data path, no serial loopback 1 - serial loopback Transmitter Physical Coding Sublayer Ports Transmitter Phase Compensation FIFO tx_datain (c) March 2009 Altera Corporation Input Parallel data input from the FPGA fabric to the transmitter. The bus width depends on the channel width multiplied by the number of channels per instance. Channel Arria II GX Device Handbook Volume 2 1-16 Chapter 1: Arria II GX Transceiver Architecture Transceiver Port List Table 1-2. Arria II GX ALTGX Megafunction Ports (Part 8 of 12) Port Name Input/Output Description Scope tx_clkout Output FPGA fabric-transceiver interface clock. Each channel has a tx_clkout signal in non-bonded channel configurations. Use this clock signal to clock the parallel data tx_datain from the FPGA fabric into the transmitter. This signal is not available in bonded channel configurations. Channel tx_coreclk Input Optional write clock port for the transmitter phase compensation FIFO. If not selected, the Quartus II software automatically selects tx_clkout/coreclkout as the write clock for the transmitter phase compensation FIFO. If selected, you must drive this port with a clock that is frequency locked to tx_clkout/coreclkout. Channel Transmitter phase compensation FIFO full or empty indicator. A high level indicates that the transmitter phase compensation FIFO is either full or empty. Channel 8B/10B encoder /Kx.y/ or /Dx.y/ control. Channel tx_phase_comp_fifo_ error Output 8B/10B Encoder tx_ctrlenable Input When asserted high, the 8B/10B encoder encodes the data on the tx_datain port as a /Kx.y/ control code group. When de-asserted low, it encodes the data on the tx_datain port as a /Dx.y/ data code group. The width of this signal depends on the channel width shown below: Channel Width tx_forcedisp Input tx_ctrlenable 8 1 16 2 8B/10B encoder force disparity control. When asserted high, it forces the 8B/10B encoder to encode the data on the tx_datain port with a positive or negative disparity, depending on the tx_dispval signal level. When de-asserted low, the 8B/10B encoder encodes the data on the tx_datain port according to the 8B/10B running disparity rules. The width of this signal depends on the channel width shown below: Channel Channel Width tx_forcedisp Arria II GX Device Handbook Volume 2 8 1 16 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Transceiver Port List 1-17 Table 1-2. Arria II GX ALTGX Megafunction Ports (Part 9 of 12) Port Name tx_dispval Input/Output Description Scope Input 8B/10B encoder force disparity value. A high level on the tx_dispval signal when the tx_forcedisp signal is asserted high forces the 8B/10B encoder to encode the data on the tx_datain port with a negative starting running disparity. A low level on the tx_dispval signal when the tx_forcedisp signal is asserted high forces the 8B/10B encoder to encode the data on the tx_datain port with a positive starting running disparity. The width of this signal depends on the channel width shown below: Channel Channel Width tx_dispval tx_invpolarity Input 8 1 16 2 Transmitter polarity inversion control. Useful feature for correcting situations where the positive and negative signals of the differential serial link are accidentally swapped during board layout. When asserted high the polarity of every bit of the 8-bit or 10-bit input data to the serializer gets inverted. Channel Asynchronous signal. tx_ bitslipboundary select Input Indicates the number of bits to slip at the transmitter for word alignment at the receiver. Channel Transmitter serial data output port. Channel Input 125-MHz clock for receiver detect and offset cancellation in PCI Express (PIPE) mode. Channel Input The width of this signal is determined by the value you set in the What is the number of channels controlled by the reconfig controller? option in the Reconfiguration settings screen. Device Transmitter Physical Media Attachment tx_dataout fixedclk Output Reconfiguration Block reconfig_fromgxb For more information, refer to AN 558: Implementing Dynamic Reconfiguration in Arria II GX Devices. reconfig_togxb[3:0] Output The width of this signal is fixed to four bits. It is independent of the value you set in the What is the number of channels controlled by the reconfig controller? option in the Reconfiguration settings screen. Device For more information, refer to AN 558: Implementing Dynamic Reconfiguration in Arria II GX Devices. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-18 Chapter 1: Arria II GX Transceiver Architecture Transceiver Port List Table 1-2. Arria II GX ALTGX Megafunction Ports (Part 10 of 12) Port Name reconfig_clk Input/Output Input Description Scope Dynamic reconfiguration clock. This clock is also used for offset cancellation in all modes except PCI Express (PIPE) mode. Channel The frequency range of this clock is 2.5 MHz to 50 MHz when the transceiver channel is configured in Transmitter only mode. The frequency range of this clock is 37.5 MHz to 50 MHz when the transciever channel is configured in Receiver only or Receiver and Tranmitter mode. PIPE Interface (Available only in PCI Express [PIPE] functional mode) powerdn Input PCI Express (PIPE) power state control. Functionally equivalent to the PowerDown[1:0] signal defined in PIPE specification revision 2.00. The width of this signal is 2 bits and is encoded as follows: 2'b00: P0 - Normal Operation 2'b01: P0s - Low Recovery Time Latency, Low Power State 2'b10: P1 - Longer Recovery Time Latency, Lower Power State 2'b11: P2 - Lowest Power State Channel tx_ forcedispcompliance Input Force 8B/10B encoder to encode with a negative running disparity. Functionally equivalent to the TxCompliance signal defined in PIPE specification revision 2.00. Must be asserted high only when transmitting the first byte of the PCI Express Compliance Pattern to force the 8B/10B encode with a negative running disparity, as required by the PCI Express (PIPE) protocol. Channel tx_forceelecidle Input Force transmitter buffer to PCI Express (PIPE) electrical idle signal levels. Functionally equivalent to the TxElecIdle signal defined in PIPE specification revision 2.00. Channel pipe8b10binv polarity Input PCI Express (PIPE) polarity inversion control. Functionally equivalent to the RxPolarity signal defined in PIPE specification revision 2.00. Available only in PCI Express (PIPE) mode. When asserted high, the polarity of every bit of the 10-bit input data to the 8B/10B decoder gets inverted. Channel Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Transceiver Port List 1-19 Table 1-2. Arria II GX ALTGX Megafunction Ports (Part 11 of 12) Port Name Input/Output Description Scope tx_detectrxloopback Input Receiver detect or PCI Express (PIPE) loopback control. Functionally equivalent to the TxDetectRx/Loopback signal defined in PIPE specification revision 2.00. When asserted high in P1 power state with the tx_forceelecidle signal asserted, the transmitter buffer begins the receiver detection operation. Once the receiver detect completion is indicated on the pipephydonestatus port, this signal must be de-asserted. Channel When asserted high in P0 power state with the tx_forceelecidle signal de-asserted, the transceiver datapath gets dynamically configured to support parallel loopback as described in "PCI Express (PIPE) Reverse Parallel Loopback" on page 1-136. pipestatus Output PCI Express (PIPE) receiver status port. Functionally equivalent to the RxStatus[2:0] signal defined in PIPE specification revision 2.00. The width of this signal is 3 bits per channel. The encoding of receiver status on the pipestatus port is as follows: 000 - Received data OK 001 - 1 skip added 010 - 1 skip removed 011 - Receiver detected 100 - 8B/10B decoder error 101 - Elastic buffer overflow 110 - Elastic buffer underflow 111 - Received disparity error. Channel pipephydonestatus Output PHY function completion indicator. Functionally equivalent to the PhyStatus signal defined in PIPE specification revision 2.00. Asserted high for one parallel clock cycle to communicate completion of several PHY functions, such as power state transition and receiver detection. Channel rx_pipedatavalid Output Valid data and control on the rx_dataout and rx_ctrldetect ports indicator. Functionally equivalent to the RxValid signal defined in PIPE specification revision 2.00. Channel pipeelecidle Output Electrical idle detected or inferred at the receiver indicator. Functionally equivalent to the RxElecIdle signal defined in PIPE specification revision 2.00. If the electrical idle inference block is enabled, it drives this signal high when it infers an electrical idle condition, as described in "Electrical Idle Inference" on page 1-99. Otherwise, it drives this signal low. If the electrical idle inference block is disabled, the rx_signaldetect signal from the signal detect circuitry in the receiver buffer is inverted and driven on this port. Channel Asynchronous Signal. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-20 Chapter 1: Arria II GX Transceiver Architecture CMU Blocks Table 1-2. Arria II GX ALTGX Megafunction Ports (Part 12 of 12) Port Name Input/Output Description Scope Input Transceiver block power down. When asserted high, all digital and analog circuitry in the PCS, PMA, CMU channels, and the CCU of the transceiver block gets powered down. Transceiver block Reset and Power Down gxb_powerdown Note that asserting the gxb_powerdown signal does not power down the refclk buffers. Asynchronous signal. The minimum pulse width is 1 us (pending characterization). Input rx_digitalreset Receiver PCS reset. When asserted high, the receiver PCS blocks get reset. The minimum pulse width is 2 parallel clock cycles. Channel Refer to the Reset Control and Power Down chapter in volume 2 of the Arria II GX Device Handbook for more details. Input rx_analogreset Receiver PMA reset. When asserted high, analog circuitry in the receiver PMA gets reset. The minimum pulse width is 2 parallel clock cycles. Channel Refer to the Reset Control and Power Down chapter in volume 2 of the Arria II GX Device Handbook for more details. Input tx_digitalreset Transmitter PCS reset. When asserted high, the transmitter PCS blocks get reset. The minimum pulse width is 2 parallel clock cycles. Channel Refer to the Reset Control and Power Down chapter in volume 2 of the Arria II GX Device Handbook for more details. Calibration Block cal_blk_clk Input Clock for transceiver calibration blocks. Device cal_blk_powerdown Input Calibration block power down control. Device CMU Blocks Each transceiver block contains two CMU blocks--CMU0 and CMU1. Each CMU block contains a CMU PLL that provides clocks to all the transmitter channels in the same transceiver block. The CMU0 block has additional capabilities to support bonded protocol functional modes such as Basic x4, XAUI, and PCI Express (PIPE). You can select these functional modes from the ALTGX MegaWizard Plug-In Manager. You can enable Basic x4 functional mode in the ALTGX MegaWizard PlugIn Manager by selecting the x4 option in Basic mode. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture CMU Blocks 1-21 Figure 1-7 shows a top-level block diagram of the CMU channels in a transceiver block. Figure 1-7. Top-Level Diagram of CMU Channels in a Transceiver Block Arria II GX Transceiver Block To Transmitter PMA High-Speed Serial Clock Low-Speed Parallel Clock Local Clock Divider Block To Transmitter PCS Transmitter Channel 2 Transmitter Channel 3 Input Reference Clocks (2) CMU1 Block CMU1 PLL High-Speed Clock CMU0 PLL High-Speed Clock Input Reference Clocks (2) CMU0 Block High-Speed SERIAL Clock (1) Low-Speed PARALLEL Clock (1) To Transmitter PMA High-Speed Serial Clock Low-Speed Parallel Clock Local Clock Divider Block To Transmitter PCS Transmitter Channel 0 Transmitter Channel 1 Notes to Figure 1-7: (1) Clocks provided to support bonded channel functional mode. (2) For more information, refer to the Arria II GX Transceiver Clocking chapter in volume 2 of the Arria II GX Device Handbook. CMU0 Block The CMU0 block, shown in Figure 1-8, contains the following blocks: (c) March 2009 CMU0 PLL CMU0 clock divider Altera Corporation Arria II GX Device Handbook Volume 2 1-22 Chapter 1: Arria II GX Transceiver Architecture CMU Blocks Figure 1-8. Diagram of CMU0 Block pll_locked CMU0 Block pll_powerdown CMU0 PLL High-Speed Clock (1) PLL Cascade Clock CMU0 PLL input reference clock Global Clock Line Dedicated refclk0 High-Speed Serial Clock for Bonded Modes (2) CMU0 PLL CMU1 PLL High-Speed Clock Dedicated refclk1 CMU0 Clock Divider Low-Speed Parallel Clock for Bonded Modes ITB Clock Lines 6 Notes to Figure 1-8: (1) In non-bonded functional modes (for example, GIGE functional mode), the transmitter channel uses the transmitter local clock divider to divide this high-speed clock output to provide clocks for its PMA and PCS blocks. (2) Used in XAUI, Basic x4, and PCI Express (PIPE) x4 functional modes. In PCI Express (PIPE) x8 functional mode, only the CMU0 channel of the master transceiver block provides clock output to all eight transceiver channels configured in PCI Express (PIPE) functional mode. CMU0 PLL Figure 1-9 shows the block diagram of the CMU0 PLL. Figure 1-9. Diagram of the CMU0 PLL CMU0 PLL /M PLL Cascade Clock Global Clock Line Dedicated refclk0 CMU0 PLL Input Reference Clock /1, /2, /4, /8 PFD Charge Pump + Loop Filter VCO /L CMU0 High-Speed Clock Dedicated refclk1 ITB Clock Lines (1) 6 Note to Figure 1-9: (1) The ITB clock lines shown are the maximum value. The actual number of ITB lines in your device depends on the number of transceiver blocks on one side of the device. f For more information about input reference clocks, refer to the "CMU PLL and Receiver CDR Input Reference Clocks" section of the Arria II GX Transceiver Clocking chapter in volume 2 of the Arria II GX Device Handbook. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture CMU Blocks 1-23 You can select the input reference clock to the CMU0 PLL from multiple clock sources. The various clock sources are: PLL cascade clock--the PLL cascade clock is the output from the general purpose PLLs in the FPGA fabric Global clock line--the input reference clock from the dedicated CLK pins are connected to the global clock line refclk0--dedicated refclk in the transceiver block refclk1--dedicated refclk in the transceiver block Inter transceiver block (ITB) lines--the ITB lines connect the refclk0 and refclk1 of all other transceiver blocks on the same side of the device. The CMU0 PLL generates the high-speed clock from the input reference clock. The phase frequency detector (PFD) tracks the voltage-controlled oscillator (VCO) output with the input reference clock. The input frequency range of the PFD is 50 to 325 MHz. f For more information about transceiver input reference clocks, refer to the Arria II GX Transceiver Clocking chapter in volume 2 of the Arria II GX Device Handbook. The VCO in the CMU0 PLL is half rate and runs at half the serial data rate. The CMU0 PLL uses two multiplier blocks (/M and /L) in the feedback path (shown in Figure 1-9) to generate the high-speed clock needed to support a native data rate range of 600 Mbps to 3.75 Gbps. Table 1-3 lists the available /M and /L settings. 1 f The Quartus II software automatically selects the /M and /L settings based on the input reference clock frequency and serial data rate. Each CMU PLL (CMU0 PLL and CMU1 PLL) has a dedicated pll_locked signal that gets asserted to indicate that the CMU PLL is locked to the input reference clock. You can use the pll_locked signal in your transceiver reset sequence as described in the Reset Control and Power Down chapter in volume 2 of the Arria II GX Device Handbook. Table 1-3. Multiplier Block Settings in the CMU0 PLL Multiplier Block Available Values /M 1, 4, 5, 8, 10,16, 20, 25 /L 1, 2, 4 PLL Bandwidth Setting You can program the PLL bandwidth setting using the ALTGX MegaWizard Plug-In Manager. The bandwidth of a PLL is the measure of its ability to track input clock and jitter. It is determined by the -3 dB frequency of the closed-loop gain of the PLL. There are three bandwidth settings: high, medium, and low. (c) March 2009 The high bandwidth setting filters out internal noise from the VCO because it tracks the input clock above the frequency of the internal VCO noise. Altera Corporation Arria II GX Device Handbook Volume 2 1-24 Chapter 1: Arria II GX Transceiver Architecture CMU Blocks With the low bandwidth setting, if the noise on the input reference clock is greater than the internal noise of the VCO, the PLL filters out the noise above the -3 dB frequency of the closed-loop gain of the PLL. The medium bandwidth setting is a compromise between the high and low settings. The -3 dB frequencies for these settings can vary because of the non-linear nature and frequency dependencies of the circuit. Power Down CMU0 PLL You can power down the CMU0 PLL by asserting the pll_powerdown signal. f For more information about recommended reset sequences, refer to the Reset Control and Power Down chapter in volume 2 of the Arria II GX Device Handbook. CMU0 Clock Divider Block The high-speed clock output from the CMU0 PLL is forwarded to two clock divider blocks: the CMU0 clock divider block and the transmitter channel local clock divider block. The CMU0 clock divider block is used only in bonded channel functional modes. In all non-bonded functional modes (example GIGE functional mode), the local clock divider block divides the high-speed clock to provide clocks for its PCS and PMA blocks. This section only discusses the CMU0 clock divider block. f For more information about the local clock divider block, refer to the "Transceiver Channel Datapath Clocking" section in the Arria II GX Transceiver Clocking chapter in volume 2 of the Arria II GX Device Handbook. You can configure the CMU0 clock divider block, shown in Figure 1-10, to select the high-speed clock output from the CMU0 PLL or CMU1 PLL. Figure 1-10. Diagram of the CMU0 Clock Divider Block Low-Speed Parallel Clock for Transmitter Channel PCS (for Bonded Modes) CMU0 Clock Divider Block CMU0 High-Speed Clock Output /N (1, 2, 4) CMU1 High-Speed Clock Output /S (4, 5, 8, 10) coreclkout to FPGA Fabric (for Bonded Modes) /2 High-Speed Serial Clock (for Bonded Modes) High-Speed Serial Clock Generation The /N divider receives the high-speed clock output from one of the CMU PLLs and produces a high-speed serial clock. This high-speed serial clock is used for bonded functional modes such as Basic x4, XAUI, and PCI Express (PIPE) x4 configurations. In XAUI, PCI Express (PIPE) x4 mode, and Basic x4 modes, the high-speed serial clock is provided to all the transmitter channels in the transceiver block. In PCI Express (PIPE) x8 mode, only the CMU0 clock divider of the master transceiver block provides the high-speed serial clock to all eight channels. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture CMU Blocks 1-25 In PCI Express (PIPE) x1 mode, the CMU0 clock divider does NOT provide high-speed serial clock. Instead, the local clock divider block in the transmitter channel receives the CMU0 PLL or CMU1 PLL high-speed clock output and generates the high-speed serial clock to its serializer. Low-Speed Parallel Clock Generation The /S divider receives the clock output from the /N divider and generates the low-speed parallel clock for the PCS block of all transmitter channels and coreclkout for the FPGA fabric. If the byte serializer block is enabled in the bonded channel modes, the /S divider output is divided by the /2 divider and sent out as coreclkout to the FPGA fabric. The Quartus II software automatically selects the /S values based on the deserialization width setting (single-width mode) that you select in the ALTGX MegaWizard Plug-In Manager. 1 The Quartus II software automatically selects all the divider settings based on the input clock frequency, data rate, deserialization width, and channel width settings. The deserialization default width setting for Arria II GX devices is single-width mode and cannot be changed. CMU1 Block The CMU1 block shown in Figure 1-11 contains the CMU1 PLL that provides the high-speed clock to the transmitter channels in the transceiver block. The CMU1 PLL is similar to the CMU0 PLL. The functionality of the CMU0 PLL is discussed in "CMU0 PLL" on page 1-22. Figure 1-11. CMU1 Block (Grayed Area Shows the Inactive Block) pll_locked CMU1 PLL High-Speed Clock pll_powerdown PLL Cascade Clock Global Clock Line Dedicated refclk0 CMU1 PLL Input Reference Clock Dedicated refclk1 CMU1 PLL CMU1 Clock Divider ITB Clock Lines 6 CMU1 Block The CMU1 PLL generates the high-speed clock that is only used in non-bonded functional modes. In non-bonded functional modes, the transmitter channels in the transceiver block can receive high-speed clock from either of the two CMU PLLs and use local dividers to provide clocks to its PCS and PMA blocks. f For more information about using two CMU PLLs to configure transmitter channels, refer to the Configuring Multiple Protocols and Data Rates chapter in volume 2 of Arria II GX Device Handbook. Power Down CMU1 PLL You can power down the CMU1 PLL by asserting the pll_powerdown signal. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-26 Chapter 1: Arria II GX Transceiver Architecture Transceiver Channel Architecture f For more information about using the pll_powerdown signal, refer to the Reset Control and Power Down chapter in volume 2 of the Arria II GX Device Handbook. Transceiver Channel Architecture Figure 1-12 shows the Arria II GX transceiver channel datapath. Figure 1-12. Arria II GX Transceiver Datapath Transmitter Channel PCS Byte Serializer TX Phase Compensation FIFO FPGA Fabric PCI Express hardIP 8B/10B Encoder Transmitter Channel PMA tx_dataout Serializer PIPE Interface Receiver Channel PCS RX Phase Compensation FIFO Byte Ordering Byte Deserializer 8B/10 Decoder Rate Match FIFO Deskew FIFO Word Aligner Receiver Channel PMA DeSerializer CDR rx_datain Each transceiver channel consists of: Transmitter channel, further divided into Transmitter channel PCS Transmitter channel PMA Receiver channel, further divided into Receiver channel PCS Receiver channel PMA Each transceiver channel interfaces to either the PCI Express hard IP block (PCI Express hard IP--transceiver interface) or directly to the FPGA fabric (FPGA fabric--transceiver interface). The transceiver channel interfaces to the PCI Express hard IP block if the hard IP block is used to implement the PCI Express PHY MAC, Data Link Layer, and Transaction Layer. Otherwise, the transceiver channel interfaces directly to the FPGA fabric. 1 The PCI Express hard IP--transceiver interface is out of the scope of this chapter. This chapter focuses on the FPGA fabric--transceiver interface. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Transceiver Channel Architecture 1-27 Figure 1-13 shows the FPGA fabric--transceiver interface and the transceiver PMA-PCS interface. Figure 1-13. FPGA Fabric--Transceiver Interface and the Transceiver PMA-PCS Interface FPGA Fabric-Transceiver Interface PMA-PCS Interface Transmitter Channel PCS Byte Serializer TX Phase Compensation FIFO FPGA Fabric PCI Express hardIP Transmitter Channel PMA 8B/10B Encoder tx_dataout Serializer PIPE Interface Receiver Channel PMA Receiver Channel PCS RX Phase Compensation FIFO Byte Ordering Byte Deserializer 8B/10 Decoder Rate Match FIFO Deskew FIFO Word Aligner DeSerializer CDR rx_datain The transceiver channel datapath is described by the single-width mode based on the FPGA fabric, transceiver interface width (channel width), and transceiver channel PMA-PCS width (serialization factor). Table 1-4 shows the FPGA fabric--transceiver interface widths (channel width) and transceiver PMA-PCS widths (serialization factor) allowed in single-width mode. Table 1-4. FPGA Fabric--Transceiver Interface Width and Transceiver PMA-PCS Widths (Note 1) Name Width/Functional Mode/Data Rate PMA-PCS interface widths 8/10 bit FPGA fabric--transceiver interface width 8/10 bit 16/20 bit Supported functional modes Data rate range in Basic functional mode PCI Express (PIPE) Gen1 XAUI GIGE Serial RapidIO SONET/SDH OC12 and OC48 SDI Basic single width 0.6 Gbps - 3.75 Gbps Note to Table 1-4: (1) In low-latency PCS mode in Basic single-width configuration, the data rate range is 0.6 Gbps to 3.75 Gbps. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-28 Chapter 1: Arria II GX Transceiver Architecture Transmitter Channel Datapath Transmitter Channel Datapath The transmitter channel datapath, shown in Figure 1-14, consists of the following blocks: TX phase compensation FIFO Byte serializer 8B/10B encoder Transmitter output buffer The Arria II GX transceiver provides the enable low latency PCS mode option in the ALTGX MegaWizard Plug-In Manager. If you select this option, the 8B/10B encoder in the data path is disabled. Figure 1-14. Transmitter Channel Datapath Transmitter Channel PCS PCI Express hardIP PIPE Interface TX Phase Compensation FIFO Byte Serializer Transmitter Channel PMA Serializer 8B/10B Encoder FPGA Fabric TX Phase Compensation FIFO The TX phase compensation FIFO interfaces the transmitter channel PCS and the FPGA fabric PIPE interface. It compensates for the phase difference between the low-speed parallel clock and the FPGA fabric interface clock. The two modes in which the TX phase compensation FIFO operates are low-latency and high-latency mode. Figure 1-15 shows the datapath and clocking of the TX phase compensation FIFO. Figure 1-15. TX Phase Compensation FIFO Data Path from the FPGA Fabric or PIPE Interface TX Phase Compensation FIFO wr_clk Data Path to the Byte Serializer or the 8B/10B Encoder or Serializer rd_clk tx_coreclk tx_clkout coreclkout Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Transmitter Channel Datapath 1-29 TX phase compensation FIFO: In low-latency mode, the FIFO is four words deep. The latency through the FIFO is two to three FPGA fabric parallel clock cycles (pending characterization). Low-latency mode is chosen automatically in every mode except PCI Express (PIPE) mode. In high-latency mode, the FIFO is eight words deep. The latency through the FIFO is approximately four to five FPGA parallel cycles (pending characterization). High-latency mode is automatically used for PCI Express (PIPE) mode. In non-bonded functional modes such as GIGE, the read port of the phase compensation FIFO is clocked by the low-speed parallel clock. The write clock is fed by the tx_clkout port of the associated channel. In bonded functional modes such as XAUI, the write clock of the FIFO is clocked by coreclkout provided by the CMU0 clock divider block. You can clock the write side by using tx_coreclk provided from the FPGA fabric by enabling the tx_coreclk port in the ALTGX MegaWizard Plug-In Manager. If you use this port, ensure that there is 0 PPM difference in frequency between the write and read side. The Quartus II software requires that you provide a 0 PPM assignment in the assignment editor. f For more information about the TX phase compensation FIFO, refer to the "Limitation of the Quartus II Software Selected Transmitter Phase Compensation FIFO Clocks" section in the Arria II GX Transceiver Clocking chapter in volume 2 of the Arria II GX Device Handbook. Input Data In PCI Express (PIPE) functional mode, the input data comes from the PIPE interface. In all other functional modes, the input data comes directly from the FPGA fabric. Output Data Destination Block The output from the TX phase compensation FIFO is used by the byte serializer block, 8B/10B encoder, or serializer block. Table 1-5 lists the conditions under which the TX phase compensation FIFO outputs are provided to these blocks. Table 1-5. Output Data Destination Block for TX Phase Compensation FIFO Output Data (c) March 2009 Byte Serializer 8B/10B Encoder Serializer If you select: If you select: If you select: single-width mode and channel width = 16 or 20 single-width mode and channel width = 8 and 8B/10B encoder enabled low latency PCS bypass mode enabled or Altera Corporation single-width mode and channel width = 8 or 10 Arria II GX Device Handbook Volume 2 1-30 Chapter 1: Arria II GX Transceiver Architecture Transmitter Channel Datapath TX Phase Compensation FIFO Status Signal An optional tx_phase_comp_fifo_error port is available in all functional modes to indicate a receiver phase compensation FIFO overflow or under run condition. The tx_phase_comp_fifo_error signal is asserted high when the TX phase compensation FIFO either overflows or under runs due to any frequency PPM difference between the FIFO read and write clocks. If the tx_phase_comp_fifo_error flag gets asserted, verify the FPGA fabric--transceiver interface clocking to ensure that there is 0 PPM difference between the TX phase compensation FIFO read and write clocks. Byte Serializer The byte serializer divides the input datapath by two. This allows you to run the transceiver channel at higher data rates while keeping the FPGA fabric interface frequency within the maximum limit of 200 MHz. In single-width mode, it converts the two-byte wide datapath to a one-byte wide datapath. For example, if you would like to run the transceiver channel at 3.125 Gbps, without the byte serializer, in single-width mode, the FPGA fabric interface clock frequency must be 312.5 MHz (3.125 G/10). This violates the FPGA fabric interface frequency limit. When you use the byte serializer, the FPGA fabric interface frequency is 156.25 MHz (3.125 G/20). 1 The byte deserializer is required in configurations that exceed the FPGA fabric--transceiver interface clock upper frequency limit. It is optional in configurations that does not exceed the FPGA fabric--transceiver interface clock upper frequency limit. Single-Width Mode Figure 1-16 shows the byte serializer datapath in single-width mode. Figure 1-16. Byte Serializer Datapath in Single-Width Mode datain[] Byte Serializer /2 (Note 1), (2) dataout[] Low-Speed Parallel Clock Notes to Figure 1-16: (1) Refer to Table 1-6 for the datain[] and dataout[] port width. (2) The datain signal is the input from the FPGA fabric that has already passed through the TX phase compensation FIFO. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Transmitter Channel Datapath 1-31 The byte serializer forwards the LSB first, followed by the MSB. The input data width to the byte serializer depends on the channel width option that you selected in the ALTGX MegaWizard Plug-In Manager. For example, in single-width mode, assuming a channel width of 20, the byte serializer sends out the least significant word datain[9:0] of the parallel data from the FPGA fabric, followed by datain[19:10]. Table 1-6 shows the input and output data widths of the byte serializer in single-width mode. Table 1-6. Input and Output Data Width of the Byte Serializer in Single-Width Mode Deserialization Width Input Data Width to the Byte Serializer Output Data Width from the Byte Serializer 16 8 20 (1) 10 (1) Single-width mode Note to Table 1-6: (1) The 8B/10B encoder is automatically bypassed by the Quartus II software for channel width of 10 or 20 bits. Asserting the tx_digitalreset signal resets the byte serializer block. For channel widths of 8 or 16 bits, if you select the 8B/10B Encoder option in the ALTGX MegaWizard Plug-In Manager, the 8B/10B encoder uses the output from the byte serializer. Otherwise, the byte serializer output is forwarded to the serializer. 8B/10B Encoder The 8B/10B encoder generates 10-bit code groups from the 8-bit data and 1-bit control identifier. In single-width mode, the 8B/10B encoder generates a 10-bit code group from the 8-bit data and 1-bit control identifier. Single-Width Mode Figure 1-17 shows the inputs and outputs of the 8B/10B encoder. Figure 1-17. 8B/10B Encoder in Single-Width Mode From the Byte Serializer To the Serializer datain[7:0] control_code tx_forcedisp 8B/10B Encoder dataout[9:0] tx_dispval In single-width mode, the 8B/10B encoder translates the 8-bit data to a 10-bit code group (control word or data word) with proper disparity. If the control_code input is high, the 8B/10B encoder translates the input data[7:0] to a 10-bit control word. If the control_code input is low, the 8B/10B encoder translates the input data[7:0] to a 10-bit data word. You can use the tx_forcedisp and tx_dispval ports to control the running disparity of the generated output data. For more information, see "Controlling Running Disparity" on page 1-33. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-32 Chapter 1: Arria II GX Transceiver Architecture Transmitter Channel Datapath Figure 1-18 shows the conversion format. The LSB is transmitted first. Figure 1-18. 8B/10B Conversion Format 7 6 5 4 3 2 1 control_code 0 H G F E D C B A 8B/10B Conversion j h g f i e d c b a 9 8 6 5 4 1 7 3 2 0 LSB MSB Control Code Encoding The ALTGX MegaWizard Plug-In Manager provides the tx_ctrlenable port to indicate whether the 8-bit data at the tx_datain port should be encoded as a control word (Kx.y). When tx_ctrlenable is low, the 8B/10B encoder block encodes the byte at the tx_datain port (the user-input port) as data (Dx.y). When tx_ctrlenable is high, the 8B/10B encoder encodes the input data as a Kx.y code group. The waveform in Figure 1-19 shows the second 0 x BC encoded as a control word (K28.5). The rest of the tx_datain bytes are encoded as a data word (Dx.y). Figure 1-19. Control Word and Data Word Transmission clock tx_datain[7:0] 83 78 D3.4 D24.3 BC BC 0F 00 K28.5 D15.0 D0.0 BF 3C tx_ctrlenable code group D28.5 D31.5 D28.1 The IEEE 802.3 8B/10B encoder specification identifies only a set of 8-bit characters for which tx_ctrlenable should be asserted. If you assert tx_ctrlenable for any other set of bytes, the 8B/10B encoder might encode the output 10-bit code as an invalid code (it does not map to a valid Dx.y or Kx.y code), or an unintended valid Dx.y code, depending on the value entered. It is possible for a downstream 8B/10B decoder to decode an invalid control word into a valid Dx.y code without asserting any code error flags. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Transmitter Channel Datapath 1 1-33 For example, depending on the current running disparity, the invalid code K24.1 (tx_datain = 8'h38 + tx_ctrl = 1'b1) can be encoded to 10'b0110001100 (0 x 18C), which is equivalent to a D24.6+ (8'hD8 from the RD+ column). Altera recommends that you do not assert tx_ctrlenable for unsupported 8-bit characters. Reset Condition The tx_digitalreset signal resets the 8B/10B encoder. During reset, the running disparity and data registers are cleared. Also, the 8B/10B encoder outputs a K28.5 pattern from the RD- column continuously until tx_digitalreset is de-asserted. The input data and control code from the FPGA fabric is ignored during the reset state. Once out of reset, the 8B/10B encoder starts with a negative disparity (RD-) and transmits three K28.5 code groups for synchronization before it starts encoding and transmitting data on its output. 1 While tx_digitalreset is asserted, the downstream 8B/10B decoder that receives the data might observe synchronization or disparity errors. Figure 1-20 shows the reset behavior of the 8B/10B encoder. When in reset (tx_digitalreset is high), a K28.5- (K28.5 10-bit code group from the RD- column) is sent continuously until tx_digitalreset is low. Due to some pipelining of the transmitter channel PCS, some "don't cares" (10'hxxx) are sent before the three synchronizing K28.5 code groups. User data follows the third K28.5 code group. Figure 1-20. 8B/10B Encoder Output during tx_digitalreset Assertion clock tx_digitalreset dataout[9:0] K28.5- K28.5- K28.5- xxx ... xxx K28.5- K28.5+ K28.5- Dx.y+ Controlling Running Disparity Upon power on or reset, the 8B/10B encoder has a negative disparity and chooses the 10-bit code from the RD- column (refer to the 8B/10B encoder specification for the RD+ and RD- column values). The ALTGX MegaWizard Plug-In Manager provides the tx_forcedisp and tx_dispval ports to control the running disparity of the output from the 8B/10B encoder. These ports are available only in Basic single-width mode. A high value on the tx_forcedisp port is the control signal to the disparity value of the output data. The disparity value (RD+ or RD-) is indicated by the value on the tx_dispval port. If the tx_forcedisp port is low, tx_dispval is ignored and the current running disparity is not altered. Forcing disparity can either maintain the current running disparity calculations if the forced disparity value (on the tx_dispval bit) happens to match the current running disparity, or flip the current running disparity calculations if it does not. If the forced disparity flips the current running disparity, the downstream 8B/10B decoder might detect a disparity error. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-34 Chapter 1: Arria II GX Transceiver Architecture Transmitter Channel Datapath Table 1-7 shows the tx_forcedisp and tx_dispval port values. Table 1-7. tx_forcedisp and tx_dispval Port Values tx_forcedisp tx_dispval Disparity Value 0 X Current running disparity has no change 1 0 Encoded data has positive disparity 1 1 Encoded data has negative disparity Figure 1-21 shows the current running disparity being altered in Basic single-width mode by forcing a positive disparity K28.5 when it was supposed to be a negative disparity K28.5. In this example, a series of K28.5 code groups are continuously being sent. The stream alternates between a positive running disparity (RD+) K28.5 and a negative running disparity (RD-) K28.5 to maintain a neutral overall disparity. The current running disparity at time n + 3 indicates that the K28.5 in time n + 4 should be encoded with a negative disparity. Because tx_forcedisp is high at time n + 4, and tx_dispval is also high, the K28.5 at time n + 4 is encoded as a positive disparity code group. Figure 1-21. 8B/10B Encoder Force Running Disparity Operation in Single-Width Mode n n+1 n+2 n+3 n+4 n+5 n+6 n+7 BC BC BC BC BC BC BC BC RD- RD+ RD- RD+ RD+ RD- RD+ RD- 17C 283 283 17C 283 17C clock tx_in[7:0] tx_ctrlenable tx_forcedisp tx_dispval Current Running Disparity dataout[9:0] 17C 283 Transmitter Polarity Inversion The positive and negative signals of a serial differential link might accidentally be swapped during board layout. Solutions like a board re-spin or major updates to the logic in the FPGA fabric can be expensive. The transmitter polarity inversion feature is provided to correct this situation. An optional tx_invpolarity port is available in all functional modes to dynamically enable the transmitter polarity inversion feature. In single-width mode, a high value on the tx_invpolarity port inverts the polarity of every bit of the 8-bit or 10-bit input data word to the serializer in the transmitter datapath. Because inverting the polarity of each bit has the same effect as swapping the positive and negative signals of the differential link, correct data is seen by the receiver. The tx_invpolarity signal is dynamic and might cause initial disparity errors at the receiver of an 8B/10B encoded link. The downstream system must be able to tolerate these disparity errors. Figure 1-22 shows the transmitter polarity inversion feature in a single-width 10-bit wide datapath configuration. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Transmitter Channel Datapath 1-35 Figure 1-22. Transmitter Polarity Inversion in Single-Width Mode Output from transmitter PCS 0 tx _invpolarity = high MSB Converted data output to the transmitter serializer 1 1 0 1 0 1 0 0 1 0 1 0 1 1 0 0 1 0 LSB 1 MSB LSB Transmitter Bit Reversal By default, the Arria II GX transmit bit order is LSBit to MSBit. In single-width mode, the LSB of the 8- or 10-bit data word is transmitted first, followed by the MSB. The transmitter bit reversal feature allows reversing the transmit bit order as MSB to LSB before it is forwarded to the serializer. If you enable the transmitter bit reversal feature in Basic single-width mode, the 8-bit D[7:0] or 10-bit D[9:0] data at the input of the serializer gets rewired to D[0:7] or D[0:9], respectively. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-36 Chapter 1: Arria II GX Transceiver Architecture Transmitter Channel Datapath Figure 1-23 shows the transmitter bit reversal feature in Basic single-width for a 10-bit wide datapath configuration. Figure 1-23. Transmitter Bit Reversal Operation in Basic Single-Width Mode Output from transmitter PCS TX bit reversal option enabled in the ALTGX MegaWizard Converted data output to the transmitter serializer D[9] D[0] D[8] D[1] D[7] D[2] D[6] D[3] D[5] D[4] D[4] D[5] D[3] D[6] D[2] D[7] D[1] D[8] D[0] D[9] Serializer The serializer converts the incoming low-speed parallel signal from the transceiver PCS to high-speed serial data and sends it to the transmitter buffer. The serializer supports an 8-bit or 10-bit serialization factor in single-width mode. The serializer block drives the serial data to the output buffer, as shown in Figure 1-24. The serializer block sends out the LSB of the input data. Figure 1-25 shows the serial bit order of the serializer block output. In this example, a constant 8'h6A (01101010) value is serialized and the serial data is transmitted from LSBit to MSBit. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Transmitter Channel Datapath 1-37 Figure 1-24. Serializer Block in an 8-Bit PCS-PMA Interface D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 8 To Output Buffer parallel clock from local divider block parallel clock from CMU0 clock divider Low-Speed Parallel Clock parallel clock from master transceiver block (1) serial clock from local divider block High-Speed Serial Clock serial clock from CMU0 clock divider serial clock from master transceiver block (1) Note to Figure 1-24: (1) The CMU0 clock divider of the master transceiver block provides the clocks. It is used only in PCI Express (PIPE) x8 mode. Figure 1-25. Serializer Bit Order (Note 1) Low-speed parallel clock High-speed serial clock tx_datain[7..0] tx_dataout[0] 01101010 0 1 0 1 0 00000000 1 1 0 Note to Figure 1-25: (1) This figure assumes that the input data to the serializer is 8 bits (channel width = 8 bits with the 8B/10B encoder disabled). (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-38 Chapter 1: Arria II GX Transceiver Architecture Transmitter Channel Datapath Transmitter Output Buffer The Arria II GX transmitter buffers support 1.5-V pseudo current mode logic (PCML) and can drive 40 inches of FR4 trace across two connectors. The transmitter buffer voltage level is (VCCH) set to 1.5 V by the ALTGX MegaWizard Plug-In Manager. With the 1.5 V (available in Quartus II software version 8.1 or later) setting, you can run the transmitter channel from 600 Mbps to 3.75 Gbps. The transmitter buffer power supply only provides voltage to the transmitter output buffers in the transceiver channels. The transmitter output buffer, as shown in Figure 1-26, has additional circuitry to improve signal integrity, such as VOD, programmable pre-emphasis circuit, internal termination circuitry, and receiver detect capability to support PCI Express (PIPE) functional mode. Figure 1-26. Transmitter Output Buffer 50 +VTT- Programmable Pre-emphasis and VOD Transmitter Output Pins 50 Receiver Detect Transmitter Termination The Arria II GX transmitter buffer includes on-chip differential termination of 100 . The resistance is adjusted by the on-chip calibration circuit in the calibration block (for more information, refer to "Calibration Blocks" on page 1-137), which compensates for temperature, voltage, and process changes. The Arria II GX transmitter buffers in the transceiver are current-mode drivers. Therefore, the resultant V OD is a function of the transmitter termination value. For more information about resultant VOD values, refer to "Programmable Output Differential Voltage" on page 1-39. You can disable on-chip termination (OCT) and use external termination. If you select external termination, the transmitter common mode is tri-stated. You can set transmitter termination in the ALTGX MegaWizard Plug-In Manager. You can also set OCT through the assignment editor. Set the assignment shown in Table 1-8 to the transmitter serial output pin. Table 1-8. Arria II GX OCT Assignment Settings Assign To Transmitter Serial Output Data Pin Assignment Name: Output Termination Available Values: OCT 100 Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Transmitter Channel Datapath 1-39 Programmable Output Differential Voltage The Arria II GX device allows you to customize the differential output voltage to handle different trace lengths, various backplanes, and various receiver requirements, as shown in Figure 1-27. Figure 1-27. VOD (Differential) Signal Level Single-Ended Waveform VA +VOD VB Differential Waveform +700 +VOD 0-V Differential VOD VOD (Differential) -VOD -700 = VA - VB Table 1-9 shows the VOD values for 100 termination resistor setting. Table 1-9. Programmable VOD Differential Peak-to-Peak (Note 1) VOD for 100 Termination Setting Unit 400 mV 600 mV 800 mV 900 mV 1000 mV 1200 mV Note to Table 1-9: (1) These values are preliminary. 1 You can set the above VOD values in the ALTGX MegaWizard Plug-In Manager. Programmable Pre-Emphasis The programmable pre-emphasis module in each transmit buffer boosts high frequencies in the transmit data signal, which might be attenuated in the transmission media. Using pre-emphasis can maximize the data eye opening at the far-end receiver. The transmission line's transfer function can be represented in the frequency domain as a low-pass filter. Any frequency components below the -3dB frequency can pass through with minimal loss. Frequency components greater than -3dB frequency are attenuated. This variation in frequency response yields data-dependent jitter and other intersymbol interference (ISI) effects. By applying pre-emphasis, the high-frequency components are boosted; that is, pre-emphasized. Pre-emphasis (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-40 Chapter 1: Arria II GX Transceiver Architecture Transmitter Channel Datapath equalizes the frequency response at the receiver so the differences between the low-frequency and high-frequency components are reduced, which minimizes the ISI effects from the transmission medium. Pre-emphasis requirements increase as data rates through legacy backplanes increase. Set the pre-emphasis settings in the ALTGX MegaWizard Plug-In Manager. Transmitter Output Buffer Power (V CCH) Arria II GX transmitter buffer power is set to 1.5 V by the ALTGX MegaWizard Plug-In Manager. Common Mode Voltage (V CM) Settings The Arria II GX devices provide a VCM of 650 mV. PCI Express (PIPE) Receiver Detect The Arria II GX transmitter buffer has a built-in receiver detection circuit for use in the PCI Express (PIPE) mode for Gen1 data rates. This circuit detects if there is a receiver downstream by sending out a pulse on the common mode of the transmitter and monitoring the reflection. This mode requires the transmitter buffer to be tri-stated (in Electrical Idle mode), OCT utilization, and the 125 MHz fixedclk signal. You can enable this feature in PCI Express (PIPE) mode by setting the tx_forceelecidle and tx_detectrxloopback ports to 1'b1. Receiver detect circuitry is active only in the P1 power state (refer to the PIPE 2.00 specification for more information about power states). In the P1 power state, the transmitter output buffer is tri-stated because the transmitter output buffer is in electrical idle. A high on the tx_detectrxloopback port triggers the receiver detect circuitry to alter the transmitter output buffer common mode voltage. The sudden change in common mode voltage effectively appears as a step voltage at the tri-stated transmitter buffer output. If a receiver (that complies with PCI Express [PIPE] input impedance requirements) is present at the far end, the time constant of the step voltage is higher. If a receiver is not present or is powered down, the time constant of the step voltage is lower. The receiver detect circuitry snoops the transmitter buffer output for the time constant of the step voltage to detect the presence of the receiver at the far end. A high pulse is driven on the pipephydonestatus port and 3'b011 is driven on the pipestatus port to indicate that a receiver has been detected. There is some latency after asserting the tx_detectrxloopback signal, before the receiver detection is indicated on the pipephydonestatus port. For the signal timing to perform the receiver detect operation, refer to Figure 1-75 on page 1-94. 1 The tx_forceelecidle port must be asserted at least 10 parallel clock cycles prior to the tx_detectrxloopback port to ensure that the transmitter buffer is tri-stated. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Transmitter Local Clock Divider Block 1-41 PCI Express (PIPE) Electrical Idle The Arria II GX transmitter output buffer supports transmission of PCI Express Electrical Idle (or individual transmitter tri-state). This feature is only active in PCI Express (PIPE) mode. The tx_forceelecidle port puts the transmitter buffer in Electrical Idle mode. This port has a specific functionality in each power state. Refer to PIPE specification 2.00 for use of the tx_forceelecidle signal under different power states. For the signal timing to perform the electrical idle transmission in PCI Express (PIPE) mode, refer to Figure 1-74 on page 1-93. Transmitter Local Clock Divider Block Each transmitter channel contains a local clock divider block. It receives the high-speed clock from CMU0 PLL or CMU1 PLL and generates the high-speed serial clock for the serializer and the low-speed parallel clock for the transmitter PCS data path. The low-speed parallel clock is also forwarded to the FPGA fabric (tx_clkout). The local clock divider block allows each transmitter channel to run at /1, /2, or /4 of the CMU PLL data rate. Note that the local clock divider block is used only in non-bonded functional modes (for example, GIGE, SONET/SDH, and SDI mode). The Quartus II software automatically selects the local clock divider block in non-bonded functional modes. Figure 1-28 shows the transmitter local clock divider block. Figure 1-28. Transmitter Local Clock Divider Block High-Speed Serial Clock CMU0 PLL High-Speed Clock /n Low-Speed Parallel Clock / 4, 5, 8, or 10 /1, 2, or 4 CMU1 PLL High-Speed Clock Receiver Channel Datapath Figure 1-29 shows the receiver channel datapath in Arria II GX devices. Figure 1-29. Receiver Channel Datapath Receiver Channel PCS FPGA Fabric PCI Express hardIP PIPE Interface RX Phase Compensation FIFO Byte Ordering Byte DeSerializer 8B/10B Decoder Rate Match FIFO Deskew FIFO Word Aligner Receiver Channel PMA DeSerializer CDR Serial Input Data rx_datain Input Reference Clock (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-42 Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath The receiver channel PMA datapath consists of the following blocks: Receiver input buffer Clock and data recovery (CDR) unit Deserializer The receiver channel PCS datapath consists of the following blocks: Word aligner Deskew FIFO Rate match (clock rate compensation) FIFO 8B/10B decoder Byte deserializer Byte ordering Receiver phase compensation FIFO PIPE interface The receiver datapath is very flexible and allows multiple configurations, depending on the selected functional mode. You can configure the receiver datapath using the ALTGX MegaWizard Plug-In Manager. This section discusses Arria II GX receiver channel datapath architecture. The sub-blocks in the receiver datapath are described in order from the serial receiver input buffer to the receiver phase compensation FIFO buffer at the FPGA fabric--transceiver interface. Receiver Input Buffer The receiver input buffer receives serial data from the rx_datain port and feeds it to the CDR unit. In the reverse serial loopback (pre-CDR) configuration, it also feeds the received serial data to the transmitter output buffer. Figure 1-30 shows the receiver input buffer. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath 1-43 Figure 1-30. Receiver Input Buffer To the Transmitter Output Buffer in the Reverse Serial Loopback (Pre-CDR) Configuration Receiver Input Buffer Equalization and DC Gain Circuitry From Serial Data Input Pins (rx_datain) To CDR 100 RX Vcm Signal Threshold Detection Circuitry 0.82/1.1 V Signal Detect Table 1-10 shows the electrical features supported by the receiver input buffer. Table 1-10. Electrical Features Supported by the Receiver Input Buffer Data Rate (Gbps) 0.6 - 3.75 I/O Standard Differential On-Chip Termination with Calibration () Common Mode Voltage (V) Coupling 1.4 V PCML 100 0.82 AC, DC 1.5 V PCML 100 0.82 AC, DC 2.5 V PCML 100 0.82 AC LVPECL 100 0.82 AC LVDS 100 1.1 AC, DC The Arria II GX receiver buffer supports the following features: Programmable differential OCT Programmable common mode voltage AC and DC coupling Programmable equalization and DC gain Signal threshold detection circuitry Differential On-Chip Termination The Arria II GX receiver buffers support optional differential on-chip termination of 100 . On-chip termination can be set using the Quartus II software Assignment Editor, as shown in Table 1-11. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-44 Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath Table 1-11. Arria II GX Receiver On-Chip Termination Assignment Settings Assign To 1 rx_datain (Receiver Input Data Pins) Assignment Name: Input Termination Available Values: OCT 100 , Off The Arria II GX receiver OCT resistors have calibration support to compensate for process, voltage, and temperature variations. For more information about OCT calibration support, refer to "Calibration Blocks" on page 1-137. Programmable Common Mode Voltage The Arria II GX receiver buffers have on-chip biasing circuitry to establish the required common mode voltage at the receiver input. It supports two common mode voltage settings of 0.82 V and 1.1 V that you can select in the ALTGX MegaWizard Plug-In Manager. You must select 0.82 V as the receiver buffer common mode voltage for the following receiver input buffer I/O standards: 1.4-V PCML 1.5-V PCML 2.5-V PCML LVPECL You must select 1.1 V as the receiver buffer common mode voltage for the following receiver input buffer I/O standard: 1 LVDS On-chip biasing circuitry is effective only if you select on-chip receiver termination. If you select external termination, you must implement off-chip biasing circuitry to establish the common mode voltage at the receiver input buffer. Link Coupling A high-speed serial link can either be AC-coupled or DC-coupled, depending on the serial protocol being implemented. While most of the serial protocols require links to be AC-coupled, protocols similar to SONET optionally allow DC coupling. AC-Coupled Links In an AC-coupled link, the AC-coupling capacitor blocks the transmitter DC common mode voltage. The on-chip receiver termination and biasing circuitry automatically restores the selected common mode voltage. Figure 1-31 shows an AC-coupled link. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath 1-45 Figure 1-31. AC-Coupled Link AC Coupling Capacitor Transmitter Receiver Transmission Medium Transmission Medium AC Coupling Capacitor RX Termination TX Termination TX VCM RX VCM The following protocols supported by Arria II GX devices mandate AC-coupled links: PCI Express (PIPE) Gigabit Ethernet Serial RapidIO XAUI SDI DC-Coupled Links In a DC-coupled link, the transmitter DC common mode voltage is seen unblocked at the receiver buffer. The link common mode voltage depends on the transmitter common mode voltage and the receiver common mode voltage. The on-chip or off-chip receiver termination and biasing circuitry must ensure compatibility between the transmitter and the receiver common mode voltage. Figure 1-32 shows a DC-coupled link. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-46 Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath Figure 1-32. DC-Coupled Link Transmitter Receiver Transmission Medium Transmission Medium TX Termination RX Termination TX VCM RX VCM You might choose to use the DC-coupled high-speed link for Basic single-width mode only. The following sections discuss DC-coupling requirements for a high-speed link with an Arria II GX device used as the transmitter, receiver, or both. Specifically, the following link configurations are discussed: Arria II GX Transmitter (PCML) to Arria II GX Receiver (PCML) Stratix II GX Transmitter (PCML) to Arria II GX Receiver (PCML) Arria II GX Transmitter (PCML) to Stratix II GX Receiver (PCML) LVDS Transmitter to Arria II GX Receiver (PCML) Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath 1-47 Figure 1-33 shows a typical Arria II GX transmitter (PCML) to Arria II GX Receiver (PCML) DC-coupled link. Figure 1-33. Arria II GX Transmitter (PCML) to Arria II GX Receiver (PCML) DC-Coupled Link VCCH = 1.5 V Transmission Medium Arria II GX Transmitter Arria II GX Receiver Transmission Medium 50- TX Termination 50- TX Termination 0.65 V 50- RX Termination 50- RX Termination Rs TX VCM RX VCM 0.82 V Table 1-12 shows the allowed transmitter and receiver settings in an Arria II GX transmitter (PCML) to Arria II GX receiver (PCML) DC coupled link. Table 1-12. Settings for an Arria II GX Transmitter (PCML) to Arria II GX Receiver (PCML) DC-Coupled Link Transmitter (Arria II GX) Settings Receiver (Arria II GX) Settings Data Rate VCCH (1) TX VCM Differential Termination 600-3750 Mbps 1.5 V 0.65 V 100 Data Rate RX VCM Differential Termination 600-3750 Mbps 0.82 V 100- Note to Table 1-12: (1) VCCH = 1.5 V can support data rates from 600 Mbps to 3750 Mbps. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-48 Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath Figure 1-34 shows the Stratix II GX transmitter (PCML) to Arria II GX receiver (PCML) DC-coupled link. Figure 1-34. Stratix II GX Transmitter (PCML) to Arria II GX Receiver (PCML) DC-Coupled Link VCCH = 1.5 V Transmission Medium Stratix II GX Transmitter Arria II GX Receiver Transmission Medium 50- TX Termination 0.6 V/0.7 V 50- TX Termination 50- RX Termination 50- RX Termination Rs TX VCM RX VCM 0.82 V Table 1-13 shows the allowed transmitter and receiver settings in a Stratix II GX to Arria II GX coupled link. Table 1-13. Settings for a Stratix II GX to Arria II GX DC-Coupled Link Transmitter (Stratix II GX) Settings Receiver (Arria II GX) Settings Data Rate VCCH (1) TX VCM (1) Differential Termination Data Rate RX VCM Differential Termination 600-3750 Mbps 1.5 V 0.6 V/0.7 V 100 600-3750 Mbps 0.82 V 100- (1.5 V PCML) Note to Table 1-13: (1) VCCH = 1.5 V with TX Vcm = 0.7 V can support data rates from 600 Mbps to 3125 Mbps. VCCH = 1.5 V with TX Vcm = 0.6 V can support data rates from 600 Mbps to 6375 Mbps. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath 1-49 Figure 1-35 shows the Arria II GX transmitter (PCML) to Stratix II GX receiver (PCML) DC-coupled link. Figure 1-35. Arria II GX Transmitter (PCML) to Stratix II GX Receiver (PCML) DC-Coupled Link VCCH = 1.5 V Transmission Medium Arria II GX Transmitter Stratix II GX Receiver Transmission Medium 50- TX Termination 50- TX Termination 50- RX Termination 50- RX Termination Rs TX VCM 0.65 V RX VCM 0.85 V Table 1-14 shows the allowed transmitter and receiver settings in an Arria II GX transmitter (PCML) to Stratix II GX receiver (PCML) DC-coupled link. Table 1-14. Settings for an Arria II GX to Stratix II GX DC-Coupled Link Transmitter (Arria II GX) Settings Receiver (Stratix II GX) Settings Data Rate VCCH (1) TX VCM Differential Termination 600-3750 Mbps 1.5 V 0.65 V 100 Data Rate I/O Standard 600-3750 Mbps 1.5 V PCML RX VCM Differential Termination 0.85 V 100- Note to Table 1-14: (1) VCCH = 1.5 V can support data rates from 600 Mbps to 3750 Mbps. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-50 Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath Figure 1-36 shows the LVDS transmitter to Arria II GX receiver (PCML) DC-coupled link. Figure 1-36. LVDS Transmitter to Arria II GX Receiver (PCML) DC-Coupled Link Transmission Medium LVDS Transmitter Arria II GX Receiver Transmission Medium 50- RX Termination 50- RX Termination Rs RX VCM 1.1 V Table 1-15 shows the allowed transmitter and receiver settings in a LVDS transmitter to Arria II GX receiver DC-coupled link. Table 1-15. Settings for a LVDS transmitter to Arria II GX Receiver DC-Coupled Link (Note 1) Receiver (Arria II GX) Settings RX VCM Differential Termination RS 1.1 V 100 (2) Notes to Table 1-15: (1) When DC coupling an LVDS transmitter to the Arria II GX receiver, use RX Vcm = 1.1 V and series resistance value RS to verify compliance to the LVDS specification. (2) Pending characterization. Programmable Equalization and DC Gain The transfer function of the physical medium can be represented as a low-pass filter in the frequency domain. Frequency components below -3 dB frequency pass through with minimal loss. Frequency components greater than -3 dB frequency get attenuated as a function of frequency due to skin-effect and dielectric losses. This variation in frequency response yields data-dependant jitter and other ISI effects, which can cause incorrect sampling of the input data. Each Arria II GX receiver buffer has independently programmable equalization circuitry that boosts the high-frequency gain of the incoming signal, thereby compensating for the low-pass filter effects of the physical medium. The amount of high-frequency gain required depends on the loss characteristics of the physical medium. Arria II GX equalization circuitry supports equalization settings that provide up to 7 dB of high-frequency boost. You can select the appropriate equalization setting in the ALTGX MegaWizard Plug-In Manager. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath 1-51 The Arria II GX receiver buffer also supports programmable DC gain circuitry. Unlike equalization circuitry, DC gain circuitry provides equal boost to the incoming signal across the frequency spectrum. The receiver buffer supports DC gain settings of 0 dB, 3 dB, and 6 dB. You can select the appropriate DC gain setting in the ALTGX MegaWizard Plug-In Manager. Signal Threshold Detection Circuitry In PCI Express (PIPE) mode, you can enable the optional signal threshold detection circuitry by NOT selecting the Force signal detection option in the ALTGX MegaWizard Plug-In Manager. If enabled, this option senses whether the signal level present at the receiver input buffer is above the signal detect threshold voltage that you specified in the What is the signal detect and signal loss threshold? option in the ALTGX MegaWizard Plug-In Manager. 1 The appropriate signal detect threshold level that complies with the PCI Express (PIPE) compliance parameter VRX-IDLE-DETDIFFp-p is pending characterization. Signal threshold detection circuitry has a hysteresis response that filters out any high-frequency ringing caused by inter-symbol interference or high-frequency losses in the transmission medium. If the signal threshold detection circuitry senses the signal level present at the receiver input buffer to be higher than the signal detect threshold, it asserts the rx_signaldetect signal high. Otherwise, the signal threshold detection circuitry de-asserts the rx_signaldetect signal low. If you select the Force signal detection option in the ALTGX MegaWizard Plug-In Manager, rx_signaldetect is always asserted high, irrespective of the signal level on the receiver input buffer. The rx_signaldetect signal is also used by the lock-to-reference/lock-to-data (LTR/LTD) controller in the receiver CDR to switch between LTR and LTD lock modes. When the signal threshold detection circuitry de-asserts the rx_signaldetect signal, the LTR/LTD controller switches the receiver CDR from LTD to LTR lock mode. For more information, refer to "LTR/LTD Controller" on page 1-54. Clock and Data Recovery Unit Each Arria II GX receiver channel has an independent CDR unit to recover the clock from the incoming serial data stream. The high-speed and low-speed recovered clocks are used to clock the receiver PMA and PCS blocks. Figure 1-37 shows the CDR block diagram. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-52 Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath Figure 1-37. CDR Unit Clock and Data Recovery (CDR) Unit rx_locktorefclk rx_locktodata signal detect rx_freqlocked LTR/LTD Controller Phase Detector (PD) rx_datain High-Speed Recovered Clock Low-Speed Recovered Clock Down Up Charge Pump + Loop Filter rx_cruclk /1, /2, /4 /2 Phase Frequency Detector (PFD) VCO /L rx_pll_locked Up Down /M The CDR operates either in LTR mode or LTD mode. In LTR mode, the CDR tracks the input reference clock. In LTD mode, the CDR tracks the incoming serial data. After the receiver power-up and reset cycle, the CDR must be kept in LTR mode until it locks to the input reference clock. Once locked to the input reference clock, the CDR output clock is trained to the configured data rate. The CDR can now switch to LTD mode to recover the clock from incoming data. The LTR/LTD controller controls the switch between LTR and LTD modes. Lock-to-Reference Mode In LTR mode, the phase frequency detector in the CDR tracks the receiver input reference clock, rx_cruclk. The PFD controls the charge pump that tunes the VCO in the CDR. Depending on the data rate and the selected input reference clock frequency, the Quartus II software automatically selects the appropriate /M and /L divider values such that the CDR output clock frequency is half the data rate. An active high, the rx_pll_locked status signal is asserted to indicate that the CDR has locked to phase and frequency of the receiver input reference clock. Figure 1-38 shows active blocks when CDR is in LTR mode. 1 The phase detector (PD) is inactive in LTR mode. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath 1-53 Figure 1-38. CDR in Lock-To-Reference Mode Clock and Data Recover (CDR) Unit rx_locktorefclk rx_locktodata signal detect rx_freqlocked LTR/LTD Controller Phase Detector (PD) rx_datain High-Speed Recovered Clock Low-Speed Recovered Clock Down Up Charge Pump + Loop Filter rx_cruclk /1, /2, /4 /2 Phase Frequency Detector (PFD) VCO /L rx_pll_locked Clock output tracks the input reference clock Up Down Active Blocks /M Inactive Blocks You can drive the receiver input reference clock with the following clock sources: Dedicated refclk pins (refclk0 and refclk1) of the associated transceiver block Inter-transceiver block clock lines from other transceiver blocks on the same side of the device (up to six ITB clock lines, two from each transceiver block) Global PLD clock driven by a dedicated clock input pin Clock output from the left PLLs in the FPGA fabric Table 1-16 shows CDR specifications in LTR mode. Table 1-16. CDR Specification in Lock-To-Reference Mode Parameter Value Input Reference Clock Frequency 50 MHz - 637.5 MHz PFD Input Frequency 50 MHz - 325 MHz /M Divider 4, 5, 8, 10, 16, 20, 25 /L Divider 1, 2, 4, 8 For input reference clock frequencies greater than 325 MHz, the Quartus II software automatically selects the appropriate /1, /2, or /4 pre-divider to meet the PFD input frequency limitation of 325 MHz. Lock-to-Data Mode The CDR must be in LTD mode to recover clock from the incoming serial data during normal operation. In LTD mode, the phase detector in the CDR tracks the incoming serial data at the receiver buffer. Depending on the phase difference between the incoming data and the CDR output clock, the PD controls the CDR charge pump that tunes the VCO. Figure 1-39 shows active blocks when the CDR is in LTD mode. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-54 Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath 1 The PFD is inactive in LTD mode. The rx_pll_locked signal toggles randomly and has no significance in LTD mode. Figure 1-39. CDR in Lock-To-Data Mode Clock and Data Recovery (CDR) Unit rx_locktorefclk rx_locktodata signal detect rx_freqlocked LTR/LTD Controller Phase Detector (PD) rx_datain High-Speed Recovered Clock Low-Speed Recovered Clock Down Up Charge Pump + Loop Filter rx_cruclk /1, /2, /4 /2 VCO /L rx_pll_locked Phase Up Frequency Detector Down (PFD) Active Blocks /M Inactive Blocks After switching to LTD mode, it can take a maximum of 1 ms for the CDR to get locked to the incoming data and produce a stable recovered clock. The actual lock time depends on the transition density of the incoming data and the PPM difference between the receiver input reference clock and the upstream transmitter reference clock. The receiver PCS logic must be held in reset until the CDR produces a stable recovered clock. f For more information about receiver reset recommendations, refer to the Reset Control and Power Down chapter in volume 2 of the Arria II GX Device Handbook. LTR/LTD Controller The LTR/LTD controller controls whether the CDR is in LTR or LTD mode. Two optional input ports (rx_locktorefclk and rx_locktodata) allow you to configure the LTR/LTD controller in either automatic lock mode or manual lock mode. Table 1-17 shows the relationship between these optional input ports and the LTR/LTD controller lock mode. Table 1-17. Optional Input Ports and LTR/LTD Controller Lock Mode rx_locktorefclk rx_locktodata LTR/LTD Controller Lock Mode 1 0 Manual - LTR Mode x 1 Manual - LTD Mode 0 0 Automatic Lock Mode Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath 1 1-55 If you do not instantiate the optional rx_locktorefclk and rx_locktodata signals, the Quartus II software automatically configures the LTR/LTD controller in automatic lock mode. Automatic Lock Mode In automatic lock mode, the LTR/LTD controller initially sets the CDR to lock to the input reference clock (LTR mode). After the CDR locks to the input reference clock, the LTR/LTD controller automatically sets it to lock to the incoming serial data (LTD mode) when the following three conditions are met: Signal threshold detection circuitry indicates the presence of valid signal levels at the receiver input buffer CDR output clock is within the configured PPM frequency threshold setting with respect to the input reference clock (frequency locked) CDR output clock and input reference clock are phase matched within approximately 0.08 UI (phase locked) The switch from LTR to LTD mode is indicated by the assertion of the rx_freqlocked signal. In LTD mode, the CDR uses a phase detector to keep the recovered clock phase-matched to the data. If the CDR does not stay locked-to-data due to frequency drift or severe amplitude attenuation, the LTR/LTD controller switches the CDR back to LTR mode to lock to the input reference clock. In automatic lock mode, the LTR/LTD controller switches the CDR from LTD to LTR mode when the following conditions are met: Signal threshold detection circuitry indicates the absence of valid signal levels at the receiver input buffer CDR output clock is not in the configured PPM frequency threshold setting with respect to the input reference clock The switch from LTD to LTR mode is indicated by the de-assertion of the rx_freqlocked signal. Manual Lock Mode In automatic lock mode, the LTR/LTD controller relies on the PPM detector and the phase relationship detector to set the CDR in LTR or LTD mode. The PPM detector and phase relationship detector reaction times can be too long for some applications that require faster CDR lock time. You can manually control the CDR to reduce its lock time by using the rx_locktorefclk and rx_locktodata ports. In manual lock mode, the LTR/LTD controller sets the CDR in LTR or LTD mode, depending on the logic level on the rx_locktorefclk and rx_locktodata signals. When the rx_locktorefclk signal is asserted high, the LTR/LTD controller forces the CDR to lock to the reference clock. When the rx_locktodata signal is asserted high, it forces the CDR to lock to data. When both signals are asserted, the rx_locktodata signal takes precedence over the rx_locktorefclk signal, forcing the CDR to lock to data. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-56 Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath When the rx_locktorefclk signal is asserted high, the rx_freqlocked signal does not have any significance and is always driven low, indicating that the CDR is in LTR mode. When the rx_locktodata signal is asserted high, the rx_freqlocked signal is always driven high, indicating that the CDR is in LTD mode. If both signals are de-asserted, the CDR is in automatic lock mode. 1 f The Altera-recommended transceiver reset sequence varies depending on the CDR lock mode. For more information about reset sequence recommendations, refer to the Reset Control and Power Down chapter in volume 2 of the Arria II GX Device Handbook. Deserializer The deserializer block clocks in serial input data from the receiver buffer using the high-speed serial recovered clock and deserializes it using the low-speed parallel recovered clock. It forwards the deserialized data to the receiver PCS channel. In single-width mode, the deserializer supports 8-bit and 10-bit deserialization factors. Figure 1-40 shows the deserializer operation in single-width mode with a 10bit deserialization factor. Figure 1-40. 10-Bit Deserializer Operation in Single-Width Mode Received Data D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 10 Clock Recovery Unit To Word Aligner High-Speed Serial Recovered Clock Low-Speed Parallel Recovered Clock Figure 1-41 shows the serial bit order of the deserializer block input and the parallel data output of the deserializer block in single-width mode with 10-bit deserialization factor. The serial stream (0101111100) is deserialized to a value 10'h17C. The serial data is assumed to be received LSB to MSB. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath 1-57 Figure 1-41. 10-Bit Deserializer Bit Order in Single-Width Mode Low-Speed Parallel Clock High-Speed Serial Clock datain 0 0 1 1 1 1 1 0 dataout 1 0 1 1 0 0 0 0 0 1 0 0101111100 1 1010000011 Word Aligner Because the data is serialized before transmission and then deserialized at the receiver, it loses the word boundary of the upstream transmitter upon deserialization. The word aligner receives parallel data from the deserializer and restores the word boundary based on a pre-defined alignment pattern that must be received during link synchronization. Serial protocols like PCI Express (PIPE), XAUI, Gigabit Ethernet, Serial RapidIO, and SONET/SDH, specify a standard word alignment pattern. For proprietary protocols, the Arria II GX transceiver architecture allows you to select a custom word alignment pattern specific to your implementation. In addition to restoring the word boundary, the word aligner also implements the following features: Synchronization state machine in functional modes like PCI Express (PIPE), XAUI, GIGE, Serial RapidIO, and Basic single-width Programmable run length violation detection in all functional modes Receiver polarity inversion in all functional modes except PCI Express (PIPE) Receiver bit reversal in Basic single-width mode Depending on the configured functional mode, the word aligner operates in one of the following three modes: (c) March 2009 Manual alignment mode Automatic synchronization state machine mode Bit-slip mode Altera Corporation Arria II GX Device Handbook Volume 2 1-58 Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath Figure 1-42 shows the word aligner operation in all supported configurations. Figure 1-42. Word Aligner in All Supported Configurations PMA-PCS Interface Single Width 10-Bit Wide 8-Bit Wide Manual Bit-Slip Alignment (Basic (OC-12, OC-48, Single-Width) Basic Single-Width) Manual Alignment (Basic Single-Width) Bit-Slip (Basic Single-Width, SDI) Automatic Synchronization State Machine (PCI Express [PIPE] XAUI, GIGE, Basic Single-Width, Serial RapidIO) Word Aligner in Single-Width Mode In single-width mode, the PMA-PCS interface is either 8-bit or 10-bit wide. In 8-bit wide PMA-PCS interface modes, the word aligner receives 8-bit wide data from the deserializer. In 10-bit wide PMA-PCS interface modes, the word aligner receives 10-bit wide data from the deserializer. Depending on the configured functional mode, you can configure the word aligner in manual alignment mode, automatic synchronization state machine mode, or bit-slip mode. Word Aligner in Single-Width Mode with 8-Bit PMA-PCS Interface Modes The following functional modes support the 8-bit PMA-PCS interface: SONET/SDH OC-12 SONET/SDH OC-48 Basic single-width Table 1-18 shows the word aligner configurations allowed in functional modes with an 8-bit wide PMA-PCS interface. Table 1-18. Word Aligner Configurations with an 8-Bit Wide PMA-PCS Interface Functional Mode Allowed Word Configurations Allowed Word Alignment Pattern Length SONET/SDH OC-12 Manual Alignment 16 bits SONET/SDH OC-48 Manual Alignment 16 bits Basic single-width Manual Alignment, Bit-Slip 16 bits Manual Alignment Mode Word Aligner in 8-Bit PMA-PCS Interface Modes In manual alignment mode, word aligner operation is controlled by the input signal rx_enapatternalign. Word aligner operation is edge-sensitive to the rx_enapatternalign signal. After de-assertion of rx_digitalreset, a rising edge on the rx_enapatternalign signal triggers the word aligner to look for the word alignment pattern in the received data stream. In SONET/SDH OC-12 and Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath 1-59 OC-48 modes, the word aligner looks for 16'hF628 (A1A2) or 32'hF6F62828 (A1A1A2A2), depending on whether the input signal rx_a1a2size is driven low or high, respectively. In Basic single-width mode, the word aligner looks for the 16-bit word alignment pattern programmed in the ALTGX MegaWizard Plug-In Manager. The word aligner aligns the 8-bit word boundary to the first word alignment pattern received after the rising edge on the rx_enapatternalign signal. Two status signals, rx_syncstatus and rx_patterndetect, with the same latency as the datapath, are forwarded to the FPGA fabric to indicate word aligner status. On receiving the first word alignment pattern after the rising edge on the rx_enapatternalign signal, both the rx_syncstatus and rx_patterndetect signals are driven high for one parallel clock cycle synchronous to the MSByte of the word alignment pattern. Any word alignment pattern received thereafter in the same word boundary causes only the rx_patterndetect signal to go high for one clock cycle. Any word alignment pattern received thereafter in a different word boundary causes only the rx_syncstatus signal to go high for one clock cycle. 1 In order for the word aligner to re-synchronize to a new word boundary, you must de-assert rx_enapatternalign and re-assert it again to create a rising edge. Figure 1-43 shows word aligner behavior in SONET/SDH OC-12 functional mode. The LSByte (8'hF6) and the MSByte (8'h28) of the 16-bit word alignment pattern are received in parallel clock cycles n and n + 1, respectively. The rx_syncstatus and rx_patterndetect signals are both driven high for one parallel clock cycle synchronous to the MSByte (8'h28) of the word alignment pattern. After initial word alignment, the 16-bit word alignment pattern is again received across the word boundary in clock cycles m, m + 1, and m + 2. Because the word alignment pattern is received in a different word boundary, only the rx_syncstatus signal is driven high for one clock cycle. If you create a rising edge on the rx_enapatternalign signal before the word alignment pattern received across clock cycles m, m + 1, and m + 2, the word aligner re-aligns to the new word boundary. Figure 1-43. Bit-Slip Mode in 8-Bit PMA-PCS Interface Mode n rx_dataout[7:0] 11110110 F6 n+1 00101000 28 m m+1 m+2 0110xxxx 10001111 xxxx0010 8F x2 6x rx_enapatternalign rx_patterndetect rx_syncstatus (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-60 Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath Bit-Slip Mode Word Aligner in 8-Bit PMA-PCS Interface Modes Basic single-width mode with 8-bit PMA-PCS interface width allows the word aligner to be configured in bit-slip mode. Word aligner operation is controlled by the input signal rx_bitslip in bit-slip mode. At every rising edge of the rx_bitslip signal, the bit-slip circuitry slips one bit into the received data stream, effectively shifting the word boundary by one bit. In bit-slip mode, the word aligner status signal rx_patterndetect is driven high for one parallel clock cycle when the received data after bit-slipping matches the 16-bit word alignment pattern programmed in the ALTGX MegaWizard Plug-In Manager. You can implement a bit-slip controller in the FPGA fabric that monitors either the rx_dataout signal and/or the rx_patterndetect signal and controls the rx_bitslip signal to achieve word alignment. Figure 1-44 shows an example of word aligner configured in bit-slip mode. For this example, consider that: 8'b11110000 is received back-to-back 16'b0000111100011110 is specified as the word alignment pattern A rising edge on the rx_bitslip signal at time n + 3 slips a single bit 0 at the MSB position, forcing the rx_dataout to 8'b01111000. Another rising edge on the rx_bitslip signal at time n + 5 forces rx_dataout to 8'b00111100. Another rising edge on the rx_bitslip signal at time n + 9 forces rx_dataout to 8'b00011110. Another rising edge on the rx_bitslip signal at time n + 13 forces the rx_dataout to 8'b00001111. At this instance, rx_dataout in cycles n + 12 and n + 13 are 8'b00011110 and 8'b00001111, respectively, which matches the specified 16-bit alignment pattern 16'b0000111100011110. This results in the assertion of the rx_patterndetect signal. Figure 1-44. Example of Word Aligner Configured in Bit-Slip Mode n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n + 9 n + 10 n + 11 n + 12 n + 13 n + 14 rx_clkout 11110000 rx_datain rx_dataout[7:0] 11110000 01111000 00111100 00011110 00001111 rx_bitslip rx_patterndetect Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath 1-61 Word Aligner in Single-Width Mode with 10-Bit PMA-PCS Interface Modes The following functional modes support the 10-bit PMA-PCS interface: PCI Express (PIPE) Gen1 Serial RapidIO XAUI GIGE SDI Basic single-width mode This section covers the following word aligner 10-bit PMA-PCS interface modes: Automatic synchronization state machine mode in 10-bit PMA-PCS interface mode Manual alignment mode in 10-bit PMA-PCS interface mode Bit-slip mode in 10-bit PMA-PCS interface mode Table 1-19 shows the word aligner configurations allowed in functional modes with a 10-bit wide PMA-PCS interface. Table 1-19. Word Aligner Configurations in a 10-Bit Wide PMA-PCS Interface Allowed Word Aligner Configurations Allowed Word Alignment Pattern Length PCI express (PIPE) Automatic Synchronization State Machine 10 bits Serial RapidIO Automatic Synchronization State Machine 10 bits XAUI Automatic Synchronization State Machine 10 bits GIGE Automatic Synchronization State Machine 10 bits SDI Bit-Slip N/A Basic single-width mode Manual Alignment, Automatic Synchronization State Machine, Bit-Slip 7 bits, 10 bits Functional Mode Automatic Synchronization State Machine Mode Word Aligner in 10-Bit PMA-PCS Interface Mode Protocols like PCI Express (PIPE), XAUI, Gigabit Ethernet, and Serial RapidIO require the receiver PCS logic to implement a synchronization state machine to provide hysteresis during link synchronization. Each of these protocols defines a specific number of synchronization code groups that the link must receive in order to acquire synchronization and a specific number of erroneous code groups that it must receive to fall out of synchronization. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-62 Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath In PCI Express (PIPE), XAUI, Gigabit Ethernet, and Serial RapidIO functional modes, the Quartus II software configures the word aligner in automatic synchronization state machine mode. It automatically selects the word alignment pattern length and pattern as specified by each protocol. In each of these functional modes, the protocol-compliant synchronization state machine is implemented in the word aligner. In Basic single-width functional mode with a 10-bit PMA-PCS interface, you can configure the word aligner in automatic synchronization state machine mode by selecting the Use the built-in synchronization state machine option in the ALTGX MegaWizard Plug-In Manager. It also allows you to program a custom 7-bit or 10-bit word alignment pattern that the word aligner uses for synchronization. 1 The 10-bit input data to the word aligner configured in automatic synchronization state machine mode must be 8B/10B encoded. Table 1-20 shows the synchronization state machine parameters that the Quartus II software allows in supported functional modes. The synchronization state machine parameters are fixed for PCI Express (PIPE), XAUI, GIGE, and Serial RapidIO modes as specified by the respective protocol. For Basic single-width mode, you can program these parameters as suited to your proprietary protocol implementation. Table 1-20. Synchronization State Machine Functional Modes PCI Express (PIPE) XAUI GIGE Serial RapidIO Basic SingleWidth Mode Number of valid synchronization code groups or ordered sets received to achieve synchronization 4 4 3 127 1--256 Number of erroneous code groups received to lose synchronization 17 4 4 3 1--64 Number of continuous good code groups received to reduce the error count by one 16 4 4 255 1--256 Functional Mode After de-assertion of the rx_digitalreset signal in automatic synchronization state machine mode, the word aligner starts looking for the word alignment pattern or synchronization code groups in the received data stream. When the programmed number of valid synchronization code groups or ordered sets is received, the rx_syncstatus signal is driven high to indicate that synchronization is acquired. The rx_syncstatus signal is constantly driven high until the programmed number of erroneous code groups is received without receiving intermediate good groups; after which rx_syncstatus is driven low. The word aligner indicates loss of synchronization (rx_syncstatus remains low) until the programmed number of valid synchronization code groups are received again. Manual Alignment Mode Word Aligner in 10-Bit PMA-PCS Interface Mode In Basic single-width mode with a 10-bit PMA-PCS interface, you can configure the word aligner in manual alignment mode by selecting the Use manual word alignment mode option in the ALTGX MegaWizard Plug-In Manager. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath 1-63 In manual alignment mode, word aligner operation is controlled by the input signal rx_enapatternalign. Word aligner operation is level-sensitive to the rx_enapatternalign signal. If the rx_enapatternalign signal is held high, the word aligner looks for the programmed 7-bit or 10-bit word alignment pattern in the received data stream. It updates the word boundary if it finds the word alignment pattern in a new word boundary. If the rx_enapatternalign signal is de-asserted low, the word aligner maintains the current word boundary even when it sees the word alignment pattern in a new word boundary. Two status signals, rx_syncstatus and rx_patterndetect, both with the same latency as the datapath, are forwarded to the FPGA fabric to indicate word aligner status. On receiving the first word alignment pattern after the rx_enapatternalign signal is asserted high, both the rx_syncstatus and rx_patterndetect signals are driven high for one parallel clock cycle. Any word alignment pattern received thereafter in the same word boundary causes only the rx_patterndetect signal to go high for one clock cycle. Any word alignment pattern received thereafter in a different word boundary causes the word aligner to update the word boundary and the rx_syncstatus signal to go high for one clock cycle. Figure 1-45 shows the manual alignment mode word aligner operation in 10-bit PMA-PCS interface mode. In this example, /K28.5/ (10'b0101111100) is specified as the word alignment pattern. The word aligner aligns to the /K28.5/ alignment pattern in cycle n because the rx_enapatternalign signal is asserted high. The rx_syncstatus signal goes high for one clock cycle, indicating alignment to a new word boundary. The rx_patterndetect signal also goes high for one clock cycle to indicate initial word alignment. At time n + 1, the rx_enapatternalign signal is de-asserted to instruct the word aligner to lock the current word boundary. The alignment pattern is detected again in a new word boundary across cycles n + 2 and n + 3. The rx_patterndetect signal remains low and rx_syncstatus goes high for one clock cycle in cycle n + 3 to indicate that the word alignment pattern is found in a new word boundary. The word aligner does not align to this new word boundary because the rx_enapatternalign signal is held low. Figure 1-45. Word Aligner in 10-Bit PMA-PCS Manual Alignment Mode n n+1 n+2 n+3 n+4 n+5 1111001010 1000000101 111110000 0101111100 rx_clkout rx_dataout[10..0] 111110000 0101111100 111110000 rx_enapatternalign rx_patterndetect rx_syncstatus (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-64 Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath 1 If the word alignment pattern is known to be unique and does not appear between word boundaries, you can constantly hold the rx_enapatternalign signal high because there is no possibility of false word alignment. If there is a possibility of the word alignment pattern occurring across word boundaries, you must control the rx_enapatternalign signal to lock the word boundary after the desired word alignment is achieved to avoid re-alignment to an incorrect word boundary. Bit-Slip Mode Word Aligner in 10-Bit PMA-PCS Interface Mode In some Basic single-width configurations with 10-bit PMA-PCS interface mode, you can configure the word aligner in bit-slip mode by selecting the Use manual bit slipping mode option in the ALTGX MegaWizard Plug-In Manager. The word aligner operation for Basic single-width with 10-bit PMA-PCS interface mode is similar to the word aligner operation in Basic single-width mode with 8-bit PMA-PCS interface mode. For word aligner operation in bit-slip mode, refer to "Manual Alignment Mode Word Aligner in 8-Bit PMA-PCS Interface Modes" on page 1-58. The only difference is that the bit-slip word aligner in 10-bit PMA-PCS interface mode allows 7-bit and 10-bit word alignment patterns, whereas the bit-slip word aligner in 8-bit PMA-PCS interface mode allows only 16-bit word alignment pattern. Programmable Run Length Violation Detection The programmable run length violation circuit resides in the word aligner block and detects consecutive 1s or 0s in the data. If the data stream exceeds the preset maximum number of consecutive 1s or 0s, the violation is signified by the assertion of the rx_rlv signal. The run length violation status signal on the rx_rlv port has lower latency compared to the parallel data on the rx_dataout port. The rx_rlv signal in each channel is clocked by its parallel recovered clock. The FPGA fabric clock might have phase difference, PPM difference (in asynchronous systems), or both, with respect to the recovered clock. To ensure that the FPGA fabric clock can latch the rx_rlv signal reliably, the run length violation circuitry asserts the rx_rlv signal for a minimum of two recovered clock cycles in single-width mode. The rx_rlv signal can be asserted longer, depending on the run length of the received data. In single-width mode, the run length violation circuit detects up to a run length of 128 (for an 8-bit deserialization factor) or 160 (for a 10-bit deserialization factor). The settings are in increments of 4 or 5 for the 8-bit or 10-bit deserialization factors, respectively. Table 1-21 summarizes the detection capabilities of the run length violation circuit. Table 1-21. Detection Capabilities of the Run Length Violation Circuit Run Length Violation Detector Range Mode Single-width mode Arria II GX Device Handbook Volume 2 PMA-PCS Interface Width Minimum Maximum 8-bit 4 128 10-bit 5 160 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath 1-65 Receiver Polarity Inversion The positive and negative signals of a serial differential link are often erroneously swapped during board layout. Solutions like board re-spin or major updates to the PLD logic can be expensive. The receiver polarity inversion feature is provided to correct this situation. An optional rx_invpolarity port is available in all single-width modes except PCI Express (PIPE) to dynamically enable the receiver polarity inversion feature. In single-width modes, a high value on the rx_invpolarity port inverts the polarity of every bit of the 8-bit or 10-bit input data word to the word aligner in the receiver data path. Because inverting the polarity of each bit has the same effect as swapping the positive and negative signals of the differential link, correct data is seen by the receiver. The rx_invpolarity signal is dynamic and can cause initial disparity errors in an 8B/10B encoded link. The downstream system must be able to tolerate these disparity errors. The generic receiver polarity inversion feature is different from the PCI Express (PIPE) 8B/10B polarity inversion feature. The generic receiver polarity inversion feature inverts the polarity of the data bits at the input of the word aligner and is not available in PCI Express (PIPE) mode. The PCI Express (PIPE) 8B/10B polarity inversion feature inverts the polarity of the data bits at the input of the 8B/10B decoder and is available only in PCI Express (PIPE) mode. Figure 1-46 shows the receiver polarity inversion feature in single-width 10-bit wide data path configurations. Figure 1-46. 10-Bit Receiver Polarity Inversion in Single-Width Mode 0 1 1 0 0 1 1 0 1 rx _ invpolarity = HIGH 0 1 0 1 0 1 0 0 1 0 Output from Deserializer To Word Aligner 1 Input to Word Aligner Receiver Bit Reversal By default, the Arria II GX receiver assumes a LSBit-to-MSBit transmission. If the transmission order is MSBit-to-LSBit, the receiver forwards the bit-flipped version of the parallel data to the FPGA fabric on the rx_dataout port. The receiver bit reversal feature is available to correct this situation. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-66 Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath The receiver bit reversal feature is available through the rx_revbitordwa port only in Basic single-width mode with the word aligner configured in bit-slip mode. When the rx_revbitordwa signal is driven high in Basic single-width mode, the 8-bit or 10-bit data D[7:0] or D[9:0] at the output of the word aligner gets rewired to D[0:7] or D[0:9], respectively. Flipping the parallel data using this feature allows the receiver to forward the correct bit-ordered data to the FPGA fabric on the rx_dataout port in the case of MSBit-to-LSBit transmission. Figure 1-47 shows the receiver bit reversal feature in Basic single-width 10-bit wide data path configurations. Figure 1-47. 10-Bit Receiver Bit Reversal in Single-Width Mode D[9] D[0] D[8] D[1] D[7] D[2] D[6] D[3] D[5] rx_revbitordwa = high D[4] D[4] D[5] D[3] D[6] D[2] D[7] D[1] D[8] D[0] D[9] Output of Word Aligner before RX bit reversal Output of Word Aligner after RX bit reversal Deskew FIFO Code groups received across four lanes in a XAUI link can be misaligned with respect to one another because of skew in the physical medium or differences between the independent clock recoveries per lane. The XAUI protocol allows a maximum skew of 40 UI (12.8 ns) as seen at the receiver of the four lanes. The XAUI protocol requires the physical layer device to implement deskew circuitry to align all four channels. To enable the deskew circuitry at the receiver to align the four channels, the transmitter sends a /A/ (/K28.3/) code group simultaneously on all four channels during inter-packet gap (IPG). The skew introduced in the physical medium and the receiver channels can cause the /A/ code groups to be received misaligned with respect to each other. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath 1-67 Deskew operation is performed by the deskew circuitry in XAUI functional mode. Deskew circuitry consists of: 1 A 16-word deep deskew FIFO in each of the four channels Control logic in the CMU0 channel of the transceiver block that controls the deskew FIFO write and read operations in each channel Deskew circuitry is only available in XAUI mode. The deskew FIFO in each channel receives data from its word aligner. The deskew operation begins only after link synchronization is achieved on all four channels as indicated by a high level on the rx_syncstatus signal from the word aligner in each channel. Until the first /A/ code group is received, the deskew FIFO read and write pointers in each channel are not incremented. After the first /A/ code group is received, the write pointer starts incrementing for each word received but the read pointer is frozen. If the /A/ code group is received on each of the four channels in 10 recovered clock cycles of each other, the read pointer of all four deskew FIFOs is released simultaneously, aligning all four channels. Figure 1-48 shows lane skew at the receiver input and how the deskew FIFO uses the /A/ code group to align the channels. Figure 1-48. Deskew FIFO--Lane Skew at the Receiver Input Lane 0 K K Lane 1 Lane 2 K Lane 3 R A K R R K K R K R K K R A K R R K K R K K R A K R R K K R K R K K R A K R R K K R K R Lanes Skew at Receiver Input R Lane 0 K K R A K R R K K R K R Lane 1 K K R A K R R K K R K R Lane 2 K K R A K R R K K R K R Lane 3 K K R A K R R K K R K R Lanes are Deskewed by Lining up the "Align"/A/, Code Groups After alignment of the first ||A|| column, if three additional aligned ||A|| columns are observed at the output of the deskew FIFOs of the four channels, the rx_channelaligned signal is asserted high, indicating channel alignment is acquired. After acquiring channel alignment, if four misaligned ||A|| columns are seen at the output of the deskew FIFOs in all four channels with no aligned ||A|| columns in between, the rx_channelaligned signal is de-asserted low, indicating loss of channel alignment. Deskew operation in XAUI functional mode is compliant to the PCS deskew state machine diagram specified in clause 48 of the IEEE P802.3ae, as shown in Figure 1-49. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-68 Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath Figure 1-49. Deskew FIFO Operation in XAUI Functional Mode (Note 1) reset + (sync_status=FAIL * SUDI) LOSS_OF_ALIGNMENT SUDI(![/||A||/]) align_status FAIL enable_deskew TRUE AUDI sync_status OK * SUDI(![/||A||/]) ALIGN_DETECT_1 !deskew_error * SUDI(![/||A||/]) enable_deskew FALSE AUDI deskew_error * SUDI SUDI(![/||A||/]) ALIGN_DETECT_2 AUDI !deskew_error * SUDI(![/||A||/]) deskew_error * SUDI SUDI(![/||A||/]) ALIGN_DETECT_3 AUDI !deskew_error * SUDI(![/||A||/]) deskew_error * SUDI 1 SUDI(![/||A||/]) ALIGN_ACQUIRED_1 !deskew_error * SUDI(![/||A||/]) enable_deskew FALSE AUDI deskew_error * SUDI 2 SUDI(![/||A||/]) ALIGN_ACQUIRED_2 AUDI !deskew_error * SUDI(![/||A||/]) deskew_error * SUDI 3 SUDI(![/||A||/]) 1 ALIGN_ACQUIRED_3 AUDI !deskew_error * SUDI(![/||A||/]) deskew_error * SUDI SUDI(![/||A||/]) 2 ALIGN_ACQUIRED_4 AUDI deskew_error * SUDI !deskew_error * SUDI(![/||A||/]) SUDI(![/||A||/]) 3 Note to Figure 1-49: (1) Source: IEEE P802.3ae TM -2002, IEEE Standard for Information technology - Telecommunications and information exchange between systems Local and metropolitan area networks - Specific requirements Part 3: Carrier sense multiple access with collision detection (CSMA/CD) access method and physical layer specifications. Rate Match (Clock Rate Compensation) FIFO In asynchronous systems, the upstream transmitter and local receiver can be clocked with independent reference clocks. Frequency differences in the order of a few hundred PPM can corrupt the data when latching from the recovered clock domain (the same clock domain as the upstream transmitter reference clock) to the local receiver reference clock domain. The rate match FIFO compensates for small clock frequency differences between the upstream transmitter and the local receiver clocks by inserting or removing SKP symbols or ordered-sets from the IPG or idle streams. It deletes SKP symbols or ordered-sets when the upstream transmitter reference clock frequency is higher than the local receiver reference clock frequency. It inserts SKP symbols or ordered-sets when the local receiver reference clock frequency is higher than the upstream transmitter reference clock frequency. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath 1-69 Rate match FIFO consists of a 20-word deep FIFO and necessary logic that controls insertion and deletion of a SKP character or ordered-set, depending on the PPM difference. Rate match FIFO is mandatory and cannot be bypassed in the following functional modes: PCI Express (PIPE) XAUI GIGE Rate match FIFO is optional in the following functional modes: Basic single-width Rate match FIFO receives data from the word aligner (non-XAUI functional modes) or deskew FIFO (XAUI functional mode) in the receiver datapath. It provides the following status signals forwarded to the FPGA fabric: 1 rx_rmfifodatainserted--indicates insertion of a skip character or ordered-set rx_rmfifodatadeleted--indicates deletion of a skip character or ordered-set rx_rmfifofull--indicates rate match FIFO full condition rx_rmfifoempty--indicates rate match FIFO empty condition Rate match FIFO status signals are not available in PCI Express (PIPE) mode. These signals are encoded on the pipestatus[2:0] signal in PCI Express (PIPE) mode, as specified in the PIPE specification. Rate Match FIFO in PCI Express (PIPE) Mode In PCI Express (PIPE) mode, the rate match FIFO is capable of compensating up to 300 PPM (total 600 PPM) difference between the upstream transmitter and the local receiver. The PCI Express (PIPE) protocol requires the transmitter to send SKP ordered sets during IPGs, adhering to rules listed in the base specification. The SKP ordered set is defined as a /K28.5/ COM symbol followed by three consecutive /K28.0/ SKP symbol groups. The PCI Express (PIPE) protocol requires the receiver to recognize a SKP ordered set as a /K28.5/ COM symbol followed by one-to-five consecutive /K28.0/ SKP symbols. Rate match FIFO operation is compliant to PCI Express Base Specification 1.1. The rate match operation begins after the synchronization state machine in the word aligner indicates synchronization is acquired by driving the rx_syncstatus signal high. The rate match FIFO looks for the SKP ordered set and deletes or inserts SKP symbols as necessary to prevent the rate match FIFO from overflowing or under running. The rate match FIFO inserts or deletes only one SKP symbol per SKP ordered set received. Rate match FIFO insertion and deletion events are communicated to the FPGA fabric on the pipestatus[2:0] port from each channel. The pipestatus[2:0] signal is driven to 3'b001 for one clock cycle synchronous to the /K28.5/ COM symbol of the SKP ordered set in which the /K28.0/ SKP symbol is inserted. The pipestatus[2:0] signal is driven to 3'b010 for one clock cycle synchronous to the /K28.5/ COM symbol of the SKP ordered set from which the /K28.0/ SKP symbol is deleted. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-70 Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath Figure 1-50 shows an example of rate match deletion in the case where two /K28.0/ SKP symbols are required to be deleted. Only one /K28.0/ SKP symbol is deleted per SKP ordered set received. Figure 1-50. Example of Rate Match Deletion in PCI Express (PIPE) Mode SKIP Symbol Deleted First Skip Ordered Set Second Skip Ordered Set datain K28.5 K28.0 Dx.y K28.5 K28.0 dataout K28.5 Dx.y K28.5 K28.0 K28.0 K28.0 pipestatus[2:0] 3'b010 xxx 3'b010 xxx xxx xxx K28.0 K28.0 Figure 1-51 shows an example of rate match insertion in the case where two SKP symbols are required to be inserted. Only one /K28.0/ SKP symbol is inserted per SKP ordered set received. Figure 1-51. Example of Rate Match Insertion in PCI Express (PIPE) Mode SKIP Symbol Inserted First Skip Ordered Set Second Skip Ordered Set datain K28.5 K28.0 Dx.y K28.5 K28.0 K28.0 K28.0 K28.0 dataout K28.5 K28.0 K28.0 Dx.y K28.5 K28.0 K28.0 K28.0 K28.0 K28.0 pipestatus[2:0] 3'b001 xxx xxx xxx 3'b001 xxx xxx xxx xxx xxx Rate match FIFO full and empty conditions are communicated to the FPGA fabric on the pipestatus[2:0] port from each channel. Rate match FIFO in PCI Express (PIPE) mode automatically deletes the data byte that causes the FIFO to go full and drives pipestatus[2:0] = 3'b101 synchronous to the subsequent data byte. Figure 1-52 shows the rate match FIFO full condition in PCI Express (PIPE) mode. The rate match FIFO becomes full after receiving data byte D4. Figure 1-52. Example of Rate Match FIFO Full Condition in PCI Express (PIPE) Mode datain D1 D2 D3 D4 D5 D6 D7 dataout D1 D2 D3 D4 D6 D7 D8 xx pipestatus[2:0] xxx xxx xxx xxx xxx xxx xxx 3'b101 D8 xx xx The rate match FIFO automatically inserts /K30.7/ (9'h1FE) after the data byte that causes the FIFO to go empty and drives the pipestatus[2:0] = 3'b110 flag synchronous to the inserted /K30.7/ (9'h1FE). Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath 1-71 Figure 1-53 shows rate match FIFO empty condition in PCI Express (PIPE) mode. The rate match FIFO becomes empty after reading out data byte D3. Figure 1-53. Example of Rate Match FIFO Empty Condition in PCI Express (PIPE) Mode datain D1 D2 D3 D4 D5 D6 dataout D1 D2 D3 /K30.7/ D4 D5 xxx xxx 3'b110 xxx xxx pipestatus[2:0] 1 xxx You can configure the rate match FIFO in low-latency mode by turning off the Enable Rate Match FIFO option in the ALTGX MegaWizard Plug-In Manager. Rate Match FIFO in XAUI Mode In XAUI mode, the rate match FIFO is capable of compensating up to 100 PPM (total 200 PPM total) difference between the upstream transmitter and the local receiver reference clock. The XAUI protocol requires the transmitter to send /R/ (/K28.0/) code groups simultaneously on all four lanes (denoted as ||R|| column) during inter-packet gaps, adhering to rules listed in the IEEE P802.3ae specification. Rate match FIFO operation in XAUI mode is compliant to the IEEE P802.3ae specification. Rate match operation begins after: The synchronization state machine in the word aligner of all four channels indicates synchronization was acquired by driving its rx_syncstatus signal high The deskew FIFO block indicates alignment was acquired by driving the rx_channelaligned signal high Rate match FIFO looks for the ||R|| column (simultaneous /R/ code group on all four channels) and deletes or inserts ||R|| column to prevent the rate match FIFO from overflowing or under running. It can insert or delete as many ||R|| columns as necessary to perform the rate match operation. Two flags, rx_rmfifodatadeleted and rx_rmfifodatainserted, that indicate rate match FIFO deletion and insertion events, respectively, are forwarded to the FPGA fabric. If an ||R|| column is deleted, the rx_rmfifodeleted flag from each of the four channels goes high for one clock cycle per deleted ||R|| column. If an ||R|| column is inserted, the rx_rmfifoinserted flag from each of the four channels goes high for one clock cycle per inserted ||R|| column. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-72 Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath Figure 1-54 shows an example of rate match deletion in the case where three ||R|| columns are required to be deleted. Figure 1-54. Example of Rate Match Deletion in XAUI Mode First ||R|| Column Second ||R|| Column Third ||R|| Column Fourth ||R|| Column datain[3] K28.5 K28.3 K28.5 K28.0 K28.5 K28.0 K28.0 K28.0 K28.5 datain[2] K28.5 K28.3 K28.5 K28.0 K28.5 K28.0 K28.0 K28.0 K28.5 datain[1] K28.5 K28.3 K28.5 K28.0 K28.5 K28.0 K28.0 K28.0 K28.5 datain[0] K28.5 K28.3 K28.5 K28.0 K28.5 K28.0 K28.0 K28.0 K28.5 dataout[3] K28.5 K28.3 K28.5 K28.5 K28.0 K28.5 dataout[2] K28.5 K28.3 K28.5 K28.5 K28.0 K28.5 dataout[1] K28.5 K28.3 K28.5 K28.5 K28.0 K28.5 dataout[0] K28.5 K28.3 K28.5 K28.5 K28.0 K28.5 rx_rmfifodatadeleted Figure 1-55 shows an example of rate match insertion in the case where two ||R|| columns are required to be inserted. Figure 1-55. Example of Rate Match Insertion in XAUI Mode First ||R|| Column Second ||R|| Column datain[3] K28.5 K28.3 K28.5 K28.0 K28.5 K28.0 datain[2] K28.5 K28.3 K28.5 K28.0 K28.5 K28.0 datain[1] K28.5 K28.3 K28.5 K28.0 K28.5 K28.0 datain[0] K28.5 K28.3 K28.5 K28.0 K28.5 K28.0 dataout[3] K28.5 K28.3 K28.5 K28.0 K28.0 K28.0 K28.5 K28.0 dataout[2] K28.5 K28.3 K28.5 K28.0 K28.0 K28.0 K28.5 K28.0 dataout[1] K28.5 K28.3 K28.5 K28.0 K28.0 K28.0 K28.5 K28.0 dataout[0] K28.5 K28.3 K28.5 K28.0 K28.0 K28.0 K28.5 K28.0 rx_rmfifodatainserted Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath 1-73 Two flags, rx_rmfifofull and rx_rmfifoempty, are forwarded to the FPGA fabric to indicate rate match FIFO full and empty conditions. In XAUI mode, the rate match FIFO does not automatically insert or delete code groups to overcome FIFO empty and full conditions, respectively. It asserts the rx_rmfifofull and rx_rmfifoempty flags for at least three recovered clock cycles to indicate rate match FIFO full and empty conditions, respectively. 1 In case of rate match FIFO full and empty conditions, you must assert the rx_digitalreset signal to reset the receiver PCS blocks. Rate Match FIFO in GIGE Mode In GIGE mode, the rate match FIFO is capable of compensating up to 100 PPM (total 200 PPM total) difference between the upstream transmitter and the local receiver reference clock. The GIGE protocol requires the transmitter to send idle ordered sets /I1/ (/K28.5/D5.6/) and /I2/ (/K28.5/D16.2/) during inter-packet gaps, adhering to rules listed in the IEEE 802.3 specification. Rate match operation begins after the synchronization state machine in the word aligner indicates synchronization is acquired by driving the rx_syncstatus signal high. The rate match FIFO is capable of deleting or inserting the /I2/ (/K28.5/D16.2/) ordered set to prevent the rate match FIFO from overflowing or under running during normal packet transmission. The rate match FIFO is also capable of deleting or inserting the first two bytes of the /C2/ ordered set (/K28.5/D2.2/Dx.y/Dx.y/) to prevent the rate match FIFO from overflowing or under running during the auto negotiation phase. Rate match FIFO can insert or delete as many /I2/ or /C2/ (first two bytes) as necessary to perform the rate match operation. Two flags, rx_rmfifodatadeleted and rx_rmfifodatainserted, that indicate rate match FIFO deletion and insertion events, respectively, are forwarded to the FPGA fabric. Both the rx_rmfifodatadeleted and rx_rmfifodatainserted flags are asserted for two clock cycles for each deleted and inserted /I2/ ordered-set, respectively. Figure 1-56 shows an example of rate match FIFO deletion in the case where three symbols are required to be deleted. Because the rate match FIFO can only delete /I2/ ordered-set, it deletes two /I2/ ordered-sets (four symbols deleted). Figure 1-56. Example of Rate Match Deletion in GIGE Mode /I2/ Ordered-Set Deleted First /I2/ Ordered Set Second /I2/ Ordered Set datain Dx.y K28.5 D16.2 K28.5 dataout Dx.y K28.5 D16.2 Dx.y D16.2 Third /I2/ Ordered Set K28.5 D16.2 Dx.y rx_rmfifodatadeleted (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-74 Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath Figure 1-57 shows an example of rate match FIFO insertion in the case where one symbol is required to be inserted. Because the rate match FIFO can only delete /I2/ ordered-set, it inserts one /I2/ ordered-sets (two symbols inserted). Figure 1-57. Example of Rate Match Insertion in GIGE Mode First /I2/ Ordered Set Second /I2/ Ordered Set datain Dx.y K28.5 D16.2 K28.5 D16.2 dataout Dx.y K28.5 D16.2 K28.5 D16.2 K28.5 D16.2 Dx.y rx_rmfifodatainserted Two flags, rx_rmfifofull and rx_rmfifoempty, are forwarded to the FPGA fabric to indicate rate match FIFO full and empty conditions. In GIGE mode, the rate match FIFO does not insert or delete code groups automatically to overcome FIFO empty and full conditions, respectively. It asserts the rx_rmfifofull and rx_rmfifoempty flags for at least two recovered clock cycles to indicate rate match FIFO full and empty conditions, respectively. 1 In case of rate match FIFO full and empty conditions, you must assert the rx_digitalreset signal to reset the receiver PCS blocks. Rate Match FIFO in Basic Single-Width Mode In Basic single-width mode, the rate match FIFO is capable of compensating up to 300 PPM (total 600 PPM total) difference between the upstream transmitter and the local receiver reference clock. 1 To enable the rate match FIFO in Basic single-width mode, the transceiver channel must have both the transmitter and receiver channels instantiated. You must select the Receiver and Transmitter option in the What is the operation mode? field in the ALTGX MegaWizard Plug-In Manager. You must also enable the 8B/10B encoder/decoder in Basic single-width mode with rate match FIFO enabled. Depending on your proprietary protocol implementation, you can select two 20-bit rate match patterns in the ALTGX MegaWizard Plug-In Manager under the What is the rate match pattern1 and What is the rate match pattern2 fields. Each of the two programmed 20-bit rate match patterns consists of a 10-bit skip pattern and a 10-bit control pattern. You must choose 10-bit code groups that have a neutral disparity as the skip patterns. The rate match FIFO operation begins after the word aligner synchronization status rx_syncstatus goes high. When the rate matcher receives either of the two 10-bit control patterns followed by the respective 10-bit skip pattern, it inserts or deletes the 10-bit skip pattern as necessary to avoid the rate match FIFO from overflowing or under running. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath 1-75 Rate match FIFO can delete a maximum of four skip patterns from a cluster, provided there is one skip pattern left in the cluster after deletion. The rate match FIFO can insert a maximum of four skip patterns in a cluster, provided there are no more than five skip patterns in the cluster after insertion. Two flags, rx_rmfifodatadeleted and rx_rmfifodatainserted, indicating rate match FIFO deletion and insertion events, respectively, are forwarded to the FPGA fabric. Figure 1-58 shows an example of rate match FIFO deletion in the case where three skip patterns are required to be deleted. In this example, /K28.5/ is the control pattern and neutral disparity /K28.0/ is the skip pattern. The first skip cluster has a /K28.5/ control pattern followed by two /K28.0/ skip patterns. The second skip cluster has a /K28.5/ control pattern followed by four /K28.0/ skip patterns. The rate match FIFO deletes only one /K28.0/ skip pattern from the first skip cluster to maintain at least one skip pattern in the cluster after deletion. Two /K28.0/ skip patterns are deleted from the second cluster for a total of three skip patterns deleted. Figure 1-58. Example of Rate Match Deletion in Basic Single-Width Mode Three Skip Patterns Deleted Second Skip Cluster First Skip Cluster datain K28.5 K28.0 K28.0 K28.5 K28.0 K28.0 dataout K28.5 K28.0 K28.5 K28.0 K28.0 K28.0 K28.0 K28.0 rx_rmfifodatadeleted Figure 1-59 shows an example of rate match FIFO insertion in the case where three skip patterns are required to be inserted. In this example, /K28.5/ is the control pattern and neutral disparity /K28.0/ is the skip pattern. The first skip cluster has a /K28.5/ control pattern followed by three /K28.0/ skip patterns. The second skip cluster has a /K28.5/ control pattern followed by one /K28.0/ skip pattern. The rate match FIFO inserts only two /K28.0/ skip patterns into the first skip cluster to maintain a maximum of five skip patterns in the cluster after insertion. One /K28.0/ skip pattern is inserted into the second cluster for a total of three skip patterns inserted. Figure 1-59. Example of Rate Match Insertion in Basic Single-Width Mode Three Skip Patterns Inserted First Skip Cluster Second Skip Cluster datain K28.5 K28.0 K28.0 K28.0 K28.5 K28.0 K28.0 Dx.y dataout K28.5 K28.0 K28.0 K28.0 K28.0 K28.0 K28.5 K28.0 K28.0 K28.0 Dx.y rx_rmfifoinserted (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-76 Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath Two flags, rx_rmfifofull and rx_rmfifoempty, are forwarded to the FPGA fabric to indicate rate match FIFO full and empty conditions. The rate match FIFO in Basic single-width mode automatically deletes the data byte that causes the FIFO to go full and asserts the rx_rmfifofull flag synchronous to the subsequent data byte. Figure 1-60 shows the rate match FIFO full condition in Basic single-width mode. The rate match FIFO becomes full after receiving data byte D4. Figure 1-60. Rate Match FIFO Full Condition in Basic Single-Width Mode datain D1 D2 D3 D4 D5 D6 D7 dataout D1 D2 D3 D4 D6 D7 D8 D8 xx xx xx rx_rmfifofull The rate match FIFO automatically inserts /K30.7/ (9'h1FE) after the data byte that causes the FIFO to go empty and asserts the rx_fifoempty flag synchronous to the inserted /K30.7/ (9'h1FE). Figure 1-61 shows rate match FIFO empty condition in Basic single-width mode. The rate match FIFO becomes empty after reading out data byte D3. Figure 1-61. Rate Match FIFO Empty Condition in Basic Single-Width Mode datain D1 D2 D3 D4 D5 D6 dataout D1 D2 D3 /K30.7/ D4 D5 rx_rmfifoempty 8B/10B Decoder Protocols like PCI Express (PIPE), XAUI, GIGE, and Serial RapidIO require the serial data sent over the link to be 8B/10B encoded to maintain the DC balance in the serial data transmitted. These protocols require the receiver PCS logic to implement an 8B/10B decoder to decode the data before forwarding it to the upper layers for packet processing. The Arria II GX receiver channel PCS datapath implements the 8B/10B decoder after the rate matcher. In functional modes with rate matcher enabled, the 8B/10B decoder receives data from the rate matcher. In functional modes with rate matcher disabled, the 8B/10B decoder receives data from the word aligner. The Arria II GX 8B/10B decoder operates in single-width mode only. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath 1-77 8B/10B Decoder in Single-Width Mode Figure 1-62 shows the block diagram of the 8B/10B decoder in single-width mode. Figure 1-62. 8B/10B Decoder in Single-Width Mode datain[9:0] rx_dataout[7:0] rx_ctrldetect[0] 8B/10B Decoder rx_errdetect[0] rx_disperr[0] recovered clock or tx_clkout[0] In single-width mode, the 8B/10B decoder receives 10-bit data from the rate matcher or word aligner (when rate matcher is disabled) and decodes it into an 8-bit data + 1-bit control identifier. The decoded data is fed to the byte deserializer or the receiver phase compensation FIFO (if byte deserializer is disabled). 1 The 8B/10B decoder is compliant to Clause 36 in the IEEE802.3 specification. The 8B/10B decoder operates in single-width mode in the following functional modes: PCI Express (PIPE) XAUI GIGE Serial RapidIO Basic single-width For PCI Express (PIPE), XAUI, GIGE, and Serial RapidIO functional modes, the ALTGX MegaWizard Plug-In Manager forces selection of the 8B/10B decoder in the receiver datapath. In Basic single-width mode, it allows you to enable or disable the 8B/10B decoder depending on your proprietary protocol implementation. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-78 Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath Figure 1-63 shows a 10-bit code group decoded into an 8-bit data and a 1-bit control identifier by the 8B/10B decoder in single-width mode. Figure 1-63. 8B/10B Decoder in Single-Width Mode j h g f i e d c b a 9 8 7 6 5 4 3 2 1 0 MSB Received Last LSB Received First 8B/10B Conversion ctrl 7 6 5 4 3 2 1 0 H G F E D C B A Parallel Data Control Code Group Detection The 8B/10B decoder indicates whether the decoded 8-bit code group is a data or control code group on the rx_ctrldetect port. If the received 10-bit code group is one of the 12 control code groups (/Kx.y/) specified in the IEEE802.3 specification, the rx_ctrldetect signal is driven high. If the received 10-bit code group is a data code group (/Dx.y/), the rx_ctrldetect signal is driven low. Figure 1-64 illustrates the 8B/10B decoder decoding the received 10-bit /K28.5/ control code group into an 8-bit data code group (8'hBC) driven on the rx_dataout port. rx_ctrldetect is asserted high synchronous with 8'hBC on the rx_dataout port, indicating that it is a control code group. The rest of the codes received are data code groups /Dx.y/. Figure 1-64. 8B/10B Decoder in Control Code Group Detection clock datain[9..0 ] D3.4 D24.3 D28.5 D28.5 D15.0 D0.0 D31.5 D28.1 83 78 BC BC 0F 00 BF 3C rx_ctrldetect rx_dataout[7..0] Control Code Group Detection Figure 1-65 shows 8B/10B decoding of the received 10-bit /K28.5/ control code group into 8-bit data code group (8'hBC) driven on the rx_dataout port. The rx_ctrldetect is asserted high synchronous with 8'hBC on the rx_dataout port, indicating that it is a control code group. The rest of the codes received are data code groups /Dx.y/. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath 1-79 Figure 1-65. 8B/10B Decoder 10-Bit Control Code Group clock datain[19:10] D3.4 D28.5 D15.0 D3.4 datain[9:0] D24.3 D28.5 D15.0 D3.4 rx_ctrldetect[1:0] 00 01 rx_dataout[15:0] 16'h8378 16'hBCBC 00 16'h0F0F 16'h8383 Byte Deserializer The FPGA fabric-transceiver interface frequency has an upper limit of 200 MHz. In functional modes that have a receiver PCS frequency greater than 200 MHz, the parallel received data and status signals cannot be forwarded directly to the FPGA fabric because it violates the upper limit of the 200 MHz FPGA fabric--transceiver interface frequency. In such configurations, the byte deserializer is required to reduce the FPGA fabric--transceiver interface frequency to half while doubling the parallel data width. For example, at 3.2 Gbps data rate with a deserialization factor of 10, the receiver PCS datapath runs at 320 MHz. The 10-bit parallel received data and status signals at 320 MHz cannot be forwarded to the FPGA fabric because it violates the upper limit of 200 MHz. The byte serializer converts the 10-bit parallel received data at 320 MHz into 20-bit parallel data at 160 MHz before forwarding to the FPGA fabric. 1 The byte deserializer is required in configurations that exceed the FPGA fabric--transceiver interface clock upper frequency limit. It is optional in configurations that do not exceed the FPGA fabric--transceiver interface clock upper frequency limit. The Arria II GX byte deserializer operates in single-width mode only. Byte Deserializer in Single-Width Mode In single-width mode, the byte deserializer receives 8-bit wide data from the 8B/10B decoder or 10-bit wide data from the word aligner (if the 8B/10B decoder is disabled) and deserializes it into 16-bit or 20-bit wide data at half the speed. Figure 1-66 shows the block diagram of the byte deserializer in single-width mode. Figure 1-66. Byte Deserializer in Single-Width Mode datain[7:0] or datain[9:0] D1 D2 D3 D4 Byte Deserializer D2 D4 D1 D3 dataout[15:0] or dataout[19:0] /2 Receiver PCS Clock (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-80 Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath Byte Ordering Block In single-width modes with the 16-bit or 20-bit FPGA fabric--transceiver interface, the byte deserializer receives one data byte (8- or 10-bit) and deserializes it into two data bytes (16- or 20-bit). Depending on when the receiver PCS logic comes out of reset, the byte ordering at the output of the byte deserializer may or may not match the original byte ordering of the transmitted data. The byte misalignment resulting from byte deserialization is unpredictable because it depends on which byte is being received by the byte deserializer when it comes out of reset. Figure 1-67 shows a scenario in which the MSByte and LSByte of the two-byte transmitter data appears straddled across two word boundaries after getting byte deserialized at the receiver. Figure 1-67. MSByte and LSByte of the Two-Byte Transmitter Data Straddled Across Two Word Boundaries Transmitter tx_datain[15:8] (MSByte) D2 D4 D6 tx_datain[7:0] (LSByte) D1 D3 D5 Byte Serializer Receiver xx D1 D2 D3 D4 D5 D6 xx Byte Deserializer D1 D3 D5 xx rx_dataout[15:8] (MSByte) xx D2 D4 D6 rx_dataout[7:0] (LSByte) Arria II GX transceivers have an optional byte ordering block in the receiver data path that you can use to restore proper byte ordering before forwarding the data to the FPGA fabric. The byte ordering block looks for the user-programmed byte ordering pattern in the byte-deserialized data. You must select a byte ordering pattern that you know appears at the LSByte/LSBytes position of the parallel transmitter data. If the byte ordering block finds the programmed byte ordering pattern in the MSByte/MSBytes position of the byte-deserialized data, it inserts the appropriate number of user-programmed PAD bytes to push the byte ordering pattern to the LSByte/LSBytes position, thereby restoring proper byte ordering. Byte Ordering Block in Single-Width Modes The byte ordering block is available in the following single-width functional modes: SONET/SDH OC-48 Basic single-width mode with: 16-bit FPGA fabric--transceiver interface No 8B/10B decoder (8-bit PMA-PCS interface) Word aligner in manual alignment mode Basic single-width mode with: 16-bit FPGA fabric--transceiver interface 8B/10B decoder Word aligner in automatic synchronization state machine mode Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath 1 1-81 For more information about configurations that allow the byte ordering block in the receiver datapath, refer to "Basic Single-Width Mode Configurations" on page 1-86. The Quartus II software automatically configures the byte ordering pattern and byte ordering PAD pattern for SONET/SDH OC-48 functional mode. For more information, refer to "OC-48 Byte Ordering" on page 1-126. In Basic single-width mode, you can program a custom byte ordering pattern and byte ordering PAD pattern in the ALTGX MegaWizard Plug-In Manager. Table 1-22 shows the byte ordering pattern length allowed in Basic single-width mode. Table 1-22. Byte Ordering Pattern Length in Basic Single-Width Mode Functional Mode Basic single-width mode with: 16-bit FPGA fabric-transceiver interface no 8B/10B decoder Word aligner in manual alignment mode Basic single-width mode with: 16-bit FPGA fabric-transceiver interface 8B/10B decoder Word aligner in automatic synchronization state machine mode Byte Ordering Pattern Length Byte Ordering PAD Pattern Length 8-bit 8-bit 9-bit (1) 9-bit Note to Table 1-22: (1) If a /Kx.y/ control code group is selected as the byte ordering pattern, the MSB of the 9-bit byte ordering pattern must be 1'b1. If a /Dx.y/ data code group is selected as the byte ordering pattern, the MSB of the 9-bit byte ordering pattern must be 1'b0. The least significant 8 bits must be the 8B/10B decoded version of the code group used for byte ordering. The byte ordering block modes of operation in single-width mode: Word-alignment-based byte ordering User-controlled byte ordering Word-Alignment-Based Byte Ordering In word-alignment-based byte ordering, the byte ordering block starts looking for the byte ordering pattern in the byte-deserialized data every time it sees a rising edge on the rx_syncstatus signal. After a rising edge on the rx_syncstatus signal, if the byte ordering block finds the first data byte that matches the programmed byte ordering pattern in the MSByte position of the byte-deserialized data, it inserts one programmed PAD pattern to push the byte ordering pattern into the LSByte position. If the byte ordering blocks finds the first data byte that matches the programmed byte ordering pattern in the LSByte position of the byte-deserialized data, it considers the data to be byte ordered and does not insert any PAD pattern. In either case, the byte ordering block asserts the rx_byteorderalignstatus signal. 1 (c) March 2009 You can choose word-alignment-based byte ordering by selecting the sync status signal from the word aligner option in the What do you want the byte ordering to be based on? field in the ALTGX MegaWizard Plug-In Manager. Altera Corporation Arria II GX Device Handbook Volume 2 1-82 Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath Figure 1-68 shows an example of the byte ordering operation in single-width modes. In this example, A is the programmed byte ordering pattern and PAD is the programmed PAD pattern. The byte deserialized data places the byte ordering pattern A in the MSByte position resulting in incorrect byte ordering. Assuming that a rising edge on the rx_syncstatus signal had occurred before the byte ordering block sees the byte ordering pattern A in the MSByte position, the byte ordering block inserts a PAD byte and pushes the byte ordering pattern A into the LSByte position. The data at the output of the byte ordering block has correct byte ordering as reflected on the rx_byteorderalignstatus signal. Figure 1-68. Example of Byte Ordering in Single-Width Modes Transmitter tx_datain[15:8] tx_datain[7:0] D2 D1 D3 A D5 D4 Channel Byte Serializer Receiver Byte Deserializer D1 A xx D2 D4 D3 Byte Ordering D1 PAD D3 D5 rx_dataout[15:8] xx D2 A D4 rx_dataout[7:0] rx_byteorderalignstatus If the byte ordering block sees another rising edge on the rx_syncstatus signal from the word aligner, it de-asserts the rx_byteorderalignstatus signal and repeats the byte ordering operation as previously discussed. User-Controlled Byte Ordering Unlike word-alignment-based byte ordering, user-controlled byte ordering provides control to the user logic to restore correct byte ordering at the receiver. When enabled, an rx_enabyteord port is available that you can use to trigger the byte ordering operation. A rising edge on the rx_enabyteord port triggers the byte ordering block. After a rising edge on the rx_enabyteord signal, if the byte ordering block finds the first data byte that matches the programmed byte ordering pattern in the MSByte position of the byte-deserialized data, it inserts one programmed PAD pattern to push the byte ordering pattern into the LSByte position. If the byte ordering blocks find the first data byte that matches the programmed byte ordering pattern in the LSByte position of the byte-deserialized data, it considers the data to be byte ordered and does not insert any PAD byte. In either case, the byte ordering block asserts the rx_byteorderalignstatus signal. Receiver Phase Compensation FIFO The receiver phase compensation FIFO in each channel ensures reliable transfer of data and status signals between the receiver channel and the FPGA fabric. The receiver phase compensation FIFO compensates for the phase difference between the parallel receiver PCS clock (FIFO write clock) and the FPGA fabric clock (FIFO read clock). Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Receiver Channel Datapath 1-83 The receiver phase compensation FIFO operates in one of the following two modes: Low latency mode--The Quartus II software automatically configures the receiver phase compensation FIFO in low latency mode in all functional modes except PCI Express (PIPE). In this mode, the FIFO is four words deep and the latency through the FIFO is 2-to-3 parallel clock cycles (pending characterization). High latency mode--The Quartus II software automatically configures the receiver phase compensation FIFO in high latency mode in PCI Express (PIPE) functional mode. In this mode, the FIFO is eight words deep and the latency through the FIFO is 4-to-5 parallel clock cycles (pending characterization). Registered mode --The Quartus II software configures the receiver phase compensation FIFO in registered mode if the selection is made in the ALTGX MegaWizard Plug-In Manager. In this mode, latency uncertainty through the receiver phase compensation FIFO is 0 cycles. This mode is available for CPRI data rates in Basic functional mode. For more information, refer to "Basic Functional Mode" on page 1-85. The receiver phase compensation FIFO write clock source varies with the receiver channel configuration. Table 1-23 shows the receiver phase compensation FIFO write clock source in different configurations. Table 1-23. Receiver Phase Compensation FIFO Write Clock Source Receiver Phase Compensation FIFO Write Clock Configuration Without Byte Serializer With Byte Serializer Non-bonded channel configuration with rate matcher Parallel transmitter PCS clock from the local clock divider in the associated channel (tx_clkout) Divide-by-two version of the parallel transmitter PCS clock from the local clock divider in the associated channel (tx_clkout) Non-bonded channel configuration without rate matcher Parallel recovered clock from the receiver PMA in the associated channel (rx_clkout) Divide-by-two version of the parallel recovered clock from the receiver PMA in the associated channel (rx_clkout) x4 bonded channel configuration Parallel transmitter PCS clock from the central clock divider in the CMU0 of the associated transceiver block (coreclkout) Divide-by-two version of the parallel transmitter PCS clock from the central clock divider in CMU0 of the associated transceiver block (coreclkout) x8 bonded channel configuration Parallel transmitter PCS clock from the central clock divider in CMU0 of the master transceiver block (coreclkout from master transceiver block) Divide-by-two version of the parallel transmitter PCS clock from the central clock divider in CMU0 of the master transceiver block (coreclkout from master transceiver block) The receiver phase compensation FIFO read clock source varies depending on whether or not you instantiate the rx_coreclk port in the ALTGX MegaWizard Plug-In Manager. Table 1-24 shows the receiver phase compensation FIFO read clock source in different configurations. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-84 Chapter 1: Arria II GX Transceiver Architecture Functional Modes Table 1-24. Receiver Phase Compensation FIFO Read Clock Source Receiver Phase Compensation FIFO Read Clock Configuration rx_coreclk Port Not Instantiated rx_coreclk Port Instantiated (1) Non-bonded channel configuration with rate matcher FPGA fabric clock driven by the clock signal on the tx_clkout port FPGA fabric clock driven by the clock signal on the rx_coreclk port Non-bonded channel configuration without rate matcher FPGA fabric clock driven by the clock signal on the rx_clkout port FPGA fabric clock driven by the clock signal on the rx_coreclk port x4 bonded channel configuration FPGA fabric clock driven by the clock signal on the coreclkout port FPGA fabric clock driven by the clock signal on the rx_coreclk port x8 bonded channel configuration FPGA fabric clock driven by the clock signal on the coreclkout port FPGA fabric clock driven by the clock signal on the rx_coreclk port Note to Table 1-24: (1) The clock signal driven on the rx_coreclk port must have 0 PPM frequency difference with respect to the receiver phase compensation FIFO write clock. Receiver Phase Compensation FIFO Error Flag An optional rx_phase_comp_fifo_error port is available in all functional modes to indicate a receiver phase compensation FIFO overrun or underflow condition. The rx_phase_comp_fifo_error signal is asserted high when the phase compensation FIFO gets either full or empty. This feature is useful to verify a phase compensation FIFO overrun or underflow condition as a probable cause of link errors. Offset Cancellation in the Receiver Buffer and Receiver CDR As silicon progresses towards smaller process nodes, the performance of circuits at these smaller nodes depends more on process variations. These process variations result in analog voltages that can be offset from required ranges. Offset cancellation logic corrects these offsets. The receiver buffer and receiver CDR require offset cancellation. f For more information, refer to "Receiver Offset Cancellation" on page 1-8 and to AN 558: Implementing Dynamic Reconfiguration in Arria II GX Devices. f Due to the offset cancellation process, the transceiver reset sequence has changed. For more information, refer to the Reset Control and Power Down chapter in volume 2 of the Arria II GX Device Handbook. Functional Modes You can configure Arria II GX transceivers in one of the following functional modes using the ALTGX MegaWizard Plug-In Manager: Basic single-width at 600 Mbps to 3.75 Gbps PCI Express (PIPE) (Gen1 at 2.5 Gbps) XAUI (3.125 Gbps up to HiGig/HiGig+ at 3.75 Gbps) GIGE (1.25 Gbps) Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Functional Modes 1-85 Serial RapidIO (1.25 Gbps, 2.5 Gbps, 3.125 Gbps) SONET/SDH (OC-12, OC-48) SDI (HD at 1.485/1.4835 Gbps, 3G at 2.97/2.967 Gbps) Basic Functional Mode The Arria II GX transceiver datapath is extremely flexible in Basic functional mode. To configure the transceiver in Basic functional mode, you must select Basic in the Which protocol will you be using? option of the ALTGX MegaWizard Plug-In Manager. The Basic functional mode runs in Basic single-width mode. Table 1-25 shows the PCS-PMA interface widths and data rates supported in Basic single-width mode. Table 1-25. PCS-PMA Interface Widths and Data Rates in Basic Single-Width Mode Basic Functional Mode Supported Data Rate Range (1) Basic single-width mode 600 Mbps to 3.75 Gbps PMA-PCS Interface Width 8-bit 10-bit Note to Table 1-25: (1) The data rate range supported in Basic single-width mode varies depending on whether or not you use the byte serializer/deserializer. For more information, refer to "Basic Single-Width Mode Configurations" on page 1-86. Low Latency PCS Datapath The ALTGX MegaWizard Plug-In Manager provides an Enable low latency PCS mode option when configured in Basic single-width mode. If you select this option, the following transmitter and receiver channel PCS blocks are truly bypassed to yield a low latency PCS datapath: 8B/10B encoder and decoder Word aligner Deskew FIFO Rate match (clock rate compensation) FIFO Byte ordering In low latency PCS modes, the transmitter and receiver phase compensation FIFOs are always enabled. Depending on the targeted data rate, the byte serializer and deserializer blocks can be optionally bypassed. For more information, refer to "Basic Single-Width Mode Configurations" on page 1-86. The PCS latency in Basic single-width mode with and without the low latency PCS mode option is pending characterization. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-86 Chapter 1: Arria II GX Transceiver Architecture Functional Modes Basic Single-Width Mode Configurations Figure 1-69 shows Arria II GX transceiver configurations allowed in Basic single-width functional mode with an 8-bit wide PMA-PCS interface. Figure 1-69. Transceiver Configurations in Basic Single-Width Mode with an 8-Bit Wide PMA-PCS Interface Arria II GX Configurations Protocol Basic Functional Modes Single Width PMA-PCS Interface Width 8- bit 10-Bit PIPE XAUI GIGE SRIO SONET /SDH SDI 10-Bit 10-Bit 10-Bit 10-Bit 8-Bit 10-Bit Functional Mode Basic Single-Width 8-Bit PMA-PCS Interface Width Data Rate (Gbps) 0.6 - 3.125 Channel Bonding x1, x4, x8 Low-Latency PCS Disabled Word Aligner (Pattern Length) Enabled Manual Alignment (16-Bit) Bit-Slip (16-Bit) Disabled 8B/10B Encoder/Decoder Disabled Disabled Disabled Rate Match FIFO Disabled Disabled Disabled Byte SerDes Disabled Enabled Disabled Enabled Disabled Enabled Data Rate (Gbps) 0.6 1.6 0.6 3.0 0.6 1.6 0.6 3.0 0.6 1.6 0.6 3.0 Byte Ordering Disabled Disabled Disabled Disabled Disabled Disabled FPGA Fabric-Transceiver Interface Width 8-Bit 16-Bit 16-Bit 8-Bit 16-Bit 8-Bit 16-Bit FPGA FPGA Fabric Fabric-Transceiver Transceiver Interface Frequency Interface Frequency (MHz) 75 200 37.5 187.5 37.5 187.5 75 200 37.5 187.5 75 200 37.5 187.5 Arria II GX Device Handbook Volume 2 Enabled (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Functional Modes 1-87 Figure 1-70 shows Arria II GX transceiver configurations allowed in Basic single-width functional mode with a 10-bit wide PMA-PCS interface. Figure 1-70. Transceiver Configurations in Basic Single-Width Mode with a 10-Bit Wide PMA-PCS Interface Arria II GX Configurations Protocol Basic Functional Modes Single Width PMA-PCS Interface Width 8-Bit 10-Bit PIPE XAUI GIGE SRIO SONET /SDH SDI 10-Bit 10-Bit 10-Bit 10-Bit 8-Bit 10-Bit Functional Mode Basic Single-Width 10-Bit PMA-PCS Interface Width Data Rate (Gbps) 0.6 - 3.75 Channel Bonding x1, x4, x8 Low-Latency PCS 0.6 - 2 (CPRI/OBSAI) x1 Disabled Word Aligner (Pattern Length) Automatic Synchronization State Machine (7-Bit, 10-Bit) Bit-Slip (7-Bit, 10-Bit) Manual Alignment (7-Bit, 10-Bit) 8B/10B Encoder/Decoder Disabled Enabled Disabled Enabled Disabled Rate Match FIFO Disabled Disabled Disabled Disabled Disabled Enabled Disabled Enabled Disabled 0.6 3.75 0.6 2.0 Enabled Disabled Enabled Disabled 0.6 3.75 0.6 2.0 Enabled Disabled Data Rate (Gbps) 0.6 2.0 Byte Ordering Disabled FPGA Fabric-Transceiver Interface Width 10-Bit 20-Bit 8-Bit 16-Bit 10-Bit 20-Bit 8-Bit 16-Bit 10-Bit 20-Bit 8-Bit 60 200 30 187.5 60 200 30 187.5 60 200 30 187.5 60 200 30 187.5 60 200 30 187.5 60 200 FPGA FPGA FabricFabric-Transceiver Transceiver Interface Frequency Frequency Interface (MHz) Disabled Disabled Disabled Disabled 0.6 3.75 0.6 2.0 Disabled Disabled Disabled Disabled 0.6 3.75 Enabled Disabled Disabled 0.6 2.0 Disabled Enabled Byte SerDes 0.6 3.75 Disabled Enabled Manual alignment (10-Bit) Disabled Enabled Disabled Disabled Disabled Disabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled 0.6 3.75 0.6 2.0 0.6 3.75 0.6 2.0 0.6 3.75 0.6 2.0 0.6 2.0 Disabled Disabled 0.6 2.0 Disabled Disabled Disabled 16-Bit 30 187.5 Enabled Disabled Disabled Disabled Disabled 16-Bit 8-Bit 16-Bit 10-Bit 20-Bit 8-Bit 10-Bit 30 187.5 60 200 30 187.5 60 200 30 187.5 60 200 60 200 The receiver phase compensation FIFO can be configured in registered mode in single-width Basic mode to reduce latency uncertainty through the PCS for CPRI and OBSAI modes, as shown in the two right-most branches of Figure 1-70. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-88 Chapter 1: Arria II GX Transceiver Architecture Functional Modes Basic Double-Width Mode Configurations Figure 1-71 shows Arria II GX transceiver configurations allowed in Basic double-width functional mode with a 20-bit wide PMA-PCS interface. Figure 1-71. Transceiver Configurations in Basic Double-Width Mode with a 20-Bit Wide PMA-PCS Interface Arria II GX Configurations Protocol Basic Functional Modes Single Width PMA-PCS Interface Width Double Width PIPE XAUI GIGE SRIO SONET /SDH SDI 20-Bit 10-Bit 10-Bit 10-Bit 10-Bit 8-Bit 10-Bit Basic Double-Width 20-Bit PMA-PCS Interface Width PMA-PCS Interface Width Data Rate (Gbps) 1.0 - 3.072 (CPRI/OBSAI) x1 Channel Bonding Disabled Low-Latency PCS Word Aligner (Pattern Length) 8B/10B Encoder/Decoder Rate Match FIFO Manual alignment (10-Bit, 20-Bit) Enabled Disabled Disabled Disabled Disabled Disabled 1.0 3.072 1.0 3.072 Disabled Disabled 16-Bit 20-Bit 50 - 153.6 50 - 153.6 Byte SerDes Data Rate (Gbps) Byte Ordering FPGA Fabric-Transceiver Interface Width FPGA FPGA Fabric Fabric-Transceiver Transceiver Interface Frequency Interface Frequency (MHz) The receiver phase compensation FIFO is configured in registered mode in double-width Basic mode to reduce latency uncertainty through the PCS for CPRI and OBSAI modes. Basic double-width mode is supported only for CPRI/OBSAI reduced latency configurations for Arria II GX devices. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Functional Modes 1-89 PCI Express (PIPE) Mode Intel Corporation has developed a PHY interface for the PCI Express Architecture (PIPE) specification to enable implementation of a PCI Express-compliant physical layer device. The PIPE specification also defines a standard interface between the physical layer device and the media access control layer (MAC). Version 2.00 of the PIPE specification provides implementation details for a PCI Express-compliant physical layer device at Gen1 (2.5 GT/s) signaling rate. To implement a Version 2.00 PIPE-compliant PHY, you must configure the Arria II GX transceivers in PCI Express (PIPE) functional mode. Arria II GX devices have built-in PCI Express hard IP blocks that you can use to implement the PHY-MAC layer, Data Link layer, and Transaction layer of the PCI Express protocol stack. You can also bypass the PCI Express hard IP blocks and implement the PHY-MAC layer, Data Link layer, and Transaction layer in the FGPA fabric using a Soft IP. If you enable the PCI Express hard IP blocks, the Arria II GX transceivers interface with these hard IP blocks. Otherwise, the Arria II GX transceivers interface with the FPGA fabric. You can configure Arria II GX transceivers in PCI Express (PIPE) functional mode using one of the following two methods: 1 ALTGX MegaWizard Plug-In Manager if you do not use the PCI Express hard IP block PCI Express Compiler if you use the PCI Express hard IP block Descriptions of PCI Express hard IP architecture and PCI Express (PIPE) mode configurations allowed when using PCI Express hard IP block are out of the scope of this chapter. For more information about the PCI Express hard IP block, refer to the PCI Express Compiler User Guide. PCI Express (PIPE) Mode Configurations Arria II GX transceivers support Gen1 (2.5 Gbps) data rates in PCI Express (PIPE) functional mode. Arria II GX transceivers support x1, x4, and x8 lane configurations in PIPE functional mode at 2.5 Gbps data rates. In PCI Express (PIPE) x1 configuration, the PCS and PMA blocks of each channel are clocked and reset independently. PCI Express (PIPE) x4 and x8 configurations support channel bonding for four-lane and eight-lane PCI Express (PIPE) links. In these bonded channel configurations, the PCS and PMA blocks of all bonded channels share common clock and reset signals. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-90 Chapter 1: Arria II GX Transceiver Architecture Functional Modes Figure 1-72 shows the Arria II GX transceiver configurations allowed in PCI Express (PIPE) functional mode. Figure 1-72. Arria II GX Transceivers in PCI Express (PIPE) Functional Mode Arria II GX Configurations Protocol Basic Functional Modes PMA-PCS Interface Width Single Width 8-bit 10-bit PIPE XAUI GIGE SRIO SONET /SDH SDI 10-bit 10-bit 10-bit 10-bit 8-bit 10-bit PIPE Functional Mode 2.5 Gbps (Gen1) Data Rate x1, x4, x8 Channel Bonding 10-Bit PMA-PCS Interface Width Automatic Synchronization State Machine (/K28.5+/,/K28.5-/) Word Aligner (Pattern) Enabled 8B/10B Encoder/ Decoder Enabled Rate Match FIFO Enabled PCI Express hardIP Disabled Byte SerDes Disabled Enabled 8-Bit 16-Bit 16-Bit 250 MHz 125 MHz 125 MHz Enabled PCS-hardIP or PCS-FPGA Fabric Interface Width PCS-hardIP or PCS-FPGA Fabric Interface Frequency Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Functional Modes 1-91 PCI Express (PIPE) Mode Datapath Figure 1-73 shows the Arria II GX transceiver datapath when configured in PCI Express (PIPE) functional mode. Figure 1-73. Arria II GX Transceiver Datapath in PCI Express (PIPE) Mode Transmitter Channel PCS FPGA Fabric PCI Express hardIP TX Phase Compensation FIFO PIPE Interface wrclk Byte Serializer rdclk Serializer rdclk wrclk tx_coreclk[0] 8B/10B Encoder Transmitter Channel PMA /2 Low-Speed Parallel Clock High-Speed Serial Clock tx_clkout[0] FPGA Fabric-Transceiver Interface Clock Receiver Channel PCS PCI Express hardIP PIPE Interface RX Phase Compensation FIFO Byte Deserializer 8B/10B Decoder rx_coreclk[0] Rate Match FIFO Word Aligner Receiver Channel PMA DeSerializer CDR Parallel Recovered Clock /2 Low-Speed Parallel Clock Table 1-26 shows the transceiver datapath clock frequencies in PCI Express (PIPE) functional mode configured using the ALTGX MegaWizard Plug-In Manager. Table 1-26. Arria II GX Transceiver Datapath Clock Frequencies in PCI Express (PIPE) Mode Functional Mode Data Rate High-Speed Serial Clock Frequency Parallel Recovered Clock and Low-Speed Parallel Clock Frequency PCI Express (PIPE) x1, x4, x8 2.5 Gbps 1.25 GHz 250 MHz FPGA Fabric-Transceiver Interface Clock Frequency With Byte Serializer/ Deserializer (16-Bit Wide) 125 MHz (Gen1) The transceiver datapath clocking varies between non-bonded (x1) and bonded (x4 and x8) configurations in PCI Express (PIPE) mode. f For more information about transceiver datapath clocking in different PCI Express (PIPE) configurations, refer to the Arria II GX Transceiver Clocking chapter in volume 2 of the Arria II GX Device Handbook. The transmitter datapath in PCI Express (PIPE) mode consists of: (c) March 2009 PIPE interface Transmitter phase compensation FIFO Optional byte serializer (enabled for 16-bit and disabled for 8-bit FPGA fabric-transceiver interface) 8B/10B encoder Altera Corporation Arria II GX Device Handbook Volume 2 1-92 Chapter 1: Arria II GX Transceiver Architecture Functional Modes 10:1 serializer Transmitter buffer with receiver detect circuitry The receiver datapath in PCI Express (PIPE) mode consists of: Receiver buffer with signal detect circuitry 1:10 deserializer Word aligner that implements PCI Express-compliant synchronization state machine Optional rate match FIFO (clock rate compensation) that can tolerate up to 600 PPM frequency difference 8B/10B decoder Optional byte deserializer (enabled for 16-bit and disabled for 8-bit FPGA fabric-transceiver interface) Receiver phase compensation FIFO PIPE interface Table 1-27 shows features supported in PCI Express (PIPE) functional mode for 2.5 Gbps data rate configurations. Table 1-27. Supported Features in PCI Express (PIPE) Mode 2.5 Gbps (Gen1) Feature x1, x4, x8 link configurations v PCI Express-compliant synchronization state machine v 300 PPM (total 600 PPM) clock rate compensation v 8-bit FPGA fabric-Transceiver interface v 16-bit FPGA fabric-Transceiver interface v Transmitter buffer electrical idle v Receiver Detection v 8B/10B encoder disparity control when transmitting compliance pattern v Power state management v Receiver status encoding v PCI Express (PIPE) Interface In PCI Express (PIPE) mode, each channel has a PIPE interface block that transfers data, control, and status signals between the PHY-MAC layer and the transceiver channel PCS and PMA blocks. The PIPE interface block is compliant to version 2.00 of the PCI Express (PIPE) specification. If you use the PCI Express hard IP block, the PHY-MAC layer is implemented in the hard IP block. Otherwise, the PHY-MAC layer may be implemented using Soft IP in the FPGA fabric. 1 The PIPE interface block is only used in PCI Express (PIPE) mode and cannot be bypassed. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Functional Modes 1-93 Besides transferring data, control, and status signals between the PHY-MAC layer and the transceiver, the PIPE interface block implements the following functions required in a PIPE-compliant physical layer device: Force the transmitter buffer in electrical idle state Initiate receiver detect sequence 8B/10B encoder disparity control when transmitting compliance pattern Manage PIPE power states Indicate completion of various PHY functions like receiver detection and power state transitions on the pipephydonestatus signal Encode receiver status and error conditions on the pipestatus[2:0] signal as specified in the PIPE specification Transmitter Buffer Electrical Idle When the input signal tx_forceelecidle is asserted high, the PIPE interface block puts the transmitter buffer in that channel in electrical idle state. During electrical idle, the transmitter buffer differential and common mode output voltage levels are compliant to the PCI Express Base Specification 1.1 for PCI Express Gen1 data rate. Figure 1-74 shows the relationship between assertion of the tx_forceelecidle signal and the transmitter buffer output on the tx_dataout port. Time T1 taken from the assertion of the tx_forceelecidle signal to the transmitter buffer reaching electrical idle voltage levels is pending characterization. Once in electrical idle state, the PCI Express (PIPE) protocol requires the transmitter buffer to stay in electrical idle for a minimum of 20 ns for Gen1 data rate. 1 The minimum period of time for which the tx_forceelecidle signal must be asserted high such that the transmitter buffer stays in electrical idle state for at least 20 ns is pending characterization. Figure 1-74. Transmitter Buffer Electrical Idle State tx_forcelecidle tx_dataout T1 >20 ns The PCI Express (PIPE) specification requires the transmitter buffer to be in electrical idle in certain power states. Refer to Table 1-26 on page 1-91 for more information on the tx_forceelecidle signal levels required in different PCI Express (PIPE) power states. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-94 Chapter 1: Arria II GX Transceiver Architecture Functional Modes Receiver Detection During the detect substate of the long-term sample storage module (LTSSM) state machine, the PCI Express (PIPE) protocol requires the transmitter channel to perform a receiver detect sequence to detect if a receiver is present at the far end of each lane. The PCI Express (PIPE) specification requires that a receiver detect operation be performed during the P1 power state. The PIPE interface block in Arria II GX transceivers provides an input signal tx_detectrxloopback for the receiver detect operation. When the input signal tx_detectrxloopback is asserted high in the P1 power state, the PIPE interface block sends a command signal to the transmitter buffer in that channel to initiate a receiver detect sequence. In the P1 power state, the transmitter buffer must always be in electrical idle state. On receiving this command signal, the receiver detect circuitry creates a step voltage at the output of the transmitter buffer. If an active receiver (that complies to the PCI Express [PIPE] input impedance requirements) is present at the far end, the time constant of the step voltage on the trace is higher compared to when the receiver is not present. The receiver detect circuitry monitors the time constant of the step signal seen on the trace to decide if a receiver was detected or not. The receiver detect circuitry monitor needs a 125-MHz clock for operation that you must drive on the fixedclk port. 1 For the receiver detect circuitry to function reliably, the AC-coupling capacitor on the serial link and the receiver termination values used in your system must be compliant to the PCI Express (PIPE) Base Specification 1.1. Receiver detect circuitry communicates the status of the receiver detect operation to the PIPE interface block. If a far-end receiver is successfully detected, the PIPE interface block asserts pipephydonestatus for one clock cycle and synchronously drives the pipestatus[2:0] signal to 3'b011. If a far-end receiver is not detected, the PIPE interface block asserts pipephydonestatus for one clock cycle and synchronously drives the pipestatus[2:0] signal to 3'b000. Figure 1-75 and Figure 1-76 show the receiver detect operation where a receiver was successfully detected and where a receiver was not detected, respectively. Figure 1-75. Receiver Detect, Successfully Detected powerdown[1:0] 2'b10(P1) tx_detectrxloopback pipephydonestatus pipestatus[2:0] Arria II GX Device Handbook Volume 2 3'b000 3'b011 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Functional Modes 1-95 Figure 1-76. Receiver Detect, Unsuccessful 2'b10 (P1) powerdown[1:0] tx_detectrxloopback pipephydonestatus 3'b000 pipestatus[2:0] Compliance Pattern Transmission Support The LTSSM state machine can enter the "polling.compliance" substate where the transmitter is required to transmit a compliance pattern as specified in the PCI Express (PIPE) Base Specification 1.1. The "polling.compliance" substate is intended to assess if the transmitter is electrically compliant with the PCI Express (PIPE) voltage and timing specifications. The compliance pattern is a repeating sequence of the following four code groups: /K28.5/ /D21.5/ /K28.5/ /D10.2/ PCI Express (PIPE) protocol requires the first /K28.5/ code group of the compliance pattern to be encoded with negative current disparity. To satisfy this requirement, the PIPE interface block provides an input signal, tx_forcedispcompliance. A high level on tx_forcedispcompliance forces the associated parallel transmitter data on the tx_datain port to transmit with negative current running disparity. For 8-bit transceiver channel width configurations, you must drive tx_forcedispcompliance high in the same parallel clock cycle as the first /K28.5/ of the compliance pattern on the tx_datain port. For 16-bit transceiver channel width configurations, you must drive only the LSB of tx_forcedispcompliance[1:0] high in the same parallel clock cycle as /K28.5/D21.5/ of the compliance pattern on the tx_datain port. Figure 1-77 and Figure 1-78 show the required level on the tx_forcedispcompliance signal while transmitting the compliance pattern in 8-bit and 16-bit channel width configurations, respectively. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-96 Chapter 1: Arria II GX Transceiver Architecture Functional Modes Figure 1-77. Compliance Pattern Transmission Support, 8-Bit Wide Channel Configurations tx_datain[7:0] K28.5 D21.5 K28.5 D10.2 K28.5 D21.5 K28.5 D10.2 BC B5 BC 4A BC B5 BC 4A tx_ctrldetect tx_forcedispcompliance Figure 1-78. Compliance Pattern Transmission Support, 16-Bit Wide Channel Configurations tx_datain[15:0] /K28.5/D21.5/ /K28.5/D10.2/ /K28.5/D21.5/ /K28.5/D10.2/ B5BC BC4A B5BC BC4A 01 tx_ctrldetect[1:0] tx_forcedispcompliance[1:0] 01 00 Power State Management The PCI Express (PIPE) specification defines four power states, namely P0, P0s, P1, and P2, that the physical layer device must support to minimize power consumption. P0 is the normal operation state during which packet data is transferred on the PCI Express (PIPE) link. P0s, P1, and P2 are low-power states into which the physical layer must transition as directed by the PHY-MAC layer to minimize power consumption. The PCI Express (PIPE) specification provides the mapping of these power states to the LTSSM states specified in the PCI Express (PIPE) Base Specification 1.1. The PHY-MAC layer is responsible for implementing the mapping logic between the LTSSM states and the four power states in the PCI Express (PIPE)-compliant PHY. The PIPE interface in Arria II GX transceivers provides an input port, powerdn[1:0], for each transceiver channel configured in PCI Express (PIPE) mode. Table 1-30 shows mapping between the logic levels driven on the powerdn[1:0] port and the resulting power state that the PIPE interface block puts the transceiver channel into. Table 1-28. powerdn[1:0] Port Power State Functions and Descriptions (Part 1 of 2) Power State powerdn Function Description P0 2'b00 Transmits normal data, transmits Electrical Idle, or enters into loopback mode Normal operation mode P0s 2'b01 Only transmits Electrical Idle Low recovery time saving state Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Functional Modes 1-97 Table 1-28. powerdn[1:0] Port Power State Functions and Descriptions (Part 2 of 2) Power State powerdn Function Description P1 2'b10 Transmitter buffer is powered down and can do a receiver detect while in this state High recovery time power saving state P2 2'b11 Transmits Electrical Idle or a beacon to wake up the downstream receiver Lowest power saving state 1 When transitioning from the P0 power state to lower power states (P0s, P1, and P2), the PCI Express (PIPE) specification requires the physical layer device to implement power saving measures. Arria II GX transceivers do not implement these power saving measures except when putting the transmitter buffer in Electrical Idle in the lower power states. The PIPE interface block indicates successful power state transition by asserting the pipephydonestatus signal for one parallel clock cycle as specified in the PCI Express (PIPE) specification. The PHY-MAC layer must not request any further power state transition until the pipephydonestatus signal has indicated the completion of the current power state transition request. Figure 1-79 shows an example waveform for a transition from P0 to P2 power state. Figure 1-79. Example of Power State Transition from P0 to P2 Parallel Clock powerdn[1:0] 2'b00 (P0) 2'b11 (P2) pipephydonestatus The PCI Express (PIPE) specification allows the PIPE interface to perform protocol functions like receiver detect, loopback, and beacon transmission in specified power states only. This requires the PHY-MAC layer to drive the tx_detectrxloopback and tx_forceelecidle signals appropriately in each power state to perform these functions. Table 1-29 summarizes the logic levels that the PHY-MAC layer must drive on the tx_detectrxloopback and tx_forceelecidle signals in each power state. Table 1-29. Logic Levels for the PHY-MAC Layer (Part 1 of 2) Power State tx_detectrxloopback tx_forceelecidle P0 0: normal mode 0: Must be deasserted 1: data path in loopback mode 1: Illegal mode P0s Don't care 0: Illegal mode 1: Must be asserted in this state (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-98 Chapter 1: Arria II GX Transceiver Architecture Functional Modes Table 1-29. Logic Levels for the PHY-MAC Layer (Part 2 of 2) Power State P1 P2 tx_detectrxloopback tx_forceelecidle 0: Electrical Idle 0: Illegal mode 1: receiver detect 1: Must be asserted in this state Don't care Deasserted in this state for sending beacon. Otherwise asserted. Receiver Status The PCI Express (PIPE) specification requires the PHY to encode the receiver status on a 3-bit RxStatus[2:0] signal. This status signal is used by the PHY-MAC layer for its operation. The PIPE interface block receives status signals from the transceiver channel PCS and PMA blocks and encodes the status on the 3-bit output signal pipestatus[2:0] to the FPGA fabric. The encoding of the status signals on pipestatus[2:0] is compliant with the PCI Express (PIPE) specification and listed in Table 1-30. Table 1-30. Encoding of the Status Signals on pipestatus[2:0] pipestatus[2:0] Description Error Condition Priority 3'b000 Received data OK N/A 3'b001 One SKP symbol added 5 3'b010 One SKP symbol deleted 6 3'b011 Receiver detected N/A 3'b100 8B/10B decode error 1 3'b101 Elastic buffer (rate match FIFO) overflow 2 3'b110 Elastic buffer (rate match FIFO) underflow 3 3'b111 Received disparity error 4 Two or more of the error conditions, for example, 8B/10B decode error (code group violation), rate match FIFO overflow or underflow, or receiver disparity error, can occur simultaneously. The PIPE interface follows the priority listed in Table 1-30 while encoding the receiver status on the pipestatus[2:0] port. For example, if the PIPE interface receives an 8B/10B decode error and disparity error for the same symbol, it drives 3'b100 on the pipestatus[2:0] signal. Fast Recovery Mode The PCI Express Base specification fast training sequences (FTS) are used for bit and byte synchronization to transition from L0s to L0 (PIPE P0s to P0) power states. The PCI Express Base Specification requires the physical layer device to acquire bit and byte synchronization after transitioning from L0s to L0 state within 16 ns to 4 s. If the Arria II GX receiver CDR is configured in Automatic Lock mode, the receiver cannot meet the PCI Express specification of acquiring bit and byte synchronization within 4 s due to the signal detect and PPM detector time. To meet this specification, each Arria II GX transceiver has a built-in Fast Recovery circuitry that you can optionally enable. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Functional Modes 1 1-99 To enable the Fast Recovery circuitry, select the Enable fast recovery mode option in the ALTGX MegaWizard Plug-In Manager. If enabled, the Fast Recovery circuitry controls the receiver CDR rx_locktorefclk and rx_locktodata signals to force the receiver CDR in LTR or LTD modes. It relies on the Electrical Idle Ordered Sets (EIOS), NFTS sequences received in L0 power state, and the signal detect signal from the receiver input buffer to control the receiver CDR lock mode. 1 The Fast Recovery circuitry is self-operational and does not require control inputs from you. When enabled, the rx_locktorefclk and rx_locktodata ports are not available in the ALTGX MegaWizard Plug-In Manager. Electrical Idle Inference The PCI Express (PIPE) protocol allows inferring the electrical idle condition at the receiver instead of detecting the electrical idle condition using analog circuitry. Clause 4.2.4.3 in PCI Express (PIPE) Base Specification 1.1 specifies conditions to infer electrical idle at the receiver in various sub-states of the LTSSM state machine. In all PCI Express (PIPE) modes (x1, x4, and x8), each receiver channel PCS has an optional Electrical Idle Inference module designed to implement the electrical idle inference conditions specified in the PCI Express (PIPE) Base Specification 1.1. You can enable the Electrical Idle Inference module by selecting the Enable electrical idle inference functionality option in the ALTGX MegaWizard Plug-In manager. If enabled, this module infers electrical idle depending on the logic level driven on the rx_elecidleinfersel[2:0] input signal. The Electrical Idle Inference module in each receiver channel indicates whether the electrical idle condition is inferred or not on the pipeelecidle signal of that channel. The Electrical Idle Interface module drives the pipeelecidle signal high if it infers an electrical idle condition; otherwise, it drives it low. Table 1-31 shows electrical idle inference conditions specified in the PCI Express (PIPE) Base Specification 1.1 and implemented in the Electrical Idle Inference module to infer electrical idle in various substates of the LTSSM state machine. For the Electrical Idle Inference Module to correctly infer an electrical idle condition in each LTSSM substate, you must drive the rx_elecidleinfersel[2:0] signal appropriately, as shown in Table 1-31. Table 1-31. Electrical Idle Inference Conditions (Part 1 of 2) (c) March 2009 LTSSM State Gen1 (2.5 Gbps) rx_elecidleinfersel[2:0] L0 Absence of update FC or alternatively skip ordered set in 128 s window 3'b100 Recovery.RcvrCfg Absence of TS1 or TS2 ordered set in 1280 UI interval 3'b101 Recovery.Speed when successful speed negotiation = 1'b1 Absence of TS1 or TS2 ordered set in 1280 UI interval 3'b101 Altera Corporation Arria II GX Device Handbook Volume 2 1-100 Chapter 1: Arria II GX Transceiver Architecture Functional Modes Table 1-31. Electrical Idle Inference Conditions (Part 2 of 2) LTSSM State Gen1 (2.5 Gbps) rx_elecidleinfersel[2:0] Recovery.Speed when successful speed negotiation = 1'b0 Absence of an exit from Electrical Idle in 2000 UI interval 3'b110 Loopback.Active Absence of an exit from Electrical Idle in 128 s window 3'b111 (as slave) In the "Recovery.Speed" substate of the LTSSM state machine with unsuccessful speed negotiation (rx_elecidleinfersel[2:0] = 3'b110), the PCI Express (PIPE) Base Specification requires the receiver to infer an electrical idle condition (pipeelecidle = high) if absence of an exit from Electrical Idle is detected in a 2000 UI interval for Gen1 data rate. The electrical idle inference module detects an absence of exit from Electrical Idle if four /K28.5/ COM code groups are not received in the specified interval. In other words, when configured for Gen1 data rate and rx_elecidleinfersel[2:0] = 3'b110, the Electrical Idle inference module asserts pipeelecidle high if it does not receive four /K28.5/ COM code groups in a 2000 UI interval. When configured for Gen1 data rate and rx_elecidleinfersel[2:0] = 3'b111 in Loopback.Active substate of the LTSSM state machine, the Electrical Idle inference module asserts pipeelecidle high if it does not receive four /K28.5/ COM code groups in a 128 s interval. 1 The Electrical Idle inference module does not have the capability to detect electrical idle exit condition based on reception of the electrical idle exit ordered set (EIEOS), as specified in the PCI Express (PIPE) Base Specification. If you select the Enable Electrical Idle Inference Functionality option in the ALTGX MegaWizard Plug-In Manager and drive rx_elecidleinfersel[2:0] = 3'b0xx, the Electrical Idle Inference Block uses EIOS detection from the Fast Recovery circuitry to drive the pipeelecidle signal If you do not select the Enable electrical idle inference functionality option in the ALTGX MegaWizard Plug-In manager, the Electrical Idle inference module is disabled. In this case, the rx_signaldetect signal from the signal detect circuitry in the receiver buffer is inverted and driven as the pipeelecidle signal. PCI Express Cold Reset Requirements The PCI Express Base Specification 1.1 defines the following three types of conventional resets to the PCI Express system components: Cold Reset--fundamental reset after power up Warm Reset--fundamental reset without removal and re-application of power Hot Reset--In-band conventional reset initiated by higher layer by setting the Hot Reset bit in the TS1 or TS2 training sequences Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Functional Modes 1-101 Fundamental reset is provided by the system to the component or adapter card using the auxiliary signal PERST#. The PCI Express Base Specification 1.1 requires that PERST# must be kept asserted for a minimum of 100 ms (TPVPERL) after the system power becomes stable in a cold reset situation. Additionally, all system components must enter the LTSSM Detect state within 20 ms and the link must become active within 100 ms after de-assertion of the PERST# signal. This implies that each PCI Express system component must become active within 200 ms after the power becomes stable. 1 The link being active is interpreted as the physical layer device coming out of Electrical Idle in L0 state of the LTSSM state machine. Figure 1-80 shows the PCI Express cold reset timing requirements. Figure 1-80. PCI Express Cold Reset Requirements 1 2 3 4 Power Rail Marker 1: Power becomes stable PERST# Marker 2: PERST# gets de-asserted TPVPERL 100 ms T2-3 d"20 ms T2-4 d"100 ms Marker 3: Maximum time for Marker 2 for the LTSSM to enter the Detect state Marker 4: Maximum time for Marker 2 for the link to become active Time taken by a PCI Express port implemented using the Arria II GX device to go from power up to link active state is stated below: Power On Reset--begins after power rails become stable. Typically takes 12 ms FPGA Configuration/Programming--begins after power on reset. Configuration time depends on the FPGA density Time taken from de-assertion of PERST# to link active--typically takes 40 ms (pending characterization and verification of the PCI Express soft IP and hard IP) To meet the PCI Express specification of 200 ms from power on to link active, the Arria II GX device configuration time must be less than 148 ms (200 ms - 12 ms for power on reset - 40 ms for link to become active after PERST# de-assertion). (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-102 Chapter 1: Arria II GX Transceiver Architecture Functional Modes Table 1-32 shows typical configuration times for Arria II GX devices when updated using the Fast Passive Parallel (FPP) configuration scheme at 125 MHz. Table 1-32. Typical Configuration Times for Arria II GX Devices Configured with Fast Passive Parallel Device Time (ms) (1) EP2AGX20 24 EP2AGX30 24 EP2AGX45 24 EP2AGX65 35 EP2AGX95 35 EP2AGX125 48 EP2AGX190 48 EP2AGX260 79 Note to Table 1-32: (1) Pending characterization. f For more information about FPP configuration scheme, refer to the Configuration, Design Security, Remote System Upgrades with Arria II GX Devices chapter in volume 1 in the Arria II GX Device Handbook. 1 Most flash memories available in the market can run up to 100 MHz. To configure the Arria II GX devices at 125 MHz, Altera recommends using a MAX II device to convert the 16-bit flash memory output at 62.5 MHz to 8-bit configuration data input to the Arria II GX devices at 125 MHz. XAUI Mode The XAUI is an optional, self-managed interface that you can insert between the reconciliation sublayer and the PHY layer to transparently extend the physical reach of the XGMII. XAUI addresses several physical limitations of the XGMII. XGMII signaling is based on the HSTL Class 1 single-ended I/O standard, which has an electrical distance limitation of approximately 7 cm. Because XAUI uses a low-voltage differential signaling method, the electrical distance limitation is increased to approximately 50 cm. Another advantage of XAUI is simplification of backplane and board trace routing. XGMII is composed of 32 transmit channels, 32 receive channels, 1 transmit clock, 1 receive clock, 4 transmitter control characters, and 4 receive control characters for a 74-pin wide interface in total. XAUI, on the other hand, only consists of 4 differential transmitter channels and 4 differential receiver channels for a 16-pin wide interface in total. This reduction in pin count significantly simplifies the routing process in the layout design. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Functional Modes 1-103 Figure 1-81 shows the relationships between the XGMII and XAUI layers. Figure 1-81. XAUI and XGMII Layers LAN Carrier Sense Multiple Access/Collision Detect (CSMA/CD) Layers Higher Layers Logical Link Control (LLC) OSI Reference Model Layers MAC Control (Optional) Media Access Control (MAC) Application Reconciliation Presentation 10 Gigabit Media Independent Interface Session Optional XGMII Extender Transport XGMII Extender Sublayer 10 Gigabit Attachment Unit Interface XGMII Extender Sublayer 10 Gigabit Media Independent Interface Network PCS Data Link PMA Physical Layer Device PMD Physical Medium Dependent Interface Medium 10 Gb/s The XGMII interface consists of four lanes of 8 bits. At the transmit side of the XAUI interface, the data and control characters are converted within the XGMII extender sublayer (XGXS) into an 8B/10B encoded data stream. Each data stream is then transmitted across a single differential pair running at 3.125 Gbps (3.75 Gbps for HiGig/HiGig+). At the XAUI receiver, the incoming data is decoded and mapped back to the 32-bit XGMII format. This provides a transparent extension of the physical reach of the XGMII and also reduces the interface pin count. XAUI functions as a self-managed interface because code group synchronization, channel deskew, and clock domain decoupling is handled with no upper layer support requirements. This functionality is based on the PCS code groups that are used during the IPG time and idle periods. PCS code groups are mapped by the XGXS to XGMII characters specified in Table 1-33. Table 1-33. XGMII Character to PCS Code-Group Mapping (Part 1 of 2) (c) March 2009 Altera Corporation XGMII TXC XGMII TXD (1) PCD Code Group Description 0 00 through FF Dxx,y Normal data transmission 1 07 K28.0 or K28.3 or K28.5 Idle in ||I|| 1 07 K28.5 Idle in ||T|| 1 9C K28.4 Sequence Arria II GX Device Handbook Volume 2 1-104 Chapter 1: Arria II GX Transceiver Architecture Functional Modes Table 1-33. XGMII Character to PCS Code-Group Mapping (Part 2 of 2) XGMII TXC XGMII TXD (1) PCD Code Group Description 1 FB K27.7 Start 1 FD K29.7 Terminate 1 FE K30.7 Error 1 Any other value K30.7 Invalid XGMII character Note to Table 1-33: (1) The values in the XGMII TXD column are in hexadecimal. Figure 1-82 shows an example of mapping between XGMII characters and the PCS code groups that are used in XAUI. The idle characters are mapped to a pseudo-random sequence of /A/, /R/, and /K/ code groups. Figure 1-82. Example of Mapping XGMII Characters to PCS Code Groups XGMII T/RxD<7..0> | | S Dp T/RxD<15..8> | | Dp Dp D --- D D --- D D D T/RxD<23..16> | | Dp Dp D D D --- D T/RxD<31..24> | | Dp Dp D D D --- D D D D D D | | | | | | D T | | | | | | D D | | | | | | | D D D | | | | | | | --- D D D D A R R K K R D --- D D D T A R R K K R D D D K A R R K K R D D D K A R R K K R D D D PCS Lane 0 K R S Dp Dp Lane 1 K R Dp Lane 2 K R Dp Dp D D D --- Lane 3 K R Dp Dp D D D --- D D The PCS code groups are sent using PCS ordered sets. PCS ordered sets consist of combinations of special and data code groups defined as a column of code groups. These ordered sets are composed of four code groups beginning in lane 0. Table 1-34 lists the defined idle ordered sets (||I||) that are used for the self-managed properties of XAUI. Table 1-34. Defined Idle Ordered Set Code Arria II GX Device Handbook Volume 2 Encoding Ordered Set Number of Code Groups Substitute for XGMII Idle ||I|| Idle ||K|| Synchronization column 4 /K28.5/K28.5/K28.5/K28.5/ ||R|| Skip column 4 /K28.0/K28.0/K28.0/K28.0/ ||A|| Align column 4 /K28.3/K28.3/K28.3/K28.3/ (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Functional Modes 1-105 Arria II GX transceivers configured in XAUI mode provide the following protocol features: (c) March 2009 XGMII-to-PCS code conversion at the transmitter PCS-to-XGMII code conversion at the receiver 8B/10B encoding and decoding IEEE P802.3ae-compliant synchronization state machine 100 PPM clock rate compensation Channel deskew of four lanes of the XAUI link Altera Corporation Arria II GX Device Handbook Volume 2 1-106 Chapter 1: Arria II GX Transceiver Architecture Functional Modes Figure 1-83 shows the XAUI mode configuration supported in Arria II GX devices. Figure 1-83. Arria II GX XAUI Mode Configuration Arria II GX Configurations Protocol Basic Single Width Functional Modes PMA-PCS Interface Width 8-bit 10-bit PIPE XAUI GIGE SRIO SONET /SDH SDI 10-bit 10-bit 10-bit 10-bit 8-bit 10-bit Functional Mode XAUI Data Rate (Gbps) 3.125 - 3.75 Channel Bonding x4 Low-Latency PCS Disabled Word Aligner (Pattern Length) Automatic Synchronization State Machine (10-Bit/K28.5/) Deskew FIFO Enabled 8B/10B Encoder/Decoder Enabled Rate Match FIFO Enabled Byte SerDes Enabled Byte Ordering Disabled FPGA Fabric-Transceiver Interface Width 16-Bit FPGA Fabric-Transceiver Interface Frequency (MHz) 156.25187.5 Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Functional Modes 1-107 XAUI Mode Datapath Figure 1-84 shows the ALTGX megafunction transceiver datapath when configured in XAUI mode. Figure 1-84. Transceiver Datapath in XAUI Mode Channel 3 Channel 2 Transmitter Channel PCS TX Phase Compensation FIFO wrclk Byte Serializer rdclk 8B/10B Encoder Transmitter Channel PMA Serializer rdclk wrclk tx_coreclk[3:2] /2 Low-Speed Parallel Clock from CMU 0 Click Divider Channel 3 Channel 2 Receiver Channel PCS Byte Deserializer RX Phase Compensation FIFO 8B/10B Decoder Rate Match FIFO Deskew FIFO Word Aligner Receiver Channel PMA Deserializer CDR rx_coreclk[3:2] Ch0 Parallel Recovered Clock Ch2 Parallel Recovered Clock /2 Low-Speed Parallel Clock from CMU 0 Clock Divider coreclkout FPGA Fabric-Transceiver Interface Clock CMU1_Channel /2 Input Reference Clock CMU1_PLL CMU1 Clock Divider Input Reference Clock CMU0_PLL CMU0 Clock Divider FPGA Fabric CMU0_Channel Low-Speed Parallel Clock High-Speed Serial Clock Channel 1 Channel 0 Transmitter Channel PCS Byte Serializer TX Phase Compensation FIFO wrclk Serializer rdclk wrclk rdclk 8B/10B Encoder Transmitter Channel PMA tx_coreclk[1:0] /2 Low-Speed Parallel Clock from CMU 0 Clock Divider Channel 1 Receiver Channel PCS Channel 0 RX Phase Compensation FIFO Byte Deserializer rx_coreclk[1:0] 8B/10B Decoder Rate Match FIFO Channel Aligner Word Aligner Ch0 Parallel Recovered Clock Receiver Channel PMA DeSerializer CDR Ch2 Parallel Recovered Clock /2 Low-Speed Parallel Clock from CMU 0 Clock Divider XGMII-To-PCS Code Conversion at the Transmitter In XAUI mode, the 8b/10b encoder in the Arria II GX transmitter datapath is controlled by a transmitter state machine that maps various 8-bit XGMII codes to 10-bit PCS code groups. This state machine complies with the IEEE P802.3ae PCS transmit source state diagram shown in Figure 1-85. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-108 Chapter 1: Arria II GX Transceiver Architecture Functional Modes Figure 1-85. XGMII-To-PCS Code Conversion in XAUI Mode (Note 1) !reset !(TX=||IDLE|| + TX=||Q|| SEND_Q IF TX=||T|| THEN cvtx_terminate tx_code_group<39:0> ENCODE(TX) PUDR (next_ifg + A_CNT0) next_ifg = A_CNT0 reset SEND_A SEND_K tx_code_group<39:0> ||A|| next_ifg K PUDR Q_det tx_code_group<39:0> ||K|| next_ifg A PUDR !Q_det UCT B SEND_Q tx_code_group<39:0> TQMSG Q_det K PUDR A A_CNT0 * cod_sel=1 B UCT SEND_RANDOM_K tx_code_group<39:0> ||K|| PUDR SEND_RANDOM_R tx_code_group<39:0> ||R|| A_CNT0 * cod_sel=1 B A_CNT0 * cod_sel=1 A A_CNT=0 A_CNT=0 A SEND_RANDOM_A A_CNT0 * cod_sel=1 tx_code_group<39:0> ||A|| PUDR Q_det B !Q_det * cod_sel=1 SEND_RANDOM_Q tx_code_group<39:0> TQMSG Q_det FALSE PUDR B A A !Q_det * cod_set=1 cod_set=1 cod_set=1 Note to Figure 1-85: (1) Source: IEEE P802.3ae TM -2002, IEEE Standard for Information technology - Telecommunications and information exchange between systems Local and metropolitan area networks - Specific requirements Part 3: Carrier sense multiple access with collision detection (CSMA/CD) access method and physical layer specifications. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Functional Modes 1-109 Table 1-35 lists the XGMII-to-PCS code group conversion in XAUI functional mode. The XGMII TXC control signal is equivalent to the tx_ctrlenable signal; the XGMII TXD control signal is equivalent to the tx_datain[7:0] signal. Table 1-35. XGMII Character to PCS Code-Group Mapping XGMII TXC XGMII TXD (1) PCD Code Group Description 0 00 through FF Dxx,y Normal data transmission 1 07 K28.0 or K28.3 or K28.5 Idle in ||I|| 1 07 K28.5 Idle in ||T|| 1 9C K28.4 Sequence 1 FB K27.7 Start 1 FD K29.7 Terminate 1 FE K30.7 Error 1 Any other value K30.7 Invalid XGMII character Note to Table 1-35: (1) The values in the XGMII TXD column are in hexadecimal. PCS-To-XGMII Code Conversion at the Receiver In XAUI mode, the 8b/10b decoder in the Arria II GX receiver datapath is controlled by a XAUI receiver state machine that converts received PCS code groups into specific 8-bit XGMII codes. Table 1-36 lists the PCS-to-XGMII code group conversion in XAUI functional mode. The XGMII RXC control signal is equivalent to the rx_ctrldetect signal; the XGMII RXD control signal is equivalent to the rx_dataout[7:0] signal. Table 1-36. PCS Code Group to XGMII Character Mapping XGMII RXC XGMII RXD (1) PCD Code Group Description 0 00 through FF Dxx,y Normal data transmission 1 07 K28.0 or K28.3 or K28.5 Idle in ||I|| 1 07 K28.5 Idle in ||T|| 1 9C K28.4 Sequence 1 FB K27.7 Start 1 FD K29.7 Terminate 1 FE K30.7 Error 1 FE Invalid code group Received code group Note to Table 1-36: (1) The values in the XGMII RXD column are in hexadecimal. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-110 Chapter 1: Arria II GX Transceiver Architecture Functional Modes Word Aligner The word aligner in XAUI functional mode is configured in automatic synchronization state machine mode. The Quartus II software automatically configures the synchronization state machine to indicate synchronization when the receiver acquires four /K28.5/ comma code groups without intermediate invalid code groups. The synchronization state machine implemented in XAUI mode is compliant to the PCS synchronization state diagram specified in Clause 48 of the IEEE P802.3ae specification and is shown in Figure 1-86. Figure 1-86. IEEE 802.3ae PCS Synchronization State Diagram (Note 1) power_on=TRUE+mr_main_rest=TRUE + (signal_detectCHANGE=TRUE + mr_loopback=FALSE +PUDI) LOSS_OF_SYNC [PUDI * signal_detect=FAIL + mr_loopback=FALSE] + PUDI(![/COMMA/]) sync_status FAIL rx_even ! rx_even SUDI (signal_detect=OK+mr_loopback=TRUE)* * PUDI([/COMMA/] COMMA_DETECT_1 rx_even TRUE SUDI PUDI(![/|DV|/] PUDI([/|DV|/] ACQUIRE_SYNC_1 PUDI(![/COMMA/] *[/INVALID/] rx_even ! rx_even SUDI cgbad rx_even=FALSE+PUDI([/COMMA/] COMMA_DETECT_2 rx_even TRUE SUDI PUDI(![/|DV|/] PUDI([/|DV|/] ACQUIRE_SYNC_2 PUDI(![/COMMA/] *[/INVALID/] rx_even ! rx_even SUDI cgbad rx_even=FALSE+PUDI([/COMMA/] COMMA_DETECT_3 SYNC_ACQUIRED_1 rx_even TRUE SUDI PUDI(![/|DV|/] PUDI([/|DV|/] sync_status OK rx_even ! rx_even SUDI cgbad cggood 2 cggood SYNC_ACQUIRED_2 SYNC_ACQUIRED_2A rx_even ! rx_even SUDI good_cgs 0 rx_even ! rx_even SUDI good_cgs good_cgs + 1 cgbad cggood *good_cgs = 3 cgbad cggood *good_cgs = 3 3 cggood SYNC_ACQUIRED_3 SYNC_ACQUIRED_3A rx_even ! rx_even SUDI good_cgs 0 rx_even ! rx_even SUDI good_cgs good_cgs + 1 cggood *good_cgs = 3 cgbad cgbad 2 cggood *good_cgs = 3 cggood SYNC_ACQUIRED_4 SYNC_ACQUIRED_4A rx_even ! rx_even SUDI good_cgs 0 rx_even ! rx_even SUDI good_cgs good_cgs + 1 cggood *good_cgs = 3 cgbad cgbad 3 cggood *good_cgs = 3 Note to Figure 1-86: (1) Source: IEEE P802.3ae TM -2002, IEEE Standard for Information technology - Telecommunications and information exchange between systems Local and metropolitan area networks - Specific requirements Part 3: Carrier sense multiple access with collision detection (CSMA/CD) access method and physical layer specifications. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Functional Modes 1-111 Receiver synchronization is indicated on the rx_syncstatus port of each channel. A high on the rx_syncstatus port indicates that the lane is synchronized; a low on the rx_syncstatus port indicates that it has fallen out of synchronization. The receiver loses synchronization when it detects four invalid code groups separated by less than four valid code groups, or when it is reset. Deskew FIFO Code groups received across four lanes in a XAUI link can be misaligned with respect to one another because of skew in the physical medium or differences between the independent clock recoveries per lane. The XAUI protocol allows a maximum skew of 40 UI (12.8 ns) as seen at the receiver of the four lanes. The XAUI protocol requires the physical layer device to implement a deskew circuitry to align all four channels. To enable the deskew circuitry at the receiver to align the four channels, the transmitter sends a /A/ (/K28.3/) code group simultaneously on all four channels during inter-packet gap. The skew introduced in the physical medium and the receiver channels can be /A/ code groups to be received misaligned with respect to each other. The deskew operation is performed by the deskew FIFO in XAUI functional mode. The deskew FIFO in each channel receives data from its word aligner. The deskew operation begins only after link synchronization is achieved on all four channels, as indicated by a high on the rx_syncstatus signal from the word aligner in each channel. Until the first /A/ code group is received, the deskew FIFO read and write pointers in each channel are not incremented. After the first /A/ code group is received, the write pointer starts incrementing for each word received but the read pointer is frozen. If the /A/ code group is received on each of the four channels within 10 recovered clock cycles of each other, the read pointer of all four deskew FIFOs is released simultaneously, aligning all four channels. Figure 1-87 shows lane skew at the receiver input and how the deskew FIFO uses the /A/ code group to align the channels. Figure 1-87. Receiver Input Lane Skew in XAUI Mode Lane 0 K Lane 2 K R A K R R K K R K R Lane 1 K K R A K R R K K R K K R A K R R K K R K R K K R A K R R K K R K K Lane 3 (c) March 2009 R Lanes Skew at Receiver Input R Lane 0 K K R A K R R K K R K R Lane 1 K K R A K R R K K R K R Lane 2 K K R A K R R K K R K R Lane 3 K K R A K R R K K R K R Altera Corporation Lanes are Deskewed by Lining up the "Align"/A/, Code Groups Arria II GX Device Handbook Volume 2 1-112 Chapter 1: Arria II GX Transceiver Architecture Functional Modes After alignment of the first ||A|| column, if three additional aligned ||A|| columns are observed at the output of the deskew FIFOs of the four channels, the rx_channelaligned signal is asserted high, indicating channel alignment is acquired. After acquiring channel alignment, if four misaligned ||A|| columns are seen at the output of the deskew FIFOs in all four channels with no aligned ||A|| columns in between, the rx_channelaligned signal is deasserted low, indicating loss of channel alignment. The deskew FIFO operation in XAUI functional mode is compliant to the PCS deskew state machine diagram specified in clause 48 of the IEEE P802.3ae, as shown in Figure 1-88. Figure 1-88. Deskew FIFO in XAUI Mode (Note 1) reset + (sync_status=FAIL * SUDI) LOSS_OF_ALIGNMENT SUDI(![/||A||/]) align_status FAIL enable_deskew TRUE AUDI sync_status OK * SUDI(![/||A||/]) ALIGN_DETECT_1 !deskew_error * SUDI(![/||A||/]) enable_deskew FALSE AUDI deskew_error * SUDI SUDI(![/||A||/]) ALIGN_DETECT_2 AUDI !deskew_error * SUDI(![/||A||/]) deskew_error * SUDI SUDI(![/||A||/]) ALIGN_DETECT_3 AUDI !deskew_error * SUDI(![/||A||/]) deskew_error * SUDI A SUDI(![/||A||/]) ALIGN_ACQUIRED_1 !deskew_error * SUDI(![/||A||/]) enable_deskew FALSE AUDI deskew_error * SUDI B SUDI(![/||A||/]) ALIGN_ACQUIRED_2 AUDI !deskew_error * SUDI(![/||A||/]) deskew_error * SUDI C SUDI(![/||A||/]) A ALIGN_ACQUIRED_3 AUDI !deskew_error * SUDI(![/||A||/]) deskew_error * SUDI SUDI(![/||A||/]) B ALIGN_ACQUIRED_4 AUDI deskew_error * SUDI !deskew_error * SUDI(![/||A||/]) SUDI(![/||A||/]) C Note to Figure 1-88: (1) Source: IEEE P802.3ae TM -2002, IEEE Standard for Information technology - Telecommunications and information exchange between systems Local and metropolitan area networks - Specific requirements Part 3: Carrier sense multiple access with collision detection (CSMA/CD) access method and physical layer specifications. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Functional Modes 1-113 Rate Match FIFO In XAUI mode, the rate match FIFO is capable of compensating up to 100 PPM (total 200 PPM total) difference between the upstream transmitter and the local receiver reference clock. The XAUI protocol requires the transmitter to send /R/ (/K28.0/) code groups simultaneously on all four lanes (denoted as ||R|| column) during inter-packet gaps, adhering to rules listed in the IEEE P802.3ae specification. The rate match FIFO operation in XAUI mode is compliant to the IEEE P802.3ae specification. The rate match operation begins after: The synchronization state machine in the word aligner of all four channels indicates synchronization acquired by driving its rx_syncstatus signal high The deskew FIFO indicates alignment acquired by driving the rx_channelaligned signal high The rate match FIFO looks for the ||R|| column (simultaneous /R/ code groups on all four channels) and deletes or inserts ||R|| columns to prevent the rate match FIFO from overflowing or under running. The rate match FIFO can insert or delete as many ||R|| columns as necessary to perform the rate match operation. Two flags, rx_rmfifodatadeleted and rx_rmfifodatainserted, that indicate rate match FIFO deletion and insertion events, respectively, are forwarded to the FPGA fabric. If an ||R|| column is deleted, the rx_rmfifodeleted flag from each of the four channels goes high for one clock cycle per deleted ||R|| column. If an ||R|| column is inserted, the rx_rmfifoinserted flag from each of the four channels goes high for one clock cycle per inserted ||R|| column. Figure 1-89 shows an example of rate match deletion in the case where three ||R|| columns are required to be deleted. Figure 1-89. Example of Rate Match Deletion in XAUI Mode First ||R|| Column Second ||R|| Column Third ||R|| Column Fourth ||R|| Column datain[3] K28.5 K28.3 K28.5 K28.0 K28.5 K28.0 K28.0 K28.0 K28.5 datain[2] K28.5 K28.3 K28.5 K28.0 K28.5 K28.0 K28.0 K28.0 K28.5 datain[1] K28.5 K28.3 K28.5 K28.0 K28.5 K28.0 K28.0 K28.0 K28.5 datain[0] K28.5 K28.3 K28.5 K28.0 K28.5 K28.0 K28.0 K28.0 K28.5 dataout[3] K28.5 K28.3 K28.5 K28.5 K28.0 K28.5 dataout[2] K28.5 K28.3 K28.5 K28.5 K28.0 K28.5 dataout[1] K28.5 K28.3 K28.5 K28.5 K28.0 K28.5 dataout[0] K28.5 K28.3 K28.5 K28.5 K28.0 K28.5 rx_rmfifodatadeleted (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-114 Chapter 1: Arria II GX Transceiver Architecture Functional Modes Figure 1-90 shows an example of rate match insertion in the case where two ||R|| columns are required to be inserted. Figure 1-90. Example of Rate Match Insertion in XAUI Mode First ||R|| Column Second ||R|| Column dataout[3] K28.5 K28.3 K28.5 K28.0 K28.5 K28.0 dataout[2] K28.5 K28.3 K28.5 K28.0 K28.5 K28.0 dataout[1] K28.5 K28.3 K28.5 K28.0 K28.5 K28.0 dataout[0] K28.5 K28.3 K28.5 K28.0 K28.5 K28.0 datain[3] K28.5 K28.3 K28.5 K28.0 K28.0 K28.0 K28.5 K28.0 datain[2] K28.5 K28.3 K28.5 K28.0 K28.0 K28.0 K28.5 K28.0 datain[1] K28.5 K28.3 K28.5 K28.0 K28.0 K28.0 K28.5 K28.0 datain[0] K28.5 K28.3 K28.5 K28.0 K28.0 K28.0 K28.5 K28.0 rx_rmfifodatadeleted GIGE Mode IEEE 802.3 defines the 1000 Base-X PHY as an intermediate, or transition, layer that interfaces various physical media with the media access control (MAC) in a gigabit ethernet system. It shields the MAC layer from the specific nature of the underlying medium. The 1000 Base-X PHY is divided into three sublayers: the physical coding sublayer the physical media attachment the physical medium dependent (PMD) The PCS sublayer interfaces with the MAC through the gigabit medium independent interface (GMII). The 1000 Base-X PHY defines a physical interface data rate of 1.25 Gbps. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Functional Modes 1-115 Figure 1-91 shows the 1000 Base-X PHY position in a Gigabit Ethernet OSI reference model. Figure 1-91. 1000 Base-X PHY in a Gigabit Ethernet OSI Reference Model LAN CSMA/CD Layers OSI Reference Model Layers Higher Layers LLC Application MAC (Optional) Presentation MAC Session Transport Reconciliation GMII Network Data Link PCS PMA PMD 1000 Base-X PHY Physical Medium Arria II GX transceivers, when configured in GIGE functional mode, have built-in circuitry to support the following PCS and PMA functions defined in the IEEE 802.3 specification: 1 (c) March 2009 8B/10B encoding and decoding Synchronization Upstream transmitter and local receiver clock frequency compensation (rate matching) Clock recovery from the encoded data forwarded by the receiver PMD Serialization and deserialization Arria II GX transceivers do not have built-in support for other PCS functions; for example, auto-negotiation state machine, collision-detect, and carrier-sense. If required, you must implement these functions in a PLD logic array or external circuits. Altera Corporation Arria II GX Device Handbook Volume 2 1-116 Chapter 1: Arria II GX Transceiver Architecture Functional Modes Figure 1-92 shows the GIGE mode configuration supported in Arria II GX devices. Figure 1-92. GIGE Mode Arria II GX Configurations Protocol Basic Single Width Functional Modes PMA-PCS Interface Width 8-bit 10-bit PIPE XAUI GIGE SRIO SONET /SDH 10-bit 10-bit 10-bit 10-bit 8-bit Functional Mode GIGE Data Rate (Gbps) 1.25 Channel Bonding x1 Low-Latency PCS Disabled Word Aligner (Pattern Length) Automatic Synchronization State Machine (7-Bit Comma, 10-Bit /K28.5/) 8B/10B Encoder/Decoder Enabled Rate Match FIFO Enabled Byte SerDes Disabled Byte Ordering Disabled FPGA Fabric-Transceiver Interface Width 8-Bit FPGA Fabric-Transceiver Interface Frequency (MHz) 125 Arria II GX Device Handbook Volume 2 ( ) SDI 10-bit (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Functional Modes 1-117 GIGE Mode Datapath Figure 1-93 shows the transceiver datapath when configured in GIGE functional mode. Figure 1-93. GIGE Mode Datapath Transmitter Channel PMA Transmitter Channel PCS FPGA Fabric TX Phase Compensation FIFO wrclk rdclk 8B/10B Encoder Serializer tx_coreclk[0] High-Speed Serial Clock Local Clock Divider Low-Speed Parallel Clock tx_clkout[0] FPGA Fabric-Transceiver Interface Clock Receiver Channel PCS RX Phase Compensation FIFO 8B/10B Decoder Rate Match FIFO Receiver Channel PMA Word Aligner DeSerializer CDR Parallel Recovered Clock rx_coreclk[0] Low-Speed Parallel Clock Table 1-37 shows the transceiver datapath clock frequencies in GIGE functional mode. Table 1-37. Transceiver Datapath Clock Frequencies in GIGE Mode Functional Mode Data Rate High-Speed Serial Clock Frequency GIGE 1.25 Gbps 625 MHz Parallel Recovered Clock and Low-Speed Parallel Clock Frequency FPGA Fabric-Transceiver Interface Clock Frequency 125 MHz 125 MHz 8B/10B Encoder In GIGE mode, the 8B/10B encoder clocks in 8-bit data and a 1-bit control identifier from the transmitter phase compensation FIFO and generates 10-bit encoded data. The 10-bit encoded data is fed to the serializer. Refer to "8B/10B Encoder" on page 1-31 for more information about 8B/10B encoder functionality. GIGE Protocol--Ordered Sets and Special Code Groups Table 1-38 lists ordered sets and special code groups specified in the IEEE802.3 specification. Table 1-38. GIGE Ordered Sets (Part 1 of 2) Code Ordered Set Number of Code Groups Encoding /C/ Configuration -- Alternating /C1/ and /C2/ /C1/ Configuration 1 4 /K28.5/D21.5/Config_Reg (1) /C2/ Configuration 2 4 /K28.5/D2.2/Config_Reg (1) (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-118 Chapter 1: Arria II GX Transceiver Architecture Functional Modes Table 1-38. GIGE Ordered Sets (Part 2 of 2) Code Ordered Set Number of Code Groups Encoding /I/ IDLE -- Correcting /I1/, Preserving /I2/ /I1/ IDLE 1 2 /K28.5/D5.6 /I2/ IDLE 2 2 /K28.5/D16.2 Encapsulation -- -- /R/ Carrier_Extend 1 /K23.7/ /S/ Start_of_Packet 1 /K27.7/ /T/ End_of_Packet 1 /K29.7/ /V/ Error_Propagation 1 /K30.7/ Note to Table 1-38: (1) Two data code groups represent the Config_Reg value. Idle Ordered-Set Generation The IEEE 802.3 specification requires the GIGE PHY to transmit idle ordered sets (/I/) continuously and repetitively whenever the GMII is idle. This ensures that the receiver maintains bit and word synchronization whenever there is no active data to be transmitted. In GIGE functional mode, any /Dx.y/ following a /K28.5/ comma is replaced by the transmitter with either a /D5.6/ (/I1/ ordered set) or a /D16.2/ (/I2/ ordered set), depending on the current running disparity. The exception is when the data following the /K28.5/ is /D21.5/ (/C1/ ordered set) or /D2.2/ (/C2/) ordered set. If the running disparity before the /K28.5/ is positive, an /I1/ ordered set is generated. If the running disparity is negative, a /I2/ ordered set is generated. The disparity at the end of a /I1/ is the opposite of that at the beginning of the /I1/. The disparity at the end of a /I2/ is the same as the beginning running disparity (right before the idle code). This ensures a negative running disparity at the end of an idle ordered set. A /Kx.y/ following a /K28.5/ is not replaced. 1 Note that /D14.3/, /D24.0/, and /D15.8/ are replaced by /D5.6/ or /D16.2/ (for /I1/, /I2/ ordered sets). /D21.5/ (part of the /C1/ order set) is not replaced. Figure 1-94 shows the automatic idle ordered set generation. Figure 1-94. Example of Automatic Ordered Set Generation clock tx_datain [ ] K28.5 D14.3 K28.5 D24.0 K28.5 D15.8 K28.5 D21.5 Dx.y tx_dataout Dx.y K28.5 D5.6 K28.5 D16.2 K28.5 D16.2 K28.5 D21.5 Ordered Set Arria II GX Device Handbook Volume 2 /I1/ /I2/ /I2/ /C2/ (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Functional Modes 1-119 Reset Condition After de-assertion of tx_digitalreset, the GIGE transmitter automatically transmits three /K28.5/ comma code groups before transmitting user data on the tx_datain port. This could affect the synchronization state machine behavior at the receiver. Depending on when you start transmitting the synchronization sequence, there could be an even or odd number of /Dx.y/ code groups transmitted between the last of the three automatically sent /K28.5/ code groups and the first /K28.5/ code group of the synchronization sequence. If there is an even number of /Dx.y/ code groups received between these two /K28.5/ code groups, the first /K28.5/ code group of the synchronization sequence begins at an odd code group boundary (rx_even = FALSE). An IEEE802.3-compliant GIGE synchronization state machine treats this as an error condition and goes into Loss of Sync state. Figure 1-95 shows an example of even numbers of /Dx.y/ between the last automatically sent /K28.5/ and the first user-sent /K28.5/. The first user-sent /K28.5/ code group received at an odd code group boundary in cycle n + 3 takes the receiver synchronization state machine in Loss of Sync state. The first synchronization ordered-set /K28.5/Dx.y/ in cycles n + 3 and n + 4 is discounted and three additional ordered sets are required for successful synchronization. Figure 1-95. Example of Reset Condition in GIGE Mode n n+1 n+2 n+3 n+4 K28.5 Dx.y Dx.y K28.5 Dx.y clock tx_digitalreset tx_dataout K28.5 xxx K28.5 K28.5 K28.5 Dx.y K28.5 Dx.y Word Aligner The word aligner in GIGE functional mode is configured in automatic synchronization state machine mode. The Quartus II software automatically configures the synchronization state machine to indicate synchronization when the receiver acquires three consecutive synchronization ordered sets. A synchronization ordered set is a /K28.5/ code group followed by an odd number of valid /Dx.y/ code groups. The fastest way for the receiver to achieve synchronization is to receive three continuous {/K28.5/, /Dx.y/} ordered set. Receiver synchronization is indicated on the rx_syncstatus port of each channel. A high on the rx_syncstatus port indicates that the lane is synchronized; a low on the rx_syncstatus port indicates that the lane has fallen out of synchronization. The receiver loses synchronization when it detects four invalid code groups separated by less than three valid code groups, or when it is reset. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-120 Chapter 1: Arria II GX Transceiver Architecture Functional Modes Table 1-39 lists the synchronization state machine parameters when configured in GIGE mode. Table 1-39. Synchronization State Machine Parameters in GIGE Functional Mode Synchronization State Machine Parameters Setting Number of valid {/K28.5/, /Dx,y/} ordered-sets received to achieve synchronization 3 Number of errors received to lose synchronization 4 Number of continuous good code groups received to reduce the error count by 1 4 Figure 1-96 shows the synchronization state machine implemented in GIGE mode. Figure 1-96. Synchronization State Machine in GIGE Mode (Note 1) power_on=TRUE+mr_main_rest=TRUE + (signal_detectCHANGE=TRUE + mr_loopback=FALSE +PUDI) LOSS_OF_SYNC [PUDI * signal_detect=FAIL + mr_loopback=FALSE] + PUDI(![/COMMA/]) sync_status FAIL rx_even ! rx_even SUDI (signal_detect=OK+mr_loopback=TRUE)* * PUDI([/COMMA/] COMMA_DETECT_1 rx_even TRUE SUDI PUDI(![/|DV|/] PUDI([/|DV|/] ACQUIRE_SYNC_1 PUDI(![/COMMA/] *[/INVALID/] rx_even ! rx_even SUDI cgbad rx_even=FALSE+PUDI([/COMMA/] COMMA_DETECT_2 rx_even TRUE SUDI PUDI(![/|DV|/] PUDI([/|DV|/] ACQUIRE_SYNC_2 PUDI(![/COMMA/] *[/INVALID/] rx_even ! rx_even SUDI cgbad rx_even=FALSE+PUDI([/COMMA/] COMMA_DETECT_3 SYNC_ACQUIRED_1 rx_even TRUE SUDI PUDI(![/|DV|/] PUDI([/|DV|/] sync_status OK rx_even ! rx_even SUDI cgbad cggood 2 cggood SYNC_ACQUIRED_2 SYNC_ACQUIRED_2A rx_even ! rx_even SUDI good_cgs 0 rx_even ! rx_even SUDI good_cgs good_cgs + 1 cgbad cggood *good_cgs = 3 cgbad cggood *good_cgs = 3 3 cggood SYNC_ACQUIRED_3 SYNC_ACQUIRED_3A rx_even ! rx_even SUDI good_cgs 0 rx_even ! rx_even SUDI good_cgs good_cgs + 1 cggood *good_cgs = 3 cgbad cgbad 2 cggood *good_cgs = 3 cggood SYNC_ACQUIRED_4 SYNC_ACQUIRED_4A rx_even ! rx_even SUDI good_cgs 0 rx_even ! rx_even SUDI good_cgs good_cgs + 1 cggood *good_cgs = 3 cgbad cgbad 3 cggood *good_cgs = 3 Note to Figure 1-96: (1) Source: IEEE P802.3ae TM -2002, IEEE Standard for Information technology - Telecommunications and information exchange between systems Local and metropolitan area networks - Specific requirements Part 3: Carrier sense multiple access with collision detection (CSMA/CD) access method and physical layer specifications. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Functional Modes 1-121 Rate Match FIFO In GIGE mode, the rate match FIFO is capable of compensating up to 100 PPM (total 200 PPM total) difference between the upstream transmitter and the local receiver reference clock. The GIGE protocol requires the transmitter to send idle ordered sets /I1/ (/K28.5/D5.6/) and /I2/ (/K28.5/D16.2/) during inter-packet gaps, adhering to the rules listed in the IEEE 802.3 specification. The rate match operation begins after the synchronization state machine in the word aligner indicates synchronization is acquired by driving the rx_syncstatus signal high. The rate matcher deletes or inserts both symbols (/K28.5/ and /D16.2/) of the /I2/ ordered sets, even if it requires deleting only one symbol to prevent the rate match FIFO from overflowing or under running. It can insert or delete as many /I2/ ordered sets as necessary to perform the rate match operation. Two flags, rx_rmfifodatadeleted and rx_rmfifodatainserted, indicating rate match FIFO deletion and insertion events, respectively, are forwarded to the FPGA fabric. Both the rx_rmfifodatadeleted and rx_rmfifodatainserted flags are asserted for two clock cycles for each deleted and inserted /I2/ ordered-set, respectively. Figure 1-97 shows an example of rate match FIFO deletion in the case where three symbols are required to be deleted. Because the rate match FIFO can only delete /I2/ ordered set, it deletes two /I2/ ordered sets (four symbols deleted). Figure 1-97. Example of Rate Match Deletion in GIGE Mode /I2/ SKIP Symbol Deleted First /I2/ Skip Ordered Set Second /I2/ Skip Ordered Set Third /I2/ Skip Ordered Set datain Dx.y K28.5 D16.2 K28.5 dataout Dx.y K28.5 D16.2 Dx.y D16.2 K28.5 D16.2 Dx.y rx_rmfifodatadeleted Figure 1-98 shows an example of rate match FIFO insertion in the case where one symbol is required to be inserted. Because the rate match FIFO can only delete /I2/ ordered set, it inserts one /I2/ ordered sets (two symbols inserted). Figure 1-98. Example of Rate Match Insertion in GIGE Mode First /I2/ Ordered Set Second /I2/ Ordered Set datain Dx.y K28.5 D16.2 K28.5 D16.2 dataout Dx.y K28.5 D16.2 K28.5 D16.2 K28.5 D16.2 Dx.y rx_rmfifodatainserted (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-122 Chapter 1: Arria II GX Transceiver Architecture Functional Modes SONET/SDH Mode SONET/SDH is one of the most common serial-interconnect protocols used in backplanes deployed in communications and telecom applications. SONET/SDH defines various optical carrier (OC) subprotocols for carrying signals of different capacities through a synchronous optical hierarchy. SONET/SDH Frame Structure Base OC-1 frames are byte-interleaved to form SONET/SDH frames. For example, 12 OC-1 frames are byte-interleaved to form 1 OC-12 frame; 48 OC-1 frames are byteinterleaved to form 1 OC-48 frame and so on. SONET/SDH frame sizes are constant, with a frame transfer rate of 125 s. Figure 1-99 shows the SONET/SDH frame structure. Figure 1-99. SONET/SDH Mode Nx3 Bytes Transport Overhead NxA1 Nx3 Bytes Payload NxA2 NxJ0/Z0 9 Rows Transport overhead bytes A1 and A2 are used for restoring frame boundary from the serial data stream. Frame sizes are fixed, so the A1 and A2 bytes appear within the serial data stream every 125 s . In an OC-12 system, 12 A1 bytes are followed by 12 A2 bytes. Similarly, in an OC-48 system, 48 A1 bytes are followed by 48 A2 bytes. In SONET/SDH systems, byte values of A1 and A2 are fixed as follows: A1 = 11110110 or 8'hF6 A2 = 00101000 or 8'h28 You can employ Arria II GX transceivers as physical layer devices in a SONET/SDH system. These transceivers provide support for SONET/SDH protocol-specific functions and electrical features; for example, alignment to A1A2 or A1A1A2A2 pattern. Arria II GX transceivers are designed to support the following three SONET/SDH subprotocols: OC-12 at 622 Mbps with 8-bit channel width OC-48 at 2488.32 Mbps with 16-bit channel width Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Functional Modes 1-123 Figure 1-100 shows SONET/SDH mode configurations supported in Arria II GX devices. Figure 1-100. SONET/SDH Mode Configurations in Arria II GX Devices Arria II GX Configurations Protocol Basic Single Width Functional Modes PMA-PCS Interface Width 8-bit 10-bit PIPE XAUI GIGE SRIO SONET /SDH SDI 10-bit 10-bit 10-bit 10-bit 8-bit 10-bit SONET/ SDH Functional Mode Data Rate (Gbps) 0.622 (OC-12) 2.488 (OC-48) x1 x1 Disabled Disabled Manual Alignment (16-Bit A1A2, 32-Bit A1A1A2A2) Manual Alignment (16-Bit A1A2, 32-Bit A1A1A2A2) Disabled Disabled Disabled Disabled Disabled Enabled Disabled Enabled 8-Bit 16-Bit 77.75 155.5 Channel Bonding Low-Latency PCS Word Aligner (Pattern Length) 8B/10B Encoder/Decoder Rate Match FIFO Byte SerDes Byte Ordering FPGA Fabric-Transceiver Interface Width FPGA Fabric-Transceiver Interface Frequency (MHz) (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-124 Chapter 1: Arria II GX Transceiver Architecture Functional Modes SONET/SDH OC-12 Datapath Figure 1-101 shows the transceiver datapath when configured in SONET/SDH OC-12 mode. Figure 1-101. SONET/SDH OC-12 Datapath Transmitter Channel PCS FPGA Fabric Transmitter Channel PMA TX Phase Compensation FIFO wrclk Serializer rdclk tx_coreclk High-Speed Serial Clock Low-Speed Parallel Clock Local Clock Divider tx_clkout FPGA Fabric-Transmitter Interface Clock Receiver Channel PCS RX Phase Compensation FIFO Word Aligner Receiver Channel PMA DeSerializer CDR rx_coreclk Parallel Recovered Clock rx_clkout FPGA Fabric-Receiver Interface Clock SONET/SDH OC-48 Datapath Figure 1-102 shows the transceiver datapath when configured in SONET/SDH OC-48 mode. Figure 1-102. SONET/SDH OC-48 Datapath FPGA Fabric Transmitter Channel PCS TX Phase Compensation FIFO wrclk Transmitter Channel PMA Byte Serializer Serializer rdclk rdclk wrclk tx_coreclk High-Speed Serial Clock /2 Low-Speed Parallel Clock tx_clkout FPGA Fabric-Transmitter Interface Clock Receiver Channel PCS RX Phase Compensation FIFO rx_coreclk Byte Ordering Byte Deserializer Word Aligner Local Clock Divider Receiver Channel PMA DeSerializer CDR /2 Parallel Recovered Clock rx_clkout FPGA Fabric-Receiver Interface Clock Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Functional Modes 1-125 SONET/SDH Transmission Bit Order Unlike Ethernet, where the LSB of the parallel data byte is transferred first, SONET/SDH requires the MSB to be transferred first and the LSB to be transferred last. To facilitate the MSB-to-LSB transfer, you must enable the following options in the ALTGX MegaWizard Plug-In Manager: Flip transmitter input data bits Flip receiver output data bits Depending on whether data bytes are transferred MSB-to-LSB or LSB-to-MSB, you must select the appropriate word aligner settings in the ALTGX MegaWizard Plug-In Manager. Table 1-40 lists the correct word aligner settings for each bit transmission order. Word Alignment The word aligner in SONET/SDH OC-12 and OC-48 modes is configured in manual alignment mode as described in "Word Aligner in Single-Width Mode with 8-Bit PMA-PCS Interface Modes" on page 1-58. In OC-12 and OC-48 configurations, you can configure the word aligner to either align to a 16-bit A1A2 pattern or a 32-bit A1A1A2A2 pattern. This is controlled by the rx_a1a2size input port to the transceiver. A low level on the rx_a1a2size port configures the word aligner to align to a 16-bit A1A2 pattern; a high level on the rx_a1a2size port configures the word aligner to align to a 32-bit A1A1A2A2 pattern. You can configure the word aligner to flip the alignment pattern bits programmed in the wizard and compare them with the incoming data for alignment. This feature offers flexibility to the SONET backplane system for either a MSBit-to-LSBit or LSBit-to-MSBit data transfer. Table 1-40 lists word alignment patterns that you must program in the ALTGX MegaWizard Plug-In Manager based on the bit-transmission order and the word aligner bit-flip option. Table 1-40. Word Aligner Settings Serial Bit Transmission Order Word Alignment Bit Flip Word Alignment Pattern MSBit-to-LSBit On 1111011000101000 (16'hF628) MSBit-to-LSBit Off 0001010001101111 (16'h146F) LSBit-to-MSBit Off 0010100011110110 (16'h28F6) The behavior of the SONET/SDH word aligner control and status signals along with an operational timing diagram are explained in "Word Aligner in Single-Width Mode with 8-Bit PMA-PCS Interface Modes" on page 1-58. OC-48 Byte Serializer and Deserializer The OC-48 transceiver datapath includes the byte serializer and deserializer to allow the PLD interface to run at a lower speed. The OC-12 configuration does not use the byte serializer and deserializer blocks. The byte serializer and deserializer blocks are explained in "Byte Serializer" on page 1-30 and "Byte Deserializer" on page 1-79, respectively. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-126 Chapter 1: Arria II GX Transceiver Architecture Functional Modes The OC-48 byte serializer converts 16-bit data words from the FPGA fabric and translates the 16-bit data words into two 8-bit data bytes at twice the rate. The OC-48 byte deserializer takes in two consecutive 8-bit data bytes and translates them into a 16-bit data word to the FPGA fabric at half the rate. OC-48 Byte Ordering Because of byte deserialization, the most significant byte of a word might appear at the rx_dataout port along with the least significant byte of the next word. In an OC-48 configuration, the byte ordering block is built into the datapath and can be used to perform byte ordering. Byte ordering in an OC-48 configuration is automatic, as explained in "Word-Alignment-Based Byte Ordering" on page 1-81. In automatic mode, the byte ordering block is triggered by the rising edge of the rx_syncstatus signal. As soon as the byte ordering block sees the rising edge of the rx_syncstatus signal, it compares the least significant byte coming out of the byte deserializer with the A2 byte of the A1A2 alignment pattern. If the least significant byte coming out of the byte deserializer does not match the A2 byte set in the ALTGX MegaWizard Plug-In Manager, the byte ordering block inserts a PAD character, as seen in Figure 1-103. Insertion of this PAD character enables the byte ordering block to restore the correct byte order. 1 The PAD character is defaulted to the A1 byte of the A1A2 alignment pattern. Figure 1-103. OC-48 Byte Ordering in Automatic Mode From Byte Deserializer To PLD Core rx_dataout (MSB) A1 A1 A2 A2 D0 D2 rx_dataout (LSB) X A1 A1 A2 A2 D1 Byte Ordering Block A1 A1 Pad A2 D1 D3 X A1 A1 A2 D0 D2 rx_clkout rx_syncstatus rx_syncstatus rx_byteorderalignstatus SDI Mode The Society of Motion Picture and Television Engineers (SMPTE) defines various SDI standards for transmission of uncompressed video. The following three SMPTE standards are popular in video broadcasting applications: SMPTE 259M standard--more popularly known as the standard-definition (SD) SDI, is defined to carry video data at 270 Mbps. SMPTE 292M standard--more popularly known as the high-definition (HD) SDI, is defined to carry video data at either 1485 Mbps or 1483.5 Mbps. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Functional Modes 1-127 SMPTE 424M standard--more popularly known as the third-generation (3G) SDI, is defined to carry video data at either 2970 Mbps or 2967 Mbps. You can configure Arria II GX transceivers in HD-SDI or 3G-SDI configuration using the ALTGX MegaWizard Plug-In Manager. Table 1-41 shows ALTGX configurations supported by the Arria II GX transceivers in SDI mode. Table 1-41. ALTGX Configurations in SDI Mode Configuration Data Rate (Mbps) refclk Frequencies (MHz) FPGA Fabric-Transceiver Interface Width HD 1485 74.25, 148.5 10-bit, 20-bit 1483.5 74.175, 148.35 10-bit, 20-bit 2970 148.5, 297 Only 20-bit interface allowed in 3G 2967 148.35, 296.7 Only 20-bit interface allowed in 3G 3G (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-128 Chapter 1: Arria II GX Transceiver Architecture Functional Modes Figure 1-104 shows SDI mode configurations supported in Arria II GX devices. Figure 1-104. SDI Mode Arria II GX Configurations Protocol Basic Single Width Functional Modes PMA-PCS Interface Width 8-bit 10-bit Functional Mode PIPE XAUI GIGE SRIO SONET /SDH SDI 10-bit 10-bit 10-bit 10-bit 8-bit 10-bit SDI Data Rate (Gbps) HD-SDI (1.485/1.4835) 3G-SDI (2.97/2.967) Channel Bonding x1 x1 Low-Latency PCS Disabled Disabled Word Aligner (Pattern Length) Bit-Slip Bit-Slip 8B/10B Encoder/Decoder Disabled Disabled Rate Match FIFO Disabled Disabled Byte SerDes Disabled Enabled Enabled Byte Ordering Disabled Disabled Disabled FPGA Fabric-Transceiver Interface Width 10-Bit 20-Bit 20-bit 148.5/ 148.35 74.25/ 74.175 148.5/ 148.35 FPGA Fabric-Transceiver Interface Frequency (MHz) Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Functional Modes 1-129 SDI Mode Datapath Figure 1-105 shows the transceiver datapath when configured in SDI mode. Figure 1-105. SDI Mode Datapath FPGA Fabric Transmitter Channel PCS TX Phase Compensation FIFO wrclk rdclk Byte Serializer wrclk tx_coreclk Transmitter Channel PMA Serializer rdclk /2 High-Speed Serial Clock Low-Speed Parallel Clock Local Clock Divider tx_clkout FPGA Fabric-Transmitter Interface Clock Receiver Channel PCS RX Phase Compensation FIFO rx_coreclk Byte Deserializer /2 Word Aligner Receiver Channel PMA DeSerializer CDR Parallel Recovered Clock rx_clkout FPGA Fabric-Receiver Interface Clock Transmitter Datapath The transmitter datapath, in HD-SDI configuration with 10-bit wide FPGA fabric-transceiver interface, consists of the transmitter phase compensation FIFO and the 10:1 serializer. The transmitter datapath, in HD-SDI and 3G-SDI configurations with 20-bit wide FPGA fabric-transceiver interface, also includes the byte serializer. 1 In SDI mode, the transmitter is purely a parallel-to-serial converter. SDI transmitter functions, such as scrambling and cyclical redundancy check (CRC) code generation, must be implemented in the FPGA logic array. Receiver Datapath In the 10-bit channel width SDI configuration, the receiver datapath consists of the clock recovery unit (CRU), 1:10 deserializer, word aligner in bit-slip mode, and receiver phase compensation FIFO. In the 20-bit channel width SDI configuration, the receiver datapath also includes the byte deserializer. 1 SDI receiver functions, such as de-scrambling, framing, and CRC checker, must be implemented in the FPGA logic array. Receiver Word Alignment and Framing In SDI systems, the word aligner in the receiver datapath is not useful because word alignment and framing happens after de-scrambling. Altera recommends driving the ALTGXB megafunction rx_bitslip signal low to avoid the word aligner from inserting bits in the received data stream. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-130 Chapter 1: Arria II GX Transceiver Architecture Functional Modes Serial RapidIO Mode The RapidIO Trade Association defines a high-performance, packet-switched interconnect standard to pass data and control information between microprocessors, digital signal, communications, and network processors, system memories, and peripheral devices. Serial RapidIO physical layer specification defines three line rates: 1.25 Gbps 2.5 Gbps 3.125 Gbps It also defines two link widths--single-lane (1x) and bonded four-lane (4x) at each line rate. Arria II GX transceivers support only single-lane (1x) configuration at all three line rates. Four 1x channels configured in Serial RapidIO mode can be instantiated to achieve a 4x Serial RapidIO link. The four transmitter channels in this 4x Serial RapidIO link are not bonded. The four receiver channels in this 4x Serial RapidIO link do not have lane alignment or deskew capability. Figure 1-106 shows the ALTGX transceiver data path when configured in Serial RapidIO mode. Figure 1-106. Serial RapidIO Mode Datapath Transmitter Channel PCS FPGA Fabric TX Phase Compensation FIFO wrclk rdclk 8B/10B Encoder Byte Serializer tx_coreclk[0] Transmitter Channel PMA Serializer High-Speed Serial Clock Local Clock Divider /2 Low-Speed Parallel Clock tx_clkout[0] FPGA Fabric-Transceiver Interface Clock Receiver Channel PCS RX Phase Compensation FIFO Byte DeSerializer Rate Match FIFO 8B/10B Decoder Word Aligner Receiver Channel PMA DeSerializer CDR Parallel Recovered Clock /2 rx_coreclk[0] Low-Speed Parallel Clock Arria II GX transceivers, when configured in Serial RapidIO functional mode, provide the following PCS and PMA functions: 8B/10B encoding/decoding Word alignment Lane Synchronization State Machine Clock recovery from the encoded data Serialization/deserialization Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Functional Modes 1-131 Figure 1-107 shows the Serial RapidIO mode configuration supported in Arria II GX devices. Figure 1-107. Serial RapidIO Mode Arria II GX Configurations Protocol Basic Single Width Functional Modes PMA-PCS Interface Width 8-bit 810-bit PIPE XAUI GIGE SRIO SONET /SDH 10-bit 10-bit 10-bit 10-bit 8-bit ( ) SDI 10-bit Functional Mode Serial RapidIO Serial RapidIO Serial RapidIO Data Rate (Gbps) 1.25 2.5 3.125 Channel Bonding x1 x1 x1 Low-Latency PCS Disabled Disabled Disabled Word Aligner (Pattern Length) Automatic Synchronization State Machine (10-Bit /K28.5/) Automatic Synchronization State Machine (10-Bit /K28.5/) Automatic Synchronization State Machine (10-Bit /K28.5/) 8B/10B Encoder/Decoder Enabled Enabled Enabled Rate Match FIFO Enabled Disabled Enabled Disabled Enabled Disabled Byte SerDes Enabled Enabled Enabled Enabled Enabled Enabled Byte Ordering Disabled Disabled Disabled Disabled Disabled Disabled FPGA Fabric-Transceiver Interface Width 16-Bit 16-Bit 16-Bit 16-Bit 16-Bit 16-Bit FPGA Fabric-Transceiver Interface Frequency (MHz) 62.5 62.5 125 125 156.25 156.25 1 Arria II GX transceivers do not have built-in support for other PCS functions; for example, pseudo-random idle sequence generation and lane alignment in 4x mode. Depending on your system requirements, you must implement these functions in the logic array or external circuits. Synchronization State Machine In Serial RapidIO mode, the ALTGX MegaWizard Plug-In Manager defaults the word alignment pattern to K28.5. The word aligner has a synchronization state machine that handles the receiver lane synchronization. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-132 Chapter 1: Arria II GX Transceiver Architecture Functional Modes The ALTGX MegaWizard Plug-In Manager automatically defaults the synchronization state machine to indicate synchronization when the receiver acquires 127 K28.5 (10'b0101111100 or 10'b1010000011) synchronization code groups without receiving an intermediate invalid code group. Once synchronized, the state machine indicates loss of synchronization when it detects three invalid code groups separated by less than 255 valid code groups, or when it is reset. Receiver synchronization is indicated on the rx_syncstatus port of each channel. A high on the rx_syncstatus port indicates that the lane is synchronized and a low indicates that it has fallen out of synchronization. Table 1-42 lists the ALTGX megafunction synchronization state machine parameters when configured in Serial RapidIO mode. Table 1-42. Synchronization State Machine Parameters in Serial RapidIO Mode Parameters Number Number of valid K28.5 code groups received to achieve synchronization. 127 Number of errors received to lose synchronization. 3 Number of continuous good code groups received to reduce the error count by one. Arria II GX Device Handbook Volume 2 255 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Loopback Modes 1-133 Figure 1-108 gives a conceptual view of the synchronization state machine implemented in Serial RapidIO functional mode. Figure 1-108. Synchronization State Machine in Serial RapidIO Mode Loss of Sync Data = Comma Data = !Valid Comma Detect if Data == Comma kcntr++ else kcntr=kcntr Data = valid; kcntr < 3 kcntr = 127 Synchronized Data=Valid Data = !Valid ecntr = 3 Synchronized Error Detect if Data == !Valid ecntr++ gcntr=0 else if gcntr==255 ecntr-gcntr=0 else gcntr++ ecntr = 0 Loopback Modes Arria II GX devices provide various loopback options that allow you to verify the working of different functional blocks in the transceiver channel. The available loopback options are: (c) March 2009 Serial loopback--available in all functional modes except PCI Express (PIPE) mode Reverse serial loopback--available in Basic mode only Reverse serial pre-CDR loopback--available in Basic mode only PCI Express (PIPE) reverse parallel loopback--supported in PCI Express (PIPE) protocol only Altera Corporation Arria II GX Device Handbook Volume 2 1-134 Chapter 1: Arria II GX Transceiver Architecture Loopback Modes Serial Loopback The serial loopback option is available for all functional modes except PCI Express (PIPE) mode. Figure 1-109 shows the datapath for serial loopback. The data from the FPGA fabric passes through the transmitter channel and gets looped back to the receiver channel, bypassing the receiver buffer. The received data is available to the FPGA logic for verification. Using this option, you can check the working for all enabled PCS and PMA functional blocks in the transmitter and receiver channels. When you enable the serial loopback option, the ALTGX MegaWizard Plug-In Manager provides the rx_seriallpbken port to dynamically enable serial loopback on a channel-by-channel basis. Set the rx_seriallpbken signal to logic high to enable serial loopback. When serial loopback is enabled, the transmitter channel sends the data to both the tx_dataout output port and the receiver channel. The differential output voltage on the tx_dataout ports is based on the selected VOD settings. The looped back data is received by the receiver CDR and is retimed through different clock domains. You must provide an alignment pattern for the word aligner to enable the receiver channel to retrieve the byte boundary. Figure 1-109. Serial Loopback Datapath Transmitter Channel PCS TX Phase Compensation FIFO Byte Serializer 8B/10B Encoder Transmitter Channel PMA Serializer FPGA Fabric Serial Loopback Receiver Channel PCS RX Phase Compensation FIFO Byte Ordering Byte DeSerializer 8B/10B Decoder Rate Match FIFO Deskew FIFO Receiver Channel PMA Word Aligner DeSerializer Receiver CDR Reverse Serial Loopback Reverse serial loopback is available as a subprotocol under Basic functional mode. In reverse serial loopback mode, the data is received through the rx_datain port, retimed through the receiver CDR, and sent out to the tx_dataout port. The received data is also available to the FPGA logic. Figure 1-110 shows the transceiver channel datapath for reverse serial loopback mode. Note that the active block of the transmitter channel is only the transmitter buffer. You can change the output differential voltage on the transmitter buffer through the ALTGX MegaWizard PlugIn Manager. You cannot alter the pre-emphasis settings for the transmitter buffer. Reverse serial loopback is often implemented when using a bit error rate tester (BERT) on the upstream transmitter. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Loopback Modes 1-135 Figure 1-110. Reverse Serial Loopback Datapath (Grayed-Out Blocks are Not Active in this Mode) Transmitter Channel PMA Transmitter Channel PCS TX Phase Compensation FIFO Byte Serialzier FPGA Fabric 8B/10B Encoder Serializer Receiver Channel PCS RX Phase Compensation FIFO Byte Ordering Byte DeSerializer 8B/10B Decoder Word Aligner Reverse Receiver Channel PMA Serial Loopback DeSerialzier Receiver CDR Reverse Serial Pre-CDR Loopback The reverse serial pre-CDR loopback is available as a subprotocol under Basic functional mode. In reverse serial pre-CDR loopback, the data received through the rx_datain port is looped back to the tx_dataout port BEFORE the receiver CDR. The received data is also available to the FPGA logic. Figure 1-111 shows the transceiver channel datapath for reverse serial pre-CDR loopback mode. Note that the active block of the transmitter channel is only the transmitter buffer. You can change the output differential voltage on the transmitter buffer through the ALTGX MegaWizard Plug-In Manager. You cannot change the pre-emphasis settings for the transmitter buffer. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-136 Chapter 1: Arria II GX Transceiver Architecture Loopback Modes Figure 1-111. Reverse Serial Pre-CDR Loopback Datapath Transmitter Channel PCS Transmitter Channel PMA Serializer FPGA Fabric Receiver channel PCS RX Phase Compensation FIFO Byte Ordering Byte DeSerializer 8B/10B Decoder Word Aligner Receiver Channel PMA DeSerializer Reverse Serial Pre-CDR Loopback Receiver CDR PCI Express (PIPE) Reverse Parallel Loopback PCI Express (PIPE) reverse parallel loopback is only available in PCI Express (PIPE) functional mode for Gen1 data rate. As shown in Figure 1-112, the received serial data passes through the receiver CDR, deserializer, word aligner, and rate matching FIFO buffer. It is then looped back to the transmitter serializer and transmitted out through the tx_dataout port. The received data is also available to the FPGA fabric through the rx_dataout port. This loopback mode is compliant with the PCI Express (PIPE) specification 2.0. To enable this loopback mode, assert the tx_detectrxloopback port. 1 This is the only loopback option supported in PCI Express (PIPE) functional mode. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Calibration Blocks 1-137 In Figure 1-112, the grayed areas show the inactive paths when the PCI Express (PIPE) reverse parallel loop back mode is enabled. Figure 1-112. PCI Express (PIPE) Reverse Parallel Loopback Mode Datapath Transmitter Channel PCS PCI Express hardIP PIPE Interface TX Phase Compensation FIFO Byte Serializer 8B/10B Encoder FPGA Fabric Transmitter Channel PMA Serializer Reverse Parallel Loopback Path Receiver Channel PCS PCI Express hardIP PIPE Interface RX Phase Compensation FIFO Byte DeSerializer 8B/10B Decoder Rate Match FIFO Word Aligner Receiver Channel PMA DeSerializer CDR Calibration Blocks Arria II GX devices contain calibration circuits that calibrate the OCT resistors and the analog portions of the transceiver blocks to ensure that the functionality is independent of process, voltage, or temperature variations. Calibration Block Location Figure 1-113 shows the location and number of calibration blocks available for different transceiver block device families. 1 In Figure 1-113 through Figure 1-115, the calibration block L0 refers to the calibration blocks on the left side. Figure 1-113. Calibration Blocks GXBL0 Arria II GX Device Calibration Block L0 2K (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 1-138 Chapter 1: Arria II GX Transceiver Architecture Calibration Blocks Figure 1-114 shows Arria II GX device families that have three transceiver blocks on the left side. Figure 1-114. Calibration Three-Transceiver Blocks 2K Calibration Block L1 GXBL2 Arria II GX Device GXBL1 GXBL0 Calibration Block L0 2K Figure 1-115 shows Arria II GX device families that have four transceiver blocks on the left side. Figure 1-115. Calibration Four-Transceiver Blocks 2K Calibration Block L1 GXBL3 GXBL2 Arria II GX Device GXBL1 GXBL0 Calibration Block L0 2K The Quartus II software automatically selects the appropriate calibration block based on the assignment of the transceiver tx_dataout and rx_datain pins. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Transceiver Architecture Calibration Blocks 1-139 Calibration The calibration block internally generates a constant internal reference voltage, independent of process, voltage, or temperature variations. It uses the internal reference voltage and external reference resistor (you must connect the resistor to the RREF pin) to generate constant reference currents. These reference currents are used by the analog block calibration circuit to calibrate the transceiver blocks. The OCT calibration circuit calibrates the OCT resistors present in the transceiver channels. You can enable the OCT resistors in the transceiver channels through the ALTGX MegaWizard Plug-In Manager. You must connect a separate 2 k (tolerance max 1%) external resistor on each RREF pin in the Arria II GX device to ground. To ensure proper operation of the calibration block, the RREF resistor connection in the board must be free from any external noise. Input Signals to the Calibration Block Figure 1-116 shows the required inputs to the calibration block. The ALTGX MegaWizard Plug-In Manager provides the cal_blk_clk and cal_blk_powerdown ports to control the calibration block. Figure 1-116. Input Signals to the Calibration Blocks RREF pin cal_blk_clk cal_blk_powerdown (Note 1) Calibration Block Internal Reference Voltage Generator Reference Signal OCT Calibration Control OCT Calibration Circuit Analog Block Calibration Circuit Analog Block Calibration Control Note to Figure 1-116: (1) The RREF pin must be connected through a 2K resistor to ground. The resistor value is preliminary. Final values will be available upon characterization. (c) March 2009 cal_blk_clk--you must use the cal_blk_clk port to provide input clock to the calibration clock. The frequency of cal_blk_clk must be in the range of 10 MHz to 125 MHz (this range is preliminary. Final values will be available upon characterization). You can use dedicated clock routes such as the global or regional clock. If you do not have a suitable input reference clock or dedicated clock routing resources available, use divide-down logic from the FPGA fabric to generate a slow clock and use local clocking routing. Drive the cal_blk_clk port of all ALTGX instances that are associated with the same calibration block from the same input pin or logic. Altera Corporation Arria II GX Device Handbook Volume 2 1-140 Chapter 1: Arria II GX Transceiver Architecture Document Revision History cal_blk_powerdown--you can perform calibration multiple times with the cal_blk_powerdown port available through the ALTGX MegaWizard Plug-In Manager. Assert this signal for approximately 500 ns (this is preliminary, final values will be available upon characterization). Following de-assertion of cal_blk_powerdown, the calibration block restarts the calibration process. Drive the cal_blk_powerdown port of all ALTGX instances that are associated with the same calibration block from the same input pin or logic. Document Revision History Table 1-43 shows the revision history for this chapter. Table 1-43. Document Revision History Date and Document Version March 2009, v1.1 Changes Made Updated: "Dynamic Reconfiguration Controller Architecture" All "AN 558: Implementing dynamic Reconfiguraiton in Arria II GX Devices" references "Transceiver Channel Reconfiguration" Table 1-2 and Table 1-4 Figure 1-69 and Figure 1-70 Summary of Changes -- Added: February 2009, v1.0 "Offset Cancellation in the Receiver Buffer and Receiver CDR" "Basic Double-Width Mode Configurations" Initial release. Arria II GX Device Handbook Volume 2 -- (c) March 2009 Altera Corporation 2. Arria II GX Transceiver Clocking AIIGX52002-1.0 Introduction This chapter provides detailed information about Arria(R) II GX transceiver clocking architecture; namely, input reference clocking, transceiver channel datapath clocking, FPGA fabric-transceiver interface clocking, and FPGA fabric PLLs-transceiver PLLs cascading. This chapter includes the following sections: "CMU PLL and Receiver CDR Input Reference Clocking" on page 2-1 "Transceiver Channel Datapath Clocking" on page 2-6 "FPGA Fabric-Transceiver Interface Clocking" on page 2-27 "FPGA Fabric PLLs-Transceiver PLLs Cascading" on page 2-56 CMU PLL and Receiver CDR Input Reference Clocking Each transceiver block has: Two clock multiplier unit (CMU) phase-locked loops (PLLs) (CMU0 PLL and CMU1 PLL), one in each clock multiplier unit channel (CMU channel) Four clock data recovery (CDR) units, one in each receiver channel The CMU PLLs and receiver CDRs require an input reference clock for their operation. The CMU PLL synthesizes the input reference clock to generate the high-speed serial clock used in the transmitter PMA. The receiver CDR uses the input reference clock as a training clock when it is in lock-to-reference (LTR) mode. The CMU PLLs and receiver CDRs in each transceiver block can derive input reference from one of the following sources: (c) February 2009 refclk0 and refclk1 pins of the same transceiver block refclk0 and refclk1 pins of other transceiver blocks on the same side of the device using the inter-transceiver block (ITB) clock network Dedicated CLK input pins on the FPGA global clock network Clock output pins from the left PLLs in the FPGA fabric Altera Corporation Arria II GX Device Handbook Volume 2 2-2 Chapter 2: Arria II GX Transceiver Clocking CMU PLL and Receiver CDR Input Reference Clocking Figure 2-1 shows the input reference clock sources for CMU PLLs and receiver CDRs within a transceiver block. Figure 2-1. Input Reference Clock Sources in a Transceiver Block refclk0 2 Transceiver Block Channel 3 refclk1 2 ITB Clock Lines Global Clock Line (1) PLL Cascade Clock 6 CDR Channel 2 ITB Clock Lines Global Clock Line (1) PLL Cascade Clock 6 CDR CMU1 Block ITB Clock Lines Global Clock Line (1) PLL Cascade Clock 6 CMU1 PLL CMU0 Block ITB Clock Lines Global Clock Line (1) PLL Cascade Clock 6 CMU0 PLL 6 CDR Channel 1 ITB Clock Lines Global Clock Line (1) PLL Cascade Clock Channel 0 ITB Clock Lines Global Clock Line (1) PLL Cascade Clock 6 CDR Note to Figure 2-1: (1) One global clock line is available for each CMU PLL and receiver CDR in a transceiver block. This configuration allows each CMU PLL and receiver CDR to derive its input reference clock from a separate FPGA CLK input pin. Arria II GX Device Handbook Volume 2 (c) February 2009 Altera Corporation Chapter 2: Arria II GX Transceiver Clocking CMU PLL and Receiver CDR Input Reference Clocking 2-3 Figure 2-2 shows the input reference clock sources for CMU PLLs and receiver CDRs in four transceiver blocks on the left side of the EP2AGX260FF35 device. Figure 2-2. Input Reference Clock Sources across Transceiver Blocks refclk0 /2 Transceiver Block GXBL3 Two CMU PLLs and Four RX CDRs refclk1 6 ITB Clock Lines 6 Global Clock Line PLL Cascade Clock /2 refclk0 /2 Transceiver Block GXBL2 Two CMU PLLs and Four RX CDRs refclk1 6 ITB Clock Lines 6 Global Clock Line PLL Cascade Clock /2 refclk0 /2 Transceiver Block GXBL1 Two CMU PLLs and Four RX CDRs refclk1 6 ITB Clock Lines 6 Global Clock Line PLL Cascade Clock /2 refclk0 /2 Transceiver Block GXBL0 Two CMU PLLs and Four RX CDRs refclk1 6 ITB Clock Lines 6 Global Clock Line PLL Cascade Clock /2 refclk0 and refclk1 Pins Each transceiver block has two dedicated refclk pins that you can use to drive the CMU PLL, receiver CDR, input reference clocks, or all three. Each of the two CMU PLLs and four receiver CDRs within a transceiver block can derive its input reference clock from either the refclk0 or refclk1 pin. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 2 2-4 Chapter 2: Arria II GX Transceiver Clocking CMU PLL and Receiver CDR Input Reference Clocking 1 The refclk pins provide the cleanest input reference clock path to the CMU PLLs. Altera recommends using the refclk pins to drive the CMU PLL input reference clock for improved transmitter output jitter performance. Table 2-17 shows the electrical specifications for the input reference clock signal driven on the refclk pins. Table 2-1. Electrical Specifications for the Input Reference Clock Protocol I/O Standard GIGE 1.2-V PCML XAUI 1.5-V PCML Serial RapidIO 2.5-V PCML SONET/SDH Differential LVPECL SDI LVDS Basic 1.2-V PCML 1.5-V PCML 2.5-V PCML DIfferential LVPECL LVDS PCI Express (PIPE) (1), (2) HCSL Coupling Termination AC On-chip AC On-chip DC Off-chip Notes to Table 2-17: (1) In PCI Express (PIPE) mode, you have the option of selecting the HCSL standard for the reference clock if compliance to the PCI Express (PIPE) protocol is required. The Quartus(R) II software automatically selects DC coupling with external termination for the refclk pins signal if configured as HCSL. (2) Refer to Figure 2-3 for an example termination scheme. Figure 2-3 shows an example termination scheme for a reference clock signal when configured as HCSL. Figure 2-3. Termination Scheme for a Reference Clock Signal When Configured as HCSL (Note 1), (2) PCI Express (HCSL) REFCLK Source Arria II GX Rs (2) REFCLK + Rs (2) REFCLK - Rp = 50 Rp = 50 Notes to Figure 2-3: (1) No biasing is required if the reference clock signals are generated from a clock source that conforms to the PCI Express (PIPE) specification. (2) Select resistor values as recommended by the PCI Express (PIPE) clock source vendor. Arria II GX Device Handbook Volume 2 (c) February 2009 Altera Corporation Chapter 2: Arria II GX Transceiver Clocking CMU PLL and Receiver CDR Input Reference Clocking 2-5 Inter-Transceiver Block (ITB) Clock Lines The ITB clock lines provide an input reference clock path from the refclk pins of one transceiver block to the CMU PLLs and receiver CDRs of other transceiver blocks. In designs that have channels located in different transceiver blocks, the ITB clock lines eliminate the need to connect the on-board reference clock crystal oscillator to the refclk pin of each transceiver block. The ITB clock lines also drive the clock signal on the refclk pins to clock logic in the FPGA fabric. Each refclk pin drives one ITB clock line for a total of up to eight ITB clock lines on the left side of the device, as shown in Figure 2-4. Figure 2-4. Inter-Transceiver Block Clock Lines (Note 1) Transceiver Block GXBL3 refclk0 Two CMU PLLs and Four RX CDRs ITB[7:0] 2 8 6 6 refclk1 Global Clock Line PLL Cascade Clock refclk1 2 Transceiver Block GXBL2 refclk0 2 Two CMU PLLs and Four RX CDRs 6 refclk1 6 Global Clock Line PLL Cascade Clock refclk1 2 To FPGA Fabric Transceiver Block GXBL1 refclk0 2 Two CMU PLLs and Four RX CDRs 6 6 Global Clock Line PLL Cascade Clock refclk1 2 Transceiver Block GXBL0 refclk0 2 Two CMU PLLs and Four RX CDRs 6 6 Global Clock Line PLL Cascade Clock refclk1 2 Note to Figure 2-4: (1) This figure shows the ITB clock lines on the left side of the EP2AGX60FF35 device. The number of ITB clock lines available in any Arria II GX device is equal to the number of refclk pins available in that device. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 2 2-6 Chapter 2: Arria II GX Transceiver Clocking Transceiver Channel Datapath Clocking Dedicated CLK Input Pins on the FPGA Global Clock Network Arria II GX devices provide six differential CLK[5:0] input pins located in non-transceiver I/O banks that you can use to provide the input reference clock to the transceiver blocks. The Quartus II software automatically chooses the global clock (GCLK) network to route the input reference clock signal from the CLK pins to the transceiver blocks. f For more information, refer to the "Dedicated Clock Input Pins" section in the Clock Networks and PLLs in Arria II GX Devices chapter in volume 1 of the Arria II GX Device Handbook. One global clock resource is available for each CMU PLL and receiver CDR within a transceiver block. This configuration allows each CMU PLL and receiver CDR to derive its input reference clock from a separate FPGA CLK input pin. Clock Output from Left PLLs in the FPGA Fabric Use the synthesized clock output from one of the left PLLs in the FPGA fabric to provide the input reference clock to the CMU PLLs and receiver CDRs. These devices provide a dedicated clock path from the left PLLs (PLL_1 and PLL_4) in the FPGA fabric to the PLL cascade network in the transceiver blocks located on the left side of the device. The additional clock multiplication factors available in the left PLLs allow more options for on-board crystal oscillator frequencies. For more information, refer to "FPGA Fabric PLLs-Transceiver PLLs Cascading" on page 2-56. Transceiver Channel Datapath Clocking The following sections describe transmitter and receiver channel datapath clocking in various configurations. Datapath clocking varies with physical coding sublayer (PCS) configurations in different functional modes as well as channel bonding options. Transmitter Channel Datapath Clocking This section describes transmitter channel PMA and PCS datapath clocking in non-bonded and bonded channel configurations. Transmitter datapath clocking in bonded channel configurations is set up to provide low channel-to-channel skew when compared to non-bonded channel configurations. The following factors contribute to transmitter channel-to-channel skew: High-speed serial clock and low-speed parallel clock skew between channels Unequal latency in the transmitter phase compensation FIFO In non-bonded channel configurations, the high-speed serial clock and low-speed parallel clock in each channel are generated independently by its local clock divider, as shown in Figure 2-5 on page 2-8. This results in higher channel-to-channel clock skew. The transmitter phase compensation FIFO in each non-bonded channel has its own pointers and control logic that can result in unequal latency in the transmitter phase compensation FIFO of each channel. The higher transceiver clock skew and unequal latency in the transmitter phase compensation FIFO in each channel can result in higher channel-to-channel skew in non-bonded channel configurations. Arria II GX Device Handbook Volume 2 (c) February 2009 Altera Corporation Chapter 2: Arria II GX Transceiver Clocking Transceiver Channel Datapath Clocking 2-7 In bonded channel configurations, the high-speed serial clock and low-speed parallel clock for all bonded channels are generated by the same CMU0 clock divider block (see Figure 2-6 on page 2-11), resulting in lower channel-to-channel clock skew. The transmitter phase compensation FIFO in all bonded channels share common pointers and control logic generated in the CMU0 channel, resulting in equal latency in the transmitter phase compensation FIFO of all bonded channels. The lower transceiver clock skew and equal latency in the transmitter phase compensation FIFOs in all channels provides lower channel-to-channel skew in bonded channel configurations. Non-Bonded Channel Configurations The following functional modes support non-bonded transmitter channel configuration: (c) February 2009 PCI Express (PIPE) x1 Gigabit Ethernet (GIGE) Serial RapidIO (SRIO) SONET/SDH SDI Basic (except Basic x4 mode) Altera Corporation Arria II GX Device Handbook Volume 2 2-8 Chapter 2: Arria II GX Transceiver Clocking Transceiver Channel Datapath Clocking Figure 2-5 shows the transmitter channel datapath clocking in a non-bonded configuration. Figure 2-5. Transmitter Datapath Clocking in a Non-Bonded Configuration Channel 3 Transmitter Channel PMA Transmitter Channel PCS 8B/10B Encoder Serializer Byte Serializer rdclk High-Speed Serial Clock wrclk TX Phase Compensation FIFO rdclk wrclk PIPE Interface PCI Express Hard IP tx_coreclk[3] /2 Low-Speed Parallel Clock Local Clock Divider Block tx_clkout[3] FPGA Fabric-Transceiver Interface Clock Channel 2 Transmitter Channel PMA Transmitter Channel PCS Byte Serializer 8B/10B Encoder Serializer rdclk High-Speed Serial Clock wrclk TX Phase Compensation FIFO rdclk wrclk PCI Express Hard IP PIPE Interface tx_coreclk[2] /2 Low-Speed Parallel Clock Local Clock Divider Block FPGA Fabric-Transceiver Interface Clock tx_clkout[2] CMU1 Clock Divider CMU1 PLL CMU1 Block Input Reference Clock FPGA Fabric CMU0 Clock Divider CMU0 PLL Input Reference Clock CMU0 Block Channel 1 Transmitter Channel PMA Transmitter Channel PCS Byte Serializer 8B/10B Encoder Serializer rdclk High-Speed Serial Clock wrclk TX Phase Compensation FIFO rdclk PIPE Interface wrclk PCI Express Hard IP tx_coreclk[1] /2 Local Clock Divider Block Low-Speed Parallel Clock tx_clkout[1] FPGA Fabric-Transceiver Interface Clock Channel 0 Transmitter Channel PMA Serializer Transmitter Channel PCS 8B/10B Encoder High-Speed Serial Clock Byte Serializer rdclk wrclk TX Phase Compensation FIFO rdclk PIPE Interface wrclk PCI Express Hard IP tx_coreclk[0] /2 Local Clock Divider Block Low-Speed Parallel Clock tx_clkout[0] FPGA Fabric-Transceiver Interface Clock In non-bonded channel configurations, each channel can derive its clock independently from either CMU0 PLL or CMU1 PLL within the same transceiver block. The CMU PLL synthesizes the input reference clock to generate a clock that runs at a frequency of half the configured data rate. This half rate clock from the CMU PLL is fed to the local clock divider block in each channel. Depending on the configured functional mode, the local clock divider block in each channel generates Arria II GX Device Handbook Volume 2 (c) February 2009 Altera Corporation Chapter 2: Arria II GX Transceiver Clocking Transceiver Channel Datapath Clocking 2-9 the low-speed parallel clock and high-speed serial clock. The serializer in the transmitter channel PMA uses both the low-speed parallel clock and high-speed serial clock for its parallel-in, serial-out operation. The low-speed parallel clock clocks both the 8B/10B encoder (if enabled) and the read port of the byte serializer (if enabled) in the transmitter channel PCS. If the configured functional mode does not use the byte serializer, the low-speed parallel clock provides clock to the read port of the transmitter phase compensation FIFO. The low-speed parallel clock is also driven directly on the tx_clkout port as the FPGA fabric-transceiver interface clock. You can use the tx_clkout port to clock transmitter data and control logic in the FPGA fabric. If the configured functional mode uses a byte serializer to reduce the FPGA fabric-transceiver interface speed, the low-speed parallel clock is divided by two. This divide-by-two version of the low-speed parallel clock provides clock to the write port of the byte serializer and the read port of the transmitter phase compensation FIFO. It is also driven on the tx_clkout port as the FPGA fabric-transceiver interface clock. You can use tx_clkout to regulate transmitter data and control logic in the FPGA fabric. Table 2-2 shows the transmitter channel datapath clock frequencies in non-bonded functional modes that have a fixed data rate. Table 2-2. Transmitter Channel Datapath Clock Frequencies in Non-Bonded Functional Modes Functional Mode Data Rate High-Speed Serial Clock Frequency Low-Speed Parallel Clock Frequency FPGA Fabric-Transceiver Interface Clock Frequency Without Byte Serializer With Byte Serializer 125 MHz PCI Express (PIPE) x1 (Gen 1) 2.5 Gbps 1.25 GHz 250 MHz N/A (1) GIGE 1.25 Gbps 625 MHz 125 MHz 125 MHz N/A 1.25 Gbps 625 MHz 125 MHz N/A 62.5 MHz 2.5 Gbps 1.25 GHz 250 MHz N/A 125 MHz 3.125 Gbps 1.5625 GHz 312.5 MHz N/A 156.25 MHz SONET/SDH OC12 622 Mbps 311 MHz 77.75 MHz 77.75 MHz N/A SONET/SDH OC48 2.488 Gbps 1.244 GHz 311 MHz N/A 155.5 MHz 1.485 Gbps 742.5 MHz 148.5 MHz 148.5 MHz 74.25 MHz 1.4835 Gbps 741.75 MHz 148.35 MHz 148.35 MHz 74.175 MHz 2.97 Gbps 1.485 GHz 297 MHz N/A 148.5 MHz 2.967 Gbps 1.4835 GHz 296.7 MHz N/A 148.35 MHz Serial RapidIO HD-SDI 3G-SDI Note to Table 2-2: (1) 250 MHz when PCI Express hard IP is enabled. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 2 2-10 Chapter 2: Arria II GX Transceiver Clocking Transceiver Channel Datapath Clocking Bonded Channel Configurations Arria II GX devices support bonded channel configurations. Arria II GX devices support x4 PCS and PMA channel bonding that allows bonding of four channels within the same transceiver block. These devices also support x8 channel bonding in PCI Express (PIPE) mode that allows bonding of eight PCS and PMA channels across two transceiver blocks on the same side of the device. Arria II GX devices with at least two transceiver blocks support x8 bonding. x4 Bonded Channel Configuration The following functional modes support x4 bonded transmitter channel configuration: PCI Express (PIPE) x4 XAUI Basic x4 Figure 2-6 shows the transmitter channel datapath clocking in x4 channel bonding configurations. 1 The Quartus II compilation generates an error if you do not assign: tx_dataout[0] of the x4 bonded link (XAUI or PCI Express [PIPE] x4) to physical channel 0 of the transceiver block tx_dataout[1] to physical channel 1 of the transceiver block tx_dataout[2] to physical channel 2 of the transceiver block tx_dataout[3] to physical channel 3 of the transceiver block Arria II GX Device Handbook Volume 2 (c) February 2009 Altera Corporation Chapter 2: Arria II GX Transceiver Clocking Transceiver Channel Datapath Clocking 2-11 Figure 2-6. Transmitter Datapath Clocking in x4 Bonded Configurations Channel 3 Transmitter Channel PCS Transmitter Channel PMA Byte Serializer 8B/10B Encoder Serializer rdclk High-Speed Serial Clock wrclk TX Phase Compensation FIFO rdclk wrclk PIPE Interface PCI Express Hard IP tx_coreclk[3] /2 Low-Speed Parallel Clock Channel 2 Transmitter Channel PCS Transmitter Channel PMA Byte Serializer 8B/10B Encoder Serializer wrclk rdclk High-Speed Serial Clock TX Phase Compensation FIFO rdclk PIPE Interface wrclk PCI Express Hard IP tx_coreclk[2] /2 Low-SPeed Parallel Clock coreclkout /2 CMU1 Block CMU1 PLL Low-Speed Parallel Clock Input Reference Clock FPGA Fabric-Transceiver Interface Clock FPGA Fabric CMU0 Block High-Speed Serial Clock CMU0 Clock Divider CMU0 PLL Input Reference Clock Channel 1 Transmitter Channel PCS Transmitter Channel PMA Byte Serializer 8B/10B Encoder Serializer wrclk rdclk High-Speed Serial Clock TX Phase Compensation FIFO rdclk PIPE Interface wrclk PCI Express Hard IP tx_coreclk[1] /2 Low-Speed Parallel Clock Channel 0 Transmitter Channel PMA Serializer Transmitter Channel PCS 8B/10B Encoder High-Speed Serial Clock Byte Serializer rdclk wrclk /2 TX Phase Compensation FIFO rdclk wrclk PIPE Interface PCI Express Hard IP tx_coreclk[0] Low-Speed Parallel Clock In x4 bonded channel configurations, CMU0 PLL or CMU1 PLL synthesizes the input reference clock to generate a clock that runs at a frequency of half the configured data rate. The half-rate clock from either of the CMU PLLs is fed to the CMU0 clock divider in the CMU0 Channel. Depending on the configured functional mode, the CMU0 clock divider block generates the high-speed serial clock and the low-speed parallel clock. The serializer in the transmitter channel PMA of the four bonded channels uses the same low-speed parallel clock and high-speed serial clock from the CMU0 block for their parallel-in, serial-out operation. The low-speed parallel clock provides clock to the 8B/10B encoder and the read port of the byte serializer (if enabled) in the transmitter channel PCS. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 2 2-12 Chapter 2: Arria II GX Transceiver Clocking Transceiver Channel Datapath Clocking If the configured functional mode does not use the byte serializer, the low-speed parallel clock from the CMU0 clock divider block clocks the read port of the transmitter phase compensation FIFO in all four bonded channels. This low-speed parallel clock is also driven directly on the coreclkout port as the FPGA fabric-transceiver interface clock. You can use the coreclkout signal to clock transmitter data and control logic in the FPGA fabric for all four bonded channels. If the configured functional mode uses the byte serializer, the low-speed parallel clock from the CMU0 clock divider is divided by two. This divide-by-two version of the low-speed parallel clock provides clock to the write port of the byte serializer and the read port of the transmitter phase compensation FIFO in all four bonded channels. It is also driven on the coreclkout port as the FPGA fabric-transceiver interface clock. You can use the coreclkout signal to clock transmitter data and control logic in the FPGA fabric for all four bonded channels. In x4 bonded channel configurations, the transmitter phase compensation FIFOs in all four bonded channels share common read and write pointers and enable signals generated in the CMU0 block channel of the transceiver block. This ensures equal transmitter phase compensation FIFO latency across all four bonded channels, resulting in low transmitter channel-to-channel skew. Table 2-3 shows the transmitter datapath clock frequencies in x4 bonded functional modes that have a fixed data rate. Table 2-3. Transmitter Datapath Clock Frequencies in x4 Bonded Functional Modes Functional Mode PCI Express (PIPE) x4 (Gen 1) XAUI High-Speed Serial Clock Frequency Low-Speed Parallel Clock Frequency 2.5 Gbps 1.25 GHz 3.125 Gbps 1.5625 GHz Data Rate FPGA Fabric-Transceiver Interface Clock Frequency Without Byte Serializer With Byte Serializer 250 MHz N/A (1) 125 MHz 312.5 MHz N/A 156.25 MHz Note to Table 2-3: (1) 250 MHz when PCI Express hard IP is enabled. x8 Bonded Channel Configuration The PCI Express (PIPE) x8 functional mode supports x8 bonded channel configuration in Arria II GX devices with at least two transceiver blocks. The eight bonded channels are located in two transceiver blocks, referred to as the master transceiver block and slave transceiver block, with four channels each. The CMU0 clock divider in the CMU0 block of the master transceiver block provides the serial PMA clock and parallel PCS clock to all eight bonded channels. The serializer in the transmitter channel PMA of the eight bonded channels uses the same low-speed parallel clock and high-speed serial clock from the CMU0 Channel of the master transceiver block for their parallel-in, serial-out operation. The low-speed parallel clock from the CMU0 Channel of the master transceiver block clocks the 8B/10B encoder and read port of the byte serializer (if enabled) in the transmitter channel PCS of all eight channels. Arria II GX Device Handbook Volume 2 (c) February 2009 Altera Corporation Chapter 2: Arria II GX Transceiver Clocking Transceiver Channel Datapath Clocking 2-13 For an 8-bit FPGA fabric-transceiver channel interface that does not use the byte serializer, the low-speed parallel clock from the CMU0 clock divider block in the master transceiver block clocks the read port of the transmitter phase compensation FIFO in all eight bonded channels. This low-speed parallel clock is also driven directly on the coreclkout port as the FPGA fabric-transceiver interface clock. You can use the coreclkout signal to clock the transmitter data and control logic in the FPGA fabric for all eight bonded channels. For a 16-bit FPGA fabric-transceiver channel interface that uses the byte serializer, the low-speed parallel clock from the CMU0 clock divider block in the master transceiver block is divided by two. This divide-by-two version of the low-speed parallel clock provides clock to the write port of the byte serializer and the read port of the transmitter phase compensation FIFO in all eight bonded channels. It is also driven on the coreclkout port as the FPGA fabric-transceiver interface clock. You can use the coreclkout signal to clock the transmitter data and control logic in the FPGA fabric for all eight bonded channels. In the PCI Express (PIPE) x8 bonded channel configuration, the transmitter phase compensation FIFOs in all eight bonded channels share common read and write pointers and enable signals generated in the CMU0 block of the master transceiver block. This ensures equal transmitter phase compensation FIFO latency across all eight bonded channels, resulting in low transmitter channel-to-channel skew. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 2 2-14 Chapter 2: Arria II GX Transceiver Clocking Transceiver Channel Datapath Clocking Figure 2-7 shows transmitter datapath clocking in PCI Express (PIPE) x8 channel bonding configurations. Figure 2-7. Transmitter Datapath Clocking in a x8 Bonded Configuration Slave Transceiver Block Transmitter Channel PCS Transmitter Channel PMA Byte Serializer 8B/10B Encoder Serializer rdclk wrclk TX Phase Compensation FIFO rdclk PIPE Interface wrclk PCI Express Hard IP tx_coreclk[7:4] /2 Low-Speed Parallel Clock from CMU0 of the Master Transceiver Block CMU1 Block CMU1 Clock Divider CMU1 PLL CMU0 Block CMU0 Clock Divider CMU0 PLL FPGA Fabric Master Transceiver Block Transmitter Channel PCS Transmitter Channel PMA Byte Serializer 8B/10B Encoder Serializer rdclk wrclk TX Phase Compensation FIFO rdclk PIPE Interface wrclk PCI Express Hard IP tx_coreclk[3:0] /2 Low Speed Parallel Clock from CMU0 of Master Transceiver Block coreclkout /2 CMU1 Block CMU1 Clock Divider CMU1 PLL Low-Speed Parallel Clock CMU0 Block High-Speed Serial Clock CMU0 Clock Divider CMU0 PLL Input Reference Clock FPGA Fabric-Transceiver Interface Clock Input Reference Clock Figure 2-8 through Figure 2-10 show allowed master and slave transceiver block locations and PCI Express (PIPE) logical lane-to-physical transceiver channel mapping in all Arria II GX devices. 1 The Quartus II compilation generates an error if you do not map the PCI Express (PIPE) logical lanes to the physical transceiver channels, as shown in Figure 2-8 through Figure 2-10. Arria II GX Device Handbook Volume 2 (c) February 2009 Altera Corporation Chapter 2: Arria II GX Transceiver Clocking Transceiver Channel Datapath Clocking 2-15 Figure 2-8 shows the PCI Express (PIPE) x8 link in two transceiver block devices. Figure 2-8. One PCI Express (PIPE) x8 Link in Two Transceiver Block Devices EP2AGX45DF25 EP2AGX65DF25 EP2AGX95DF25 EP2AGX125DF25 EP2AGX45DF29 EP2AGX65DF29 Transceiver Block GXBL1 (Slave) PCI Express Lane 7 Channel3 PCI Express Lane 6 Channel2 PCI Express Lane 5 Channel1 PCI Express Lane 4 Channel0 Transceiver Block GXBL0 (Master) PCI Express Lane 3 Channel3 PCI Express Lane 2 Channel2 PCI Express Lane 1 PCI Express Lane 0 Channel1 Channel0 Figure 2-9 shows the PCI Express (PIPE) x8 link in three transceiver block devices. Figure 2-9. Two PCI Express (PIPE) x8 Link in Three Transceiver Block Devices (Note 1) EP2AGX95EF29 EP2AGX125EF29 EP2AGX190EF29 EP2AGX260EF29 EP2AGX95EF35 EP2AGX125EF35 Transceiver Block GXBL2 Channel3 Channel2 Channel1 Channel0 PCI Express Lane 7 PCI Express Lane 6 PCI Express Lane 5 PCI Express Lane 4 PCI Express Lane 3 PCI Express Lane 2 PCI Express Lane 1 PCI Express Lane 0 Transceiver Block GXBL1 (Slave) Channel3 Channel2 Channel1 Channel0 Transceiver Block GXBL0(Master) Channel3 First PCI Express (PIPE) x8 Link Channel2 Channel1 Channel0 Note to Figure 2-9: (1) Arria II GX devices with three transceiver blocks allow a maximum of one PCI Express (PIPE) x8 link occupying two transceiver blocks. You can configure the other transceiver block to implement other functional modes. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 2 2-16 Chapter 2: Arria II GX Transceiver Clocking Transceiver Channel Datapath Clocking Figure 2-10 shows the PCI Express (PIPE) x8 link in four transceiver block devices. Figure 2-10. Two PCI Express (PIPE) x8 Link in Four Transceiver Block Devices EP2AGX190FF35 EP2AGX260FF35 Transceiver Block GXBL3 (Slave) PCI Express Lane 7 Channel3 PCI Express Lane 6 Channel2 PCI Express Lane 5 Channel1 PCI Express Lane 4 Channel0 Second PCI Express (PIPE) x8 Link (1) Transceiver Block GXBL2 (Master) PCI Express Lane 3 Channel3 PCI Express Lane 2 Channel2 PCI Express Lane 1 Channel1 PCI Express Lane 0 Channel0 Transceiver Block GXBL1 (Slave) PCI Express Lane 7 Channel3 PCI Express Lane 6 Channel2 PCI Express Lane 5 Channel1 PCI Express Lane 4 Channel0 First PCI Express (PIPE) x8 Link Transceiver Block GXBL0 (Master) PCI Express Lane 3 Channel3 PCI Express Lane 2 Channel2 PCI Express Lane 1 Channel1 PCI Express Lane 0 Channel0 Note to Figure 2-10: (1) The second x8 link does not have PCI Express hard IP support. Use soft IP support for the second x8 link. Receiver Channel Datapath Clocking This section describes receiver PMA and PCS datapath clocking in supported configurations. The receiver datapath clocking varies between non-bonded and bonded channel configurations. It also varies with the use of PCS blocks; for example, deskew FIFO and rate matcher. Non-Bonded Channel Configurations In non-bonded channel configurations, receiver PCS blocks of each channel are clocked independently. Each non-bonded channel also has separate rx_analogreset and rx_digitalreset signals that allow independent reset of the receiver PCS logic in each channel. Arria II GX Device Handbook Volume 2 (c) February 2009 Altera Corporation Chapter 2: Arria II GX Transceiver Clocking Transceiver Channel Datapath Clocking f 2-17 For more information about transceiver reset and power down signals, refer to the Reset Control and Power Down chapter in volume 2 of the Arria II GX Device Handbook. In addition, in non-bonded channel configurations, receiver PCS clocking varies, depending on whether the configured functional mode uses the rate matcher block or not. Non-Bonded Receiver Clocking without Rate Matcher The following functional modes have non-bonded receiver channel configuration without rate-matcher: (c) February 2009 Serial RapidIO SONET/SDH SDI Basic without rate matcher Altera Corporation Arria II GX Device Handbook Volume 2 2-18 Chapter 2: Arria II GX Transceiver Clocking Transceiver Channel Datapath Clocking Figure 2-11 shows receiver datapath clocking in non-bonded channel configurations without rate matcher. Figure 2-11. Receiver Datapath Clocking in Non-Bonded Configurations without Rate Matcher Channel 3 Receiver Channel PCS Receiver Channel PMA Input Reference Clock CDR DeSerializer Word Aligner 8B/10B Decoder Byte De-Serializer Byte Ordering RX Phase Compensation FIFO PIPE Interface PCI Express Hard IP Serial Recovered Clock rx_coreclk[3] Ch3 Parallel Recovered Clock /2 rx_clkout[3] FPGA Fabric-Transceiver Interface Clock Channel 2 Receiver Channel PMA Receiver Channel PCS Input Reference Clock CDR DeSerializer Word Aligner 8B/10B Decoder Byte De-Serializer Byte Ordering RX Phase Compensation FIFO PIPE Interface PCI Express Hard IP Serial Recovered Clock rx_coreclk[2] Ch2 Parallel Recovered Clock /2 rx_clkout[2] FPGA Fabric-Transceiver Interface Clock FPGA Fabric Channel 1 Receiver Channel PMA Receiver Channel PCS Input Reference Clock CDR DeSerializer Word Aligner 8B/10B Decoder Byte De-Serializer Byte Ordering RX Phase Compensation FIFO PIPE Interface PCI Express Hard IP Serial Recovered Clock rx_coreclk[1] Ch1 Parallel Recovered Clock /2 rx_clkout[1] FPGA Fabric-Transceiver Interface Clock Channel 0 Receiver Channel PMA Receiver Channel PCS Input Reference Clock CDR DeSerializer Word Aligner 8B/10B Decoder Byte De-Serializer Byte Ordering RX Phase Compensation FIFO PIPE Interface PCI Express Hard IP Serial Recovered Clock rx_coreclk[0] Ch0 Parallel Recovered Clock /2 rx_clkout[0] FPGA Fabric-Transceiver Interface Clock In non-bonded configurations without rate matcher, the CDR in each receiver channel recovers the serial clock from the received data. Also, the serial recovered clock frequency is half the configured data rate due to the half-rate CDR architecture. The serial recovered clock is divided within the receiver PMA to generate the parallel recovered clock. The deserializer uses the serial recovered clock in the receiver PMA. The parallel recovered clock and deserialized data is forwarded to the receiver PCS. The parallel recovered clock in each channel clocks the word aligner and 8B/10B decoder (if enabled). Arria II GX Device Handbook Volume 2 (c) February 2009 Altera Corporation Chapter 2: Arria II GX Transceiver Clocking Transceiver Channel Datapath Clocking 2-19 If the configured functional mode does not use the byte deserializer, the parallel recovered clock also clocks the write side of the receiver phase compensation FIFO. It is also driven on the rx_clkout port as the FPGA fabric-transceiver interface clock. You can use the rx_clkout signal to latch the receiver data and status signals in the FPGA fabric. If the configured functional mode uses the byte deserializer, the parallel recovered clock is divided by two. This divide-by-two version of the parallel recovered clock clocks the read side of the byte deserializer, the byte ordering block (if enabled), and the write side of the receiver phase compensation FIFO. It is also driven on the rx_clkout port as the FPGA fabric-transceiver interface clock. You can use the rx_clkout signal to latch the receiver data and status signals in the FPGA fabric. Table 2-4 shows receiver datapath clock frequencies in non-bonded functional modes without rate matcher. Table 2-4. Receiver Datapath Clock Frequencies in Non-Bonded Functional Modes without Rate Matcher High-Speed Serial Clock Frequency Low-Speed Parallel Clock Frequency 1.25 Gbps 625 MHz 2.5 Gbps 1.25 GHz 3.125 Gbps SONET/SDH OC12 SONET/SDH OC48 Functional Mode Data Rate Without Byte Serializer With Byte Serializer 125 MHz N/A 62.5 MHz 250 MHz N/A 125 MHz 1.5625 GHz 312.5 MHz N/A 156.25 MHz 622 Mbps 311 MHz 77.75 MHz 77.75 MHz N/A 2.488 Gbps 1.244 GHz 311 MHz N/A 155.5 MHz 1.485 Gbps 742.5 MHz 148.5 MHz 148.5 MHz 74.25 MHz 1.4835 Gbps 741.75 MHz 148.35 MHz 148.35 MHz 74.175 MHz 2.97 Gbps 1.485 GHz 297 MHz N/A 148.5 MHz 2.967 Gbps 1.4835 Ghz 296.7 MHz N/A 148.35 MHz Serial RapidIO HD SDI 3G-SDI FPGA Fabric-Transceiver Interface Clock Frequency Non-Bonded Receiver Clocking with Rate Matcher The following functional modes have non-bonded receiver channel configurations with rate-matcher: (c) February 2009 PCI Express (PIPE) x1 GIGE Serial RapidIO Basic with rate matcher Altera Corporation Arria II GX Device Handbook Volume 2 2-20 Chapter 2: Arria II GX Transceiver Clocking Transceiver Channel Datapath Clocking Figure 2-12 shows receiver datapath clocking in non-bonded channel configurations with rate matcher. Figure 2-12. Receiver Datapath Clocking in Non-Bonded Configurations with Rate Matcher Channel 3 Receiver Channel PMA Receiver Channel PCS Input Reference Clock DeSerializer CDR Word Aligner Rate Match FIFO 8B/10B Decoder Byte DeSerializer Byte Ordering RX Phase Compensation FIFO PIPE Interface PCI Express Hard IP Serial Recovered Clock rx_coreclk[3] From CMU0 PLL From CMU1 PLL Ch3 Parallel Recovered Clock Local Clock Divider /2 Low-Speed Parallel Clock tx_clkout[3] Transmitter Channel PMA FPGA Fabric_Transceiver Interface Clock Channel 2 Receiver Channel PMA Receiver Channel PCS Input Reference Clock DeSerializer CDR Word Aligner Rate Match FIFO 8B/10B Decoder Byte DeSerializer Byte Ordering RX Phase Compensation FIFO PIPE Interface PCI Express Hard IP Serial Recovered Clock rx_coreclk[2] From CMU0 PLL Local Clock Divider From CMU1 PLL Ch2 Parallel Recovered Clock /2 Low-Speed Parallel Clock tx_clkout[2] Transmitter Channel PMA FPGA Fabric_Transceiver Interface Clock FPGA Fabric Channel 1 Receiver Channel PMA Receiver Channel PCS Input Reference Clock CDR DeSerializer Word Aligner Rate Match FIFO 8B/10B Decoder Byte DeSerializer Byte Ordering RX Phase Compensation FIFO PIPE Interface PCI Express Hard IP Serial Recovered Clock rx_coreclk[1] From CMU0 PLL From CMU1 PLL Ch1 Parallel Recovered Clock Local Clock Divider /2 Low-Speed Parallel Clock tx_clkout[1] Transmitter Channel PMA FPGA Fabric_Transceiver Interface Clock Channel 0 Receiver Channel PMA Receiver Channel PCS Input Reference Clock CDR DeSerializer Word Aligner Rate Match FIFO 8B/10B Decoder Byte DeSerializer Byte Ordering RX Phase Compensation FIFO PIPE Interface PCI Express Hard IP Serial Recovered Clock rx_coreclk[0] From CMU0 PLL From CMU1 PLL Local Clock Divider Transmitter Channel PMA Ch0 Parallel Recovered Clock Low-Speed Parallel Clock /2 tx_clkout[0] FPGA Fabric_Transceiver Interface Clock In non-bonded configurations with rate matcher, the CDR in each receiver channel recovers the serial clock from the received data. Also, the serial recovered clock frequency is half the configured data rate due to the half rate CDR architecture. The serial recovered clock is divided within the receiver PMA to generate the parallel recovered clock. The deserializer uses the serial recovered clock in the receiver PMA. The parallel recovered clock and deserialized data is forwarded to the receiver PCS. Arria II GX Device Handbook Volume 2 (c) February 2009 Altera Corporation Chapter 2: Arria II GX Transceiver Clocking Transceiver Channel Datapath Clocking 2-21 The parallel recovered clock from the receiver PMA in each channel clocks the word aligner and the write port of the rate match FIFO. The low-speed parallel clock from the transmitter local clock divider block in each channel clocks the read port of the rate match FIFO, 8B/10B decoder, and the write port of the byte deserializer (if enabled). The parallel transmitter PCS clock or its divide-by-two version (if byte deserializer is enabled) clocks the write port of the receiver phase compensation FIFO. It is also driven on the tx_clkout port as the FPGA fabric-transceiver interface clock. You can use the tx_clkout signal to latch the receiver data and status signals in the FPGA fabric. Table 2-5 shows the receiver datapath clock frequencies in non-bonded functional modes with rate matcher. Table 2-5. Receiver Datapath Clock Frequencies in Non-Bonded Functional Modes with Rate Matcher Functional Mode Serial Recovered Clock Frequency Parallel Recovered Clock Frequency 2.5 Gbps 1.25 GHz 1.25 1.25 Gbps Data Rate PCI Express (PIPE) x1 (Gen 1) GIGE Serial RapidIO FPGA Fabric-Transceiver Interface Clock Frequency Without Byte Serializer With Byte Serializer 250 MHz N/A (1) 125 MHz 625 MHz 125 MHz 125 MHz N/A 625 MHz 125 MHz N/A 62.5 MHz 2.5 Gbps 1.25 GHz 250 MHz N/A 125 MHz 3.125 Gbps 1.5625 GHz 312.5 MHz N/A 156.25 MHz Note to Table 2-5: (1) 250 MHz when PCI Express hard IP is enabled. Bonded Channel Configurations The Arria II GX device supports x4 channel bonding that allows bonding of four channels within the same transceiver block. It also supports x8 channel bonding that allows bonding of eight channels across two transceiver blocks in PCI Express (PIPE) mode. x4 Bonded Channel Configuration The following functional modes support x4 receiver channel bonded configuration: PCI Express (PIPE) x4 XAUI In x4 bonded channel configurations, the receiver datapath clocking varies, depending on whether the configured functional mode uses the deskew FIFO or not. x4 Bonded Channel Configuration with Deskew FIFO XAUI functional mode has x4 bonded channel configuration with deskew FIFO. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 2 2-22 Chapter 2: Arria II GX Transceiver Clocking Transceiver Channel Datapath Clocking Figure 2-13 shows receiver datapath clocking in x4 channel bonding configurations with deskew FIFO. Figure 2-13. Receiver Datapath Clocking in x4 Bonded Channel Configuration with Deskew FIFO Channel 3 Receiver Channel PMA Receiver Channel PCS Input Reference Clock CDR DeSerializer Word Aligner Rate Match FIFO Deskew FIFO 8B/10B Decoder Byte DeSerializer Byte Ordering RX Phase Compensation FIFO PCI Express Hard IP PIPE Interface Serial Recovered Clock rx_coreclk[3] Ch3 Parallel Recovered Clock Ch0 Parallel Recovered Clock /2 Low-Speed Parallel Clock from CMU0 Clock Divider Channel 2 Receiver Channel PMA Receiver Channel PCS Input Reference Clock CDR DeSerializer Word Aligner Deskew FIFO Rate Match FIFO 8B/10B Decoder Byte DeSerializer Byte Ordering RX Phase Compensation FIFO PCI Express Hard IP PIPE Interface Serial Recovered Clock rx_coreclk[2] Ch2 Parallel Recovered Clock Ch0 Parallel Recovered Clock /2 Low-Speed Parallel Clock from CMU0 Clock Divider coreclkout CMU1 Block /2 CMU1 Clock Divider CMU1 PLL Input Reference Clock FPGA Fabric-Transceiver Interface Clock FPGA Fabric CMU0 Block Low-Speed Parallel Clock CMU0 Clock Divider CMU0 PLL Input Reference Clock Channel 1 Receiver Channel PMA Input Reference Clock CDR DeSerializer Receiver Channel PCS Word Aligner Deskew FIFO Rate Match FIFO 8B/10B Decoder Byte DeSerializer Byte Ordering RX Phase Compensation FIFO PIPE Interface PCI Express Hard IP Serial Recovered Clock rx_coreclk[1] Ch1 Parallel Recovered Clock Ch0 Parallel Recovered Clock /2 Low-Speed Parallel Clock from CMU0 Clock Divider Channel 0 Receiver Channel PMA Receiver Channel PCS Input Reference Clock CDR DeSerializer Word Aligner Deskew FIFO Rate Match FIFO 8B/10B Decoder Byte DeSerializer Byte Ordering RX Phase Compensation FIFO PIPE Interface PCI Express Hard IP Serial Recovered Clock rx_coreclk[0] Ch0 Parallel Recovered Clock /2 Low-Speed Parallel Clock from CMU0 Clock Divider Arria II GX Device Handbook Volume 2 (c) February 2009 Altera Corporation Chapter 2: Arria II GX Transceiver Clocking Transceiver Channel Datapath Clocking 2-23 In x4 bonded channel configurations with deskew FIFO, the CDR in each receiver channel recovers the serial clock from the received data. Also, the serial recovered clock frequency is half the configured data rate due to the half-rate CDR architecture. The serial recovered clock is divided within each channel's receiver PMA to generate the parallel recovered clock. The deserializer uses the serial recovered clock in the receiver PMA. The parallel recovered clock and deserialized data is forwarded to the receiver PCS in each channel. The parallel recovered clock from the receiver PMA in each channel clocks the word aligner in that channel. The parallel recovered clock from Channel 0 clocks the deskew FIFO and the write port of the rate match FIFO in all four bonded channels. The low-speed parallel clock from the CMU0 clock divider block clocks the read port of the rate match FIFO, 8B/10B decoder, and the write port of the byte deserializer (if enabled) in all four bonded channels. The low-speed parallel clock or its divide-by-two version (if byte deserializer is enabled) clocks the write port of the receiver phase compensation FIFO. It is also driven on the coreclkout port as the FPGA fabric-transceiver interface clock. You can use the coreclkout signal to latch the receiver data and status signals in the FPGA fabric for all four bonded channels. In x4 bonded channel configurations, the receiver phase compensation FIFOs in all four bonded channels share common read and write pointers and enable signals generated in the CMU0 block of the transceiver block. Table 2-6 shows receiver datapath clock frequencies in x4 bonded functional modes with deskew FIFO. Table 2-6. Receiver Datapath Clock Frequencies in x4 Bonded Functional Modes with Deskew FIFO Functional Mode Serial Recovered Clock Frequency Parallel Recovered Clock and Parallel Transmitter PCS Clock Frequency 2.5 Gbps 1.25 GHz 3.125 Gbps 1.5625 GHz Data Rate PCI Express (PIPE) x4 (Gen 1) XAUI FPGA Fabric-Transceiver Interface Clock Frequency Without Byte Serializer With Byte Serializer 250 MHz N/A (1) 125 MHz 312.5 MHz N/A 156.25 MHz Note to Table 2-6: (1) 250 MHz when PCI Express hard IP is enabled. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 2 2-24 Chapter 2: Arria II GX Transceiver Clocking Transceiver Channel Datapath Clocking x4 Bonded Channel Configurations without Deskew FIFO PCI Express (PIPE) x4 functional modes have x4 bonded channel configurations without deskew FIFO. Figure 2-14 shows receiver datapath clocking in x4 channel bonding configurations without deskew FIFO. Figure 2-14. Receiver Datapath Clocking in x4 Bonded Channel Configurations without Deskew FIFO Channel 3 Receiver Channel PMA Receiver Channel PCS Input Reference Clock CDR DeSerializer Rate Match FIFO Word Aligner 8B/10B Decoder Byte DeSerializer Byte Ordering RX Phase Compensation FIFO PCI Express Hard IP PIPE Interface Serial Recovered Clock rx_coreclk[3] Ch3 Parallel Recovered Clock /2 Low-Speed Parallel Clock from CMU0 Clock Divider Channel 2 Receiver Channel PMA Receiver Channel PCS Input Reference Clock CDR DeSerializer Rate Match FIFO Word Aligner 8B/10B Decoder Byte DeSerializer Byte Ordering RX Phase Compensation FIFO PCI Express Hard IP PIPE Interface Serial Recovered Clock rx_coreclk[2] Ch2 Parallel Recovered Clock /2 Low-Speed Parallel Clock from CMU0 Clock Divider coreclkout /2 CMU1 Block CMU1 Clock Divider CMU1 PLL Input Reference Clock FPGA Fabric_Transceiver Interface Clock FPGA Fabric CMU0 Block CMU0 Clock Divider Low-Speed Parallel Clock CMU0 PLL Input Reference Clock Channel 1 Receiver Channel PMA Receiver Channel PCS Input Reference Clock CDR DeSerializer Rate Match FIFO Word Aligner 8B/10B Decoder Byte DeSerializer Byte Ordering RX Phase Compensation FIFO PIPE Interface PCI Express Hard IP Serial Recovered Clock rx_coreclk[1] Ch1 Parallel Recovered Clock /2 Low-Speed Parallel Clock from CMU0 Clock Divider Channel 0 Receiver Channel PMA Receiver Channel PCS Input Reference Clock CDR DeSerializer Word Aligner Rate Match FIFO 8B/10B Decoder Byte DeSerializer Byte Ordering RX Phase Compensation FIFO PIPE Interface PCI Express Hard IP Serial Recovered Clock rx_coreclk[0] Ch0 Parallel Recovered Clock /2 Low-Speed Parallel Clock from CMU0 Clock Divider Arria II GX Device Handbook Volume 2 (c) February 2009 Altera Corporation Chapter 2: Arria II GX Transceiver Clocking Transceiver Channel Datapath Clocking 2-25 In x4 bonded channel configurations without deskew FIFO, the CDR in each receiver channel recovers the serial clock from the received data. The serial recovered clock frequency is half the configured data rate due to the half-rate CDR architecture. The serial recovered clock is divided within each channel's receiver PMA to generate the parallel recovered clock. The deserializer uses the serial recovered clock in the receiver PMA. The parallel recovered clock and deserialized data is forwarded to the receiver PCS in each channel. The parallel recovered clock from the receiver PMA in each channel clocks the word aligner and write side of the rate match FIFO in that channel. The low-speed parallel clock from the CMU0 clock divider block in CMU0 Channel clocks the read port of the rate match FIFO, 8B/10B decoder, and the write port of the byte deserializer (if enabled). The low-speed parallel clock or its divide-by-two version (if byte deserializer is enabled) clocks the receiver phase compensation FIFO. It is also driven on the coreclkout port as the FPGA fabric-transceiver interface clock. You can use the coreclkout signal to latch the receiver data and status signals in the FPGA fabric for all four bonded channels. In x4 bonded channel configurations, the receiver phase compensation FIFOs in all four bonded channels share common read and write pointers and enable signals generated in the CMU0 channel of the transceiver block. Table 2-7 shows receiver datapath clock frequencies in x4 bonded functional modes without deskew FIFO. Table 2-7. Receiver Datapath Clock Frequencies in x4 Bonded Functional Modes without Deskew FIFO Functional Mode Data Rate PCI Express (PIPE) x4 (Gen 1) 2.5 Gbps Serial Recovered Clock Frequency Parallel Recovered Clock and Parallel Transmitter PCS Clock Frequency 1.25 GHz 250 MHz FPGA Fabric-Transceiver Interface Clock Frequency Without Byte Serializer With Byte Serializer N/A (1) 125 MHz Note to Table 2-7: (1) 250 MHz when PCI Express hard IP is enabled. x8 Bonded Channel Configuration PCI Express (PIPE) x8 functional mode supports x8 receiver channel bonding configuration. The eight bonded channels are located in two transceiver blocks, referred to as the master transceiver block and slave transceiver block, with four channels each. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 2 2-26 Chapter 2: Arria II GX Transceiver Clocking Transceiver Channel Datapath Clocking Figure 2-15 shows receiver datapath clocking in PCI Express (PIPE) x8 bonded channel configuration. Figure 2-15. Receiver Datapath Clocking in x8 Bonded Channel Configuration Slave Transceiver Block Receiver Channel PMA Receiver Channel PCS Input Reference Clock CDR DeSerializer Word Aligner Rate Match FIFO 8B/10B Decoder Byte DeSerializer Byte Ordering RX Phase Compensation FIFO PIPE Interface PCI Express Hard IP Serial Recovered Clock rx_coreclk[7:4] Parallel Recovered Clock /2 Low-Speed Parallel Clock from CMU0 Clock Divider CMU1 Block CMU1 Clock Divider CMU1 PLL CMU0 Block CMU0 Clock Divider CMU0 PLL FPGA Fabric Master Transceiver Block Receiver Channel PMA Receiver Channel PCS Input Reference Clock CDR DeSerializer Word Aligner Rate Match FIFO 8B/10B Decoder Byte DeSerializer Byte Ordering RX Phase Compensation FIFO PIPE Interface PCI Express Hard IP Serial Recovered Clock rx_coreclk[3:0] Parallel Recovered Clock /2 Low-Speed Parallel Clock from CMU0 Clock Divider coreclkout /2 CMU1 Block CMU1 Clock Divider CMU1 PLL Input Reference Clock FPGA Fabric_Transceiver Interface Clock CMU0 Block CMU0 Clock Divider CMU0 PLL Input Reference Clock The CDR in each of the eight receiver channels recovers the serial clock from the received data on that channel. The serial recovered clock frequency is half the configured data rate. The serial recovered clock is divided within each channel's receiver PMA to generate the parallel recovered clock. The deserializer uses the serial recovered clock in the receiver PMA. The parallel recovered clock and deserialized data from the receiver PMA in each channel is forwarded to the receiver PCS in that channel. Arria II GX Device Handbook Volume 2 (c) February 2009 Altera Corporation Chapter 2: Arria II GX Transceiver Clocking FPGA Fabric-Transceiver Interface Clocking 2-27 The parallel recovered clock from the receiver PMA in each channel clocks the word aligner and write side of the rate match FIFO in that channel. The low-speed parallel clock from the CMU0 clock divider of the master transceiver block clocks the read port of the rate match FIFO, 8B/10B decoder, and the write port of the byte deserializer (if enabled) in all eight channels. The low-speed parallel clock or its divide-by-two version (if byte-deserializer is enabled) clocks the write port of the receiver phase compensation FIFO in all eight channels. It is also driven on the coreclkout port as the FPGA fabric-transceiver interface clock. You can use the coreclkout signal to latch the receiver data and status signals in the FPGA fabric for all eight bonded channels. Both the receiver phase compensation FIFO pointers and the control circuitry from Channel 0 in the master transceiver block are shared by the receiver phase compensation FIFOs across all eight channels in PCI Express (PIPE) x8 mode. Table 2-8 shows the receiver datapath clock frequencies in PCI Express (PIPE) x8 functional mode. Table 2-8. Receiver Datapath Clock Frequencies in PCI Express (PIPE) x8 Functional Modes Functional Mode Data Rate PCI Express (PIPE) x8 (Gen 1) 2.5 Gbps Serial Recovered Clock Frequency Parallel Recovered clock and Parallel Transmitter PCS Clock Frequency 1.25 GHz 250 MHz FPGA Fabric-Transceiver Interface Clock Frequency Without Byte Serializer With Byte Serializer N/A (1) 125 MHz Note to Table 2-8: (1) 250 MHz when PCI Express hard IP is enabled. FPGA Fabric-Transceiver Interface Clocking The FPGA fabric-transceiver interface clocks consist of clock signals from the FPGA fabric to the transceiver blocks and clock signals from the transceiver blocks to the FPGA fabric. The FPGA fabric-transceiver interface clocks are subdivided into the following three categories: "Input Reference Clocks" on page 2-27 "Phase Compensation FIFO Clocks" on page 2-28 "Other Transceiver Clocks" on page 2-28 Input Reference Clocks The CMU PLLs and receiver CDRs in each transceiver block derive the input reference from one of the following sources: (c) February 2009 refclk0 and refclk1 pins of the same transceiver block refclk0 and refclk1 pins of other transceiver blocks on the same side of the device using the inter-transceiver block (ITB) clock network Altera Corporation Arria II GX Device Handbook Volume 2 2-28 Chapter 2: Arria II GX Transceiver Clocking FPGA Fabric-Transceiver Interface Clocking CLK input pins on the FPGA global clock (GCLK) network Clock output pins from the left PLLs in the FPGA fabric The input reference clock follows these guidelines: If the input reference clock to the CMU PLL or receiver CDR is provided through the FPGA CLK input pins or the clock output from the left PLLs in the FPGA fabric, the input reference clock becomes a part of the FPGA fabric-transceiver interface clocks. If the input reference clock is provided through the FPGA CLK input pins, the Quartus II software automatically routes the input reference clock on the FPGA fabric global clock (GCLK) network. If the input reference clock is provided through the output clock from a left PLL, the Quartus II software routes the input reference clock on a dedicated clock path from the left PLL to the CMU PLL or receiver CDR. Phase Compensation FIFO Clocks The transmitter and receiver phase compensation FIFOs in each channel ensure reliable transfer of data, control, and status signals between the FPGA fabric and the transceiver channels. The transceiver channel forwards the tx_clkout signal (in non-bonded modes) or the coreclkout signal (in bonded channel modes) to the FPGA fabric to clock the data and control signals into the transmitter phase compensation FIFO. The transceiver channel also forwards the recovered clock rx_clkout (in configurations without rate matcher) or tx_clkout/coreclkout (in configurations with rate matcher) to the FPGA fabric to clock the data and status signals from the receiver phase compensation FIFO into the FPGA fabric. The phase compensation FIFO clocks form a part of the FPGA fabric-transceiver interface clocks and are routed on either a global clock resource (GCLK), regional clock resource (RCLK), or periphery clock (PCLK) resource in the FPGA fabric. Other Transceiver Clocks The following transceiver clocks form a part of the FPGA fabric-transceiver interface clocks: cal_blk_clk--calibration block clock fixed_clk--125 MHz fixed-rate clock used in PCI Express (PIPE) receiver detect circuitry The Quartus II software automatically routes fixed_clk on the FPGA fabric global clock (GCLK) or regional clock (RCLK) network. Arria II GX Device Handbook Volume 2 (c) February 2009 Altera Corporation Chapter 2: Arria II GX Transceiver Clocking FPGA Fabric-Transceiver Interface Clocking 2-29 Table 2-9 summarizes FPGA fabric-transceiver interface clocks. Table 2-9. FPGA Fabric-Transceiver Interface Clocks Clock Name Clock Description FPGA Fabric Clock Resource Utilization (1) Interface Direction pll_inclk CMU PLL input reference clock when driven from an FPGA CLK input pin FPGA fabric-to-transceiver GCLK rx_cruclk Receiver CDR input reference clock when driven from an FPGA CLK input pin FPGA fabric-to-transceiver GCLK tx_clkout Phase compensation FIFO clock Transceiver-to-FPGA fabric GCLK, RCLK, PCLK coreclkout Phase compensation FIFO clock Transceiver-to-FPGA fabric GCLK, RCLK, PCLK rx_clkout Phase compensation FIFO clock Transceiver-to-FPGA fabric GCLK, RCLK, PCLK fixed_clk PCI Express receiver detect clock FPGA fabric-to-transceiver GCLK, RCLK Note to Table 2-9: (1) For more information about GCLK, RCLK, and PCLK resources available in each device, refer to the Clock Networks and PLLs in Arria II GX Devices chapter in volume 1 of the Arria II GX Device Handbook. "FPGA Fabric-Transmitter Interface Clocking" (below) and "FPGA Fabric-Receiver Interface Clocking" on page 2-42 describe the criteria and methodology to share transmitter and receiver phase compensation FIFO clocks in order to reduce the GCLK, RCLK, and PCLK resource utilization in your design. FPGA Fabric-Transmitter Interface Clocking The transmitter phase compensation FIFO compensates for the phase difference between the FPGA fabric clock (phase compensation FIFO write clock) and the parallel transmitter PCS clock (phase compensation FIFO read clock). The transmitter phase compensation FIFO write clock forms the FPGA fabric-transmitter interface clock. The phase compensation FIFO write and read clocks must have exactly the same frequency, in other words, 0 PPM frequency difference. Arria II GX transceivers provide the following two options for selecting the transmitter phase compensation FIFO write clock: Quartus II software-selected transmitter phase compensation FIFO write clock User-selected transmitter phase compensation FIFO write clock Quartus II Software-Selected Transmitter Phase Compensation FIFO Write Clock If you do not select the tx_coreclk port in the ALTGX MegaWizard TM Plug-In Manager, the Quartus II software automatically selects the transmitter phase compensation FIFO write clock for each channel in that ALTGX instance. The Quartus II software selects the FIFO write clock depending on the channel configuration. Non-Bonded Channel Configuration In the non-bonded channel configuration, the transmitter channels may or may not be identical. Identical transmitter channels are defined as channels that have exactly the same CMU PLL input reference clock source, have exactly the same CMU PLL configuration, and have exactly the same transmitter PMA and PCS configuration. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 2 2-30 Chapter 2: Arria II GX Transceiver Clocking FPGA Fabric-Transceiver Interface Clocking 1 Identical transmitter channels may have different transmitter voltage output differential (VOD) or pre-emphasis settings. Example 1: Four Identical Channels in a Transceiver Block If all four channels within a transceiver block are identical, the Quartus II software automatically drives the write port of the transmitter phase compensation FIFO in all four channels with tx_clkout[0], as shown in Figure 2-16. Use the tx_clkout[0] signal to clock the transmitter data and control logic for all four channels in the FPGA fabric. 1 This configuration uses only one FPGA GCLK, RCLK, or PCLK resource for tx_clkout[0]. Arria II GX Device Handbook Volume 2 (c) February 2009 Altera Corporation Chapter 2: Arria II GX Transceiver Clocking FPGA Fabric-Transceiver Interface Clocking 2-31 Figure 2-16. Four Identical Channels in a Transceiver Block for Example 1 Channel 3 Transmitter Channel PMA Transmitter Channel PCS TX Phase Compensation FIFO rdclk Local Clock Divider Block Channel 3 TX Data and Control Logic wrclk tx_coreclk[3] /2 Low-Speed Parallel Clock Channel 2 Transmitter Channel PMA Transmitter Channel PCS TX Phase Compensation FIFO rdclk Local Clock Divider Block Low-Speed Parallel Clock Channel 2 TX Data and Control Logic wrclk tx_coreclk[2] /2 High-Speed Serial Clock CMU1 Block CMU0 Block CMU1 Clock Divider CMU1 PLL CMU0 Clock Divider CMU0 PLL Input Reference Clock FGPA Fabric Channel 1 Transmitter Channel PMA Transmitter Channel PCS TX Phase Compensation FIFO rdclk Local Clock Divider Block Channel 1 TX Data and Control Logic wrclk tx_coreclk[1] /2 Low-Speed Parallel Clock Channel 0 Transmitter Channel PMA Transmitter Channel PCS TX Phase Compensation FIFO rdclk Local Clock Divider Block Channel 0 TX Data and Control Logic wrclk tx_coreclk[0] /2 Low-Speed Parallel Clock tx_clkout[0] Example 2: Two Groups of Two Identical Channels in a Transceiver Block Example 2 assumes channels 0 and 1, driven by CMU0 PLL in a transceiver block, are identical. Also, channels 2 and 3, driven by CMU1 PLL in the same transceiver block, are identical. In this case, the Quartus II software automatically drives the write port of the transmitter phase compensation FIFO in channels 0 and 1 with the tx_clkout[0] signal. It also drives the write port of the transmitter phase compensation FIFO in channels 2 and 3 with the tx_clkout[2] signal. Use the tx_clkout[0] signal to clock the transmitter data and control logic for channels 0 and 1 in the FPGA fabric. Use the tx_clkout[2] signal to clock the transmitter data and control logic for channels 2 and 3 in the FPGA fabric. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 2 2-32 Chapter 2: Arria II GX Transceiver Clocking FPGA Fabric-Transceiver Interface Clocking 1 This configuration uses two FPGA clock resources (global, regional, or both), one for the tx_clkout[0] signal and one for the tx_clkout[2] signal. Figure 2-17 shows FPGA fabric-transmitter interface clocking for Example 2. Figure 2-17. FPGA Fabric-Transmitter Interface Clocking for Example 2 Channel 3 Transmitter Channel PMA Transmitter Channel PCS TX Phase Compensation FIFO rdclk Local Clock Divider Block Channel 3 TX Data and Control Logic wrclk tx_coreclk[3] /2 Low-Speed Parallel Clock Channel 2 Transmitter Channel PMA Transmitter Channel PCS TX Phase Compensation FIFO rdclk Local Clock Divider Block Channel 2 TX Data and Control Logic wrclk tx_coreclk[2] /2 Low-Speed Parallel Clock tx_clkout[2] CMU1 Block CMU0 Block CMU1 Clock DIvider CMU1 PLL CMU0 Clock DIvider CMU0 PLL Input Reference Clock FPGA Fabric Input Reference Clock Channel 1 Transmitter Channel PMA Transmitter Channel PCS TX Phase Compensation FIFO rdclk Local Clock Divider Block Channel 1 TX Data and Control Logic wrclk tx_coreclk[1] /2 Low-Speed Parallel Clock Channel 0 Transmitter Channel PMA Transmitter Channel PCS TX Phase Compensation FIFO rdclk Local Clock Divider Block Channel 0 TX Data and Control Logic wrclk tx_coreclk[0] /2 Low-Speed Parallel Clock tx_clkout[0] Arria II GX Device Handbook Volume 2 (c) February 2009 Altera Corporation Chapter 2: Arria II GX Transceiver Clocking FPGA Fabric-Transceiver Interface Clocking 2-33 Bonded Channel Configuration In the x4 bonded channel configuration, all four channels within the transceiver block are identical. The Quartus II software automatically drives the write port of the transmitter phase compensation FIFO in all four channels with the coreclkout signal. Use the coreclkout signal to clock the transmitter data and control logic for all four channels in the FPGA fabric. In the x8 bonded channel configuration, all eight channels across two transceiver blocks are identical. The Quartus II software automatically drives the write port of the transmitter phase compensation FIFO in all eight channels with the coreclkout signal from the master transceiver block. Use the coreclkout signal to clock the transmitter data and control logic for all eight channels in the FPGA fabric. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 2 2-34 Chapter 2: Arria II GX Transceiver Clocking FPGA Fabric-Transceiver Interface Clocking Figure 2-18 shows FPGA fabric-transmitter interface clocking in an x4 bonded channel configuration. Figure 2-18. FPGA Fabric-Transmitter Interface Clocking in an x4 Bonded Channel Configuration Channel 3 Transmitter Channel PCS TX Phase Compensation FIFO rdclk Channel 3 TX Data and Control Logic wrclk tx_coreclk[3] /2 Parallel PCS Clock Channel 2 Transmitter Channel PCS TX Phase Compensation FIFO rdclk Channel 2 TX Data and Control Logic wrclk tx_coreclk[2] /2 Parallel PCS Clock CMU1 Block CMU1 PLL coreclkout FPGA Fabric /2 CMU0 Block CMU0 Clock Divider CMU0 PLL Input Reference Clock Channel 1 Transmitter Channel PCS TX Phase Compensation FIFO rdclk Channel 1 TX Data and Control Logic wrclk tx_coreclk[1] /2 Parallel PCS Clock Channel 0 Transmitter Channel PCS TX Phase Compensation FIFO rdclk /2 Channel 0 TX Data and Control Logic wrclk tx_coreclk[0] Parallel PCS Clock Arria II GX Device Handbook Volume 2 (c) February 2009 Altera Corporation Chapter 2: Arria II GX Transceiver Clocking FPGA Fabric-Transceiver Interface Clocking 2-35 Limitations of the Quartus II Software-Selected Transmitter Phase Compensation FIFO Write Clock The Quartus II software uses a single tx_clkout signal to clock the transmitter phase compensation FIFO write port of all identical channels within a transceiver block. This results in one global or regional clock resource being used for each group of identical channels within a transceiver block. For identical channels located across transceiver blocks, the Quartus II software does not use a single tx_clkout signal to clock the write port of the transmitter phase compensation FIFOs for all channels. Instead, it uses one tx_clkout signal for each group of identical channels per transceiver block. This results in higher clock resource utilization. Example 3: Sixteen Identical Channels Across Four Transceiver Blocks Consider 16 identical transmitter channels located across four transceiver blocks, as shown in Figure 2-19. The Quartus II software uses tx_clkout from Channel 0 in each transceiver block to clock the write port of the transmitter phase compensation FIFO in all four channels of that transceiver block. This results in four clocks resources (global, regional, or both) being used, one for each transceiver block. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 2 2-36 Chapter 2: Arria II GX Transceiver Clocking FPGA Fabric-Transceiver Interface Clocking Figure 2-19. Sixteen Identical Channels across Four Transceiver Blocks for Example 3 Transceiver Block GXBL3 Channel 3 tx_coreclk[15:12] Channel [15:12] TX Data and Control Logic tx_coreclk[11:8] Channel [11:8] TX Data and Control Logic Channel 2 Channel 1 Channel 0 tx_clkout[12] Transceiver Block GXBL2 Channel 3 Channel 2 Channel 1 Channel 0 tx_clkout[8] FPGA Fabric Transceiver Block GXBL1 Channel 3 tx_coreclk[7:4] Channel [7:4] TX Data and Control Logic tx_coreclk[3:0] Channel [3:0] TX Data and Control Logic Channel 2 Channel 1 Channel 0 tx_clkout[4] Transceiver Block GXBL0 Channel 3 Channel 2 Channel 1 Channel 0 tx_clkout[0] Because all 16 channels are identical, using a single tx_clkout to clock the transmitter phase compensation FIFO in all 16 channels results in only one global or regional clock resource being used instead of four. To achieve this, you must choose the transmitter phase compensation FIFO write clocks instead of the Quartus II software automatic selection, as described in "User-Selected Transmitter Phase Compensation FIFO Write Clock" on page 2-37. Arria II GX Device Handbook Volume 2 (c) February 2009 Altera Corporation Chapter 2: Arria II GX Transceiver Clocking FPGA Fabric-Transceiver Interface Clocking 2-37 User-Selected Transmitter Phase Compensation FIFO Write Clock The ALTGX MegaWizard Plug-In Manager provides an optional port named tx_coreclk for each instantiated transmitter channel. If you enable this port, the Quartus II software does not automatically select the transmitter phase compensation FIFO write clock source. Instead, the signal that you drive on the tx_coreclk port of the channel clocks the write side of its transmitter phase compensation FIFO. Use the flexibility of selecting the transmitter phase compensation FIFO write clock to reduce clock resource utilization (global, regional, or both). You can connect the tx_coreclk ports of all identical channels in your design and drive them using a common clock driver that has 0 PPM frequency difference with respect to the FIFO read clocks of all your channels. Use the common clock driver to clock the transmitter data and control logic in the FPGA fabric for all identical channels. This FPGA fabric-transceiver interface clocking scheme utilizes only one global or regional clock resource for all identical channels in your design. Example 4: Sixteen Identical Channels Across Four Transceiver Blocks Figure 2-20 shows 16 identical transmitter channels located across four transceiver blocks. The tx_coreclk ports of all 16 transmitter channels are connected together and driven by a common clock driver. This common clock driver also drives the transmitter data and control logic of all 16 transmitter channels in the FPGA fabric. Only one global or regional clock resource is used with this clocking scheme, compared to four clock resources (global, regional, or both) needed without the tx_coreclk ports (the Quartus II software-selected transmitter phase compensation FIFO write clock). (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 2 2-38 Chapter 2: Arria II GX Transceiver Clocking FPGA Fabric-Transceiver Interface Clocking Figure 2-20. Sixteen Identical Channels across Four Transceiver Blocks for Example 4 Common Clock Driver Transceiver Block GXBL3 Channel 3 tx_coreclk[15:12] Channel [15:12] TX Data and Control Logic Channel 2 Channel 1 tx_clkout[15:12] Channel 0 Transceiver Block GXBL2 Channel 3 tx_coreclk[11:8] Channel [11:8] TX Data and Control Logic Channel 2 Channel 1 tx_clkout[11:8] Channel 0 FPGA Fabric Transceiver Block GXBL1 Channel 3 tx_coreclk[7:4] Channel [7:4] TX Data and Control Logic tx_coreclk[3:0] Channel [3:0] TX Data and Control Logic Channel 2 Channel 1 tx_clkout[7:4] Channel 0 Transceiver Block GXBL0 Channel 3 Channel 2 Channel 1 tx_clkout[3:0] Channel 0 Common Clock Driver Selection Rules The common clock driver driving the tx_coreclk ports of all identical channels must have 0 PPM frequency difference with respect to the transmitter phase compensation FIFO read clocks of these channels. If there is any frequency difference between the FIFO write clock (tx_coreclk) and the FIFO read clock, the FIFO overflows or under runs, resulting in corrupted data transfer between the FPGA fabric and the transmitter. Arria II GX Device Handbook Volume 2 (c) February 2009 Altera Corporation Chapter 2: Arria II GX Transceiver Clocking FPGA Fabric-Transceiver Interface Clocking 2-39 Table 2-10 shows the transmitter phase compensation FIFO read clocks that the Quartus II software selects in various configurations. Table 2-10. Transmitter Phase Compensation FIFO Read Clocks Transmitter Phase Compensation FIFO Read Clock Configuration Non-Bonded Channel Configuration x4 Bonded Channel Configuration x8 Bonded Channel Configuration Without Byte Serializer With Byte Serializer Parallel transmitter PCS clock from the local clock divider in the associated channel (tx_clkout) Divide-by-two version of the parallel transmitter PCS clock from the local clock divider in the associated channel (tx_clkout) Low-speed parallel clock from the CMU0 clock divider of the associated transceiver block (coreclkout) Divide-by-two version of the low-speed parallel clock from the CMU0 clock divider of the associated transceiver block (coreclkout) Low-speed parallel clock from the CMU0 clock divider of the master transceiver block (coreclkout from master transceiver block) Divide-by-two version of the low-speed parallel clock from the CMU0 clock divider of the master transceiver block (coreclkout from master transceiver block) To ensure that you understand the 0 PPM clock driver rule, the Quartus II software expects the following set of user assignments whenever the tx_coreclk port is used to drive the transmitter phase compensation FIFO write clock: 1 GXB 0 PPM Core Clock Setting Failure to make this assignment when using the tx_coreclk port results in a Quartus II compilation error. GXB 0 PPM Core Clock Setting The GXB 0 PPM core clock setting is intended for advanced users who know the clocking configuration of the entire system and want to reduce the FPGA fabric global and regional clock resource utilization. The GXB 0 PPM core clock setting allows the following clock drivers to drive the tx_coreclk ports: 1 tx_clkout in non-bonded channel configurations coreclkout in bonded channel configurations FPGA CLK input pins Transceiver REFCLK pins Clock output from the left corner PLLs (PLL_1 and PLL_4) The Quartus II software does not allow gated clocks or clocks generated in FPGA logic to drive the tx_coreclk ports. Because the GXB 0 PPM core clock setting allows FPGA CLK input pins and transceiver REFCLK pins as the clock driver, the Quartus II compiler cannot determine if there is a 0 PPM difference between the FIFO write clock and read clock for each channel. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 2 2-40 Chapter 2: Arria II GX Transceiver Clocking FPGA Fabric-Transceiver Interface Clocking 1 You must ensure that the clock driver for all connected tx_coreclk ports has a 0 PPM difference with respect to the FIFO read clock in those channels. Figure 2-20 shows the Quartus II assignments that you must make in the assignment editor. Table 2-11. Quartus II Assignments Assignment Description From: Full design hierarchy name of one of the following clock drivers that you choose to drive the tx_coreclk ports of all identical channels (1): To: tx_clkout coreclkout FPGA CLK input pins Transceiver REFCLK pins Clock output from left corner PLLs tx_dataout pins of all identical channels whose tx_coreclk ports are connected together and driven by the 0 PPM clock driver. Assignment Name: GXB 0 PPM Core Clock Setting Value: ON Note to Table 2-11: (1) You can find the full hierarchy name of the 0 PPM clock driver using the Node Finder feature in the Quartus II Assignment Editor. Example 5: Sixteen Identical Channels Across Four Transceiver Blocks Figure 2-21 shows 16 identical transmitter channels located across four transceiver blocks. The tx_coreclk ports of all 16 transmitter channels are connected together and driven by the tx_clkout[4] signal from channel 0 in transceiver block GXBL1. The tx_clkout[4] signal also drives the transmitter data and control logic of all 16 transmitter channels in the FPGA fabric. Only one global clock resource is used by the tx_clkout[4] signal with this clocking scheme. Arria II GX Device Handbook Volume 2 (c) February 2009 Altera Corporation Chapter 2: Arria II GX Transceiver Clocking FPGA Fabric-Transceiver Interface Clocking 2-41 Figure 2-21. Sixteen Identical Channels across Four Transceiver Blocks for Example 5 Transceiver Block GXBL3 Channel 3 tx_coreclk[15:12] Channel [15:12] TX Data and Control Logic Channel 2 Channel 1 Channel 0 tx_clkout[15:12] Transceiver Block GXBL2 Channel 3 tx_coreclk[11:8] Channel [11:8] TX Data and Control Logic Channel 2 Channel 1 Channel 0 tx_clkout[11:8] FPGA Fabric Transceiver Block GXBL1 Channel 3 tx_coreclk[7:4] Channel [7:4] TX Data and Control Logic Channel 2 Channel 1 tx_clkout[4] Channel 0 tx_clkout[7:4] Transceiver Block GXBL0 Channel 3 tx_coreclk[3:0] Channel [3:0] TX Data and Control Logic Channel 2 Channel 1 Channel 0 tx_clkout[3:0] (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 2 2-42 Chapter 2: Arria II GX Transceiver Clocking FPGA Fabric-Transceiver Interface Clocking Table 2-11 shows the Quartus II assignments that you must make for the clocking scheme shown in Figure 2-21. Table 2-12. Quartus II Assignments Assignment Description From: top_level/top_xcvr_instance1/altgx_component/tx_ clkout[4] (1) To: tx_dataout[15..0] Assignment Name: GXB 0 PPM Core Clock Setting Value: ON Note to Table 2-12: (1) This is an example design hierarchy path for the tx_clkout[4] signal. FPGA Fabric-Receiver Interface Clocking The receiver phase compensation FIFO compensates for the phase difference between the parallel receiver PCS clock (FIFO write clock) and the FPGA fabric clock (FIFO read clock). The receiver phase compensation FIFO read clock forms the FPGA fabric-receiver interface clock. The FIFO write and read clocks must have exactly the same frequency, in other words, 0 PPM frequency difference. Arria II GX transceivers provide the following two options for selecting the receiver phase compensation FIFO read clock: Quartus II software-selected receiver phase compensation FIFO read clock User-selected receiver phase compensation FIFO read clock Quartus II Software-Selected Receiver Phase Compensation FIFO Read Clock If you do not select the rx_coreclk port in the ALTGX MegaWizard Plug-In Manager, the Quartus II software automatically selects the receiver phase compensation FIFO read clock for each channel in that ALTGX instance. The Quartus II software selects the FIFO read clock depending on the channel configuration. Non-Bonded Channel Configuration with Rate Matcher In the non-bonded channel configuration, the transceiver channels may or may not be identical. Identical transceiver channels are defined as channels that have the same CMU PLL and receiver CDR input reference clock source, have exactly the same CMU PLL and receiver CDR configuration, and have exactly the same PMA and PCS configuration. Example 6: Four Identical Channels in a Transceiver Block If all four channels within a transceiver block are identical, the Quartus II software automatically drives the read port of the receiver phase compensation FIFO in all four channels with tx_clkout[0], as shown in Figure 2-22. Use the tx_clkout[0] signal to latch the receiver data and status signals from all four channels in the FPGA fabric. Arria II GX Device Handbook Volume 2 (c) February 2009 Altera Corporation Chapter 2: Arria II GX Transceiver Clocking FPGA Fabric-Transceiver Interface Clocking 1 2-43 This configuration uses only one FPGA global or regional clock resource for tx_clkout[0]. Figure 2-22. Four Identical Channels in a Transceiver Block for Example 6 Channel 3 Receiver Channel PMA Receiver Channel PCS Parallel Data wrclk Transmitter Channel PMA Local Clock Divider Block RX Phase Compensation FIFO Channel 3 RX Data and Status Logic rdclk tx_coreclk[3] /2 Low-Speed Parallel Clock Channel 2 Receiver Channel PMA Receiver Channel PCS Parallel Data wrclk Transmitter Channel PMA Local Clock Divider Block RX Phase Compensation FIFO Channel 2 RX Data and Status Logic rdclk tx_coreclk[2] /2 Low-Speed Parallel Clock CMU1 Block CMU0 Block CMU1 Clock Divider CMU1 PLL CMU0 Clock Divider CMU0 PLL Input Reference Clock FPGA Fabric Channel 1 Receiver Channel PMA Receiver Channel PCS Parallel Data RX Phase Compensation FIFO wrclk Transmitter Channel PMA Local Clock Divider Block Channel 1 RX Data and Status Logic rdclk tx_coreclk[1] /2 Low-Speed Parallel Clock Channel 0 Receiver Channel PMA Receiver Channel PCS Parallel Data wrclk Transmitter Channel PMA Local Clock Divider Block RX Phase Compensation FIFO Channel 0 RX Data and Status Logic rdclk tx_coreclk[0] /2 Low-Speed Parallel Clock tx_clkout[0] (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 2 2-44 Chapter 2: Arria II GX Transceiver Clocking FPGA Fabric-Transceiver Interface Clocking Example 7: Two Groups of Two Identical Channels in a Transceiver Block Example 7 assumes channels 0 and 1, driven by CMU0 PLL in a transceiver block, are identical. Also, channels 2 and 3, driven by CMU1 PLL in the same transceiver block, are identical. In this case, the Quartus II software automatically drives the read port of the receiver phase compensation FIFO in channels 0 and 1 with the tx_clkout[0] signal. It also drives the read port of the receiver phase compensation FIFO in channels 2 and 3 with the tx_clkout[2] signal. Use the tx_clkout[0] signal to latch the receiver data and status signals from channels 0 and 1 in the FPGA fabric. Use the tx_clkout[2] signal to latch the receiver data and status signals from channels 2 and 3 in the FPGA fabric. 1 This configuration uses two FPGA clock resources (global, regional, or both), one for the tx_clkout[0] signal and one for the tx_clkout[2] signal. Arria II GX Device Handbook Volume 2 (c) February 2009 Altera Corporation Chapter 2: Arria II GX Transceiver Clocking FPGA Fabric-Transceiver Interface Clocking 2-45 Figure 2-23 shows FPGA fabric-receiver interface clocking for Example 7. Figure 2-23. FPGA Fabric-Receiver Interface Clocking for Example 7 Channel 3 Receiver Channel PMA Receiver Channel PCS Parallel Data wrclk Transmitter Channel PMA Local Clock Divider Block RX Phase Compensation FIFO Channel 3 RX Data and Status Logic rdclk rx_coreclk[3] /2 Low-Speed Parallel Clock Channel 2 Receiver Channel PMA Receiver Channel PCS Parallel Data wrclk Transmitter Channel PMA Local Clock Divider Block RX Phase Compensation FIFO Channel 2 RX Data and Status Logic rdclk rx_coreclk[2] /2 Low-Speed Parallel Clock tx_clkout[2] CMU1 Block CMU1 PLL CMU0 Block CMU0 PLL Reference Clock FPGA Fabric Reference Clock Channel 1 Receiver Channel PMA Receiver Channel PCS Parallel Data RX Phase Compensation FIFO wrclk Channel 1 RX Data and Status Logic rdclk Transmitter Channel PMA Local Clock Divider Block rx_coreclk[1] /2 Low-Speed Parallel Clock Channel 0 Receiver Channel PMA Receiver Channel PCS Parallel Data wrclk Transmitter Channel PMA Local Clock Divider Block RX Phase Compensation FIFO Channel 0 RX Data and Status Logic rdclk rx_coreclk[0] /2 Low-Speed Parallel Clock tx_clkout[0] (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 2 2-46 Chapter 2: Arria II GX Transceiver Clocking FPGA Fabric-Transceiver Interface Clocking Non-Bonded Channel Configuration without Rate Matcher In non-bonded channel configuration without rate matcher, the Quartus II software cannot determine if the incoming serial data in all channels have a 0 PPM frequency difference. The Quartus II software automatically drives the read port of the receiver phase compensation FIFO in each channel with the recovered clock driven on the rx_clkout port of that channel. Use the rx_clkout signal from each channel to latch its receiver data and status signals in the FPGA fabric. 1 This configuration uses one FPGA clock resource (global, regional, or both) per channel for the rx_clkout signal. Figure 2-24 shows the FPGA fabric-receiver interface clocking for non-bonded channel configurations without rate matcher. Figure 2-24. FPGA Fabric-Receiver Interface Clocking for Non-Bonded Channel Configurations without Rate Matcher Channel 3 Receiver Channel PMA Receiver Channel PCS Parallel Data RX Phase Compensation FIFO wrclk rx_datain[3] CDR Parallel Recovered Clock Channel 3 RX Data and Status Logic rdclk rx_coreclk[3] /2 rx_clkout[3] Channel 2 AMP rChannel e vie ce R Receiver PMA Receiver Channel PCS Parallel Data RX Phase Compensation FIFO wrclk Channel 2 RX Data and Status Logic rdclk Input Reference Clock rx_datain[2] rx_coreclk[2] /2 CDR Parallel Recovered Clock rx_clkout[2] FPGA Fabric Channel 1 AMP Channel re vie cePMA R Receiver Receiver Channel PCS Parallel Data RX Phase Compensation FIFO wrclk Channel 1 RX Data and Status Logic rdclk Input Reference Clock rx_datain[1] rx_coreclk[1] /2 CDR Parallel Recovered Clock rx_clkout[1] Channel 0 AMP rChannel e vie ce R Receiver PMA Receiver Channel PCS Parallel Data RX Phase Compensation FIFO wrclk Channel 0 RX Data and Status Logic rdclk Input Reference Clock rx_datain[0] CDR rx_coreclk[0] /2 Parallel Recovered Clock rx_clkout[0] Arria II GX Device Handbook Volume 2 (c) February 2009 Altera Corporation Chapter 2: Arria II GX Transceiver Clocking FPGA Fabric-Transceiver Interface Clocking 2-47 Bonded Channel Configuration All bonded transceiver channel configurations have a rate matcher in the receiver data path. In the x4 bonded channel configurations, the Quartus II software automatically drives the read port of the receiver phase compensation FIFO in all four channels with the coreclkout signal. Use the coreclkout signal to latch the receiver data and status signals from all four channels in the FPGA fabric. In x8 bonded channel configurations, the Quartus II software automatically drives the read port of the receiver phase compensation FIFO in all eight channels with the coreclkout signal from the master transceiver block. Use the coreclkout signal to latch the receiver data and status signals from all eight channels in the FPGA fabric. 1 (c) February 2009 This configuration uses one FPGA global or regional clock resource per bonded link for the coreclkout signal. Altera Corporation Arria II GX Device Handbook Volume 2 2-48 Chapter 2: Arria II GX Transceiver Clocking FPGA Fabric-Transceiver Interface Clocking Figure 2-25 shows FPGA fabric-receiver interface clocking in an x4 bonded channel configuration. Figure 2-25. FGPA Fabric-Receiver Interface Clocking in an x4 Bonded Channel Configuration Channel 3 Receiver Channel PCS Parallel Data RX Phase Compensation FIFO wrclk Low-Speed Parallel Clock from CMU0 Clock Divider Channel 3 RX Data and Status Logic rdclk rx_coreclk[3] /2 Channel 2 Receiver Channel PCS Parallel Data RX Phase Compensation FIFO wrclk Low-Speed Parallel Clock from CMU0 Clock Divider Channel 2 RX Data and Status Logic rdclk rx_coreclk[2] /2 CMU1 Block CMU1 PLL FPGA Fabric coreclkout /2 CMU0 Block CMU0 Clock Divider CMU0 PLL Reference Clock Channel 1 Receiver Channel PCS Parallel Data RX Phase Compensation FIFO wrclk rdclk Channel 1 RX Data and Status Logic rx_coreclk[1] /2 Low-Speed Parallel Clock from CMU0 Clock Divider Channel 0 Receiver Channel PCS Parallel Data RX Phase Compensation FIFO wrclk /2 rdclk Channel 0 RX Data and Status Logic rx_coreclk[0] Low-Speed Parallel Clock from CMU0 Clock Divider Arria II GX Device Handbook Volume 2 (c) February 2009 Altera Corporation Chapter 2: Arria II GX Transceiver Clocking FPGA Fabric-Transceiver Interface Clocking 2-49 Limitations of Quartus II Software-Selected Receiver Phase Compensation FIFO Read Clock In non-bonded channel configurations without rate matcher, the Quartus II software cannot determine if the incoming serial data in all channels has a 0 PPM frequency difference. The Quartus II software uses the recovered clock rx_clkout signal from each channel to clock the read port of its receiver phase compensation FIFO. This results in one clock resource (global, regional, or both) being used per channel for the rx_clkout signal. Example 8: Sixteen Channels Across Four Transceiver Blocks Consider 16 non-bonded receiver channels without rate matcher located across four transceiver blocks, as shown in Figure 2-26. The incoming serial data for all 16 channels has a 0 PPM frequency difference with respect to each other. The Quartus II software uses rx_clkout from each channel to clock the read port of its receiver phase compensation FIFO. This results in 16 clocks resources (global, regional, or both) being used, one for each channel. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 2 2-50 Chapter 2: Arria II GX Transceiver Clocking FPGA Fabric-Transceiver Interface Clocking Figure 2-26. Sixteen Non-Bonded Receiver Channels without Rate Matcher for Example 8 Transceiver Block GXBL3 rx_coreclk[15] Channel 3 rx_clkout[15] rx_coreclk[14] rx_clkout[14] rx_coreclk[13] rx_clkout[13] rx_coreclk[12] Channel 2 Channel [15:12] RX Data and Status Logic Channel 1 Channel 0 rx_clkout[12] Transceiver Block GXBL2 rx_coreclk[11] Channel 3 rx_clkout[11] rx_coreclk[10] rx_clkout[10] rx_coreclk[9] rx_clkout[9] rx_coreclk[8] Channel 2 Channel [11:8] RX Data and Status Logic Channel 1 Channel 0 rx_clkout[8] FPGA Fabric Transceiver Block GXBL1 rx_coreclk[7] Channel 3 rx_clkout[7] rx_coreclk[6] Channel 2 rx_clkout[6] rx_coreclk[5] rx_clkout[5] rx_coreclk[4] Channel [7:4] RX Data and Status Logic Channel 1 Channel 0 rx_clkout[4] Transceiver Block GXBL0 rx_coreclk[3] Channel 3 rx_clkout[3] rx_coreclk[2] rx_clkout[2] rx_coreclk[1] rx_clkout[1] rx_coreclk[0] Channel 2 Channel [3:0] RX Data and Status Logic Channel 1 Channel 0 rx_clkout[0] Since the recovered clock rx_clkout signals from all 16 channels have a 0 PPM frequency difference, you can use a single rx_clkout to clock the receiver phase compensation FIFO in all 16 channels. This results in only one global or regional clock resource being used instead of 16. To achieve this, you must select the receiver phase compensation FIFO read clocks instead of the Quartus II software automatic selection, as described in "User-Selected Receiver Phase Compensation FIFO Read Clock" on page 2-51. Arria II GX Device Handbook Volume 2 (c) February 2009 Altera Corporation Chapter 2: Arria II GX Transceiver Clocking FPGA Fabric-Transceiver Interface Clocking 2-51 User-Selected Receiver Phase Compensation FIFO Read Clock The ALTGX MegaWizard Plug-In Manager provides an optional port named rx_coreclk for each instantiated receiver channel. If you enable this port, the Quartus II software does not automatically select the receiver phase compensation FIFO read clock source. Instead, the signal that you drive on the rx_coreclk port of the channel clocks the read side of its receiver phase compensation FIFO. You can use the flexibility of selecting the receiver phase compensation FIFO read clock to reduce clock resource utilization (global, regional, or both). You can connect the rx_coreclk ports of all receiver channels in your design and drive them using a common clock driver that has a 0 PPM frequency difference with respect to the FIFO write clocks of these channels. Use this common clock driver to latch the receiver data and status signals in the FPGA fabric for these channels. This FPGA fabric transceiver interface clocking scheme utilizes only one global or regional clock resource for all channels. Example 9: Sixteen Identical Channels Across Four Transceiver Blocks Figure 2-27 shows 16 channels located across four transceiver blocks. The incoming serial data to all 16 channels has a 0 PPM frequency difference with respect to each other. The rx_coreclk ports of all 16 channels are connected together and driven by a common clock driver. This common clock driver also latches the receiver data and status logic of all 16 receiver channels in the FPGA fabric. Only one clock resource (global, regional, or both) is used with this clocking scheme, compared to 16 clock resources (global, regional, or both) needed without the rx_coreclk ports (the Quartus II software-selected receiver phase compensation FIFO read clock). (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 2 2-52 Chapter 2: Arria II GX Transceiver Clocking FPGA Fabric-Transceiver Interface Clocking Figure 2-27. Sixteen Identical Channels across Four Transceiver Blocks for Example 9 Common Clock Driver Transceiver Block GXBL3 Channel 3 rx_coreclk[15:12] Channel [15:12] RX Data and Status Logic Channel 2 Channel 1 rx_clkout[15:12] Channel 0 Transceiver Block GXBL2 Channel 3 rx_coreclk[11:8] Channel [11:8] RX Data and Status Logic Channel 2 Channel 1 rx_clkout[11:8] Channel 0 FPGA Fabric Transceiver Block GXBL1 Channel 3 rx_coreclk[7:4] Channel [7:4] RX Data and Status Logic Channel 2 Channel 1 rx_clkout[7:4] Channel 0 Transceiver Block GXBL0 Channel 3 rx_coreclk[3:0] Channel [3:0] RX Data and Status Logic Channel 2 Channel 1 rx_clkout[3:0] Channel 0 Common Clock Driver Selection Rules The common clock driver driving the rx_coreclk ports of all channels must have a 0 PPM frequency difference with respect to the receiver phase compensation FIFO write clocks of these channels. If there is any frequency difference between the FIFO read clock (rx_coreclk) and the FIFO write clock, the FIFO overflows or under runs, resulting in corrupted data transfer between the FPGA fabric and the receiver. Arria II GX Device Handbook Volume 2 (c) February 2009 Altera Corporation Chapter 2: Arria II GX Transceiver Clocking FPGA Fabric-Transceiver Interface Clocking 2-53 Table 2-13 shows receiver phase compensation FIFO write clocks that the Quartus II software selects in various configurations. Table 2-13. Receiver Phase Compensation FIFO Write Clocks Receiver Phase Compensation FIFO Write Clock Configuration Without Byte De-Serializer With Byte De-Serializer Non-Bonded Channel Configuration with rate matcher Low-speed parallel clock from the local clock divider in the associated channel (tx_clkout) Divide-by-two version of the low-speed parallel clock from the local clock divider in the associated channel (tx_clkout) Non-Bonded Channel Configuration without rate matcher Parallel recovered clock from the receiver PMA in the associated channel (rx_clkout) Divide-by-two version of the parallel recovered clock from the receiver PMA in the associated channel (rx_clkout) Low-speed parallel clock from the CMU0 clock divider of the associated transceiver block (coreclkout) Divide-by-two version of the low-speed parallel clock from the CMU0 clock divider of the associated transceiver block (coreclkout) Low-speed parallel clock from the CMU0 clock divider of the master transceiver block (coreclkout from the master transceiver block) Divide-by-two version of the low-speed parallel clock from the CMU0 clock divider of the master transceiver block (coreclkout from the master transceiver block) x4 Bonded Channel Configuration x8 Bonded Channel Configuration To ensure that you understand the 0 PPM clock driver rule, the Quartus II software expects the following set of user assignments whenever the rx_coreclk port is used to drive the receiver phase compensation FIFO read clock: 1 GXB 0 PPM Core Clock Setting Failing to make this assignment correctly when using the rx_coreclk port results in a Quartus II compilation error. GXB 0 PPM Core Clock Setting The GXB 0 PPM core clock setting is intended for advanced users who know the clocking configuration of the entire system and want to reduce the FPGA fabric global and regional clock resource utilization. The GXB 0 PPM core clock setting allows the following clock drivers to drive the rx_coreclk ports: 1 (c) February 2009 tx_clkout in non-bonded channel configurations with rate matcher tx_clkout and rx_clkout in non-bonded configurations without rate matcher coreclkout in bonded channel configurations FPGA CLK input pins Transceiver REFCLK pins Clock output from the left corner PLLs (PLL_1 and PLL_4) The Quartus II software does not allow gated clocks or clocks generated in FPGA logic to drive the tx_coreclk ports. Altera Corporation Arria II GX Device Handbook Volume 2 2-54 Chapter 2: Arria II GX Transceiver Clocking FPGA Fabric-Transceiver Interface Clocking Since the 0 PPM clock group assignment allows FPGA CLK input pins and transceiver REFCLK pins as clock drivers, the Quartus II compiler cannot determine if there is a 0 PPM difference between the FIFO write clock and read clock for each channel. 1 You must ensure that the clock driver for all connected rx_coreclk ports has a 0 PPM difference with respect to the FIFO write clock in those channels. Table 2-14 shows the Quartus II assignments that you must make for the clocking scheme shown in Figure 2-27. Table 2-14. Quartus II Assignments Assignment Description From: Full design hierarchy name of one of the following clock drivers that you choose to drive the rx_coreclk ports of all identical channels (1): tx_clkout rx_clkout coreclkout FPGA CLK input pins Transceiver REFCLK pins Clock output from left and right or top and bottom PLLs To: rx_datain pins of all channels whose rx_coreclk ports are connected together and driven by the 0 PPM clock driver. Assignment Name: GXB 0 PPM Core Clock Setting Value: ON Note to Table 2-14: (1) You can find the full hierarchy name of the 0 PPM clock driver using the Node Finder feature in the Quartus II Assignment Editor. Example 10: Sixteen Channels Across Four Transceiver Blocks Figure 2-28 shows 16 non-bonded channels without rate matcher located across four transceiver blocks. The incoming serial data to all 16 channels have a 0 PPM frequency difference with respect to each other. The rx_coreclk ports of all 16 channels are connected together and driven by rx_clkout[9] in transceiver block GXBL2. The rx_clkout[9] also clocks the receiver data and status signals of all 16 channels in the FPGA fabric. Only one global or regional clock resource is used by rx_clkout[9] with this clocking scheme. Arria II GX Device Handbook Volume 2 (c) February 2009 Altera Corporation Chapter 2: Arria II GX Transceiver Clocking FPGA Fabric-Transceiver Interface Clocking 2-55 Figure 2-28. Sixteen Channels across Four Transceiver Blocks for Example 10 Transceiver Block GXBL3 Channel 3 Channel [15:12] RX Data and Status Logic rx_coreclk[15:12] Channel 2 Channel 1 Channel 0 rx_clkout[15:12] Transceiver Block GXBL2 Channel [11:8] RX Data and Status Logic Channel 3 rx_coreclk[11:8] Channel 2 Channel 1 rx_clkout[9] Channel 0 rx_clkout[11:8] FPGA Fabric Transceiver Block GXBL1 Channel 3 rx_coreclk[7:4] Channel [7:4] RX Data and Status Logic Channel 2 Channel 1 Channel 0 rx_clkout[7:4] Transceiver Block GXBL0 Channel 3 rx_coreclk[3:0] Channel [3:0] RX Data and Status Logic Channel 2 Channel 1 Channel 0 rx_clkout[3:0] (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 2 2-56 Chapter 2: Arria II GX Transceiver Clocking FPGA Fabric PLLs-Transceiver PLLs Cascading Table 2-15 shows the Quartus II assignments that you must make for the clocking scheme shown in Figure 2-28. Table 2-15. Quartus II Assignments for Example 10 Assignment Description From: top_level/top_xcvr_instance1/altgx_component/rx_ clkout[9](1) To: rx_datain[15..0] Assignment Name: GXB 0 PPM Core Clock Setting Value: ON Note to Table 2-15: (1) This is an example design hierarchy path for the rx_clkout[9] signal. FPGA Fabric PLLs-Transceiver PLLs Cascading The CMU PLL synthesizes the input reference clock to generate the high-speed serial clock used in the transmitter PMA. The receiver CDR synthesizes the input reference clock in lock-to-reference mode to generate the high-speed serial clock. This high-speed serial clock output from the CMU PLL and receiver CDR runs at a frequency that is half the configured data rate. The CMU PLLs and receiver CDRs only support multiplication factors (M) of 2, 4, 5, 8, 10, 16, 20, and 25. If you use an on-board crystal oscillator to provide the input reference clock through the dedicated REFCLK pins or ITB lines, the allowed crystal frequencies are limited by the CMU PLL and receiver CDR multiplication factors. The input reference clock frequencies are also limited by the allowed phase frequency detector (PFD) frequency range between 50 MHz and 325 MHz. Example 11: Channel Configuration for 3 Gbps Data Rate Consider a channel configured for 3 Gbps data rate. The high-speed serial clock output from the CMU PLL and receiver CDR must run at 1.5 Gbps. Table 2-16 shows the allowed input reference clock frequencies for Example 11. Table 2-16. Allowed Input Reference Clock Frequencies for Example 11 (Part 1 of 2) Multiplication Factor (M) On-Board Crystal Reference Clock Frequency (MHz) Allowed with /N = 1 With /N = 2 2 750 1500 No. Violates the PFD frequency limit of 325 MHz. 4 375 750 No. Violates the PFD frequency limit of 325 MHz. 5 300 600 Yes. 8 187.5 375 Yes. 10 150 300 Yes. 16 93.75 187.5 Yes. Arria II GX Device Handbook Volume 2 (c) February 2009 Altera Corporation Chapter 2: Arria II GX Transceiver Clocking FPGA Fabric PLLs-Transceiver PLLs Cascading 2-57 Table 2-16. Allowed Input Reference Clock Frequencies for Example 11 (Part 2 of 2) Multiplication Factor (M) On-Board Crystal Reference Clock Frequency (MHz) Allowed with /N = 1 With /N = 2 20 75 150 Yes. 25 60 120 Yes. For a 3-Gbps data rate, the Quartus II software only allows an input reference clock frequency of 60, 75, 93.75, 150, 187.5, 300, 375, and 750 MHz. To overcome this limitation, Arria II GX devices allow the synthesized clock output from left corner PLLs in the FPGA fabric to drive the CMU PLL and receiver CDR input reference clock. The additional clock multiplication factors available in the left corner PLLs allow more options for on-board crystal oscillator frequencies. Dedicated Left PLL Cascade Lines Network Arria II GX devices have a dedicated PLL cascade network on the left side of the device that connects to the input reference clock selection circuitry of the CMU PLLs and receiver CDRs. The dedicated PLL cascade network on the left side of the device connects to the input reference clock selection circuitry of the CMU PLLs and receiver CDRs in transceiver blocks located on the left side of the device. The dedicated PLL cascade networks are segmented by bidirectional tri-state buffers located along the clock line. Segmentation of the dedicated PLL cascade network allows two left PLLs to drive the cascade clock line simultaneously to provide the input reference clock to the CMU PLLs and receiver CDRs in different transceiver blocks. The following sections describe the dedicated PLL cascade networks available in the Arria II GX device family. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 2 2-58 Chapter 2: Arria II GX Transceiver Clocking FPGA Fabric PLLs-Transceiver PLLs Cascading The following are the FPGA fabric PLLs-transceiver PLLs cascading option available for Arria II GX devices with four channels: EP2AGX20CU17 EP2AGX20CF25 EP2AGX30CU17 EP2AGX30CF25 EP2AGX45CU17 EP2AGX65CU17 Figure 2-29 shows the FPGA fabric PLLs-transceiver PLLs cascading option allowed in the EP2AGX20CU17, EP2AGX20CF25, EP2AGX30CF25, EP2AGX45CU17, and EP2AGX65CU17 devices. Figure 2-29. FPGA Fabric PLLs-Transceiver PLLs Cascading Option Allowed in the EP2AGX20CU17, EP2AGX20CF25, EP2AGX30CF25, EP2AGX45CU17, and EP2AGX65CU17 Devices PLL Cascade Network Transceiver Block GXBL0 Channel 3 Channel 2 EP2AGX20CU17 EP2AGX20CF25 EP2AGX30CU17 EP2AGX30CF25 EP2AGX45CU17 EP2AGX65CU17 PLL_1 CDR CDR CMU1 PLL CMU0 PLL Channel 1 Channel 0 PLL_4 CDR CDR The following are the FPGA fabric PLLs-transceiver PLLs cascading option available for Arria II GX devices with eight channels: EP2AGX45DF25 EP2AGX45DF29 EP2AGX65DF25 EP2AGX45DF29 Arria II GX Device Handbook Volume 2 (c) February 2009 Altera Corporation Chapter 2: Arria II GX Transceiver Clocking FPGA Fabric PLLs-Transceiver PLLs Cascading 2-59 EP2AGX95DF25 EP2AGX125DF25 Figure 2-30 shows the FPGA fabric PLLs-transceiver PLLs cascading option allowed in the EP2AGX45DF25, EP2AGX45DF29, EP2AGX65DF25, EP2AGX45DF29, EP2AGX95DF25, and EP2AGX125DF25 devices. Figure 2-30. FPGA Fabric PLLs-Transceiver PLLs Cascading Option Allowed in the EP2AGX45DF25, EP2AGX45DF29, EP2AGX65DF25, EP2AGX45DF29, EP2AGX95DF25, and EP2AGX125DF25 Devices PLL Cascade Network EP2AGX45DF25 EP2AGX45DF29 EP2AGX65DF25 EP2AGX45DF29 EP2AGX95DF25 EP2AGX125DF25 Transceiver Block GXBL1 Channel 3 CDR Channel 2 CDR CMU1 PLL PLL_1 CMU0 PLL Channel 1 CDR Channel 0 CDR Transceiver Block GXBL0 Channel 3 CDR Channel 2 CDR CMU1 PLL CMU0 PLL Channel 1 Channel 0 PLL_4 CDR CDR The following are the FPGA fabric PLLs-transceiver PLLs cascading option available for Arria II GX devices with twelve channels: (c) February 2009 EP2AGX95EF29 EP2AGX95EF35 EP2AGX125EF29 EP2AGX125EF35 EP2AGX190EF29 EP2AGX260EF29 Altera Corporation Arria II GX Device Handbook Volume 2 2-60 Chapter 2: Arria II GX Transceiver Clocking FPGA Fabric PLLs-Transceiver PLLs Cascading Figure 2-31 shows the FPGA fabric PLLs-transceiver PLLs cascading option allowed in the EP2AGX95EF29, EP2AGX95EF35, EP2AGX125EF29, EP2AGX125EF35, EP2AGX190EF29, and EP2AGX260EF29 devices. Figure 2-31. FPGA Fabric PLLs Transceiver PLLs Cascading Option Allowed in the EP2AGX95EF29, EP2AGX95EF35, EP2AGX125EF29, EP2AGX125EF35, EP2AGX190EF29, and EP2AGX260EF29 Devices PLL Cascade Network EP2AGX95EF29 EP2AGX95EF35 EP2AGX125EF29 EP2AGX125EF35 EP2AGX190EF29 EP2AGX260EF29 Transceiver Block GXBL2 Channel 3 Channel 2 CDR CDR CMU1 PLL PLL_1 CMU0 PLL Channel 1 Channel 0 CDR CDR Transceiver Block GXBL1 Channel 3 Channel 2 CDR CDR CMU1 PLL CMU0 PLL Channel 1 Channel 0 CDR CDR Transceiver Block GXBL0 Channel 3 Channel 2 CDR CDR CMU1 PLL CMU0 PLL Channel 1 Channel 0 Arria II GX Device Handbook Volume 2 PLL_4 CDR CDR (c) February 2009 Altera Corporation Chapter 2: Arria II GX Transceiver Clocking FPGA Fabric PLLs-Transceiver PLLs Cascading 2-61 The following are the FPGA fabric PLLs-transceiver PLLs cascading option available for Arria II GX devices with sixteen channels: EP2AGX190FF35 EP2AGX260FF35 Figure 2-32 shows the FPGA fabric PLLs-transceiver PLLs cascading option allowed in the EP2AGX190FF35 and EP2AGX260FF35 devices. Figure 2-32. FPGA Fabric PLLs-Transceiver PLLs Cascading Option Allowed in the EP2AGX190FF35 and EP2AGX260FF35 Devices PLL Cascade Network EP2AGX190FF35 EP2AGX260FF35 Transceiver Block GXBL3 Channel 3 Channel 2 CDR CDR CMU1 PLL PLL_1 CMU0 PLL Channel 1 Channel 0 CDR CDR Transceiver Block GXBL2 Channel 3 Channel 2 CDR CDR CMU1 PLL CMU0 PLL Channel 1 Channel 0 CDR CDR Transceiver Block GXBL1 Channel 3 Channel 2 CDR CDR CMU1 PLL CMU0 PLL Channel 1 Channel 0 CDR CDR Transceiver Block GXBL0 Channel 3 Channel 2 CDR CDR CMU1 PLL CMU0 PLL Channel 1 Channel 0 (c) February 2009 Altera Corporation PLL_4 CDR CDR Arria II GX Device Handbook Volume 2 2-62 Chapter 2: Arria II GX Transceiver Clocking FPGA Fabric PLLs-Transceiver PLLs Cascading FPGA Fabric PLLs-Transceiver PLLs Cascading Rules PLL cascade networks are single clock lines segmented by bidirectional tri-state buffers located along the clock line. Segmentation of the PLL cascade network allows two left PLLs to drive the cascade clock line simultaneously to provide two input reference clocks to the CMU PLLs and receiver CDRs in different transceiver blocks. When cascading two or more FPGA fabric PLLs to the CMU PLLs and receiver CDRs, there must be no crossover in the cascaded clock paths on the PLL cascade network. Example 12: Design Target-EP2AGX190FF35 Device Consider a design targeting the EP2AGX190FF35 device and requiring input reference clocks to the following CMU PLLs and receiver CDRs from two left PLLs in the FPGA fabric: CMU0 PLL in transceiver block GXBL1 Receiver CDRs in channel 2 and channel 3 in transceiver block GXBL1 Case 1: PLL_4 is used to provide the input reference clock to the receiver CDRs in channel 2 and channel 3 (shown in green). PLL_1 is used to provide the input reference clock to the CMU0 PLL (shown in blue) in transceiver block GXBL1. Arria II GX Device Handbook Volume 2 (c) February 2009 Altera Corporation Chapter 2: Arria II GX Transceiver Clocking FPGA Fabric PLLs-Transceiver PLLs Cascading 2-63 Figure 2-33 shows that this FPGA fabric-transceiver PLL cascading configuration is illegal due to crossover (shown in red) of cascade clock paths on the PLL cascade network. Figure 2-33. Illegal FPGA Fabric-Transceiver PLL Cascading Configuration Transceiver Block GXBL3 Channel 3 Channel 2 CDR PLL Cascade Network EP2AGX190FF35 PLL_1 CDR CMU1 PLL CMU0 PLL Channel 1 Channel 0 CDR CDR Transceiver Block GXBL2 Channel 3 CDR Channel 2 CDR CMU1 PLL CMU0 PLL Channel 1 Channel 0 CDR CDR Transceiver Block GXBL1 Channel 3 Channel 2 CDR CDR CMU1 PLL CMU0 PLL Channel 1 Channel 0 CDR CDR Transceiver Block GXBL0 Channel 3 Channel 2 CDR CDR CMU1 PLL CMU0 PLL Channel 1 Channel 0 (c) February 2009 Altera Corporation CDR CDR PLL_4 Arria II GX Device Handbook Volume 2 2-64 Chapter 2: Arria II GX Transceiver Clocking FPGA Fabric PLLs-Transceiver PLLs Cascading Case 2: PLL_1 is used to provide the input reference clock to the receiver CDRs in channel 2 and channel 3 (shown in blue). PLL_4 is used to provide the input reference clock to the CMU0 PLL (shown in green) in transceiver block GXBL1. Figure 2-34 shows that this FPGA fabric-transceiver PLL cascading configuration is legal because there is no crossover of the cascade clock paths on the PLL cascade network. Figure 2-34. Legal FPGA Fabric-Transceiver PLL Cascading Configuration Transceiver Block GXBL3 Channel 3 Channel 2 CDR PLL Cascade Network EP2AGX190FF35 PLL_1 CDR CMU1 PLL CMU0 PLL Channel 1 Channel 0 CDR CDR Transceiver Block GXBL2 Channel 3 CDR Channel 2 CDR CMU1 PLL CMU0 PLL Channel 1 Channel 0 CDR CDR Transceiver Block GXBL1 Channel 3 Channel 2 CDR CDR CMU1 PLL CMU0 PLL Channel 1 Channel 0 CDR CDR Transceiver Block GXBL0 Channel 3 Channel 2 CDR CDR CMU1 PLL CMU0 PLL Channel 1 Channel 0 Arria II GX Device Handbook Volume 2 CDR CDR PLL_4 (c) February 2009 Altera Corporation Chapter 2: Arria II GX Transceiver Clocking Document Revision History 2-65 Document Revision History Table 2-17 shows the revision history for this chapter. Table 2-17. Document Revision History Date and Document Version February 2009, v1.0 (c) February 2009 Changes Made Initial release. Altera Corporation Summary of Changes -- Arria II GX Device Handbook Volume 2 2-66 Arria II GX Device Handbook Volume 2 Chapter 2: Arria II GX Transceiver Clocking Document Revision History (c) February 2009 Altera Corporation 3. Configuring Multiple Protocols and Data Rates AIIGX52003-1.0 Introduction This chapter describes the multiple protocols and data rates for Arria(R) II GX devices. Each transceiver channel in an Arria II GX device can run at an independent data rate or protocol mode. Within each transceiver channel, the transmitter and receiver channel can run at different data rates. Each transceiver block consists of two clock multiplier unit (CMU) phase-locked loops (PLLs) that provide clocks to all the transmitter channels within the transceiver block. Each receiver channel contains a dedicated clock data recovery (CDR). This chapter includes the following sections: "Transceiver PLL Configurations" on page 3-1 "Creating Transceiver Channel Instances" on page 3-2 "General Requirements to Combine Channels" on page 3-2 "Sharing CMU PLLs" on page 3-3 "Combining Receiver Only Channels" on page 3-8 "Combining Transmitter Channel and Receiver Channel Instances" on page 3-9 "Combining Channels Configured in Protocol Functional Modes" on page 3-10 "Combining Transceiver Instances Using PLL Cascade Clocks" on page 3-12 "Combining Transceiver Instances in Multiple Transceiver Blocks" on page 3-13 "Summary" on page 3-15 Transceiver PLL Configurations You can configure each transmitter channel to use one of the two CMU PLLs in the transceiver block. In addition, each transmitter channel has a local divider (/1, /2, or /4) that divides the high-clock output of the CMU PLL to provide high-speed serial and low-speed parallel clocks for its physical coding sublayer (PCS) and physical medium attachment (PMA) functional blocks. You can configure the Rx CDR present in the receiver channel to a distinct data rate and provide separate input reference clocks. Each receiver channel also contains a local divider that divides the high-speed clock output of the Rx CDR and provides clocks for its PCS and PMA functional blocks. To enable transceiver channel settings, the Quartus(R) II software provides the ALTGX MegaWizardTM Plug-In Manager interface. The ALTGX MegaWizard Plug-In Manager allows you to instantiate a single transceiver channel or multiple transceiver channels in Receiver and Transmitter, Receiver Only, and Transmitter Only configurations. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 2 3-2 Chapter 3: Configuring Multiple Protocols and Data Rates Creating Transceiver Channel Instances Creating Transceiver Channel Instances You can instantiate multiple transceiver channels in the General screen of the ALTGX MegaWizard Plug-In Manager in the following ways: For the What is the number of channels? option, select the required value. This method creates the transceiver channels with identical configurations. For examples, refer to "Combining Transceiver Instances in Multiple Transceiver Blocks" on page 3-13. For the What is the number of channels? option, select 1 and create a single channel transceiver instance. To instantiate additional transceiver channels with an identical configuration, stamp the created ALTGX instance multiple times. If you need additional transceiver channels with different configurations, create separate ALTGX megafunction instances with different settings and use them in your design. When you create instances using the above methods, you can force the placement of up to four transceiver channels within the same transceiver block. This is done by assigning the tx_dataout and rx_datain ports of the channel instances to a single transceiver bank. If you do not assign pins to the tx_dataout and rx_datain ports, the Quartus II software chooses default pin assignments. When you compile the design, the Quartus II software combines multiple channel instances within the same transceiver block if the instances meet specific requirements. The following sections explain these requirements for different transceiver configurations. General Requirements to Combine Channels When you create multiple ALTGX instances, the Quartus II software requires that you set identical values on the following parameters and signals to combine the ALTGX instances within the same transceiver block or in the transceiver blocks on the same side of the device. The following sections describe these requirements. Control Signals The gxb_powerdown port is an optional port that you can enable in the ALTGX MegaWizard Plug-In Manager. If enabled, you must drive the gxb_powerdown port in the ALTGX instances from the same logic or the same input pin to enable the Quartus II software to assign them in the same transceiver block. If the gxb_powerdown port is disabled, the Quartus II software ties the port to ground. Calibration Clock and Power Down Each calibration block in an Arria II GX device is shared by multiple transceiver blocks. If your design uses multiple transceiver blocks, depending on the transceiver banks selected, you must connect the cal_blk_clk and cal_blk_powerdown ports of all channel instances to the same input pin or logic. f For more information about the calibration block and transceiver banks that are connected to a specific calibration block, refer to the "Calibration Block" section in the Arria II GX Transceiver Architecture chapter in volume 2 of the Arria II GX Device Handbook. Arria II GX Device Handbook Volume 2 (c) February 2009 Altera Corporation Chapter 3: Configuring Multiple Protocols and Data Rates Sharing CMU PLLs 1 3-3 Asserting the cal_blk_powerdown port affects the calibration circuit on all transceiver channels connected to the calibration block. Sharing CMU PLLs 1 Each Arria II GX transceiver block contains two CMU PLLs. When you create multiple transceiver channel instances and intend to combine them in the same transceiver block, the Quartus II software checks whether a single CMU PLL can be used to provide clock outputs for the transmitter side of the channel instances. If a single CMU PLL is not sufficient, the Quartus II software attempts to combine the channel instances using two CMU PLLs. Otherwise, the Quartus II software issues a Fitter error. The following two sections describe the ALTGX instance requirements to enable the Quartus II software to share the CMU PLL. 1 Only channels combined within the same transceiver block can share the two CMU PLLs available in a transceiver block. Multiple Channels Sharing a CMU PLL To enable the Quartus II software to share the same CMU PLL for multiple channels, the following parameters in the channel instantiations must be identical: Base data rate (the CMU PLL is configured for this data rate) CMU PLL bandwidth setting Reference clock frequency Input reference clock pin pll_powerdown port of the ALTGX instances must be driven from the same logic Each channel instance can have a different local divider setting. This is a useful option when you intend to run each channel within the transceiver block at different data rates that are derived from the same base data rate using the local divider values /1, /2, and /4. This is shown in Example 1. Example 1 Consider an example design with four instances in a Receiver and Transmitter configuration in the same transceiver block at the following serial data rates. Assume that each instance contains a channel, is driven from the same clock source, and has the same CMU PLL bandwidth settings. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 2 3-4 Chapter 3: Configuring Multiple Protocols and Data Rates Sharing CMU PLLs Table 3-1 shows the configuration for Example 1. Table 3-1. Configuration for Example 1 ALTGX MegaWizard Plug-In Manager Settings User-Created Instance Name Number of Channels Configuration Effective Data Rate inst0 1 Receiver and Transmitter 3.75 Gbps inst1 1 Receiver and Transmitter 0.9375 Gbps inst2 1 Receiver and Transmitter 1.875 Gbps inst3 1 Receiver and Transmitter 3.75 Gbps For Example 1, you can share a single CMU PLL for all four channels: One CMU PLL can be configured to run at 3.75 Gbps. Each channel can divide the CMU PLL clock output using the local divider and achieve the required data rates of 3.75 Gbps, 1.875 Gbps, and 0.9375 Gbps. Because each receiver channel has a dedicated CDR, the receiver side in each instance can be set up for these three data rates without restrictions. The following steps show you how to achieve the configuration. To enable the Quartus II software to share a single CMU PLL for all four channels, set the following values in the General screen of the ALTGX MegaWizard Plug-In Manager. 1 For inst0: Set What is the effective data rate? to 3.75 Gbps Set Specify base data rate to 3.75 Gbps For inst1: Set What is the effective data rate? to 1.875 Gbps Set Specify base data rate to 3.75 Gbps For inst2: Set What is the effective data rate? to 0.9375 Gbps Set Specify base data rate to 3.75 Gbps For inst3: Set What is the effective data rate? to 3.75 Gbps Set Specify base data rate to 3.75 Gbps The Specify base data rate option is 3.75 Gbps for all four instances. Because the CMU PLL bandwidth setting and input reference clock are the same and the pll_powerdown ports are driven from the same logic or pin, the Quartus II software shares a single CMU PLL that runs at 3.75 Gbps. You can force the placement of transceiver channels to a specific transceiver block by assigning pins to tx_dataout and rx_datain. Otherwise, the Quartus II software selects a transceiver block. Arria II GX Device Handbook Volume 2 (c) February 2009 Altera Corporation Chapter 3: Configuring Multiple Protocols and Data Rates Sharing CMU PLLs 3-5 Figure 3-1 shows the scenario before and after the Quartus II software combines the transceiver channel instances. Because the Rx CDR is not shared between channels, only the CMU PLL is shown. 1 Each ALTGX instance has a pll_powerdown port. You must drive the pll_powerdown ports of all instances from the same logic to allow the Quartus II software to share the same CMU PLL. If you drive the pll_powerdown ports of the ALTGX instance using different logic, the Quartus II software does not use the same CMU PLL even if all the other required parameters of all the ALTGX instances are identical. Figure 3-1. ALTGX Instances before and after Compilation for Example 1 Before Compilation Example 1 ALTGX Effective Data Rate: 3.75 Gbps After Compilation Example 1 CMU PLL Base Data Rate: 3.75 Gbps Transceiver Block Inst 0 ALTGX Effective Data Rate: 1.875 Gbps Inst 0 Effective Data Rate: 3.75 Gbps TX Loc Div: /1 Inst 1 Effective Data Rate: 1.875 Gbps TX Loc Div: /2 CMU PLL Base Data Rate: 3.75 Gbps Inst 1 ALTGX Effective Data Rate: 0.9375 Gbps Inst 2 Effective Data Rate: 0.9375 Gbps TX Loc Div: /4 Inst 3 Effective Data Rate: 3.75 Gbps TX Loc Div: /1 CMU PLL Base Data Rate: 3.75 Gbps CMU PLL Base Data Rate: 3.75 Gbps Inst 2 ALTGX Effective Data Rate: 3.75 Gbps CMU PLL Base Data Rate: 3.75 Gbps Inst 3 (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 2 3-6 Chapter 3: Configuring Multiple Protocols and Data Rates Sharing CMU PLLs Multiple Channels Sharing Two CMU PLLs In some cases, a single CMU PLL is not sufficient to run the transmitter channels within a transceiver block at the desired data rates. Using a second CMU PLL is useful if you want to combine channels that require different configurations, such as: Quartus II software-defined protocols (for example, Basic, Gigabit Ethernet [GIGE], SONET/synchronous digital hierarchy [SDH], Serial Digital Interface [SDI], or PCI Express [PIPE] modes) CMU PLL bandwidth settings Different input reference clocks Example 2 Consider a design that requires four channels set up in a Receiver and Transmitter configuration in the same transceiver block at the serial data rates shown in Table 3-2. Table 3-2. Configuration for Example 2 ALTGX MegaWizard Plug-In Manager Settings User-Created Instance Name Number of Channels Configuration Effective Data Rate inst0 1 Receiver and Transmitter 3.75 Gbps inst1 1 Receiver and Transmitter 1.875 Gbps inst2 1 Receiver and Transmitter 0.9375 Gbps inst3 1 Receiver and Transmitter 2 Gbps Assume that instance 0, 1, and 2 are driven from the same clock source and have the same CMU PLL bandwidth settings. In this case, you can use one CMU PLL for instance 0, 1, and 2. Refer to "Example 1" on page 3-3 for the ALTGX MegaWizard Plug-In Manager settings that enable the Quartus II software to share the same CMU PLL. A second CMU PLL is required for instance 3. You can force the placement of transceiver channels to a specific transceiver block by assigning pins to the tx_dataout and rx_datain pins of the four ALTGX instances. Otherwise, the Quartus II software selects a transceiver block. Figure 3-2 shows the transceiver configuration before and after the Quartus II software combines the transceiver channels within the same transceiver block. Because the Rx CDR is not shared between channels, only the CMU PLLs are shown. 1 You must connect the pll_powerdown port of instance 0, 1, and 2 to the same logic output to share the same CMU PLL for these instances. Arria II GX Device Handbook Volume 2 (c) February 2009 Altera Corporation Chapter 3: Configuring Multiple Protocols and Data Rates Sharing CMU PLLs 3-7 Figure 3-2. ALTGX Transceiver Channel Instances before and after Compilation for Example 2 Before Compilation Example 2 ALTGX Effective Data Rate: 3.75 Gbps After Compilation Example 2 CMU PLL Base Data Rate: 3.75 Gbps Inst 0 Transceiver Block Inst 0 Effective Data Rate: 3.75 Gbps TX Loc Div: /1 ALTGX Effective Data Rate: 1.875 Gbps CMU PLL Base Data Rate: 3.75 Gbps Inst 1 Effective Data Rate: 1.875 Gbps TX Loc Div: /2 Inst 2 Effective Data Rate: 0.9375 Gbps TX Loc Div: /4 CMU PLL Base Data Rate: 3.75 Gbps Inst 1 ALTGX Effective Data Rate: 0.9375 Gbps CMU PLL Base Data Rate: 3.75 Gbps CMU PLL Base Data Rate: 2 Gbps Inst 3 Effective Data Rate: 2 Gbps TX Loc Div: /1 Inst 2 ALTGX Effective Data Rate: 2 Gbps CMU PLL Base Data Rate: 2 Gbps Inst 3 (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 2 3-8 Chapter 3: Configuring Multiple Protocols and Data Rates Combining Receiver Only Channels In cases where you have two instances with the same serial data rate but with different CMU PLL data rates, the Quartus II software creates a separate CMU PLL for the two instances. For example, consider the configuration shown in Table 3-3. Table 3-3. Sample Configuration Where Instances Cannot Be Combined in a Single Transceiver Block ALTGX MegaWizard Plug-In Manager Settings User-Created Instance Name 1 Number of Channels Configuration Effective Data Rate Base Data Rate inst0 1 Receiver and Transmitter 1.5 Gbps 1.5 Gbps inst1 1 Receiver and Transmitter 1.5 Gbps 3.0 Gbps inst2 1 Receiver and Transmitter 1 Gbps 1 Gbps Even though the effective data rate of inst1 is 1.5 Gbps (3 Gbps/2 = 1.5 Gbps), the same as inst0, when you compile the design, the Quartus II software requires two CMU PLLs to provide clocks for the transmitter side of the two instances because their base data rates are different. In this example, you have the third instance, inst2, that requires a third CMU PLL. Therefore, the Quartus II software cannot combine the above three instances within the same transceiver block. Combining Receiver Only Channels You can selectively use the receiver in the transceiver channel by selecting the Receiver Only configuration in the What is the Operating Mode? option on the General screen of the ALTGX MegaWizard Plug-In Manager. You can combine Receiver Only channel instances of different configurations and data rates into the same transceiver block. Since each receiver channel contains its own dedicated CDR, each Receiver Only instance (assuming one receiver channel per instance) can have different data rates. 1 For the Quartus II software to combine the Receiver Only instances within the same transceiver block, you must connect gxb_powerdown (if used) of all the channel instances from the same logic or input pin. For more information, refer to "General Requirements to Combine Channels" on page 3-2. It is possible to have up to four receiver channels that can run at different data rates by using separate input reference clocks if there are enough clock routing resources available. If you instantiate the Receiver Only configuration, the ALTGX MegaWizard Plug-In Manager does not allow you to enable the rate matching FIFO (clock rate compensation FIFO) in the receiver channel PCS because tx_clkout is not available in a Receiver Only instance to clock the read side of the rate matching FIFO. If you need to perform clock rate compensation, implement the rate matching FIFO in the FPGA fabric. 1 If you create a Receiver Only instance and do not use the transmitter channel that is present in the same physical transceiver channel, the Quartus II software automatically powers down the unused transmitter channel. Arria II GX Device Handbook Volume 2 (c) February 2009 Altera Corporation Chapter 3: Configuring Multiple Protocols and Data Rates Combining Transmitter Channel and Receiver Channel Instances 3-9 Combining Transmitter Channel and Receiver Channel Instances You can create a separate transmitter channel instance and a separate receiver channel instance and assign the tx_dataout and rx_datain pins of the transmitter and receiver instance, respectively, in the same physical transceiver channel. This configuration is useful in cases where you intend to run the transmitter and receiver channel at different serial data rates. To create a transmitter channel instance and a receiver channel instance, select the Transmitter Only and Receiver Only options in the operating mode (General screen) of the ALTGX MegaWizard Plug-In Manager. Multiple Transmitter Channel and Receiver Channel Instances The Quartus II software allows you to combine multiple Transmitter Only channel and Receiver Only channel instances within the same transceiver block. Based on the pin assignments, the Quartus II software combines the corresponding Transmitter Only and Receiver Only channels in the same physical channel. To enable the Quartus II software to combine the transmitter channel and receiver channel instances in the same transceiver block, follow the rules and requirements outlined in the following sections: "General Requirements to Combine Channels" on page 3-2 "Multiple Channels Sharing a CMU PLL" on page 3-3 "Multiple Channels Sharing Two CMU PLLs" on page 3-6 "Combining Receiver Only Channels" on page 3-8 Example 3 Consider that you create four ALTGX instances, as shown in Table 3-4. Table 3-4. Four ALTGX Instances for Example 3 Instance Name Configuration Effective Data Rate Input Reference Clock Frequency inst0 Transmitter only 3.125 Gbps 156.25 MHz inst1 Receiver only 2.5 Gbps 156.25 MHz inst2 Transmitter only 1.25 Gbps 125 MHz inst3 Receiver only 2 Gbps 125 MHz After you create the above instances, if you force the placement of the instances shown in Table 3-5, the Quartus II software combines inst0 and inst1 into physical channel 0 and inst2 and inst3 into physical channel 1. Table 3-5. Forced Placement of the Instances for Example 3 (c) February 2009 Instance Name Physical Channel Pin Assignments in the Same Transceiver Block inst0 Tx pin of channel 0 inst1 Rx pin of channel 0 Altera Corporation inst2 Tx pin of channel 1 inst3 Rx pin of channel 1 Arria II GX Device Handbook Volume 2 3-10 Chapter 3: Configuring Multiple Protocols and Data Rates Combining Channels Configured in Protocol Functional Modes Figure 3-3 shows the transceiver channel instances before and after compilation. Figure 3-3. ALTGX Transceiver Channel Instances before and after Compilation for Example 3 Before Compilation Example 3 ALTGX Effective Data Rate: 3.125 Gbps After Compilation Example 3 CMU PLL Base Data Rate: 3.125 Gbps Transceiver Block Inst 0 Transceiver Channel0 ALTGX TX Channel Inst 0 Effective Data Rate: 3.25 Gbps TX Loc Div: /1 Inst 1 RX Channel Effective Data Rate: 2.5 Gbps RX CDR Base Data Rate: 2.5 Gbps Inst 1 CMU PLL Base Data Rate: 3.125 Gbps ALTGX Effective Data Rate: 1.25 Gbps CMU PLL Base Data Rate: 1.25 Gbps Transceiver Channel1 CMU PLL Base Data Rate: 1.25 Gbps Inst 2 TX Channel Inst 2 Effective Data Rate: 1.25 Gbps TX Loc Div: /1 RX Channel Inst 3 Effective Data Rate: 2 Gbps ALTGX RX CDR Base Data Rate: 2 Gbps Inst 3 Combining Channels Configured in Protocol Functional Modes The following sections describe combining channels that are configured in protocol functional modes. Basic x4 Mode The ALTGX MegaWizard Plug-In Manager provides a Basic mode with a x4 option in the Which sub-protocol will you be using? option on the General screen. If you select this option, all the transmitter channels within the transceiver block receive the high-speed serial and low-speed parallel clock from the CMU0 clock divider block (present in the CMU0 channel). Each receiver channel within the transceiver block is clocked independently by the recovered clock from its receiver CDR. Arria II GX Device Handbook Volume 2 (c) February 2009 Altera Corporation Chapter 3: Configuring Multiple Protocols and Data Rates Combining Channels Configured in Protocol Functional Modes 3-11 When you use this mode, the ALTGX MegaWizard Plug-In Manager allows you to select one or more channels from the What is the number of channels? option on the General screen. 1 If you select the number of channels to be less than four, the remaining transmitter channels within the transceiver block cannot be used. Therefore, if you have more than one instance configured in Transmit Only or Receiver and Transmitter mode with the x4 option enabled, the Quartus II software cannot combine the instances within the same transceiver block. Only the transmitter channels share a common clock. The receiver channels are clocked independently. Therefore, you can configure the unused receiver channels within a transceiver block in any allowed configuration. For example, assume that you configure the ALTGX MegaWizard Plug-In Manager with the options shown in Table 3-6. Table 3-6. General Screen Options in Basic x4 Mode Option Value What protocol will you be using? Basic mode Which subprotocol will you be using? What is the operating mode? x4 Receiver and Transmitter What is the number of channels? 2 If you create the instance with the above selection, you cannot use the remaining two transmitter channels in the transceiver block. However, you can use the remaining two receiver channels in a different configuration. Figure 3-4 shows examples of supported and unsupported configurations. Figure 3-4. Examples of Supported and Unsupported Configurations to Combine Instances in Basic x4 Mode Transceiver Block Transceiver Block Instance 0 2 Channels Receiver and Transmitter Basic mode and x4 sub-protocol Instance 0 2 Channels Receiver and Transmitter Basic mode and x4 sub-protocol Instance 1 2 Channels Receiver only Basic mode (any configuration) 2 Channels Transmitter only Basic mode (any configuration) Supported Configuration (c) February 2009 Altera Corporation Instance 1 Unsupported Configuration Transceiver Block Instance 0 2 Channels Receiver and Transmitter Basic mode and x4 sub-protocol Instance 1 2 Channels Receiver and Transmitter Basic mode and x4 sub-protocol Unsupported Configuration Arria II GX Device Handbook Volume 2 3-12 Chapter 3: Configuring Multiple Protocols and Data Rates Combining Transceiver Instances Using PLL Cascade Clocks Combining Channels Using the PCI Express hard IP Block with Other Channels The Arria II GX device contains an embedded PCI Express hard IP block that performs the phyMAC, datalink, and transaction layer functionality specified by PCI Express base specification 2.0. Each PCI Express hard IP block is shared by two transceiver blocks. The PCI Express compiler wizard provides you the options to configure the PCI Express hard IP block. When enabled, the transceiver channels associated with this block are enabled. There are restrictions on combining transceiver channels with different functional and/or protocol modes (for example, Basic mode) within two contiguous transceiver blocks with the channels that use PCI Express hard IP block. The restrictions depend on the number of channels used (x1 or x4) and the number of virtual channels (VC) selected in the PCI Express compiler MegaWizard Plug-In Manager. Table 3-7 shows the restrictions. Table 3-7. PCI Express hard IP Block Restrictions When Combining Transceiver Channels with Different Functional and/or Protocol Modes (Note 1), (2) PCI Express Configuration (PCI Express hard IP Options Enabled in the PCIe Compiler Wizard) Link Width Lane (Data Interface Width) Virtual Channel (VC) Transceiver Block 0 (3) Transceiver Block 1 (4) Ch0 (5) Ch1 Ch2 Ch3 CH4 Ch5 Ch6 Ch7 1 64 bit 1 PCIe x1 Avail. Avail. Avail. Avail. Avail. Avail. Avail. 4 64 bit 1 PCIe x4 N/A N/A N/A Avail. Avail. Avail. Avail. 8 128 bit 1 PCIe x8 N/A N/A N/A N/A N/A N/A N/A Notes to Table 3-7: (1) Avail.--the channels can be used in other configurations. (2) N/A--the channels are NOT available for use. (3) Transceiver block 0--the master transceiver block that provides high-speed serial and low-speed parallel clocks in a PCI Express (PIPE) x4 or x8 configuration. (4) Transceiver block 1--the adjacent transceiver block that shares the same PCI Express hard IP block with transceiver block 0. (5) The physical channel 0 in the transceiver block. For more information about physical-to-logical channel mapping in PCI Express (PIPE) functional mode, refer to the "x8 Channel Configuration" section in the Arria II GX Transceiver Clocking chapter in volume 2 of the Arria II GX Device Handbook. f For more information about the PCI Express Compiler MegaCore Functions and hard IP implementation, refer to the PCI Express Compiler User Guide. Combining Transceiver Instances Using PLL Cascade Clocks The Arria II GX device provides multiple input reference clock sources to clock the CMU PLLs and Rx CDRs in each transceiver block. The following are the input reference clock sources that can clock the CMU PLLs and Rx CDRs: refclks from the same transceiver block Global clock lines refclks from transceiver blocks on the same side of the device using the inter-transceiver block (ITB) lines PLL cascade clock (this is the cascaded clock output from the PLLs in the FPGA fabric) Arria II GX Device Handbook Volume 2 (c) February 2009 Altera Corporation Chapter 3: Configuring Multiple Protocols and Data Rates Combining Transceiver Instances in Multiple Transceiver Blocks 3-13 If you use the PLL cascade clock to provide input reference clocks to the CMU PLLs or Rx CDRs, there are requirements for combining transceiver channels (as described in the following sections). The Arria II GX transceiver has the ability to cascade the output of the general purpose PLLs to the CMU PLLs and receiver CDRs. The left side of the Arria II GX device contains a PLL cascade clock network--a single line network that connects the PLL cascade clock to the transceiver block. This clock line is segmented to allow different PLL cascade clocks to drive the transceiver CMU PLLs and Rx CDRs. The segmentation locations differ based on the device family. Therefore, there are restrictions when you want to combine transceiver channels that use different PLL cascade clocks as input reference clocks. f For more information about using the PLL cascade clock and segmentation, refer to the "PLL Cascading" section in the Arria II GX Transceiver Clocking chapter in volume 2 of the Arria II GX Device Handbook. Combining Transceiver Instances in Multiple Transceiver Blocks "Creating Transceiver Channel Instances" on page 3-2 describes the method to instantiate multiple transceiver channels using a single ALTGX instance. The following section describes the method to instantiate multiple transceiver channels using multiple transceiver blocks. When you create a transceiver instance that has more than four transceiver channels, the Quartus II software attempts to combine the transceiver channels in multiple transceiver blocks. This is shown in Example 4. Example 4 Consider that you create two ALTGX instances with the configuration shown in Table 3-8. Table 3-8. Two ALTGX Instances for Example 4 Configuration Effective Data Rate Input Reference Clock 7 Receiver and Transmitter 3.125 Gbps 156.25 Gbps 1 Receiver and Transmitter 3.125 Gbps 156.25 Gbps Instance Name Number of Transceiver Channels inst0 inst1 In this case, assuming that all the required parameters specified in "Multiple Channels Sharing a CMU PLL" on page 3-3 are identical in inst0 and inst1, the Quartus II software fits inst0 and inst1 in two transceiver blocks. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 2 3-14 Chapter 3: Configuring Multiple Protocols and Data Rates Combining Transceiver Instances in Multiple Transceiver Blocks Figure 3-5 shows the transceiver instances before compilation for Example 4. Figure 3-5. Transceiver Channel Instances before Compilation for Example 4 Inst0 Effective Data Rate: 3.125 Gbps Input Clock Frequency: 156.125 MHz Number of Channels: 7 Inst1 Effective Data Rate: 3.125 Gbps Input Clock Frequency: 156.25 MHz Number of Channels: 1 Figure 3-6 shows the transceiver instances after compilation for Example 4. Figure 3-6. Combined Transceiver Instances after Compilation for Example 4 Transceiver Block 0 Ch3 of inst0 Transceiver Block 1 Ch0 of inst1 Effective Data Rate: 3.125 Gbps Ch2 of inst0 Effective Data Rate: 3.125 Gbps Ch6 of inst0 Effective Data Rate: 3.125 Gbps Effective Data Rate: 3.125 Gbps CMU PLL CMU PLL Base Data Rate: 3.125 Gbps Base Data Rate: 3.125 Gbps Ch1 of inst0 Ch5 of inst0 Effective Data Rate: 3.125 Gbps Effective Data Rate: 3.125 Gbps Ch0 of inst0 Ch4 of inst0 Effective Data Rate: 3.125 Gbps Effective Data Rate: 3.125 Gbps 1 You can force the placement of the transceiver channels in specific transceiver banks by assigning pins to the tx_dataout and rx_datain ports of inst0 and inst1. Arria II GX Device Handbook Volume 2 (c) February 2009 Altera Corporation Chapter 3: Configuring Multiple Protocols and Data Rates Summary 3-15 1 Even though inst0 instantiates seven transceiver channels, the ALTGX MegaWizard Plug-In Manager provides only one bit for the pll_inclk port for inst0. In your design, provide only one clock input for the pll_inclk port. The Quartus II software uses two transceiver blocks to fit the seven channels and internally connects the input reference clock (connected to the pll_inclk port in your design) to the CMU PLLs of two transceiver blocks. 1 For inst1, the ALTGX MegaWizard Plug-In Manager provides a pll_inclk port. In this example, it is assumed that a single reference clock is provided for inst0 and inst1. Therefore, connect the pll_inclk port of inst0 and inst1 to the same input reference clock pin. This enables the Quartus II software to share a single CMU PLL in transceiver block1 that has three channels of inst0 and one channel of inst1 (shown as ch5, ch6, and ch7 in transceiver block 1) in Figure 3-6. For the Rx CDRs in inst0, the ALTGX MegaWizard Plug-In Manager provides seven bits for the rx_cruclk port (if you do not select the Train Receiver CDR from pll_inclk option in the PLL/Ports screen). This allows separate input reference clocks to the Rx CDRs of each channel. Summary The following summarizes how to configure multiple protocols and data rates in a transceiver block: (c) February 2009 You can run each transceiver channel at independent data rates or protocol functional modes. Each transceiver block consists of two CMU PLLs that provide clocks to run the transmitter channels within the transceiver block. To enable the Quartus II software to combine multiple instances of transceiver channels within a transceiver block, follow the rules specified in "General Requirements to Combine Channels" on page 3-2 and "Sharing CMU PLLs" on page 3-3. You can reset each CMU PLL within a transceiver block using a pll_powerdown signal. For each transceiver instance, the ALTGX MegaWizard Plug-In Manager provides an option to select the pll_powerdown port. If you want to share the same CMU PLL between multiple transceiver channels, connect the pll_powerdown ports of the instances and drive the signal from the same logic. If you enable the PCI Express hard IP block using the PCI Express compiler, the Quartus II software has certain requirements about using the remaining transceiver channels within the transceiver block in other configurations. For more information, refer to "Combining Channels Using the PCI Express hard IP Block with Other Channels" on page 3-12. Altera Corporation Arria II GX Device Handbook Volume 2 3-16 Chapter 3: Configuring Multiple Protocols and Data Rates Document Revision History Document Revision History Table 3-9 shows the revision history for this chapter. Table 3-9. Document Revision History Date and Document Version February 2009, v1.0 Changes Made Initial release. Arria II GX Device Handbook Volume 2 Summary of Changes -- (c) February 2009 Altera Corporation 4. Reset Control and Power Down AIIGX52004-1.1 Introduction Arria(R) II GX devices offer multiple reset signals to control transceiver channels and clock multiplier unit (CMU) phase-locked loops (PLLs) independently. The ALTGX Transceiver MegaWizardTM Plug-In Manager provides individual reset signals for each channel instantiated in the design. It also provides one power-down signal for each transceiver block. This chapter includes the following sections: "User Reset and Power-Down Signals" on page 4-1 "Transceiver Reset Sequences" on page 4-4 "Dynamic Reconfiguration Reset Sequences" on page 4-17 "Power Down" on page 4-20 "Simulation Requirements" on page 4-20 Figure 4-1 shows the reset control and power-down block for an Arria II GX device. Figure 4-1. Reset Control and Power-Down Block tx_digitalreset rx_digitalreset rx_analogreset Reset Controller pll_powerdown gxb_powerdown User Reset and Power-Down Signals Each transceiver channel in the Arria II GX device has individual reset signals to reset its physical coding sublayer (PCS) and physical medium attachment (PMA) blocks. Each CMU PLL in the transceiver block has a dedicated reset signal. The transceiver block also has a power-down signal that affects all the channels and CMU PLLs in the transceiver block. 1 (c) March 2009 All reset and power-down signals are asynchronous. Altera Corporation Arria II GX Device Handbook Volume 2 4-2 Chapter 4: Reset Control and Power Down User Reset and Power-Down Signals The following reset signals are available for each transceiver channel: tx_digitalreset--provides asynchronous reset to all digital logic in the transmitter PCS, including the XAUI transmit state machine, the built-in self test (BIST) pseudo-random binary sequence (PRBS) generator, and the BIST pattern generator. This signal is available in the ALTGX MegaWizard Plug-In Manager in Transmitter Only and Receiver and Transmitter configurations. The minimum pulse width for this signal is two parallel clock cycles. rx_digitalreset--resets all digital logic in the receiver PCS, including the XAUI and GIGE receiver state machine, the XAUI channel alignment state machine, the BIST-PRBS verifier, and the BIST-incremental verifier. This signal is available in the ALTGX MegaWizard Plug-In Manager in Receiver Only and Receiver and Transmitter configurations. The minimum pulse width for this signal is two parallel clock cycles. 1 The tx_digitalreset and rx_digitalreset signals must be asserted until the clocks out of the transmitter PLL and receiver CDR are stabilized. Stable parallel clocks are essential for proper operation of transmitter and receiver phase compensation FIFOs in the PCS. rx_analogreset--resets the receiver CDR present in the receiver channel. This signal is available in the ALTGX MegaWizard Plug-In Manager in Receiver Only and Receiver and Transmitter configurations. The minimum pulse width is two parallel clock cycles. The following power-down signal is available for each CMU PLL in the transceiver block: pll_powerdown--each transceiver block has two CMU PLLs. Each CMU PLL has a dedicated power-down signal called pll_powerdown. The pll_powerdown signal powers down the CMU PLLs that provide high-speed serial and low-speed parallel clocks to the transceiver channels. The following power-down signal is common to the transceiver block: 1 gxb_powerdown--powers down the entire transceiver block. When this signal is asserted, the PCS and PMA in all the transceiver channels and the CMU PLLs are powered down. This signal operates independently from the other reset signals. The refclk (refclk0 or refclk1) buffer is not powered down by any of the above signals. The following status signals are available: pll_locked--indicates the status of the transmitter PLL. A high on this signal shows that the transmitter PLL is locked to the incoming reference clock frequency. rx_pll_locked--a high on this signal shows that the receiver CDR is locked to the incoming reference clock frequency. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 4: Reset Control and Power Down User Reset and Power-Down Signals f 1 4-3 rx_freqlocked--indicates the status of the receiver CDR lock mode. A high level indicates that the receiver is in lock-to-data mode. A low level indicates that the receiver CDR is in lock-to-reference mode. busy--indicates the status of the dynamic reconfiguration controller. The busy signal remains low for the first reconfig_clk clock cycle after power up. It then gets asserted from the second reconfig_clk clock cycle. Assertion on this signal indicates that the offset cancellation process is being executed on the receiver buffer as well as the receiver CDR. When this signal is de-asserted, it indicates that the offset cancellation is complete. For more information, refer to AN 558: Implementing Dynamic Reconfiguration in Arria II GX Devices. This application note will be available in March, 2009. To review this document when it is available, go to the Literature page of the Altera website (www.altera.com). If none of the channels is instantiated in a transceiver block, the Quartus(R) II software automatically powers down the entire transceiver block. Blocks Affected by Reset and Power Down Signals Table 4-1 shows the blocks that are affected by specific reset and power-down signals. Table 4-1. Blocks Affected by Reset and Power-Down Signals Transceiver Block rx_digitalreset rx_analogreset tx_digitalreset CMU PLLs pll_powerdown gxb_powerdown v v Transmitter Phase Compensation FIFO v v Byte Serializer v v 8B/10B Encoder v v Serializer v v v Transmitter Buffer v Transmitter XAUI State Machine v v Receiver Buffer v Receiver CDR v v Receiver Deserializer Receiver Word Aligner v v Receiver Deskew FIFO v v Receiver Clock Rate Compensation FIFO v v Receiver 8B/10B Decoder v v Receiver Byte Deserializer v v Receiver Byte Ordering v v Receiver Phase Compensation FIFO v v Receiver XAUI State Machine v v (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 4-4 Chapter 4: Reset Control and Power Down Transceiver Reset Sequences Transceiver Reset Sequences You can configure transceiver channels in Arria II GX devices in various configurations. In all functional modes except XAUI functional mode, transceiver channels can be either bonded or non-bonded. In XAUI functional mode, transceiver channels must be bonded. In PCI Express (PIPE) functional mode, transceiver channels can be either bonded or non-bonded and need to follow a specific reset sequence. The two categories of reset sequences for Arria II GX devices described in this chapter are: 1 "All Supported Functional Modes Except PCI Express (PIPE) Functional Mode" on page 4-6--describes the reset sequences in bonded and non-bonded configurations. "PCI Express (PIPE) Functional Mode" on page 4-15--describes the reset sequence for the initialization/compliance phase and normal operation phase in PCI Express (PIPE) functional modes. The busy signal remains low for the first reconfig_clk clock cycle. It then gets asserted from the second reconfig_clk clock cycle. Subsequent de-assertion of the busy signal indicates the completion of the offset cancellation process. This busy signal is required in transceiver reset sequences except for Transmitter Only channel configurations. Refer to the reset sequences shown in Figure 4-2 and the associated references listed in the notes. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 4: Reset Control and Power Down Transceiver Reset Sequences 4-5 Figure 4-2. Transceiver Reset Sequences Chart Reset Sequence All supported functional modes except PCI Express (PIPE) PCI Express (PIPE) Initialization and Compliance and Normal Operation Phases (1) Bonded "Transmitter Only" Channel (2) Non-Bonded "Receiver and Transmitter" Channel Receiver CDR in Automatic Lock Mode (3) Receiver CDR in Manual Lock Mode (4) "Transmitter Only" Channel (2) "Receiver Only" Channel Receiver CDR in Automatic Lock Mode (5) Receiver CDR in Manual Lock Mode (6) "Receiver and Transmitter" Channel Receiver CDR in Automatic Lock Mode (7) Receiver CDR in Manual Lock Mode (8) Note to Figure 4-2: (1) (2) (3) (4) (5) (6) (7) (8) Refer to the Timing Diagram in Figure Refer to the Timing Diagram in Figure Refer to the Timing Diagram in Figure Refer to the Timing Diagram in Figure Refer to the Timing Diagram in Figure Refer to the Timing Diagram in Figure Refer to the Timing Diagram in Figure Refer to the Timing Diagram in Figure 1 (c) March 2009 4-10. 4-3. 4-4. 4-5. 4-6. 4-7. 4-8. 4-9. Altera strongly recommends adhering to these reset sequences for proper operation of the Arria II GX transceiver. Altera Corporation Arria II GX Device Handbook Volume 2 4-6 Chapter 4: Reset Control and Power Down Transceiver Reset Sequences All Supported Functional Modes Except PCI Express (PIPE) Functional Mode This section describes the reset sequences for transceiver channels in bonded and non-bonded configurations. Timing diagrams of some typical configurations are shown to facilitate proper reset sequence implementation. In these functional modes, you can set the receiver CDR either in automatic lock or manual lock mode. 1 In manual lock mode, the receiver CDR locks to the reference clock (lock-to-reference) or the incoming serial data (lock-to-data), depending on the logic levels on the rx_locktorefclk and rx_locktodata signals. With the receiver CDR in manual lock mode, you can either configure the transceiver channels in the Arria II GX device in a non-bonded configuration or a bonded configuration. In a bonded configuration, such as XAUI mode, four channels are bonded together. Table 4-2 shows the lock-to-reference (LTR) and lock-to-data (LTD) controller lock modes for the rx_locktorefclk and rx_locktodata signals. Table 4-2. Lock-To-Reference and Lock-To-Data Modes rx_locktorefclk rx_locktodata LTR/LTD Controller Lock Mode 1 0 Manual, LTR Mode -- 1 Manual, LTD Mode 0 0 Automatic Lock Mode Bonded Channel Configuration In a bonded channel configuration, you can reset all the bonded channels simultaneously. Examples of bonded channel configurations are XAUI, PCI Express (PIPE), and Basic x4 functional modes. In Basic x4 functional mode, you can bond Transmitter Only channels together. In XAUI mode, the receiver and transmitter channels are bonded. Each of the receiver channels in this mode has its own output status signals, rx_pll_locked and rx_freqlocked. The timing of these signals is considered in the reset sequence. The following timing diagrams describe the reset and power-down sequences for bonded configurations under the following set-ups: Transmitter Only channel set-up--applicable to Basic x4 functional mode Receiver and Transmitter channel set-up--receiver CDR in automatic lock mode; applicable to XAUI functional mode Receiver and Transmitter channel set-up--receiver CDR in manual lock mode; applicable to XAUI functional mode Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 4: Reset Control and Power Down Transceiver Reset Sequences 4-7 Transmitter Only Channel This configuration contains only a transmitter channel. If you create a Transmitter Only instance in the ALTGX MegaWizard Plug-In Manager in Basic x4 functional mode, use the reset sequence shown in Figure 4-3. Figure 4-3. Sample Reset Sequence for Four Transmitter Only Channels Reset and Power-Down Signals 1 1 s (1) 2 pll_powerdown 4 tx_digitalreset Ouput Status Signals 3 pll_locked Note to Figure 4-3: (1) To be characterized. As shown in Figure 4-3, perform the following reset sequence steps for the Transmitter Only channel configuration: 1. After power up, assert pll_powerdown for a minimum period of 1 s (the time between markers 1 and 2). 2. Keep the tx_digitalreset signal asserted during this time period. After you de-assert the pll_powerdown signal, the transmitter PLL starts locking to the transmitter input reference clock. 3. After the transmitter PLL locks, as indicated by the pll_locked signal going high (marker 3), de-assert the tx_digitalreset signal (marker 4). The transmitter is ready for transmitting data. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 4-8 Chapter 4: Reset Control and Power Down Transceiver Reset Sequences Receiver and Transmitter Channel--Receiver CDR in Automatic Lock Mode This configuration contains both a transmitter and receiver channel. For XAUI functional mode, with the receiver CDR in automatic lock mode, use the reset sequence shown in Figure 4-4. Figure 4-4. Sample Reset Sequence for Four Receiver and Transmitter Channels--Receiver CDR in Automatic Lock Mode Reset Signals 1 1 s (1) 2 pll_powerdown 4 tx_digitalreset 6 rx_analogreset 8 rx_digitalreset Output Status Signals 3 pll_locked Two parallel clock cycles 5 busy 7 rx_freqlocked (0) 7 rx_freqlocked (3) 4 s (1) Note to Figure 4-4: (1) To be characterized. As shown in Figure 4-4, perform the following reset sequence steps for the receiver CDR in automatic lock mode configuration: 1. After power up, assert pll_powerdown for a minimum period of 1 s (the time between markers 1 and 2). 2. Keep the tx_digitalreset, rx_analogreset, and rx_digitalreset signals asserted during this time period. After you de-assert the pll_powerdown signal, the transmitter PLL starts locking to the transmitter input reference clock. 3. After the transmitter PLL locks, as indicated by the pll_locked signal going high, de-assert the tx_digitalreset signal. At this point, the transmitter is ready for data traffic. 4. For the receiver operation, after de-assertion of the busy signal, wait for two parallel clock cycles to de-assert the rx_analogreset signal. After rx_analogreset is de-asserted, the receiver CDR of each channel starts locking to the receiver input reference clock. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 4: Reset Control and Power Down Transceiver Reset Sequences 4-9 5. Wait for the rx_freqlocked signal from each channel to go high. The rx_freqlocked signal of each channel may go high at different times (indicated by the slashed pattern at marker 7). 6. In a bonded channel group, when the rx_freqlocked signals of all the channels have gone high, from that point onwards wait for at least 4 s for the receiver parallel clock to be stable, then de-assert the rx_digitalreset signal (marker 8). At this point, all the receivers are ready for data traffic. Receiver and Transmitter Channel--Receiver CDR in Manual Lock Mode This configuration contains both a transmitter and receiver channel. For XAUI functional mode, with the receiver CDR in manual lock mode, use the reset sequence shown in Figure 4-5. Figure 4-5. Sample Reset Sequence of Four Receiver and Transmitter Channels--Receiver CDR in Manual Lock Mode Reset Signals 1 s (1) 1 2 pll_powerdown 4 tx_digitalreset 6 rx_analogreset 9 rx_digitalreset 4 s (1) CDR Control Signals 8 rx_locktorefclk ( 0 ) 8 rx_locktorefclk ( 3 ) 8 rx_locktodata ( 0 ) 8 rx_locktodata ( 3 ) Output Status Signals 3 pll_locked Two parallel clock cycles 5 busy 7 rx_pll_locked ( 0 ) 7 rx_pll_locked ( 3 ) 15 s (1) Note to Figure 4-5: (1) To be characterized. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 4-10 Chapter 4: Reset Control and Power Down Transceiver Reset Sequences As shown in Figure 4-5, perform the following reset sequence steps for the receiver CDR in manual lock mode configuration: 1. After power up, assert pll_powerdown for a minimum period of 1 s (the time between markers 1 and 2). 2. Keep the tx_digitalreset, rx_analogreset, rx_digitalreset, and rx_locktorefclk signals asserted and the rx_locktodata signal de-asserted during this time period. After you de-assert the pll_powerdown signal, the transmitter PLL starts locking to the transmitter input reference clock. 3. After the transmitter PLL locks, as indicated by the pll_locked signal going high (marker 3), de-assert the tx_digitalreset signal (marker 4). For the receiver operation, after de-assertion of the busy signal, wait for two parallel clock cycles to de-assert the rx_analogreset signal. After the rx_analogreset signal is de-asserted, the receiver CDR of each channel starts locking to the receiver input reference clock because rx_locktorefclk is asserted. 4. Wait for the rx_pll_locked signal from each channel to go high. The rx_pll_locked signal of each channel may go high at different times with respect to each other (indicated by the slashed pattern at the marker 7). 5. In a bonded channel group, when the last rx_pll_locked signal goes high, from that point onwards, wait at least 15 s and then de-assert rx_locktorefclk and assert rx_locktodata (marker 8). At this point, the receiver CDR enters lock-to-data mode and the receiver PLL starts locking to the received data. 6. De-assert rx_digitalreset at least 4 s (the time between markers 8 and 9) after asserting the rx_locktodata signal. Non-Bonded Channel Configuration In non-bonded channels, each channel in the ALTGX megafunction instance contains its own tx_digitalreset, rx_analogreset, rx_digitalreset, rx_pll_locked, and rx_freqlocked signals. You can reset each channel independently. For example, if there are four non-bonded channels, the ALTGX MegaWizard Plug-In Manager provides five signals: tx_digitalreset, rx_analogreset, rx_digitalreset, rx_pll_locked, and rx_freqlocked. The following timing diagrams describe the reset and power-down sequences for one channel in a non-bonded configuration, under five different set-ups: 1 Transmitter Only channel set-up Receiver Only channel set-up--receiver CDR in automatic lock mode Receiver Only channel set-up--receiver CDR in manual lock mode Receiver and Transmitter channel set-up--receiver CDR in automatic lock mode Receiver and Transmitter channel set-up--receiver CDR in manual lock mode Follow the same reset sequence for all the other channels in the non-bonded configuration. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 4: Reset Control and Power Down Transceiver Reset Sequences 4-11 Transmitter Only Channel This configuration contains only a transmitter channel. If you create a Transmitter Only instance in the ALTGX MegaWizard Plug-In Manager, use the same reset sequence as shown in Figure 4-2. Receiver Only Channel--Receiver CDR in Automatic Lock Mode This configuration contains only a receiver channel. If you create a Receiver Only instance in the ALTGX MegaWizard Plug-In Manager with the receiver CDR in automatic lock mode, use the reset sequence shown in Figure 4-6. Figure 4-6. Sample Reset Sequence of Receiver-Only Channel--Receiver CDR in Automatic Lock Mode Reset Signals 2 rx_analogreset 4 rx_digitalreset Two parallel clock cycles Output Status Signals 1 busy 3 rx_freqlocked 4 s (1) Note to Figure 4-6: (1) To be characterized. As shown in Figure 4-6, perform the following reset sequence steps for the receiver CDR in automatic lock mode configuration: 1. After power up, wait for the busy signal to be de-asserted (marker 1). 2. De-assert the rx_analogreset signal (marker 2). 3. Keep the rx_digitalreset signal asserted during this time period. After you de-assert the rx_analogreset signal, the receiver PLL starts locking to the receiver input reference clock. 4. Wait for the rx_freqlocked signal to go high (marker 3). 5. After rx_freqlocked goes high, wait at least 4 s and then de-assert the rx_digitalreset signal (marker 4). At this point, the receiver is ready to receive data. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 4-12 Chapter 4: Reset Control and Power Down Transceiver Reset Sequences Receiver Only Channel--Receiver CDR in Manual Lock Mode This configuration contains only a receiver channel. If you create a Receiver Only instance in the ALTGX MegaWizard Plug-In Manager with the receiver CDR in manual lock mode, use the reset sequence shown in Figure 4-7. Figure 4-7. Sample Reset Sequence of Receiver-Only Channel--Receiver CDR in Manual Lock Mode Reset Signals 2 rx_analogreset 5 rx_digitalreset 4 s (1) CDR Control Signals 4 rx_locktorefclk 4 rx_locktodata Two parallel clock cycles Output Status Signals 1 busy 3 rx_pll_locked 15 s (1) Note to Figure 4-7: (1) To be characterized. As shown in Figure 4-7, perform the following reset sequence steps for the receiver CDR in manual lock mode: 1. After power up, assert rx_analogreset for a minimum period of two parallel clock cycles (the time between markers 1 and 2). 2. Keep the rx_digitalreset and rx_locktorefclk signals asserted and the rx_locktodata signal de-asserted during this time period. 3. After de-assertion of the busy signal, de-assert the rx_analogreset signal, after which the receiver CDR starts locking to the receiver input reference clock because the rx_locktorefclk signal is asserted. 4. Wait at least 15 s (the time between markers 3 and 4) after the rx_pll_locked signal goes high and then de-assert the rx_locktorefclk signal. At the same time, assert the rx_locktodata signal (marker 4). At this point, the receiver CDR enters lock-to-data mode and the receiver PLL starts locking to the received data. 5. De-assert rx_digitalreset at least 4 s (the time between markers 4 and 5) after asserting the rx_locktodata signal. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 4: Reset Control and Power Down Transceiver Reset Sequences 4-13 Receiver and Transmitter Channel--Receiver CDR in Automatic Lock Mode This configuration contains both a transmitter and receiver channel. If you create a Receiver and Transmitter instance in the ALTGX MegaWizard Plug-In Manager with the receiver CDR in automatic lock mode, use the reset sequence shown in Figure 4-8. Figure 4-8. Sample Reset Sequence of Receiver and Transmitter Channel--Receiver CDR in Automatic Lock Mode Reset Signals 1 1 s (1) 2 pll_powerdown 4 tx_digitalreset 6 rx_analogreset 8 rx_digitalreset Two parallel clock cycles Output Status Signals 5 busy 3 pll_locked 7 rx_freqlocked 4 s (1) Note to Figure 4-8: (1) To be characterized. As shown in Figure 4-8, perform the following reset sequence steps for the receiver CDR in automatic lock mode: 1. After power up, assert pll_powerdown for a minimum period of 1 s (the time between markers 1 and 2). 2. Keep the tx_digitalreset, rx_analogreset, and rx_digitalreset signals asserted during this time period. After you de-assert the pll_powerdown signal, the transmitter PLL starts locking to the transmitter input reference clock. 3. After the transmitter PLL locks, as indicated by the pll_locked signal going high (marker 3), de-assert tx_digitalreset. For receiver operation, wait for the busy signal to be de-asserted, after which rx_analogreset is de-asserted. After you de-assert rx_analogreset, the receiver CDR starts locking to the receiver input reference clock. 4. Wait for the rx_freqlocked signal to go high (marker 7). 5. After the rx_freqlocked signal goes high, wait at least 4 s and then de-assert the rx_digitalreset signal (marker 8). The transmitter and receiver are ready for data traffic. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 4-14 Chapter 4: Reset Control and Power Down Transceiver Reset Sequences Receiver and Transmitter Channel--Receiver CDR in Manual Lock Mode This configuration contains both a transmitter and receiver channel. If you create a Receiver and Transmitter instance in the ALTGX MegaWizard Plug-In Manager with the receiver CDR in manual lock mode, use the reset sequence shown in Figure 4-9. Figure 4-9. Sample Reset Sequence of Receiver and Transmitter Channel--Receiver CDR in Manual Lock Mode Reset Signals 1 1 s (1) 2 pll_powerdown 4 tx_digitalreset 6 rx_analogreset 9 rx_digitalreset 4 s (1) CDR Control Signals 8 rx_locktorefclk 8 rx_locktodata Two parallel clock cycles Output Status Signals 5 busy 3 pll_locked 7 rx_pll_locked 15 s (1) Note to Figure 4-9: (1) To be characterized. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 4: Reset Control and Power Down Transceiver Reset Sequences 4-15 As shown in Figure 4-9, perform the following reset sequence steps for the receiver in manual lock mode: 1. After power up, assert pll_powerdown for a minimum period of 1 s (the time between markers 1 and 2). 2. Keep the tx_digitalreset, rx_analogreset, rx_digitalreset, and rx_locktorefclk signals asserted and the rx_locktodata signal de-asserted during this time period. After you de-assert the pll_powerdown signal, the transmitter PLL starts locking to the transmitter input reference clock. 3. After the transmitter PLL locks, as indicated by the pll_locked signal going high (marker 3), de-assert tx_digitalreset. For receiver operation, wait for the busy signal to be de-asserted. At this point, rx_analogreset is de-asserted. After rx_analogreset is de-asserted, the receiver CDR starts locking to the receiver input reference clock because rx_locktorefclk is asserted. 4. Wait for at least 15 s (the time between markers 7 and 8) after the rx_pll_locked signal goes high, then de-assert the rx_locktorefclk signal. At the same time, assert the rx_locktodata signal (marker 8). At this point, the receiver CDR enters lock-to-data mode and the receiver CDR starts locking to the received data. 5. De-assert rx_digitalreset at least 4 s (the time between markers 8 and 9) after asserting the rx_locktodata signal. PCI Express (PIPE) Functional Mode You can configure PCI Express (PIPE) functional mode with or without the receiver clock rate compensation FIFO in the Arria II GX device. The reset sequence remains the same of whether or not you use the receiver clock rate compensation FIFO. PCI Express (PIPE) Reset Sequence PCI Express (PIPE) protocol consists of initialization/compliance phase and normal operation phase. The reset sequences for these two phases are discussed based on the timing diagram in Figure 4-10. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 4-16 Chapter 4: Reset Control and Power Down Transceiver Reset Sequences Figure 4-10. Reset Sequence of PCI Express (PIPE) Functional Mode Initialization/Compliance Phase Normal Operation Phase Reset/Power Down Signals 1 s (1) 1 2 pll_powerdown 4 tx_digitalreset 6 rx_analogreset 8 12 13 rx_digitalreset T3 (3) Two parallel clock cycles Output Status Signals 5 busy 3 pll_locked 7 rx_pll_locked 9 10 11 rx_freqlocked T2 (2) T1 (2) Ignore receive data Notes to Figure 4-10: (1) To be characterized. (2) The minimum T1 and T2 period is 4 s. (3) The minimum T3 period is two parallel clock cycles. PCI Express (PIPE) Initialization/Compliance Phase After the device is powered up, a PCI Express (PIPE)-compliant device goes through the compliance phase during initialization. The rx_digitalreset signal must be de-asserted during this compliance phase to achieve transitions on the pipephydonestatus signal, as expected by the link layer. The rx_digitalreset signal is de-asserted based on the assertion of the rx_freqlocked signal. During the initialization/compliance phase, do not use the rx_freqlocked signal to trigger a de-assertion of the rx_digitalreset signal. Instead, perform the following reset sequence: 1. After power up, assert pll_powerdown for a minimum period of 1 s (the time between markers 1 and 2). Keep the tx_digitalreset, rx_analogreset, and rx_digitalreset signals asserted during this time period. After you de-assert the pll_powerdown signal, the transmitter PLL starts locking to the transmitter input reference clock. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 4: Reset Control and Power Down Dynamic Reconfiguration Reset Sequences 4-17 2. After the transmitter PLL locks, as indicated by the pll_locked signal going high (marker 3), de-assert tx_digitalreset. For receiver operation, wait for the busy signal to be de-asserted and for rx_analogreset to be de-asserted. After rx_analogreset is de-asserted, the receiver CDR starts locking to the receiver input reference clock. 3. When the receiver CDR locks to the input reference clock, as indicated by the rx_pll_locked signal going high at marker 7 in Figure 4-10, de-assert the rx_digitalreset signal (marker 8). After de-asserting rx_digitalreset, the pipephydonestatus signal transitions from the transceiver channel to indicate the status to the link layer. Depending on its status, pipephydonestatus helps with the continuation of the compliance phase. After successful completion of this phase, the device enters into the normal operation phase. PCI Express (PIPE) Normal Phase 1. After completion of the Initialization/Compliance phase when the rx_freqlocked signal is de-asserted, (marker 10 in Figure 4-10), wait for the rx_pll_locked signal assertion signifying the lock-to-reference clock. 2. Next, wait for the rx_freqlocked signal to go high again. In this phase, the received data is valid (not electrical idle) and the receiver CDR locks to the incoming data. 3. Proceed with the reset sequence after assertion of the rx_freqlocked signal. 4. After the rx_freqlocked signal goes high, wait for at least 4 s before asserting rx_digitalreset (marker 12 in Figure 4-10) for two parallel receive clock cycles so that the receiver phase compensation FIFO is initialized. Data from the transceiver block is not valid from the time the rx_freqlocked signal goes low (marker 10 in Figure 4-10) to the time the rx_digitalreset is de-asserted (marker 13 in Figure 4-10). The PLD logic ignores the data during this period (between markers 10 and 13 in Figure 4-10). 1 You can configure the Arria II GX device in x1, x2, x4, and x8 PIPE lane configurations. The reset sequence described in "PCI Express (PIPE) Reset Sequence" on page 4-15 applies to all these multi-lane configurations. Dynamic Reconfiguration Reset Sequences When using dynamic reconfiguration in data rate divisions in TX or Channel and TX CMU PLL select/reconfig modes, use the following reset sequences. Reset Sequence when Using Dynamic Reconfiguration with Data Rate Division in the TX Option Use the example reset sequence shown in Figure 4-11 when you are using the dynamic reconfiguration controller to change the data rate of the transceiver channel. In this example, dynamic reconfiguration is used to dynamically reconfigure the data rate of the transceiver channel configured in Basic x1 mode with the receiver CDR in automatic lock mode. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 4-18 Chapter 4: Reset Control and Power Down Dynamic Reconfiguration Reset Sequences Figure 4-11. Reset Sequence in Basic 1 Mode with the Receiver CDR in Automatic Lock Mode (TX Option) Reset and Control Signals 1 4 tx_digitalreset rate_switch_ctrl[1:0] New Value 1 write_all Output Status Signals 2 3 busy As shown in Figure 4-11, perform the following reset procedure when using the dynamic reconfig controller to change the configuration of the transmitter channel: 1. After power up and properly establishing that the transmitter is operating as desired, write the desired new value for the data rate in the appropriate register (in this example, rate_switch_ctrl[1:0]) and subsequently assert the write_all signal (marker 1) to initiate the dynamic reconfiguration. f For more information, refer to AN 558: Implementing Dynamic Reconfiguration in Arria II GX Devices. 2. Assert the tx_digitalreset signal. 3. As soon as write_all is asserted, the dynamic reconfiguration controller starts to execute its operation. This is indicated by the assertion of the busy signal (marker 2). 4. After the completion of dynamic reconfiguration, the busy signal is de-asserted (marker 3). 5. Lastly, tx_digitalreset can be de-asserted to continue with the transmitter operation (marker 4). Reset Sequence when Using Dynamic Reconfiguration with the Channel and TX PLL select/reconfig Option Use the example reset sequence shown in Figure 4-12 when you are using the dynamic reconfig controller to change the TX PLL settings of the transceiver channel. In this example, the dynamic reconfiguration is used to dynamically reconfigure the data rate of the transceiver channel configured in Basic x1 mode with the receiver CDR in automatic lock mode. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 4: Reset Control and Power Down Dynamic Reconfiguration Reset Sequences 4-19 Figure 4-12. Reset Sequence in Basic 1 Mode with Receiver CDR in Automatic Lock Mode (Channel and TX PLL select/reconfig Option) Reset and Control Signals 1 5 tx_digitalreset 6 1 rx_analogreset 1 8 rx_digitalreset reconfig_mode_sel[2:0] New Value write_all Output Status Signals five parallel clock cycles 2 3 busy 4 channel_reconfig_done 7 rx_1reqlocked 4 s As shown in Figure 4-12, perform the following reset procedure when using the dynamic reconfig controller to change the configuration of the transceiver channel: 1. After power up and establishing that the transceiver is operating as desired, write the desired new value in the appropriate registers (including reconfig_mode_sel[2:0]) and subsequently assert the write_all signal (marker 1) to initiate the dynamic reconfiguration. f For more information, refer to AN 558: Implementing Dynamic Reconfiguration in Arria II GX Devices. 2. Assert the tx_digitalreset, rx_analogreset, and rx_digitalreset signals. 3. As soon as write_all is asserted, the dynamic reconfiguration controller starts to execute its operation. This is indicated by the assertion of the busy signal (marker 2). 4. Wait for the assertion of the channel_reconfig_done signal (marker 4), which indicates the completion of dynamic reconfiguration in this mode. 5. After assertion of the channel_reconfig_done signal, de-assert tx_digitalreset (marker 5) and wait for at least five parallel clock cycles to de-assert the rx_analogreset signal (marker 6). 6. Lastly, wait for the rx_freqlocked signal to go high. After rx_freqlocked goes high (marker 7), wait for 4 s to de-assert the rx_digitalreset signal (marker 8). At this point, the receiver is ready for data traffic. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 4-20 Chapter 4: Reset Control and Power Down Power Down Power Down The Quartus II software automatically selects the power down channel feature, which takes effect when you configure the Arria II GX device. All unused transceiver channels and blocks are powered down to reduce overall power consumption. The gxb_powerdown signal is an optional transceiver block signal. It powers down all the blocks in the transceiver block. The minimum pulse width for this signal is 1 s. After power up, if you use the gxb_powerdown signal, wait for de-assertion of the busy signal, then assert the gxb_powerdown signal for a minimum of 1 s. To finish, follow the sequence in Figure 4-13. Figure 4-13. Sample Reset Sequence of Four Receiver and Transmitter Channels--Receiver CDR in Automatic Lock Mode with Optional gxb_powerdown Signal Reset/Power Down Signals 1 s (1) 2 3 gxb_powerdown pll_powerdown 5 tx_digitalreset 6 rx_analogreset 8 rx_digitalreset Output Status Signals 1 busy 4 pll_locked 7 rx_freqlocked 4 s (1) Note to Figure 4-13: (1) To be characterized. Simulation Requirements The following are simulation requirements: The gxb_powerdown port is optional. In simulation, if the gxb_powerdown port is not instantiated, you must assert the tx_digitalreset, rx_digitalreset, and rx_analogreset signals appropriately for correct simulation behavior. If the gxb_powerdown port is instantiated, and the other reset signals are not used, you must assert the gxb_powerdown signal for at least one parallel clock cycle for correct simulation behavior. Arria II GX Device Handbook Volume 2 (c) March 2009 Altera Corporation Chapter 4: Reset Control and Power Down Document Revision History 4-21 You can de-assert the rx_digitalreset signal immediately after the rx_freqlocked signal goes high to reduce the simulation run time. It is not necessary to wait 4 s (as suggested in the actual reset sequence). The busy signal is de-asserted after about 20 parallel reconfig_clk clock cycles in order to reduce the simulation run time. For silicon behavior in hardware, follow the reset sequences described in this chapter. In PCI Express (PIPE) mode simulation, you must assert the tx_forceelecidle signal for at least one parallel clock cycle before transmitting normal data for correct simulation behavior. Document Revision History Table 4-3 shows the revision history for this chapter. Table 4-3. Document Revision History Date and Document Version Changes Made Summary of Changes March 2009, v1.1 Added the "Dynamic Reconfiguration Reset Sequences" section. -- February 2009, v1.0 Initial release. -- (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 2 4-22 Arria II GX Device Handbook Volume 2 Chapter 4: Reset Control and Power Down Document Revision History (c) March 2009 Altera Corporation Additional Information About this Handbook This handbook provides comprehensive information about the Altera(R) Arria(R) II GX family of devices. How to Contact Altera For the most up-to-date information about Altera products, see the following table. Contact (Note 1) Contact Method Address Technical support Website www.altera.com/support Technical training Website www.altera.com/training Email custrain@altera.com Altera literature services Email literature@altera.com Non-technical support (General) Email nacomp@altera.com (Software Licensing) Email authorization@altera.com Note: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions The following table shows the typographic conventions that this document uses. Visual Cue Meaning Bold Type with Initial Capital Letters Indicates command names and dialog box titles. For example, Save As dialog box. bold type Indicates directory names, project names, disk drive names, file names, file name extensions, dialog box options, software utility names, and other GUI labels. For example, \qdesigns directory, d: drive, and chiptrip.gdf file. Italic Type with Initial Capital Letters Indicates document titles. For example, AN 519: Stratix IV Design Guidelines. Italic type Indicates variables. For example, n + 1. Variable names are enclosed in angle brackets (< >). For example, <file name> and <project name>.pof file. Initial Capital Letters Indicates keyboard keys and menu names. For example, Delete key and the Options menu. "Subheading Title" Quotation marks indicate references to sections within a document and titles of Quartus II Help topics. For example, "Typographic Conventions." (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 2 Info-2 Additional Information Visual Cue Courier type Meaning Indicates signal, port, register, bit, block, and primitive names. For example, data1, tdi, and input. Active-low signals are denoted by suffix n. For example, resetn. Indicates command line commands and anything that must be typed exactly as it appears. For example, c:\qdesigns\tutorial\chiptrip.gdf. Also indicates sections of an actual file, such as a Report File, references to parts of files (for example, the AHDL keyword SUBDESIGN), and logic function names (for example, TRI). 1., 2., 3., and a., b., c., and so on. Numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure. Bullets indicate a list of items when the sequence of the items is not important. 1 The hand points to information that requires special attention. c A caution calls attention to a condition or possible situation that can damage or destroy the product or your work. w A warning calls attention to a condition or possible situation that can cause you injury. r The angled arrow instructs you to press Enter. f The feet direct you to more information about a particular topic. Arria II GX Device Handbook Volume 2 (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 3 101 Innovation Drive San Jose, CA 95134 www.altera.com AIIGX5V3-1.0 Copyright (c) 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Contents Chapter Revision Dates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v Section I. Arria II GX Device Data Sheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-1 Chapter 1. Arria II GX Device Data Sheet Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Maximum Allowed I/O Operating Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Schmitt Trigger Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 I/O Standard Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 Power Consumption for Arria II GX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 Transceiver Performance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 Core Performance Specifications for Arria II GX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 Clock Tree Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 PLL Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24 DSP Block Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 Embedded Memory Block Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26 Periphery Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27 High-Speed I/O Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27 External Memory Interface Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 Duty Cycle Distortion (DCD) Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-33 Additional Information About this Handbook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info-1 How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info-1 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info-1 (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 3 iv Arria II GX Device Handbook Volume 3 Contents (c) February 2009 Altera Corporation Chapter Revision Dates The chapters in this book, Arria II GX Device Handbook Volume 3, were revised on the following dates. Where chapters or groups of chapters are available separately, part numbers are listed. Chapter 1 (c) February 2009 Arria II GX Device Data Sheet Revised: February 2009 Part Number: AIIGX53001-1.0 Altera Corporation Arria II GX Device Handbook Volume 3 vi Arria II GX Device Handbook Volume 3 Chapter Revision Dates (c) February 2009 Altera Corporation Section I. Arria II GX Device Data Sheet This section provides information about the Arria (R) II GX device data sheet. This section includes the following chapters: Chapter 1, Arria II GX Device Data Sheet Revision History Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in this volume. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 3 I-2 Arria II GX Device Handbook Volume 3 Section I. Arria II GX Device Data Sheet (c) February 2009 Altera Corporation 1. Arria II GX Device Data Sheet AIIGX53001-1.0 Introduction This chapter describes the electrical and switching characteristics of the Arria(R) II GX device family. This chapter contains the following sections: "Electrical Characteristics" on page 1-1 "Switching Characteristics" on page 1-11 "Glossary" on page 1-30 Electrical Characteristics The following sections describe the electrical characteristics. Operating Conditions When Arria II GX devices are implemented in a system, they are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of Arria II GX devices, system designers must consider the following operating requirements: 1 Arria II GX devices are offered in both commercial and industrial grades. Commercial devices are offered in -4 (fastest), -5, and -6 (slowest) speed grades. Industrial device is only offered in -5 speed grade. In this chapter, a prefix associated with the operating temperature range is attached to the speed grades; commercial with the "C" prefix, and industrial with the "I" prefix. Commercial devices are therefore indicated as C4, C5, and C6 speed grade respectively, while the industrial device is indicated as I5. Absolute Maximum Ratings Absolute maximum ratings define the maximum operating conditions for Arria II GX devices. The values are based on experiments conducted with the device and theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied under these conditions. 1 (c) February 2009 Conditions beyond those listed in Table 1-1 may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device. Altera Corporation Arria II GX Device Handbook Volume 3 1-2 Chapter 1: Arria II GX Device Data Sheet Electrical Characteristics Table 1-1. Arria II GX Device Absolute Maximum Ratings Symbol Description Minimum Maximum Unit VC C Supplies power to the core, periphery, I/O registers, PCIe HIP block, and transceiver PCS -0.5 1.35 V VC CC B Supplies power to the configuration RAM bits -0.5 1.65 V VC CB AT Battery back-up power supply for design security volatile key register -0.5 3.75 V VC CP D Supplies power to the I/O pre-drivers, differential input buffers, and MSEL circuitry -0.5 3.75 V VC CIO Supplies power to the I/O banks -0.5 3.9 V VC CD_P LL Supplies power to the digital portions of the PLL -0.5 1.35 V VC CA _PLL Supplies power to the analog portions of the PLL and device-wide power management circuitry -0.5 3.75 V VI DC input voltage -0.5 4.0 V VC CA Supplies power to the transceiver PMA regulator -- 2.625 V VC CL_GXB Supplies power to the transceiver PMA TX, PMA RX, and clocking -- 1.21 V VC CH_GXB Supplies power to the transceiver PMA output (TX) buffer -- 1.54 V TJ Operating junction temperature -40 100 C TS TG Storage temperature (no bias) -65 150 C Maximum Allowed Overshoot and Undershoot Voltage During transitions, input signals may overshoot to the voltage shown in Table 1-2 and undershoot to -2.0 V for magnitude of currents less than 100 mA and periods shorter than 20 ns. Table 1-2 lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage over the device lifetime. The maximum allowed overshoot duration is specified as a percentage of high-time over the lifetime of the device. A DC signal is equivalent to 100% duty cycle. For example, a signal that overshoots to 4.3 V can only be at 4.3 V for 5.41% over the lifetime of the device: for a device lifetime of 10 years, this amounts to 5.41/10ths of a year. Arria II GX Device Handbook Volume 3 (c) February 2009 Altera Corporation Chapter 1: Arria II GX Device Data Sheet Electrical Characteristics 1-3 Table 1-2. Maximum Allowed Overshoot During Transitions Symbol VI (AC) Description AC Input Voltage Condition Overshoot Duration as % of High Time Unit 4.0 V 100.000 % 4.05 V 79.330 % 4.1 V 46.270 % 4.15 V 27.030 % 4.2 V 15.800 % 4.25 V 9.240 % 4.3 V 5.410 % 4.35 V 3.160 % 4.4 V 1.850 % 4.45 V 1.080 % 4.5 V 0.630 % 4.55 V 0.370 % 4.6 V 0.220 % Maximum Allowed I/O Operating Frequency Table 1-3 defines the maximum allowed I/O operating frequency for I/Os using the specified I/O standards to ensure device reliability. Table 1-3. Maximum Allowed I/O Operating Frequency I/O Standard SSTL-18, SSTL -15 I/O Frequency (MHz) 300 HSTL-18, HSTL-15 3.3-V and 3.0-V LVTTL 250 3.3-V, 3.0-V, 2.5-V, 1.8-V, 1.5-V LVCMOS PCI and PCI-X SSTL-2 1.2-V LVCMOS 200 HSTL-12 Recommended Operating Conditions This section lists the functional operation limits for AC and DC parameters for Arria II GX devices. The steady-state voltage and current values expected from Arria II GX devices are provided in Table 1-4. All supplies are required to monotonically reach their full-rail values without plateaus within tRAMP . (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 3 1-4 Chapter 1: Arria II GX Device Data Sheet Electrical Characteristics Table 1-4 shows the recommended operating conditions for Arria II GX device. Table 1-4. Arria II GX Device Recommended Operating Conditions Symbol Description Condition Minimum Typical Maximum 0.87 0.90 0.93 Unit Supplies power to the core, periphery, I/O registers, PCIe HIP block, and transceiver PCS -- VC C VC CC B Supplies power to the configuration RAM bits -- 1.425 1.50 1.575 VCCBAT (2) Battery back-up power supply for design security volatile key registers -- 1.2 -- 3.3 Supplies power to the I/O pre-drivers, differential input buffers, and MSEL circuitry -- 3.135 3.3 3.465 V -- 2.85 3.0 3.15 V -- 2.375 2.5 2.625 V -- 3.135 3.3 3.465 V -- 2.85 3.0 3.15 V -- 2.375 2.5 2.625 V -- 1.71 1.8 1.89 V -- 1.425 1.5 1.575 V V VCCPD VCCIO Supplies power to the I/O banks (1) V V V -- 1.14 1.2 1.26 VC CD_P LL Supplies power to the digital portions of the PLL -- 0.87 0.90 0.93 Supplies power to the analog portions of the PLL and device-wide power management circuitry -- 2.375 2.5 2.625 VC CA _PLL VI DC Input voltage -- -0.5 -- 3.6 V VO Output voltage -- 0 -- VC CIO V VC CA Supplies power to the transceiver PMA regulator -- 2.375 2.5 2.625 VC CL_GXB Supplies power to the transceiver PMA TX, PMA RX, and clocking -- 1.045 1.1 1.155 VC CH_GX B Supplies power to the transceiver PMA output (TX) buffer -- 1.425 1.5 1.575 Commercial 0 -- 85 C Industrial -40 -- 100 C Normal POR 0.05 -- 100 ms Fast POR 0.05 -- 4 ms TJ tRAM P Operating junction temperature Power Supply Ramp time V V V V V Note to Table 1-4: (1) VCCIO for 3C and 8C I/O banks where the configuration pins reside only supports 3.3-, 3.0-, 2.5-, or 1.8-V voltage levels. (2) Altera recommends a 3.0-V nominal battery voltage when connecting VCC BAT to a battery for volatile key backup. If you do not use the volatile security key, you may connect the VCC BAT to either GND or a 3.0-V power supply. DC Characteristics This section lists the supply current, I/O pin leakage current, on-chip termination (OCT) accuracy and variation, input pin capacitance, internal weak pull-up and pull-down resistance, hot socketing, and Schmitt trigger input specifications. Arria II GX Device Handbook Volume 3 (c) February 2009 Altera Corporation Chapter 1: Arria II GX Device Data Sheet Electrical Characteristics 1-5 Supply Current Standby current is the current the device draws after the device is configured with no inputs or outputs toggling and no activity in the device. Since these currents vary largely with resources used, use the Excel-based Early Power Estimator (EPE) to get supply current estimates for your design. I/O Pin Leakage Current Table 1-5 defines the Arria II GX I/O pin leakage current specifications. Table 1-5. Arria II GX I/O Pin Leakage Current Symbol Description Conditions Min Typ Max Unit II Input pin VI = 0 V to VCCIOM AX -10 -- 10 A IOZ Tri-stated I/O pin VO = 0 V to VC CIOMA X -10 -- 10 A OCT Specifications Table 1-6 lists the Arria II GX series OCT with and without calibration accuracy. Table 1-6. OCT With and Without Calibration Specification for I/Os (Note 1) Calibration Accuracy Symbol Description Conditions Unit Commercial 25- RS 3.0/2.5 25- series OCT without calibration VC CIO = 3.0/2.5 V 30 % 50- RS 3.0/2.5 50- series COT without calibration VC CIO = 3.0/2.5 V 30 % 25- RS 1.8 25- series OCT without calibration VCC IO = 1.8 V 40 % 50- RS 1.8 50- series OCT without calibration VCC IO = 1.8 V 40 % 25- RS 1.5/1.2 25- series OCT without calibration VC CIO = 1.5/1.2 V 50 % 50- RS 1.5/1.2 50- series OCT without calibration VC CIO = 1.5/1.2 V 50 % 25- RS 3.0/2.5/1.8/ 1.5/1.2 25- series OCT with calibration VCC IO = 3.0/2.5/1.8/ 1.5/1.2 V 10 % 50- RS 3.0/2.5/1.8/ 1.5/1.2 50- series OCT with calibration VCC IO = 3.0/2.5/1.8/ 1.5/1.2 V 10 % Note to Table 1-6: (1) OCT with calibration accuracy is valid at the time of calibration only. OCT calibration is automatically performed at power-up for OCT-enabled I/Os. When voltage and temperature conditions change after calibration, the resistance may change. Use Equation 1-1 to determine the OCT variation when voltage and temperature vary after power-up calibration. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 3 1-6 Chapter 1: Arria II GX Device Data Sheet Electrical Characteristics Equation 1-1. OCT Variation (Note 1) dR dR ROCT = RC AL 1 + ------- x T + ------- x V dT dV Note to Equation 1-1: (1) RCAL is calibrated OCT at power up. T and V are variations in temperature and voltage with respect to temperature and VCCIO values, respectively, at power up. Table 1-7 lists OCT variation with temperature and voltage after power-up calibration. Table 1-7. OCT Variation after Power-up Calibration Nominal Voltage dR/dT (%/C) dR/dT(%/mV) 3.0 0.262 -0.026 2.5 0.234 -0.039 1.8 0.219 -0.086 1.5 0.199 -0.136 1.2 0.161 -0.288 Pin Capacitance Table 1-8 shows the Arria II GX device family pin capacitance. Table 1-8. Arria II GX Device Capacitance Symbol Description Typical Unit 7.5 pF CIODIFF Input capacitance on dual-purpose differential I/O pins CIOCLK Input capacitance on dual-purpose clock output/feedback pins and dedicated clock input pins 7 pF CIOOCT Input capacitance on dual-purpose RUP and RDN pins 7 pF Internal Weak Pull-Up and Weak Pull-Down Resistors Table 1-9 lists the Arria II GX devices weak pull-up and pull-down resistor values. Table 1-9. Arria II GX Internal Weak Pull-up and Weak Pull-Down Resistors (Part 1 of 2) (Note 1) Symbol RPU Description Value of I/O pin pull-up resistor before and during configuration, as well as user mode if the programmable pull-up resistor option is enabled. Arria II GX Device Handbook Volume 3 Conditions Min. Typ. Max. Unit VCC IO = 3.3 V 5% (2), (3) 7 25 41 k VCC IO = 3.0 V 5% (2), (3) 7 28 47 k VCC IO = 2.5 V 5% (2), (3) 8 35 61 k VCC IO = 1.8 V 5% (2), (3) 10 57 108 k VCC IO = 1.5 V 5% (2), (3) 13 82 163 k VCC IO = 1.2 V 5% (2), (3) 19 143 351 k (c) February 2009 Altera Corporation Chapter 1: Arria II GX Device Data Sheet Electrical Characteristics 1-7 Table 1-9. Arria II GX Internal Weak Pull-up and Weak Pull-Down Resistors (Part 2 of 2) (Note 1) Symbol RPD Description Value of TCK pin pull-down resistor Conditions Min. Typ. Max. Unit VC CIO = 3.3 V 5% (4) 6 19 29 k VC CIO = 3.0 V 5% (4) 6 22 32 k VC CIO = 2.5 V 5% (4) 6 25 42 k VC CIO = 1.8 V 5% (4) 7 35 70 k VC CIO = 1.5 V 5% (4) 8 50 112 k Notes to Table 1-9: (1) All I/O pins have an option to enable weak pull-up except configuration, test, and JTAG pins. The weak pull-down feature is only available for JTAG TCK. (2) Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO. (3) RPU = (VCCIO - VI)/IRPU. Minimum condition: -40C; VCCIO = VCC + 5%, V I = VCC + 5% - 50 mV. Typical condition: 25C; VCCIO = VCC, VI = 0 V. Maximum condition: 100C; VCCIO = VCC - 5%, VI = 0 V; in which VI refers to the voltage input at the I/O pin. (4) RPD = VI/I RPD. Minimum condition: -40C; VCCIO = VCC + 5%, VI = 50 mV. Typical condition: 25C; VCCIO = VCC, VI = VCC - 5%. Maximum condition: 100C; VCCIO = VCC - 5%, VI = VCC - 5%; in which V I refers to the voltage input at the I/O pin. Hot Socketing Table 1-10 defines the hot socketing specification for Arria II GX devices. Table 1-10. Arria II GX Hot Socketing Specifications Symbol Description Maximum IIIOPIN(DC) DC current per I/O pin 300 A IIOPIN(AC) AC current per I/O pin 8 mA (1) IXCVRTX(DC) DC current per transceiver TX pin 100 mA IXCVRRX(DC) DC current per transceiver RX pin 50 mA Notes to Table 1-10: (1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which "C" is I/O pin capacitance and "dv/dt" is slew rate. Schmitt Trigger Input The Arria II GX device supports Schmitt trigger input on TDI, TMS, TCK, nSTATUS, nCONFIG, nCE, CONF_DONE, and DCLK pins. A Schmitt trigger introduces hysteresis to the input signal for improved noise immunity, especially for signals with slow edge rates. Table 1-11 lists the hysteresis specifications across the supported V CCIO range for Schmitt trigger inputs in Arria II GX devices. Table 1-11. Arria II GX Schmitt Trigger Input Hysteresis Specifications Symbol VSchmitt (c) February 2009 Description Hysteresis for Schmitt trigger input Altera Corporation Condition Minimum Unit VCCIO = 3.3 V 220 mV VCCIO = 2.5 V 180 mV VCCIO = 1.8 V 110 mV VCCIO = 1.5 V 70 mV Arria II GX Device Handbook Volume 3 1-8 Chapter 1: Arria II GX Device Data Sheet Electrical Characteristics I/O Standard Specifications Table 1-12 through Table 1-17 list input voltage (VIH and VIL), output voltage (VOH and VOL), and current drive characteristics (IOH and IOL) for various I/O standards supported by Arria II GX devices. They also show the Arria II GX device family I/O standard specifications. VOL and VOH values are valid at the corresponding IOH and IOL, respectively. 1 For an explanation of terms used in Table 1-12 through Table 1-17, refer to "Glossary" on page 1-30. Table 1-12 lists the Arria II GX single-ended I/O standards. Table 1-12. Single-Ended I/O Standards VCCIO (V) VIL (V) VIH (V) VO L (V) VOH (V) Min Typ Max Min Max Min Max Max Min IOL (mA) IOH (mA) 3.135 3.3 3.465 -0.3 0.8 1.7 VCCIO + 0.3 0.4 2.4 2 -2 3.135 3.3 3.465 -0.3 0.8 1.7 VCCIO + 0.3 0.2 VCCIO - 0.2 0.1 -0.1 2.85 3 3.15 -0.3 0.8 1.7 VCCIO + 0.3 0.4 2.4 2 -2 2.85 3 3.15 -0.3 0.8 1.7 VCCIO + 0.3 0.2 VCCIO - 0.2 0.1 -0.1 2.375 2.5 2.625 -0.3 0.7 1.7 VCCIO + 0.3 0.4 2 1 -1 1.71 1.8 1.89 -0.3 0.35 x VCC IO 0.65 x VCC IO VCC IO + 0.3 0.45 VCC IO - 0.45 2 -2 1.425 1.5 1.575 -0.3 0.35 x VCC IO 0.65 x VCC IO VCC IO + 0.3 0.25 * VCC IO 0.75 x VC CIO 2 -2 1.14 1.2 1.26 -0.3 0.35 x VCC IO 0.65 x VCC IO VCC IO + 0.3 0.25 * VCC IO 0.75 x VC CIO 2 -2 2.85 3 3.15 -- 0.3 x VCC IO 0.5 x VCC IO 3.6 0.1 x VCC IO 0.9 x VCC IO 1.5 -0.5 2.85 3 3.15 -- 0.35 x VCC IO 0.5 x VCC IO -- 0.1 x VCC IO 0.9 x VCC IO 1.5 -0.5 I/O Standard 3.3 V LVTTL 3.3 V LVCMOS 3.0 V LVTTL 3.0 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 3.0-V PCI 3.0-V PCI-X Table 1-13 lists the Arria II GX single-ended SSTL and HSTL I/O reference voltage specifications. Table 1-13. Single-Ended SSTL and HSTL I/O Reference Voltage Specifications (Part 1 of 2) VCC IO (V) VREF (V) VTT (V) I/O Standard SSTL-2 Class I, II SSTL-18 Class I, II Min Typ Max Min Typ Max Min Typ Max 2.375 2.5 2.625 0.49 x VC CIO 0.5 x VC CIO 0.51 x VCC IO VREF 0.04 VREF VREF + 0.04 1.71 1.8 1.89 0.49 x VC CIO 0.5 x VC CIO 0.51 x VCC IO VREF 0.04 VREF VREF + 0.04 Arria II GX Device Handbook Volume 3 (c) February 2009 Altera Corporation Chapter 1: Arria II GX Device Data Sheet Electrical Characteristics 1-9 Table 1-13. Single-Ended SSTL and HSTL I/O Reference Voltage Specifications (Part 2 of 2) VCC IO (V) VREF (V) VTT (V) I/O Standard Min Typ Max Min Typ Max Min Typ Max 1.425 1.5 1.575 0.49 x VC CIO 0.5 x VC CIO 0.51 x VCC IO VREF 0.04 VREF VREF + 0.04 HSTL-18 Class I, II 1.71 1.8 1.89 0.85 0.9 0.95 -- VC CIO/2 -- HSTL-15 Class I, II 1.425 1.5 1.575 0.68 0.75 0.9 -- VC CIO/2 -- 1.14 1.2 1.26 0.48 x VC CIO 0.5 x VC CIO 0.52 x VCC IO -- VC CIO/2 -- SSTL-15 Class I, II HSTL-12 Class I, II Table 1-14 lists the Arria II GX single-ended SSTL and HSTL I/O standard signal specifications. Table 1-14. Single-Ended SSTL and HSTL I/O Standard Signal Specifications VIL(DC ) (V) VIH (D C) (V) VIL (A C) (V) VIH (A C) (V) VO L (V) VOH (V) Iol (mA) Ioh (mA) VTT + 0.57 8.1 -8.1 VTT 0.76 VTT + 0.76 16.2 -16.2 VREF + 0.25 VTT 0.475 VTT + 0.475 6.7 -6.7 VREF -0.25 VREF + 0.25 0.28 VCC IO 0.28 13.4 -13.4 VCC IO + 0.3 VREF 0.175 VREF + 0.175 0.2 x VC CIO 0.8 x VC CIO 8 -8 VREF + 0.1 VCC IO + 0.3 VREF 0.175 VREF + 0.175 0.2 x VC CIO 0.8 x VC CIO 16 -16 VREF 0.1 VREF + 0.1 VCC IO + 0.3 VREF -0.2 VREF + 0.2 0.4 VCC IO 0.4 8 -8 -0.3 VREF 0.1 VREF + 0.1 VCC IO + 0.3 VREF -0.2 VREF + 0.2 0.4 VCC IO 0.4 16 -16 -0.3 VREF 0.1 VREF + 0.1 VCC IO + 0.3 VREF -0.2 VREF + 0.2 0.4 VCC IO 0.4 8 -8 -0.3 VREF 0.1 VREF + 0.1 VCC IO + 0.3 VREF -0.2 VREF + 0.2 0.4 VCC IO 0.4 16 -16 -0.15 VREF 0.08 VREF + 0.08 VCC IO + 0.15 VREF -0.15 VREF + 0.15 0.25 x VC CIO 0.75 x VC CIO 8 -8 -0.15 VREF 0.08 VREF + 0.08 VCC IO + 0.15 VREF -0.15 VREF + 0.15 0.25 x VC CIO 0.75 x VC CIO 16 -16 I/O Standard SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I SSTL-18 Class II SSTL-15 Class I SSTL-15 Class II HSTL-18 Class I HSTL-18 Class II HSTL-15 Class I HSTL-15 Class II HSTL-12 Class I HSTL-12 Class II (c) February 2009 Min Max Min Max Max Min Max Min -0.3 VREF 0.15 VREF + 0.15 VCC IO + 0.3 VREF 0.31 VREF + 0.31 VTT 0.57 -0.3 VREF 0.15 VREF + 0.15 VCC IO + 0.3 VREF 0.31 VREF + 0.31 -0.3 VREF 0.125 VREF + 0.125 VCC IO + 0.3 VREF -0.25 -0.3 VREF 0.125 VREF + 0.125 VCC IO + 0.3 -0.3 VREF 0.1 VREF + 0.1 -0.3 VREF 0.1 -0.3 Altera Corporation Arria II GX Device Handbook Volume 3 1-10 Chapter 1: Arria II GX Device Data Sheet Electrical Characteristics Table 1-15 lists the Arria II GX differential SSTL I/O standards. Table 1-15. Differential SSTL I/O Standards VCC IO (V) VSWIN G(DC ) (V) VX(A C) (V) VSWIN G(AC ) (V) VOX (A C) (V) I/O Standard SSTL-2 Class I, II Min Typ Max Min Max Min Typ Max Min Max Min Typ Max 2.375 2.5 2.625 0.36 VC CIO VCC IO/2 - 0.2 -- VCCIO/2 + 0.2 0.7 VCC IO (1) -- (1) 1.71 1.8 1.89 0.25 VC CIO VCC IO/2 0.175 -- VCCIO/2 + 0.175 0.5 VCC IO (1) -- (1) 1.425 1.5 1.575 0.2 -- (1) -- (1) 0.35 -- (1) -- (1) SSTL-18 Class I, II SSTL-15 Class I, II Note to Table 1-15: (1) Pending silicon characterization. Table 1-16 lists the Arria II GX HSTL I/O standards. Table 1-16. Differential HSTL I/O Standards VCC IO (V) VDIF(DC) (V) VX (A C) (V) VC M(DC ) (V) VDIF(A C) (V) I/O Standard Min Typ Min Max Min Typ Max Min Typ 1.89 0.2 -- 0.85 -- 0.95 0.88 -- 0.95 0.4 -- 0.79 0.4 -- 0.52 x VC CIO 0.3 -- HSTL-18 Class I 1.71 HSTL-15 Class I, II 1.425 1.5 1.575 0.2 -- 0.71 -- 0.79 0.71 -- 1.14 1.26 -- -- 0.5 x VC CIO -- 0.48 x VCC IO 0.5 x VC CIO HSTL-12 Class I, II 1.8 Max 1.2 0.16 Max Min Max Table 1-17 lists the Arria II GX differential I/O standard specifications. Table 1-17. Differential I/O Standard Specifications I/O Standard VCCIO (V) Min Typ VTH (mV) Max Min Cond. VC M = 1.25 V VICM (V) (4) VOD (V) (1) Max Min Cond. Max -- 0.05 Dm ax <= 700 Mbps 1.80 -- 1.05 Dm ax > 700 Mbps 1.55 VOS (V) Min Typ Max Min Typ Max 0.247 -- 0.6 1.125 1.25 1.375 2.5V LVDS 2.375 RSDS (3) 2.375 2.5 2.625 -- -- -- -- -- -- 0.1 0.2 0.6 0.5 1.2 1.4 MiniLVDS (3) 2.375 2.5 2.625 -- -- -- -- -- -- 0.25 -- 0.6 1 1.2 1.4 0.6 Dm ax <= 700 Mbps 1.8 Dm ax > 700 Mbps -- -- -- -- -- -- 1.0 1.6 LVPECL (2) 2.375 2.5 2.5 2.625 2.625 100 300 -- -- Notes to Table 1-17: (1) (2) (3) (4) RL range: 90 <= RL <= 110 . LVPECL input standard is supported at the dedicated clock input pins (GCLK) only. RSDS and mini-LVDS I/O standards are only supported for differential outputs. VIN range: 0 <= VIN <= 1.85 V. Arria II GX Device Handbook Volume 3 (c) February 2009 Altera Corporation Chapter 1: Arria II GX Device Data Sheet Switching Characteristics 1-11 Power Consumption for Arria II GX Devices Altera(R) offers two ways to estimate power for a design: the Excel-based Early Power Estimator and the Quartus(R) II PowerPlay Power Analyzer feature. The interactive Excel-based Early Power Estimator is typically used prior to designing the FPGA in order to get a magnitude estimate of the device power. The Quartus II PowerPlay Power Analyzer provides better quality estimates based on the specifics of the design after place-and-route is complete. The PowerPlay Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities which, when combined with detailed circuit models, can yield very accurate power estimates. f For more information about power estimation tools, refer to the Early Power Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II Handbook. Switching Characteristics This section provides performance characteristics of the Arria II GX core and periphery blocks for commercial grade devices. These characteristics can be designated as Preliminary and Final. Preliminary characteristics are created using simulation results, process data, and other known parameters. Final characteristics are based on actual silicon characterization and testing. These numbers reflect the actual performance of the device under worst-case silicon process, voltage, and junction temperature conditions. 1 The table title shows the designations as "Preliminary" or "Final" for each table. Transceiver Performance Specifications Table 1-18 lists the Arria II GX transceiver specifications. Table 1-18. Arria II GX Transceiver Specification--Preliminary (Part 1 of 4) Symbol/ Description C4 C5 C6 Conditions Unit Min Typ Max Min Typ Max Min Typ Max Reference Clock Input frequency from REFCLK input pins -- 50 -- 622.08 50 -- 622.08 50 -- 622.08 MHz Input frequency from PLD input -- 50 -- 200 50 -- 200 50 -- 200 MHz Absolute VMAX for a REFCLK pin -- -- -- 2.2 -- -- 2.2 -- -- 2.2 V Absolute VMIN for a REFCLK pin -- -0.3 -- -- -0.3 -- -- -0.3 -- -- V Rise/fall time -- -- -- 0.2 -- -- 0.2 -- -- 0.2 UI Duty cycle -- 45 -- 55 45 -- 55 45 -- 55 % Peak-to-peak differential input voltage -- 200 -- 2000 200 -- 2000 200 -- 2000 mV (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 3 1-12 Chapter 1: Arria II GX Device Data Sheet Switching Characteristics Table 1-18. Arria II GX Transceiver Specification--Preliminary (Part 2 of 4) Symbol/ Description C4 C5 C6 Conditions Unit Min Typ Max Min Typ Max Min Typ Max Spread-spectrum modulating clock frequency PCI Express 30 -- 33 30 -- 33 30 -- 33 Spread-spectrum downspread PCI Express -- 0 to -- -- 0 to -- -- 0 to -- -0.5% -0.5% kHz -0.5% On-chip termination resistors -- -- 100 -- -- 100 -- -- 100 -- VICM (AC coupled) -- -- 1200 -- -- 1200 -- -- 1200 -- mV 250 -- 550 250 -- 550 250 -- 550 mV -- 2000 1% -- -- 2000 1% -- -- 2000 1% -- 10 -- 125 10 -- 125 10 -- 125 MHz -- 125 -- -- 125 -- -- 125 -- MHz -- -- 1 -- -- 1 -- -- 1 -- s Data rate -- 600 -- 3750 600 -- 3125 600 -- 3125 Mbps Absolute VM AX for a receiver pin (1) -- -- -- 1.5 -- -- 1.5 -- -- 1.5 V Absolute VM IN for a receiver pin -- -0.4 -- -- -0.4 -- -- -0.4 -- -- V VICM (DC coupled) Rref HCSL I/O standard for PCI Express reference clock -- -- Transceiver Clocks Calibration block clock frequency fixedclk clock frequency Transceiver block minimum power-down pulse width -- PCI Express Receiver Detect Receiver Maximum peak-to-peak differential input voltage VID (diff p-p) VICM = 0.82 V setting -- -- 2.7 -- -- 2.7 -- -- 2.7 V VICM =1.1 V setting (7) -- -- 1.6 -- -- 1.6 -- -- 1.6 V Minimum peak-to-peak differential input voltage VID (diff p-p) Data Rate = 600 Mbps to 3.75 Gbps. 100 -- -- 100 -- -- 100 -- -- mV VICM = 0.82 V setting -- 820 -- -- 820 -- -- 820 -- mV VICM =1.1 V setting (7) -- 1100 -- -- 1100 -- -- 1100 -- mV VICM Arria II GX Device Handbook Volume 3 (c) February 2009 Altera Corporation Chapter 1: Arria II GX Device Data Sheet Switching Characteristics 1-13 Table 1-18. Arria II GX Transceiver Specification--Preliminary (Part 2 of 4) Symbol/ Description C4 C5 C6 Conditions Unit Min Typ Max Min Typ Max Min Typ Max Spread-spectrum modulating clock frequency PCI Express 30 -- 33 30 -- 33 30 -- 33 Spread-spectrum downspread PCI Express -- 0 to -- -- 0 to -- -- 0 to -- -0.5% -0.5% kHz -0.5% On-chip termination resistors -- -- 100 -- -- 100 -- -- 100 -- VICM (AC coupled) -- -- 1200 -- -- 1200 -- -- 1200 -- mV 250 -- 550 250 -- 550 250 -- 550 mV -- 2000 1% -- -- 2000 1% -- -- 2000 1% -- 10 -- 125 10 -- 125 10 -- 125 MHz -- 125 -- -- 125 -- -- 125 -- MHz -- -- 1 -- -- 1 -- -- 1 -- s Data rate -- 600 -- 3750 600 -- 3125 600 -- 3125 Mbps Absolute VM AX for a receiver pin (1) -- -- -- 1.5 -- -- 1.5 -- -- 1.5 V Absolute VM IN for a receiver pin -- -0.4 -- -- -0.4 -- -- -0.4 -- -- V VICM (DC coupled) HCSL I/O standard for PCI Express reference clock -- Rref -- Transceiver Clocks Calibration block clock frequency fixedclk clock frequency Transceiver block minimum power-down pulse width -- PCI Express Receiver Detect Receiver Maximum peak-to-peak differential input voltage VID (diff p-p) VICM = 0.82 V setting -- -- 2.7 -- -- 2.7 -- -- 2.7 V VICM =1.1 V setting (7) -- -- 1.6 -- -- 1.6 -- -- 1.6 V Minimum peak-to-peak differential input voltage VID (diff p-p) Data Rate = 600 Mbps to 3.75 Gbps. 100 -- -- 100 -- -- 100 -- -- mV VICM = 0.82 V setting -- 820 -- -- 820 -- -- 820 -- mV VICM =1.1 V setting (7) -- 1100 -- -- 1100 -- -- 1100 -- mV VICM (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 3 1-14 Chapter 1: Arria II GX Device Data Sheet Switching Characteristics Table 1-18. Arria II GX Transceiver Specification--Preliminary (Part 3 of 4) Symbol/ Description Differential on-chip termination resistors Return loss differential mode Return loss common mode C4 C5 C6 Conditions 100- setting Unit Min Typ Max Min Typ Max Min Typ Max -- 100 -- -- 100 -- -- 100 -- PCI Express 50 MHz to 1.25 GHz: -10dB XAUI 100 MHz to 2.5 GHz: -10dB PCI Express 50 MHz to 1.25 GHz: -6dB XAUI 100 MHz to 2.5 GHz: -6dB Programmable PPM detector (2) -- Run length -- -- 80 -- -- 80 -- -- 80 -- UI Programmable equalization -- -- -- 7 -- -- 7 -- -- 7 dB 65 -- 175 65 -- 175 65 -- 175 mV 75 -- -- 75 -- -- 75 s 15 -- -- 15 -- -- s Signal detect/loss threshold 62.5, 100, 125, 200, ppm 250, 300, 500, 1000 PCI Express (PIPE) Mode CDR LTR time (3) -- -- -- CDR minimum T1b (4) -- 15 -- LTD lock time (5) -- 0 100 4000 0 100 4000 0 100 4000 ns Data lock time from rx_freqlocked (6) -- -- -- 4000 -- -- 4000 -- -- 4000 ns DC Gain Setting = 0 -- 0 -- -- 0 -- -- 0 -- dB DC Gain Setting = 1 -- 3 -- -- 3 -- -- 3 -- dB DC Gain Setting = 2 -- 6 -- -- 6 -- -- 6 -- dB -- -- -- -- -- -- -- -- -- Mbps 0.65 V setting -- 650 -- -- 650 -- -- 650 -- mV 100- setting -- 100 -- -- 100 -- -- 100 -- Programmable DC gain Transmitter Data rate VOC M Differential on-chip termination resistors Return loss differential mode Return loss common mode PCI Express 50 MHz to 1.25 GHz: -10dB XAUI 312 MHz to 625 MHz: -10dB 625 MHz to 3.125 GHz: -10dB/decade slope PCI Express 50 MHz to 1.25 GHz: -6dB Rise time -- 50 -- 200 50 -- 200 50 -- 200 ps Fall time -- 50 -- 200 50 -- 200 50 -- 200 ps Intra-differential pair skew -- -- -- 15 -- -- 15 -- -- 15 ps Arria II GX Device Handbook Volume 3 (c) February 2009 Altera Corporation Chapter 1: Arria II GX Device Data Sheet Switching Characteristics 1-15 Table 1-18. Arria II GX Transceiver Specification--Preliminary (Part 4 of 4) Symbol/ Description C4 C5 C6 Conditions Unit Min Typ Max Min Typ Max Min Typ Max Intra-transceiver block skew PCI Express (PIPE) x4 -- -- 120 -- -- 120 -- -- 120 ps Inter-transceiver block skew PCI Express (PIPE) x8 -- -- 300 -- -- 300 -- -- 300 ps -- -- -- 100 -- -- 100 -- -- 100 s Interface speed -- 25 -- 200 25 -- 160 25 -- 130 MHz Digital reset pulse width -- CMU PLL0 and CMU PLL1 CMU PLL lock time from CMUPLL_reset deassertion PLD-Transceiver Interface Minimum is 2 parallel clock cycles Notes to Table 1-18: (1) (2) (3) (4) The device cannot tolerate prolonged operation at this absolute maximum. The rate matcher supports only up to +/-300 parts per million (ppm). Time taken to rx_pll_locked goes high from rx_analogreset deassertion. Refer to Figure 1-1. Time for which the CDR must be kept in lock-to-reference mode after rx_pll_locked goes high and before rx_locktodata is asserted in manual mode. Refer to Figure 1-1. (5) Time taken to recover valid data after the rx_locktodata signal is asserted in manual mode. Refer to Figure 1-1. (6) Time taken to recover valid data after the rx_freqlocked signal goes high in automatic mode. Refer to Figure 1-2. (7) The 1.1-V RX VIC M setting must be used if the input serial data standard is LVDS and the link is DC-coupled. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 3 1-16 Chapter 1: Arria II GX Device Data Sheet Switching Characteristics Figure 1-1 shows the lock time parameters in manual mode. 1 LTD = lock-to-data. LTR = lock-to-reference. Figure 1-1. Lock Time Parameters for Manual Mode r x_analogreset CDR status LTR LTD r x_pll_locked r x_locktodata Invalid Data Valid data r x_dataout CDR LTR Time LTD lock time CDR Minimum T1b Figure 1-2 shows the lock time parameters in automatic mode. Figure 1-2. Lock Time Parameters for Automatic Mode CDR status LTR LTD r x_freqlocked r x_dataout Invalid Valid data data Data lock time from rx_freqlocked Arria II GX Device Handbook Volume 3 (c) February 2009 Altera Corporation Chapter 1: Arria II GX Device Data Sheet Switching Characteristics 1-17 Figure 1-3 shows the differential receiver input waveform. Figure 1-3. Receiver Input Waveform Single-Ended Waveform Positive Channel (p) VID Negative Channel (n) VCM Ground Differential Waveform VID (diff peak-peak) = 2 x VID (single-ended) VID p-n=0V VID Figure 1-4 shows the transmitter output waveform. Figure 1-4. Transmitter Output Waveform--Preliminary Single-Ended Waveform Positive Channel (p) VOD Negative Channel (n) VCM Ground Differential Waveform VOD (diff peak-peak) = 2 x VOD (single-ended) VOD p-n=0V VOD Table 1-19 shows the typical VOD for TX term that equals 100 . . Table 1-19. Typical VOD Setting, TX Term = 100 --Preliminary VO D Setting (mV) Symbol VOD Typical (mV) (c) February 2009 200 400 600 700 800 900 1000 1200 200 400 600 700 800 900 1000 1200 Altera Corporation Arria II GX Device Handbook Volume 3 1-18 Chapter 1: Arria II GX Device Data Sheet Switching Characteristics Table 1-20 shows the typical VOD for TX term that equals 150 . . Table 1-20. Typical VOD Setting, TX Term = 150 --Preliminary VO D Setting (mV) Symbol VOD Typical (mV) 300 600 900 1050 1200 300 600 900 1050 1200 Table 1-21 shows the Arria II GX transceiver block AC specifications. Table 1-21. Arria II GX Transceiver Block AC Specification--Preliminary (Note 1), (2) (Part 1 of 6) C4 Symbol/ Description C5 C6 Conditions Unit Min Typ Max Min Typ Max Min Typ Max SONET/SDH Receiver Jitter Tolerance Jitter frequency = 0.03 KHz > 15 > 15 > 15 UI Pattern = PRBS23 Jitter tolerance at 622.08 Mbps Jitter frequency = 25 KHZ > 1.5 > 1.5 > 1.5 UI Pattern = PRBS23 Jitter frequency = 250 KHz > 0.15 > 0.15 > 0.15 UI Pattern = PRBS23 Jitter frequency = 0.06 KHz > 15 > 15 > 15 UI Pattern = PRBS23 Jitter frequency = 100 KHZ Jitter tolerance at 2488.32 Mbps > 1.5 > 1.5 > 1.5 UI Pattern = PRBS23 Jitter frequency = 1 MHz > 0.15 > 0.15 > 0.15 UI Pattern = PRBS23 Jitter frequency = 10 MHz > 0.15 > 0.15 > 0.15 UI Pattern = PRBS23 Fibre Channel Transmit Jitter Generation (3), (10) Total jitter FC-1 Pattern = CRPAT -- -- 0.23 -- -- 0.23 -- -- 0.23 UI Deterministic jitter FC-1 Pattern = CRPAT -- -- 0.11 -- -- 0.11 -- -- 0.11 UI Total jitter FC-2 Pattern = CRPAT -- -- 0.33 -- -- 0.33 -- -- 0.33 UI Deterministic jitter FC-2 Pattern = CRPAT -- -- 0.2 -- -- 0.2 -- -- 0.2 UI Fibre Channel Receiver Jitter Tolerance (3), (11) Deterministic jitter FC-1 Pattern = CJTPAT > 0.37 > 0.37 > 0.37 UI Random jitter FC-1 Pattern = CJTPAT > 0.31 > 0.31 > 0.31 UI Arria II GX Device Handbook Volume 3 (c) February 2009 Altera Corporation Chapter 1: Arria II GX Device Data Sheet Switching Characteristics 1-19 Table 1-21. Arria II GX Transceiver Block AC Specification--Preliminary (Note 1), (2) (Part 2 of 6) C4 Symbol/ Description Sinusoidal jitter FC-1 C5 C6 Conditions Unit Min Typ Max Min Typ Max Min Typ Max Fc/25000 > 1.5 > 1.5 > 1.5 UI Fc/1667 > 0.1 > 0.1 > 0.1 UI Deterministic jitter FC-2 Pattern = CJTPAT > 0.33 > 0.33 > 0.33 UI Random jitter FC-2 Pattern = CJTPAT > 0.29 > 0.29 > 0.29 UI Sinusoidal jitter FC-2 Fc/25000 > 1.5 > 1.5 > 1.5 UI Fc/1667 > 0.1 > 0.1 > 0.1 UI XAUI Transmit Jitter Generation (4) Total jitter at 3.125 Gbps Pattern = CJPAT -- -- 0.3 -- -- 0.3 -- -- 0.3 UI Deterministic jitter at 3.125 Gbps Pattern = CJPAT -- -- 0.17 -- -- 0.17 -- -- 0.17 UI XAUI Receiver Jitter Tolerance (4) Total jitter > 0.65 > 0.65 > 0.65 UI Deterministic jitter > 0.37 > 0.37 > 0.37 UI Peak-to-peak jitter Jitter frequency = 22.1 KHz > 8.5 > 8.5 > 8.5 Peak-to-peak jitter Jitter frequency = 1.875 MHz > 0.1 > 0.1 > 0.1 Peak-to-peak jitter Jitter frequency = 20 MHz > 0.1 > 0.1 > 0.1 UI UI UI PCI Express Transmit Jitter Generation (5) Total jitter at 2.5 Gbps (Gen1) Compliance pattern -- -- 0.25 -- -- 0.25 -- -- 0.25 UI PCI Express Receiver Jitter Tolerance (5) Total jitter at 2.5 Gbps (Gen1) Compliance pattern > 0.6 > 0.6 > 0.6 UI Serial RapidIO Transmit Jitter Generation (6) Deterministic jitter (peak-to-peak) Data Rate = 1.25, 2.5, 3.125 Gbps -- -- 0.17 -- -- 0.17 -- -- 0.17 UI Pattern = CJPAT Total jitter (peak-to-peak) Data Rate = 1.25, 2.5, 3.125 Gbps -- -- 0.35 -- -- 0.35 -- -- 0.35 UI Pattern = CJPAT Serial RapidIO Receiver Jitter Tolerance (6) Deterministic jitter tolerance (peak-to-peak) Data Rate = 1.25, 2.5, 3.125 Gbps > 0.37 > 0.37 > 0.37 UI Pattern = CJPAT Combined deterministic and random jitter tolerance (peak-to-peak) (c) February 2009 Data Rate = 1.25, 2.5, 3.125 Gbps > 0.55 > 0.55 > 0.55 UI Pattern = CJPAT Altera Corporation Arria II GX Device Handbook Volume 3 1-20 Chapter 1: Arria II GX Device Data Sheet Switching Characteristics Table 1-21. Arria II GX Transceiver Block AC Specification--Preliminary (Note 1), (2) (Part 3 of 6) C4 Symbol/ Description C5 C6 Conditions Unit Min Typ Max Min > 8.5 Jitter Frequency = 22.1 KHz Data Rate = 1.25, 2.5, 3.125 Gbps Typ Max Min > 8.5 Typ Max > 8.5 UI Pattern = CJPAT Jitter Frequency = 1.875 MHz Sinusoidal jitter tolerance (peak-to-peak) > 0.1 > 0.1 > 0.1 Data Rate = 1.25, 2.5, 3.125 Gbps UI Pattern = CJPAT Jitter Frequency = 20 MHz > 0.1 > 0.1 > 0.1 Data Rate = 1.25, 2.5, 3.125 Gbps UI Pattern = CJPAT GIGE Transmit Jitter Generation (7) Deterministic jitter Pattern = CRPAT -- -- 0.14 -- -- 0.14 -- -- 0.14 Pattern = CRPAT -- -- 0.279 -- -- 0.279 -- -- 0.279 (peak-to-peak) Total jitter (peak-to-peak) UI UI GIGE Receiver Jitter Tolerance (7) Deterministic jitter tolerance (peak-to-peak) Pattern = CJPAT > 0.4 > 0.4 > 0.4 Combined deterministic and random jitter tolerance (peak-to-peak) Pattern = CJPAT > 0.66 > 0.66 > 0.66 UI UI HiGig Transmit Jitter Generation (8) Deterministic jitter (peak-to-peak) Data Rate = 3.75 Gbps -- -- 0.17 -- -- -- -- -- -- UI Pattern = CJPAT Total jitter (peak-to-peak) Data Rate = 3.75 Gbps -- -- 0.35 -- -- -- -- -- -- UI Pattern = CJPAT HiGig Receiver Jitter Tolerance (8) Deterministic jitter tolerance (peak-to-peak) Data Rate = 3.75 Gbps > 0.37 -- -- -- -- -- -- UI Pattern = CJPAT Combined deterministic and random jitter tolerance (peak-to-peak) Data Rate = 3.75 Gbps > 0.65 -- -- -- -- -- -- UI Pattern = CJPAT Arria II GX Device Handbook Volume 3 (c) February 2009 Altera Corporation Chapter 1: Arria II GX Device Data Sheet Switching Characteristics 1-21 Table 1-21. Arria II GX Transceiver Block AC Specification--Preliminary (Note 1), (2) (Part 4 of 6) C4 Symbol/ Description C5 C6 Conditions Unit Min Jitter Frequency = 22.1 KHz Typ Max > 8.5 Min Typ Max Min Typ Max -- -- -- -- -- -- Data Rate = 3.75 Gbps UI Pattern = CJPAT Jitter Frequency = 1.875MHz Sinusoidal jitter tolerance (peak-to-peak) > 0.1 -- -- -- -- -- -- Data Rate = 3.75 Gbps UI Pattern = CJPAT Jitter Frequency = 20 MHz > 0.1 -- -- -- -- -- -- Data Rate = 3.75 Gbps UI Pattern = CJPAT SDI Transmitter Jitter Generation (9) Alignment jitter (peak-to-peak) (c) February 2009 Data Rate = 1.485 Gbps (HD) Pattern = Color Bar Low-Frequency Roll-Off = 100 KHz 0.2 Data Rate = 2.97 Gbps (3G) Pattern = Color Bar Low-Frequency Roll-Off = 100 KHz 0.3 Altera Corporation -- -- 0.2 -- -- 0.2 -- -- UI -- -- 0.3 -- -- 0.3 -- -- UI Arria II GX Device Handbook Volume 3 1-22 Chapter 1: Arria II GX Device Data Sheet Switching Characteristics Table 1-21. Arria II GX Transceiver Block AC Specification--Preliminary (Note 1), (2) (Part 5 of 6) C4 Symbol/ Description C5 C6 Conditions Unit Min Typ Max Min Typ Max Min Typ Max SDI Receiver Jitter Tolerance (9) Jitter Frequency = 15 KHz >2 >2 >2 Data Rate = 2.97 Gbps (3G) Pattern = Single Line Scramble Color Bar Jitter Frequency = 100 KHz Sinusoidal jitter tolerance (peak-to-peak) UI > 0.3 > 0.3 > 0.3 Data Rate = 2.97 Gbps (3G) Pattern = Single Line Scramble Color Bar Jitter Frequency = 148.5 MHz UI > 0.3 > 0.3 > 0.3 Data Rate = 2.97 Gbps (3G) Pattern = Single Line Scramble Color Bar Arria II GX Device Handbook Volume 3 UI (c) February 2009 Altera Corporation Chapter 1: Arria II GX Device Data Sheet Switching Characteristics 1-23 Table 1-21. Arria II GX Transceiver Block AC Specification--Preliminary (Note 1), (2) (Part 6 of 6) C4 Symbol/ Description C5 C6 Conditions Unit Min Typ Max Min >1 Jitter Frequency = 20 KHz Typ Max Min >1 Typ Max >1 Data Rate = 1.485 Gbps (HD) Pattern = 75% Color Bar Sinusoidal Jitter Tolerance (peak-to-peak) UI Jitter Frequency = 100 KHz Data Rate = 1.485 Gbps (HD) Pattern = 75% Color Bar > 0.2 Jitter Frequency = 148.5 MHz > 0.2 > 0.2 > 0.2 UI > 0.2 > 0.2 Data Rate = 1.485 Gbps (HD) Pattern =75% Color Bar UI Notes to Table 1-21: (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) Dedicated refclk pins were used to drive the input reference clocks. The Jitter numbers specified are valid for the stated conditions only. The jitter numbers for Fibre Channel are compliant to the FC-PI-4 Specification revision 6.10. The jitter numbers for XAUI are compliant to the IEEE802.3ae-2002 Specification. The jitter numbers for PCI Express (PIPE) are compliant to the PCIe Base Specification 2.0. The jitter numbers for Serial RapidIO are compliant to the RapidIO Specification 1.3. The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification. The jitter numbers for HiGig are compliant to the IEEE802.3ae-2002 Specification. The HD-SDI and 3G-SDI jitter numbers are compliant to the SMPTE292M and SMPTE424M Specifications. The Fibre Channel transmitter jitter generation numbers are compliant to the specification at T inter operability point. The Fibre Channel receiver jitter tolerance numbers are compliant to the specification at R interpretability point. Core Performance Specifications for Arria II GX Devices This section describes the clock tree, phase-locked loop (PLL), digital signal processing (DSP), embedded memory, configuration, and JTAG specifications. Clock Tree Specifications Table 1-22 lists the clock tree specifications for Arria II GX devices. Table 1-22. Arria II GX Clock Tree Performance--Preliminary (Part 1 of 2) Performance (1) Device (c) February 2009 Unit C4 C5 C6 EP2AGX20 500 500 400 MHz EP2AGX30 500 500 400 MHz EP2AGX45 500 500 400 MHz EP2AGX65 500 500 400 MHz Altera Corporation Arria II GX Device Handbook Volume 3 1-24 Chapter 1: Arria II GX Device Data Sheet Switching Characteristics Table 1-22. Arria II GX Clock Tree Performance--Preliminary (Part 2 of 2) Performance (1) Device Unit C4 C5 C6 EP2AGX95 500 500 400 MHz EP2AGX125 500 500 400 MHz EP2AGX190 500 500 400 MHz EP2AGX260 500 500 400 MHz Note to Table 1-22: (1) The performance specifications are applicable to GCLK and RCLK networks. PLL Specifications Table 1-23 describes the PLL specifications for Arria II GX devices. Table 1-23. Arria II GX PLL Specifications--Preliminary (Part 1 of 2) Symbol Min Typ Max Unit Input clock frequency (from clock input pins residing in top/bottom banks) 5 -- 472.5 (1) MHz Input clock frequency (from clock input pins residing in right banks) 5 -- 500 MHz fINPF D Input frequency to the PFD 5 -- 325 MHz fVC O PLL VCO operating Range (2) 600 -- 1300 MHz fINDUTY Input clock duty cycle 40 -- 60 % fEINDUTY External feedback clock input duty cycle 40 -- 60 % tINCC J Input clock cycle to cycle jitter -- -- (4) ps fOUT Output frequency for internal global or regional clock -- -- 472.5 MHz fOUT_EXT Output frequency for external clock output -- -- 472.5 (3) MHz tOUTDUTY Duty cycle for external clock output (when set to 50%) 45 50 55 % tOUTPJ _DC Dedicated clock output period jitter -- -- (4) ps tOUTPJ _IO Regular I/O clock output period jitter -- -- (4) ps tFC OMP External feedback clock compensation time -- -- 10 ns tCONF IGPLL Time required to reconfigure PLL scan chains -- (4) -- SCANCLK cycles tCONF IGPHAS E Time required to reconfigure phase shift 1 -- 1 SCANCLK cycles fSC ANC LK SCANCLK frequency -- -- 100 MHz tLOCK Time required to lock from end of device configuration -- -- (4) ms tDLOCK Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) -- -- (4) ms PLL closed-loop low bandwidth range -- (4) -- MHz PLL closed-loop medium bandwidth range -- (4) -- MHz PLL closed-loop high bandwidth range -- (4) -- MHz Accuracy of PLL phase shift -- (4) -- ps fIN fCL B W tPLL_P SERR Description Arria II GX Device Handbook Volume 3 (c) February 2009 Altera Corporation Chapter 1: Arria II GX Device Data Sheet Switching Characteristics 1-25 Table 1-23. Arria II GX PLL Specifications--Preliminary (Part 2 of 2) Symbol Description tARES ET Minimum pulse width on areset signal Min Typ Max Unit 10 -- -- ns Notes to Table 1-23: (1) FIN is limited by I/O FMA X. (2) The VCO frequency reported by the Quartus II software in the PLL summary section of the compilation report takes into consideration the VCO post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification. (3) This specification is limited by the lower of the two: I/O Fma x or F out of the PLL. (4) Pending silicon characterization. DSP Block Specifications Table 1-24 describes the Arria II GX DSP block performance specifications. Table 1-24. Arria II GX DSP Block Performance Specifications--Preliminary (Note 1) Resources Used Performance Mode Unit 9 x 9-bit multiplier Number of Multipliers C4 C5 C6 1 315 245 200 MHz 12 x 12-bit multiplier 1 315 245 200 MHz 18 x 18-bit multiplier 1 350 275 225 MHz 36 x 36-bit multiplier 1 285 220 180 MHz 18 x 18-bit Multiply Accumulator 4 315 245 200 MHz 18 x 18-bit Multiply Adder 4 315 245 200 MHz 18 x 18-bit Multiply Adder-Signed Full Precision 2 315 245 200 MHz 18 x 18-bit Multiply Adder with loopback (2) 2 250 195 160 MHz 36-bit Shift (32-bit data) 1 285 220 180 MHz Double mode 1 285 220 180 MHz Notes to Table 1-24: (1) Maximum is for fully-pipelined block with Round and Saturation disabled. (2) Maximum is for non-pipelined block with loopback input registers disabled and Round and Saturation disabled. Embedded Memory Block Specifications Table 1-25 describes the Arria II GX embedded memory block specifications. Table 1-25. Arria II GX Embedded Memory Block Performance Specifications--Preliminary (Part 1 of 2) Resources Used Memory Memory Logic Array Block (MLAB) Mode Performance Unit ALUTs Embedded Memory C4 C5 C6 Single port 64 x 10 0 1 500 500 400 MHz Simple dual-port 32 x 20 single clock 0 1 500 500 400 MHz Simple dual-port 64 x 10 single clock 0 1 500 500 400 MHz (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 3 1-26 Chapter 1: Arria II GX Device Data Sheet Switching Characteristics Table 1-25. Arria II GX Embedded Memory Block Performance Specifications--Preliminary (Part 2 of 2) Resources Used Memory M9K Block Mode Performance Unit ALUTs Embedded Memory C4 C5 C6 Single-port 256 x 36 0 1 390 350 295 MHz Single-port 256 x 36, with the read-during-write option set to Old Data 0 1 250 225 190 MHz Simple dual-port 256 x 36 single CLK 0 1 390 350 295 MHz Single-port 256 x 36 single CLK, with the read-during-write option set to Old Data 0 1 250 225 190 MHz True dual port 512 x 18 single CLK 0 1 390 350 295 MHz True dual-port 512 x 18 single CLK, with the read-during-write option set to Old Data 0 1 250 225 190 MHz Configuration Table 1-26 lists the Arria II GX configuration mode specifications. Table 1-26. Arria II GX Configuration Mode Specifications--Preliminary Programming Mode DCLK FMAX Unit Passive Serial 125 MHz Fast Passive Parallel 125 MHz Fast Active Serial 40 MHz Remote Update only in Fast AS mode 10 MHz JTAG Specifications Table 1-27 lists the JTAG timing parameters and values for Arria II GX devices. Table 1-27. Arria II GX JTAG Timing Parameters and Values--Preliminary Symbol Description Min Max Unit tJC P TCK clock period 30 -- ns tJC H TCK clock high time 14 -- ns tJC L TCK clock low time 14 -- ns tJP SU (TDI) TDI JTAG port setup time 1 -- ns tJP SU (TMS ) TMS JTAG port setup time 3 -- ns tJP H JTAG port hold time 5 -- ns tJP CO JTAG port clock to output -- 11 (1) ns tJP ZX JTAG port high impedance to valid output -- 14 (1) ns tJP XZ JTAG port valid output to high impedance -- 14 (1) ns Note to Table 1-27: (1) A 1-ns adder is required for each VCC IO voltage step down from 3.3 V. For example, tJP CO = 12 ns if VCC IO of the TDO I/O bank = 2.5 V, or 13 ns if it equals to 1.8 V. Arria II GX Device Handbook Volume 3 (c) February 2009 Altera Corporation Chapter 1: Arria II GX Device Data Sheet Switching Characteristics 1-27 Periphery Performance This section describes periphery performance, including high-speed I/O and external memory interface. I/O performance supports several system interfacing, for example the high-speed I/O interface, external memory interface, and the PCI/PCI-X bus interface. I/O using SSTL-18 Class I termination standard can achieve up to the stated DDR2 SDRAM interfacing speed as indicated in Table 1-30 with typical DDR2 SDRAM memory interface setup. I/O using general-purpose I/O standards such as 3.0, 2.5, 1.8, or 1.5 LVTTL/LVCMOS are capable of typical 200 MHz interfacing frequency with 10pF load. 1 Actual achievable frequency depends on design- and system-specific factors. You should perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system. High-Speed I/O Specification Table 1-28 lists the high-speed I/O timing for Arria II GX devices. Table 1-28. High-Speed I/O Specifications C4 Symbol C5 C6 Conditions Unit Min Max Min Max Min Max Clock boost factor, W = 1 to 40 (1) 5 500 5 472.5 5 472.5 MHz fHSDR_TX (true differential output data rate) SERDES factor, J = 3 to 10 150 1000 (2) 150 840 150 740 Mbps fHSDR_TX_E3R (emulated differential 3R output data rate) SERDES factor, J = 3 to 10 (3) 640 (3) (4) (3) (4) Mbps DPA mode (5) 150 1000 150 840 150 740 Mbps Non-DPA mode (3) 945 (6) (3) 740 (3) 640 Mbps Clock fINCLK (input clock frequency) Transmitter Receiver fHSDR_RX Notes to Table 1-28: (1) fINCLK = fHS DR / W. Use W to determine the supported selection of input reference clock frequencies for the desired data rate. (2) This applies to interfacing with DPA receivers. For interfacing with non-DPA receivers, maximum supported data rate is 945 Mbps. Beyond 840 Mbps, PCB trace compensation is required. PCB trace compensation refers to the adjustment of PCB trace length for LVDS channels to improve channel-to-channel skews, and is optional when interfacing with DPA receivers. (3) The minimum specification is dependent on the clock source (for example, PLL and clock pin) and the clock routing resource you use (global, regional, or local). The I/O differential buffer and input register do not have a minimum toggle rate. (4) Pending silicon characterization. (5) Dedicated SERDES and DPA features are only available on right banks. (6) PCB trace compensation refers to the adjustment of PCB trace length for LVDS channels to improve channel-to-channel skews, and is required to support data rate beyond 840 Mbps. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 3 1-28 Chapter 1: Arria II GX Device Data Sheet Switching Characteristics Table 1-29 shows DPA lock time specifications for Arria II GX devices. Table 1-29. DPA Lock Time Specifications--Preliminary Training Pattern Transition Density Min Unit 00000000001111111111 10% 256 Number of repetitions 00001111 25% 256 Number of repetitions 10010000 50% 256 Number of repetitions 10101010 100% 256 Number of repetitions 01010101 -- 256 Number of repetitions Standard SPI-4 Parallel Rapid I/O Miscellaneous External Memory Interface Specifications Table 1-30 lists the maximum clock rate support for external memory interfaces with the half-rate controller for the Arria II GX device family. 1 Use Table 1-30 for memory interface timing analysis. Table 1-30. Arria II GX Maximum Clock Rate Support for External Memory Interfaces with Half-Rate Controller--Preliminary (Note 1), (2) Memory Standards C4 (MHz) C5 (MHz) C6 (MHz) DDR3 SDRAM (3) 300 N/A N/A DDR2 SDRAM (4) 300 (5) 267 (6) 200 DDR SDRAM (4) 200 200 200 QDRII SRAM (7), (8) 250 250 200 Notes to Table 1-30: (1) These numbers are preliminary until characterization is final. The supported operating frequencies listed here are memory interface maximums for the FPGA device family. Your design's actual achievable performance is based on design- and system-specific factors, as well as static timing analysis of the completed design. (2) The maximum clock rates are applicable to Class I termination for interfaces using either row I/Os or column I/Os. The maximum clock rates can be lower for Class II termination or interfaces using a combination of row and column I/Os. (3) Arria II GX devices support DDR3 SDRAM components only if no levelling support is required for DDR3 DIMMs. Interfaces with multiple DDR3 SDRAM components require component arrangement according to DDR2 DIMM tree topology. (4) This applies to interfaces with both components and single rank unbuffered modules. (5) The 300-MHz DDR2 interface requires the use of 400-MHz DDR2 SDRAM modules or components. (6) The 267-MHz DDR2 interface requires the use of 333-MHz DDR2 SDRAM modules or components. (7) QDRII SRAM supports 1.8-V and 1.5-V HSTL I/O standards. However, Altera recommends using the 1.8-V HSTL I/O standard for maximum performance because of the higher I/O drive strength. (8) Arria II GX devices feature I/Os capable of electrical support for QDRII. However, Altera does not currently supply a controller or PHY megafunction for QDRII interfaces. Arria II GX Device Handbook Volume 3 (c) February 2009 Altera Corporation Chapter 1: Arria II GX Device Data Sheet Switching Characteristics 1-29 DLL and DQS Logic Block Specifications Table 1-31 lists DLL frequency range specifications for Arria II GX devices. Table 1-31. Arria II GX DLL Frequency Range Specifications--Preliminary Frequency Range (MHz) Frequency Mode Resolution () C4 C5 C6 0 90 - 150 90 - 140 90 - 120 22.5 1 120 - 200 120 - 190 120 - 170 30 2 150 - 240 150 - 230 150 - 200 36 3 180 - 300 180 - 290 180 - 250 45 4 240 - 370 240 - 350 240 - 310 30 5 290 - 450 290 - 420 290 - 370 36 Table 1-32 lists the DQS phase offset delay per stage for Arria II GX devices. Table 1-32. DQS Phase Offset Delay Per Setting--Preliminary (Note 1), (2), (3) Speed Grade Min Max Unit C4 7.0 13.0 ps C5 (4) (4) ps C6 8.5 15.5 ps Notes to Table 1-32: (1) The valid settings for phase offset are -64 to +63 for frequency modes 0 to 3 and -32 to +31 for frequency modes 4 to 5. (2) The typical value equals the average of the minimum and maximum values. (3) Delay settings are linear. (4) Pending silicon characterization. Duty Cycle Distortion (DCD) Specifications Table 1-33 lists the worst-case DCD for Arria II GX devices. Table 1-33. Duty Cycle Distortion on Arria II GX I/O Pins--Preliminary (Note 1) C4 C5 C6 Symbol Output Duty Cycle Unit Min Max Min Max Min Max 45 55 45 55 45 55 % Note to Table 1-33: (1) Preliminary DCD specification applies to clock outputs from PLLs, global clock tree, and I/O elements (IOE) driving dedicated and general purpose I/O pins. (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 3 1-30 Chapter 1: Arria II GX Device Data Sheet Glossary Glossary Table 1-34 shows the glossary for this chapter. Table 1-34. Glossary Letter Subject Definitions A -- -- B -- -- C -- D Differential I/O Standards -- Receiver Input Waveforms Single-Ended Waveform Positive Channel (p) = VOH VOD Negative Channel (n) = VOL VCM Ground Differential Waveform VOD p-n=0V VOD Transmitter Output Waveforms Single-Ended Waveform Positive Channel (p) = VIH VID Negative Channel (n) = VIL VCM Ground Differential Waveform VID p-n=0V VID E F -- -- fHSCLK Left/Right PLL input clock frequency. fHSDR High-Speed I/O Block: Maximum/minimum LVDS data transfer rate (f HS DR = 1/TUI), non-DPA. fHSDRDPA High-Speed I/O Block: Maximum/minimum LVDS data transfer rate (f HS DRDPA = 1/TUI), DPA. Arria II GX Device Handbook Volume 3 (c) February 2009 Altera Corporation Chapter 1: Arria II GX Device Data Sheet Glossary 1-31 Table 1-34. Glossary (Continued) Letter Subject Definitions G -- -- H -- -- I -- -- J J High-Speed I/O Block: Deserialization factor (width of parallel data bus). JTAG Timing Specifications JTAG Timing Specifications are in the following figure: TMS TDI t JCP t JCH t JCL t JPH t JPSU TCK tJPZX t JPXZ t JPCO TDO K -- -- L -- -- M -- -- N -- -- O -- -- P PLL Specifications The block diagram shown in the following figure highlights the PLL Specification parameters: Diagram of PLL Specifications (1) CLKOUT Pins Switchover fOUT_EXT CLK fIN N fINPFD PFD CP LF VCO K fVCO Core Clock Counters C0..C9 fOUT GCLK RCLK M Key Reconfigurable in User Mode External Feedback Note: (1) CoreClock can only be fed by dedicated clock input pins or PLL outputs. Q R -- RL (c) February 2009 -- Receiver differential input discrete resistor (external to the Arria II GX device). Altera Corporation Arria II GX Device Handbook Volume 3 1-32 Chapter 1: Arria II GX Device Data Sheet Glossary Table 1-34. Glossary (Continued) Letter Subject Definitions S SW (sampling window) The period of time during which the data must be valid in order to capture it correctly. The setup and hold times determine the ideal strobe position within the sampling window: Timing Diagram Bit Time 0.5 x TCCS Single-ended Voltage Referenced I/O Standard RSKM Sampling Window (SW) RSKM 0.5 x TCCS The JEDEC standard for SSTL and HSTL I/O standards define both the AC and DC input signal values. The AC values indicate the voltage levels at which the receiver must meet its timing specifications. The DC values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. Once the receiver input has crossed the AC value, the receiver changes to the new logic state. The new logic state is then maintained as long as the input stays beyond the AC threshold. This approach is intended to provide predictable receiver timing in the presence of input waveform ringing: Single-Ended Voltage Referenced I/O Standard VCCIO VOH VIH (AC ) VIH(DC) VREF VIL(DC) VIL(AC ) VOL VSS T tC High-speed receiver and transmitter input and output clock period. TCCS (channel-tochannelskew) The timing difference between the fastest and slowest output edges, including tC O variation and clock skew, across channels driven by the same PLL. The clock is included in the TCCS measurement (refer to the Timing Diagram figure under S in this table). tDUTY High-speed I/O Block: Duty cycle on high-speed transmitter output clock. Timing Unit Interval (TUI) The timing budget allowed for skew, propagation delays, and data sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC /w) U tFALL Signal high-to-low transition time (80-20%) tINC CJ Cycle-to-cycle jitter tolerance on PLL clock input tOUTP J_IO Period jitter on general purpose I/O driven by a PLL tOUTP J_DC Period jitter on dedicated clock output driven by a PLL tRIS E Signal low-to-high transition time (20-80%) -- Arria II GX Device Handbook Volume 3 -- (c) February 2009 Altera Corporation Chapter 1: Arria II GX Device Data Sheet Document Revision History 1-33 Table 1-34. Glossary (Continued) Letter V W Subject Definitions VCM (DC ) DC Common Mode Input Voltage. VICM Input Common Mode Voltage: The common mode of the differential signal at the receiver. VID Input differential Voltage Swing: The difference in voltage between the positive and complementary conductors of a differential transmission at the receiver. VDIF(A C) AC differential Input Voltage: Minimum AC input differential voltage required for switching. VDIF(DC ) DC differential Input Voltage: Minimum DC input differential voltage required for switching. VIH Voltage Input High: The minimum positive voltage applied to the input which will be accepted by the device as a logic high. VIH(AC ) High-level AC input voltage VIH(DC) High-level DC input voltage VIL Voltage Input Low: The maximum positive voltage applied to the input which will be accepted by the device as a logic low. VIL(AC ) Low-level AC input voltage VIL(DC) Low-level DC input voltage VOCM Output Common Mode Voltage: The common mode of the differential signal at the transmitter. VOD Output differential Voltage Swing: The difference in voltage between the positive and complementary conductors of a differential transmission at the transmitter. W High-Speed I/O BLOCK: Clock Boost Factor X -- -- Y -- -- Z -- -- Document Revision History Table 1-35 shows the revision history for this chapter. Table 1-35. Document Revision History Date and Document Version February 2009, v1.0 (c) February 2009 Changes Made Initial release. Altera Corporation Summary of Changes -- Arria II GX Device Handbook Volume 3 1-34 Arria II GX Device Handbook Volume 3 Chapter 1: Arria II GX Device Data Sheet Document Revision History (c) February 2009 Altera Corporation Additional Information About this Handbook This handbook provides comprehensive information about the Altera Arria II GX family of devices. How to Contact Altera For the most up-to-date information about Altera products, see the following table. Contact (Note 1) Contact Method Address Technical support Website www.altera.com/support Technical training Website www.altera.com/training Email custrain@altera.com Altera literature services Email literature@altera.com Non-technical support (General) Email nacomp@altera.com (Software Licensing) Email authorization@altera.com Note: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions The following table shows the typographic conventions that this document uses. Visual Cue Meaning Bold Type with Initial Capital Letters Indicates command names and dialog box titles. For example, Save As dialog box. bold type Indicates directory names, project names, disk drive names, file names, file name extensions, dialog box options, software utility names, and other GUI labels. For example, \qdesigns directory, d: drive, and chiptrip.gdf file. Italic Type with Initial Capital Letters Indicates document titles. For example, AN 519: Stratix IV Design Guidelines. Italic type Indicates variables. For example, n + 1. Variable names are enclosed in angle brackets (< >). For example, <file name> and <project name>.pof file. Initial Capital Letters Indicates keyboard keys and menu names. For example, Delete key and the Options menu. "Subheading Title" Quotation marks indicate references to sections within a document and titles of Quartus II Help topics. For example, "Typographic Conventions." (c) February 2009 Altera Corporation Arria II GX Device Handbook Volume 3 Info-2 Additional Information Visual Cue Courier type Meaning Indicates signal, port, register, bit, block, and primitive names. For example, data1, tdi, and input. Active-low signals are denoted by suffix n. For example, resetn. Indicates command line commands and anything that must be typed exactly as it appears. For example, c:\qdesigns\tutorial\chiptrip.gdf. Also indicates sections of an actual file, such as a Report File, references to parts of files (for example, the AHDL keyword SUBDESIGN), and logic function names (for example, TRI). 1., 2., 3., and a., b., c., and so on. Numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure. Bullets indicate a list of items when the sequence of the items is not important. 1 The hand points to information that requires special attention. c A caution calls attention to a condition or possible situation that can damage or destroy the product or your work. w A warning calls attention to a condition or possible situation that can cause you injury. r The angled arrow instructs you to press Enter. f The feet direct you to more information about a particular topic. Arria II GX Device Handbook Volume 3 (c) February 2009 Altera Corporation Section I. Arria II GX Device Data Sheet This section provides information about the Arria (R) II GX device data sheet. This section includes the following chapters: Chapter 1, Arria II GX Device Data Sheet Revision History Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in this volume. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 3 I-2 Arria II GX Device Handbook Volume 3 Section I. Arria II GX Device Data Sheet (c) March 2009 Altera Corporation 1. Arria II GX Device Data Sheet AIIGX53001-1.1 Introduction This chapter describes the electrical and switching characteristics of the Arria(R) II GX device family. This chapter contains the following sections: "Electrical Characteristics" on page 1-1 "Switching Characteristics" on page 1-11 "Glossary" on page 1-30 Electrical Characteristics The following sections describe the electrical characteristics. Operating Conditions When Arria II GX devices are implemented in a system, they are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of Arria II GX devices, system designers must consider the following operating requirements: 1 Arria II GX devices are offered in both commercial and industrial grades. Commercial devices are offered in -4 (fastest), -5, and -6 (slowest) speed grades. Industrial device is only offered in -5 speed grade. In this chapter, a prefix associated with the operating temperature range is attached to the speed grades; commercial with the "C" prefix, and industrial with the "I" prefix. Commercial devices are therefore indicated as C4, C5, and C6 speed grade respectively, while the industrial device is indicated as I5. Absolute Maximum Ratings Absolute maximum ratings define the maximum operating conditions for Arria II GX devices. The values are based on experiments conducted with the device and theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied under these conditions. 1 (c) March 2009 Conditions beyond those listed in Table 1-1 may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device. Altera Corporation Arria II GX Device Handbook Volume 3 1-2 Chapter 1: Arria II GX Device Data Sheet Electrical Characteristics Table 1-1. Arria II GX Device Absolute Maximum Ratings Symbol Description Minimum Maximum Unit VC C Supplies power to the core, periphery, I/O registers, PCIe HIP block, and transceiver PCS -0.5 1.35 V VC CC B Supplies power to the configuration RAM bits -0.5 1.65 V VC CB AT Battery back-up power supply for design security volatile key register -0.5 3.75 V VC CP D Supplies power to the I/O pre-drivers, differential input buffers, and MSEL circuitry -0.5 3.75 V VC CIO Supplies power to the I/O banks -0.5 3.9 V VC CD_P LL Supplies power to the digital portions of the PLL -0.5 1.35 V VC CA _PLL Supplies power to the analog portions of the PLL and device-wide power management circuitry -0.5 3.75 V VI DC input voltage -0.5 4.0 V VC CA Supplies power to the transceiver PMA regulator -- 2.625 V VC CL_GXB Supplies power to the transceiver PMA TX, PMA RX, and clocking -- 1.21 V VC CH_GX B Supplies power to the transceiver PMA output (TX) buffer -- 1.54 V TJ Operating junction temperature -40 100 C TS TG Storage temperature (no bias) -65 150 C Maximum Allowed Overshoot and Undershoot Voltage During transitions, input signals may overshoot to the voltage shown in Table 1-2 and undershoot to -2.0 V for magnitude of currents less than 100 mA and periods shorter than 20 ns. Table 1-2 lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage over the device lifetime. The maximum allowed overshoot duration is specified as a percentage of high-time over the lifetime of the device. A DC signal is equivalent to 100% duty cycle. For example, a signal that overshoots to 4.3 V can only be at 4.3 V for 5.41% over the lifetime of the device: for a device lifetime of 10 years, this amounts to 5.41/10ths of a year. Arria II GX Device Handbook Volume 3 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Device Data Sheet Electrical Characteristics 1-3 Table 1-2. Maximum Allowed Overshoot During Transitions Symbol VI (AC) Description AC Input Voltage Condition Overshoot Duration as % of High Time Unit 4.0 V 100.000 % 4.05 V 79.330 % 4.1 V 46.270 % 4.15 V 27.030 % 4.2 V 15.800 % 4.25 V 9.240 % 4.3 V 5.410 % 4.35 V 3.160 % 4.4 V 1.850 % 4.45 V 1.080 % 4.5 V 0.630 % 4.55 V 0.370 % 4.6 V 0.220 % Maximum Allowed I/O Operating Frequency Table 1-3 defines the maximum allowed I/O operating frequency for I/Os using the specified I/O standards to ensure device reliability. Table 1-3. Maximum Allowed I/O Operating Frequency I/O Standard SSTL-18, SSTL -15 HSTL-18, HSTL-15 I/O Frequency (MHz) 300 3.3-V and 3.0-V LVTTL 3.3-V, 3.0-V, 2.5-V, 1.8-V, 1.5-V LVCMOS PCI and PCI-X 250 SSTL-2 1.2-V LVCMOS HSTL-12 200 Recommended Operating Conditions This section lists the functional operation limits for AC and DC parameters for Arria II GX devices. The steady-state voltage and current values expected from Arria II GX devices are provided in Table 1-4. All supplies are required to monotonically reach their full-rail values without plateaus within tRAMP . (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 3 1-4 Chapter 1: Arria II GX Device Data Sheet Electrical Characteristics Table 1-4 shows the recommended operating conditions for Arria II GX device. Table 1-4. Arria II GX Device Recommended Operating Conditions Symbol Description Condition Minimum Typical Maximum Unit VC C Supplies power to the core, periphery, I/O registers, PCIe HIP block, and transceiver PCS -- 0.87 0.90 0.93 V VC CC B Supplies power to the configuration RAM bits -- 1.425 1.50 1.575 V VCCBAT (2) Battery back-up power supply for design security volatile key registers -- 1.2 -- 3.3 V -- 3.135 3.3 3.465 V VCCPD Supplies power to the I/O pre-drivers, differential input buffers, and MSEL circuitry -- 2.85 3.0 3.15 V -- 2.375 2.5 2.625 V -- 3.135 3.3 3.465 V -- 2.85 3.0 3.15 V -- 2.375 2.5 2.625 V -- 1.71 1.8 1.89 V -- 1.425 1.5 1.575 V VCCIO Supplies power to the I/O banks (1) -- 1.14 1.2 1.26 V VC CD_P LL Supplies power to the digital portions of the PLL -- 0.87 0.90 0.93 V VC CA _PLL Supplies power to the analog portions of the PLL and device-wide power management circuitry -- 2.375 2.5 2.625 V VI DC Input voltage -- -0.5 -- 3.6 V VO Output voltage -- 0 -- VC CIO V VC CA Supplies power to the transceiver PMA regulator -- 2.375 2.5 2.625 V VC CL_GXB Supplies power to the transceiver PMA TX, PMA RX, and clocking -- 1.045 1.1 1.155 V VC CH_GX B Supplies power to the transceiver PMA output (TX) buffer -- 1.425 1.5 1.575 V TJ Operating junction temperature Commercial 0 -- 85 C tRAM P Power Supply Ramp time Industrial -40 -- 100 C Normal POR 0.05 -- 100 ms Fast POR 0.05 -- 4 ms Notes to Table 1-4: (1) VCCIO for 3C and 8C I/O banks where the configuration pins reside only supports 3.3-, 3.0-, 2.5-, or 1.8-V voltage levels. (2) Altera recommends a 3.0-V nominal battery voltage when connecting VCC BAT to a battery for volatile key backup. If you do not use the volatile security key, you may connect the VCC BAT to either GND or a 3.0-V power supply. DC Characteristics This section lists the supply current, I/O pin leakage current, on-chip termination (OCT) accuracy and variation, input pin capacitance, internal weak pull-up and pull-down resistance, hot socketing, and Schmitt trigger input specifications. Arria II GX Device Handbook Volume 3 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Device Data Sheet Electrical Characteristics 1-5 Supply Current Standby current is the current the device draws after the device is configured with no inputs or outputs toggling and no activity in the device. Since these currents vary largely with resources used, use the Excel-based Early Power Estimator (EPE) to get supply current estimates for your design. I/O Pin Leakage Current Table 1-5 defines the Arria II GX I/O pin leakage current specifications. Table 1-5. Arria II GX I/O Pin Leakage Current Symbol Description Conditions Min Typ Max Unit II Input pin VI = 0 V to VCCIOM AX -10 -- 10 A IOZ Tri-stated I/O pin VO = 0 V to VC CIOMA X -10 -- 10 A OCT Specifications Table 1-6 lists the Arria II GX series OCT with and without calibration accuracy. Table 1-6. OCT With and Without Calibration Specification for I/Os (Note 1) Calibration Accuracy Symbol Description Conditions Unit Commercial 25- RS 3.0/2.5 25- series OCT without calibration VC CIO = 3.0/2.5 V 30 % 50- RS 3.0/2.5 50- series COT without calibration VC CIO = 3.0/2.5 V 30 % 25- RS 1.8 25- series OCT without calibration VCC IO = 1.8 V 40 % 50- RS 1.8 50- series OCT without calibration VCC IO = 1.8 V 40 % 25- RS 1.5/1.2 25- series OCT without calibration VC CIO = 1.5/1.2 V 50 % 50- RS 1.5/1.2 50- series OCT without calibration VC CIO = 1.5/1.2 V 50 % 25- RS 3.0/2.5/1.8/ 1.5/1.2 25- series OCT with calibration VCC IO = 3.0/2.5/1.8/ 1.5/1.2 V 10 % 50- RS 3.0/2.5/1.8/ 1.5/1.2 50- series OCT with calibration VCC IO = 3.0/2.5/1.8/ 1.5/1.2 V 10 % Note to Table 1-6: (1) OCT with calibration accuracy is valid at the time of calibration only. OCT calibration is automatically performed at power-up for OCT-enabled I/Os. When voltage and temperature conditions change after calibration, the resistance may change. Use Equation 1-1 to determine the OCT variation when voltage and temperature vary after power-up calibration. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 3 1-6 Chapter 1: Arria II GX Device Data Sheet Electrical Characteristics Equation 1-1. OCT Variation (Note 1) dR dR R OCT = RCA L 1 + ------- x T + ------- x V dT dV Note to Equation 1-1: (1) RCAL is calibrated OCT at power up. T and V are variations in temperature and voltage with respect to temperature and VCCIO values, respectively, at power up. Table 1-7 lists OCT variation with temperature and voltage after power-up calibration. Table 1-7. OCT Variation after Power-up Calibration Nominal Voltage dR/dT (%/C) dR/dT(%/mV) 3.0 0.262 -0.026 2.5 0.234 -0.039 1.8 0.219 -0.086 1.5 0.199 -0.136 1.2 0.161 -0.288 Pin Capacitance Table 1-8 shows the Arria II GX device family pin capacitance. Table 1-8. Arria II GX Device Capacitance Symbol Description Typical Unit 7.5 pF CIODIFF Input capacitance on dual-purpose differential I/O pins CIOCLK Input capacitance on dual-purpose clock output/feedback pins and dedicated clock input pins 7 pF CIOOCT Input capacitance on dual-purpose RUP and RDN pins 7 pF Internal Weak Pull-Up and Weak Pull-Down Resistors Table 1-9 lists the Arria II GX devices weak pull-up and pull-down resistor values. Table 1-9. Arria II GX Internal Weak Pull-up and Weak Pull-Down Resistors (Part 1 of 2) (Note 1) Symbol RPU Description Value of I/O pin pull-up resistor before and during configuration, as well as user mode if the programmable pull-up resistor option is enabled. Arria II GX Device Handbook Volume 3 Conditions Min. Typ. Max. Unit VCC IO = 3.3 V 5% (2), (3) 7 25 41 k VCC IO = 3.0 V 5% (2), (3) 7 28 47 k VCC IO = 2.5 V 5% (2), (3) 8 35 61 k VCC IO = 1.8 V 5% (2), (3) 10 57 108 k VCC IO = 1.5 V 5% (2), (3) 13 82 163 k VCC IO = 1.2 V 5% (2), (3) 19 143 351 k (c) March 2009 Altera Corporation Chapter 1: Arria II GX Device Data Sheet Electrical Characteristics 1-7 Table 1-9. Arria II GX Internal Weak Pull-up and Weak Pull-Down Resistors (Part 2 of 2) (Note 1) Symbol RPD Description Value of TCK pin pull-down resistor Conditions Min. Typ. Max. Unit VC CIO = 3.3 V 5% (4) 6 19 29 k VC CIO = 3.0 V 5% (4) 6 22 32 k VC CIO = 2.5 V 5% (4) 6 25 42 k VC CIO = 1.8 V 5% (4) 7 35 70 k VC CIO = 1.5 V 5% (4) 8 50 112 k Notes to Table 1-9: (1) All I/O pins have an option to enable weak pull-up except configuration, test, and JTAG pins. The weak pull-down feature is only available for JTAG TCK. (2) Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO. (3) RPU = (VCCIO - VI)/IRPU. Minimum condition: -40C; VCCIO = VCC + 5%, V I = VCC + 5% - 50 mV. Typical condition: 25C; VCCIO = VCC, VI = 0 V. Maximum condition: 100C; VCCIO = VCC - 5%, VI = 0 V; in which VI refers to the voltage input at the I/O pin. (4) RPD = VI/I RPD. Minimum condition: -40C; VCCIO = VCC + 5%, VI = 50 mV. Typical condition: 25C; VCCIO = VCC, VI = VCC - 5%. Maximum condition: 100C; VCCIO = VCC - 5%, VI = VCC - 5%; in which V I refers to the voltage input at the I/O pin. Hot Socketing Table 1-10 defines the hot socketing specification for Arria II GX devices. Table 1-10. Arria II GX Hot Socketing Specifications Symbol Description Maximum IIIOPIN(DC) DC current per I/O pin 300 A IIOPIN(AC) AC current per I/O pin 8 mA (1) IXCVRTX(DC) DC current per transceiver TX pin 100 mA IXCVRRX(DC) DC current per transceiver RX pin 50 mA Note to Table 1-10: (1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which "C" is I/O pin capacitance and "dv/dt" is slew rate. Schmitt Trigger Input The Arria II GX device supports Schmitt trigger input on TDI, TMS, TCK, nSTATUS, nCONFIG, nCE, CONF_DONE, and DCLK pins. A Schmitt trigger introduces hysteresis to the input signal for improved noise immunity, especially for signals with slow edge rates. Table 1-11 lists the hysteresis specifications across the supported VCCIO range for Schmitt trigger inputs in Arria II GX devices. Table 1-11. Arria II GX Schmitt Trigger Input Hysteresis Specifications Symbol VSchmitt (c) March 2009 Description Hysteresis for Schmitt trigger input Altera Corporation Condition Minimum Unit VCCIO = 3.3 V 220 mV VCCIO = 2.5 V 180 mV VCCIO = 1.8 V 110 mV VCCIO = 1.5 V 70 mV Arria II GX Device Handbook Volume 3 1-8 Chapter 1: Arria II GX Device Data Sheet Electrical Characteristics I/O Standard Specifications Table 1-12 through Table 1-17 list input voltage (VIH and VIL), output voltage (VOH and VOL), and current drive characteristics (IOH and IOL) for various I/O standards supported by Arria II GX devices. They also show the Arria II GX device family I/O standard specifications. VOL and VOH values are valid at the corresponding IOH and IOL, respectively. 1 For an explanation of terms used in Table 1-12 through Table 1-17, refer to "Glossary" on page 1-30. Table 1-12 lists the Arria II GX single-ended I/O standards. Table 1-12. Single-Ended I/O Standards VCCIO (V) VIL (V) VIH (V) VO L (V) VOH (V) Min Typ Max Min Max Min Max Max Min IOL (mA) IOH (mA) 3.3 V LVTTL 3.135 3.3 3.465 -0.3 0.8 1.7 VCCIO + 0.3 0.4 2.4 2 -2 3.3 V LVCMOS 3.135 3.3 3.465 -0.3 0.8 1.7 VCCIO + 0.3 0.2 VCCIO - 0.2 0.1 -0.1 3.0 V LVTTL 2.85 3 3.15 -0.3 0.8 1.7 VCCIO + 0.3 0.4 2.4 2 -2 3.0 V LVCMOS 2.85 3 3.15 -0.3 0.8 1.7 VCCIO + 0.3 0.2 VCCIO - 0.2 0.1 -0.1 2.5 V LVCMOS 2.375 2.5 2.625 -0.3 0.7 1.7 VCCIO + 0.3 0.4 2 1 -1 1.8 V LVCMOS 1.71 1.8 1.89 -0.3 0.35 x VCC IO 0.65 x VCC IO VCC IO + 0.3 0.45 VCC IO - 0.45 2 -2 1.5 V LVCMOS 1.425 1.5 1.575 -0.3 0.35 x VCC IO 0.65 x VCC IO VCC IO + 0.3 0.25 * VCC IO 0.75 x VC CIO 2 -2 1.2 V LVCMOS 1.14 1.2 1.26 -0.3 0.35 x VCC IO 0.65 x VCC IO VCC IO + 0.3 0.25 * VCC IO 0.75 x VC CIO 2 -2 3.0-V PCI 2.85 3 3.15 -- 0.3 x VCC IO 0.5 x VCC IO 3.6 0.1 x VCC IO 0.9 x VCC IO 1.5 -0.5 3.0-V PCI-X 2.85 3 3.15 -- 0.35 x VCC IO 0.5 x VCC IO -- 0.1 x VCC IO 0.9 x VCC IO 1.5 -0.5 I/O Standard Table 1-13 lists the Arria II GX single-ended SSTL and HSTL I/O reference voltage specifications. Table 1-13. Single-Ended SSTL and HSTL I/O Reference Voltage Specifications (Part 1 of 2) VCC IO (V) VREF (V) VTT (V) I/O Standard Min Typ Max Min Typ Max Min Typ Max SSTL-2 Class I, II 2.375 2.5 2.625 0.49 x VC CIO 0.5 x VC CIO 0.51 x VCC IO VREF 0.04 VREF VREF + 0.04 SSTL-18 Class I, II 1.71 1.8 1.89 0.49 x VC CIO 0.5 x VC CIO 0.51 x VCC IO VREF 0.04 VREF VREF + 0.04 Arria II GX Device Handbook Volume 3 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Device Data Sheet Electrical Characteristics 1-9 Table 1-13. Single-Ended SSTL and HSTL I/O Reference Voltage Specifications (Part 2 of 2) VCC IO (V) VREF (V) VTT (V) I/O Standard Min Typ Max Min Typ Max Min Typ Max SSTL-15 Class I, II 1.425 1.5 1.575 0.49 x VC CIO 0.5 x VC CIO 0.51 x VCC IO VREF 0.04 VREF VREF + 0.04 HSTL-18 Class I, II 1.71 1.8 1.89 0.85 0.9 0.95 -- VC CIO/2 -- HSTL-15 Class I, II 1.425 1.5 1.575 0.68 0.75 0.9 -- VC CIO/2 -- HSTL-12 Class I, II 1.14 1.2 1.26 0.48 x VC CIO 0.5 x VC CIO 0.52 x VCC IO -- VC CIO/2 -- Table 1-14 lists the Arria II GX single-ended SSTL and HSTL I/O standard signal specifications. Table 1-14. Single-Ended SSTL and HSTL I/O Standard Signal Specifications VIL(DC ) (V) VIH (D C) (V) VIL (A C) (V) VIH (A C) (V) VO L (V) VOH (V) Iol (mA) Ioh (mA) VTT + 0.57 8.1 -8.1 VTT 0.76 VTT + 0.76 16.2 -16.2 VREF + 0.25 VTT 0.475 VTT + 0.475 6.7 -6.7 VREF -0.25 VREF + 0.25 0.28 VCC IO 0.28 13.4 -13.4 VCC IO + 0.3 VREF 0.175 VREF + 0.175 0.2 x VC CIO 0.8 x VC CIO 8 -8 VREF + 0.1 VCC IO + 0.3 VREF 0.175 VREF + 0.175 0.2 x VC CIO 0.8 x VC CIO 16 -16 VREF 0.1 VREF + 0.1 VCC IO + 0.3 VREF -0.2 VREF + 0.2 0.4 VCC IO 0.4 8 -8 -0.3 VREF 0.1 VREF + 0.1 VCC IO + 0.3 VREF -0.2 VREF + 0.2 0.4 VCC IO 0.4 16 -16 HSTL-15 Class I -0.3 VREF 0.1 VREF + 0.1 VCC IO + 0.3 VREF -0.2 VREF + 0.2 0.4 VCC IO 0.4 8 -8 HSTL-15 Class II -0.3 VREF 0.1 VREF + 0.1 VCC IO + 0.3 VREF -0.2 VREF + 0.2 0.4 VCC IO 0.4 16 -16 HSTL-12 Class I -0.15 VREF 0.08 VREF + 0.08 VCC IO + 0.15 VREF -0.15 VREF + 0.15 0.25 x VC CIO 0.75 x VC CIO 8 -8 HSTL-12 Class II -0.15 VREF 0.08 VREF + 0.08 VCC IO + 0.15 VREF -0.15 VREF + 0.15 0.25 x VC CIO 0.75 x VC CIO 16 -16 I/O Standard Min Max Min Max Max Min Max Min SSTL-2 Class I -0.3 VREF 0.15 VREF + 0.15 VCC IO + 0.3 VREF 0.31 VREF + 0.31 VTT 0.57 SSTL-2 Class II -0.3 VREF 0.15 VREF + 0.15 VCC IO + 0.3 VREF 0.31 VREF + 0.31 SSTL-18 Class I -0.3 VREF 0.125 VREF + 0.125 VCC IO + 0.3 VREF -0.25 SSTL-18 Class II -0.3 VREF 0.125 VREF + 0.125 VCC IO + 0.3 SSTL-15 Class I -0.3 VREF 0.1 VREF + 0.1 SSTL-15 Class II -0.3 VREF 0.1 HSTL-18 Class I -0.3 HSTL-18 Class II (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 3 1-10 Chapter 1: Arria II GX Device Data Sheet Electrical Characteristics Table 1-15 lists the Arria II GX differential SSTL I/O standards. Table 1-15. Differential SSTL I/O Standards VCC IO (V) VSWIN G(DC ) (V) VX(A C) (V) VSWIN G(AC ) (V) VOX (A C) (V) I/O Standard Min Typ Max Min Max Min Typ Max Min Max Min Typ Max SSTL-2 Class I, II 2.375 2.5 2.625 0.36 VC CIO VCC IO/2 - 0.2 -- VCCIO/2 + 0.2 0.7 VCC IO (1) -- (1) SSTL-18 Class I, II 1.71 1.8 1.89 0.25 VC CIO VCC IO/2 0.175 -- VCCIO/2 + 0.175 0.5 VCC IO (1) -- (1) SSTL-15 Class I, II 1.425 1.5 1.575 0.2 -- (1) -- (1) 0.35 -- (1) -- (1) Note to Table 1-15: (1) Pending silicon characterization. Table 1-16 lists the Arria II GX HSTL I/O standards. Table 1-16. Differential HSTL I/O Standards VCC IO (V) VDIF(DC) (V) VX (A C) (V) VC M(DC ) (V) VDIF(A C) (V) I/O Standard Min Typ 1.8 Max Min Max Min Typ Max Min Typ 1.89 0.2 -- 0.85 -- 0.95 0.88 -- 0.95 0.4 -- 0.79 0.4 -- 0.52 x VC CIO 0.3 -- HSTL-18 Class I 1.71 HSTL-15 Class I, II 1.425 1.5 1.575 0.2 -- 0.71 -- 0.79 0.71 -- HSTL-12 Class I, II 1.14 1.26 -- -- 0.5 x VC CIO -- 0.48 x VCC IO 0.5 x VC CIO 1.2 0.16 Max Min Max Table 1-17 lists the Arria II GX differential I/O standard specifications. Table 1-17. Differential I/O Standard Specifications I/O Standard VCCIO (V) Min Typ VTH (mV) Max Min Cond. VC M = 1.25 V VICM (V) (4) VOD (V) (1) Max Min Cond. Max -- 0.05 Dm ax <= 700 Mbps 1.80 -- 1.05 Dm ax > 700 Mbps 1.55 VOS (V) Min Typ Max Min Typ Max 0.247 -- 0.6 1.125 1.25 1.375 2.5V LVDS 2.375 RSDS (3) 2.375 2.5 2.625 -- -- -- -- -- -- 0.1 0.2 0.6 0.5 1.2 1.4 MiniLVDS (3) 2.375 2.5 2.625 -- -- -- -- -- -- 0.25 -- 0.6 1 1.2 1.4 0.6 Dm ax <= 700 Mbps 1.8 -- -- -- -- -- -- 1.0 Dm ax > 700 Mbps 1.6 LVPECL (2) 2.375 2.5 2.5 2.625 2.625 100 300 -- -- Notes to Table 1-17: (1) (2) (3) (4) RL range: 90 <= RL <= 110 . LVPECL input standard is supported at the dedicated clock input pins (GCLK) only. RSDS and mini-LVDS I/O standards are only supported for differential outputs. VIN range: 0 <= VIN <= 1.85 V. Arria II GX Device Handbook Volume 3 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Device Data Sheet Switching Characteristics 1-11 Power Consumption for Arria II GX Devices Altera(R) offers two ways to estimate power for a design: the Excel-based Early Power Estimator and the Quartus(R) II PowerPlay Power Analyzer feature. The interactive Excel-based Early Power Estimator is typically used prior to designing the FPGA in order to get a magnitude estimate of the device power. The Quartus II PowerPlay Power Analyzer provides better quality estimates based on the specifics of the design after place-and-route is complete. The PowerPlay Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities which, when combined with detailed circuit models, can yield very accurate power estimates. f For more information about power estimation tools, refer to the Early Power Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II Handbook. Switching Characteristics This section provides performance characteristics of the Arria II GX core and periphery blocks for commercial grade devices. These characteristics can be designated as Preliminary or Final. Preliminary characteristics are created using simulation results, process data, and other known parameters. Final characteristics are based on actual silicon characterization and testing. These numbers reflect the actual performance of the device under worst-case silicon process, voltage, and junction temperature conditions. 1 The table title shows the designations as "Preliminary" for each table with preliminary characteristics. Transceiver Performance Specifications Table 1-18 lists the Arria II GX transceiver specifications. Table 1-18. Arria II GX Transceiver Specification (Part 1 of 4)--Preliminary Symbol/ Description C4 C5 C6 Conditions Unit Min Typ Max Min Typ Max Min Typ Max Reference Clock Input frequency from REFCLK input pins -- 50 -- 622.08 50 -- 622.08 50 -- 622.08 MHz Input frequency from PLD input -- 50 -- 200 50 -- 200 50 -- 200 MHz Absolute VMAX for a REFCLK pin -- -- -- 2.2 -- -- 2.2 -- -- 2.2 V Absolute VMIN for a REFCLK pin -- -0.3 -- -- -0.3 -- -- -0.3 -- -- V Rise/fall time -- -- -- 0.2 -- -- 0.2 -- -- 0.2 UI Duty cycle -- 45 -- 55 45 -- 55 45 -- 55 % (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 3 1-12 Chapter 1: Arria II GX Device Data Sheet Switching Characteristics Table 1-18. Arria II GX Transceiver Specification (Part 2 of 4)--Preliminary Symbol/ Description C4 C5 C6 Conditions Peak-to-peak differential input voltage -- Unit Min Typ Max Min Typ Max Min Typ Max 200 -- 2000 200 -- 2000 200 -- 2000 mV -- 33 30 -- 33 30 -- 33 kHz -- -- -- -- Spread-spectrum modulating clock frequency PCI Express 30 Spread-spectrum downspread PCI Express -- On-chip termination resistors 0 to -0.5% 0 to -0.5% 0 to -0.5% -- -- -- 100 -- -- 100 -- -- 100 -- -- -- 1200 -- -- 1200 -- -- 1200 -- mV 250 -- 550 250 -- 550 250 -- 550 mV -- 2000 1% -- -- 2000 1% -- -- 2000 1% -- 10 -- 125 10 -- 125 10 -- 125 MHz -- 125 -- -- 125 -- -- 125 -- MHz -- -- 1 -- -- 1 -- -- 1 -- s Data rate -- 600 -- 3750 600 -- 3125 600 -- 3125 Mbps Absolute VM AX for a receiver pin (1) -- -- -- 1.5 -- -- 1.5 -- -- 1.5 V Absolute VM IN for a receiver pin -- -0.4 -- -- -0.4 -- -- -0.4 -- -- V VICM = 0.82 V setting -- -- 2.7 -- -- 2.7 -- -- 2.7 V VICM =1.1 V setting (7) -- -- 1.6 -- -- 1.6 -- -- 1.6 V Data Rate = 600 Mbps to 3.75 Gbps. 100 -- -- 100 -- -- 100 -- -- mV VICM (AC coupled) VICM (DC coupled) Rref HCSL I/O standard for PCI Express reference clock -- -- Transceiver Clocks Calibration block clock frequency fixedclk clock frequency Transceiver block minimum power-down pulse width -- PCI Express Receiver Detect Receiver Maximum peak-to-peak differential input voltage VID (diff p-p) Minimum peak-to-peak differential input voltage VID (diff p-p) Arria II GX Device Handbook Volume 3 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Device Data Sheet Switching Characteristics 1-13 Table 1-18. Arria II GX Transceiver Specification (Part 3 of 4)--Preliminary Symbol/ Description C4 C5 C6 Conditions Unit Min Typ Max Min Typ Max Min Typ Max VICM = 0.82 V setting -- 820 -- -- 820 -- -- 820 -- mV VICM =1.1 V setting (7) -- 1100 -- -- 1100 -- -- 1100 -- mV Differential on-chip termination resistors 100- setting -- 100 -- -- 100 -- -- 100 -- Return loss differential mode PCI Express 50 MHz to 1.25 GHz: -10dB XAUI 100 MHz to 2.5 GHz: -10dB Return loss common mode PCI Express 50 MHz to 1.25 GHz: -6dB VICM XAUI 100 MHz to 2.5 GHz: -6dB 62.5, 100, 125, 200, Programmable PPM detector (2) -- Run length -- -- 80 -- -- 80 -- -- 80 -- UI Programmable equalization -- -- -- 7 -- -- 7 -- -- 7 dB 65 -- 175 65 -- 175 65 -- 175 mV 75 -- -- 75 -- -- 75 s 15 -- -- 15 -- -- s Signal detect/loss threshold PCI Express (PIPE) Mode ppm 250, 300, 500, 1000 CDR LTR time (3) -- -- -- CDR minimum T1b (4) -- 15 -- LTD lock time (5) -- 0 100 4000 0 100 4000 0 100 4000 ns Data lock time from rx_freqlocked (6) -- -- -- 4000 -- -- 4000 -- -- 4000 ns DC Gain Setting = 0 -- 0 -- -- 0 -- -- 0 -- dB DC Gain Setting = 1 -- 3 -- -- 3 -- -- 3 -- dB DC Gain Setting = 2 -- 6 -- -- 6 -- -- 6 -- dB -- -- -- -- -- -- -- -- -- Mbps Programmable DC gain Transmitter Data rate VOC M 0.65 V setting -- 650 -- -- 650 -- -- 650 -- mV Differential on-chip termination resistors 100- setting -- 100 -- -- 100 -- -- 100 -- 200 ps Return loss differential mode Return loss common mode PCI Express 312 MHz to 625 MHz: -10dB 625 MHz to 3.125 GHz: -10dB/decade slope XAUI PCI Express Rise time (c) March 2009 50 MHz to 1.25 GHz: -10dB -- Altera Corporation 50 MHz to 1.25 GHz: -6dB 50 -- 200 50 -- 200 50 -- Arria II GX Device Handbook Volume 3 1-14 Chapter 1: Arria II GX Device Data Sheet Switching Characteristics Table 1-18. Arria II GX Transceiver Specification (Part 4 of 4)--Preliminary Symbol/ Description C4 C5 C6 Conditions Unit Min Typ Max Min Typ Max Min Typ Max Fall time -- 50 -- 200 50 -- 200 50 -- 200 ps Intra-differential pair skew -- -- -- 15 -- -- 15 -- -- 15 ps Intra-transceiver block skew PCI Express (PIPE) x4 -- -- 120 -- -- 120 -- -- 120 ps Inter-transceiver block skew PCI Express (PIPE) x8 -- -- 300 -- -- 300 -- -- 300 ps -- -- -- 100 -- -- 100 -- -- 100 s Interface speed -- 25 -- 200 25 -- 160 25 -- 130 MHz Digital reset pulse width -- CMU PLL0 and CMU PLL1 CMU PLL lock time from CMUPLL_reset deassertion PLD-Transceiver Interface Minimum is 2 parallel clock cycles Notes to Table 1-18: (1) (2) (3) (4) The device cannot tolerate prolonged operation at this absolute maximum. The rate matcher supports only up to +/-300 parts per million (ppm). Time taken to rx_pll_locked goes high from rx_analogreset deassertion. Refer to Figure 1-1. Time for which the CDR must be kept in lock-to-reference mode after rx_pll_locked goes high and before rx_locktodata is asserted in manual mode. Refer to Figure 1-1. (5) Time taken to recover valid data after the rx_locktodata signal is asserted in manual mode. Refer to Figure 1-1. (6) Time taken to recover valid data after the rx_freqlocked signal goes high in automatic mode. Refer to Figure 1-2. (7) The 1.1-V RX VIC M setting must be used if the input serial data standard is LVDS and the link is DC-coupled. Arria II GX Device Handbook Volume 3 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Device Data Sheet Switching Characteristics 1-15 Figure 1-1 shows the lock time parameters in manual mode. 1 LTD = lock-to-data. LTR = lock-to-reference. Figure 1-1. Lock Time Parameters for Manual Mode r x_analogreset CDR status LTR LTD r x_pll_locked r x_locktodata Invalid Data Valid data r x_dataout CDR LTR Time LTD lock time CDR Minimum T1b Figure 1-2 shows the lock time parameters in automatic mode. Figure 1-2. Lock Time Parameters for Automatic Mode CDR status LTR LTD r x_freqlocked r x_dataout Invalid Valid data data Data lock time from rx_freqlocked (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 3 1-16 Chapter 1: Arria II GX Device Data Sheet Switching Characteristics Figure 1-3 shows the differential receiver input waveform. Figure 1-3. Receiver Input Waveform Single-Ended Waveform Positive Channel (p) VID Negative Channel (n) VCM Ground Differential Waveform VID (diff peak-peak) = 2 x VID (single-ended) VID p-n=0V VID Figure 1-4 shows the transmitter output waveform. Figure 1-4. Transmitter Output Waveform--Preliminary Single-Ended Waveform Positive Channel (p) VOD Negative Channel (n) VCM Ground Differential Waveform VOD (diff peak-peak) = 2 x VOD (single-ended) VOD p-n=0V VOD Table 1-19 shows the typical VOD for TX term that equals 100 . . Table 1-19. Typical VOD Setting, TX Term = 100 --Preliminary VO D Setting (mV) Symbol VOD Typical (mV) 200 400 600 700 800 900 1000 1200 200 400 600 700 800 900 1000 1200 Arria II GX Device Handbook Volume 3 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Device Data Sheet Switching Characteristics 1-17 Table 1-20 shows the typical VOD for TX term that equals 150 . Table 1-20. Typical VOD Setting, TX Term = 150 --Preliminary VO D Setting (mV) Symbol VOD Typical (mV) 300 600 900 1050 1200 300 600 900 1050 1200 Table 1-21 shows the Arria II GX transceiver block AC specifications. Table 1-21. Arria II GX Transceiver Block AC Specification (Note 1), (2) (Part 1 of 6)--Preliminary C4 Symbol/ Description C5 C6 Conditions Unit Min Typ Max Min Typ Max Min Typ Max SONET/SDH Receiver Jitter Tolerance Jitter frequency = 0.03 KHz > 15 > 15 > 15 UI > 1.5 > 1.5 > 1.5 UI > 0.15 > 0.15 > 0.15 UI > 15 > 15 > 15 UI > 1.5 > 1.5 > 1.5 UI > 0.15 > 0.15 > 0.15 UI > 0.15 > 0.15 > 0.15 UI Pattern = PRBS23 Jitter tolerance at 622.08 Mbps Jitter frequency = 25 KHZ Pattern = PRBS23 Jitter frequency = 250 KHz Pattern = PRBS23 Jitter frequency = 0.06 KHz Pattern = PRBS23 Jitter frequency = 100 KHZ Jitter tolerance at 2488.32 Mbps Pattern = PRBS23 Jitter frequency = 1 MHz Pattern = PRBS23 Jitter frequency = 10 MHz Pattern = PRBS23 Fibre Channel Transmit Jitter Generation (3), (10) Total jitter FC-1 Pattern = CRPAT -- -- 0.23 -- -- 0.23 -- -- 0.23 UI Deterministic jitter FC-1 Pattern = CRPAT -- -- 0.11 -- -- 0.11 -- -- 0.11 UI Total jitter FC-2 Pattern = CRPAT -- -- 0.33 -- -- 0.33 -- -- 0.33 UI Deterministic jitter FC-2 Pattern = CRPAT -- -- 0.2 -- -- 0.2 -- -- 0.2 UI Fibre Channel Receiver Jitter Tolerance (3), (11) Deterministic jitter FC-1 Pattern = CJTPAT > 0.37 > 0.37 > 0.37 UI Random jitter FC-1 Pattern = CJTPAT > 0.31 > 0.31 > 0.31 UI (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 3 1-18 Chapter 1: Arria II GX Device Data Sheet Switching Characteristics Table 1-21. Arria II GX Transceiver Block AC Specification (Note 1), (2) (Part 2 of 6)--Preliminary C4 Symbol/ Description Sinusoidal jitter FC-1 C5 C6 Conditions Unit Min Typ Max Min Typ Max Min Typ Max Fc/25000 > 1.5 > 1.5 > 1.5 UI Fc/1667 > 0.1 > 0.1 > 0.1 UI Deterministic jitter FC-2 Pattern = CJTPAT > 0.33 > 0.33 > 0.33 UI Random jitter FC-2 Pattern = CJTPAT > 0.29 > 0.29 > 0.29 UI Fc/25000 > 1.5 > 1.5 > 1.5 UI Fc/1667 > 0.1 > 0.1 > 0.1 UI Sinusoidal jitter FC-2 XAUI Transmit Jitter Generation (4) Total jitter at 3.125 Gbps Pattern = CJPAT -- -- 0.3 -- -- 0.3 -- -- 0.3 UI Deterministic jitter at 3.125 Gbps Pattern = CJPAT -- -- 0.17 -- -- 0.17 -- -- 0.17 UI XAUI Receiver Jitter Tolerance (4) Total jitter > 0.65 > 0.65 > 0.65 UI Deterministic jitter > 0.37 > 0.37 > 0.37 UI Peak-to-peak jitter Jitter frequency = 22.1 KHz > 8.5 > 8.5 > 8.5 UI Peak-to-peak jitter Jitter frequency = 1.875 MHz > 0.1 > 0.1 > 0.1 UI Peak-to-peak jitter Jitter frequency = 20 MHz > 0.1 > 0.1 > 0.1 UI PCI Express Transmit Jitter Generation (5) Total jitter at 2.5 Gbps (Gen1) Compliance pattern -- -- 0.25 -- -- 0.25 -- -- 0.25 UI PCI Express Receiver Jitter Tolerance (5) Total jitter at 2.5 Gbps (Gen1) Compliance pattern > 0.6 > 0.6 > 0.6 UI Serial RapidIO Transmit Jitter Generation (6) Deterministic jitter (peak-to-peak) Total jitter (peak-to-peak) Data Rate = 1.25, 2.5, 3.125 Gbps -- -- 0.17 -- -- 0.17 -- -- 0.17 UI -- -- 0.35 -- -- 0.35 -- -- 0.35 UI Pattern = CJPAT Data Rate = 1.25, 2.5, 3.125 Gbps Pattern = CJPAT Serial RapidIO Receiver Jitter Tolerance (6) Deterministic jitter tolerance (peak-to-peak) Combined deterministic and random jitter tolerance (peak-to-peak) Data Rate = 1.25, 2.5, 3.125 Gbps > 0.37 > 0.37 > 0.37 UI > 0.55 > 0.55 > 0.55 UI Pattern = CJPAT Data Rate = 1.25, 2.5, 3.125 Gbps Pattern = CJPAT Arria II GX Device Handbook Volume 3 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Device Data Sheet Switching Characteristics 1-19 Table 1-21. Arria II GX Transceiver Block AC Specification (Note 1), (2) (Part 3 of 6)--Preliminary C4 Symbol/ Description C5 C6 Conditions Unit Min Jitter Frequency = 22.1 KHz Data Rate = 1.25, 2.5, 3.125 Gbps Typ Max Min Typ Max Min Typ Max > 8.5 > 8.5 > 8.5 UI > 0.1 > 0.1 > 0.1 UI > 0.1 > 0.1 > 0.1 UI Pattern = CJPAT Jitter Frequency = 1.875 MHz Sinusoidal jitter tolerance (peak-to-peak) Data Rate = 1.25, 2.5, 3.125 Gbps Pattern = CJPAT Jitter Frequency = 20 MHz Data Rate = 1.25, 2.5, 3.125 Gbps Pattern = CJPAT GIGE Transmit Jitter Generation (7) Deterministic jitter (peak-to-peak) Total jitter (peak-to-peak) Pattern = CRPAT -- -- 0.14 -- -- 0.14 -- -- 0.14 UI Pattern = CRPAT -- -- 0.279 -- -- 0.279 -- -- 0.279 UI GIGE Receiver Jitter Tolerance (7) Deterministic jitter tolerance (peak-to-peak) Pattern = CJPAT > 0.4 > 0.4 > 0.4 UI Combined deterministic and random jitter tolerance (peak-to-peak) Pattern = CJPAT > 0.66 > 0.66 > 0.66 UI HiGig Transmit Jitter Generation (8) Deterministic jitter (peak-to-peak) Total jitter (peak-to-peak) Data Rate = 3.75 Gbps -- -- 0.17 -- -- -- -- -- -- UI -- -- 0.35 -- -- -- -- -- -- UI > 0.37 -- -- -- -- -- -- UI > 0.65 -- -- -- -- -- -- UI Pattern = CJPAT Data Rate = 3.75 Gbps Pattern = CJPAT HiGig Receiver Jitter Tolerance (8) Deterministic jitter tolerance (peak-to-peak) Combined deterministic and random jitter tolerance (peak-to-peak) (c) March 2009 Data Rate = 3.75 Gbps Pattern = CJPAT Data Rate = 3.75 Gbps Pattern = CJPAT Altera Corporation Arria II GX Device Handbook Volume 3 1-20 Chapter 1: Arria II GX Device Data Sheet Switching Characteristics Table 1-21. Arria II GX Transceiver Block AC Specification (Note 1), (2) (Part 4 of 6)--Preliminary C4 Symbol/ Description C5 C6 Conditions Unit Min Typ Max Min Typ Max Min Typ Max > 8.5 -- -- -- -- -- -- UI > 0.1 -- -- -- -- -- -- UI > 0.1 -- -- -- -- -- -- UI Jitter Frequency = 22.1 KHz Data Rate = 3.75 Gbps Pattern = CJPAT Jitter Frequency = 1.875MHz Sinusoidal jitter tolerance (peak-to-peak) Data Rate = 3.75 Gbps Pattern = CJPAT Jitter Frequency = 20 MHz Data Rate = 3.75 Gbps Pattern = CJPAT SDI Transmitter Jitter Generation (9) Alignment jitter (peak-to-peak) Data Rate = 1.485 Gbps (HD) Pattern = Color Bar Low-Frequency Roll-Off = 100 KHz 0.2 -- -- 0.2 -- -- 0.2 -- -- UI Data Rate = 2.97 Gbps (3G) Pattern = Color Bar Low-Frequency Roll-Off = 100 KHz 0.3 -- -- 0.3 -- -- 0.3 -- -- UI Arria II GX Device Handbook Volume 3 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Device Data Sheet Switching Characteristics 1-21 Table 1-21. Arria II GX Transceiver Block AC Specification (Note 1), (2) (Part 5 of 6)--Preliminary C4 Symbol/ Description C5 C6 Conditions Unit Min Typ Max Min Typ Max Min Typ Max SDI Receiver Jitter Tolerance (9) Jitter Frequency = 15 KHz Data Rate = 2.97 Gbps (3G) Pattern = Single Line Scramble Color Bar >2 >2 >2 UI > 0.3 > 0.3 > 0.3 UI > 0.3 > 0.3 > 0.3 UI Jitter Frequency = 100 KHz Sinusoidal jitter tolerance (peak-to-peak) Data Rate = 2.97 Gbps (3G) Pattern = Single Line Scramble Color Bar Jitter Frequency = 148.5 MHz Data Rate = 2.97 Gbps (3G) Pattern = Single Line Scramble Color Bar (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 3 1-22 Chapter 1: Arria II GX Device Data Sheet Switching Characteristics Table 1-21. Arria II GX Transceiver Block AC Specification (Note 1), (2) (Part 6 of 6)--Preliminary C4 Symbol/ Description C5 C6 Conditions Unit Min Typ Max Min Typ Max Min Typ Max Jitter Frequency = 20 KHz Data Rate = 1.485 Gbps (HD) Pattern = 75% Color Bar Sinusoidal Jitter Tolerance (peak-to-peak) Jitter Frequency = 100 KHz Data Rate = 1.485 Gbps (HD) Pattern = 75% Color Bar >1 >1 >1 UI > 0.2 > 0.2 > 0.2 UI > 0.2 > 0.2 > 0.2 UI Jitter Frequency = 148.5 MHz Data Rate = 1.485 Gbps (HD) Pattern =75% Color Bar Notes to Table 1-21: (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) Dedicated refclk pins were used to drive the input reference clocks. The Jitter numbers specified are valid for the stated conditions only. The jitter numbers for Fibre Channel are compliant to the FC-PI-4 Specification revision 6.10. The jitter numbers for XAUI are compliant to the IEEE802.3ae-2002 Specification. The jitter numbers for PCI Express (PIPE) are compliant to the PCIe Base Specification 2.0. The jitter numbers for Serial RapidIO are compliant to the RapidIO Specification 1.3. The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification. The jitter numbers for HiGig are compliant to the IEEE802.3ae-2002 Specification. The HD-SDI and 3G-SDI jitter numbers are compliant to the SMPTE292M and SMPTE424M Specifications. The Fibre Channel transmitter jitter generation numbers are compliant to the specification at T inter operability point. The Fibre Channel receiver jitter tolerance numbers are compliant to the specification at R interpretability point. Core Performance Specifications for Arria II GX Devices This section describes the clock tree, phase-locked loop (PLL), digital signal processing (DSP), embedded memory, configuration, and JTAG specifications. Clock Tree Specifications Table 1-22 lists the clock tree specifications for Arria II GX devices. Table 1-22. Arria II GX Clock Tree Performance (Part 1 of 2)--Preliminary Performance (1) Device Unit C4 C5 C6 EP2AGX20 500 500 400 MHz EP2AGX30 500 500 400 MHz EP2AGX45 500 500 400 MHz EP2AGX65 500 500 400 MHz Arria II GX Device Handbook Volume 3 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Device Data Sheet Switching Characteristics 1-23 Table 1-22. Arria II GX Clock Tree Performance (Part 2 of 2)--Preliminary Performance (1) Device Unit C4 C5 C6 EP2AGX95 500 500 400 MHz EP2AGX125 500 500 400 MHz EP2AGX190 500 500 400 MHz EP2AGX260 500 500 400 MHz Note to Table 1-22: (1) The performance specifications are applicable to GCLK and RCLK networks. PLL Specifications Table 1-23 describes the PLL specifications for Arria II GX devices. Table 1-23. Arria II GX PLL Specifications (Part 1 of 2)--Preliminary Symbol Min Typ Max Unit Input clock frequency (from clock input pins residing in top/bottom banks) 5 -- 472.5 (1) MHz Input clock frequency (from clock input pins residing in right banks) 5 -- 500 MHz fINPF D Input frequency to the PFD 5 -- 325 MHz fVC O PLL VCO operating Range (2) 600 -- 1300 MHz fINDUTY Input clock duty cycle 40 -- 60 % fEINDUTY External feedback clock input duty cycle 40 -- 60 % tINCC J Input clock cycle to cycle jitter -- -- (4) ps fOUT Output frequency for internal global or regional clock -- -- 472.5 MHz fIN Description fOUT_EXT Output frequency for external clock output -- -- 472.5 (3) MHz tOUTDUTY Duty cycle for external clock output (when set to 50%) 45 50 55 % tOUTPJ _DC Dedicated clock output period jitter -- -- (4) ps tOUTPJ _IO Regular I/O clock output period jitter -- -- (4) ps tFC OMP External feedback clock compensation time -- -- 10 ns tCONF IGPLL Time required to reconfigure PLL scan chains -- (4) -- SCANCLK cycles tCONF IGPHAS E Time required to reconfigure phase shift 1 -- 1 SCANCLK cycles fSC ANC LK SCANCLK frequency -- -- 100 MHz tLOCK Time required to lock from end of device configuration -- -- (4) ms tDLOCK Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) -- -- (4) ms PLL closed-loop low bandwidth range -- (4) -- MHz PLL closed-loop medium bandwidth range -- (4) -- MHz PLL closed-loop high bandwidth range -- (4) -- MHz Accuracy of PLL phase shift -- (4) -- ps fCL B W tPLL_P SERR (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 3 1-24 Chapter 1: Arria II GX Device Data Sheet Switching Characteristics Table 1-23. Arria II GX PLL Specifications (Part 2 of 2)--Preliminary Symbol Description tARES ET Minimum pulse width on areset signal Min Typ Max Unit 10 -- -- ns Notes to Table 1-23: (1) FIN is limited by I/O FMA X. (2) The VCO frequency reported by the Quartus II software in the PLL summary section of the compilation report takes into consideration the VCO post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification. (3) This specification is limited by the lower of the two: I/O Fma x or F out of the PLL. (4) Pending silicon characterization. DSP Block Specifications Table 1-24 describes the Arria II GX DSP block performance specifications. Table 1-24. Arria II GX DSP Block Performance Specifications (Note 1) --Preliminary Resources Used Performance Mode Unit Number of Multipliers C4 C5 C6 9 x 9-bit multiplier 1 315 245 200 MHz 12 x 12-bit multiplier 1 315 245 200 MHz 18 x 18-bit multiplier 1 350 275 225 MHz 36 x 36-bit multiplier 1 285 220 180 MHz 18 x 18-bit Multiply Accumulator 4 315 245 200 MHz 18 x 18-bit Multiply Adder 4 315 245 200 MHz 18 x 18-bit Multiply Adder-Signed Full Precision 2 315 245 200 MHz 18 x 18-bit Multiply Adder with loopback (2) 2 250 195 160 MHz 36-bit Shift (32-bit data) 1 285 220 180 MHz Double mode 1 285 220 180 MHz Notes to Table 1-24: (1) Maximum is for fully-pipelined block with Round and Saturation disabled. (2) Maximum is for non-pipelined block with loopback input registers disabled and Round and Saturation disabled. Embedded Memory Block Specifications Table 1-25 describes the Arria II GX embedded memory block specifications. Table 1-25. Arria II GX Embedded Memory Block Performance Specifications (Part 1 of 2)--Preliminary Resources Used Memory Memory Logic Array Block (MLAB) Mode Performance Unit ALUTs Embedded Memory C4 C5 C6 Single port 64 x 10 0 1 500 500 400 MHz Simple dual-port 32 x 20 single clock 0 1 500 500 400 MHz Simple dual-port 64 x 10 single clock 0 1 500 500 400 MHz Arria II GX Device Handbook Volume 3 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Device Data Sheet Switching Characteristics 1-25 Table 1-25. Arria II GX Embedded Memory Block Performance Specifications (Part 2 of 2)--Preliminary Resources Used Memory M9K Block Mode Performance Unit ALUTs Embedded Memory C4 C5 C6 Single-port 256 x 36 0 1 390 350 295 MHz Single-port 256 x 36, with the read-during-write option set to Old Data 0 1 250 225 190 MHz Simple dual-port 256 x 36 single CLK 0 1 390 350 295 MHz Single-port 256 x 36 single CLK, with the read-during-write option set to Old Data 0 1 250 225 190 MHz True dual port 512 x 18 single CLK 0 1 390 350 295 MHz True dual-port 512 x 18 single CLK, with the read-during-write option set to Old Data 0 1 250 225 190 MHz Configuration Table 1-26 lists the Arria II GX configuration mode specifications. Table 1-26. Arria II GX Configuration Mode Specifications--Preliminary DCLK FMAX Unit Passive Serial 125 MHz Fast Passive Parallel 125 MHz Fast Active Serial 40 MHz Remote Update only in Fast AS mode 10 MHz Programming Mode JTAG Specifications Table 1-27 lists the JTAG timing parameters and values for Arria II GX devices. Table 1-27. Arria II GX JTAG Timing Parameters and Values--Preliminary Symbol Description Min Max Unit tJC P TCK clock period 30 -- ns tJC H TCK clock high time 14 -- ns tJC L TCK clock low time 14 -- ns tJP SU (TDI) TDI JTAG port setup time 1 -- ns tJP SU (TMS ) TMS JTAG port setup time 3 -- ns tJP H JTAG port hold time 5 -- ns tJP CO JTAG port clock to output -- 11 (1) ns tJP ZX JTAG port high impedance to valid output -- 14 (1) ns tJP XZ JTAG port valid output to high impedance -- 14 (1) ns Note to Table 1-27: (1) A 1-ns adder is required for each VCC IO voltage step down from 3.3 V. For example, tJP CO = 12 ns if VCC IO of the TDO I/O bank = 2.5 V, or 13 ns if it equals to 1.8 V. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 3 1-26 Chapter 1: Arria II GX Device Data Sheet Switching Characteristics Periphery Performance This section describes periphery performance, including high-speed I/O and external memory interface. I/O performance supports several system interfacing, for example the high-speed I/O interface, external memory interface, and the PCI/PCI-X bus interface. I/O using SSTL-18 Class I termination standard can achieve up to the stated DDR2 SDRAM interfacing speed as indicated in Table 1-30 with typical DDR2 SDRAM memory interface setup. I/O using general-purpose I/O standards such as 3.0, 2.5, 1.8, or 1.5 LVTTL/LVCMOS are capable of typical 200 MHz interfacing frequency with 10pF load. 1 Actual achievable frequency depends on design- and system-specific factors. You should perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system. High-Speed I/O Specification Table 1-28 lists the high-speed I/O timing for Arria II GX devices. Table 1-28. High-Speed I/O Specifications C4 Symbol C5 C6 Conditions Unit Min Max Min Max Min Max Clock boost factor, W = 1 to 40 (1) 5 500 5 472.5 5 472.5 MHz fHSDR_TX (true differential output data rate) SERDES factor, J = 3 to 10 150 1000 (2) 150 840 150 740 Mbps fHSDR_TX_E3R (emulated differential 3R output data rate) SERDES factor, J = 3 to 10 (3) 640 (3) (4) (3) (4) Mbps DPA mode (5) 150 1000 150 840 150 740 Mbps Non-DPA mode (3) 945 (6) (3) 740 (3) 640 Mbps Clock fINCLK (input clock frequency) Transmitter Receiver fHSDR_RX Notes to Table 1-28: (1) fINCLK = fHS DR / W. Use W to determine the supported selection of input reference clock frequencies for the desired data rate. (2) This applies to interfacing with DPA receivers. For interfacing with non-DPA receivers, maximum supported data rate is 945 Mbps. Beyond 840 Mbps, PCB trace compensation is required. PCB trace compensation refers to the adjustment of PCB trace length for LVDS channels to improve channel-to-channel skews, and is optional when interfacing with DPA receivers. (3) The minimum specification is dependent on the clock source (for example, PLL and clock pin) and the clock routing resource you use (global, regional, or local). The I/O differential buffer and input register do not have a minimum toggle rate. (4) Pending silicon characterization. (5) Dedicated SERDES and DPA features are only available on right banks. (6) PCB trace compensation refers to the adjustment of PCB trace length for LVDS channels to improve channel-to-channel skews, and is required to support data rate beyond 840 Mbps. Arria II GX Device Handbook Volume 3 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Device Data Sheet Switching Characteristics 1-27 Table 1-29 shows DPA lock time specifications for Arria II GX devices. Table 1-29. DPA Lock Time Specifications--Preliminary Standard SPI-4 Parallel Rapid I/O Miscellaneous Training Pattern Transition Density Min Unit 00000000001111111111 10% 256 Number of repetitions 00001111 25% 256 Number of repetitions 10010000 50% 256 Number of repetitions 10101010 100% 256 Number of repetitions 01010101 -- 256 Number of repetitions External Memory Interface Specifications Table 1-30 lists the maximum clock rate support for external memory interfaces with the half-rate controller for the Arria II GX device family. 1 Use Table 1-30 for memory interface timing analysis. Table 1-30. Arria II GX Maximum Clock Rate Support for External Memory Interfaces with Half-Rate Controller (Note 1), (2)--Preliminary Memory Standards C4 (MHz) C5 (MHz) C6 (MHz) DDR3 SDRAM (3) 300 N/A N/A DDR2 SDRAM (4) 300 (5) 267 (6) 200 DDR SDRAM (4) 200 200 200 QDRII SRAM (7), (8) 250 250 200 Notes to Table 1-30: (1) These numbers are preliminary until characterization is final. The supported operating frequencies listed here are memory interface maximums for the FPGA device family. Your design's actual achievable performance is based on design- and system-specific factors, as well as static timing analysis of the completed design. (2) The maximum clock rates are applicable to Class I termination for interfaces using either row I/Os or column I/Os. The maximum clock rates can be lower for Class II termination or interfaces using a combination of row and column I/Os. (3) Arria II GX devices support DDR3 SDRAM components only if no levelling support is required for DDR3 DIMMs. Interfaces with multiple DDR3 SDRAM components require component arrangement according to DDR2 DIMM tree topology. (4) This applies to interfaces with both components and single rank unbuffered modules. (5) The 300-MHz DDR2 interface requires the use of 400-MHz DDR2 SDRAM modules or components. (6) The 267-MHz DDR2 interface requires the use of 333-MHz DDR2 SDRAM modules or components. (7) QDRII SRAM supports 1.8-V and 1.5-V HSTL I/O standards. However, Altera recommends using the 1.8-V HSTL I/O standard for maximum performance because of the higher I/O drive strength. (8) Arria II GX devices feature I/Os capable of electrical support for QDRII. However, Altera does not currently supply a controller or PHY megafunction for QDRII interfaces. (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 3 1-28 Chapter 1: Arria II GX Device Data Sheet Switching Characteristics DLL and DQS Logic Block Specifications Table 1-31 lists DLL frequency range specifications for Arria II GX devices. Table 1-31. Arria II GX DLL Frequency Range Specifications--Preliminary Frequency Range (MHz) Frequency Mode Resolution () C4 C5 C6 0 90 - 150 90 - 140 90 - 120 22.5 1 120 - 200 120 - 190 120 - 170 30 2 150 - 240 150 - 230 150 - 200 36 3 180 - 300 180 - 290 180 - 250 45 4 240 - 370 240 - 350 240 - 310 30 5 290 - 450 290 - 420 290 - 370 36 Table 1-32 lists the DQS phase offset delay per stage for Arria II GX devices. Table 1-32. DQS Phase Offset Delay Per Setting (Note 1), (2), (3)--Preliminary Speed Grade Min Max Unit C4 7.0 13.0 ps C5 (4) (4) ps C6 8.5 15.5 ps Notes to Table 1-32: (1) The valid settings for phase offset are -64 to +63 for frequency modes 0 to 3 and -32 to +31 for frequency modes 4 to 5. (2) The typical value equals the average of the minimum and maximum values. (3) Delay settings are linear. (4) Pending silicon characterization. Duty Cycle Distortion (DCD) Specifications Table 1-33 lists the worst-case DCD for Arria II GX devices. Table 1-33. Duty Cycle Distortion on Arria II GX I/O Pins (Note 1) --Preliminary C4 C5 C6 Symbol Output Duty Cycle Unit Min Max Min Max Min Max 45 55 45 55 45 55 % Note to Table 1-33: (1) Preliminary DCD specification applies to clock outputs from PLLs, global clock tree, and I/O elements (IOE) driving dedicated and general purpose I/O pins. Arria II GX Device Handbook Volume 3 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Device Data Sheet I/O Timing 1-29 I/O Timing Altera offers two ways to determine I/O timing: the Excel-based I/O Timing and the Quartus II Timing Analyzer. The Excel-based I/O Timing provides pin timing performance for each device density and speed grade. The data is typically used prior to designing the FPGA to get an estimate of the timing budget as part of the link timing analysis. The Quartus II Timing Analyzer provides a more accurate and precise I/O timing data based on the specifics of the design after place-and-route is complete. f (c) March 2009 Altera Corporation The Excel-based I/O Timing spreadsheet is downloadable from Arria II GX Devices Literature webpage. Arria II GX Device Handbook Volume 3 1-30 Chapter 1: Arria II GX Device Data Sheet Glossary Glossary Table 1-34 shows the glossary for this chapter. Table 1-34. Glossary (Part 1 of 4) Letter Subject Definitions A -- -- B -- -- C -- -- Receiver Input Waveforms Single-Ended Waveform Positive Channel (p) = VOH VOD Negative Channel (n) = VOL VCM Ground Differential Waveform VOD p-n=0V VOD D Differential I/O Standards Transmitter Output Waveforms Single-Ended Waveform Positive Channel (p) = VIH VID Negative Channel (n) = VIL VCM Ground Differential Waveform VID p-n=0V VID E F -- -- fHSCLK Left/Right PLL input clock frequency. fHSDR High-Speed I/O Block: Maximum/minimum LVDS data transfer rate (f HS DR = 1/TUI), non-DPA. fHSDRDPA High-Speed I/O Block: Maximum/minimum LVDS data transfer rate (f HS DRDPA = 1/TUI), DPA. Arria II GX Device Handbook Volume 3 (c) March 2009 Altera Corporation Chapter 1: Arria II GX Device Data Sheet Glossary 1-31 Table 1-34. Glossary (Part 2 of 4) Letter Subject Definitions G -- -- H -- -- I -- -- J High-Speed I/O Block: Deserialization factor (width of parallel data bus). JTAG Timing Specifications are in the following figure: TMS TDI J t JCP JTAG Timing Specifications t JCH t JCL t JPH t JPSU TCK tJPZX t JPXZ t JPCO TDO K -- -- L -- -- M -- -- N -- -- O -- -- The block diagram shown in the following figure highlights the PLL Specification parameters: Diagram of PLL Specifications (1) CLKOUT Pins Switchover fOUT_EXT CLK fIN P PLL Specifications N fINPFD PFD CP LF VCO K fVCO Core Clock Counters C0..C9 fOUT GCLK RCLK M Key Reconfigurable in User Mode External Feedback Note: (1) CoreClock can only be fed by dedicated clock input pins or PLL outputs. Q R -- RL (c) March 2009 -- Receiver differential input discrete resistor (external to the Arria II GX device). Altera Corporation Arria II GX Device Handbook Volume 3 1-32 Chapter 1: Arria II GX Device Data Sheet Glossary Table 1-34. Glossary (Part 3 of 4) Letter Subject Definitions The period of time during which the data must be valid in order to capture it correctly. The setup and hold times determine the ideal strobe position within the sampling window: Timing Diagram SW (sampling window) Bit Time 0.5 x TCCS RSKM Sampling Window (SW) RSKM 0.5 x TCCS The JEDEC standard for SSTL and HSTL I/O standards define both the AC and DC input signal values. The AC values indicate the voltage levels at which the receiver must meet its timing specifications. The DC values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. Once the receiver input has crossed the AC value, the receiver changes to the new logic state. The new logic state is then maintained as long as the input stays beyond the AC threshold. This approach is intended to provide predictable receiver timing in the presence of input waveform ringing: S Single-Ended Voltage Referenced I/O Standard Single-ended Voltage Referenced I/O Standard VCCIO VOH VIH (AC ) VIH(DC) VREF VIL(DC) VIL(AC ) VOL VSS tC High-speed receiver and transmitter input and output clock period. TCCS (channel-tochannelskew) The timing difference between the fastest and slowest output edges, including tC O variation and clock skew, across channels driven by the same PLL. The clock is included in the TCCS measurement (refer to the Timing Diagram figure under S in this table). High-speed I/O Block: Duty cycle on high-speed transmitter output clock. T U Timing Unit Interval (TUI) tDUTY The timing budget allowed for skew, propagation delays, and data sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC /w) tFALL Signal high-to-low transition time (80-20%) tINC CJ Cycle-to-cycle jitter tolerance on PLL clock input tOUTP J_IO Period jitter on general purpose I/O driven by a PLL tOUTP J_DC Period jitter on dedicated clock output driven by a PLL tRIS E Signal low-to-high transition time (20-80%) -- Arria II GX Device Handbook Volume 3 -- (c) March 2009 Altera Corporation Chapter 1: Arria II GX Device Data Sheet Document Revision History 1-33 Table 1-34. Glossary (Part 4 of 4) Letter V W Subject Definitions VCM (DC ) DC Common Mode Input Voltage. VICM Input Common Mode Voltage: The common mode of the differential signal at the receiver. VID Input differential Voltage Swing: The difference in voltage between the positive and complementary conductors of a differential transmission at the receiver. VDIF(A C) AC differential Input Voltage: Minimum AC input differential voltage required for switching. VDIF(DC ) DC differential Input Voltage: Minimum DC input differential voltage required for switching. VIH Voltage Input High: The minimum positive voltage applied to the input which will be accepted by the device as a logic high. VIH(AC ) High-level AC input voltage VIH(DC) High-level DC input voltage VIL Voltage Input Low: The maximum positive voltage applied to the input which will be accepted by the device as a logic low. VIL(AC ) Low-level AC input voltage VIL(DC) Low-level DC input voltage VOCM Output Common Mode Voltage: The common mode of the differential signal at the transmitter. VOD Output differential Voltage Swing: The difference in voltage between the positive and complementary conductors of a differential transmission at the transmitter. W High-Speed I/O BLOCK: Clock Boost Factor X -- -- Y -- -- Z -- -- Document Revision History Table 1-35 shows the revision history for this chapter. Table 1-35. Document Revision History Date and Document Version Changes Made Summary of Changes March 2009, v1.1 Added "I/O Timing" section. -- February 2009, v1.0 Initial release. -- (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 3 1-34 Arria II GX Device Handbook Volume 3 Chapter 1: Arria II GX Device Data Sheet Document Revision History (c) March 2009 Altera Corporation Additional Information About this Handbook This handbook provides comprehensive information about the Altera Arria II GX family of devices. How to Contact Altera For the most up-to-date information about Altera products, see the following table. Contact (Note 1) Contact Method Address Technical support Website www.altera.com/support Technical training Website www.altera.com/training Email custrain@altera.com Altera literature services Email literature@altera.com Non-technical support (General) Email nacomp@altera.com (Software Licensing) Email authorization@altera.com Note: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions The following table shows the typographic conventions that this document uses. Visual Cue Meaning Bold Type with Initial Capital Letters Indicates command names and dialog box titles. For example, Save As dialog box. bold type Indicates directory names, project names, disk drive names, file names, file name extensions, dialog box options, software utility names, and other GUI labels. For example, \qdesigns directory, d: drive, and chiptrip.gdf file. Italic Type with Initial Capital Letters Indicates document titles. For example, AN 519: Stratix IV Design Guidelines. Italic type Indicates variables. For example, n + 1. Variable names are enclosed in angle brackets (< >). For example, <file name> and <project name>.pof file. Initial Capital Letters Indicates keyboard keys and menu names. For example, Delete key and the Options menu. "Subheading Title" Quotation marks indicate references to sections within a document and titles of Quartus II Help topics. For example, "Typographic Conventions." (c) March 2009 Altera Corporation Arria II GX Device Handbook Volume 3 Info-2 Additional Information Visual Cue Courier type Meaning Indicates signal, port, register, bit, block, and primitive names. For example, data1, tdi, and input. Active-low signals are denoted by suffix n. For example, resetn. Indicates command line commands and anything that must be typed exactly as it appears. For example, c:\qdesigns\tutorial\chiptrip.gdf. Also indicates sections of an actual file, such as a Report File, references to parts of files (for example, the AHDL keyword SUBDESIGN), and logic function names (for example, TRI). 1., 2., 3., and a., b., c., and so on. Numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure. Bullets indicate a list of items when the sequence of the items is not important. 1 The hand points to information that requires special attention. c A caution calls attention to a condition or possible situation that can damage or destroy the product or your work. w A warning calls attention to a condition or possible situation that can cause you injury. r The angled arrow instructs you to press Enter. f The feet direct you to more information about a particular topic. Arria II GX Device Handbook Volume 3 (c) March 2009 Altera Corporation