Nuvoton
Bus Termination Regulator
W83312SN
W83312SN
Publication Date: Mar., 2010
-I- Revision A5
-Table of Content-
1. .............................................................................................................. 1 GENERAL DESCRIPTION
2. ...................................................................................................................................... 1 FEATURES
3. ........................................................................................................................... 2 BLOCK DIAGRAM
4. .................................................. 2 PIN CONFIGURATION AND TYPICAL APPLICATION CIRCUIT
5. .......................................................................................................................... 3 PIN DESCRIPTION
6. ........................................................................................................ 4 FUNCTIONAL DESCRIPTION
7. .................................................................................................. 7 ELECTRICAL CHARACTERISTIC
8. ........................................................................................... 9 TYPICAL OPERATING WAVEFORMS
9. ................................................................................................................ 22 PACKAGE DIMENSION
10. .......................................................................................................... 23 ORDERING INFORMATION
11. ................................................................................................. 23 TOP MARKING SPECIFICATION
12. ..................................................................................................................... 24 REVISION HISTORY
W83312SN
Publication Date: Mar., 2010
-1- Revision A5
1. GENERAL DESCRIPTION
The W83312SN is a linear regulator which provides a power achieves peak 3.0Amp bi-
directional sinking and sourcing capability for a high speed bus terminator application. The
chip simply implements a stable power supply which tracks half of input power
dynamically for bus terminator with a single chip. The W83312SN is promoted with small
footprint 8-SOP 150mil power package. With W83312SN design, a high integration, high
performance, and cost-effective solution are promoted.
2. FEATURES
2.1. General
z Memory Termination Regulator for DDR1, DDR2, DDR3 and Low Power DDR3
z Sink and Source 3A Peak Current
z Integrated Power MOSFET
z Adjustable VOUT by External Resistors
z Low External Component Count
z Low Output Voltage Offset
z Current Limit Protection
z Over Temperature Protection
z -40°C to 85°C Ambient Operating Temperature Range
2.2. Package
z SOP-8 150mil with Exposed Pad Package
z Lead Free (ROHS Compliant) and Halogen Free
2.3. Applications
z Desktop PCs, Notebooks, and Workstations
z Graphics Card Memory Termination
z Set Top Boxes, Digital TVs and Printers
z Active Termination Buses
z DDR1, DDR2 and DDR3 Memory Systems
W83312SN
3. BLOCK DIAGRAM
Publication Date: Mar., 2010
-2- Revision A5
4. PIN CONFIGURATION AND TYPICAL APPLICATION CIRCUIT
Current Limit
Protection
Thermal
Shutdown
Control
Logic
VREF
VCNTL VIN
VOUT
GND
VIN
GND
VREF
VOUT
NC
NC
1
2
3
4
8
7
6
5
VCNTL
NC
W83312SN
(Top View)
W83312SN
Publication Date: Mar., 2010
-3- Revision A5
Typical Application Circuits
R1 CIN
CCNTL
COUT
CSS
R2
Enable
VCNTL VIN
VREF
VOUT
GND
VCNTL=3.3V/5V VDDQ=2.5V/1.8V/1.5V
VTT = VDDQ x R2 / (R1+R2)
5. PIN DESCRIPTION
SYMBOL PIN I/O FUNCTION
VIN 1 I
Main power input pin which supplies current to output pin.
For lower power dissipation consideration, using VDDQ
(Supply voltage for DRAM) as power source is
recommended.
VREF 3 I
Internal reference voltage source. Generally, VREF tracks
VDDQ/2 for DDR application.
Using voltage dividing resistors and capacitor as low pass
filter for noise immunity and output voltage soft start is
recommended.
If using an N-MOSFET as shutdown function, please make
sure the sinking current capability can pull down VREF under
0.2V.
VOUT 4 O Voltage output pin which is regulated to track VREF voltage.
VCNTL 6 I
Power for internal control logic circuitry. A ceramic
decoupling capacitor with 1uF is required.
GND 2 Ground. Connect to negative terminal of the output capacitor.
NC 5, 7, 8 No connection.
W83312SN
6. FUNCTIONAL DESCRIPTION
6.1 VTT Sink/Source Regulator
The W83312SN is a sink/source tracking Double Data Rate (DDR) termination regulator
specifically designed for low input voltage, low cost and low external component count
systems where space is a key application parameter. The W83312SN integrates a high
performance, low dropout linear regulator that is capable of both sinking and sourcing current.
6.2 General Regulator
The W83312SN could also serves as a general linear regulator. The W83312SN accepts an
external reference voltage at VREF pin and provides output voltage regulated to this reference
voltage as shown in Fig.6-1, where
VOUT=VEXT x R2/ (R1+R2)
Fig. 6-1
The W83312SN supports wide VREF voltage input range, making it versatile and idea for
many types of low power LDO applications. The dropout voltage is the input voltage minus
output voltage that produces 2% decrease in output voltage, where
VINMIN =VDROPOUT + VOUT
The output voltage range depends on VCNTL voltage and output loading which means higher
VCNTL voltage can support higher output voltage and higher output loading.
Fig.6-2 and Table 6-1 show that the relationships among VOUT, VDROPOUT and IOUT when
VCNTL=5V. For example, if VOUT=3.4V, the maximum output loading is 1.5A with 0.25V
dropout voltage and the minimum VIN is 3.65V. The Max column in the table means the
minimum dropout voltage needed in worst conditions. Choose suitable VIN voltage to obtain
better efficiency.
R1 CIN
VEXT
VIN
VCNTL=3.3V/5V
GND
VOUT
VREF
VIN VCNTL
R2 CSS
COUT
CCNTL
VOUT = VEXT x R2 / (R1+R2)
VCNTL=5V
Parameter Conditions Typ. Max Unit
IOUT=1A, 0.6V≦ VOUT ≦3.4V 0.15 0.3
IOUT=1.5A, 0.6V≦ VOUT ≦3.4V 0.25 0.5
IOUT=2A, 0.6V≦ VOUT ≦3.2V 0.35 0.7
Dropout
Voltage
IOUT=2.5A, 0,8V≦ VOUT ≦3V 0.5 1
V
Publication Date: Mar., 2010
-4- Revision A5
W83312SN
VOUT vs. Dropout Voltage, VCNTL=5V
0
0.1
0.2
0.3
0.4
0.5
0.6
0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4
VOUT (V)
Dropout Voltage (V)
IOUT=1A IOUT=1.5A
IOUT=2A IOUT=2.5A
Table 6-1
Fig.6-3 and Table 6-2 show that the relationships among VOUT, VDROPOUT and IOUT when
VCNTL=3.3V.
Fig. 6-2
VOUT vs. Dropout Voltage, VCNTL=3.3V
0
0.1
0.2
0.3
0.4
0.5
0.6
0.6 0.8 1 1.2 1.4 1.6 1.8
VOUT (V)
Dropout Voltage (V)
IOUT=1A IOUT=1.5 A
IOUT=2A IOUT=2.5 A
VCNTL=3.3V
Parameter Conditions Typ. Max Unit
IOUT=1A, 0.6V≦ VOUT ≦1.8V 0.35 0.7
IOUT=1.5A, 0.6V≦ VOUT ≦1.6V 0.35 0.7
IOUT=2A, 0.6V≦ VOUT≦ 1.6V 0.6 1.2
Dropout
Voltage
IOUT=2.5A, 0.8V≦ VOUT≦ 1.4V 0.45 0.9
V
Table 6-2
Fi
g
. 6-3
6.3 Shutdown Function
When the external reference voltage at VREF pin is under shutdown threshold, the internal
regulator will be turned off and VOUT is at High-Z state.
6.4 Over Current Protection
The W83312SN provides a current limit circuitry, which monitors the output current and
controls NMOS’s gate voltage to limit the output current at 3.5A, typically.
6.5 Over Temperature Protection
The W83312SN monitors its junction temperature. If the device junction temperature exceeds
its threshold value, typically 165°C, the VOUT is shut off. The shutdown is a non-latch
protection.
6.6 Thermal Design
Since the W83312SN is a linear regulator, the VOUT current flows in both source and sink
directions, thereby dissipating power from the device. When the device is sourcing current, the
Publication Date: Mar., 2010
-5- Revision A5
W83312SN
Publication Date: Mar., 2010
-6- Revision A5
voltage difference between VIN and VOUT times IOUT current becomes the power dissipation
as shown in below equation.
PDISS_SOURCE = (VIN-VOUT) x IOUT_SOURCE
In this case, if VIN is connected to an alternative power supply lower than the VDDQ voltage,
overall power loss can be reduced. For the sink phase, VOUT voltage is applied across the
internal LDO regulator and the power dissipation, PDISS_SINK can be calculated by below
equation.
PDISS_SINK = VOUT x IOUT_SINK
Because the device does not sink and source current at the same time and the IOUT current
may vary rapidly with time, the actual power dissipation should be the time average of the
above dissipations over the thermal relaxation duration of the system. Another source of
power consumption is the current used for the internal current control circuitry form VCNTL
supply and the VIN supply. This can be estimate as 10mW or less during normal operating
conditions. The power must be effectively dissipated from the package.
Maximum power dissipation allowed by the package is calculated by below equation.
PPKG = [ TJ(MAX) – TA(MAX)] / θJA
, where
z TJ(MAX) is +125°C
z TA(MAX) is the maximum ambient temperature in the system
z θJA is the thermal resistance form junction to ambient
6.7 Input Capacitor
Depending on the trace impedance between the VIN bulk power supply to the device, a
transient increase of source current is supplied mostly by the charge from the VIN input
capacitor. Use a 100uF (or greater) capacitor to supply this transient charge. Provide more
input capacitance as more output capacitance is used at VOUT.
6.8 Output Capacitor
For stable operation, the total capacitance of the VOUT terminal must be greater than 100uF.
Attach two or more capacitors in parallel to minimize the effect of equivalent series resistance
(ESR) and equivalent series inductance (ESL).
6.9 Layout Consideration
Consider the following points before starting the W83312SN layout design. Fig. 6-4 shows the
suggestion of minimum land pattern. Fig. 6-5 shows the recommended PCB layout. Using
“dog bone” copper patterns on the top layer can increase efficiency of heat dissipating.
z The input bypass capacitor for VIN should be placed as close as possible to the pin with
short and wide connections.
z The output capacitor for VOUT should be placed close to the pin with short and wide
connection in order to avoid ESR and/or ESL trace inductance.
z In order to effectively remove heat from the package, properly prepare the thermal land.
Apply solder directly to the package’s thermal pad. The wide traces of component and the
side copper connected to the thermal land pad help to dissipate heat. The thermal land
connected to the ground plane could also be used to help dissipation.
W83312SN
Publication Date: Mar., 2010
-7- Revision A5
7. ELECTRICAL CHARACTERISTIC
7.1 Absolute Maximum Ratings (Note1)
ITEM SYMBOL RATING UNIT
Input Voltage VIN -0.3 to 7 V
Control Logic Input Voltage VCNTL -0.3 to 7 V
Reference Voltage VREF -0.3 to 5 V
Human Body Mode ±2 kV
Machine Mode ±200 V
Electrostatic discharge protection (Note2)
Latch-Up ±100 mA
Storage Temperature Range -65 to 150 °C
7.2 Thermal Information
ITEM RATING UNIT
Power Dissipation, PD @ TA=25°C Internal Limited W
Package Thermal Resistance, ESOP8, θJA 75 °C/W
7.3 Recommended Operating Conditions
ITEM SYMBOL MIN MAX UNIT
VIN 1.2 5.5
VCNTL 3 5.5
V
Input Voltage
VREF 0.6 3.3 V
Sourcing 0 2.5
Continuous Output Current Sinking 0 2.5
A
Sourcing 0 3.0
Peak Output Current Sinking 0 3.0
A
130
95
219
24
50
75
Unit: mil
(Not to scale)
Ground
VCNTL
VOUT VIN
CCNTL
COUT
Ground
For heat
dissipatin
CIN
Fig. 6-4 Fig. 6-5
W83312SN
Publication Date: Mar., 2010
-8- Revision A5
Operating Temperature Range -40 85 °C
Junction Temperature Range (Note3)
-40 125
°C
7.4 Electrical Characteristics
Typicals and limits appearing in normal type apply for Tj = 25°C. Limits appearing in Boldface type apply
over the entire junction temperature range for operation, -40 ° C to 85 ° C (Note4). VCNTL= 3.3V/5V,
VIN=2.5V/1.8V/1.5V, VREF=1.25V/0.9V/0.75V, COUT=100uF, all voltage outputs unloaded (unless
otherwise noted).
PA RAMETER SYMBOL TEST CONDITION MIN TYP MAX UNITS
Input
IOUT=0A, VCNTL=3.3V 0.5
0.7
VCNTL Operating Current ICNTL IOUT =0A, VCNTL=5V 0.7
1 mA
IOUT=0A, VCNTL=3.3V 0.3
0.5
VIN Operating Current IVIN IOUT=0A, VCNTL=5V 0.3
0.5 mA
VREF < 0.2V, VCNTL=3.3V 60
90
VCNTL Quiescent Current in
Shutdown Mode ISD_CNTL VREF < 0.2V, VCNTL=5V 60
90 uA
VIN Quiescent Current in
Shutdown Mode ISD_VIN VREF < 0.2V -1 0 1 uA
IIH VREF=3.3V -1 0 1
VREF Leakage Current
IIL VREF=0V -1 0 1 uA
Output (DDR1 / DDR2 / DDR3)
Output Offset Voltage (VREF-
VOUT) VOS IOUT=0A -5 5 mV
IOUT=0 → +2.5A (Note5)
-20 20
Load Regulation (VREF-VOUT) ∆VLIOUT=0 → -2.5A (Note5)
-20 20 mV
Protection
Current Limit ILIM In any VIN ±3 ±3.5 ±4.5 A
Thermal Shutdown Temperature TSD 3.3V < VCNTL < 5V (Note6)
150 165 175 °C
Thermal Shutdown Hysteresis ∆TSD 3.3V < VCNTL < 5V 30 °C
VREF Shutdown Mode
VIH Enable 0.6
Shutdown Threshold
VIL Disable
0.2 V
Note1. Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these or any other
conditions beyond those indicated under recommended operating conditions is not implied. Exposure to
absolute maximum rated conditions for extended periods may affect device reliability.
Note2. Devices are ESD sensitive. Handling precaution recommended.
Note3. At elevated temperatures, devices must be de-rated based on thermal resistance. The device in the
ESOP-8 package must be de-rated at θJA=75˚C/W junction to ambient with minimum PCB footprint.
W83312SN
Note4. Limits are 100% production tested at 25˚C. Limits over operating temperature range are guaranteed
through correlation using Statistical Quality Control (SQC) methods. The limits are used to calculate
average outgoing quality level.
Note5. VOUT load regulation is tested by using a 10ms period and 50% duty cycle current pulse.
Note6. The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX),
the junction to ambient thermal resistance, θJA , and the ambient temperature, TA. exceeding the
maximum allowable power dissipation will cause excessive die temperature and the regulator will go into
thermal shutdown. Ensured by design, no production tested.
8. TYPICAL OPERATING WAVEFORMS
VIN=2.5V, VCNTL=3.3V, VOUT=1.25V @ 3A Sourcing VIN=2.5V, VCNTL=3.3V, VOUT=1.25V @ 2.5A Sourcing
VIN=2.5V, VCNTL=5V, VOUT=1.25V @ 3A Sourcing VIN=2.5V, VCNTL=5V, VOUT=1.25V @ 2.5A Sourcing
Publication Date: Mar., 2010
-9- Revision A5
W83312SN
VIN=1.8V, VCNTL=3.3V, VOUT=0.9V @ 3A Sourcing
VIN=1.8V, VCNTL=5V, VOUT=0.9V @ 3A Sourcing
VIN=1.8V, VCNTL=3.3V, VOUT=0.9V @ 2.5A Sourcing
VIN=1.8V, VCNTL=5V, VOUT=0.9V @ 2.5A Sourcing
VIN=1.5V, VCNTL=3.3V, VOUT=0.75V @ 3A Sourcing VIN=1.5V, VCNTL=3.3V, VOUT=0.75V @ 2.5A Sourcing
Publication Date: Mar., 2010
-10- Revision A5
W83312SN
VIN=1.5V, VCNTL=5V, VOUT=0.75V @ 3A Sourcing VIN=1.5V, VCNTL=5V, VOUT=0.75V @ 2.5A Sourcing
VIN=1.2V, VCNTL=3.3V, VOUT=0.6V @ 3A Sourcing VIN=1.2V, VCNTL=3.3V, VOUT=0.6V @ 2.5A Sourcing
Publication Date: Mar., 2010
-11- Revision A5
W83312SN
VIN=1.2V, VCNTL=5V, VOUT=0.6V @ 3A Sourcing VIN=1.2V, VCNTL=5V, VOUT=0.6V @ 2.5A Sourcing
VIN=2.5V, VCNTL=3.3V, VOUT=1.25V @ 3A Sinking VIN=2.5V, VCNTL=3.3V, VOUT=1.25V @ 2.5A Sinking
VIN=2.5V, VCNTL=5V, VOUT=1.25V @ 3A Sinking VIN=2.5V, VCNTL=5V, VOUT=1.25V @ 2.5A Sinking
Publication Date: Mar., 2010
-12- Revision A5
W83312SN
VIN=1.8V, VCNT3O.9V @ 3A Sinking VIN=1.8V, VCNTL=3.3V, VOUT=0.9V @ 2.5A Sinking
VIN=1.8V, VCNTL=5V, VOUT=0.9V @ 3A Sinking VIN=1.8V, VCNTL=5V, VOUT=0.9V @ 2.5A Sinking
VIN=1.5V, VCNTL=3.3V, VOUT=0.75V @ 3A Sinking VIN=1.5V, VCNTL=3.3V, VOUT=0.75V @ 2.5A Sinking
Publication Date: Mar., 2010
-13- Revision A5
W83312SN
VIN=1.5V, VCNTL=5V, VOUT=0.75V @ 3A Sinking VIN=1.5V, VCNTL=5V, VOUT=0.75V @ 2.5A Sinking
VIN=1.2V, VCNTL=3.3V, VOUT=0.6V @ 3A Sinking
VIN=1.2V, VCNTL=5V, VOUT=0.6V @ 3A Sinking
VIN=1.2V, VCNTL=3.3V, VOUT=0.6V @ 2.5A Sinking
VIN=1.2V, VCNTL=5V, VOUT=0.6V @ 2.5A Sinking
Publication Date: Mar., 2010
-14- Revision A5
W83312SN
VIN=2.5V, VCNTL=3.3V, VOUT=1.25V, VOUT short to GND VIN=2.5V, VCNTL=5V, VOUT=1.25V, VOUT short to GND
VIN=2.5V, VCNTL=3.3V, VOUT=1.25V, VOUT short to VIN VIN=2.5V, VCNTL=5V, VOUT=1.25V, VOUT short to VIN
Publication Date: Mar., 2010
-15- Revision A5
W83312SN
VIN=1.8V, VCNTL=3.3V, VOUT=0.9V, VOUT short to GND VIN=1.8V, VCNTL=5V, VOUT=0.9V, VOUT short to GND
VIN=1.8V, VCNTL=3.3V, VOUT=0.9V, VOUT short to VIN VIN=1.8V, VCNTL=5V, VOUT=0.9V, VOUT short to VIN
VIN=1.5V, VCNTL=3.3V, VOUT=0.75V, VOUT short to GND VIN=1.5V, VCNTL=5V, VOUT=0.75V, VOUT short to GND
Publication Date: Mar., 2010
-16- Revision A5
W83312SN
VIN=1.5V, VCNTL=3.3V, VOUT=0.75V, VOUT short to VIN VIN=1.5V, VCNTL=5V, VOUT=0.75V, VOUT short to VIN
VIN=1.2V, VCNTL=3.3V, VOUT=0.6V, VOUT short to GND VIN=1.2V, VCNTL=5V, VOUT=0.6V, VOUT short to GND
VIN=1.2V, VCNTL=3.3V, VOUT=0.6V, VOUT short to VIN VIN=1.2V, VCNTL=5V, VOUT=0.6V, VOUT short to VIN
Publication Date: Mar., 2010
-17- Revision A5
W83312SN
VCNTL Current vs. Temperature
410
430
450
470
490
510
530
550
570
590
-40 -20 0 20 40 60 80 100 120
Temperature (°C)
VCNTL Current (uA)
DDR1 @ VCNTL=3.3V
DDR1 @ VCNTL=5V
VCNTL Current vs. Temperature
410
430
450
470
490
510
530
550
570
590
-40 -20 0 20 40 60 80 100 120
Temperature (°C)
VCNTL Current (uA)
DDR2 @ VCNTL=3.3V
DDR2 @ VCNTL=5V
VCNTL Current vs. Temperature
410
430
450
470
490
510
530
550
570
590
-40 -20 0 20 40 60 80 100 120
Temperature (°C)
VCNTL Current (uA)
DDR3 @ VCNTL=3.3V
DDR3 @ VCNTL=5V
VCNTL Current vs. Temperature
410
430
450
470
490
510
530
550
570
590
-40 -20 0 20 40 60 80 100 120
Temperature (°C)
VCNTL Current (uA)
LP DDR @ VCNTL=3.3V
LP DDR @ VCNTL=5V
Publication Date: Mar., 2010
-18- Revision A5
W83312SN
VIN Current vs. Temperature
180
200
220
240
260
280
300
320
-40 -20 0 20 40 60 80 100 120
Temperature (°C)
VIN Current (uA)
DDR1 @ VCNTL=3.3V
DDR1 @ VCNTL=5V
VIN Current vs. Temperature
150
160
170
180
190
200
210
220
-40 -20 0 20 40 60 80 100 120
Temperature (°C)
VIN Current (uA)
DDR2 @ VCNTL=3.3V
DDR2 @ VCNTL=5V
VIN Current vs. Temperature
130
140
150
160
170
180
190
-40 -20 0 20 40 60 80 100 120
Temperature (°C)
VIN Current (uA)
DDR3 @ VCNTL=3.3V
DDR3 @ VCNTL=5V
VIN Current vs. Temperature
110
120
130
140
150
160
-40 -20 0 20 40 60 80 100 120
Temperature (°C)
VIN Current (uA)
LP DDR @ VCNTL=3.3V
LP DDR @ VCNTL=5V
Turn On/Off Threshold vs. Temperature
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
-40 -20 0 20 40 60 80 100 120
Temperature (°C)
Voltage (V)
Turn On @ VCNTL=3.3V
Turn On @ VCNTL=5V
Turn Off @ VCNTL=3.3V
Turn Off
@
VCNTL=5V
VCNTL Shutdown Current vs. Temperature
45
50
55
60
65
70
-40-20 0 20406080100120
Temperature (°C)
VCNTL Current (uA)
VCNTL=3.3V
VCNTL=5V
Publication Date: Mar., 2010
-19- Revision A5
W83312SN
DDR1 Current Limit vs. Temperature
2
2.5
3
3.5
4
4.5
5
-40-20 0 20406080100120
Temperature (°C)
Current (A)
Source @ VCNTL=3.3V
Source @ VCNTL=5V
Sink @ VCNTL=3.3V
Sink @ VCNTL=5V
DDR2 Current Limit vs. Temperature
2
2.5
3
3.5
4
4.5
5
-40 -20 0 20 40 60 80 100 120
Temperature (°C)
Current (A)
Source @ VCNTL=3.3V
Source @ VCNTL=5V
Sink @ VCNTL=3.3V
Sink @ VCNTL=5V
DDR3 Current Limit vs. Temperature
2
2.5
3
3.5
4
4.5
5
-40-20 0 20406080100120
Temperature (°C)
Current (A)
Source @ VCNTL=3.3V
Source @ VCNTL=5V
Sink @ VCNTL=3.3V
Sink @ VCNTL=5V
LP DDR Current Limit vs. Temperature
2
2.5
3
3.5
4
4.5
5
-40 -20 0 20 40 60 80 100 120
Temperature (°C)
Current (A)
Source @ VCNTL=3.3V
Source @ VCNTL=5V
Sink @ VCNTL=3.3V
Sink @ VCNTL=5V
Publication Date: Mar., 2010
-20- Revision A5
W83312SN
Normalized VOFFSET vs. Temperature
-5.00
-4.00
-3.00
-2.00
-1.00
0.00
1.00
2.00
3.00
4.00
5.00
-40 -20 0 20 40 60 80 100 120
Temperature (°C)
VOFFSET (mV)
DDR1 @ VCNTL=3.3V
DDR1 @ VCNTL=5V
Normalized VOFFSET vs. Temperature
-5.00
-4.00
-3.00
-2.00
-1.00
0.00
1.00
2.00
3.00
4.00
5.00
-40 -20 0 20 40 60 80 100 120
Temperature (°C)
VOFFSET (mV
)
DDR2 @ VCNTL=3.3V
DDR2 @ VCNTL=5V
Normalized VOFFSET vs. Temperature
-5.00
-4.00
-3.00
-2.00
-1.00
0.00
1.00
2.00
3.00
4.00
5.00
-40 -20 0 20 40 60 80 100 120
Temperature (°C)
VOFFSET (mV)
DDR3 @ VCNTL=3.3V
DDR3 @ VCNTL=5V
Normalized VOFFSET vs. Temperature
-5.00
-4.00
-3.00
-2.00
-1.00
0.00
1.00
2.00
3.00
4.00
5.00
-40 -20 0 20 40 60 80 100 120
Temperature (°C)
VOFFSET (mV)
LP DDR @ VCNTL=3.3V
LP DDR @ VCNTL=5V
Publication Date: Mar., 2010
-21- Revision A5
W83312SN
9. PACKAGE DIMENSION PACKAGE DIMENSION
SOP8-EP (150mil)
Publication Date: Mar., 2010
-22- Revision A5
W83312SN
¾ TAPING SPECIFICATION
Note: W83312SN L/F size is D1-3 & E1-3 dimension
SOP8-EP Package
10. ORDERING INFORMATION
Part Number Package Type Supplied as Production Flow
W83312SN 8PIN SOP8-EP (Green Package) T Shape: 2,500 units/T&R Commercial, -40°C to +85°C
11. TOP MARKING SPECIFICATION
1st Line: Nuvoton logo
2nd Line: W83312SN (Part number)
3rd line: Tracking code
W83312SN
752ABBX
z 752: packages assembled in Year 2007, week 52
z A: assembly house ID
z BB: Internal use only
z X: the IC version (A means A; B means B & C means C…etc.)
Publication Date: Mar., 2010
-23- Revision A5
W83312SN
12. REVISION HISTORY
VERSION DATE PAGE DESCRIPTION
A1 11/28/2008 All New Create
A2 12/29/2008 4, 5, 7 Update the linear regulator chart &
VIN Recommended Range
A3 8/1/2009 All
1. Updated operating temperature range
2. Updated 6.2 General Regulator
3. Updated Typical Operating Waveforms
A4 1/29/2010 6 Correct Typo, add PCB Layout Suggestion
A5 3/31/2010 6,20
1. Add suggestion land pattern
2. Update the SOP8-EP package outline
Important Notice
Nuvoton products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Nuvoton products are not intended for applications wherein failure
of Nuvoton products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Nuvoton customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Nuvoton for any damages resulting from such improper
use or sales.
Publication Date: Mar., 2010
-24- Revision A5
