BIMOS SERIAL-INPUT, LATCHED SINK DRIVERS UCN5821A THRU UCN5824A, UCNS829EB, AND UCN5841A/EP/LW THRU UCN5843A/EP/LW FEATURES UCN5821A thru m 3.3 MHz Minimum Data Input Rate UCNS824A m@ CMOS, PMOS, NMOS, TTL Compatible . CLOCK Ee our; Mm Low-Power CMOS Logic and Latches SERIAL DATA IN OUT2 @ High-Voltage Current Sink Outputs For the UCN5829EB only: M Internal Current Sensing @ Constant-Frequency PWM Current Control @ Control For External High-Side Driver @ User-Defined Output Enable Timeout @ Internal Thermal Shutdown Circuitry LOGIC GROUND OUT; Dwg. PP-026 Serial-Input Output Part Number Shift Register Output Ratings Features UCN5821A 8-Bit 50 V, 350:mA Darlington UCN5822A 80 V,.350 mA UCN5823A 100: V,350 mA UCN5824A 8-Bit 50.V,.100.mA Saturated UCN5829EB 9-Bit 50V; 4.6A PWM-Current Control UCN5841 A/EP/LW 8-Bit 35 V, 350 mA internal Diodes UCN5842A/EP/LW 50 V,.350 mA UCN5843A/EP/LW 50 V,350-mA Suffix A = DIP, EB = Batwing PLCC, EP = PLCC, LW = wide-body SOIC UCN5829EB UCN5841LW thru UCN5841EP thru < < . UCN5843LW UCN5843EP a ee UCN58414 thru fx oe fee 8 282d $2 b & # UCN5843A Yess 33a al . a tl? Mell Yop CLK [| A 2 cenopi ty | CONTROL | -| 39 | GND Vee Li es ours GROUND C3 ey one shor Je rj} clock [2 of OS'S Cel eye riazj os SERIAL DATA IN [7 oats att 9 e jw H ere SHIFT REGISTER LATCHES COMMON SERIAL DATA OUT [6 CLAMP DIODE STROBE [ OUTPUT ENABLE [8 Dwg. No. A-14,362 aa vw N 5 Dwg. No. A-12,659 eee tT ot 2 ot TT Tt TF oo @ @ ee @ << So w o yw fa fl Fahad | 6 27 [ae NO. CONNECTION NO OUT, OUT , OUT, OUT, OUT ,| 23 OUT , OUT OUT OUT , CONNECTION Dwg. PP-028 36