6
2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L128L18F_2.p65 – Rev. 8/00 ©2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
FLOW-THROUGH SYNCBURST SRAM
TQFP PIN DESCRIPTIONS (continued)
x18 x32/x36 SYMBOL TYPE DESCRIPTION
85 85 ADSC# Input Synchronous Address Status Controller: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ or WRITE is performed using the new address if
CE# is LOW. ADSC# is also used to place the chip into power-down
state when CE# is HIGH.
31 31 MODE Input Mode: This input selects the burst sequence. A LOW on this pin
selects “linear burst.” NC or HIGH on this pin selects “interleaved
burst.” Do not alter input state while device is operating.
64 64 ZZ Input Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained. When ZZ is active, all other inputs are
ignored.
(a) 58, 59, (a) 52, 53, DQa Input/ SRAM Data I/Os: For the x18 version, Byte “a” is DQa pins; Byte “b”
62, 63, 68, 69, 56-59, 62, 63 Output is DQb pins. For the x32 and x36 versions, Byte “a” is DQa pins;
72, 73 Byte “b” is DQb pins; Byte “c” is DQc pins; Byte “d” is DQd pins.
(b) 8, 9, 12, (b) 68, 69, DQb Input data must meet setup and hold times around the rising edge
13, 18, 19, 22, 72-75, 78, 79 of CLK.
23
(c) 2, 3, 6-9, DQc
12, 13
(d) 18, 19, DQd
22-25, 28, 29
74 51 NC/DQPa NC/ No Connect/Parity Data I/Os: On the x32 version, these pins are No
24 80 NC/DQPb I/O Connect (NC). On the x18 version, Byte “a” parity is DQPa; Byte “b”
–1NC/DQPc parity is DQPb. On the x36 version, Byte “a” parity is DQPa; Byte
–30 NC/DQPd “b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is DQPd.
15, 41, 65, 91 15, 41, 65, 91 V
DD
Supply Power Supply: See DC Electrical Characteristics and Operating
Conditions for range.
4, 11, 20, 27, 4, 11, 20, 27, V
DD
Q Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and
54, 61, 70, 77 54, 61, 70, 77 Operating Conditions for range.
5, 10, 14, 17, 5, 10, 14, 17, V
SS
Supply Ground: GND.
21, 26, 40, 55, 21, 26, 40, 55,
60, 67, 71, 76, 60, 67, 71, 76,
90 90
38, 39, 42, 43 38, 39, 42, 43 DNU –Do Not Use: These signals may either be unconnected or wired to
GND to improve package heat dissipation.
1-3, 6, 7, 16, 16, 66 NC –No Connect: These signals are not internally connected and may be
25, 28-30, connected to ground to improve package heat dissipation.
51-53, 56, 57,
66, 75, 78, 79,
95, 96
50 50 NC/SA –No Connect: This pin is reserved for address expansion.