Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
1
Rev. D
12/06/05
ISSI
®
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
IS61LV51216
IS64LV51216
FEATURES
• High-speed access time:
— 8, 10, and 12 ns
• CMOS low power operation
• Low stand-by power:
— Less than 5 mA (typ.) CMOS stand-by
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial and Automotive temperatures available
• Lead-free available
512K x 16 HIGH SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH 3.3V SUPPLY
DESCRIPTION
The ISSI IS61/64LV51216 is a high-speed, 8M-bit static
RAM organized as 525,288 words by 16 bits. It is fabricated
using ISSI's high-performance CMOS technology. This
highly reliable process coupled with innovative circuit de-
sign techniques, yields high-performance and low power
consumption devices.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS61/64LV51216 is packaged in the JEDEC standard
44-pin TSOP Type II and 48-pin Mini BGA (9mm x 11mm).
FUNCTIONAL BLOCK DIAGRAM
DECEMBER 2005
A0-A18
CE
OE
WE
512K x 16
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VDD
I/O
DATA
CIRCUIT
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
UB
LB
2
Integrated Silicon Solution, Inc. — www.issi.com —
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Rev. D
12/06/05
ISSI
®
IS61LV51216
IS64LV51216
TRUTH TABLE
I/O PIN
Mode WEWE
WEWE
WE CECE
CECE
CE OEOE
OEOE
OE LBLB
LBLB
LB UBUB
UBUB
UB I/O0-I/O7 I/O8-I/O15 VDD Current
Not Selected X H X X X High-Z High-Z ISB1, ISB2
Output Disabled H L H X X High-Z High-Z ICC
X L X H H High-Z High-Z
Read H L L L H DOUT High-Z ICC
H L L H L High-Z DOUT
HLLLL DOUT DOUT
Write L L X L H DIN High-Z ICC
L L X H L High-Z DIN
LLXLL DIN DIN
PIN DESCRIPTIONS
A0-A18 Address Inputs
I/O0-I/O15 Data Inputs/Outputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
LB Lower-byte Control (I/O0-I/O7)
UB Upper-byte Control (I/O8-I/O15)
NC No Connection
VDD Power
GND Ground
44-Pin TSOP (Type II)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A0
A1
A2
A3
A4
CE
I/O0
I/O1
I/O2
I/O3
VDD
GND
I/O4
I/O5
I/O6
I/O7
WE
A5
A6
A7
A8
A9
A17
A16
A15
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
I/O8
A18
A14
A13
A12
A11
A10
PIN CONFIGURATIONS
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Rev. D
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ISSI
®
IS61LV51216
IS64LV51216
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND –0.5 to VDD+0.5 V
VDD VDD Related to GND –0.3 to +4.0 V
TSTG Storage Temperature –65 to +150 °C
PTPower Dissipation 1.0 W
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
48-Pin mini BGA (9mmx11mm)
1 2 3 4 5 6
A
B
C
D
E
F
G
H
LB OE A0 A1 A2 N/C
I/O
8
UB A3 A4 CE I/O
0
I/O
9
I/O
10
A5 A6 I/O
1
I/O
2
GND I/O
11
A17 A7 I/O
3
VDD
VDD I/O
12
GND A16 I/O
4
GND
I/O
14
I/O
13
A14 A15 I/O
5
I/O
6
I/O
15
NC A12 A13 WE I/O
7
A18 A8 A9A10 A11 NC
PIN CONFIGURATIONS
PIN DESCRIPTIONS
A0-A18 Address Inputs
I/O0-I/O15 Data Inputs/Outputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
LB Lower-byte Control (I/O0-I/O7)
UB Upper-byte Control (I/O8-I/O15)
NC No Connection
VDD Power
GND Ground
4
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Rev. D
12/06/05
ISSI
®
IS61LV51216
IS64LV51216
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8 -10 -12
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit
ICC VDD Dynamic Operating VDD = Max., Com. — 110 — 100 — 90 mA
Supply Current IOUT = 0 mA, f = fMAX Ind. — 120 — 110 — 100
Auto. — 120
ISB1TTL Standby Current VDD = Max., Com. — 30 — 30 — 30 mA
(TTL Inputs) VIN = VIH or VIL Ind. — 35 — 35 — 35
CE ≥ VIH, f = 0 Auto. — 40
ISB2CMOS Standby VDD = Max., Com. — 20 — 20 — 20 mA
Current (CMOS Inputs) CE ≥ VDD – 0.2V, Ind. — 25 — 25 — 25
VIN ≥ VDD – 0.2V, or Auto. — 30
VIN ≤ 0.2V, f = 0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VDD = Min., IOH = –4.0 mA 2.4 — V
VOL Output LOW Voltage VDD = Min., IOL = 8.0 mA — 0.4 V
VIH Input HIGH Voltage 2.2 VDD + 0.3 V
VIL Input LOW Voltage(1) –0.3 0.8 V
ILI Input Leakage GND ≤ VIN ≤ VDD Com. –1 1 µA
Ind. –5 5
Auto. -10 -10
ILO Output Leakage GND ≤ VOUT ≤ VDD Com. –1 1 µA
Outputs Disabled Ind. –5 5
Auto. -10 -10
Notes:
1. VIL (min.) = –2.0V for pulse width less than 10 ns.
OPERATING RANGE
Range Ambient Temperature VDD
Commercial 0°C to +70°C 3.3V +10%, -5%
Industrial –40°C to +85°C 3.3V +10%, -5%
Automotive –40°C to +125°C 3.3V +10%, -5%
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Rev. D
12/06/05
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ISSI
®
IS61LV51216
IS64LV51216
CAPACITANCE(1)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Input/Output Capacitance VOUT = 0V 8 pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
AC TEST LOADS
Figure 1 Figure 2
319 Ω
5 pF
Including
jig and
scope
353 Ω
OUTPUT
3.3V
Z
O
= 50Ω
1.5V
50Ω
OUTPUT
30 pF
Including
jig and
scope
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 3 ns
Input and Output Timing 1.5V
and Reference Level
Output Load See Figures 1 and 2
6
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Rev. D
12/06/05
ISSI
®
IS61LV51216
IS64LV51216
DATA VALID
READ1.eps
PREVIOUS DATA VALID
t AA
t OHA
t OHA
t RC
D
OUT
ADDRESS
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-8 -10 -12
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tRC Read Cycle Time 8 — 10 — 12 — ns
tAA Address Access Time — 8 — 10 — 12 ns
tOHA Output Hold Time 3 — 3 — 3 — ns
tACE CE Access Time — 8 — 10 — 12 ns
tDOE OE Access Time — 3.5 — 4 — 5 ns
tHZOE
(2)
OE to High-Z Output — 3 — 4 0 5 ns
tLZOE
(2)
OE to Low-Z Output 0 — 0 — 0 — ns
tHZCE
(2
CE to High-Z Output 0 3 0 4 0 6 ns
tLZCE
(2)
CE to Low-Z Output 3 — 3 — 3 — ns
tBA LB, UB Access Time — 3.5 — 4 — 5 ns
tHZB
(2)
LB, UB to High-Z Output 0 3 0 3 0 4 ns
tLZB
(2)
LB, UB to Low-Z Output 0 — 0 — 0 — ns
tPU Power Up Time 0 — 0 — 0 — ns
tPD Power Down Time — 8 — 10 — 12 ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to
3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage.
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Rev. D
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ISSI
®
IS61LV51216
IS64LV51216
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE
t
LZCE
t
HZOE
HIGH-Z DATA VALID
UB_CEDR2.eps
t
HZB
ADDRESS
OE
CE
LB, UB
D
OUT
t
HZCE
t
BA
t
LZB
t
RC
t
PD
I
SB
I
CC
50%
V
DD
Supply
Current
50%
t
PU
READ CYCLE NO. 2(1,3)
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = VIL.
3. Address is valid prior to or coincident with CE LOW transition.
8
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Rev. D
12/06/05
ISSI
®
IS61LV51216
IS64LV51216
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-8 -10 -12
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tWC Write Cycle Time 8 — 10 — 12 — ns
tSCE CE to Write End 6.5 — 8 — 8 — ns
tAW Address Setup Time 6.5 — 8 — 8 — ns
to Write End
tHA Address Hold from Write End 0 — 0 — 0 — ns
tSA Address Setup Time 0 — 0 — 0 — ns
tPWB LB, UB Valid to End of Write 6.5 — 8 — 8 — ns
tPWE1WE Pulse Width 6.5 — 8 — 8 — ns
tPWE2WE Pulse Width (OE = LOW) 8.0 — 10 — 12 — ns
tSD Data Setup to Write End 5 — 6 — 6 — ns
tHD Data Hold from Write End 0 — 0 — 0 — ns
tHZWE
(2)
WE LOW to High-Z Output — 3.5 — 5 — 6 ns
tLZWE
(2)
WE HIGH to Low-Z Output 2 — 2 — 2 — ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to
3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced
to the rising or falling edge of the signal that terminates the write. Shaded area product in development
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Rev. D
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ISSI
®
IS61LV51216
IS64LV51216
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs
and at least one of the LB and UB inputs being in the LOW state.
2. WRITE = (CE) [ (LB) = (UB) ] (WE).
AC WAVEFORMS
WRITE CYCLE NO. 1
(CE Controlled, OE is HIGH or LOW)
(1 )
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCE
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
PBW
t
HD
t
SA
t
HZWE
ADDRESS
CE
UB, LB
WE
D
OUT
D
IN DATAIN VALID
t
LZWE
t
SD
UB_CEWR1.eps
10
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. D
12/06/05
ISSI
®
IS61LV51216
IS64LV51216
AC WAVEFORMS
WRITE CYCLE NO. 2
(WE Controlled. OE is HIGH During Write Cycle)
(1,2)
DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
PBW
t
HD
t
SA
t
HZWE
ADDRESS
CE
UB, LB
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
UB_CEWR2.eps
WRITE CYCLE NO. 3
(WE Controlled. OE is LOW During Write Cycle)
(1)
DATA UNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
PBW
t
HD
t
SA
t
HZWE
ADDRESS
CE
UB, LB
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
UB_CEWR3.eps
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Rev. D
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ISSI
®
IS61LV51216
IS64LV51216
AC WAVEFORMS
WRITE CYCLE NO. 4
(LB, UB Controlled, Back-to-Back Write)
(1,3)
DATA UNDEFINED
t
WC
ADDRESS 1 ADDRESS 2
t
WC
HIGH-Z
t
PBW
WORD 1
LOW
WORD 2
UB_CEWR4.eps
t
HD
t
SA
t
HZWE
ADDRESS
CE
UB, LB
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
t
PBW
DATA
IN
VALID
t
SD
t
HD
t
SA
t
HA
t
HA
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid
states to initiate a Write, but any can be deasserted to terminate the Write. The t SA, t HA, t SD, and t HD timing is referenced to the
rising or falling edge of the signal that terminates the Write.
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
12
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Rev. D
12/06/05
ISSI
®
IS61LV51216
IS64LV51216
ORDERING INFORMATION:
Commercial Range: 0°C to +70°C
Speed Order Part No. Package
(ns)
8 IS61LV51216-8T TSOP (Type II)
IS61LV51216-8TL TSOP (Type II), Lead-free
IS61LV51216-8M Mini BGA (9mm x 11mm)
10 IS61LV51216-10T TSOP (Type II)
IS61LV51216-10M Mini BGA (9mm x 11mm)
12 IS61LV51216-12T TSOP (Type II)
Industrial Range: –40°C to +85°C
Speed Order Part No. Package
(ns)
8 IS61LV51216-8TI TSOP (Type II)
IS61LV51216-8MI Mini BGA (9mm x 11mm)
10 IS61LV51216-10TI TSOP (Type II)
IS61LV51216-10TLI TSOP (Type II), Lead-free
IS61LV51216-10MI Mini BGA (9mm x 11mm)
IS61LV51216-10MLI Mini BGA (9mm x 11mm), Lead-free
12 IS61LV51216-12TI TSOP (Type II)
Automotive Range: –40°C to +125°C
Speed Order Part No. Package
(ns)
12 IS64LV51216-12TA3 TSOP (Type II)(1)
IS64LV51216-12TLA3 TSOP (Type II)(1), Lead-free
Note:
1. Copper Leadframe
PACKAGING INFORMATION ISSI®
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. D
01/15/03
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Mini Ball Grid Array
Package Code: M (48-pin)
Notes:
1. Controlling dimensions are in millimeters.
SEATING PLANE
A
A1
A2
A
B
C
D
E
F
G
H
e
e
D1
E1E
D
φ b (48x)
Top View Bottom View
6 5 4 3 2 11 2 3 4 5 6
A
B
C
D
E
F
G
H
PACKAGING INFORMATION ISSI®
2
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Rev. D
01/15/03
mBGA - 7.2mm x 8.7mm
MILLIMETERS INCHES
Sym. Min. Typ. Max. Min. Typ. Max.
N0.
Leads 48
A — — 1.20 — — 0.047
A1 0 .24 — 0.30 0.009 — 0.012
A2 0.60 — — 0.024 — —
D 8.60 8.70 8.80 0.339 0.343 0.346
D1 5.25BSC 0.207BSC
E 7.10 7.20 7.30 0.280 0.283 0.287
E1 3.75BSC 0.148BSC
e 0.75BSC 0.030BSC
b 0.30 0.35 0.40 0.012 0.014 0.016
mBGA - 9mm x 11mm
MILLIMETERS INCHES
Sym. Min. Typ. Max. Min. Typ. Max.
N0.
Leads 48
A — — 1.20 — — 0.047
A1 0.24 — 0.30 0.009 — 0.012
A2 0.60 — — 0.024 — —
D 10.90 11.00 11.10 0.429 0.433 0.437
D1 5.25BSC 0.207BSC
E 8.90 9.00 9.10 0.350 0.354 0.358
E1 3.75BSC 0.148BSC
e 0.75BSC 0.030BSC
b 0.30 0.35 0.40 0.012 0.014 0.016
mBGA - 6mm x 8mm
MILLIMETERS INCHES
Sym. Min. Typ. Max. Min. Typ. Max.
N0.
Leads 48
A — — 1.20 .— — 0.047
A1 0.25 — 0.40 0.010 — 0.016
A2 0.60 — — 0.024 — —
D 7.90 8.00 8.10 0.311 0.314 0.319
D1 5.60BSC 0.220BSC
E 5.90 6.00 6.10 0.232 0.236 0.240
E1 4.00BSC 0.157BSC
e 0.80BSC 0.031BSC
b 0.40 0.45 0.50 0.016 0.018 0.020
Mini Ball Grid Array
Package Code: M (48-pin)
PACKAGING INFORMATION ISSI®
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
06/18/03
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Plastic TSOP
Package Code: T (Type II)
D
SEATING PLANE
b
eC
1N/2
N/2+1N
E1
A1
A
E
Lα
ZD
.
Notes:
1. Controlling dimension: millimieters,
unless otherwise specified.
2. BSC = Basic lead spacing
between centers.
3. Dimensions D and E1 do not
include mold flash protrusions and
should be measured from the
bottom of the package.
4. Formed leads shall be planar with
respect to one another within
0.004 inches at the seating plane.
Plastic TSOP (T - Type II)
Millimeters Inches Millimeters Inches Millimeters Inches
Symbol Min Max Min Max Min Max Min Max Min Max Min Max
Ref. Std.
No. Leads (N) 32 44 50
A — 1.20 — 0.047 — 1.20 — 0.047 — 1.20 — 0.047
A1 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006
b 0.30 0.52 0.012 0.020 0.30 0.45 0.012 0.018 0.30 0.45 0.012 0.018
C 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008
D 20.82 21.08 0.820 0.830 18.31 18.52 0.721 0.729 20.82 21.08 0.820 0.830
E1 10.03 10.29 0.391 0.400 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405
E 11.56 11.96 0.451 0.466 11.56 11.96 0.455 0.471 11.56 11.96 0.455 0.471
e 1.27 BSC 0.050 BSC 0.80 BSC 0.032 BSC 0.80 BSC 0.031 BSC
L 0.40 0.60 0.016 0.024 0.41 0.60 0.016 0.024 0.40 0.60 0.016 0.024
ZD 0.95 REF 0.037 REF 0.81 REF 0.032 REF 0.88 REF 0.035 REF
α0° 5° 0° 5° 0° 5° 0° 5° 0° 5° 0° 5°
