M48T212A-85MH1TR - STMicroelectronics

1/20

PRELIMINARY DATA

March 2000

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M48T212A

3.3V TIMEKEEPER® CONTROLLER

■CON VERTS LOW POWER SRAM int o

NVRAMs

■YEAR 2000 COMPLIAN T (4-Digit Year)

■USES SUPER CAPACITOR or LITHIUM

BATTERY (User Supplied)

■BATTERY LOW FLAG

■INTEGRATED REAL TIME CLOCK,

POWER-FAIL CONTROL CIRCUIT

■AUTOMATIC POWER-FAIL CHIP DESELECT

and WRITE P ROTEC T ION

■WATCHDOG T IME R

■WRITE PROTECT VOLTAGES

(VPFD = Power-fail Deselect Voltage):

– M48T 212A : 2.7V ≤ VPFD ≤ 3.0V

■MI CR OPRO C ESSOR POWER- O N RES ET

■PR O GRAMM A BLE A L A R M O U TPU T ACTI VE

in the BATTERY BACKED-UP MODE

DESCRIPTION

The M48T 212A is a se lf-containe d device that in-

cludes a real time clock (RTC), programmable

alarms, a watchdog timer, and two external chip

enable out puts which prov ide con trol of up t o four

(two in parallel) external low-power static RAMs.

A built-in 32.768 kHz oscillator (external crystal

controlled) is used for the clock/calendar f unction.

Access to all TIMEKEEPER functions and the ex-

ternal RAM is the same as conventional byt e- wide

SRAM. The 16 TIMEKEEPER Registers offer

Century, Year, Month, Date, Day, Hour, Minute,

Second, Control, Calibration, Alarm, Watchdog,

and Flags. Externally attached static RAMs are

controlled by the M48T212A via the E1CON and

E2CON signals (see Table 4).

Automatic backup and write protection for an ex-

ternal SRAM is provided through VOUT, E1CON

and E2CON pins. (Users are urged to insure that

voltage specifications, for both the controller chip

and ext ernal SRAM chosen, are similar).

Figure 1. Logic Diagram

AI03047

A0-A3

DQ0-DQ7

VCC

M48T212A

VSS

E2CON

E1CON

RSTIN2

RSTIN1

RST

IRQ/FT

VOUT

WDI

VCAP

VCCSW

VBAT–

SOH44 (MH)

M48T212A

2/20

The lithium energy source (or super capacitor)

used to permanently power the real time clock is

also used to retain RAM data in the absence of

VCC power through the VOUT pin.

The chip enable outputs to RAM (E1CON and

E2CON) are controlled during power transients to

prevent dat a corruption. The dat e is autom at ically

adjusted for months with less than 31 days and

corrects for leap years. T he i nternal wat chdog tim-

er provides programmable alarm windows.

The nine clock bytes (F h - 9h and 1h) are no t the

actual clock counters, they are memory locations

consisting of BiPORTTM read/write memory cells

within the static RAM array. Clock circuitry up-

dates the clock bytes with current information once

per second. The information ca n be accessed by

the user in the same manner as any other l ocation

in the static memory array.

Byte 8h is the clock c ontrol register . This byte con-

trols user access to the cl ock inf ormation and also

stores the clock calibration setting. Byte 7h con-

tains the watchdog timer setting. The watchdog

timer can generate either a reset or an interrupt,

depending on the state of the W atchdog Stee ring

bit (WDS). Bytes 6h-2h include bits that, when pro-

grammed , provide for clock alarm functionality.

Alarms are activated when the register content

matches the month, date, hours, minutes, and

seconds of the clock registers. Byte 1h contains

century information. Byte 0h contains additional

flag information pertaining to the watchd og timer,

alarm and battery status.

The M48T212A also has its own Power-Fail De-

tect circuit. This control circuitry constantly moni-

tors the supply voltage for an out of tolerance

condition. When VCC is out of tolerance, the circuit

wri te pr otect s the TI MEKE EPER regist e r data and

external SRAM, providing data security in the

midst of unpredictable system operation. As VCC

falls, the control circuitry automatically switches to

the battery, maintaining data and clock operation

until valid power is restored.

Table 1. Signal Names

A0-A3 Address Inputs

DQ0-DQ7 Data Inputs/Outputs

XO Oscillator Output

XI Oscillator Input

RSTIN1 Reset 1 Input

RSTIN2 Reset 2 Input

RST Reset Output (Open Drain)

WDI Watchdog Input

A Bank Select Input

EChip Enable Input

EX External Chip Enable Input

GOutput Enable Input

WWrite Enable Input

E1CON RAM Chip Enable 1 Output

E2CON RAM Chip Enable 2 Output

IRQ/FT Int/Freq Test Output (Open Drain)

Vccsw VCC Switch Output

VOUT Supply Voltage Output

VCAP Super Capa citor Input

VBAT– Battery Ground Pin (optional)

VCC Supply Voltage

VSS Ground

NC Not Connected internally

Figure 2. SOIC Connecti ons

AI03048

VSS

E1CON

VOUT

VCC

M48T212A

XO EX

VCCSW

WDI

E2CON DQ7

DQ5DQ0

DQ1 DQ3

DQ4

DQ6

RSTIN2

RST

VCAP

VBAT–

RSTIN1

DQ2

IRQ/FT

3/20

M48T212A

Table 2. Absolute Maximum Ratings (1)

Note: 1. Stres ses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the devic e. This i s a stress

rating only and function al opera tion of the device at these or any other con di t i ons above those i ndi cated i n the operational section

of this sp ecific ation is not implied. Exposure to the absolute maximum rating c onditio ns for ex te nded pe riods o f t ime may affect

reliability.

2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).

CAUTION: Negative undershoots bel ow –0.3V are not all owed on any pin while in the Battery Back-up mode.

Table 3. Operating Modes (1)

No te: 1. X = V IH or VIL.

2. VSO = Battery Back-up S witchover Voltage. (See Tabl e 7 for det ai l s).

Table 4. Truth Table for SRAM Bank Select (1)

No te: 1. X = V IH or VIL.

2. VSO = Battery Back-up S witchover Voltage. (See Tabl e 7 for det ai l s).

Symbol Parameter Value Unit

TAAmbient Operating Temperature 0 to 70 °C

TSTG Storage Temperature (VCC Off, Oscillator Off) –55 to 125 °C

TSLD (2) Lead Solder Temperature for 10 sec 260 °C

VIO Input or Output Voltages –0.3 to 4.6 V

VCC Supply Voltage –0.3 to 4.6 V

IOOutput Current 20 mA

PDPower Dissip ation 1 W

Mode VCC E G W DQ7-DQ0 Power

Deselect

3.0V to 3.6V

VIH X X High-Z Standby

Write VIL XVIL DIN Active

Read VIL VIL VIH DOUT Active

Read VIL VIH VIH High-Z Active

Deselect VSO to VPFD (min) (2) X X X High-Z CMOS Standby

Deselect ≤ VSO (2) X X X High-Z Batter y Back-Up

Mode VCC EX A E1CON E2CON Power

Select 3.0V to 3.6V

Low Low Low High Active

Low High High Low Active

Deselect High X High High Standby

Deselect VSO to VPFD (min) (2) X X High High CMOS Standby

Deselect ≤ VSO (2) X X High High Batter y Back-Up

M48T212A

4/20

Figure 3. Hardware Hookup

No te : 1. See descript ion in Power Su pply De coupling and Undershoot Prot ection.

2. Traces connecting E1CON and E2CON to external SRAM should be as short as possible.

AI03049

A0-A3

DQ0-DQ7

VCC

WDI

RSTIN1

RSTIN2

VCAP

VCC

A0-Axx

0.1µF

3.3V

E2CON

RST

IRQ/FT

M48T212A

CMOS

SRAM

VOUT

E1CON Note 2

MOTOROLA

MTD20P06HDL

VCCSW

1N5817 (1)

A0-A18

VCC

CMOS

SRAM

VSS

SuperCap Supply

A0-Axx

32 kHz

Crystal

Figure 4. AC Testing Load Circuit (3,4)

Note: 1. DQ0-DQ7

2. E1CON and E2CON

3. Exc l udi ng open-drai n out put pins

AI03239

CL = 100pF or 5pF

(1)

CL = 30 pF

(2)

645Ω

DEVICE

UNDER

TEST

1.75V

CL includes JIG capacitance

Table 5. AC Measu remen t Conditions

Note that Output Hi-Z is defined as the point where data

is no longer driven.

Input Rise and Fall Times ≤ 5ns

Input Pulse Voltages 0 to 3V

Input and Output Timing Ref. Voltages 1.5V

5/20

M48T212A

Table 6. Capacitance (1)

(TA = 25 °C, f = 1 MHz)

Not e: 1. Sampled only, not 100% tested.

2. Outputs desel ected .

Table 7. DC Characteristics

(TA = 0 to 70°C; VCC = 3V t o 3.6V)

No te : 1. Outputs des el ected .

2. RSTIN1 and RS TIN2 intern ally pulled-up t o VCC through 100KΩ resistor. WDI internally pulled-down to VSS through 100KΩ resistor.

3. For I RQ/FT & RST pins (Open Drain).

4. Condi tioned output s (E 1 CON - E2CON) can only sus tain CMOS leak age currents in the battery bac k-up mode. Higher lea kage cur -

rents will red uce battery life.

5. External SRAM must match TIMEKEEPER Contro ller ch ip VCC specification.

6. When fully charged.

Symbol Parameter Test Condition Min Max Unit

CIN Input Capacitance VIN = 0V 10 pF

COUT (2) Input/Output Capacitance VOUT = 0V 10 pF

Symbol Parameter Test Condition Min Typ Max Unit

ILI (1,2) Input Leakage Current 0V ≤ VIN ≤ VCC ±1 µA

ILO (1) Output Leak age Curren t 0V ≤ VOUT ≤ VCC ±1 µA

ICC Supply Curre nt Outputs Open 4 1 0 mA

ICC1 Supply Current (Standby) TTL E = VIH 3mA

CC2 Supply Current (Standby) CMOS E = VCC –0.2 2mA

BAT Battery Current OSC ON 575 800 nA

Battery Current OSC OFF 100 nA

VIL Input Low Voltage –0.3 0.8 V

VIH Input High Voltage 2.0 VCC + 0.3 V

VOL Output Low Voltage IOL = 2.1mA 0.4 V

Output Low Vo ltage (open drain) (3) IOL = 10mA 0.4 V

VOH O utput High Voltage IOH = –1.0mA 2.4 V

VOHB (4) VOH Battery Back-up IOUT2 = –1.0µA 2.0 3.6 V

IOUT1 (5) VOUT Current (Active) VOUT1 > VCC –0.3 70 mA

IOUT2 VOUT Current (Battery Back-up) VOUT2 > VBAT –0.3 100 µA

VPFD Power-fail Deselect Voltage 2.7 2.9 3.0 V

VSO Battery Back-up Switchover Voltage VPFD –100mV V

VBAT Battery Voltage 3.0 V

VCAP Capacitor Voltage (6) VCC V

M48T212A

6/20

Table 8. Power Down/Up AC Chara cteri stics

(TA = 0 to 70°C)

Symbol Parameter Min Max Unit

tFVPFD (max) to VPFD (min) VCC Fall Time 300 µs

tFB VPFD (min) to VSS VCC Fall Time 150 µs

tRVPFD (min) to VPFD (max) VCC Rise Time 10 µs

tREC VPFD (max) to RST High 40 200 ms

tRB VSS to VPFD (min) VCC Rise Time 5µs

Figure 5. Power Down/ Up AC Waveform

AI02638

VCC

INPUTS

RST

OUTPUTS

DON'T CARE

HIGH-Z

tFB

tRECtRB

VALID VALID

VPFD (max)

VPFD (min)

VSO

VALID VALID

VCCSW

7/20

M48T212A

Table 9. Chip Enable Control and Bank Select Characteri stics

(TA = 0 to 70°C)

Symbol Parameter

M48T212A

Unit-85

Min Max

tEXPD EX to E1CON or E2CON (Low or High) 15 ns

tAPD A to E1CON or E2CON (Low or High) 15 ns

Figu re 6. Chi p Enable C o nt rol and Ba nk Select Tim i ng

AI02639

tEXPD tAPD

tEXPD

E1CON

E2CON

Table 10. Read Mode Characteri stics

(TA = 0 to 70°C)

Note: 1. CL = 5pF

Symbol Parameter

M48T212A

Unit-85

Min Max

tAVAV Read Cycle Time 85 ns

tAVQV Address Valid to Output Valid 85 ns

tELQV Chip Enable Low to Output Valid 85 ns

tGLQV Output Enable Low to Output Valid 35 ns

tELQX (1) Chip Enable Low to Output Transition 5 ns

tGLQX (1) Output Enable Low to Output Transition 0 ns

tEHQZ (1) Chip Enable High to Output Hi-Z 25 ns

tGHQZ (1) Output Enable High to Output Hi-Z 25 ns

tAXQX Address Transition to Output Transition 5 ns

M48T212A

8/20

Table 11. Write Mode AC Characteristics

(TA = 0 to 70°C)

Note: 1. CL = 5pF.

2. If E goes low simultaneously wit h W going low , t he outputs remain i n the hi gh i m pedance state.

Symbol Parameter

M48T212A

Unit-85

Min Max

tAVAV Write Cycle Time 85 ns

tAVWL Address Valid to Write Enable Low 0 ns

tAVEL Address Valid to Chip Enable Low 0 ns

tWLWH Write Enable Pulse Width 55 ns

tELEH Chip Enable Low to Chip Enable High 60 ns

tWHAX Write Enable High to Address Transition 0 ns

tEHAX Chip Enable High to Address Transition 0 ns

tDVWH Input Valid to Write Enable High 30 ns

tDVEH Input Valid to Chip Enable High 30 ns

tWHDX Write Enable High to Input Transition 0 ns

tEHDX Chip Enable High to Input Transition 0 ns

tWLQZ (1,2) Write Enable Low to Output High-Z 25 ns

tAVWH Address Valid to Write Enable High 65 ns

tAVEH Address Valid to Chip Enable High 65 ns

tWHQX (1,2) Write Enable High to Output Transition 5 ns

Address Decoding

The M48T212A accommodates 4 address lines

(A3-A0) which allo w access to the sixteen by tes of

th e TIMEKEEPE R cl o ck registers. All TIMEKEEP-

ER registers reside in the controller chip itself. All

TIM EKEEPER r egi sters ar e access ed by enabling

E (Chip Enable).

READ MODE

The M48T212A executes a read cycle whenever

W (Write Enable) is high and E (Chip Enable) is

low. The unique address specified by the address

inputs (A3-A0) defines which one of the on-chip

TIMEKEEPER registers is to be accessed. When

the address presented t o the M48T212A is in the

range of 0h-Fh, one of the on-board TIMEKEEP-

ER registers is accessed and valid data will be

available to the eight data output drivers within

tAVQV after the addres s inpu t signal is stable, pro-

viding that the E and G access time s a re also sat -

isfied. If they are not, then data access must be

measured from the latter occurring signal (E or G)

and the limiting parameter is either tELQV for E or

tGLQV for G rathe r than the address access time.

When EX input is low, an external SRA M locat ion

will be se lec t e d.

Note: Care should be taken to avoid taking both E

and EX low simultaneously to avoid bus conten-

tion.

9/20

M48T212A

Figure 8. Write Cycle Timing: RTC Control Signals

AI02641

DQ0-DQ7

DATA IN

VALID

ADDRESS

tAVAV

tAVEH

tAVAV tAVAV

WRITE WRITE READ

DATA OUT

VALID

DATA OUT

VALID

tAVWH

tAVQV

tWLWH

tWHDX

tWHAX

tWHQX tWLQZ

tDVWH

tGLQV

tEHQZ tDVEH

DATA IN

VALID

tELEH tEHAX

tAVEL

tEHDX

tAVWL

Figu re 7. Re ad Cycle Timi ng: R TC C ontrol Si gn a l s

AI02640

DQ7-DQ0

DATA OUT

VALID

ADDRESS

tAVAV

tELQV

tAVAV tAVAV

READ READ WRITE

DATA IN

VALID

DATA OUT

VALID

tAVQV tWHAXtAVWL

tELQX

tGLQV

tGHQZ

tWLWH

tAXQXtGLQX

M48T212A

10/20

Table 12. Alarm Repeat Modes

RPT5 RPT4 RPT3 RPT2 RPT1 Alarm Setting

11111 Once per Second

11110 Once per Minute

11100 Once per Hour

11000 Once per Day

10000 Once per M onth

00000 Once per Year

WRITE MODE

The M4 8T212 A is in th e Write M ode whenever W

(Write Enable) and E (Chip Enable) are in a low

state after the address inputs are stable. The start

of a write is referenced from the latter occurring

falling edge of W or E . A write is terminated by the

earlier rising edge of W or E. The addres ses must

be held vali d throughout the cycl e. E or W mus t re-

turn high for a minimum of tEHAX from Chip Enable

or tWHAX f rom Write Enable prior to the init iation of

another read or write cycle. Data-in must be v alid

tDVWH prior t o t he end of write and remain valid for

tWHDX afterward.

G sho uld be kept high during write cycles to avoid

bus contention; although, if the output bus has

been act ivated by a low on E and G a low on W will

disable the outputs tWLQZ after W falls.

When E is low during the write, one of the on-

board TIMEKEEPER regi sters will be sel ected and

data will be written into the device. When EX is low

(and E is high) an external SRAM location is se-

lected.

Note: Care should be taken to avoid taking both E

and EX low simultaneously to avoid bus conten-

tion.

DATA RETENTION MODE

With valid VCC appl ied, the M48T212 A can be ac-

cessed as d escribed a bove with read or write cy-

cles. Should the supply voltage decay, the

M48T212A will automatically deselect, write pro-

tecting itself (and any external SRAM) when V CC

falls between VPFD (max) and VPFD (min ). This is

accomplished by inter nally inhibiting access to the

clock registers via the E signal. At this time, the

Reset pin (RST) is driven active and will remain

active until VCC returns t o nominal levels.

External RAM access is inhibited in a si milar man-

ner by forcing E1CON and E2CON to a high level.

This level is within 0.2V of the VBAT. E1CON and

E2CON wi ll rema in at this level as long as VCC re-

mains at an out-of tolerance condition.

When VCC falls below the level of the battery

(VBAT), power input is switched from the VCC pin

to the battery and t he clock registers a nd exte rnal

SRAM are maintained from the attached battery

supply. All outputs become high impedance. The

VOUT pin is capable of supplying 100µA of current

to the attached memory with less than 0.3V drop

under this condition. O n power up, when V CC re-

turns to a nominal value, write protection contin-

ues for 200ms (max) by inhibiting E1CON or

E2CON.

Figure 9. Alarm Interrupt Reset Waveforms

AI03021

A0-A3

ACTIVE FLAG BIT

ADDRESS 0h

IRQ/FT

HIGH-Z

1h Fh

11/20

M48T212A

The RST signal also remains active during this

time (see Figure 5).

Note: Most low power SRAMs on the market to-

day can be u sed with the M48T212A TIMEKEEP-

ER Controller. There are, however some criteria

which should be used in making the f inal choice of

an SRAM to use. The S RA M mus t be designed in

a way where the chip enable input disables all oth-

er inputs to the SRAM. This allows inputs to the

M48T212A and SRAMs to be Don’t Care once

VCC falls below VPFD(min). The SRAM should also

guarantee dat a retention down to VCC =2.0V. The

chip enable access time must be sufficient to meet

the system needs with the chip enable output

propagation delays included.

If the SRAM includes a second chip enable pin

(E2), thi s pin should be tied to VOUT.

If data rete ntio n lifetime is a c ri tical parameter for

th e syste m, it i s import ant t o review th e dat a reten-

tion current specifications for the particular

SRAMs being evaluated. Most SRAMs specify a

data retention current at 3.0V. Manufacturers gen-

erally specify a typical cond ition for room temper-

ature along with a wors t case con dition (gen erally

at elevated temperatures). The system level re-

quirements will determine the choice of which val-

ue to use.

The data retention current value of the SRAMs can

then be added to the IBAT value of the M48T 212A

to determine the total current requirements for

data retention. T he available battery capa city can

then be divided by this current to determine the

amount of data retention availabl e.

For a further more detailed review of lifetime calcu-

lations, please see Appl ication Not e AN1012.

Table 13. TIMEKEEPER Register M ap

Address Function/Range

BCD Format

D7 D6 D5 D4 D3 D2 D1 D0

Fh 10 Years Year Year 00-99

Eh 0 0 0 10M Month Month 01-12

Dh 0 0 10 Date Date: Day of Month Date 01-31

Ch 0 FT 0 0 0 Day of Week Day 01-7

Bh 0 0 10 Hours Hours (24 Hour Format) Hour 00-23

Ah 0 10 Minutes Minutes Min 00-59

9h ST 10 Seconds Seconds Sec 00-59

8h W R S Calibration Control

7h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog

6h AFE 0 ABE Al 10M Alarm Month A Month 01-12

5h RPT4 RPT5 AI 10 Date Alarm Date A Date 01-31

4h RPT3 0 AI 10 Hour Alarm Hour A Hour 00-23

3h RPT2 Alarm 10 Minutes Alarm Minutes A Min 00-59

2h RPT1 Alarm 10 Seconds Alarm Seconds A Sec 00-59

1h 1000 Year 100 Year Century 00-99

0h WDF AF Y BL Y Y Y Y Flag

Key s: S = Sign Bit

FT = Frequency Test Bit

R = Re ad Bit

W = Wri te Bit

ST = Stop Bit

0 = Must be set to zero

BL = Battery Low Flag

BMB0-BMB 4 = Watchd og M ultipli er Bits

AFE = Alarm Flag Enable Flag

R B0-RB 1 = Watc hd og Resolut ion Bits

WDS = Watchdog Steering Bit

ABE = Alarm in Battery Back-Up Mode Enable Bit

R PT1-RPT5 = Al arm Rep eat Mo de B i ts

WDF = Wat chdog flag

AF = Alarm flag

Y = ’1’ or ’0’

M48T212A

12/20

TIMEKEEPER REGISTERS

The M48T212A offers 16 internal registers which

contain TIMEKEEPER, Alarm, Watchdog, Flag,

and Control dat a. T hese regi s ters are m emory lo-

cations which contain external (user accessible)

and internal copies of the data (usually referred to

as Bi PORTTM TIMEKEEPER cells).

The external copies are independent of internal

functions except t hat they are updated periodically

by the simultaneous transfer of the incremented

in te r n a l c opy . TIMEKE EPER a nd Al a r m R e gisters

store data in BCD. Control, Watchdog and Flags

Registers store data in Binary Format.

CLOCK OPERATIONS

Reading the Clock

Updates to the TIMEKEEPER registers should be

halted bef ore clock data is read to prevent reading

data in transition. Because the BiPORT TIME-

KEEPER cells i n the RAM a rr a y are on l y d a ta reg-

isters, and not the actual clock counters, updating

the registers can b e halted without disturbing the

clock i tse l f.

Updating is halted when a ’1' is written to the

READ bit, D6 in the Control Regist er (8h). As long

as a `1' r emains in t hat position, updating is halted.

After a halt is issued, the registers reflect the

count; that is, the day, date, and time that were

current at the moment the halt command was is-

sued.

All of the TIMEKEEPER registe rs are update d si-

multaneously. A halt will not interrupt an update in

progress. Updating occurs 1 second after the

READ bit is reset to a ’0'.

Setting the Clock

Bit D7 of the Control Register (8h) is the WRITE

bit. Setting the WRITE bit to a `1', like the READ

bit, halts updates to the TIMEKEEPER registers.

The user can then load them with the correct da y,

date, and time data in 24 hour BCD format (see

Table 13).

Resetting the WRIT E bit to a `0' then transfers the

values of all t ime registers (Fh-9h, 1h) to the actual

TIMEKEEPER counters and allows normal opera-

tion to resume. After the WRITE bit is reset, the

next clock update will occ ur one second later.

Note: Upon power-up following a power failure,

the READ bi t will automatic al ly be s et to a ` 1'. This

will prevent the clock from updating the TIME-

KEEPER registers, and will allow the user to read

the exact time of the power-down event.

Res ett in g the R E AD Bit to a ` 0' w ill a llow the clo ck

to update these registers with the current time. The

WRITE Bit will be reset to a `0' upon powerup .

Stopping and Starting the Oscillator

The oscillator may be st opped at any time. If the de-

vice is going to spend a signi ficant am ount of time

on the shelf, t he oscillator can be t urned off to mi n-

imize current drain on the battery. The STO P bit is

located at Bit D7 within the Seconds Register (9h).

Setting it to a ’1' stops the oscillator. When reset to

a ’0', the M48T212A oscillator starts within one sec-

ond.

Note: It is not necessary to set the WRITE bit when

setting or resetting the FREQUENCY TEST bit (FT)

or the STOP bit (ST).

SETTING ALARM CLOCK REGISTERS

Address locations 6h-2h contain the alarm settings.

The alarm can be configured to go off at a pre-

scribed time on a specific month, date, hour,

minute, or second or repeat every year, month,

day, hour, minute, or second. It can also be pro-

grammed to go off while the M48T212A is in the

battery back-up to serve as a system wake-up cal l .

Bits RP T5-RPT1 pu t the alarm in t he repeat mo de

of operation. Table 12 sho ws the poss ible c onfigu-

rations. Codes no t listed in the table default to t he

once per second mode to quickly alert the user of

an incorrect alarm s ett ing.

When the clock information matches the alarm

clock settings b ased on the match criteria defined

by RPT5-RPT1, the AF (Alarm Flag) is set.

If AFE (Alarm Flag Enable) is also set, the alarm

condition activates the IRQ/FT pin. The IRQ/FT

output is cleared by a read to the F lags regist er as

shown in Figure 9. A s ubsequent read of the Flags

The IRQ/FT pi n can also be activat ed in the battery

back-up m ode. The IRQ/ FT w ill g o lo w if an alarm

occurs and both ABE (Alarm in Battery Back-up

Mode Enabl e) and AFE are set. The ABE and AFE

bits are reset during power-up, therefore an alarm

generated during power-up will only set AF. The

user can read the F lag Regist er at syst em boot-up

to determine if an alarm was generated while the

M48T212A was in the deselect mode during pow-

er-up. Figure 10 illustrates the back-up mode alarm

timing.

13/20

M48T212A

WATCHDOG TI MER

The watchdog timer can be used to detect an ou t-

of-control microprocessor. The us er program s the

watchdog timer by setting the desired amount of

time-out into the Watc hdog Regi ster, address 7h.

Bits BMB4-BM B0 store a binary multiplier and the

two lower order bits RB1-RB0 select the resolu-

tion, where 00=1/16 second, 01=1/4 second, 10=1

second, and 11=4 seconds. The amount of time-

out is then determined to be the multiplication of

the five bit mul tiplier value wi th the resolution. (For

example: writing 00 001110 in the Watchdo g Reg-

ister = 3*1 or 3 seconds). If the processor does not

reset the timer within the specified period, the

M48T212A sets the WDF (Watchdog Flag) and

generates a wat chdog interrupt or a m icroproces -

sor re set.

The most significa nt bit of the Watchdog Regi ster

is the Watc hdog Steering Bit (WDS). When set t o

a ‘0’, the watchdog will activate the IRQ/FT pin

when timed-out. When WDS is set to a ‘1’, the

watchdog will output a negative pul se on the RS T

pin for 40 to 200 ms. The W atchdog register and

the FT bit will reset to a ‘0’ at the end of a Watch-

dog time-out when the WDS bit is set to a ‘1’.

The watchdog timer can be reset by two methods:

1. a transition (high-to-low or low-to-high) can be

applied to the Watchdog Input pin (WDI) or

2. the microprocessor can perform a write of the

Watchdog Regi ster.

The time-out period then starts over. The WDI pin

should be tied to VSS if not used. The watchdog

will be reset on each transition (edge) seen by the

WDI pin. In the order to perform a software reset

of the watchdog timer, the original time-out period

can be written into the Watchd og Register, effec-

tively restarting the count-down cycle.

Should the wat chdog t imer time-out, and the WDS

bit is programmed to output an interrupt , a value of

00h needs to be written to the Watchdog Register

in order to clear the IRQ/FT pin. This will also dis-

able the watchdog function until it is again pro-

grammed correctly. A read of the Flags Register

will reset the Watchdog Flag (Bit D7; Register 0h).

The watchdog function is automatically disabled

upon power-up and the Watchdog Register is

cleared. If the watchdog function i s set t o output to

the IRQ /FT pin and the frequency test function is

activated, the watchdog function prevails and the

frequency test function is denied.

Figure 10. Back-Up Mode Alarm Waveforms

AI03622

VCC

IRQ/FT

HIGH-Z

VPFD (max)

VPFD (min)

AFE bit/ABE bit

AF bit in Flags Register

HIGH-Z

tREC

M48T212A

14/20

VCC SWITCH OUTPUT

Vccsw output goes low when VOUT switches to

VCC turning on a customer supplied P-Channel

MOSFET (see Figure 3). The Motorola

MTD20P06HDL is recommended. This MOSFET

in turn con nects VOUT to a sep arate supply when

the current requirement is greater than IOUT1 (see

Table 7). This output may also b e used simply to

indicate the status of the internal battery switcho-

ver comparator, which controls t he source (VCC or

battery) of the VOUT output.

POWER-ON RESET

The M48T212A continuously monitors VCC. When

VCC falls to t he power f ail detect t rip point, t he RST

pulls low (open drain) and rem ains low on power-

up for 40 to 200ms after VCC passes VPFD. The

RST pin i s an open d rain output and an appropri-

ate pull-up resistor to VCC should be chosen to

control rise time.

Note: If the RST output is fed back into either of

the RSTIN inputs (for a microprocessor with a bi-

directional reset ) then a 1kΩ (max) pull-up res istor

is recommended.

Reset Inputs (RSTIN1 & RSTIN2)

The M48T212A provides two independent inputs

which can generate an out put reset. The duration

and function of these resets is identical to a reset

generated by a power cycle. Table 14 and Fi gure

12 illustrate the AC reset characteristics of this

function. During the time RST is enabled (tR1HRH

& tR2HRH), the Reset Inputs are ignored.

Note: RSTIN1 and RSTIN2 are each internally

pulled up to VCC through a 100KΩ resistor.

Calibrating the Clo ck

The M48T212A is dr iven by a quartz controlled os-

cillator with a nominal frequency of 32,768 Hz. The

devices are tested not to exceed ±35 ppm (parts

per million) oscillator frequency error at 25°C,

which equates t o about ±1. 53 m inutes per mo nth.

When the Calibration circuit is prope rly employed,

accuracy improves to better than +1/–2 ppm at

25°C.

The oscillation rate of crystals chang es with tem-

perature. The M48T 212A design employ s per iodic

counter correction. The calibration circuit adds or

subtracts counts from the o scillator divider circuit

at the divide by 256 stage, as shown in Figure 11.

The number of times pulses which are blanked

(subtracted, negative calibration) or split (added,

positive calibration) depends upon the value load-

ed into the five Calibration bits found in the Control

tracting counts slows the clock down.

The Calibration bits occupy the five lower order

bits (D4-D0) in t he Control Regi ster 8h. These bits

can be set to represent a ny value betw een 0 and

31 in binary form. Bit D5 is a Sign bit; ’1’ indicates

positive calibration, ’0’ indicates negative calibra-

tion. Calibration occurs within a 64 minute cycle.

The first 62 minutes in the cycle may, once per

minute, have one second eit her short ened by 128

or lengthened by 256 os cill ator cycl es.

If a binary ’1' is loaded into the register, only the

first 2 minutes in the 64 minute cycle will be modi-

fied; if a binary 6 is loaded, the first 12 will be af-

fected, and so on.

Therefore, e ach calibration step ha s the effect of

adding 512 or subtracting 256 osc illator cycles for

every 125,829,120 actual oscillator cycles, that is

+4.068 or –2.034 ppm of adjustment per calibra-

tion step i n t he cal ibrat ion registe r. Ass um ing that

the oscillator is running at exactly 32,768 Hz, each

of the 31 increm ents in the Calibration byte wo uld

represent +10.7 or –5.35 seconds per month

which corresponds to a total range of +5. 5 or –2.75

minutes per month.

Two methods are available for ascertaining how

much calibration a gi ven M48T212 A may require.

The first involves setting the clock, l ett i ng it run for

a month and comparing it to a known accurat e ref-

erence and r ecor ding dev iation over a fixed period

of time. Calibration values, including t he number of

seconds lost or gained in a given period, can be

found in Application Note AN934: TIMEKEEPER

Calibration.

This allows the designer to g ive the end user the

ability to cali brate the clock as the environment re-

quires, even if the final product is packaged in a

non-user serviceable enclosure. The designer

could provide a simple utility that accesses the

Calibration byte.

The second approach is better suited to a manu-

facturing envi ronment, and involves the use of the

IRQ/FT pin. The pin will toggle at 512Hz, when the

Stop bit (ST, D7 of 9h) is ’0’, the Frequency T est

bit (FT, D6 of Ch) is ’1’ , the Alarm Flag E nabl e bit

(AFE, D7 of 6h) is ’0’, and the Wat chdog S teering

bit (WDS, D7 of 7h) is ’1’ or the Watchdog Regis ter

(7h = 0) is reset.

Any deviation from 512 Hz indicates the degree

and direction of oscillator frequency shift at the test

temperature. For example, a reading of

512.010124 Hz would indicate a +20 ppm oscilla-

tor frequency error, requiring a –10 (WR001010)

to be loaded into the Calibration Byte for correc-

tion. Note that setting or cha nging the Calibrat ion

Byte does not affect the Fr equency test output f re-

quency.

The IRQ/FT pin is an open d rain out put which re-

quires a pull-up resistor to VCC for proper opera-

tion. A 500-10kΩ resistor is recommended in order

to control the rise time. The FT bit is cleared on

power-up.

15/20

M48T212A

BATTERY LOW WARNING

The M48T212A automatically performs battery

voltage monitoring upo n power-up and at factory-

programmed time intervals of approximately 24

hours. The Battery Low (BL) bit, Bit D4 of Flags

is found to be less than approximately 2.5V. T he

BL bit wil l remain as serted until compl etion of bat -

tery replacement and subsequent battery low

monitoring tests, either during the next power-up

sequence or the next scheduled 24-hour interva l.

If a battery low is generated during a power-up se-

quence, this indicates that the battery is below ap-

proximately 2.5 volts and may not be able to

maintain data integrity in the SRAM. Data should

be considered suspect and verified as correct. A

fresh battery should be installed.

If a battery low indication is generated during the

24-hour interval check, this indicates that the bat-

tery is n ear end of lif e. However, data is not com -

promised due to the fact that a nominal Vcc is

supplied. In order to insure data integrity during

subsequent pe riods of bat tery back- up mode, the

battery should be replaced. The battery s hould be

replaced with VCC powering the device to avoid

data loss.

The M48T212A only monitors the battery when a

nominal Vcc i s applied to t he device. Thus appl ica-

tions whi ch require ext ensive durat ions in t he bat-

tery back-up mode should be powered-up

periodically (at least once every f ew months) i n or-

der for t his technique to be beneficial .

Additionally, if a battery low is indicated, data in-

tegrity should be verified upon power-up via a

checksum or other technique.

Note: B attery Low w arning is on ly valid whe n us-

ing a 3V button cel l battery. Use a super capacitor

for back-up supply causes the BL flag to be invalid.

INITIAL POWER-O N DEFAULTS

Upon application of power to the device, the fol-

lowing register bits are set to a ’0' state: WDS,

BMB0-BMB4, RB0-RB1, AFE, ABE, W and FT

(See Tabl e 16).

Table 14. Reset AC Characteristics

(TA = 0 to 70°C; VCC = 3V t o 3.6V)

Note : 1. Pulse width less than 50ns will result in no RESET (for noise immunity).

2. Pulse width less than 20ms will result in no RESET (for n oi se immunity).

3. CL = 5pF (see Figure 4).

Table 15. Crystal Electrical Ch aracteristi cs (External ly Supplied )

Note: Load capacitors are integrated within the M48T212A. Circuit board layout considerations for the 32kHz crystal of minimum trace

le ngths and is olat ion fro m R F genera tin g signal s s ho uld be t aken in to a ccou nt . S T rec omm ends the KD S D T-3 8 Tunin g Fork Typ e

quartz crystal for all temperature operations. KDS can be contacted at 913-491-6825 or at

http://www.kdsj.co.jp

for forther informa tion

on th is crystal type.

Symbol Parameter Min Max Unit

tR1 (1) RSTIN1 Low to RSTIN1 High 200 ns

tR2 (2) RSTIN2 Low to RSTIN2 High 100 ms

tR1HRH (3) RSTIN1 High to RST High 40 200 ms

tR2HRH (3) RSTIN2 High to RST High 40 200 ms

Symbol Description Min Typ Max Unit

fOResonant Frequency 32,768 kHz

RSSeries Resistance 50 70 kΩ

CLLoad Capacitance 12.5 pF

M48T212A

16/20

Figu re 11. Ca l ibr ati on W aveform

AI00594B

NORMAL

POSITIVE

CALIBRATION

NEGATIVE

CALIBRATION

Figure 12. RSTIN1 & RST IN2 Timi ng W aveform s

No te : 1. Wit h pul l -up resistor.

AI02642

RSTIN1

RST (1)

RSTIN2

tR1

tR1HRH

tR2

tR2HRH

Table 16. Default Values

No te: 1. WDS, BMB0-BMB4, RB0, RB1.

2. State of othe r contro l b its undefined.

3. State of othe r contro l b its rema i ns unchanged.

4. Assuming these bits set to ‘1’ prior to power-down.

Condition W R FT AFE ABE WATCHDOG

Initial Power-up

(Battery Attach for SNAPHAT) (2) 00000 0

RESET (3) 00000 0

Power-down (4) 01011 0

Subsequent Power-up 01000 0

17/20

M48T212A

Figure 13. Supply Voltage Protection

AI02169

VCC

0.1µF DEVICE

VCC

VSS

POWER SUPPLY DECOUPLING

AND UNDERSHOO T PROTECTION

Note: I CC transients, including th ose produce d by

output switching, can produce voltage fluctua-

tions, resulting in spikes on the VCC bus. These

transients can be reduced if capacitors are used to

store energy, which stabilizes the VCC bus. The

energy stored in the bypass c apacitors will be re-

leased as low going spikes are generat ed or ener-

gy will be a bsorbed when ov ershoot s occur.

A cerami c bypas s c apacit or val ue of 0.1µF is rec-

ommended in order to provide the needed filtering.

In addition to transients that are caused by normal

SRAM operation, power cy cling can generate neg-

ative voltage spikes on V CC that drive it to v alues

below VSS by as much as one volt. These negative

spikes can cause data corruption in the SRAM

while in battery backup mo de.

To protect from these voltage spikes, ST recom-

mends connecting a schottky diode from VCC to

VSS (cathode connected to VCC, anode to VSS).

(Schottky diode 1N5817 is recommended for

through hole and MBRS120T3 is recommended

for surface mount ).

M48T212A

18/20

Table 17. Ordering Information Scheme

For a list of availabl e options (S peed, P ack age, et c...) or for further information on any aspect of this de-

vice, pleas e contact the STM icroelectronics Sales Office nearest t o you.

Example: M48T212A -85 MH 1 TR

Device Type

M48T

Supply Voltage and Write Protect Voltage

212A = VCC = 3.0V to 3.6V; VPFD = 2.7V to 3.0V

Speed

-85 = 85ns

Package

MH = SOH44

Temperature Range

1 = 0 to 70 °C

6 = –40 to 85 °C

Shipping Method for SOIC

blank = Tubes

TR = Tape & Reel

Table 18. Revision History

Date Revision Details

October 1999 First Issue

03/01/00

SNAPHAT Battery & Crystal removed

Hardware Hookup scheme changed (Figure 3)

Back-Up Mode Alarm Waveforms changed (Figure 10)

Default Values Table added (Table 16)

SOH44 package silhouette, mechanical drawings and mechanical data changed (Figure 14)

19/20

M48T212A

Table 19. SOH44 - 44 lead Plastic Small Outline SNAPHAT, Package Mech an ical Data

Symb mm inches

Typ Min Max Typ Min Max

A 3.05 0.120

A1 0.05 0.36 0.002 0.014

A2 2.34 2.69 0.092 0.106

B 0.36 0.46 0.014 0.018

C 0.15 0.32 0.006 0.012

D 17.71 18.49 0.697 0.728

E 8.23 8.89 0.324 0.350

e 0.81 – – 0.032 – –

H 11.51 12.70 0.453 0.500

L 0.41 1.27 0.016 0.050

α0° 8° 0° 8°

N44 44

CP 0.10 0.004

Figure 14. SOH44 - 44 lead Plastic Small Outline SNAPHAT, Package Outlin e

Drawing is not to scale.

SOH-C

LA1 α

M48T212A

20/20

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