NT5SV8M16HS 128Mb Synchronous DRAM Feature Key Timing Parameters CL=CAS (Read) Latency) Access Time Clock Setup Hold Speed Grade Frequency CL2 CL3 Time Time -75B/-75BI 133 MHz 10 ns 7.5 ns 1.5 ns 0.8 ns -6K/-6KI 166 MHz - 6 ns 1.5 ns 1.0 ns z Single pulsed RAS Interface z Auto refresh (CBR) and self-refresh z Fully Synchronous to positive clock edge z Suspend mode and power down mode z Four banks controlled by BA0/BA1 (Bank Select) z Standard power operation z Programmable CAS Latency: 2, 3 z Random column address every CK (1-N Rule) z Programmable Burst Length: 1, 2, 4, 8 or full page z Single power supply - 3.30.3 V z Programmable Wrap. Sequential or interleave z LVTTL compatible z Multiple burst read with single write option z Packages: 54pin TSOP II z Automatic and controlled pre-charge commend z RoHS & Halogen Free Compliant z Dual data mask for byte controller 1 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM General Description The NT5SV8M16HS is four-bank Synchronous DRAMs organized as 2Mbit x 16 I/O x 4 Bank. These synchronous devices achieve high-speed data transfer rates of up to 166MHz (133MHz) by employing a pipeline chip architecture that synchronizes the output data to a system clock. The device is designed to comply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, and data input/output (I/O or DQ) circuits are synchronized with the positive edge of an externally supplied clock. RAS, CAS, WE, and CS are pulsed signals which are examined at the positive edge of each externally applied clock (CK). Internal chip operating modes are defined by combinations of these signals and a command decoder initiates the necessary timings for each operation. A fifteen bit address bus accepts address data in the conventional RAS/CAS multiplexing style. Twelve addresses (A0-A11) and two bank select addresses (BA0, BA1) are strobe with RAS, nine column addresses (A0-A8). Prior to any access operation, the CAS latency, burst length, and burst sequence must be programmed into the device by address inputs A0-A11, BA0, BA1 during a mode register set cycle. In addition, it is possible to program a multiple burst sequence with single write cycle for write through cache operation. Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 133MHz (or 166MHz) is possible depending on burst length, CAS latency, and speed grade of the device. Auto Refresh (CBR) and Self Refresh operation are supported. 2 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM Ordering Information Standard Grade Speed Organization 8M x 16 Part Number Package Clock (Mbps) CL-TRCD-TRP NT5SV8M16HS-75B 400mil 54-PIN 133 3-3-3 NT5SV8M16HS-6K TSOPII 166 3-3-3 Industrial Grade Speed Organization 8M x 16 Part Number Package Clock (Mbps) Clock (Mbps) NT5SV8M16HS-75BI 400mil 54-PIN 133 3-3-3 NT5SV8M16HS-6KI TSOPII 166 3-3-3 3 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM Pin Configuration - 54 Pin TSOPII (x16) < TOP View> See the balls through the package 4 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM Input / Output Functional Description Symbol Type CK Input Function Clock: The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. Clock Enable: Activates the CK signal when high and deactivates the CK signal when low. By CKE Input deactivating the clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode. Chip Select: CS enables the command decoder when low and disables the command decoder CS Input when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. Input Data Mask: The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In x16 products, the LDQM and UDQM control the lower and upper byte I/O buffers, respectively. In Read mode, DQM has a latency of two clock cycles and controls the output LDQM, UQDM Input buffers like an output enable. DQM low turns the output buffers on and DQM high turns them off. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if DQM is high. BA0 - BA1 Input Bank Address Inputs: Selects which bank is to be active. Address Inputs: During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11) when sampled at rising edge. During a Read or Write command cycle, A0-A8 defines the column (CA0-CA8) when sampled at A0 - A11 Input rising edge. During a Precharge command cycle, A10 is used to invoke autoprecharge operation at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled. DQ0 - DQ15 Input/output Data Inputs/Output: Data Input/Output pins operate in the same manner as on conventional DRAMs. VDD Supply Power Supply: VSS Supply Ground VDDQ Supply DQ Power Supply: VSSQ Supply DQ Ground NC 3.3V 0.3V 3.3V 0.3V No Connect: No internal electrical connection is present. 5 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM Ban k0 R ow-Ad dress Latch & De coder Bank Control Logic Refresh Counter 12 Address Register R ow-Ad dress MUX Control Logic C omman d De code Block Diagram 6 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM Power-up and Initialization The default power on state of the mode register is supplier specific and may be undefined. The following power on and initialization sequence guarantees the device is preconditioned to user's specific needs. The Synchronous DRAM must be powered up and initialized in a predefined manner. During power on, all VDD and VDDQ pins must be built up simultaneously to the specified voltage when the input signals are held in the "NOP" state. The power on voltage must not exceed VDD+0.3V on any of the input pins or VDD supplies. The CK signal must be started at the same time. After power on, an initial pause of 200s is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. A minimum of two Auto Refresh cycles are also required. These may be done before or after programming the Mode Register. Failure to follow these steps may lead to unpredictable start-up modes. Register Definition Programming the Mode Register For application flexibility, CAS latency, burst length, burst sequence, and operation type are user defined variables and must be programmed into the SDRAM Mode Register with a single Mode Register Set Command. Any content of the Mode Register can be altered by re-executing the Mode Register Set Command. If the user chooses to modify only a subset of the Mode Register variables, all four variables must be redefined when the Mode Register Set Command issued. After initial power up, the Mode Register Set Command must be issued before read or write cycles may begin. All banks must be in a precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The Mode Register Set Command is activated by the low signals of RAS, CAS, CS, and WE at the positive edge of the clock. The address input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new command may be issued following the mode register set command once a delay equal to tRSC has elapsed. CAS Latency The CAS latency is a parameter that is used to define the delay from a rising clock edge of Read Command to this Read Command becomes available at the outputs. The CAS latency expresses in terms of clock cycles and can have a value of 2 or 3 cycles. The value of the CAS latency is determined by the speed grade of the device and the clock frequency that uses in the application. A table showing the relationship between the CAS latency, speed grade, and clock frequency appears in the Electrical Characteristics section of this document. Once the appropriate CAS latency has been selected it must be programmed into the mode register after power up. 7 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM MRS Mode Register Operation Table (Address Input for Mode Set) 8 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM Burst Mode Operation Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). There are three parameters that define how the burst mode will operate. These parameters include burst sequence, burst length, and operation mode. The burst sequence and burst length are programmable, and are determined by address bits A0 - A3 during the Mode Register Set command. Operation mode is also programmable and is set by address bits A7 - A11, BA0, and BA1. The burst type is used to define the order in which the burst data will be delivered or stored to the SDRAM. Two types of burst sequences are supported, sequential and interleaved. See the table below. The burst length controls the number of bits that will be output after a Read Command, or the number of bits to be input after a Write Command. The burst length can be programmed to have values of 1, 2, 4, 8 and full page sequential burst. Burst operation mode can be normal operation or multiple burst with single write operation. Normal operation implies that the device will perform burst operations on both read and write cycles until the desired burst length is satisfied. Multiple burst with single write operation was added to support Write through Cache operation. Here, the programmed burst length only applies to read cycles. All write cycles are single write operations when this mode is selected. Burst Length and Sequence Burst Length Starting Address (A2 A1 A0) 2 4 8 256 (Full Page) Sequential Address (Decimal) Interleave Addressing (Decimal) X X 0 0 1 0 1 X X 1 1 0 1 0 X 0 0 0 1 2 3 0 1 2 3 X 0 1 1 2 3 0 1 0 3 2 X 1 0 2 3 0 1 2 3 0 1 X 1 1 3 0 1 2 3 2 1 0 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 n= A0-A7 Cn, Cn1+2, Cn+3, C+4, ... Not Support Note: Page Length is a function of I/O organization and column addressing. X16 configuration; Page Length=512 Bit. 9 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM Bank Activate Command In relation to the operation of a fast page mode DRAM, the Bank Activate command correlates to a falling RAS signal. The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock. The Bank Select address BA0 - BA1 is used to select the desired bank. The row address A0 - A11 is used to determine which row to activate in the selected bank. The Bank Activate command must be applied before any Read or Write operation can be executed. The delay from when the Bank Activate command is applied to when the first read or write operation can begin must meet or exceed the RAS to CAS delay time (tRCD). Once a bank has been activated it must be precharged before another Bank Activate command can be applied to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC). The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay time (tRRD). The maximum time that each bank can be held active is specified as tRAS(max). Bank Activate Command Cycle Bank Select Bits BA0 BA1 Bank 0 0 Bank 0 1 0 Bank 1 0 1 Bank 2 1 1 Bank 3 10 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM Read and Write Access Modes After Bank activated, a READ or WRITE cycle can be executed. This is accomplished setting RAS high and CAS low at the clock's rising edge after the necessary RAS to CAS delay (TRCD). WE must also be define at this time to determine whether the access cycle is on read operation (WE high), or a write operation (WE low). The address inputs determine the starting column address. The SDRAM provides a wide variety of fast access modes. A single Read or Write Command will initiate a serial read or write operation on successive clock cycles up to 133 MHz for PC133 or 166MHz for PC166 devices. The number of serial data bits for each access is equal to the burst length, which is programmed into the Mode Register. Similar to Page Mode of conventional DRAMs, a read or write cycle cannot begin until the sense amplifiers latch the selected row address information. The refresh period (tREF) is what limits the number of random column accesses to an activated bank. A new burst access can be done even before the previous burst ends. The ability to interrupt a burst operation at every clock cycle is supported; this is referred to as the 1-N rule. When the previous burst is interrupted by another Read or Write Command, the remaining addresses are overridden by the new address. Precharging an active bank after each Read or Write operation is not necessary providing the same row is to be accessed again. To perform a read or write cycle to a different row within an activated bank, the bank must be precharged and a new Bank Activate command must be issued. When more than one bank is activated, interleaved (ping pong) bank Read or Write operations are possible. By using the programmed burst length and alternating the access and precharge operations between multiple banks, fast and seamless data access operation among many different pages can be realized. When multiple banks are activated, column to column interleave operation can be done between different pages. Finally, Read or Write Commands can be issued to the same bank or between active banks on every clock cycle. Burst Read Command The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst, the Mode Register sets the type of burst (sequential or interleave) and the burst length (1, 2, 4, 8). The delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the CAS latency that is set in the Mode Register. Burst Read Operation 11 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM Read Interrupted by a Read A Burst Read may be interrupted before completion of the burst by another Read Command, with the only restriction being that the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the burst length. The data from the first Read Command continues to appear on the outputs until the CAS latency from the interrupting Read Command is satisfied, at this point the data from the interrupting Read Command appears. Read Interrupted by a Write To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will issue data on the first or second clocks cycles of the write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ bus. Read Interrupted by a Write 12 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM Non-Minimum Read to Write Interval Burst Write Command The Burst Write command is initiated by having CS, CAS, and WE low while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. There is no CAS latency required for burst write cycles. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. When the burst has finished, any additional data supplied to the DQ pins will be ignored. 13 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM Write Interrupted by a Write A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. Write Interrupted by a Read A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is registered. The DQs must be in the high impedance state at least one cycle before the interrupting read data appears on the outputs to avoid data contention. When the Read Command is registered, any residual data from the burst write cycle will be ignored. Data that is presented on the DQ pins before the Read Command is initiated will actually be written to the memory. Minimum Write to Read Interval (Burst Length = 4, T0 T1 T2 T3 T4 T5 T6 Latency =2 , 3) T8 T7 CK COMMAND WRITE A Latency = 2 tCK2, DQs latency = 3 t CK3, DQs READ B NOP DOUT B0 DIN A0 DIN A0 : "H or "L NOP NOP NOP NOP DOUT B1 DOUT B2 DOUT B3 DOUT B0 Input data for a WRITE is masked. DOUT B1 DOUT B2 NOP NOP DOUT B3 Input data must be removed from the DQs at least one clock Cycle before the Read data appears on the outputs to avoid data contention. 14 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM Non-Minimum Write to Read Interval Auto-Precharge Operation Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge Command or the auto-precharge function. When a Read or a Write Command is given to the SDRAM, the CAS timing accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is low when the Read or Write Command is issued, then normal Read or Write burst operation is executed and the bank remains active at the completion of the burst sequence. If A10 is high when the Read or Write Command is issued, then the auto-precharge function is engaged. During auto-precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge before all burst read cycles have been completed. Regardless of burst length, the precharge will begin (CAS latency - 1) clocks prior to the last data output. Auto-precharge can also be implemented during Write commands. A Read or Write Command without auto-precharge can be terminated in the midst of a burst operation. However, a Read or Write Command with auto-precharge cannot be interrupted by a command to the same bank. Therefore use of a Read (or Write, or Precharge) Command to the same bank is prohibited during a read (or write) cycle with auto-precharge until the entire burst operation is completed. Once the precharge operation has started the bank cannot be reactivated until the Precharge time (tRP) has been satisfied. When using the Auto-precharge Command, the interval between the Bank Activate Command and the beginning of the internal precharge operation must satisfy tRAS(min). If this interval does not satisfy tRAS(min) then tRCD must be extended. 15 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM Burst Read with Auto-Precharge: BL=1 Burst Read with Auto-Precharge: BL=2 Burst Read with Auto-Precharge: BL=4 16 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM Although a Read Command with auto-precharge cannot be interrupted by a command to the same bank, it can be interrupted by a Read or Write Command to a different bank. If the command is issued before auto-precharge begins then the precharge function will begin with the new command. The bank being auto-precharged may be reactivated after the delay tRP. Burst Read with Auto-Precharge Interrupted by Read If interrupting a Read Command with auto-precharge with a Write Command, DQM must be used to avoid DQ contention. Burst Read with Auto-Precharge Interrupted by Write 17 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The bank undergoing auto-precharge cannot be reactivated until tDAL, Data-in to Active delay, is satisfied. Burst Write with Auto-Precharge Similar to the Read Command, a Write Command with auto-precharge cannot be interrupted by a command to the same bank. It can be interrupted by a Read or Write Command to a different bank, however. The interrupting command will terminate the write. The bank undergoing auto-precharge cannot be reactivated until tDAL is satisfied. Burst Write with Auto-Precharge Interrupted by Write 18 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM Burst Write with Auto-Precharge Interrupted by Read Precharge Command The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is triggered when CS, RAS, and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge each bank separately or all banks simultaneously. Three address bits, A10, BA0, and BA1, are used to define which bank(s) is to be precharged when the command is issued. Bank Selection for Precharge by Address Bits A10 Bank select Precharge Bank(s) Low BA0, BA1 Single bank Defined by BA0, BA1 HIGH Don't Care All Banks. For read cycles, the Precharge Command may be applied (CAS latency - 1) prior to the last data output. For write cycles, a delay must be satisfied from the start of the last burst write cycle until the Precharge Command can be issued. This delay is known as tDPL, Data-in to Precharge delay. After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Precharge time (tRP). 19 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM Burst Read Followed by the Precharge Command Burst Write Followed by the Precharge Command 20 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM Precharge Termination The Precharge Command may be used to terminate either a burst read or burst write operation. When the Precharge command is issued, the burst operation is terminated and bank precharge begins. For burst read operations, valid data will continue to appear on the data bus as a function of CAS Latency. Burst Read Interrupted by Precharge Burst write operations will be terminated by the Precharge command. The last write data that will be properly stored in the device is that write data that is presented to the device a number of clock cycles prior to the Precharge command equal to the Data-in to Precharge delay, tDPL. Precharge Termination of a Burst Write (Burst Length = 8, T0 T1 T2 T3 T4 T5 T6 Latency =2 , 3) T8 T7 CK COMMAND NOP NOP WRITE AX0 NOP NOP NOP Precharge A NOP NOP DQM tDPL Latency = 2 tCK2, DQs DIN Ax0 DIN Ax1 DIN Ax2 tDPL Latency = 3 tCK2, DQs DIN Ax1 DIN Ax0 DIN B0 Note: 21 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM Automatic Refresh Command (CAS before RAS Refresh) When CS, RAS, and CAS are held low with CKE and WE high at the rising edge of the clock, the chip enters the Automatic Refresh mode (CBR). All banks of the SDRAM must be precharged and idle for a minimum of the Precharge time (tRP) before the Auto Refresh Command (CBR) can be applied. An address counter, internal to the device provides the address during the refresh cycle. No control of the external address pins is required once this cycle has started. When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the Auto Refresh Command (CBR) and the next Activate Command or subsequent Auto Refresh Command must be greater than or equal to the RAS cycle time (tRC). Self Refresh Command The SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command is defined by having CS, RAS, CAS, and CKE held low with WE high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command. Once the command is registered, CKE must be held low to keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self Refresh Operation to save power. The user may halt the external clock while the device is in Self Refresh mode, however, the clock must be restarted before the device can exit Self Refresh operation. Once the clock is cycling, the device will exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the device exits Self Refresh Operation and before the next command can be issued. This delay is equal to the RAS cycle time (tRC) plus the Self Refresh exit time (tSREX). Power Down Mode In order to reduce standby power consumption, two power down modes are available: Precharge and Active Power Down mode. To enter Precharge Power Down mode, all banks must be precharged and the necessary precharge delay (tRP) must occur before the SDRAM can enter the power down mode. If a bank is activated but not performing a Read or Write operation, Active Power Down mode will be entered. (Issuing a Power Down Mode Command when the device is performing a Read or Write operation causes the device to enter Clock Suspend mode. See the following Clock Suspend section.) Once the Power Down mode is initiated by holding CKE low, all of the receiver circuits except CKE are gated off. The Power Down mode does not perform any refresh operations, therefore the device can't remain in Power Down mode longer than the Refresh period (tREF) of the device. The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command (or Device Deselect Command) is required on the next rising clock edge. 22 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM Power Down Mode Exit Timing Data Mask The SDRAM has a Data Mask function that can be used in conjunction with data read and write cycles. When the Data Mask is activated (DQM high) during a write cycle, the write operation is prohibited immediately (zero clock latency). If the Data Mask is activated during a read cycle, the data outputs are disabled and become high impedance after a two-clock delay, independent of CAS latency. Data Mask Activated during a Read Cycle 23 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM No Operation Command The No Operation Command should be used in cases when the SDRAM is in an idle or a wait state. The purpose of the No Operation Command is to prevent the SDRAM from registering any unwanted commands between operations. A No Operation Command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle. Deselect Command The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is brought high, the RAS, CAS, and WE signals become don't cares. Clock Suspend Mode During normal access mode, CKE is held high, enabling the clock. When CKE is registered low while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends or "freezes" any clocked operation that was currently being executed. There is a one-clock delay between the registration of CKE low and the time at which the SDRAM's operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high to when Clock Suspend mode is exited. When the operation of the SDRAM is suspended during the execution of a Burst Read operation, the last valid data output onto the DQ pins will be actively held valid until Clock Suspend mode is exited. Clock Suspend during a Read Cycle If Clock Suspend mode is initiated during a burst write operation, the input data is masked and is ignored until the Clock Suspend mode is exited. 24 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM Clock Suspend during a Write Cycle 25 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM Command Truth Table (See note 1) CKE BA0, Function Device State Previous Current CS RAS CAS WE DQM A11, A10 Notes BA1 Mode Register Set Auto (CBR) A9-A0 Cycle Cycle Idle H X L L L L X Idle H H L L L H X X X X Idle H L L L L H X X X X L H H X X X L H H H X X X X H X L L H L X BS L X H X L L H L X X H X OP Code Refresh Entry Self Refresh Idle SelfExit Self Refresh Refresh Single Bank See Current Precharge State Table Precharge all See Current Banks State Table Bank Activate Idle H X L L H H X BS Row Address 2 Write Active H X L H L L X BS L Column 2 Active H X L H L L X BS H Column 2 Active H X L H L H X BS L Column 2 Active H X L H L H X BS H Column 2 Reserved - H X L H H L X X X X No Operation Any H X L H H H X X X X Device Deselect Any H X H X X X X X X X Activate H L X X X X X X X X Write with 2 Auto-Precharge Read Read with Auto-precharge Clock Suspend Mode Entry Clock Suspend 1 Activate L H X X X X X X X X Activate H X X X X X L X X X Mode Exit Data Write/ Output Enable Data Mask/ 5 Activate H X X X X X H X X X Output Disable 26 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM CKE BA0, Function Device State Previous Current CS RAS CAS WE DQM A11, A10 BA1 Power Down Mode Idle/Activate Cycle Cycle H L L H Entry Power Down Mode Any (Power Entry Down) 1. H X X X L H H H H X X X L H H H Notes A9-A0 X X X X 6, 7 X X X X 6, 7 All of the SDRAM operations are defined by states of CS, WE, RAS, CAS, and DQM at the positive rising edge of the clock. Refer to the Current State Truth Table. 2. Bank Select (BA0, BA1): BA0, BA1 = 0,0 selects bank 0; BA0, BA1 = 1,0 selects bank 1; BA0, BA1 = 0,1 selects bank 2; BA0, BA1 = 1,1 selects bank 3. 3. Not applicable. 4. During normal access mode, CKE is held high and CK is enabled. When it is low, it freezes the internal clock and extends data Read and Write operations. One clock delay is required for mode entry and exit. 5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the data outputs are disabled and become high impedance after a two-clock delay. DQM also provides a data mask function for Write cycles. When it activates, the Write operation at the clock is prohibited (zero clock latency). 6. All banks must be precharged before entering the Power Down Mode. (If this command is issued during a burst operation, the device state will be Clock Suspend Mode.) The Power Down Mode does not perform any refresh operations; therefore the device can't remain in this mode longer than the Refresh period (tREF) of the device. One clock delay is required for mode entry and exit. 7. A No Operation or Device Deselect Command is required on the next clock edge following CKE going high. 27 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM Clock Enable (CKE) Truth Table CKE Current State Previous Command Action Current CS RAS CAS WE BA0, BA1 A11-A0 Cycle Cycle H X X X X X X X L H H X X X X X L H L H H H X X L H L H H L X X ILLEGAL 2 L H L H L X X X ILLEGAL 2 L H L L X X X X ILLEGAL 2 L L X X X X X X Maintain Self Refresh H X X X X X X X INVALID L H H X X X X X Self Refresh INVALID Exit Self Refresh with Device Deselect Exit Self Refresh with no operation Power Down mode exit, all 1 2 2 1 2 banks idle Power Down CB All Banks Idle Notes L H L X X X X X ILLEGAL L L X X X X X X Maintain Power Down Mode H H H X X X Refer to the Idle State 3 H H L H X X section of the Current State 3 H H L L H X Truth Table 3 H H L L L H H H L L L L H L H X X H L L H H L L H L H X X OP Code 2 CBR Refresh Mode Register Set 4 X Refer to the Idle State 3 X X section of the Current State 3 L H X Truth Table. 3 L L L H Entry Self Refresh 4 L L L L L L X X X X X X X H H X X X X X X X X Op Code Mode Register Set Power Down 4 Refer to operations in the Current State Truth Table. Any State other H L X X X X X X Begin Clock Suspend next cycle L H X X X X X X Exit Clock Suspend next cycle L L X X X X X X Maintain Clock Suspend 5 than listed above 28 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM 1. For the given Current State CKE must be low in the previous cycle. 2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE (tCES) must be satisfied. When exiting power down mode, a NOP command (or Device Deselect Command) is required on the first rising clock after CKE goes high (see page 26). 3. The address inputs depend on the command that is issued. See the Idle State section of the Current State Truth Table for more information. 4. The Precharge Power Down Mode, the Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle state. 5. Must be a legal command as defined in the Current State Truth Table. 29 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM Current State Truth Table (See note 1) Command Current Description State Action BA0, BA1 RAS CAS WE Mode Register Set L L L L Auto/Self Refresh L L L H X X Start Auto/Self Refresh Precharge L L H L BS X No Operation Bank Activate L L H H BS OP Code Idle Row Active Notes A11-A0 CS Set the Mode Register Row Activate the specified bank and Address row 2 2,3 Write w/o Precharge L H L L BS Column ILLEGAL 4 Read w/o Precharge L H L H BS Column ILLEGAL 4 No Operation L H H H X X No Operation Device Deselect H X X X X X No Operation or Power Down Mode Register Set L L L L Auto/Self Refresh L L L H X X ILLEGAL Precharge L L H L BS X Precharge 6 Bank Activate L L H H BS ILLEGAL 4 Write L H L L BS Column Read L H L H BS Column No Operation L H H H X X No Operation Device Deselect H X X X X X No Operation Mode Register Set L L L L Auto/Self Refresh L L L H X X Precharge L L H L BS X OP Code 5 ILLEGAL Row Address OP Code Start Write; Determine if Auto-Precharge Start Write; Determine if Auto-Precharge 7, 8 7, 8 ILLEGAL ILLEGAL Terminate Burst; Start the Precharge Read Row Bank Activate L L H H BS Write L H L L BS Column Read L H L H BS Column Burst Stop L H H L X X Burst Stop No Operation L H H H X X Continue the Burst Device Deselect H X X X X X Continue the Burst Address ILLEGAL Terminate Burst; Start the Write cycle Terminate Burst; Start the Read cycle 4 8,9 8,9 30 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM Command Current Description State Action BA0, BA1 Notes A11-A0 CS RAS CAS WE Mode Register Set L L L L Auto/Self Refresh L L L H X X Precharge L L H L BS X OP Code ILLEGAL ILLEGAL Terminate Burst; Start the Precharge Write Bank Activate L L H H BS Write L H L L BS Row Address Column ILLEGAL Terminate Burst; Start a new 4 8,9 Write cycle Read L H L H BS Column Terminate Burst; Start the Read 8,9 cycle Burst Stop L H H L X X Burst Stop No Operation L H H H X X Continue the Burst Device Deselect H X X X X X Continue the Burst Mode Register Set L L L L Auto/Self Refresh L L L H X X ILLEGAL Precharge L L H L BS X ILLEGAL 4 Bank Activate L L H H BS ILLEGAL 4 Write L H L L BS Column ILLEGAL 4 Read L H L H BS Column ILLEGAL 4 No Operation L H H H X X Continue the Burst Device Deselect L X X X X X Continue the Burst Mode Register Set L L L L Auto/Self Refresh L L L H X X ILLEGAL Precharge L L H L BS X ILLEGAL 4 Bank Activate L L H H BS ILLEGAL 4 Write L H L L BS Column ILLEGAL 4 Read L H L H BS Column ILLEGAL 4 No Operation L H H H X X Continue the Burst Device Deselect L X X X X X Continue the Burst OP Code Read with Auto Precharge Precharge Row Address OP Code Write with Auto ILLEGAL ILLEGAL Row Address 31 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM Command Current Description State Action BA0, BA1 Notes A11-A0 CS RAS CS WE Mode Register Set L L L L Auto/Self Refresh L L L H X X Precharge L L H L BS X OP Code ILLEGAL ILLEGAL No Operation; Bank(s) idle after tRP Precharging Bank Activate L L H H BS Write L H L L BS Read L H L H No Operation L H H H Row ILLEGAL 4 Column ILLEGAL 4 BS Column ILLEGAL 4 X X Address No Operation; Bank(s) idle after tRP Device Deselect H X X X X X No Operation; Bank(s) idle after tRP Mode Register Set L L L L OP Code Auto/Self Refresh L L L H X X ILLEGAL Precharge L L H L BS X ILLEGAL 4 Bank Activate L L H H BS ILLEGAL 4,10 Write L H L L BS Column ILLEGAL 4 Read L H L H BS Column ILLEGAL 4 No Operation L H H H X X Row Activating ILLEGAL Row Address No Operation; Row Active after tRCD Device Deselect H X X X X X No Operation; Row Active after tRCD Write Mode Register Set L L L L OP Code Auto/Self Refresh L L L H X X ILLEGAL Precharge L L H L BS X ILLEGAL 4 Bank Activate L L H H BS ILLEGAL 4 Write L H L L BS Column Start Write; Determine if Auto 9 Read L H L H BS Column Precharge 9 No Operation L H H H X X No Operation; Row Active after Device Deselect H X X X X X tDPL Recovering ILLEGAL Row Address 32 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM Command Current Description State Action BA0, BA1 Notes A11-A0 CS RAS CS WE Mode Register Set L L L L Auto/Self Refresh L L L H X X ILLEGAL Precharge L L H L BS X ILLEGAL 4 Bank Activate L L H H BS ILLEGAL 4 Write L H L L BS OP Code ILLEGAL Row Address Write Recovering Column 9 Precharge with Auto Precharge Start Write; Determine if Auto Read L H L H BS Column Start Write; Determine if Auto 9 Precharge No Operation L H H H X X No Operation; Row Active after tDPL Device Deselect H X X X X X No Operation; Row Active after tDPL Mode Register Set L L L L OP Code Auto/Self Refresh L L L H X X ILLEGAL Precharge L L H L BS X ILLEGAL Bank Activate L L H H BS Write L H L L BS Column ILLEGAL Read L H L H BS Column ILLEGAL No Operation L H H H X X No Operation; Idle after tRC Device Deselect H X X X X X No Operation; Idle after tRC Mode Register Set L L L L Auto/Self Refresh L L L H X X ILLEGAL Precharge L L H L BS X ILLEGAL Bank Activate L L H H BS Write L H L L BS Column ILLEGAL Read L H L H BS Column ILLEGAL No Operation L H H H X X Refreshing Mode Register Accessing ILLEGAL Row Address OP Code ILLEGAL ILLEGAL Row Address ILLEGAL No Operation; Idle after two clock cycles Device Deselect H X X X X X No Operation; Idle after two clock cycles 33 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM 1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is being applied to. 2. All Banks must be idle; otherwise, it is an illegal action. 3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is entered. 4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation. 6. The minimum and maximum Active time (tRAS) must be satisfied. 7. The RAS to CAS Delay (tRCD) must occur before the command is given. 8. Column address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied. Absolute Maximum Ratings Symbol Parameter Unit Notes VDD Power Supply Voltage -1.0 to +4.6 V 1 VDDQ Power Supply Voltage for Output -1.0 to +4.6 V 1 Input Voltage -0.3 to VDD + 0.3 V 1 Output Voltage -0.3 to VDD + 0.3 V 1 0 to +70 1 -40 to +85 1 -55 to +150 1 Power Dissipation 1.0 W 1 Short Circuit Output Current 50 mA 1 VIN VOUT Commercial TA Operating Temperature (ambient) Industrial TSTG PD IOUT 1. Rating Storage Temperature Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 34 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM Recommended DC Operating Conditions Rating Symbol Parameter Minimum Typical Maximum Unite Notes VDD Supply Voltage 3.0 3.3 3.6 V 1 VDDQ Supply Voltage for Out put 3.0 3.3 3.6 V 1 VIH Input High Voltage 2.0 3.0 VDD + 0.3 V 1, 2 VIL Input Low Voltage -0.3 0 0.8 V 1, 3 VOH Output Logic High Voltage 2.4 - - V IoH = -2mA VOL Output Logic Low Voltage - - 0.4 V IoH = -2mA 1. All voltages referenced to VSS and VSSQ. 2. VIH (max) = VDD + 2.3V for pulse width 3ns. 3. VIL (min) = VSS - 2.0V for pulse width 3ns. Capacitance (TA = 23C, f = 1MHz, VDD = 3.3V, VREF=1.4+/-200mV) Symbol Parameter Min. Max. Units CIN Input Capacitance (A0-A11, BS0, BS1, CS, RAS, CAS, WE, CKE, DQM) 2.5 3.8 pF CADD Address 2.5 3.8 pF CCLK Input Clock (CLK) 2.5 3.5 pF COUT Output Capacitance (DQ0 - DQ15) 4.0 6.0 pF DC Electrical Characteristics (VDD = 3.3V 0.3V) Symbol II(L) Parameter Input Leakage Current, any input (0.0V VIN VDD), All Other Pins Not Under Test = 0V Min. Typ. Max. Units -1 - +1 A Note 1 VIH Output Level (LVTTL) 2.0 3.0 VDD+0.3 V 2 VIL Output Level (LVTTL) -0.3 0 0.8 V 3 2.4 - - V - - 0.4 V VOH VOL Output Level (LVTTL) Output "H" Level Voltage (IOUT = -2.0mA) Output Level (LVTTL) Output "L" Level Voltage (IOUT = +2.0mA) Notes: 1. 2. 3. Any input 0V VIN VDDQ Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. VIH (max) = 5.6V AC. The overshoot voltage duration is 3ns. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 35 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM DC Output Load Circuit 36 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM Operating, Standby, and Refresh Currents Max. Parameter Symbol Test Condition 6K 6KI 75B 75BI 130 130 90 90 Units Notes mA 1,2,3 mA 1 Burst length=1, One bank active Operating Current IDD1 tRC tRC(min), IOL=0mA Precharge Standby Current IDD2P CKE VIL(max), tCK = 10ns 4 4 4 4 in Power Down Mode IDD2PS CKE & CLK VIL(max), tCK= 4 4 4 4 Precharge Standby Current IDD2N 20 20 20 20 IDD2NS CKE VIH(min), CS VIH(min), tCK = 15ns Input signals are changed one time during 2clks.All other pins VDD-0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable. Active standby current in IDD3P power-down mode Active Standby Current in Non PowerDown Mode in Non Power Down Mode Burst Mode Operating 10 10 10 10 CKE VIL(max), tCK = 15ns 10 10 10 10 IDD3PS CKE VIL(max), tCK = 10 10 10 10 IDD3N CKE VIH(min), CS VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.2V 35 35 35 35 IDD3NS CKE VIH(min), tCK = stable. IDD4 tCK tCK(min), IOL=0mA Current , Input signals are 1,5 mA 1,7 mA 1.6 mA 1.5 30 30 30 30 150 150 110 110 mA 1,3,4 220 220 200 200 mA 1 2 2 4 4 mA 1 All banks active Auto Refresh Current IDD5 tRC tRC(min), All banks active Self Refresh Current IDD6 CKE 0.2V Normal Low Power 1. Currents given are valid for a single device. . 2. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of tCK and tRC. Input signals are changed up to three times during tRC(min). 3. The specified values are obtained with the output open. 4. Input signals are changed once during tCK(min). 5. Input signals are changed once during three clock cycles. 6. Active Standby Current will be higher if Clock Suspend is entered during a burst read cycle (add 1mA per DQ). 7. Input signals are stable. 37 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM AC Characteristics (VDD = 3.3V 0.3V) 1. An initial pause of 200s, with DQM and CKE held high, is required after power-up. A Precharge All Banks command must be given followed by a minimum of two Auto (CBR) Refresh cycles before or after the Mode Register Set operation. 2. The Transition time is measured between VIH and VIL (or between VIL and VIH) 3. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 4. Load Circuit A: AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.40V crossover point 5. Load Circuit A: AC measurements assume tT = 1.0ns AC Characteristics Diagrams tT VIH t CKL Clock t SETUP t CKH 1.4V VIL Vtt = 1.4V 50 Output Zo = 50 t HOLD 50pF AC Output Load Circuit (A) Input 1.4V tAC tOH tLZ Output 1.4V 38 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM Operating AC Parameters -6K/-6KI Symbol tCK tAC tOH -75B/-75BI Parameter Units Min. Max. Min. Max. Clock Cycle Time, CAS Latency = 3 6 1000 7.5 1000 ns Clock Cycle Time, CAS Latency = 2 - - 10 1000 ns Clock Access Time, CAS Latency = 3 - 5 - 5.4 ns Clock Access Time, CAS Latency = 2 - 6 - 6 ns Output data hold time, CAS Latency = 3 2.5 - 3 - ns Output data hold time, CAS Latency = 2 3 3 Notes ns tCH Clock High Pulse Width 2.5 - 2.5 - ns tCL Clock Low Pulse Width 2.5 - 2.5 - ns tIS Input Setup Time 1.5 - 1.5 - ns tIH Input Hold Time 1 - 0.8 - ns tSLZ CLK to Output in Low-Z 1 - 1 - ns CLK to Output in Hi-Z, CAS Latency = 3 0.3 8 0.5 10 ns CLK to Output in Hi-Z, CAS Latency = 2 1.5 - 1.5 - ns tRRD Bank to Bank Delay Time 12 - 15 - ns 1 tRCD RAS to CAS Delay 18 - 20 - ns 1 tRP Precharge Time 18 - 20 - ns 1 tRAS Active Command Period 42 100K 45 100K ns 1 tRC Bank Cycle Time 60 - 65 - ns 1 tRDL Last Data Into Row Precharge 2 - 2 - CLK tDAL Last Data Into Active Delay 2 CLK + tRP - 2 CLK + tRP - - tCDL Last Data Into new Col. Address 1 - 1 - CLK tBDL Last Data Into Burst Stop 1 - 1 - CLK tCCD CAS to CAS Delay Time 1 - 1 - CLK tRSC Mode Register Set Cycle Time 12 - 15 - ns tOH Data Out Hold Time 2.5 - 2.7 - ns tLZ Data Out to Low Impedance Time 0 - 0 - ns tHZ Data Out to High Impedance Time 3 6 3 7 ns tDQZ DQM Data Out Disable Latency 2 - 2 - CK tREF Mode Register Set Cycle Time - 64 - 64 ms tSREX Self Refresh Exit Time 1 - 1 - CK tDS Data In Set-up Time 1.5 - 1.5 - ns tSHZ Delay 2, 4 3 5 39 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM tDH Data In Hold Time tDPL 1 - 0.8 - ns Data input to Precharge 12 - 15 - ns tWR Write Recovery Time 12 - 15 - ns tDAL3 Data In to Active Delay, CAS Latency = 3 5 - 5 - CK tDAL2 Data In to Active Delay, CAS Latency = 2 4 - 4 - CK tDQW DQM Write Mask Latency 0 - 2 - CK 1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing / clock period (count fractions as a whole number). 2. AC Output Load Circuit B. 3. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. 4. Data Out Hold Time with no load must meet 1.8ns 5. 4096 auto refresh cycles. 40 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM Bank2,3 = Idle *BA0 = "L" AC Parameters for Write Timing 41 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. REV 1.7 Dec 2011 Hi -Z * BA0 = L Bank2,3 = Idle DQ DQM A0-A9, A11 A10 * BA1 WE CAS RAS CS CKE CK RA x RA x T1 A ctiv ate Co m ma n d B a nk 0 T0 tR C D tC K 3 T2 CA x tRA S T4 Re a d wi th A uto Pre ch arg e Com m an d Ba nk 0 t R RD T3 T6 Ac ti vate Co mm a nd Ba n k 1 tA C3 RB x RB x tRC T5 A x0 t OH A x1 Be gin Auto Pre ch arg e Ba n k 0 T7 tR P Ax2 CB x T9 Rea d with Auto Pre ch arg e Com man d B a nk 1 T8 Ax3 T1 0 Bx 0 R Ay RA y B x1 Be gin Auto Pr ec harg e Ba n k 1 T12 Ac tivate Co m ma n d Ba n k 0 T 11 T1 3 Bx2 (Burst length = 4, CAS latency = 3; tRCD, tR P = 3) NT5SV8M16HS 128Mb Synchronous DRAM AC Parameters for Read Timing (3/3/3) 42 CONSUMER DRAM NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. (c) NANYA TECHNOLOGY CORP. All rights reserved. NT5SV8M16HS 128Mb Synchronous DRAM AC Parameters for Read Timing (3/3/3) 43 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. REV 1.7 Dec 2011 DQ DQM A0-A9 A10,A11 BA0,BA1 WE CAS RAS CS CKE CK Hi -Z T0 T3 T4 T5 Mo d e Re gister S et Co mm an d T6 An y Co mm a nd t RSC A ddre ss Ke y t RP T2 Pr ec harg e Com ma n d A ll Ba nk s t CK2 T1 T7 T8 T9 T1 0 T1 1 T1 2 T 13 T14 T1 5 T1 6 T1 7 T18 ( T1 9 T2 0 T 21 T2 2 latency = 2) NT5SV8M16HS 128Mb Synchronous DRAM Mode Register Set 44 CONSUMER DRAM NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. (c) NANYA TECHNOLOGY CORP. All rights reserved. REV 1.7 Dec 2011 DQ DQM A0-A9, A11 A10 BS C KE CK tCK T2 T3 T4 P re ch arg e 1s t Auto Refre sh Co m ma n d Co m ma n d Al l B a nk s tR P High level is required T1 I nput s must be s table for 200 s Hi -Z T0 T5 T7 T8 T9 T1 0 T1 1 T1 2 8th Auto Refre sh Co mm a n d T 14 tRC T1 3 Minimum of 8 R ef resh Cy cles are required T6 T1 5 T1 8 Mo d e Re gis ter S et Co mm a n d T1 9 An y Co mm a nd 2 Clock min. T17 A ddre s s Ke y T16 T2 0 T21 T22 NT5SV8M16HS 128Mb Synchronous DRAM Power-On Sequence and Auto Refresh (CBR) 45 CONSUMER DRAM NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. (c) NANYA TECHNOLOGY CORP. All rights reserved. REV 1.7 Dec 2011 Hi-Z BA0= L Bank2,3=I dle * DQ DQM A0-A9, A11 A10 * BA1 WE CAS RAS CS CKE CK RA x RA x tCK 3 T1 A ctiv ate Co m ma n d B an k 0 T0 T2 CA x T4 Re a d Co mm a nd Ba n k 0 T3 t CES T5 T6 Ax 0 A x1 tCEH T8 T9 Clo ck Su sp e n d 1 Cy cle T7 T1 1 Cl oc k S us pe n d 2 Cycl e s Ax2 T10 T12 Ax3 T1 4 T15 Clo ck Su sp e n d 3 Cy cle s T13 T1 6 A x4 T1 7 T 18 T1 9 A x6 tHZ T2 0 Ax7 T2 1 T2 2 (Burst length = 8, CAS latency = 3; tRC D = 3) NT5SV8M16HS 128Mb Synchronous DRAM Clock Suspension / DQ during Burst Read 46 CONSUMER DRAM NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. (c) NANYA TECHNOLOGY CORP. All rights reserved. REV 1.7 Dec 2011 Hi- Z Bank2, 3=I dle * BA0=L DQ DQM A0-A9, A10 * BA1 WE CAS RAS CS CKE CK RA x RA x tCK3 T1 Activate Command Bank 0 T0 T2 CA x T4 DA x 1 T5 Write Command Bank 0 Clock Suspend 1 Cycle DA x0 T3 T7 T8 DA x 2 Clock Suspend 2 Cycles T6 T9 T1 1 DA x 3 T1 2 Clock Suspend 3 Cycles T1 0 T13 T14 T1 6 DA x 5 T15 DAx 6 T1 7 (Burst length = 8, DA x7 T1 8 T1 9 T2 0 T21 T2 2 latency = 3; tR CD = 3) NT5SV8M16HS 128Mb Synchronous DRAM Clock Suspension / DQM during Burst Write 47 CONSUMER DRAM NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. (c) NANYA TECHNOLOGY CORP. All rights reserved. NT5SV8M16HS 128Mb Synchronous DRAM Power Down Mode and Clock Suspend 48 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM Pre ch a rg e Co m ma n d A ll B a nk s DQ DQ M A0-A9, A11 A10 BS CKE CK Hi -Z T0 T1 t CK2 tRP T2 T3 A uto R efre sh Co m ma n d T4 T5 T6 tRC T7 T8 T9 T1 0 Auto Refre sh C o mm a nd T1 1 T1 2 T1 3 tR C T14 T1 5 T1 6 T1 7 T1 8 ( T1 9 T2 0 T2 1 latency = 2) T2 2 Auto Refresh (CBR) 49 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. REV 1.7 Dec 2011 DQ DQM A0-A9, A11 A10 BS WE C AS R AS CS C KE CK A ll Ba n ks m u st be i dl e Hi -Z T0 tC E S T1 tS B T3 T4 P ow er Do wn Entry S el f R efre s h Entry T2 tC E S Tm Tm+3 Tm+4 P ow er D o wn Ex it Self R efre sh E xi t tS R E X Tm+ 1 Tm+2 A ny C om m an d Tm+7 Tm+8 Tm+9 Tm+1 0 Tm+11 Tm+12 Tm+13 tR C Tm+5 Tm+6 Tm+14 Tm+15 (Note: The CK signal must be reestablished prior to CKE returning high.) NT5SV8M16HS 128Mb Synchronous DRAM Self Refresh (Entry and Exit) 50 CONSUMER DRAM NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. (c) NANYA TECHNOLOGY CORP. All rights reserved. REV 1.7 Dec 2011 * BA0=L Bank 2, 3=Idle DQ Acti vate Co mm an d Ba n k 1 RB x A0-A9, A11 DQM RB x Hi-Z Hi gh A10 * BA1 CKE CK T0 tRCD tCK 3 T1 CB x T3 Re a d Co mm an d Ba n k 1 T2 T4 tA C3 T5 Bx0 Bx1 RA x RA x T7 Ac ti vate Co mm an d Ba nk 0 T6 Bx2 T8 Bx3 Bx 4 CA x Bx 5 T1 0 Rea d Co mm a nd Ba nk 0 T9 T1 2 P re ch ar ge Co mm a nd Ba n k 1 Bx6 T1 1 Ax0 T13 A x1 R By R By T15 Ac tivate Co m ma nd B an k 1 T14 Ax4 T1 6 Ax6 T1 8 Rea d Co m ma nd B ank 1 Ax5 CB y T17 A x7 T1 9 By0 T2 1 Pre ch arg e Co m ma n d B ank 0 T2 0 T2 2 (Burst length = 8, CAS latency = 3; tRC D, tRP = 3) NT5SV8M16HS 128Mb Synchronous DRAM Random Row Read (Interleaving Banks) with Precharge 51 CONSUMER DRAM NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. (c) NANYA TECHNOLOGY CORP. All rights reserved. REV 1.7 Dec 2011 Hi-Z RBx RBx High Bank2,3=Idle A ctiv ate Com ma n d * BA0=L B a nk 1 DQ DQ M A0-A9, A11 A10 * BA1 C KE CK T0 T2 CBx T3 Re a d with Auto P re ch ar ge Co m ma n d B ank 1 tR C D tC K3 T1 T4 tA C3 T5 Bx0 T6 Bx1 Bx 2 RA x RAx RA x RAx T8 A cti vate Com ma n d Ba nk 0 T7 Bx 3 T9 Bx5 Bx6 Re ad with Auto Pr ec harg e Co mm a nd Ba n k 0 Bx4 T1 1 T1 2 T1 3 Bx 7 Ax0 S tart A uto Prech arg e B an k 1 CAx T10 T1 4 Ax1 T1 7 T1 8 RBy RBy Ax 5 Ax6 T1 9 Re ad with Auto P re ch arg e Co m ma nd B ank 1 A x4 CBy Start Auto Pr ec harg e Ba nk 0 T16 A ctiv ate Com ma n d B a nk 1 T1 5 Ax7 T2 0 T21 By0 T2 2 (Burst length = 8,C AS latency = 3; tRC D, tRP = 3) NT5SV8M16HS 128Mb Synchronous DRAM Random Row Read (Interleaving Banks) with Auto-Precharge 52 CONSUMER DRAM NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. (c) NANYA TECHNOLOGY CORP. All rights reserved. REV 1.7 Dec 2011 Ac ti vate C o mm a nd Ba n k 0 * BA0=L Bank2,3=Idle DQ Hi- Z RA x A0-A9, A11 DQ M RA x Hig h A10 * BA1 CKE CK T0 C AX DA x 0 T2 DA x 1 T3 Wr ite wi th Auto P rec ha rg e Co mm a nd Ba n k 0 tR C D tC K 3 T1 T4 T5 DA x 4 T6 RB x RB x DA x 6 T8 A ctiv ate Co m ma n d B an k 1 DA x5 T7 DB x 0 CB x T1 0 DB x 1 T11 W rite with Auto P re ch arge Com ma n d B an k 1 DA x 7 T9 T1 3 DB x 3 DB x4 T1 4 RA y RA y T16 Acti vate Co mm an d Ba nk 0 DB x5 T1 5 T1 7 DB x 6 T1 8 DA y 0 CA y T2 0 DA y 1 D Ay 2 T2 2 tD AL T21 Wri te with A uto Pre ch arg e C om ma n d Ba nk 0 DB x 7 T1 9 latency = 3; tRCD, tRP = 3) Number of clocks depends on clock cycle ti me and speed sort. See the Clock Fr equency and Latency table. Bank may be reactivated at the completion of tDA L . DB x 2 tD A L T12 (Burst length = 8, NT5SV8M16HS 128Mb Synchronous DRAM Random Row Write (Interleaving Banks) with Auto-Precharge 53 CONSUMER DRAM NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. (c) NANYA TECHNOLOGY CORP. All rights reserved. REV 1.7 Dec 2011 Hi- Z A ctiv ate Co m ma n d B an k 0 RA x RA x Hig h * BA0=L Bank2,3=Idl e DQ DQM A0-A9, A11 A10 * BA1 CKE CK T0 t RCD t CK3 T1 CA X D Ax1 T3 Wri te C o mm a nd Ba n k 0 DA x0 T2 T4 T5 D A x4 T6 R Bx R Bx D Ax 6 T8 Ac tiv ate C o m ma n d B an k 1 DA x 5 T7 DA x 7 T9 DB x 1 T1 1 W ri te Com m an d B a nk 1 DB x 0 CB x T1 0 DB x 3 T1 3 Pre c harg e Com m an d B a nk 0 DB x 2 T1 2 D Bx 4 tRP T1 4 RA y RA y T1 6 Ac ti vate Co mm a n d Ba n k 0 DB x 5 T1 5 (Burst length = 8, T1 7 DB x 6 T1 8 DB x 7 T1 9 CA y DAy2 W rite Co m ma n d B a nk 0 P re ch ar ge C o mm a nd DA y0 T2 2 DA y1 T2 1 tD P L T2 0 latency = 3; tRC D, tRP = 3) NT5SV8M16HS 128Mb Synchronous DRAM Random Row Write (Interleaving Banks) with Precharge 54 CONSUMER DRAM NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. (c) NANYA TECHNOLOGY CORP. All rights reserved. REV 1.7 Dec 2011 * BA0=L Bank2,3=Idle DQ Acti vate Co mm an d Ba n k0 RA x A0-A9, A 11 Hi-Z RA x DQM T1 tC K 3 A10 * BA1 CKE CK T0 T2 CA x T4 Re a d Co mm an d Ba n k 0 T3 T5 T6 A x0 T7 A x1 T8 A x3 T1 0 D Ay0 DA y 1 T1 2 C Ay T1 1 T13 DAy3 T14 Th e Re ad Data Wr ite The Wri te Data is M aske d wi th a Co mm a nd i s M as ke d with a Two Cl o ck Ba n k 0 Zero Cl oc k Late nc y L aten cy Ax2 T9 DA y4 T1 5 T1 6 (Burst length = 8, T1 8 Pre ch arg e Co m ma n d B an k 0 T17 T1 9 T2 0 T2 1 T2 2 latency = 3; tRC D, tRP = 3) NT5SV8M16HS 128Mb Synchronous DRAM Read / Write Cycle 55 CONSUMER DRAM NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. (c) NANYA TECHNOLOGY CORP. All rights reserved. REV 1.7 Dec 2011 Hi-Z DQ BA0=L Bank2, 3=Idle * tC K3 T1 A cti vate C om m a nd B ank 0 RA x A0-A9, A11 DQM RA x A10 * BA1 CKE CK T0 t RCD T2 CA x T4 RB x RB x T5 A ctiv ate Co m ma n d B an k 1 R ea d Co mm a n d Ba n k 0 T3 Ax0 t AC3 T6 A x1 CB x T8 Re a d Com m a nd B ank 1 T7 Ax2 Ax3 CB y T1 0 Rea d Co m ma n d Ba n k 1 T9 Bx0 T1 2 Re a d Co m m an d B a nk 1 B x1 CB z T 11 By1 CA y T1 4 Bz0 T15 Bz1 T 16 R ea d with P re ch arg e A uto Pr e ch a rg e Co m ma n d Co mm a n d B an k 1 Ba n k 0 By0 T1 3 (Burst length = 4, Ay0 T1 7 T1 9 T2 0 A y1 Ay2 Ay3 S tar t Auto P re c ha rg e B a nk 0 T1 8 T2 1 T2 2 latency = 3; tR CD, tRP = 3) NT5SV8M16HS 128Mb Synchronous DRAM Interleaved Column Read Cycle 56 CONSUMER DRAM NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. (c) NANYA TECHNOLOGY CORP. All rights reserved. REV 1.7 Dec 2011 DQ * BA0=L Bank2,3= Idle A cti vate C om m a nd B a nk 0 RA x A0-A9, A11 DQM RA x Hi -Z Hi g h A10 * BA1 WE CAS RAS CS CKE CK T0 tCK3 T1 CA x T3 RB x RB x T4 A cti vate C om m a nd Read B ank 1 C o mm a n d Ba n k 0 T2 T5 A x1 CB x T7 A x2 R e a d wi th Auto P re n c harg e Co m m an d Ba k 1 A x0 T6 T8 Ax 3 T9 Bx 1 T 12 Bx2 R e a d wi th A uto Pare ch a rg e C o m ma n d B nk 0 Bx0 T1 1 T1 3 Bx3 T 14 RB y RB y Ac tiv ate C o m ma n d B an k 1 Ay0 Sta rt A uto P re ch a rg e Ba n k 1 CA y T1 0 T1 6 CB y T1 7 Ay1 Ay3 R e a d with Auto Pre c harg e C om m a nd B ank 1 Ay2 S ta rt Auto Pre c h ar ge B ank 0 T1 5 T1 8 T2 0 T2 1 B y0 By1 S ta rt A uto P re ch a rg e B ank 1 T 19 (Burst length = 4, CAS latency = 3; tR CD, tRP = 3) T 22 NT5SV8M16HS 128Mb Synchronous DRAM Auto Precharge after Read Burst 57 CONSUMER DRAM NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. (c) NANYA TECHNOLOGY CORP. All rights reserved. REV 1.7 Dec 2011 Bank2,3= Idle * BA0=L DQ Acti vate Co mm an d Ba n k 0 RA x A0-A9, A11 DQM RA x Hi-Z Hi gh A10 * BA1 CKE CK T0 DA x1 T2 Wri te Co mm an d Ba n k 0 DA x 0 CA x t CK 2 T1 R Bx R Bx T4 DA x 3 CBx DB x 0 T5 T6 DB x1 Write wi th A ctivate A uto P re charg e Co mm an d C om ma nd B an k 1 B an k 1 DAx 2 T3 T7 DBx 2 T8 DA y0 DA y 1 t DA L CA y T1 0 DA y 2 RB y DAy 3 T12 RB y T1 1 RA z RA z DBy 3 T16 DA z0 CA z T17 DA z 1 T1 8 B a nk m a y be re a ctiv ate d at the co mpletio n of t DAL . N um b er of cl oc ks d ep e nd s o n clo ck c ycl e a n d s pe e d s or t. Se e th e Cl oc k Fre qu e n cy a nd L ate n cy ta bl e. W rite wi th Ac ti vate Auto P rec harg e Co mm an d Co mm an d Ba n k 0 B an k 0 DB y2 T15 DB y 1 tD AL CB y T1 4 DB y0 T13 Wri te with Wri te with Acti vate Auto Pre ch arg e Auto Pr ech arge C o mma n d Com ma n d C o mm an d Ba nk 1 Ba nk 0 Ba n k 1 DB x 3 T9 DA z 2 T19 DAz 3 T2 0 T2 2 tD AL T2 1 (Burst l ength = 4, CA S laten cy = 2) NT5SV8M16HS 128Mb Synchronous DRAM Auto Precharge after Write Burst 58 CONSUMER DRAM NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. (c) NANYA TECHNOLOGY CORP. All rights reserved. NT5SV8M16HS 128Mb Synchronous DRAM Burst Read and Single Write Operation 59 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. REV 1.7 Dec 2011 DQ DQM Hi- Z Low A0-A9, A11 A10 BA0,BA1 CKE CK T0 T2 A cti vate C om m a nd B ank A RA x RA x t CK3 T1 tRC D T3 T5 Read C o mm a nd Ba n k A T4 CA x T6 T7 Ax0 T8 Ax1 T9 A x2 Ax3 T 10 T1 1 W ri te C o m m an d B a nk A D Ay 2 T1 4 DA y 1 T1 3 DA y 0 CA y T1 2 DA y 3 T1 5 P re ch a rg e C o mm a n d Ba n k A T 18 T1 9 T2 0 T2 1 T2 2 Latency = 3, tR CD, tRP = 3) T1 7 t DPL T1 6 (at 100MHz Burst Length = 4, NT5SV8M16HS 128Mb Synchronous DRAM CS Function (Only CS signal needs to be asserted at minimum rate) 60 CONSUMER DRAM NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. (c) NANYA TECHNOLOGY CORP. All rights reserved. NT5SV8M16HS 128Mb Synchronous DRAM Package Dimensions (400mil; 54 lead; Thin Small Outline Package) 0.13 0.13 0.20 11.76 Detail A 10.16 22.22 Lead #1 Seating Plane 0.10 0.80 Basic 0.35 + 0.10 - 0.05 0.71REF 1.20 Max Detail A 0.25 Basic 0.5 0.05 Min Gage Plane 0.1 61 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM Revision Log Rev Date Modification 0.1 02/2010 Preliminary Release. 1.0 03/2010 Official Release. 1.1 04/2010 1.2 04/2010 II(L) data modified on Page-35. 1.3 06/2010 Delete AC Parameters for Read Timing (2/2/2) &(3/2/2) 1.4 07/2010 Modified IDD Specification 1.5 07/2010 Modified 6K/6KI IDD6 Specification 1.6 03/2011 1.7 12/2011 1. Add Full Page mode on MRS setting on Page-8. 2. Complete IDD parameter on Page-37. 1. Revised the Symbol of Data Out Hold Time 2. Revised the unit of tRDL/tCDL /tBDL/tCCD Re-organized AC Parameter Table 62 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT5SV8M16HS 128Mb Synchronous DRAM (R) Nanya Technology Corporation. All rights reserved. Printed in Taiwan, R.O.C., 2011 The following are trademarks of NANYA TECHNOLOGY CORPORATION in R.O.C, or other countries, or both. NANYA and NANYA logo Other company, product and service names may be trademarks or service marks of others. NANYA TECHNOLOGY CORPORATION (NTC) reserves the right to make changes without notice. NTC warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with NTC's standard warranty. Testing and other quality control techniques are utilize to the extent NTC deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ("Critical Applications"). NTC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTEND, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. Inclusion of NTC products in such applications is understood to be fully at the risk of the customer. Use of NTC products in such applications requires the written approval of an appropriate NTC officer. Question concerning potential risk applications should be directed to NTC through a local sales office. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards should be provided by customer to minimize the inherent or procedural hazards.NTC assumes no liability of applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does NTC warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of NTC covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. NANYA TECHNOLOGY CORPORATION HWA YA Technology Park 669, FU HSING 3rd Rd., Kueishan, Taoyuan, Taiwan, R.O.C. The NANYA TECHNOLOGY CORPORATION Home page can be found at http:\\www.nanya.com 63 REV 1.7 CONSUMER DRAM (c) NANYA TECHNOLOGY CORP. All rights reserved. Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.