NT5SV8M16HS
128Mb Synchronous DRAM
1
REV 1.7 CONSUMER DRAM
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Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Feature
Key Timing Parameters CL=CAS (Read) Latency)
Speed Grade Clock
Frequency
Access Time Setup
Time
Hold
Time
CL2 CL3
-75B/-75BI 133 MHz 10 ns 7.5 ns 1.5 ns 0.8 ns
-6K/-6KI 166 MHz - 6 ns 1.5 ns 1.0 ns
z Single pulsed RAS Interface
z Fully Synchronous to positive clock edge
z Four banks controlled by BA0/BA1 (Bank Select)
z Programmable CAS Latency: 2, 3
z Programmable Burst Length: 1, 2, 4, 8 or full page
z Programmable Wrap. Sequential or interleave
z Multiple burst read with single write option
z Automatic and controlled pre-charge commend
z Dual data mask for byte controller
z Auto refresh (CBR) and self-refresh
z Suspend mode and power down mode
z Standard power operation
z Random column address every CK (1-N Rule)
z Single power supply – 3.3±0.3 V
z LVTTL compatible
z Packages: 54pin TSOP II
z RoHS & Halogen Free Compliant
NT5SV8M16HS
128Mb Synchronous DRAM
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REV 1.7 CONSUMER DRAM
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General Description
The NT5SV8M16HS is four-bank Synchronous DRAMs organized as 2Mbit x 16 I/O x 4 Bank. These synchronous devices
achieve high-speed data transfer rates of up to 166MHz (133MHz) by employing a pipeline chip architecture that
synchronizes the output data to a system clock.
The device is designed to comply with all JEDEC standards set for synchronous DRAM products, both electrically and
mechanically. All of the control, address, and data input/output (I/O or DQ) circuits are synchronized with the positive edge
of an externally supplied clock.
RAS, CAS, WE, and CS are pulsed signals which are examined at the positive edge of each externally applied clock (CK).
Internal chip operating modes are defined by combinations of these signals and a command decoder initiates the
necessary timings for each operation. A fifteen bit address bus accepts address data in the conventional RAS/CAS mul-
tiplexing style. Twelve addresses (A0-A11) and two bank select addresses (BA0, BA1) are strobe with RAS, nine column
addresses (A0-A8).
Prior to any access operation, the CAS latency, burst length, and burst sequence must be programmed into the device by
address inputs A0-A11, BA0, BA1 during a mode register set cycle. In addition, it is possible to program a multiple burst
sequence with single write cycle for write through cache operation.
Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is
possible with standard DRAMs. A sequential and gapless data rate of up to 133MHz (or 166MHz) is possible depending on
burst length, CAS latency, and speed grade of the device. Auto Refresh (CBR) and Self Refresh operation are supported.
NT5SV8M16HS
128Mb Synchronous DRAM
3
REV 1.7 CONSUMER DRAM
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Ordering Information
Standard Gr ade
Organization Part Number Package Speed
Clock (Mbps) CL-TRCD-TRP
8M x 16 NT5SV8M16HS-75B 400mil 54-PIN
TSOPII
133 3-3-3
NT5SV8M16HS-6K 166 3-3-3
Industrial Grade
Organization Part Number Package Speed
Clock (Mbps) Clock (Mbps)
8M x 16 NT5SV8M16HS-75BI 400mil 54-PIN
TSOPII
133 3-3-3
NT5SV8M16HS-6KI 166 3-3-3
NT5SV8M16HS
128Mb Synchronous DRAM
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REV 1.7 CONSUMER DRAM
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Pin Configuration – 54 Pin TSOPII (x16)
< TOP View>
See the balls through the package
NT5SV8M16HS
128Mb Synchronous DRAM
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REV 1.7 CONSUMER DRAM
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Input / Output Functional Description
Symbol Type Function
CK Input
Clock: The system clock input. All of the SDRAM inputs are sampled on the rising edge of the
clock.
CKE Input
Clock Enable: Activates the CK signal when high and deactivates the CK signal when low. By
deactivating the clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh
mode.
CS Input
Chip Select: CS enables the command decoder when low and disables the command decoder
when high. When the command decoder is disabled, new commands are ignored but previous
operations continue.
RAS, CAS, WE Input
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
LDQM, UQDM Input
Input Data Mask: The Data Input/Output mask places the DQ buffers in a high impedance state
when sampled high. In x16 products, the LDQM and UDQM control the lower and upper byte I/O
buffers, respectively. In Read mode, DQM has a latency of two clock cycles and controls the output
buffers like an output enable. DQM low turns the output buffers on and DQM high turns them off. In
Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be
written if it is low but blocks the write operation if DQM is high.
BA0 – BA1 Input Bank Address Inputs: Selects which bank is to be active.
A0 – A11 Input
Address Inputs:
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11) when
sampled at rising edge.
During a Read or Write command cycle, A0-A8 defines the column (CA0-CA8) when sampled at
rising edge.
During a Precharge command cycle, A10 is used to invoke autoprecharge operation at the end of
the burst read or write cycle. If A10 is high, autoprecharge is selected and BA0, BA1 defines the
bank to be precharged. If A10 is low, autoprecharge is disabled.
DQ0 – DQ15 Input/output Data Inputs/Output: Data Input/Output pins operate in the same manner as on conventional
DRAMs.
VDD Supply
Power Supply: 3.3V ± 0.3V
VSS Supply
Ground
VDDQ Supply
DQ Power Supply: 3.3V ± 0.3V
VSSQ Supply
DQ Ground
NC No Connect: No internal electrical connection is present.
NT5SV8M16HS
128Mb Synchronous DRAM
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REV 1.7 CONSUMER DRAM
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Block Diagram
Control Logic
Command
De code
Refresh Counter Row-Address MUX
12
Ban k0
Row-Address Latch
&Decoder
Address Register
Bank Control Logic
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128Mb Synchronous DRAM
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Power-up and Initialization
The default power on state of the mode register is supplier specific and may be undefined. The following power on and
initialization sequence guarantees the device is preconditioned to user’s specific needs.
The Synchronous DRAM must be powered up and initialized in a predefined manner. During power on, all VDD and VDDQ
pins must be built up simultaneously to the specified voltage when the input signals are held in the “NOP” state. The power
on voltage must not exceed VDD+0.3V on any of the input pins or VDD supplies. The CK signal must be started at the
same time. After power on, an initial pause of 200µs is required followed by a precharge of all banks using the precharge
command. To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held
high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be
issued to initialize the Mode Register. A minimum of two Auto Refresh cycles are also required. These may be done before
or after programming the Mode Register. Failure to follow these steps may lead to unpredictable start-up modes.
Register Definition
Programming the Mode Register
For application flexibility, CAS latency, burst length, burst sequence, and operation type are user defined variables and
must be programmed into the SDRAM Mode Register with a single Mode Register Set Command. Any content of the Mode
Register can be altered by re-executing the Mode Register Set Command. If the user chooses to modify only a subset of
the Mode Register variables, all four variables must be redefined when the Mode Register Set Command issued.
After initial power up, the Mode Register Set Command must be issued before read or write cycles may begin. All banks
must be in a precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be
issued. The Mode Register Set Command is activated by the low signals of RAS, CAS, CS, and WE at the positive edge of
the clock. The address input data during this cycle defines the parameters to be set as shown in the Mode Register
Operation table. A new command may be issued following the mode register set command once a delay equal to tRSC has
elapsed.
CAS Latency
The CAS latency is a parameter that is used to define the delay from a rising clock edge of Read Command to this Read
Command becomes available at the outputs. The CAS latency expresses in terms of clock cycles and can have a value of 2
or 3 cycles. The value of the CAS latency is determined by the speed grade of the device and the clock frequency that uses
in the application. A table showing the relationship between the CAS latency, speed grade, and clock frequency appears in
the Electrical Characteristics section of this document. Once the appropriate CAS latency has been selected it must be
programmed into the mode register after power up.
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128Mb Synchronous DRAM
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MRS Mode Register Operation Table (Address Input for Mode Set)
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128Mb Synchronous DRAM
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REV 1.7 CONSUMER DRAM
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Burst Mode Operation
Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations
(read cycle). There are three parameters that define how the burst mode will operate. These parameters include burst
sequence, burst length, and operation mode. The burst sequence and burst length are programmable, and are determined
by address bits A0 - A3 during the Mode Register Set command. Operation mode is also programmable and is set by
address bits A7 - A11, BA0, and BA1.
The burst type is used to define the order in which the burst data will be delivered or stored to the SDRAM. Two types of
burst sequences are supported, sequential and interleaved. See the table below.
The burst length controls the number of bits that will be output after a Read Command, or the number of bits to be input
after a Write Command. The burst length can be programmed to have values of 1, 2, 4, 8 and full page sequential burst.
Burst operation mode can be normal operation or multiple burst with single write operation. Normal operation implies that
the device will perform burst operations on both read and write cycles until the desired burst length is satisfied. Multiple
burst with single write operation was added to support Write through Cache operation. Here, the programmed burst length
only applies to read cycles. All write cycles are single write operations when this mode is selected.
Burst Length and Sequence
Burst Length Starting Address (A2 A1 A0) Sequential Address (Decimal) Interleave Addressing (Decimal)
2
X X 0 0 1 0 1
X X 1 1 0 1 0
4
X 0 0 0 1 2 3 0 1 2 3
X 0 1 1 2 3 0 1 0 3 2
X 1 0 2 3 0 1 2 3 0 1
X 1 1 3 0 1 2 3 2 1 0
8
0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6
0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5
0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4
1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3
1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2
1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1
1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0
256
(Full Page)
n= A0-A7 Cn, Cn1+2, Cn+3, C+4, ... Not Support
Note: Page Length is a function of I/O organization and column addressing. X16 configuration; Page Length=512 Bit.
NT5SV8M16HS
128Mb Synchronous DRAM
10
REV 1.7 CONSUMER DRAM
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Bank Activate Command
In relation to the operation of a fast page mode DRAM, the Bank Activate command correlates to a falling RAS signal. The
Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock. The
Bank Select address BA0 - BA1 is used to select the desired bank. The row address A0 - A11 is used to determine which
row to activate in the selected bank.
The Bank Activate command must be applied before any Read or Write operation can be executed. The delay from when
the Bank Activate command is applied to when the first read or write operation can begin must meet or exceed the RAS to
CAS delay time (tRCD). Once a bank has been activated it must be precharged before another Bank Activate command can
be applied to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is
determined by the RAS cycle time of the device (tRC). The minimum time interval between interleaved Bank Activate
commands (Bank A to Bank B and vice versa) is the Bank to Bank delay time (tRRD). The maximum time that each bank can
be held active is specified as tRAS(max).
Bank Activate Command Cycle
Bank Select Bits
BA0 BA1 Bank
0 0 Bank 0
1 0 Bank 1
0 1 Bank 2
1 1 Bank 3
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128Mb Synchronous DRAM
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Read and Write Access Modes
After Bank activated, a READ or WRITE cycle can be executed. This is accomplished setting RAS high and CAS low at the
clock’s rising edge after the necessary RAS to CAS delay (TRCD). WE must also be define at this time to determine whether
the access cycle is on read operation (WE high), or a write operation (WE low). The address inputs determine the starting
column address.
The SDRAM provides a wide variety of fast access modes. A single Read or Write Command will initiate a serial read or
write operation on successive clock cycles up to 133 MHz for PC133 or 166MHz for PC166 devices. The number of serial
data bits for each access is equal to the burst length, which is programmed into the Mode Register.
Similar to Page Mode of conventional DRAMs, a read or write cycle cannot begin until the sense amplifiers latch the
selected row address information. The refresh period (tREF) is what limits the number of random column accesses to an
activated bank. A new burst access can be done even before the previous burst ends. The ability to interrupt a burst
operation at every clock cycle is supported; this is referred to as the 1-N rule. When the previous burst is interrupted by
another Read or Write Command, the remaining addresses are overridden by the new address.
Precharging an active bank after each Read or Write operation is not necessary providing the same row is to be accessed
again. To perform a read or write cycle to a different row within an activated bank, the bank must be precharged and a new
Bank Activate command must be issued. When more than one bank is activated, interleaved (ping pong) bank Read or
Write operations are possible. By using the programmed burst length and alternating the access and precharge operations
between multiple banks, fast and seamless data access operation among many different pages can be realized. When
multiple banks are activated, column to column interleave operation can be done between different pages. Finally, Read or
Write Commands can be issued to the same bank or between active banks on every clock cycle.
Burst Read Command
The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the
clock. The address inputs determine the starting column address for the burst, the Mode Register sets the type of burst
(sequential or interleave) and the burst length (1, 2, 4, 8). The delay from the start of the command to when the data from
the first cell appears on the outputs is equal to the value of the CAS latency that is set in the Mode Register.
Burst Read Operation
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Read Interrupted by a Read
A Burst Read may be interrupted before completion of the burst by another Read Command, with the only restriction being
that the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the
remaining addresses are overridden by the new address with the burst length. The data from the first Read Command
continues to appear on the outputs until the CAS latency from the interrupting Read Command is satisfied, at this point the
data from the interrupting Read Command appears.
Read Interrupted by a Write
To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high
impedance state to avoid data contention on the DQ bus. If a Read Command will issue data on the first or second clocks
cycles of the write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have
control of the DQ bus.
Read Interrupted by a Write
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128Mb Synchronous DRAM
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Non-Minimum Read to Write Interval
Burst Write Command
The Burst Write command is initiated by having CS, CAS, and WE low while holding RAS high at the rising edge of the clock.
The address inputs determine the starting column address. There is no CAS latency required for burst write cycles. Data for
the first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The
remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. When the
burst has finished, any additional data supplied to the DQ pins will be ignored.
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128Mb Synchronous DRAM
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Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is
interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the
programmed burst length is satisfied.
Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is registered. The
DQs must be in the high impedance state at least one cycle before the interrupting read data appears on the outputs to
avoid data contention. When the Read Command is registered, any residual data from the burst write cycle will be ignored.
Data that is presented on the DQ pins before the Read Command is initiated will actually be written to the memory.
Minimum Write to Read Interval
(Burst Length = 4, Latency =2 , 3)
CK
T0 T2T1 T3 T4 T5 T6 T7 T8
COMMAND
Latency = 2
tCK3,DQs
latency = 3
tCK2,DQs
READ B NOP
WRITE A NOP NOP NOP NOP NOP NOP
DIN A0
DIN A0
DOUT B0DOUT B3
DOUT B2
DOUT B1
Input data for a WRITE is
masked.
: “H＂or “L＂
Input data must be removed from the DQs at least one clock Cycle before
the Read data appears on the outputs to avoid data contention.
DOUT B0DOUT B3
DOUT B2
DOUT B1
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128Mb Synchronous DRAM
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Non-Minimum Write to Read Interval
Auto-Precharge Operation
Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge
Command or the auto-precharge function. When a Read or a Write Command is given to the SDRAM, the CAS timing
accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at the earliest
possible moment during the burst read or write cycle. If A10 is low when the Read or Write Command is issued, then
normal Read or Write burst operation is executed and the bank remains active at the completion of the burst sequence. If
A10 is high when the Read or Write Command is issued, then the auto-precharge function is engaged. During
auto-precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge
before all burst read cycles have been completed.
Regardless of burst length, the precharge will begin (CAS latency - 1) clocks prior to the last data output. Auto-precharge
can also be implemented during Write commands.
A Read or Write Command without auto-precharge can be terminated in the midst of a burst operation. However, a Read or
Write Command with auto-precharge cannot be interrupted by a command to the same bank. Therefore use of a Read (or
Write, or Precharge) Command to the same bank is prohibited during a read (or write) cycle with auto-precharge until the
entire burst operation is completed. Once the precharge operation has started the bank cannot be reactivated until the
Precharge time (tRP) has been satisfied.
When using the Auto-precharge Command, the interval between the Bank Activate Command and the beginning of the
internal precharge operation must satisfy tRAS(min). If this interval does not satisfy tRAS(min) then tRCD must be
extended.
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128Mb Synchronous DRAM
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Burst Read with Auto-Precharge: BL=1
Burst Read with Auto-Precharge: BL=2
Burst Read with Auto-Precharge: BL=4
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Although a Read Command with auto-precharge cannot be interrupted by a command to the same bank, it can be
interrupted by a Read or Write Command to a different bank. If the command is issued before auto-precharge begins then
the precharge function will begin with the new command. The bank being auto-precharged may be reactivated after the
delay tRP.
Burst Read with Auto-Precharge Interrupted by Read
If interrupting a Read Command with auto-precharge with a Write Command, DQM must be used to avoid DQ contention.
Burst Read with Auto-Precharge Interrupted by Write
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If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The bank undergoing
auto-precharge cannot be reactivated until tDAL, Data-in to Active delay, is satisfied.
Burst Write with Auto-Precharge
Similar to the Read Command, a Write Command with auto-precharge cannot be interrupted by a command to the same
bank. It can be interrupted by a Read or Write Command to a different bank, however. The interrupting command will
terminate the write. The bank undergoing auto-precharge cannot be reactivated until tDAL is satisfied.
Burst Write with Auto-Precharge Interrupted by Write
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Burst Write with Auto-Precharge Interrupted by Read
Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is
triggered when CS, RAS, and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be
used to precharge each bank separately or all banks simultaneously. Three address bits, A10, BA0, and BA1, are used to
define which bank(s) is to be precharged when the command is issued.
Bank Selection for Precharge by Address Bits
A10 Bank select Precharge Bank(s)
Low BA0, BA1 Single bank Defined by BA0, BA1
HIGH Don’t Care All Banks.
For read cycles, the Precharge Command may be applied (CAS latency - 1) prior to the last data output. For write cycles, a
delay must be satisfied from the start of the last burst write cycle until the Precharge Command can be issued. This delay is
known as tDPL, Data-in to Precharge delay.
After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can
be executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the
Precharge time (tRP).
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Burst Read Followed by the Precharge Command
Burst Write Followed by the Precharge Command
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Precharge Termination
The Precharge Command may be used to terminate either a burst read or burst write operation. When the Precharge
command is issued, the burst operation is terminated and bank precharge begins. For burst read operations, valid data will
continue to appear on the data bus as a function of CAS Latency.
Burst Read Interrupted by Precharge
Burst write operations will be terminated by the Precharge command. The last write data that will be properly stored in the
device is that write data that is presented to the device a number of clock cycles prior to the Precharge command equal to
the Data-in to Precharge delay, tDPL.
Precharge Termination of a Burst Write
(Burst Length = 8, Latency =2 , 3)
CK
T0 T2T1 T3 T4 T5 T6 T7 T8
COMMAND
DQM
WRITE AX0
NOPNOP NOP NOP NOP Precharge A NOP NOP
Note:
Latency = 2
tCK2,DQs
DIN Ax0
Latency = 3
tCK2,DQs
DIN Ax0 DIN B0
DIN Ax1 DIN Ax2
DIN Ax1
tDPL
tDPL
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Automatic Refresh Command (CAS before RAS Refresh)
When CS, RAS, and CAS are held low with CKE and WE high at the rising edge of the clock, the chip enters the Automatic
Refresh mode (CBR). All banks of the SDRAM must be precharged and idle for a minimum of the Precharge time (tRP)
before the Auto Refresh Command (CBR) can be applied. An address counter, internal to the device provides the
address during the refresh cycle. No control of the external address pins is required once this cycle has started.
When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the
Auto Refresh Command (CBR) and the next Activate Command or subsequent Auto Refresh Command must be greater
than or equal to the RAS cycle time (tRC).
Self Refresh Command
The SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command is defined by
having CS, RAS, CAS, and CKE held low with WE high at the rising edge of the clock. All banks must be idle prior to issuing
the Self Refresh Command. Once the command is registered, CKE must be held low to keep the device in Self Refresh
mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The
clock is internally disabled during Self Refresh Operation to save power. The user may halt the external clock while the
device is in Self Refresh mode, however, the clock must be restarted before the device can exit Self Refresh operation.
Once the clock is cycling, the device will exit Self Refresh operation after CKE is returned high. A minimum delay time is
required when the device exits Self Refresh Operation and before the next command can be issued. This delay is equal to
the RAS cycle time (tRC) plus the Self Refresh exit time (tSREX).
Power Dow n Mode
In order to reduce standby power consumption, two power down modes are available: Precharge and Active Power Down
mode. To enter Precharge Power Down mode, all banks must be precharged and the necessary precharge delay (tRP) must
occur before the SDRAM can enter the power down mode. If a bank is activated but not performing a Read or Write
operation, Active Power Down mode will be entered. (Issuing a Power Down Mode Command when the device is
performing a Read or Write operation causes the device to enter Clock Suspend mode. See the following Clock Suspend
section.) Once the Power Down mode is initiated by holding CKE low, all of the receiver circuits except CKE are gated off.
The Power Down mode does not perform any refresh operations, therefore the device can’t remain in Power Down mode
longer than the Refresh period (tREF) of the device.
The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command (or Device
Deselect Command) is required on the next rising clock edge.
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Power Down Mode Exit Timing
Data Mask
The SDRAM has a Data Mask function that can be used in conjunction with data read and write cycles. When the Data
Mask is activated (DQM high) during a write cycle, the write operation is prohibited immediately (zero clock latency). If the
Data Mask is activated during a read cycle, the data outputs are disabled and become high impedance after a two-clock
delay, independent of CAS latency.
Data Mask Activated during a Read Cycle
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No Operation Command
The No Operation Command should be used in cases when the SDRAM is in an idle or a wait state. The purpose of the No
Operation Command is to prevent the SDRAM from registering any unwanted commands between operations. A No
Operation Command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the clock. A No
Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle.
Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is
brought high, the RAS, CAS, and WE signals become don’t cares.
Clock Suspend Mode
During normal access mode, CKE is held high, enabling the clock. When CKE is registered low while at least one of the
banks is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends or
“freezes” any clocked operation that was currently being executed. There is a one-clock delay between the registration of
CKE low and the time at which the SDRAM’s operation suspends. While in Clock Suspend mode, the SDRAM ignores any
new commands that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay
from when CKE returns high to when Clock Suspend mode is exited.
When the operation of the SDRAM is suspended during the execution of a Burst Read operation, the last valid data output
onto the DQ pins will be actively held valid until Clock Suspend mode is exited.
Clock Suspend during a Read Cycle
If Clock Suspend mode is initiated during a burst write operation, the input data is masked and is ignored until the Clock
Suspend mode is exited.
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Clock Suspend during a Write Cycle
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Command Truth Table (See note 1)
Function Device State
CKE
CS RAS CAS WE DQM
BA0,
BA1
A10
A11,
A9-A0
Notes
Previous
Cycle
Current
Cycle
Mode Register Set Idle H X L L L L X OP Code
Auto (CBR)
Refresh
Idle H H L L L H X X X X
Entry Self Refresh Idle H L L L L H X X X X
Exit Self Refresh
Idle Self-
Refresh
L H
H X X X
X X X X
L H H H
Single Bank
Precharge
See Current
State Table
H X L L H L X BS L X 2
Precharge all
Banks
See Current
State Table
H X L L H L X X H X
Bank Activate Idle H X L L H H X BS Row Address 2
Write Active H X L H L L X BS L Column 2
Write with
Auto-Precharge
Active H X L H L L X BS H Column 2
Read Active H X L H L H X BS L Column 2
Read with
Auto-precharge
Active H X L H L H X BS H Column 2
Reserved - H X L H H L X X X X
No Operation Any H X L H H H X X X X
Device Deselect Any H X H X X X X X X X
Clock Suspend
Mode Entry
Activate H L X X X X X X X X
1
Clock Suspend
Mode Exit
Activate L H X X X X X X X X
Data Write/
Output Enable
Activate H X X X X X L X X X
5
Data Mask/
Output Disable
Activate H X X X X X H X X X
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Function Device State
CKE
CS RAS CAS WE DQM
BA0,
BA1
A10
A11,
A9-A0
Notes
Previous
Cycle
Current
Cycle
Power Down Mode
Entry
Idle/Activate H L
H X X X
X X X X 6, 7
L H H H
Power Down Mode
Entry
Any (Power
Down)
L H
H X X X
X X X X 6, 7
L H H H
1. All of the SDRAM operations are defined by states of CS, WE, RAS, CAS, and DQM at the positive rising edge of the clock. Refer to the
Current State Truth Table.
2. Bank Select (BA0, BA1): BA0, BA1 = 0,0 selects bank 0; BA0, BA1 = 1,0 selects bank 1; BA0, BA1 = 0,1 selects bank 2; BA0, BA1 = 1,1
selects bank 3.
3. Not applicable.
4. During normal access mode, CKE is held high and CK is enabled. When it is low, it freezes the internal clock and extends data Read and
Write operations. One clock delay is required for mode entry and exit.
5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the
data outputs are disabled and become high impedance after a two-clock delay. DQM also provides a data mask function for Write cycles.
When it activates, the Write operation at the clock is prohibited (zero clock latency).
6. All banks must be precharged before entering the Power Down Mode. (If this command is issued during a burst operation, the device state
will be Clock Suspend Mode.) The Power Down Mode does not perform any refresh operations; therefore the device can’t remain in this
mode longer than the Refresh period (tREF) of the device. One clock delay is required for mode entry and exit.
7. A No Operation or Device Deselect Command is required on the next clock edge following CKE going high.
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Clock Enable (CKE) Truth Table
Current State
CKE Command
Action Notes
Previous
Cycle
Current
Cycle
CS RAS CAS WE BA0, BA1 A11-A0
Self Refresh
H X X X X X X X INVALID 1
L H H X X X X X
Exit Self Refresh with Device
Deselect
2
L H L H H H X X
Exit Self Refresh with no
operation
2
L H L H H L X X ILLEGAL 2
L H L H L X X X ILLEGAL 2
L H L L X X X X ILLEGAL 2
L L X X X X X X Maintain Self Refresh
Power Down CB
H X X X X X X X INVALID 1
L H H X X X X X
Power Down mode exit, all
banks idle
2
L H L X X X X X ILLEGAL 2
L L X X X X X X Maintain Power Down Mode
All Banks Idle
H H H X X X
Refer to the Idle State
section of the Current State
Truth Table
3
H H L H X X 3
H H L L H X 3
H H L L L H X X CBR Refresh
H H L L L L OP Code Mode Register Set 4
H L H X X X
Refer to the Idle State
section of the Current State
Truth Table.
3
H L L H X X 3
H L L L H X 3
H L L L L H X X Entry Self Refresh 4
H L L L L L Op Code Mode Register Set
L X X X X X X X Power Down 4
Any State other
than listed above
H H X X X X X X
Refer to operations in the
Current State Truth Table.
H L X X X X X X Begin Clock Suspend next cycle 5
L H X X X X X X Exit Clock Suspend next cycle
L L X X X X X X Maintain Clock Suspend
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1. For the given Current State CKE must be low in the previous cycle.
2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE (tCES)
must be satisfied. When exiting power down mode, a NOP command (or Device Deselect Command) is required on the first rising clock
after CKE goes high (see page 26).
3. The address inputs depend on the command that is issued. See the Idle State section of the Current State Truth Table for more information.
4. The Precharge Power Down Mode, the Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle state.
5. Must be a legal command as defined in the Current State Truth Table.
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Current State Truth Table (See note 1)
Current
State
Description
Command
Action Notes
CS RAS CAS WE BA0, BA1 A11-A0
Idle
Mode Register Set L L L L OP Code Set the Mode Register 2
Auto/Self Refresh L L L H X X Start Auto/Self Refresh 2,3
Precharge L L H L BS X No Operation
Bank Activate L L H H BS
Row
Address
Activate the specified bank and
row
Write w/o Precharge L H L L BS Column ILLEGAL 4
Read w/o Precharge L H L H BS Column ILLEGAL 4
No Operation L H H H X X No Operation
Device Deselect H X X X X X No Operation or Power Down 5
Row Active
Mode Register Set L L L L OP Code ILLEGAL
Auto/Self Refresh L L L H X X ILLEGAL
Precharge L L H L BS X Precharge 6
Bank Activate L L H H BS
Row
Address
ILLEGAL 4
Write L H L L BS Column
Start Write; Determine if
Auto-Precharge
7, 8
Read L H L H BS Column
Start Write; Determine if
Auto-Precharge
7, 8
No Operation L H H H X X No Operation
Device Deselect H X X X X X No Operation
Read
Mode Register Set L L L L OP Code ILLEGAL
Auto/Self Refresh L L L H X X ILLEGAL
Precharge L L H L BS X
Terminate Burst; Start the
Precharge
Bank Activate L L H H BS
Row
Address
ILLEGAL 4
Write L H L L BS Column
Terminate Burst; Start the Write
cycle
8,9
Read L H L H BS Column
Terminate Burst; Start the Read
cycle
8,9
Burst Stop L H H L X X Burst Stop
No Operation L H H H X X Continue the Burst
Device Deselect H X X X X X Continue the Burst
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Current
State
Description
Command
Action Notes
CS RAS CAS WE BA0, BA1 A11-A0
Write
Mode Register Set L L L L OP Code ILLEGAL
Auto/Self Refresh L L L H X X ILLEGAL
Precharge L L H L BS X
Terminate Burst; Start the
Precharge
Bank Activate L L H H BS
Row
Address
ILLEGAL 4
Write L H L L BS Column
Terminate Burst; Start a new
Write cycle
8,9
Read L H L H BS Column
Terminate Burst; Start the Read
cycle
8,9
Burst Stop L H H L X X Burst Stop
No Operation L H H H X X Continue the Burst
Device Deselect H X X X X X Continue the Burst
Read with
Auto Pre-
charge
Mode Register Set L L L L OP Code ILLEGAL
Auto/Self Refresh L L L H X X ILLEGAL
Precharge L L H L BS X ILLEGAL 4
Bank Activate L L H H BS
Row
Address
ILLEGAL 4
Write L H L L BS
Column ILLEGAL 4
Read L H L H BS Column ILLEGAL 4
No Operation L H H H X X Continue the Burst
Device Deselect L X X X X X Continue the Burst
Write with
Auto
Precharge
Mode Register Set L L L L OP Code ILLEGAL
Auto/Self Refresh L L L H X X ILLEGAL
Precharge L L H L BS X ILLEGAL 4
Bank Activate L L H H BS
Row
Address
ILLEGAL 4
Write L H L L BS
Column ILLEGAL 4
Read L H L H BS Column ILLEGAL 4
No Operation L H H H X X Continue the Burst
Device Deselect L X X X X X Continue the Burst
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Current
State
Description
Command
Action Notes
CS RAS CS WE BA0, BA1 A11-A0
Precharging
Mode Register Set L L L L OP Code ILLEGAL
Auto/Self Refresh L L L H X X ILLEGAL
Precharge L L H L BS X
No Operation; Bank(s) idle after
tRP
Bank Activate L L H H BS
Row
Address
ILLEGAL 4
Write L H L L BS Column ILLEGAL 4
Read L H L H BS Column ILLEGAL 4
No Operation L H H H X X
No Operation; Bank(s) idle after
tRP
Device Deselect H X X X X X
No Operation; Bank(s) idle after
tRP
Row
Activating
Mode Register Set L L L L OP Code ILLEGAL
Auto/Self Refresh L L L H X X ILLEGAL
Precharge L L H L BS X ILLEGAL 4
Bank Activate L L H H BS
Row
Address
ILLEGAL 4,10
Write L H L L BS Column ILLEGAL 4
Read L H L H BS Column ILLEGAL 4
No Operation L H H H X X
No Operation; Row Active after
tRCD
Device Deselect H X X X X X
No Operation; Row Active after
tRCD
Write
Recovering
Mode Register Set L L L L OP Code ILLEGAL
Auto/Self Refresh L L L H X X ILLEGAL
Precharge L L H L BS X ILLEGAL 4
Bank Activate L L H H BS
Row
Address
ILLEGAL 4
Write L H L L BS Column Start Write; Determine if Auto
Precharge
9
Read L H L H BS Column 9
No Operation L H H H X X No Operation; Row Active after
tDPL
Device Deselect H X X X X X
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Current
State
Description
Command
Action Notes
CS RAS CS WE BA0, BA1 A11-A0
Write
Recovering
with Auto
Precharge
Mode Register Set L L L L OP Code ILLEGAL
Auto/Self Refresh L L L H X X ILLEGAL
Precharge L L H L BS X ILLEGAL 4
Bank Activate L L H H BS
Row
Address
ILLEGAL 4
Write L H L L BS Column
Start Write; Determine if Auto
Precharge
9
Read L H L H BS Column
Start Write; Determine if Auto
Precharge
9
No Operation L H H H X X
No Operation; Row Active after
tDPL
Device Deselect H X X X X X
No Operation; Row Active after
tDPL
Refreshing
Mode Register Set L L L L OP Code ILLEGAL
Auto/Self Refresh L L L H X X ILLEGAL
Precharge L L H L BS X ILLEGAL
Bank Activate L L H H BS
Row
Address
ILLEGAL
Write L H L L BS Column ILLEGAL
Read L H L H BS Column ILLEGAL
No Operation L H H H X X No Operation; Idle after tRC
Device Deselect H X X X X X No Operation; Idle after tRC
Mode
Register
Accessing
Mode Register Set L L L L OP Code ILLEGAL
Auto/Self Refresh L L L H X X ILLEGAL
Precharge L L H L BS X ILLEGAL
Bank Activate L L H H BS
Row
Address
ILLEGAL
Write L H L L BS Column ILLEGAL
Read L H L H BS Column ILLEGAL
No Operation L H H H X X
No Operation; Idle after two
clock cycles
Device Deselect H X X X X X
No Operation; Idle after two
clock cycles
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1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is
being applied to.
2. All Banks must be idle; otherwise, it is an illegal action.
3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is
entered.
4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being refer-
enced by the Current State then the action may be legal depending on the state of that bank.
5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation.
6. The minimum and maximum Active time (tRAS) must be satisfied.
7. The RAS to CAS Delay (tRCD) must occur before the command is given.
8. Column address A10 is used to determine if the Auto Precharge function is activated.
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.
Absolute Maximum Ratings
Symbol Parameter Rating Unit Notes
VDD Power Supply Voltage -1.0 to +4.6 V 1
VDDQ Power Supply Voltage for Output -1.0 to +4.6 V 1
VIN Input Voltage -0.3 to VDD + 0.3 V 1
VOUT Output Voltage -0.3 to VDD + 0.3 V 1
TA Operating Temperature (ambient)
Commercial 0 to +70 ℃ 1
Industrial -40 to +85 ℃ 1
TSTG Storage Temperature -55 to +150 ℃ 1
PD Power Dissipation 1.0 W 1
IOUT Short Circuit Output Current 50 mA 1
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
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Recommended DC Operating Conditions
Symbol Parameter Rating Unite Notes
Minimum Typical Maximum
VDD Supply Voltage 3.0 3.3 3.6 V 1
VDDQ Supply Voltage for Out put 3.0 3.3 3.6 V 1
VIH Input High Voltage 2.0 3.0 VDD + 0.3 V 1, 2
VIL Input Low Voltage -0.3 0 0.8 V 1, 3
VOH Output Logic High Voltage 2.4 - - V
IoH = -2mA
VOL Output Logic Low Voltage - - 0.4 V
IoH = -2mA
1. All voltages referenced to VSS and VSSQ.
2. VIH (max) = VDD + 2.3V for pulse width ≤ 3ns.
3. VIL (min) = VSS - 2.0V for pulse width ≤ 3ns.
Capacitance (TA = 23°C, f = 1MHz, VDD = 3.3V, VREF=1.4+/-200mV)
Symbol Parameter Min. Max. Units
CIN Input Capacitance (A0-A11, BS0, BS1, CS, RAS, CAS, WE, CKE, DQM) 2.5 3.8 pF
CADD Address 2.5 3.8 pF
CCLK Input Clock (CLK) 2.5 3.5 pF
COUT Output Capacitance (DQ0 – DQ15) 4.0 6.0 pF
DC Electrical Characteristics (VDD = 3.3V ±0.3V)
Symbol Parameter Min. Typ. Max. Units Note
II(L) Input Leakage Current, any input
(0.0V ≤ VIN ≤ VDD), All Other Pins Not Under Test = 0V
-1 - +1
μA
1
VIH Output Level (LVTTL) 2.0 3.0
VDD+0.3 V 2
VIL Output Level (LVTTL) -0.3 0 0.8
V 3
VOH Output Level (LVTTL)
Output “H” Level Voltage (IOUT = -2.0mA)
2.4 - -
V
VOL Output Level (LVTTL)
Output “L” Level Voltage (IOUT = +2.0mA)
- - 0.4
V
Notes:
1. Any input 0V ≤ VIN ≤ VDDQ Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
2. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.
3. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
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DC Output Load Circuit
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Operating, Standby, and Refresh Currents
Parameter Symbol Test Condition Max. Units Notes
6K 6KI 75B 75BI
Operating Current IDD1 Burst length=1, One bank active
tRC ≥ tRC(min), IOL=0mA 130 130 90 90 mA 1,2,3
Precharge Standby Current
in Power Down Mode
IDD2P CKE ≤ VIL(max), tCK = 10ns 4 4 4 4
mA 1
IDD2PS CKE & CLK ≤ VIL(max), tCK=∞ 4 4 4 4
Precharge Standby Current
in Non PowerDown Mode
IDD2N CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
Input signals are changed one time during
2clks.All other pins ≥ VDD-0.2V or ≤ 0.2V 20 20 20 20
mA
1,5
IDD2NS CKE ≥ VIH(min), tCK = ∞
Input signals are stable. 10 10 10 10 1,7
Active standby current in
power-down mode
IDD3P CKE ≤ VIL(max), tCK = 15ns 10 10 10 10
mA 1.6
IDD3PS CKE ≤ VIL(max), tCK = ∞ 10 10 10 10
Active Standby Current
in Non Power Down Mode
IDD3N CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
Input signals are changed one time during
2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V
35 35 35 35
mA 1.5
IDD3NS CKE ≥ VIH(min), tCK = ∞ , Input signals are
stable. 30 30 30 30
Burst Mode Operating
Current
IDD4 tCK ≥ tCK(min), IOL=0mA
All banks active 150 150 110 110 mA 1,3,4
Auto Refresh Current IDD5 tRC ≥ tRC(min), All banks active 220 220 200 200 mA 1
Self Refresh Current IDD6 CKE ≤ 0.2V Normal
2 2 4 4 mA 1
Low Power
1. Currents given are valid for a single device. .
2. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of tCK and tRC. Input
signals are changed up to three times during tRC(min).
3. The specified values are obtained with the output open.
4. Input signals are changed once during tCK(min).
5. Input signals are changed once during three clock cycles.
6. Active Standby Current will be higher if Clock Suspend is entered during a burst read cycle (add 1mA per DQ).
7. Input signals are stable.
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AC Characteristics (VDD = 3.3V ± 0.3V)
1. An initial pause of 200µs, with DQM and CKE held high, is required after power-up. A Precharge All Banks command
must be given followed by a minimum of two Auto (CBR) Refresh cycles before or after the Mode Register Set
operation.
2. The Transition time is measured between VIH and VIL (or between VIL and VIH)
3. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or
between VIL and VIH) in a monotonic manner.
4. Load Circuit A: AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.40V crossover
point
5. Load Circuit A: AC measurements assume tT = 1.0ns
AC Characteristics Diagrams
Output
Input
Clock
tOH
tSETUP tHOLD
tAC
tLZ
1.4V
1.4V
1.4V
Vtt = 1.4V
Output 50
50pF
Zo= 50
AC Output Load Circuit (A)
tCKH
tCKL
VIL
VIH
tT
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Operating AC Parameters
Symbol Parameter -6K/-6KI -75B/-75BI
Units Notes
Min. Max. Min. Max.
tCK
Clock Cycle Time, CAS Latency = 3 6 1000 7.5 1000 ns
Clock Cycle Time, CAS Latency = 2 - - 10 1000 ns
tAC
Clock Access Time, CAS Latency = 3 - 5 - 5.4 ns
Clock Access Time, CAS Latency = 2 - 6 - 6 ns
tOH
Output data hold time, CAS Latency = 3 2.5 - 3 - ns
Output data hold time, CAS Latency = 2 3 3 ns
tCH Clock High Pulse Width 2.5 - 2.5 - ns
tCL Clock Low Pulse Width 2.5 - 2.5 - ns
tIS Input Setup Time1.5 - 1.5 - ns
tIH Input Hold Time1 - 0.8 - ns
tSLZ CLK to Output in Low-Z 1 - 1 - ns
tSHZ
CLK to Output in Hi-Z, CAS Latency = 3 0.3 8 0.5 10 ns
CLK to Output in Hi-Z, CAS Latency = 21.5 - 1.5 - ns
tRRD Bank to Bank Delay Time12 - 15 - ns 1
tRCD RAS to CAS Delay18 - 20 - ns 1
tRP Precharge Time18 - 20 - ns 1
tRAS Active Command Period42 100K 45 100K ns 1
tRC Bank Cycle Time 60 - 65 - ns 1
tRDL Last Data Into Row Precharge 2 - 2 - CLK
tDAL Last Data Into Active Delay2 CLK + tRP - 2 CLK + tRP - -
tCDL Last Data Into new Col. Address Delay 1 - 1 - CLK
tBDL Last Data Into Burst Stop1 - 1 - CLK
tCCD CAS to CAS Delay Time1 - 1 - CLK
tRSC Mode Register Set Cycle Time12 - 15 - ns
tOH Data Out Hold Time2.5 - 2.7 - ns 2, 4
tLZ Data Out to Low Impedance Time0 - 0 - ns
tHZ Data Out to High Impedance Time3 6 3 7 ns 3
tDQZ DQM Data Out Disable Latency2 - 2 - CK
tREF Mode Register Set Cycle Time- 64 - 64 ms 5
tSREX Self Refresh Exit Time 1 - 1 - CK
tDS Data In Set-up Time1.5 - 1.5 - ns
NT5SV8M16HS
128Mb Synchronous DRAM
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REV 1.7 CONSUMER DRAM
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tDH Data In Hold Time1 - 0.8 - ns
tDPL Data input to Precharge12 - 15 - ns
tWR Write Recovery Time12 - 15 - ns
tDAL3 Data In to Active Delay, CAS Latency = 3 5 - 5 - CK
tDAL2 Data In to Active Delay, CAS Latency = 2 4 - 4 - CK
tDQW DQM Write Mask Latency0 - 2 - CK
1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows:
the number of clock cycles = specified value of timing / clock period (count fractions as a whole number).
2. AC Output Load Circuit B.
3. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
4. Data Out Hold Time with no load must meet 1.8ns
5. 4096 auto refresh cycles.
NT5SV8M16HS
128Mb Synchronous DRAM
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AC Parameters for Write Timing
*BA0 = ”L”
B
a
nk
2
,
3
= Idl
e
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128Mb Synchronous DRAM
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AC Parameters for Read Timing (3/3/3)
CK
CKE
CS
DQ
RAS
CAS
WE
*BA1
DQM
T2 T3 T4
T0 T1 T6 T7 T8 T9T5 T11 T12 T13
T10
Hi -Z
A1 0
A0-A9,
tRCD
tRAS
Activate
Command
Bank 0
Ac ti va te
Command
Bank 1
Ac tiva te
Command
Ba n k 0
tCK3
Read with
Auto Precharge
Command
Bank 1
tRC
tAC3 tOH
Bx 0 Bx1
CBx R Ay
RBx
RBx
RAy
CAx
RAx
RAx
*BA0 = ＂
L＂
Read with
Auto Precharge
Command
Ba nk 0
Be g in Au t o
Precharge
Ba n k 0
Bank2,3 = Idle
tRP
Bx2
Be g in Au to
Pr ec harg e
Ba n k 1
tRRD
Ax 3Ax2Ax1Ax0
(Burstlength = 4, CASlatency =3; tRCD,t
RP =3)
A11
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128Mb Synchronous DRAM
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AC Parameters for Read Timing (3/3/3)
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128Mb Synchronous DRAM
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Mode Register Set
CK
CKE
CS
DQ
RAS
CAS
WE
BA 0,B A 1
DQM
T2 T3 T4T0 T1 T6 T7 T8 T9T5 T11 T12 T13 T14
T10 T16 T17 T18 T19T15 T22T20 T21
Hi-Z
A1 0 ,A 11
A0-A9
Pr ec ha r g e
Command
All Banks
Mode Register
Set Command
Any
Command
Address Key
tRP
tCK2
tRSC
(latency = 2)
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128Mb Synchronous DRAM
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Power-On Sequence and Auto Refresh (CBR)
stable for 200 s
CK
CKE
DQ
BS
DQM
T2 T3 T4
T0 T1 T6 T7 T8 T9T5 T11 T12 T13 T14
T10 T16 T17 T18 T19T15 T22T20 T21
Hi-Z
A10
A0- A9,
Precharge
Command
Al l B a nk s
tRP
Minimum of 8 Refresh Cycles are required
1s t Au t o R e f r e sh
Command
tRC
High level
is required
8th Auto Refresh
Command
Inputs must be
tCK
Any
Command
2Clockmin.
Mode Register
Address Key
Set Command
A11
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128Mb Synchronous DRAM
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Clock Suspension / DQ during Burst Read
CK
CKE
CS
DQ
RAS
CAS
WE
DQM
T2 T3 T4
T0 T1 T6 T7 T8 T9T5 T11 T12 T13 T14
T10 T16 T17 T18 T19T15 T22T20 T21
Hi-Z
A1 0
A0-A9, RAx
Ax 0 Ax1 Ax2 Ax3
Activate
Command
Bank 0 C l oc k S us pe n d
2 Cycl e s
Clock Suspend
1Cycle
Clock Suspend
3Cycles
RAx
Read
Command
Bank 0
CAx
*BA1
Ax4 Ax6 Ax7
*BA0=＂
L＂
Bank2,3=Idle
(Burst length = 8, CASlatency = 3;tRCD =3)
A11
tCES tCEH
tHZ
tCK3
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Clock Suspension / DQM during Burst Write
CK
CKE
CS
DQ
RAS
CAS
WE
*BA1
DQM
T2 T3 T4
T0 T1 T6 T7 T8 T9T5 T11 T12 T13 T14
T10 T16 T17 T18 T19T15 T22T20 T21
Hi- Z
A10
A0-A9, RAx
Activate
Command
Bank 0
RAx
CAx
DAx0
Clock Suspend
1Cycle
DAx1 DAx2
Clock Suspend
2Cycles Clock Suspend
3Cycles
Write
Command
Ba n k 0
tCK3
DAx5 DAx6 DAx7DAx3
*BA0=＂
L＂
Bank2,3=Idle
(Burstlength =8, latency = 3; tRCD =3)
NT5SV8M16HS
128Mb Synchronous DRAM
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REV 1.7 CONSUMER DRAM
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Power Dow n Mode and Clock Suspend
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128Mb Synchronous DRAM
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Auto Refresh (CBR)
CK
CKE
DQ
BS
DQM
T2 T3 T4
T0 T1 T6 T7 T8 T9T5 T11 T12 T13 T14
T10 T16 T17 T18 T19T15 T22T20 T21
Hi-Z
A10
A0 - A 9,
Precharge
Command
Auto Refresh
Co m ma n d
Au to R e fre sh
Command
tRC
tRP tRC
tCK2
All Banks
(latency = 2)
A11
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128Mb Synchronous DRAM
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Self Refresh (Entry and Exit)
CK
CKE
CS
DQ
RAS
CAS
WE
BS
DQM
T2 T3 T4
T0 T1
Hi-Z
A10
All Banks
must be idle
Self Refresh
Entry
A0 - A 9,
Tm Tm+2 Tm+3 Tm+4 Tm+5
Tm+ 1 Tm+7 Tm+8 Tm+9 Tm+10Tm+6 Tm+13Tm+11 Tm+12 Tm+15Tm+14
t
tSB
Any Command
tRC
tSREX
Se lf R e fre sh
Exit
Power Down
Entry
Power Down
Ex it
(Note: The CK signal must be reestablished prior to CKE returning high.)
A11
CES
tCES
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Random Row Read (Interleaving Banks) with Precharge
CK
CKE
DQ
*BA1
DQM
T2 T3 T4
T0 T1 T6 T7 T8 T9T5 T11 T12 T13 T14
T10 T16 T17 T18 T19T15 T22T20 T21
Hi-Z
A10
A0- A9, CBy
Read
Co m ma nd
Bank 1
By0
tCK 3
High
tAC3
Acti vate
Command
Bank 1
RBx
RBx
Ac ti va te
Command
Ba n k 0
RAx
RAx
CBx
Read
Command
Bank 1
Ac tiva te
Command
Bank 1
RBy
RBy
tRCD
Precharge
Command
Bank 1
CAx
Read
Command
Ba n k 0
Bx0 Bx1 Bx2 Bx3 Bx 4 Bx 5 Bx6 Ax0 Ax1 Ax4 Ax5 Ax6 Ax7
Precharge
Command
Bank 0
*BA 0 = ＂
L＂
Bank2,3=Idle
(Burst length = 8, CAS latency = 3; tRCD,t
RP =3)
A11
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128Mb Synchronous DRAM
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REV 1.7 CONSUMER DRAM
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Random Row Read (Interleaving Banks) with Auto-Precharge
CK
CKE
DQ
*BA1
DQM
T2 T3 T4
T0 T1 T6 T7 T8 T9T5 T11 T12 T13 T14
T10 T16 T17 T18 T19T15 T22T20 T21
Hi-Z
A1 0
A0 -A 9, CBy
By0
tCK3
High
tAC3
Activate
Command
Bank 1
RBx
RBx
Activate
Command
Ba nk 0
RA x
RA x
CBx
Activate
Command
Bank 1
RBy
RBy
tRCD
CAx
Bx0 Bx1 Bx 2 Bx 3 Bx4 Bx5 Bx6 Bx 7 Ax0 Ax4 Ax 5 Ax6
Read with
Auto Precharge
Command
Bank 1
Ax1
Start Auto Precharge
Bank 1
Read with
Au to Pr ec ha rg e
Command
Bank 0
St a rt Au to Pr ec ha rg e
Ba nk 0
Read with
Auto Precharge
Co m ma nd
Bank 1
*BA0=
＂
L＂
Bank2,3=Idle
RAx
RAx
Ax7
(Burstlength =8,CAS latency = 3; tRCD,t
RP =3)
A1 1
NT5SV8M16HS
128Mb Synchronous DRAM
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REV 1.7 CONSUMER DRAM
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Random Row Write (Interleaving Banks) with Auto-Precharge
CK
CKE
DQ
*BA1
DQM
T2 T3 T4T0 T1 T6 T7 T8 T9T5 T11 T12 T13 T14T10 T16 T17 T18 T19T15 T22T20 T21
Hi- Z
A1 0
A0-A9,
tCK3
High
DAx0 DAx1 DAx4 DAx7DAx6DAx5 DBx0 DBx3DBx2DBx1 DBx4 DBx5 DAy2
DAy1DAy0
CAXRAx
RAx RBx
RBx
Acti va te
Command
Ba nk 0
RAy
RAy
CBx CAy
tRCD
DBx7DBx6
Write with
Auto Precharge
Command
Bank 0
*BA 0 = ＂
L＂
Bank2,3=Idle
tDAL
Number of clocks depends on clock cycle time and speed sort.
See the Clock Fr equency and Latency table.
Bank may be reactivated at the completion of tDAL.
(Burst length = 8, latency = 3; tRCD,t
RP =3)
A11
tDAL
W rit e w it h
Auto Precharge
Command
Bank 1
Activate
Command
Bank 1
Wr ite with
Au t o P rec ha r g e
Command
Bank 0
Ac ti va te
Command
Bank 0
NT5SV8M16HS
128Mb Synchronous DRAM
54
REV 1.7 CONSUMER DRAM
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Dec 2011 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Random Row Write (Interleaving Banks) with Precharge
CK
CKE
DQ
*BA1
DQM
T2 T3 T4
T0 T1 T6 T7 T8 T9T5 T11 T12 T13 T14
T10 T16 T17 T18 T19T15 T22T20 T21
Hi- Z
A10
A0-A9,
tCK3
High
DAx0 DAx1 DAx4 DAx7DAx6DAx5 DBx0 DBx3DBx2DBx1 DBx4 DBx5 DAy2
DAy1DAy0
CAXRAx
RAx RBx
RBx RAy
RAy
CBx
Write
Command
Bank 0
CAy
Precharge
Command
tRP
tRC D
DBx7DBx6
(Burst length = 8, latency = 3; tRCD,t
RP =3)
tDPL
A11
Ac tiv at e
Command
Bank 1
Ac ti vate
Command
Ba n k 0
Write
Command
Bank 1
Pre c ha rg e
Command
Bank 0
Write
Command
Ba n k 0
Activate
Command
Bank 0
e
*BA0=＂
L＂
Bank2,3=Idl
NT5SV8M16HS
128Mb Synchronous DRAM
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REV 1.7 CONSUMER DRAM
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Read / Write Cycle
CK
CKE
DQ
*BA1
DQM
T2 T3 T4T0 T1 T6 T7 T8 T9T5 T11 T12 T13 T14
T10 T16 T17 T18 T19T15 T22T20 T21
Hi-Z
A10
A0- A9,
tCK3
CAy
DAy0 DAy1 DAy3Ax0 Ax1 Ax3Ax 2
Acti va te
Command
Bank0
RAx
RAx
CAx
Read
Command
Bank 0
DAy4
*BA0=＂
L＂
Bank2,3=Idle
(Burst length = 8, latency = 3; tRCD,t
RP =3)
A11
Wr ite
Command
Bank 0
The Write Data
is Masked with a
Zero Cloc k
Latency
The Read Data
is M asked wi th a
Two Clock
La t e nc y
Pre ch a rg e
Co m ma n d
Bank 0
NT5SV8M16HS
128Mb Synchronous DRAM
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Interleaved Column Read Cycle
CK
CKE
DQ
*BA1
DQM
T2 T3 T4
T0 T1 T6 T7 T8 T9T5 T11 T12 T13 T14
T10 T16 T17 T18 T19T15 T22T20 T21
Hi-Z
A1 0
A0-A9,
tCK3
tRCD tAC3
CBy
Read
Command
Bank 1
CBz
Read
Co m m an d
Bank 1
CAy
Precharge
Command
Bank 1
Ax0 Ax3Ax2Ax1 Bx0 By1By0Bx1 Bz0 Bz1 Ay0 Ay3Ay2Ay1
Activate
Command
Bank 0
RAx
RAx
CBx
Read
Command
Bank 1
CAx
Activate
Command
Bank 1
Read
Command
Bank 0
RBx
RBx
Read with
Auto Precharge
Command
Bank 0
Start Auto Precharge
Bank 0
*BA0=＂
L＂
Bank2,3=Idle
(Burst length = 4, latency = 3; tRCD,t
RP =3)
A11
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128Mb Synchronous DRAM
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Auto Precharge after Read Burst
CK
CKE
CS
DQ
RAS
CAS
WE
*BA1
DQM
T2 T3 T4
T0 T1 T6 T7 T8 T9T5 T11 T12 T13 T 14T10 T16 T17 T18 T19T15 T22T20 T21
Hi-Z
A10
A0-A9,
tCK3
High
Read with
Auto Pre c harg e
Command
Bank 1
CBy
Start Auto Precharge
Ba n k 1
Start Auto Precharge
Bank 0
Ax 3Ax2Ax0 Ax1 Bx3Bx2Bx0 Bx 1 Ay3Ay2Ay0 Ay1
Activate
Command
Bank 0
RAx
RAx
Read with
Auto P re c ha rg e
Co m m an d
Ba
n
k1
CBx
Read with
Auto Precharge
Command
B
a
nk 0
Ac tiv ate
Command
Bank 1
RBx
CAx RBx
Activate
Command
Bank 1
Read
Command
Ba n k 0
RBy
CAy RBy
By0 By1
Start
Bank 1
Auto Precharge
(Burst length = 4, CAS latency = 3; tRCD,t
RP =3)
A11
*BA0=＂
L＂
Bank2,3=Idle
NT5SV8M16HS
128Mb Synchronous DRAM
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Auto Precharge after Write Burst
CK
CKE
DQ
*BA1
DQM
T2 T3 T4
T0 T1 T6 T7 T8 T9T5 T11 T12 T13 T14T10 T16 T17 T18 T19T15 T22T20 T21
Hi-Z
A10
A0-A9,
tCK 2
High
Write with
Au to Pr ech a rge
Command
Ba n k 1
CBy
Activate
Co mm an d
Bank 1
RBx
RBx
Write wi th
Auto Precharge
Command
Bank 1
CBx
DAx3DAx2DAx1DAx0 DBx3DBx2DBx1DBx0 DAy3DAy2DAy1DAy0 DBy3DBy2DBy1DBy0 DAz3DAz2DAz1DAz0
Ac ti va te
Co mm an d
Ba n k 0
RAz
RAz
Write
Co mm an d
Bank 0
CAx
Write with
Au to Pre ch arg e
Command
Ba nk 0
CAy
Acti vat e
Command
Ba nk 1
RBy
RBy
Acti vate
Command
Ba n k 0
RAx
RAx
Write with
Au t o P rec ha rg e
Co mm an d
Bank 0
CAz
*BA0=＂
L＂
Bank2,3=Idle
A11
tDA L tDAL
N um b er o f cl oc ks d ep e nd s o n clo ck c ycl e a n d s pe e d s or t.
See the Clock Frequency and Latency table.
Bank may be reactivated at the completion of tDAL.
tDAL
(Burst length= 4,CAS latency = 2)
NT5SV8M16HS
128Mb Synchronous DRAM
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Burst Read and Single Write Operation
NT5SV8M16HS
128Mb Synchronous DRAM
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CS Function (Only CS signal needs to be asserted at minimum rate)
CK
CKE
DQ
BA0,BA1
DQM
T2 T3 T4T0 T1 T6 T7 T8 T9T5 T11 T12 T13 T14
T10 T16T17T18T19T15 T22T20 T21
Hi- Z
A10
A0 - A 9, A 11
tCK3
RAx
Low
RAx CAx CAy
Ax0 DAy0 DAy3DAy2DAy1Ax3Ax2Ax1
tRC D tDPL
(at 100MHz Burst Length = 4, Latency =3, tRCD,t
RP =3)
Precharge
Command
Bank A
Write
Command
Bank A
Read
Command
Ba n k A
Activate
Command
Bank A
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128Mb Synchronous DRAM
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Package Dimensions (400mil; 54 lead; Thin Small Outline Package)
Lead #1
0.80 Basic 0.35
10.16
±
0.13
22.22
±
0.13
11.76
±
0.20
-
0.05
+ 0.10
0.71REF
Detail A
0.10
Seating Plane
Detail A
0.5
±
0.1
0.05 Min
1.20 Max
0.25 Basic Gage Plan
e
NT5SV8M16HS
128Mb Synchronous DRAM
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REV 1.7 CONSUMER DRAM
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Revision Log
Rev Date Modification
0.1 02/2010 Preliminary Release.
1.0 03/2010 Official Release.
1.1 04/2010
1. Add Full Page mode on MRS setting on Page-8.
2. Complete IDD parameter on Page-37.
1.2 04/2010 II(L) data modified on Page-35.
1.3 06/2010 Delete AC Parameters for Read Timing (2/2/2) &(3/2/2)
1.4 07/2010 Modified IDD Specification
1.5 07/2010 Modified 6K/6KI IDD6 Specification
1.6 03/2011
1. Revised the Symbol of Data Out Hold Time
2. Revised the unit of tRDL/tCDL /tBDL/tCCD
1.7 12/2011 Re-organized AC Parameter Table
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128Mb Synchronous DRAM
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®
Nanya Technology Corporation.
All rights reserved.
Printed in Taiwan, R.O.C., 2011
The following are trademarks of NANYA TECHNOLOGY CORPORATION in R.O.C, or other countries, or both.
NANYA and NANYA logo
Other company, product and service names may be trademarks or service marks of others.
NANYA TECHNOLOGY CORPORATION (NTC) reserves the right to make changes without notice. NTC warrants
performance of its semiconductor products and related software to the specifications applicable at the time of sale in
accordance with NTC’s standard warranty. Testing and other quality control techniques are utilize to the extent NTC deems
necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except
those mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property
or environmental damage (“Critical Applications”).
NTC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTEND, AUTHORIZED, OR WARRANTED TO BE
SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL
APPLICATIONS.
Inclusion of NTC products in such applications is understood to be fully at the risk of the customer. Use of NTC products in
such applications requires the written approval of an appropriate NTC officer. Question concerning potential risk
applications should be directed to NTC through a local sales office.
In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards should
be provided by customer to minimize the inherent or procedural hazards.NTC assumes no liability of applications
assistance, customer product design, software performance, or infringement of patents or services described herein. Nor
does NTC warrant or represent that any license, either express or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right of NTC covering or relating to any combination, machine, or process in
which such semiconductor products or services might be or are used.
NANYA TECHNOLOGY CORPORATION
HWA YA Technology Park
669, FU HSING 3rd Rd., Kueishan,
Taoyuan, Taiwan, R.O.C.
The NANYA TECHNOLOGY CORPORATION
Home page can be found at http:\\www.nanya.com
