64-Position Up/Down
Control Digital Potentiometer
AD5227
Rev. 0
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Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
FEATURES
64-position digital potentiometer
10 kΩ, 50 kΩ, 100 kΩ end-to-end terminal resistance
Simple up/down digital or manual configurable control
Midscale preset
Low potentiometer mode tempco = 10 ppm/°C
Low rheostat mode tempco = 35 ppm/°C
Ultralow power, IDD = 0.4 µA typ and 3 µA max
Fast adjustment time, ts = 1 µs
Chip select enable multiple device operation
Low operating voltage, 2.7 V to 5.5 V
Automotive temperature range, −40°C to +105°C
Compact thin SOT-23-8 (2.9 mm × 3 mm) Pb-free package
APPLICATIONS
Mechanical potentiometer and trimmer replacements
LCD backlight, contrast, and brightness controls
Portable electronics level adjustment
Programmable power supply
Digital trimmer replacements
Automatic closed-loop control
FUNCTIONAL BLOCK DIAGRAM
04419-0-001
CS
U/D
CLK
GND
VDD
6-BIT UP/DOWN
CONTROL
LOGIC
POR
MIDSCALE WIPER
REGISTER
A
W
B
AD5227
Figure 1.
GENERAL DESCRIPTION
The AD5227 is Analog Devices’ latest 64-step up/down control
digital potentiometer1. This device performs the same electronic
adjustment function as a 5 V potentiometer or variable resistor.
Its simple 3-wire up/down interface allows manual switching or
high speed digital control. The AD5227 presets to midscale at
power-up. When CS is enabled, the devices changes step at
every clock pulse. The direction is determined by the state of
the U/D pin (see Table 1). The interface is simple to activate by
any host controller, discrete logic, or manually with a rotary
encoder or pushbuttons. The AD5227’s 64-step resolution, small
footprint, and simple interface enable it to replace mechanical
potentiometers and trimmers with typically 6× improved
resolution, solid-state reliability, and design layout flexibility,
resulting in a considerable cost savings in end users’ systems.
1 The terms digital potentiometer and RDAC are used interchangeably.
The AD5227 is available in a compact thin SOT-23-8 (TSOT-8)
Pb-free package. The part is guaranteed to operate over the
automotive temperature range of −40°C to +105°C.
Users who consider EEMEM potentiometers should refer to
some recommendations in the Applications section.
Table 1. Truth Table
CS CLK U/D Operation1
0 ↓ 0 RWB Decrement
0 ↓ 1 RWB Increment
1 X X No Operation
1 RWA increments if RWB decrements and vice versa.
AD5227
Rev. 0 | Page 2 of 16
TABLE OF CONTENTS
Electrical Characteristics ................................................................. 3
Interface Timing Diagrams......................................................... 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 10
Programming the Digital Potentiometers............................... 10
Digital Interface .......................................................................... 11
Terminal Voltage Operation Range.......................................... 11
Power-Up and Power-Down Sequences.................................. 11
Layout and Power Supply Biasing............................................ 11
Applications..................................................................................... 12
Manual Control with Toggle and Pushbutton Switches........ 12
Manual Control with Rotary Encoder..................................... 12
Adjustable LED Driver .............................................................. 12
Adjustable Current Source for LED Driver ............................ 12
Automatic LCD Panel Backlight Control................................ 13
6-Bit Controller .......................................................................... 13
Constant Bias with Supply to Retain Resistance Setting...... 14
Outline Dimensions....................................................................... 15
Ordering Guide .......................................................................... 15
REVISION HISTORY
Revision 0: Initial Version
AD5227
Rev. 0 | Page 3 of 16
ELECTRICAL CHARACTERISTICS
10 kΩ, 50 kΩ, 100 kΩ versions: VDD = 3 V ± 10% or 5 V ± 10%, VA = VDD, VB = 0 V, −40°C < TA < +105°C, unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ1 Max Unit
DC CHARACTERISTICS RHEOSTAT MODE
Resistor Differential Nonlinearity2 R-DNL RWB, A = no connect −0.5 ±0.15 +0.5 LSB
Resistor Integral Nonlinearity2 R-INL RWB, A = no connect −1 ±0.3 +1 LSB
Nominal Resistor Tolerance3 ∆RAB/RAB −20 +20 %
Resistance Temperature Coefficient (∆RAB/RAB)/∆T × 106 35 ppm/°C
Wiper Resistance RW V
DD = 2.7 V 100 200 Ω
V
DD = 5.5 V 50 Ω
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE
Resolution N 6 Bits
Integral Nonlinearity3 INL −1 ±0.1 +1 LSB
Differential Nonlinearity3, 4 DNL −0.5 ±0.1 +0.5 LSB
Voltage Divider Temperature Coefficient (∆VW/VW)/∆T × 106 Midscale 5 ppm/°C
Full-Scale Error VWFSE ≥+31 steps from midscale −1 −0.5 0 LSB
Zero-Scale Error VWZSE ≤−32 steps from midscale 0 0.5 +1 LSB
RESISTOR TERMINALS
Voltage Range5 V
A, B, W With respect to GND 0 VDD V
Capacitance A, B6 C
A, B f = 1 MHz, measured to
GND
140 pF
Capacitance W6 CW f = 1 MHz, measured to
GND
150 pF
Common-Mode Leakage ICM V
A = VB = VW 1 nA
DIGITAL INPUTS (CS, CLK, U/D)
Input Logic High VIH 2.4 5.5 V
Input Logic Low VIL 0 0.8 V
Input Current II V
IN = 0 V or 5 V ±1 µA
Input Capacitance6 C
I 5 pF
POWER SUPPLIES
Power Supply Range VDD 2.7 5.5 V
Supply Current IDD VIH = 5 V or VIL = 0 V,
VDD = 5 V
0.4 3 µA
Power Dissipation7 P
DISS VIH = 5 V or VIL = 0 V,
VDD = 5 V
17 µW
Power Supply Sensitivity PSSR VDD = 5 V ± 10% 0.01 0.05 %/%
DYNAMIC CHARACTERISTICS6, 8, 9
Bandwidth –3 dB BW_10 k RAB = 10 kΩ, midscale 460 kHz
BW_50 k RAB = 50 kΩ, midscale 100 kHz
BW_100 k RAB = 100 kΩ, midscale 50 kHz
Total Harmonic Distortion THD VA = 1 V rms, RAB = 10 kΩ,
VB = 0 V dc, f = 1 kHz
0.05 %
Adjustment Settling Time tS VA = 5 V ± 1 LSB error
band, VB = 0, measured at
VW
1 µs
Resistor Noise Voltage eN_WB R
WB = 5 kΩ, f = 1 kHz 14 nV/√Hz
Footnotes on the next page.
AD5227
Rev. 0 | Page 4 of 16
Parameter Symbol Conditions Min Typ1 Max Unit
INTERFACE TIMING CHARACTERISTICS (applies to all parts6, 10)
Clock Frequency fCLK 50 MHz
Input Clock Pulse Width tCH, tCL Clock level high or low 10 ns
CS to CLK Setup Time tCSS 10 ns
CS Rise to CLK Hold Time tCSH 10 ns
U/D to Clock Fall Setup Time tUDS 10 ns
1 Typicals represent average readings at 25°C, VDD = 5 V.
2 Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 NL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
4 DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminals A, B, W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
8 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
9 All dynamic characteristics use VDD = V.
10 All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. Switching characteristics are measured using
VDD = 5 V.
INTERFACE TIMING DIAGRAMS
04419-0-004
CS = LOW
U/D = HIGH
CLK
R
WB
Figure 2. Increment RWB
04419-0-005
CS = LOW
U/D = 0
CLK
RWB
Figure 3. Decrement RWB
04419-0-006
1
0
1
0
1
0
CS
CLK
U/D
RWB
t
S
t
UDS
t
CL
t
CH
t
CSS
t
CSH
Figure 4. Detailed Timing Diagram(Only RWB Decrement Shown)
AD5227
Rev. 0 | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
VDD to GND −0.3 V, +7 V
VA, VB, VW to GND 0 V, VDD
Digital Input Voltage to GND (CS, CLK, U/D) 0 V, VDD
Maximum Current
IWB, IWA Pulsed ±20 mA
IWB Continuous (RWB ≤ 5 kΩ, A open)1 ±1 mA
IWA Continuous (RWA ≤ 5 kΩ, B open)1 ±1 mA
IAB Continuous
(RAB = 10 kΩ/50 kΩ/100 kΩ)1
±500 µA/
±100 µA/±50 µA
Operating Temperature Range −40°C to +105°C
Maximum Junction Temperature (TJmax) 150°C
Storage Temperature −65°C to +150°C
Lead Temperature (Soldering, 10 s – 30 s) 245°C
Thermal Resistance2 θJA 230°C/W
1 Maximum terminal current is bounded by the maximum applied voltage
across any two of the A, B, and W terminals at a given resistance, the
maximum current handling of the switches, and the maximum power
dissipation of the package. VDD = 5 V.
2 Package power dissipation = (TJmax – TA) / θJA.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD5227
Rev. 0 | Page 6 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
04419-0-003
AD5227
TOP VIEW
(Not to Scale)
CLK
1
U/D
2
A
3
G
ND
4
V
DD
CS
B
W
8
7
6
5
Figure 5. SOT-23-8 Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 CLK Clock Input. Each clock pulse executes the step-up or step-down of the resistance. The direction is determined
by the state of the U/D pin. CLK is a negative-edge trigger. Logic high signal can be higher than VDD, but lower
than 5.5 V.
2 U/D Up/Down Selections. Logic 1 selects up and Logic 0 selects down. U can be higher than VDD, but lower than 5.5 V.
3 A Resistor Terminal A. GND ≤ VA ≤ VDD.
4 GND Common Ground.
5 W Wiper Terminal W. GND ≤ VW ≤ VDD.
6 B Resistor Terminal B. GND ≤ VB ≤ VDD.
7 CS Chip Select. Active Low. Logic high signal can be higher than VDD, but lower than 5.5 V.
8 VDD Positive Power Supply, 2.7 V to 5.5 V.
AD5227
Rev. 0 | Page 7 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
0.25
–0.25
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0.20
0645648403224168
04419-0-007
CODE (Decimal)
RHEOSTAT MODE INL (LSB)
V
DD
= 5.5V
–40°C
+25°C
+85°C
+105°C
Figure 6. R-INL vs. Code vs. Temperature, VDD = 5 V
0.25
–0.25
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0.20
0645648403224168
04419-0-008
CODE (Decimal)
RHEOSTAT MODE DNL (LSB)
V
DD
= 5.5V
–40°C
+25°C
+85°C
+105°C
Figure 7. R-DNL vs. Code vs. Temperature, VDD = 5 V
0.25
–0.25
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0.20
0645648403224168
04419-0-010
CODE (Decimal)
POTENTIOMETER MODE INL (LSB)
V
DD
= 5.5V
–40°C
+25°C
+85°C
+105°C
Figure 8. INL vs. Code, VDD = 5 V
0.25
–0.25
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0.20
0645648403224168
04419-0-012
CODE (Decimal)
POTENTIOMETER MODE DNL (LSB)
V
DD
= 5.5V
–40°C
+25°C
+85°C
+105°C
Figure 9. DNL vs. Code vs. Temperature, VDD = 5 V
0
–0.9
–0.8
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
–40 –20 0 20 40 60 10080
04419-0-013
TEMPERATURE (°C)
FSE (LSB)
V
DD
= 5.5V
V
DD
= 2.7V
Figure 10. Full-Scale Error vs. Temperature
1.0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
–40 –20 0 20 40 60 10080
04419-0-014
TEMPERATURE (°C)
ZSE (LSB)
V
DD
= 5.5V
V
DD
= 2.7V
Figure 11. Zero-Scale Error vs. Temperature
AD5227
Rev. 0 | Page 8 of 16
1
0.1
–40 –20 0 20 40 60 10080
04419-0-015
TEMPERATURE (°C)
SUPPLY CURRENT (
µ
A)
V
DD
= 5.5V
Figure 12. Supply Current vs. Temperature
1
0.1
–40 –20 0 20 40 60 10080
04419-0-016
TEMPERATURE (°C)
NOMINAL RESISTANCE, R
AB
(k
Ω
)
V
DD
= 5.5V
R
AB
= 50kΩ
R
AB
= 100kΩ
R
AB
= 10kΩ
Figure 13. Nominal Resistance vs. Temperature
120
0
20
40
60
80
100
–40 –20 0 20 40 60 10080
04419-0-017
TEMPERATURE (°C)
WIPER RESISTANCE, R
W
(Ω)
V
DD
= 5.5V
V
DD
= 2.7V
Figure 14. Wiper Resistance vs. Temperature
20
–20
–15
–10
–5
0
5
10
15
0 8 16 24 32 40 48 56 64
04419-0-018
CODE (Decimal)
RHEOSTAT MODE TEMPCO (ppm/°C)
10kΩ
50kΩ
100kΩ
V
DD
= 5.5V
Figure 15. Rheostat Mode Tempco ∆RWB/∆T vs. Code
20
–20
–15
–10
–5
0
5
10
15
0 8 16 24 32 40 48 56 64
04419-0-019
CODE (Decimal)
POTENTIOMETER MODE TEMPCO (ppm/°C)
10kΩ
50kΩ
100kΩ
V
DD
= 5.5V
Figure 16. Potentiometer Mode Tempco ∆RWB/∆T vs. Code
6
–54
–48
–42
–36
–30
–24
–18
–12
–6
0
1k 10k 1M
START 1 000.000Hz STOP 1 000 000.000Hz
REF LEVEL
0dB
/
DI
V
6.0dB MARKE
R
MAG (A/R) 461 441.868H
z
–8.957dB
100k
04419-0-042
dB
T
A
= 25°C
V
DD
= 5.5V
V
A
= 50mV rms
32 STEPS
16 STEPS
8 STEPS
4 STEPS
2 STEPS
1 STEP
Figure 17. Gain vs. Frequency vs. Code, RAB = 10 kΩ
AD5227
Rev. 0 | Page 9 of 16
6
–54
–48
–42
–36
–30
–24
–18
–12
–6
0
1k 10k 1M
START 1 000.000Hz STOP 1 000 000.000Hz
REF LEVEL
0dB
/
DI
V
6.0dB MARKE
R
MAG (A/R) 100 885.289H
z
–9.060dB
100k
04419-0-043
dB
T
A
= 25°C
V
DD
= 5.5V
V
A
= 50mV rms
32 STEPS
16 STEPS
8 STEPS
4 STEPS
2 STEPS
1 STEP
Figure 18. Gain vs. Frequency vs. Code, RAB = 50 kΩ
6
–54
–48
–42
–36
–30
–24
–18
–12
–6
0
1k 10k 1M
START 1 000.000Hz STOP 1 000 000.000Hz
REF LEVEL
0dB
/
DI
V
6.0dB MARKE
R
MAG (A/R) 52 246.435H
z
–9.139dB
100k
04419-0-044
dB
T
A
= 25°C
V
DD
= 5.5V
V
A
= 50mV rms
32 STEPS
16 STEPS
8 STEPS
4 STEPS
2 STEPS
1 STEP
Figure 19. Gain vs. Frequency vs. Code, RAB = 100 kΩ
0
–60
–40
–20
100 1k 10k 100k 1M
04419-0-023
FREQUENCY (Hz)
PSRR (dB)
V
DD
= 5V DC ±10% p-p AC
V
DD
= 3V DC ±10% p-p AC
STEP = MIDSCALE, V
A
= V
DD
, V
B
= 0V
Figure 20. PSRR
200
0
100
150
50
10k 100k 10M1M
04419-0-024
FREQUENCY (Hz)
I
DD
(
µ
A)
V
DD
= 5V
V
DD
= 3V
Figure 21. IDD vs. CLK Frequency
1.2
0
0.2
0.4
0.6
0.8
1.0
0 8 16 24 32 40 48 56 64
04419-0-025
CODE (Decimal)
THEORETICAL I
WB_MAX
(mA)
R
AB
= 10kΩ
R
AB
= 50kΩ
R
AB
= 100kΩ
A = OPEN
T
A
= 25°C
Figure 22. Maximum IWB vs. Code
04419-0-022
CH1 2.00V CH2 50.0mV M 400ns A CH2 60.0mV
V
W
1
2
VA
T 0.00000s
V
DD
= 5V
V
A
= 5V
V
B
= 0V
VB = 0V
STEP N+1
STEP N
Figure 23. Step Change Settling Time
AD5227
Rev. 0 | Page 10 of 16
THEORY OF OPERATION
The AD5227 is a 64-position 3-terminal digitally controlled
potentiometer device. It presets to a midscale at system power-
on. When CS is enabled, changing the resistance settings is
achieved by clocking the CLK pin. It is negative-edge triggered,
and the direction of stepping is determined by the state of the
U/D input. When the wiper reaches the maximum or the
minimum setting, additional CLK pulses do not change the
wiper setting.
04419-0-026
CS
U/D
CLK
GND
V
DD
6-BIT UP/DOWN
CONTROL
LOGIC
POR
MIDSCALE WIPER
REGISTER
A
W
B
AD5227
Figure 24. Functional Block Diagram
04419-0-027
B
W
A
D0
D2
D1
D4
D5
D3
R
S
R
S
=
R
AB
/64
R
W
R
S
R
S
R
S
RDAC
UP/DOWN
CTRL AND
DECODE
Figure 25. AD5227 Equivalent RDAC Circuit
PROGRAMMING THE DIGITAL POTENTIOMETERS
Rheostat Operation
If only the W-to-B or W-to-A terminals are used as variable
resistors, the unused terminal can be opened or shorted with W.
This operation is called rheostat mode and is shown in Figure 26.
04419-0-028
A
W
B
A
W
B
A
W
B
Figure 26. Rheostat Mode Configuration
The end-to-end resistance, RAB, has 64 contact points accessed
by the wiper terminal, plus the B terminal contact, assuming
that RWB is used (see Figure 25). Clocking the CLK input steps,
RWB by one step. The direction is determined by the state of U/D
pin. The change of RWB can be determined by the number of
clock pulses, provided that the AD5227 has not reached its
maximum or minimum scale. ∆RWB can, therefore, be
approximated as
⎟
⎠
⎞
⎜
⎝
⎛+×±=∆ W
AB
WB R
R
CPR 64 (1)
where:
CP is the number of clock pulses.
RAB is the end-to-end resistance.
RW is the wiper resistance contributed by the on-resistance of
the internal switch.
Since in the lowest end of the resistor string a finite wiper
resistance is present, care should be taken to limit the current
flow between W and B in this state to a maximum pulse current
of no more than 20 mA. Otherwise, degradation or possible
destruction of the internal switches can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the Wiper W and Terminal A also produces a
digitally controlled complementary resistance, RWA . When these
terminals are used, the B terminal can be opened or shorted to
W. S i m i l a r l y, ∆ R WA can be approximated as
()
⎟
⎠
⎞
⎜
⎝
⎛+−±=∆ W
AB
WA R
R
CPR 64
64 (2)
Equations 1 and 2 do not apply when CP = 0.
The typical distribution of the resistance tolerance from device
to device is process lot dependent. It is possible to have ±20%
tolerance.
Potentiometer Mode Operation
If all three terminals are used, the operation is called
potentiometer mode. The most common configuration is the
voltage divider operation as shown in Figure 27.
04419-0-029
A
W
B
V
I
V
C
Figure 27. Potentiometer Mode Configuration
AD5227
Rev. 0 | Page 11 of 16
The change of VWB is known provided that the AD5227 has not
reached the maximum or minimum scale. If one ignores the
effect of the wiper resistance, the transfer functions can be
simplified as
AWB V
CP
V64
+=∆ U/D = 1 (3)
AWB V
CP
V64
−=∆ U/D = 0 (4)
Unlike rheostat mode operation where the absolute tolerance is
high, potentiometer mode operation yields an almost ratiometric
function of CP/64 with a relatively small error contributed by
the RW term. The tolerance effect is, therefore, almost canceled.
Although the thin film step resistor, RS, and CMOS switches
resistance, RW, have very different temperature coefficients, the
ratiometric adjustment also reduces the overall temperature
coefficient to 5 ppm/°C except at low value codes where RW
dominates.
Potentiometer mode operation includes an op amp gain
configuration among others. The A, W, and B terminals can be
input or output terminals and have no polarity constraint
provided that |VAB|, |VWA |, and |VWB| do not exceed VDD-to-GND.
DIGITAL INTERFACE
The AD5227 contains a 3-wire serial input interface. The three
inputs are clock (CLK), chip select (CS), and up/down control
(U/D). These inputs can be controlled digitally for optimum
speed and flexibility
When CS is pulled low, a clock pulse increments or decrements
the up/down counter. The direction is determined by the state
of the U/D pin. When a specific state of the U/D remains, the
device continues to change in the same direction under con-
secutive clocks until it comes to the end of the resistance setting.
All digital inputs, CS, CLK, and U/D pins, are protected with a
series input resistor and a parallel Zener ESD structure as
shown in Figure 28.
04419-0-030
1kΩLOGIC
Figure 28. Equivalent ESD Protection Digital Pins
TERMINAL VOLTAGE OPERATION RANGE
The AD5227 is designed with internal ESD protection diodes
(Figure 29), but the diodes also set the boundary of the terminal
operating voltages. Voltage present on Terminal A, B, or W that
exceeds VDD by more than 0.5 V is clamped by the diode and,
therefore, elevates VDD. There is no polarity constraint between
VAB, VWA , and VWB, but they cannot be higher than VDD-to-GND.
POWER-UP AND POWER-DOWN SEQUENCES
Because of the ESD protection diodes, it is important to power
on VDD before applying any voltage to Terminals A, B, and W.
Otherwise, the diodes are forward-biased such that VDD can be
powered unintentionally and can affect the rest of the system
circuit. Similarly, VDD should be powered down last. The ideal
power-on sequence is in the following order: GND, VDD, VA/B/W,
and digital inputs.
04419-0-031
V
DD
GND
A
W
B
Figure 29. Maximum Terminal Voltages Set by VDD and GND
LAYOUT AND POWER SUPPLY BIASING
It is a good practice to use compact, minimum lead length
layout design. The leads to the input should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance. It is also good
practice to bypass the power supplies with quality capacitors.
Low ESR (equivalent series resistance) 1 µF to 10 µF tantalum
or electrolytic capacitors should be applied at the supplies to
minimize any transient disturbance and filter low frequency
ripple.
Figure 30 illustrates the basic supply bypassing configuration
for the AD5227. The ground pin of the AD5227 is a digital
ground reference that should be joined to the common ground
at a single point to minimize the digital ground bounce.
04419-0-032
V
DD
V
DD
+
GND
AD5227
C2
10µFC1
0.1µF
Figure 30. Power Supply Bypassing
AD5227
Rev. 0 | Page 12 of 16
APPLICATIONS
MANUAL CONTROL WITH TOGGLE AND
PUSHBUTTON SWITCHES
The AD5227’s simple interface allows it to be used with
mechanical switches for simple manual operation. The states of
the CS and U/D can be selected by toggle switches and the CLK
input can be controlled by a pushbutton switch. Because of the
numerous bounces due to contact closure, the pushbutton
switch should be debounced by flip-flops or by the ADM812 as
shown in Figure 31.
04419-0-033
UP/DOWN
MR RESET
V
CC
GND
ADM812
CLK
AD5227
CS
U/D
5V
INCREMENT
Figure 31. Manual Push Button Up/Down Control
MANUAL CONTROL WITH ROTARY ENCODER
Figure 32 shows another way of using AD5227 to emulate
mechanical potentiometer in a rotary knob operation. The
rotary encoder U1 has a C ground terminal and two out-of-
phase signals, A and B. When U1 is turned clockwise, a pulse
generated from the B terminal leads a pulse generated from the
A terminal and vice versa. Signals A and B of U1 pass through a
quadrature decoder U2 that translates the phase difference
between A and B of U1 into compatible inputs for U3 AD5227.
Therefore, when B leads A (clockwise), U2 provides the AD5227
with a logic high U/D signal, and vice versa. U2 also filters
noise, jitter, and other transients as well as debouncing the
contact bounces generated by U1.
04419-0-034
U3
AD5227
DIGITAL
POTENTIOMETER
CLK
1V
DD
8
U/D
2CS 7
A13 B1 6
GND
4W1 5B1
A1
W1
U2
LS7084
QUADRATURE
DECODER
RBIAS
1CLK 8
V
DD
2U/D 7
VSS
3X4/X1 6
A
4B5
B
C
A
U1
ROTARY
ENCODER
RE11CT-V1Y12-EF2CS
R3
10kΩ
R1
10kΩR2
10kΩ
5V
Figure 32. Manual Rotary Control
ADJUSTABLE LED DRIVER
The AD5227 can be used in many electronics-level adjustments
such as LED drivers for LCD panel backlight control. Figure 33
shows an adjustable LED driver. The AD5227 sets the voltage
across the white LED D1 for the brightness control. Since U2
handles up to 250 mA, a typical white LED with VF of 3.5 V
requires a resistor, R1, to limit the U2 current. This circuit is
simple but not power-efficient, therefore the U2 shutdown pin
can be toggled with a PWM signal to conserve power.
04419-0-035
AW
B
10kΩ
V
DD
GND
CS
CLK
U/D
U1
AD5227
C1
1µFC2
0.1µF
5V
U2
AD8591
+
–V+
V– SD
5V C3
0.1µF
R1
6ΩWHITE
LED
D1
PWM
Figure 33. Low Cost Adjustable LED Driver
ADJUSTABLE CURRENT SOURCE FOR LED DRIVER
Since LED brightness is a function of current rather than
forward voltage, an adjustable current source is preferred over a
voltage source as shown in Figure 34.
04419-0-036
A
W
B
10kΩ
R1
418kΩ
GND
U2
AD5227
V
DD
5V
CS
CLK
U/D
5V
U3
AD8591
+
–
V+
V–
5V
PWM
V
IN
V
OUT
GND
U1
ADP3333
ARM-1.5
SD
R
SET
0.1Ω
VL
ID
D1
Figure 34. Adjustable Current Source for LED Driver
The load current can be found as the VWB of the AD5227
divided by RSET.
SET
WB
DR
V
I= (5)
AD5227
Rev. 0 | Page 13 of 16
The U1 ADP3333ARM-1.5 is a 1.5 V LDO that is lifted above or
lowered below 0 V. When VWB of the AD5227 is at minimum,
there is no current through D1, so the GND pin of U1 would be
at –1.5 V if U3 were biased with the dual supplies. As a result,
some of the U2 low resistance steps have no effect on the output
until the U1 GND pin is lifted above 0 V. When VWB of the
AD5227 is at its maximum, VOUT becomes VL + VAB, so the U1
supply voltage must be biased with adequate headroom.
Similarly, a PWM signal can be applied at the U1 shutdown pin
for power efficiency. This circuit works well for a single LED.
ADJUSTABLE HIGH POWER LED DRIVER
Figure 35 shows a circuit that can drive three to four high power
LEDs. ADP1610 is an adjustable boost regulator that provides
the voltage headroom and current for the LEDs. The AD5227
and the op amp form an average gain of 12 feedback network
that servos the RSET voltage and ADP1610’s FB pin 1.2 V band
gap reference voltage. As the loop is set, the voltage across RSET is
regulated around 0.1 V and adjusted by the digital
potentiometer.
SET
R
LED R
V
ISET
= (6)
RSET should be small enough to conserve power but large
enough to limit maximum LED current. R3 should also be used
in parallel with AD5227 to limit the LED current within an
achievable range. A wider current adjustment range is possible
by lowering the R2 to R1 ratio, as well as changing R3 accordingly.
04419-0-037
SS RT GND
IN
U2
ADP1610
SW
FB
PWM
1.2V
SD
COMP
C
SS
10nF
C
C
390pF
R
C
100kΩ
L1
10µF
D1 C3
10µF
R4
13.5kΩ
D2
D3
D4
V
OUT
C2
10µF
5V
+
–
AD8541
U1
L1–SLF6025-100M1R0
D1–MBR0520LT1
U3
V+
V–
5V
C8
0.1µF
U1
AD5227
BA
10kΩ
R3
200Ω
WR1
100Ω
R2
1.1kΩ
R
SET
0.25Ω
Figure 35. Adjustable Current Source for LEDs in Series
AUTOMATIC LCD PANEL BACKLIGHT CONTROL
With the addition of a photocell sensor, an automatic brightness
control can be achieved. As shown in Figure 36, the resistance of
the photocell changes linearly but inversely with the light output.
The brighter the light output, the lower the photocell resistance
and vice versa. The AD5227 sets the voltage level that is gained
up by U2 to drive N1 to a desirable brightness. With the photocell
acting as the variable feedback resistor, the change in the light
output changes the R2 resistance, therefore causing U2 to drive
N1 accordingly to regulate the output. This simple low cost
implementation of the LED controller can compensate for the
temperature and aging effects typically found in high power
LEDs. Similarly, for power efficiency, a PWM signal can be
applied at the gate of N2 to switch the LED on and off without
any noticeable effect.
04419-0-038
CS
CLK
U/D
AW
B
10kΩ
V
DD
GND
U1
AD5227
C1
1µFC2
0.1µF
5V
U2
AD8591
+
–V+
V–
5V C3
0.1µF
R1
1kΩ
R2
5V
PWM
N1
2N7002
WHITE
LED
D1
5V
PHOTOCELL
SD
Figure 36. Automatic LCD Panel Backlight Control
6-BIT CONTROLLER
The AD5227 can form a simple 6-bit controller with a clock
generator, a comparator, and some output components. Figure 37
shows a generic 6-bit controller with a comparator that first
compares the sampling output with the reference level and
outputs either a high or low level to the AD5227 U/D pin. The
AD5227 then changes step at every clock cycle in the direction
indicated by the U/D state. Although this circuit is not as elegant
as the one shown in Figure 36, it is self-contained, very easy to
design, and can adapt to various applications.
04419-0-039
CLK
U/D B
5V
V
DD
GNDCS
U1
AD5227
+
–
U2
COMPARATOR
SAMPLING_OUTPUT
REF
U3
AD8531
+
–
OUTPUT
OP AMP
Figure 37. 6-Bit Controller
AD5227
Rev. 0 | Page 14 of 16
CONSTANT BIAS WITH SUPPLY TO
RETAIN RESISTANCE SETTING
Users who consider EEMEM potentiometers but cannot justify
the additional cost and programming for their designs can con-
sider constantly biasing the AD5227 with the supply to retain
the resistance setting as shown in Figure 38. The AD5227 is
designed specifically with low power to allow power conservation
even in battery-operated systems. As shown in Figure 39, a
similar low power digital potentiometer is biased with a 3.4 V
450 mA/hour Li-Ion cell phone battery. The measurement shows
that the device drains negligible power. Constantly biasing the
potentiometer is a practical approach because most portable
devices do not require detachable batteries for charging. Although
the resistance setting of the AD5227 is lost when the battery
needs to be replaced, this event occurs so infrequently that the
inconvenience is minimal for most applications.
04419-0-040
VDD
AD5227
U1
GND
VDD
U2
GND
COMPONENT X
VDD
U3
GND
COMPONENT Y
GND
V
DD
BATTERY OR
SYSTEM POWER
SW1
+
–
Figure 38. Constant Bias AD5227 for Resistance Retention
3.50
3.40
3.41
3.42
3.43
3.44
3.45
3.46
3.47
3.48
3.49
024681012
04419-0-041
DAYS
BATTERY VOLTAGE (V)
T
A
= 25°C
Figure 39. Battery Consumption Measurement
AD5227
Rev. 0 | Page 15 of 16
OUTLINE DIMENSIONS
1 3
56
2
8
4
7
2.90 BSC
PIN 1
1.60 BSC
1.95
BSC
0.65 BSC
0.38
0.22
0.10 MAX
0.90
0.87
0.84
SEATING
PLANE
1.00 MAX 0.20
0.08 0.60
0.45
0.30
8°
4°
0°
2.80 BSC
COMPLIANT TO JEDEC STANDARDS MO-193BA
Figure 40. 8-Lead Small Outline Transistor Package TSOT-8 [Thin SOT-23-8]
(UJ-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model RAB 1kΩ)
Temperature
Range
Package
Code Package Description
Full Container
Quantity Branding
AD5227BUJZ10-RL72 10 −40°C to +105°C UJ TSOT-8 3000 D3G
AD5227BUJZ10-R22 10 −40°C to +105°C UJ TSOT-8 250 D3G
AD5227BUJZ50-RL72 50 −40°C to +105°C UJ TSOT-8 3000 D3H
AD5227BUJZ50-R22 50 −40°C to +105°C UJ TSOT-8 250 D3H
AD5227BUJZ100-RL72 100 −40°C to +105°C UJ TSOT-8 3000 D3J
AD5227BUJZ100-R22 100 −40°C to +105°C UJ TSOT-8 250 D3J
AD5227EVAL 10 Evaluation Board 1
1 The end-to-end resistance RAB is available in 10 kΩ, 50 kΩ, and 100 kΩ versions. The final three characters of the part number determine the nominal resistance value,
for example, 10 kΩ = 10.
2 Z = Pb-free part.
AD5227
Rev. 0 | Page 16 of 16
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04419–0–3/04(0)
