1550 MHz to 2650 MHz Quadrature Modulator with
2100 MHz to 2600 MHz Frac-N PLL and Integrated VCO
Data Sheet
ADRF6703
Rev. B
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.
FEATURES
IQ modulator with integrated fractional-N PLL
RF output frequency range: 1550 MHz to 2650 MHz
Internal LO frequency range: 2100 MHz to 2600 MHz
Output P1dB: 14.2 dBm @ 2140 MHz
Output IP3: 33.2 dBm @ 2140 MHz
Noise floor: −159.6 dBm/Hz @ 2140 MHz
Baseband bandwidth: 750 MHz (3 dB)
SPI serial interface for PLL programming
Integrated LDOs and LO buffer
Power supply: 5 V/240 mA
40-lead 6 mm × 6 mm LFCSP
APPLICATIONS
Cellular communications systems
GSM/EDGE, CDMA2000, W-CDMA, TD-SCDMA, LTE
Broadband wireless access systems
Satellite modems
GENERAL DESCRIPTION
The ADRF6703 provides a quadrature modulator and
synthesizer solution within a small 6 mm × 6 mm footprint
while requiring minimal external components.
The ADRF6703 is designed for RF outputs from 1550 MHz to
2650 MHz. The low phase noise VCO and high performance
quadrature modulator make the ADRF6703 suitable for next
generation communication systems requiring high signal
dynamic range and linearity. The integration of the IQ
modulator, PLL, and VCO provides for significant board
savings and reduces the BOM and design complexity.
The integrated fractional-N PLL/synthesizer generates a 2× fLO
input to the IQ modulator. The phase detector together with an
external loop filter is used to control the VCO output. The VCO
output is applied to a quadrature divider. To reduce spurious
components, a sigma-delta (Σ-Δ) modulator controls the
programmable PLL divider.
The IQ modulator has wideband differential I and Q inputs,
which support baseband as well as complex IF architectures.
The single-ended modulator output is designed to drive a
50 Ω load impedance and can be disabled.
The ADRF6703 is fabricated using an advanced silicon-
germanium BiCMOS process. It is available in a 40-lead,
exposed-paddle, Pb-free, 6 mm × 6 mm LFCSP package.
Performance is specified from −40°C to +85°C. A lead-free
evaluation board is available.
Table 1.
Part No. Internal LO Range ±3 dB RFOUT Balun Range
ADRF6701 750 MHz 400 MHz
1150 MHz 1250 MHz
ADRF6702 1550 MHz 1200 MHz
2150 MHz 2400 MHz
ADRF6703 2100 MHz 1550 MHz
2600 MHz 2650 MHz
ADRF6704
2500 MHz
2050 MHz
290 MHz 3000 MHz
FUNCTIONAL BLOCK DIAGRAM
MUX
RSET CP VTUNE
LOSEL
LON
LOP
QN
2:1
MUX
VCO
CORE
QP
TEMP
SENSOR
DECL3
DECL2
DECL1
ENOP
BUFFER
BUFFER
RFOUTNC
NOTES
1. NC = NO CO NNE C T. DO NO T CO NNE CT TO THIS PIN.
VCC1VCC2VCC3VCC4VCC5VCC6
–
+
CHARGE P UMP
250µA,
500µA (DEFAULT),
750µA,
1000µA
PRESCALER
÷2
LE
CLK SPI
INTERFACE
DATA
MUXOUT
÷2
0/90
REFIN
GND
ADRF6703
29
VCC7
34
2616
39
3
3
4
8
6
14
13
12
38
37
36
7 11 15 20 21 23 2425 28 30 31 35
2
9
40
IP
IN
27 17 10 1
22
PHASE
FREQUENCY
DETECTOR
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
FRACTION
REG MODULUS INTEGER
REG
N COUNT E R
21 TO 123
×2
÷2
÷4
18
19
32
33
08570-001
5
DIVIDER
÷2
Figure 1.
ADRF6703 Data Sheet
Rev. B | Page 2 of 36
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings ............................................................ 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 16
PLL + VCO .................................................................................. 16
Basic Connections for Operation ............................................. 16
External LO ................................................................................. 16
Loop Filter ................................................................................... 17
DAC-to-IQ Modulator Interfacing .......................................... 18
Adding a Swing-Limiting Resistor ........................................... 18
IQ Filtering .................................................................................. 19
Baseband Bandwidth ................................................................. 19
Device Programming and Register Sequencing ..................... 19
Register Summary .......................................................................... 20
Register Description ....................................................................... 21
Register 0—Integer Divide Control (Default: 0x0001C0) .... 21
Register 1—Modulus Divide Control (Default: 0x003001) .. 22
Register 2—Fractional Divide Control (Default: 0x001802) 22
Register 3—Σ-Δ Modulator Dither Control (Default:
0x10000B) .................................................................................... 23
Register 4—PLL Charge Pump, PFD, and Reference Path
Control (Default: 0x0AA7E4) ................................................... 24
Register 5—LO Path and Modulator Control (Default:
0x0000D5) ................................................................................... 26
Register 6—VCO Control and VCO Enable (Default:
0x1E2106) .................................................................................... 27
Register 7—External VCO Enable ........................................... 27
Characterization Setups ................................................................. 28
Evaluation Board ............................................................................ 30
Evaluation Board Control Software ......................................... 30
Outline Dimensions ....................................................................... 35
Ordering Guide .......................................................................... 35
REVISION HISTORY
10/11—Rev. A to Re v. B
Changes to Table 1 ............................................................................ 1
6/11—Rev. 0 to Rev. A
Changes to Figure 1 .......................................................................... 1
Changes to Figure 5 ........................................................................ 10
Changes to Figure 17 and Figure 18 ............................................. 12
6/11—Revision 0: Initial Version
Data Sheet ADRF6703
Rev. B | Page 3 of 36
SPECIFICATIONS
VS = 5 V; TA = 25°C; baseband I/Q amplitude = 1 V p-p differential sine waves in quadrature with a 500 mV dc bias; baseband I/Q
frequency (fBB) = 1 MHz; fPFD = 38.4 MHz; fREF = 153.6 MHz at +4 dBm Re:50 Ω (1 V p-p); 130 kHz loop filter, unless otherwise noted.
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
OPERATING FREQUENCY RANGE IQ modulator (±3 dB RF output range) 1550 2650 MHz
PLL LO range 2100 2600 MHz
RF OUTPUT = 2140 MHz RFOUT pin
Nominal Output Power Baseband VIQ = 1 V p-p differential 4.95 dBm
IQ Modulator Voltage Gain RF output divided by baseband input voltage 0.95 dB
OP1dB 14.2 dBm
−44.1
dBm
Sideband Suppression −52.3 dBc
Quadrature Error +0.0/−0.6 Degrees
I/Q Amplitude Balance 0.04 dB
Second Harmonic POUT − P (fLO ± (2 × fBB)) −63.0 dBc
Third Harmonic POUT − P (fLO ± (3 × fBB)) −52.0 dBc
Output IP2 f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT ≈ −2 dBm per tone 70.1 dBm
Output IP3 f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT ≈ −2 dBm per tone 33.2 dBm
Noise Floor I/Q inputs = 0 V differential with 500 mV dc bias, 20 MHz carrier offset −159.6 dBm/Hz
RF OUTPUT = 2300 MHz RFOUT pin
Nominal Output Power Baseband VIQ = 1 V p-p differential 4.48 dBm
IQ Modulator Voltage Gain RF output divided by baseband input voltage 0.48 dB
OP1dB 13.5 dBm
Carrier Feedthrough −46.0 dBm
Sideband Suppression −44.0 dBc
Quadrature Error −0.25/−0.98 Degrees
I/Q Amplitude Balance 0.06 dB
Second Harmonic POUT − P (fLO ± (2 × fBB)) −67.0 dBc
Third Harmonic POUT − P (fLO ± (3 × fBB)) −53.0 dBc
Output IP2 f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT ≈ −2 dBm per tone 68.6 dBm
Output IP3 f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT ≈ −2 dBm per tone 32.7 dBm
Noise Floor I/Q inputs = 0 V differential with 500 mV dc bias, 20 MHz carrier offset −159.7 dBm/Hz
RF OUTPUT = 2600 MHz RFOUT pin
Nominal Output Power Baseband VIQ = 1 V p-p differential 2.75 dBm
IQ Modulator Voltage Gain RF output divided by baseband input voltage −1.25 dB
OP1dB 11.8 dBm
Carrier Feedthrough −46.8 dBm
Sideband Suppression −35.3 dBc
Quadrature Error 0.56/2.3 Degrees
I/Q Amplitude Balance 0.06 dB
Second Harmonic POUT − P (fLO ± (2 × fBB)) −63.0 dBc
P
OUT
− P (f
LO
± (3 × f
BB
))
−51.0
dBc
Output IP2 f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT ≈ −2 dBm per tone 62.0 dBm
Output IP3 f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT ≈ −2 dBm per tone) 29.2 dBm
Noise Floor I/Q inputs = 0 V differential with 500 mV dc bias, 20 MHz carrier offset −161.7 dBm/Hz
SYNTHESIZER SPECIFICATIONS Synthesizer specifications referenced to the modulator output
Internal LO Range 2100 2600 MHz
Figure of Merit (FOM)1 −222.0 dBc/Hz/Hz
ADRF6703 Data Sheet
Rev. B | Page 4 of 36
Parameter Test Conditions/Comments Min Typ Max Unit
REFERENCE CHARACTERISTICS REFIN, MUXOUT pins
REFIN Input Frequency 12 160 MHz
REFIN Input Capacitance 4 pF
Phase Detector Frequency 20 40 MHz
MUXOUT Output Level Low (lock detect output selected) 0.25 V
High (lock detect output selected) 2.7 V
50
%
Charge Pump Current Programmable to 250 µA, 500 µA, 750 µA, 1000 µA 500 µA
Output Compliance Range 1 2.8 V
PHASE NOISE (FREQUENCY =
2140 MHz, fPFD = 38.4 MHz)
Closed loop operation (see Figure 35 for loop filter design)
10 kHz offset −105.3 dBc/Hz
100 kHz offset −103.1 dBc/Hz
1 MHz offset −127.9 dBc/Hz
10 MHz offset −149.7 dBc/Hz
Integrated Phase Noise 1 kHz to 10 MHz integration bandwidth 0.29 °rms
Reference Spurs fPFD/2 −110 dBc
fPFD −102.0 dBc
fPFD × 2 −87.2 dBc
fPFD × 3 −90.4 dBc
fPFD × 4 −98.4 dBc
PHASE NOISE (FREQUENCY =
2300 MHz, fPFD = 38.4 MHz)
Closed loop operation (see Figure 35 for loop filter design)
10 kHz offset −103.5 dBc/Hz
100 kHz offset −102.2 dBc/Hz
1 MHz offset −128.4 dBc/Hz
10 MHz offset −149.5 dBc/Hz
Integrated Phase Noise 1 kHz to 10 MHz integration bandwidth 0.295 °rms
Reference Spurs fPFD/2 −110.7 dBc
fPFD −102.3 dBc
fPFD × 2 −85.5 dBc
fPFD × 3 −92.4 dBc
fPFD × 4 −101.1 dBc
PHASE NOISE (FREQUENCY =
2600 MHz, fPFD = 38.4 MHz)
Closed loop operation (see Figure 35 for loop filter design)
10 kHz offset −98.8 dBc/Hz
100 kHz offset −100.2 dBc/Hz
1 MHz offset −129.2 dBc/Hz
10 MHz offset −151.0 dBc/Hz
Integrated Phase Noise 1 kHz to 10 MHz integration bandwidth 0.37 °rms
Reference Spurs fPFD/2 −110.6 dBc
f
PFD
−106.5
dBc
fPFD × 2 −88.6 dBc
fPFD × 3 −92.4 dBc
fPFD × 4 −102.5 dBc
Measured at RFOUT, frequency = 2140 MHz
Second harmonic −41 dBc
Third harmonic −65 dBc
LO INPUT/OUTPUT LOP, LON
Output Frequency Range Divide by 2 circuit in LO path enabled 2100 2600 MHz
Divide by 2 circuit in LO path disabled 4200 5200 MHz
LO Output Level at 2140 MHz 2× LO or 1× LO mode, into a 50 Ω load, LO buffer enabled 0.1 dBm
LO Input Level Externally applied 2× LO, PLL disabled 0 dBm
LO Input Impedance Externally applied 2× LO, PLL disabled 50 Ω
Data Sheet ADRF6703
Rev. B | Page 5 of 36
Parameter Test Conditions/Comments Min Typ Max Unit
BASEBAND INPUTS IP, IN, QP, QN pins
400
500
600
mV
Bandwidth POUT ≈ −7 dBm, RF flatness of IQ modulator output calibrated out
0.5 dB 350 MHz
3 dB 750 MHz
Differential Input Impedance Frequency = 1 MHz2 945 Ω
Differential Input Capacitance Frequency = 1 MHz2 1 pF
LOGIC INPUTS CLK, DATA, LE, ENOP, LOSEL
Input High Voltage, VINH 1.4 3.3 V
Input Low Voltage, VINL 0 0.7 V
Input Current, IINH/IINL 0.1 µA
Input Capacitance, CIN 5 pF
TEMPERATURE SENSOR VPTAT voltage measured at MUXOUT
Output Voltage TA = 25°C, RL ≥10 kΩ (LO buffer disabled) 1.624 V
Temperature Coefficient TA = −40°C to +85°C, RL ≥10 kΩ 3.65 mV/°C
POWER SUPPLIES VCC1, VCC2, VCC3, VCC4, VCC5, VCC6, VCC7
Voltage Range 4.75 5 5.25 V
Supply Current Normal Tx mode (PLL and IQMOD enabled, LO buffer disabled) 240 mA
Tx mode using external LO input (internal VCO/PLL disabled) 134 mA
Tx mode with LO buffer enabled 290 mA
Power-down mode 22 µA
1 The figure of merit (FOM) is computed as phase noise (dBc/Hz) – 10log10(fPFD) – 20log10(fLO/fPFD). The FOM was measured across the full LO range, with fREF = 80 MHz,
fREF power = 10 dBm (500 V/μs slew rate) with a 40 MHz fPFD. The FOM was computed at 50 kHz offset.
2 Refer to Figure 40 for plot of input impedance over frequency.
ADRF6703 Data Sheet
Rev. B | Page 6 of 36
TIMING CHARACTERISTICS
Table 3.
Parameter Limit Unit Test Conditions/Comments
t
1
20
ns min
LE to CLK setup time
t2 10 ns min DATA to CLK setup time
t3 10 ns min DATA to CLK hold time
t4 25 ns min CLK high duration
t5 25 ns min CLK low duration
t6 10 ns min CLK to LE setup time
t7 20 ns min LE pulse width
CLK
DATA
LE
DB23 (MSB) DB22 DB2 DB1
(CONTROL BIT C2)(CONTROL BIT C3) DB0 (LSB)
(CONTROL BIT C1)
t
2
t
3
t
7
t
6
t
1
t
4
t
5
08570-002
Figure 2. Timing Diagram
Data Sheet ADRF6703
Rev. B | Page 7 of 36
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Supply Voltage (VCC1 to VCC7) 5.5 V
Digital I/O, CLK, DATA, LE −0.3 V to +3.6 V
LOP, LON 18 dBm
IP, IN, QP, QN −0.5 V to +1.5 V
REFIN −0.3 V to +3.6 V
θJA (Exposed Paddle Soldered Down)1 35°C/W
Maximum Junction Temperature 150°C
Operating Temperature Range
−40°C to +85°C
Storage Temperature Range −65°C to +150°C
1 Per JDEC standard JESD 51-2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ADRF6703 Data Sheet
Rev. B | Page 8 of 36
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
NOTES
1. NC =
NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSE
D PADDLE SHOULD BE SOLDERED TO A
LOW IMPEDANCE GROUND PLANE.
1VCC1 2DECL1 3CP 4
GND 5
RSET 6
REFIN 7
GND 8
MUXOUT 9
DECL2 10
VCC2
23 GND
24 NC
25 GND
26 RFOUT
27 VCC5
28 GND
29 VCC6
30 GND
22 VCC4
21 GND
11GND 12DATA 13CLK
15GND
17
VCC3 16
ENOP
18QP 19QN 20GND
14LE
33 IP
34 VCC7
35 GND
36 LOSEL
37 LON
38 LOP
39 VTUNE
40 DECL3
32 IN
31 GND
TOP VIEW
(Not to Scale)
ADRF6703
08570-003
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1, 10, 17, 22, 27, 29, 34 VCC1, VCC2, VCC3,
VCC4, VCC5, VCC6,
VCC7
Power Supply Pins. The power supply voltage range is 4.75 V to 5.25 V. Drive all of
these pins from the same power supply voltage. Decouple each pin with 100 pF and
0.1 µF capacitors located close to the pin.
2
DECL1
Decoupling Node for Internal 3.3 V LDO. Decouple this pin with 100 pF and 0.1 µF
capacitors located close to the pin.
3 CP Charge Pump Output Pin. Connect VTUNE to this pin through the loop filter. If
an external VCO is being used, connect the output of the loop filter to the VCO’s
voltage control pin. The PLL control loop should then be closed by routing the VCO’s
frequency output back into the ADRF6703 through the LON and LOP pins.
4, 7, 11, 15, 20, 21, 23,
25, 28, 30, 31, 35
GND Ground. Connect these pins to a low impedance ground plane.
24 NC Do not connect to this pin.
5 RSET Charge Pump Current. The nominal charge pump current can be set to 250 µA, 500 µA,
750 µA, or 1000 µA using DB10 and DB11 of Register 4 and by setting DB18 to 0 (CP
reference source).
In this mode, no external RSET is required. If DB18 is set to 1, the four nominal charge
pump currents (INOMINAL) can be externally tweaked according to the following
equation:
Ω−
×
=8.37
4.217
NOMINAL
CP
SET I
I
R
where ICP is the base charge pump current in microamps. For further details on the
charge pump current, see the Register 4—PLL Charge Pump, PFD, and Reference Path
Control section.
6 REFIN Reference Input. The nominal input level is 1 V p-p. Input range is 12 MHz to 160 MHz.
This pin has high input impedance and should be ac-coupled. If REFIN is being driven
by laboratory test equipment, the pin should be externally terminated with a 50 Ω
resistor (place the ac-coupling capacitor between the pin and the resistor). When
driven from an 50 Ω RF signal generator, the recommended input level is 4 dBm.
8 MUXOUT Multiplexer Output. This output allows a digital lock detect signal, a voltage
proportional to absolute temperature ( VPTAT ), or a buffered, frequency-scaled
reference signal to be accessed externally. The output is selected by programming
DB21 to DB23 in Register 4.
9 DECL2 Decoupling Node for 2.5 V LDO. Connect 100 pF, 0.1 µF, and 10 µF capacitors between this
pin and ground.
12 DATA Serial Data Input. The serial data input is loaded MSB first with the three LSBs being
the control bits.
Data Sheet ADRF6703
Rev. B | Page 9 of 36
Pin No. Mnemonic Description
13 CLK Serial Clock Input. This serial clock input is used to clock in the serial data to the
registers. The data is latched into the 24-bit shift register on the CLK rising edge.
Maximum clock frequency is 20 MHz.
14 LE Latch Enable. When the LE input pin goes high, the data stored in the shift registers is
loaded into one of the six registers, the relevant latch being selected by the first three
control bits of the 24-bit word.
16 ENOP Modulator Output Enable/Disable. See Table 6.
18, 19, 32, 33 QP, QN, IN, IP
Modulator Baseband Inputs. Differential in-phase and quadrature baseband inputs.
These inputs should be dc-biased to 0.5 V.
26 RFOUT RF Output. Single-ended, 50 Ω internally biased RF output. RFOUT must be ac-coupled
to its load.
36 LOSEL LO Select. This digital input pin determines whether the LOP and LON pins operate as
inputs or outputs. This pin should not be left floating. LOP and LON become inputs if
the LOSEL pin is set low and the LDRV bit of Register 5 is set low. External LO drive
must be a 2× LO. In addition to setting LOSEL and LDRV low and providing an external
2× LO, the LXL bit of Register 5 (DB4) must be set to 1 to direct the external LO to the
IQ modulator. LON and LOP become outputs when LOSEL is high or if the LDRV bit of
Register 5 (DB3) is set to 1. A 1× LO or 2× LO output can be selected by setting the
LDIV bit of Register 5 (DB5) to 1 or 0 respectively (see Table 7).
37, 38 LON, LOP Local Oscillator Input/Output. The internally generated 1× LO or 2× LO is available on
these pins. When internal LO generation is disabled, an external 1× LO or 2× LO can be
applied to these pins.
39 VTUNE VCO Control Voltage Input. This pin is driven by the output of the loop filter. Nominal
input voltage range on this pin is 1.3 V to 2.5 V. If the external VCO mode is activated,
this pin can be left open.
40 DECL3 Decoupling Node for VCO LDO. Connect a 100 pF capacitor and a 10 µF capacitor
between this pin and ground.
EP
Exposed Paddle. The exposed paddle should be soldered to a low impedance
ground plane.
Table 6. Enabling RFOUT
ENOP Register 5 Bit DB6 RFOUT
X1 0 Disabled
0 X1 Disabled
1 1 Enabled
1 X = don’t care.
Table 7. LO Port Configuration1, 2
LON/LOP Function
LOSEL
Register 5 Bit DB5(LDIV)
Register 5 Bit DB4(LXL)
Register 5 Bit DB3 (LDRV)
Input (2× LO) 0 X 1 0
Output (Disabled) 0 X 0 0
Output (1× LO) 0 0 0 1
Output (1× LO) 1 0 0 0
Output (1× LO) 1 0 0 1
Output (2× LO) 0 1 0 1
Output (2× LO) 1 1 0 0
Output (2× LO) 1 1 0 1
1 X = don’t care.
2 LOSEL should not be left floating.
ADRF6703 Data Sheet
Rev. B | Page 10 of 36
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V; TA = 25°C; baseband I/Q amplitude = 1 V p-p differential sine waves in quadrature with a 500 mV dc bias; baseband I/Q
frequency (fBB) = 1 MHz; fPFD = 38.4 MHz; fREF = 153.6 MHz at +4 dBm Re:50 Ω (1 V p-p); 130 kHz loop filter, unless otherwise noted.
0
1
2
3
4
5
6
7
8
9
10
2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600
SSB OUT P UT PO WER ( dBm)
LO FREQUENCY (MHz)
T
A
= –40° C
T
A
= +25°C
T
A
= +85°C
08570-104
Figure 4. Single Sideband (SSB) Output Power (POUT) vs.
LO Frequency (fLO) and Temperature; Multiple Devices Shown
10
11
12
13
14
15
16
17
18
19
20
2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600
1dB OUT P UT COM P RE S S IO N ( dBm)
LO FREQUENCY (MHz)
VS = 5.25V
VS = 4.75V
VS = 5.00V
08570-105
Figure 5. SSB Output 1dB Compression Point (OP1dB) vs. LO Frequency (fLO)
and Temperature; Multiple Devices Shown
–20
–16
–12
–8
–4
0
4
8
12
16
20
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0.1 110
SSB O UTPUT POW E R ( dBm)
SECO ND- ORDER DISTORTION (dBc),
THI RD- ORDER DISTORTION (dBc),
CARRIER FEE DTHRO UGH (dBm),
SIDE BAND S UP P RE S S IO N ( dBc)
BASEBAND I NP UT VOLTAGE (V p-p Differential)
CARRIER
FEE DTHRO UGH (dBm)
THI RD- ORDER DISTORTION (dBc)
SSB O UTPUT POW E R ( dBm)
SIDEBAND
SUPPRESSION (dBc)
SECO ND- ORDER DISTORTION (dBc)
08570-106
Figure 6. SSB Output Power, Second- and Third-Order Distortion, Carrier
Feedthrough and Sideband Suppression vs. Baseband Differential Input
Voltage (fOUT = 2140 MHz)
0
1
2
3
4
5
6
7
8
9
10
2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600
SSB OUT P UT PO WER ( dBm)
LO FREQUENCY (MHz)
V
S
= 5.25V
V
S
= 4.75V
V
S
= 5.00V
08570-107
Figure 7. Single Sideband (SSB) Output Power (POUT) vs.
LO Frequency (fLO) and Power Supply; Multiple Devices Shown
10
11
12
13
14
15
16
17
18
19
20
2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600
1dB OUT P UT COM P RE S S IO N ( dBm)
LO FREQUENCY (MHz)
VS = 5.25V
VS = 4.75V
VS = 5.00V
08570-108
Figure 8. SSB Output 1dB Compression Point (OP1dB) vs. LO Frequency (fLO)
and Power Supply
15
10
5
0
–5
–10
–15
–20
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0.1 110
SSB O UTPUT POW E R ( dBm)
SECO ND- ORDER DISTORTION (dBc),
THI RD- ORDER DISTORTION (dBc),
CARRIER FEE DTHRO UGH (dBm),
SIDE BAND S UP P RE S S IO N ( dBc)
BASEBAND I NP UT VOLTAGE (V p-p Differential)
CARRIER
FEE DTHRO UGH (dBm)
THI RD- ORDER DISTORTION (dBc)
SSB O UTPUT POW E R ( dBm)
SIDEBAND
SUPPRESSION (dBc)
SECO ND- ORDER DISTORTION (dBc)
08570-109
Figure 9. SSB Output Power, Second- and Third-Order Distortion, Carrier
Feedthrough and Sideband Suppression vs. Baseband Differential Input
Voltage (fOUT = 2600 MHz)
Data Sheet ADRF6703
Rev. B | Page 11 of 36
–80
–70
–60
–50
–40
–30
–20
–10
0
2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600
CARRIE R FEE DTHROUGH (dBm)
LO FREQUENCY (MHz)
T
A
= –40° C
T
A
= +25°C
T
A
= +85°C
08570-110
Figure 10. Carrier Feedthrough vs. LO Frequency (fLO) and Temperature;
Multiple Devices Shown
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600
UNDESIRED S IDEBAND (dBc)
LO FREQUENCY (MHz)
T
A
= –40° C
T
A
= +25°C
T
A
= +85°C
08570-111
Figure 11. Sideband Suppression vs. LO Frequency (fLO) and Temperature;
Multiple Devices Shown
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600
OUTPUT IP3AND IP 2 ( dBm)
LO FREQUENCY (MHz)
T
A
= –40° C
T
A
= +25°C
T
A
= +85°C
OIP2
OIP3
08570-112
Figure 12. OIP3 and OIP2 vs. LO Frequency (fLO) and Temperature
(POUT ≈ −2 dBm per Tone); Multiple Devices Shown
– 80
–70
–60
–50
–40
–30
–20
–10
0
2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600
CARRIE R FEE DTHROUGH (dBm)
LO FREQUENCY (MHz)
TA = –40° C
TA = +25°C
TA = +85°C
08570-113
Figure 13. Carrier Feedthrough vs. LO Frequency (fLO) and Temperature After
Nulling at 25°C; Multiple Devices Shown
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600
UNDESIRED S IDEBAND NUL LED ( dBc)
LO FREQUENCY (MHz)
T
A
= –40° C
T
A
= +25°C
T
A
= +85°C
08570-114
Figure 14. Sideband Suppression vs. LO Frequency (fLO) and Temperature
After Nulling at 25°C; Multiple Devices Shown
–80
–75
–70
–65
–60
–55
–50
–45
–40
–35
–30
–25
–20
2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600
THIRD-ORDER DI STORTION (dBc),
SECOND-ORDER DI STORTION (dBc)
LO FREQUENCY (MHz)
THIRD-ORDER DI STORTION
SECOND-ORDER DI STORTION
T
A
= –40° C
T
A
= +25°C
T
A
= +85°C
08570-115
Figure 15. Second- and Third-Order Distortion vs. LO Frequency (fLO) and
Temperature
ADRF6703 Data Sheet
Rev. B | Page 12 of 36
–160
–150
–140
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
1k 10k 100k 1M 10M 100M
PHASE NO I SE, L O F REQUENCY = 2140M Hz ( dBc/ Hz )
OFFSET FREQUENCY (Hz)
2.5kHz LO O P FILTER
130kHz L OOP FILTER
08570-116
T
A
= –40° C
T
A
= +25°C
T
A
= +85°C
Figure 16. Phase Noise vs. Offset Frequency and Temperature, fLO = 2140 MHz
–160
–150
–140
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
110 100 1000 10000 100000
PHASE NO I SE, L O F REQUENCY = 2300M Hz ( dBc/ Hz )
OFFSET FREQUENCY (kHz )
T
A
= –40° C
T
A
= +25°C
T
A
= +85°C
2.5kHz LO O P FILTER
130kHz L OOP FILTER
08570-117
Figure 17. Phase Noise vs. Offset Frequency and Temperature, fLO = 2300 MHz
–160
–150
–140
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
110 100 1000 10000 100000
PHASE NO I SE, L O F REQUENCY = 2600M Hz ( dBc/ Hz )
OFFSET FREQUENCY (kHz )
T
A
= –40° C
T
A
= +25°C
T
A
= +85°C
08570-118
2.5kHz LO O P FILTER
130kHz L OOP FILTER
Figure 18. Phase Noise vs. Offset Frequency and Temperature, fLO = 2600 MHz
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600
INTEGRATE D P HAS E NOI S E ( °rms)
LO FREQUENCY (MHz)
T
A
= –40° C
T
A
= +25°C
T
A
= +85°C
08570-119
Figure 19. Integrated Phase Noise vs. LO Frequency
–150
–140
–130
–120
–110
–100
–90
–80
2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600
PHASE NOI S E , 100kHz O FF S E T (dBc/ Hz )
LO FREQUENCY (MHz)
OFFSET = 1kHz
OFFS E T = 100kHz
OFFSET = 5MHz
08570-120
T
A
= –40° C
T
A
= +25°C
T
A = +85°C
Figure 20. Phase Noise vs. LO Frequency at 1 kHz, 100 kHz, and 5 MHz Offsets
–150
–140
–130
–120
–110
–100
–90
–80
2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600
PHASE NO I SE , 1MHz OFF SET (d Bc/Hz)
LO FREQUENCY (MHz)
OFF S E T = 10kHz
OFFSET = 1MHz
T
A
= –40° C
T
A
= +25°C
T
A
= +85°C
08570-121
Figure 21. Phase Noise vs. LO Frequency at 10 kHz and 1 MHz Offsets
Data Sheet ADRF6703
Rev. B | Page 13 of 36
–120
–110
–100
–90
–80
–70
2100 2200 2300 2400 25002150 2250 2350 2450 2550 2600
SPUR LEVEL (dBc)
LO FREQUENCY (MHz)
2 × PF D FREQUENCY
4 × PF D FREQUENCY
TA = –40° C
TA = +25°C
TA = +85°C
08570-122
Figure 22. PLL Reference Spurs vs. LO Frequency (2× PFD and 4× PFD) at
Modulator Output
–120
–110
–100
–90
–80
–70
–115
–105
–95
–85
–75
2100 2200 2300 2400 25002150 2250 2350 2450 2550 2600
SPUR LEVEL (dBc)
LO FREQUENCY (MHz)
1 × PF D FREQUENCY
3 × PF D FREQUENCY
TA = –40° C
TA = +25°C
TA = +85°C
0.5 × P FD F RE QUENCY
08570-123
Figure 23. PLL Reference Spurs vs. LO Frequency (0.5× PFD, 1× PFD,
and 3× PFD) at Modulator Output
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600
V
TUNE
(V)
LO FREQUENCY (MHz)
T
A
= –40° C
T
A
= +25°C
T
A
= +85°C
08570-124
Figure 24. VTUNE vs. LO Frequency and Temperature
–120
–110
–100
–90
–80
–70
–115
–105
–95
–85
–75
2100 2200 2300 2400 25002150 2250 2350 2450 2550 2600
SPUR LEVEL (dBc)
LO FREQUENCY (MHz)
2 × PF D FREQUENCY
4 × PF D FREQUENCY
TA = –40° C
TA = +25°C
TA = +85°C
08570-125
Figure 25. PLL Reference Spurs vs. LO Frequency (2× PFD and 4× PFD) at LO
Output
–120
–110
–100
–90
–80
–70
–115
–105
–95
–85
–75
2100 2200 2300 2400 25002150 2250 2350 2450 2550 2600
SPUR LEVEL (dBc)
LO FREQUENCY (MHz)
3 × PF D FREQUENCY
0.5 ×, 2 × P FD F RE QUENCY
TA = –40° C
TA = +25°C
TA = +85°C
08570-126
Figure 26. PLL Reference Spurs vs. LO Frequency (0.5× PFD, 2× PFD, and
3× PFD) at LO Output
–180
–160
–140
–120
–100
–80
–60
–40
–20
0
1k 10k 100k 1M 10M
PHASE NO I SE (d Bc/Hz)
FREQUENCY (Hz)
08570-127
LO = 2594. 13M Hz
LO = 2306. 26M Hz
LO = 2138. 95M Hz
Figure 27. Open-Loop VCO Phase Noise at 2138.95 MHz, 2306.26 MHz, and
2594.13 MHz
ADRF6703 Data Sheet
Rev. B | Page 14 of 36
0
10
20
30
40
50
60
70
80
90
100
–164 –163 –162 –161 –160 –159 –158 –157
CUMULAT I VE PERCENTAGE ( %)
NOISE FLOOR (dBm/Hz)
2140MHz
2300MHz
2600MHz
08570-128
Figure 28. IQ Modulator Noise Floor Cumulative Distributions at 2140 MHz,
2300 MHz, and 2600 MHz
–25
–20
–15
–10
–5
0
5
10
15
050 100 150 200 250 300
FREQUENCUY DEVIAT IO N FRO M 2410M Hz ( M Hz )
TIME (µs)
08570-129
Figure 29. Frequency Deviation from LO Frequency at
LO = 2.41 GHz to 2.4 GHz vs. Lock Time
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600
SSB OUTPUT POWER AND LO FEE DTHRO UGH (dBm)
LO FREQUENCY (MHz)
SSB OUTPUT POWER
LO FEEDTHROUGH
08570-130
Figure 30. SSB Output Power and LO Feedthrough with RF Output Disabled
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
–40 –15 10 35 60 85
VPTAT (V)
TEMPERATURE ( °C)
08570-131
Figure 31. VPTAT Voltage vs. Temperature
Data Sheet ADRF6703
Rev. B | Page 15 of 36
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600
RET URN LO S S ( dB)
LO FREQUENCY (MHz)
RF OUT
LO INPUT
08570-132
Figure 32. Input Return Loss of LO Input (LON, LOP Driven Through MABA-
007159 1:1 Balun) and Output Return Loss of RFOUT vs. Frequency
160
180
200
220
240
260
280
300
2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600
SUPPLY CURRENT (mA)
LO FREQUENCY (MHz)
08570-133
T
A
= –40° C
T
A
= +25°C
T
A
= +85°C
Figure 33. Power Supply Current vs. Frequency and Temperature (PLL and
IQMOD Enabled, LO Buffer Disabled)
21
2600MHz 2100MHz
08570-134
Figure 34. Smith Chart Representation of RF Output
ADRF6703 Data Sheet
Rev. B | Page 16 of 36
THEORY OF OPERATION
The ADRF6703 integrates a high performance IQ modulator
with a state of the art fractional-N PLL. The ADRF6703 also
integrates a low noise VCO. The programmable SPI port allows
the user to control the fractional-N PLL functions and the
modulator optimization functions. This includes the capability
to operate with an externally applied LO or VCO.
The quadrature modulator core within the ADRF6703 is a part
of the next generation of industry-leading modulators from
Analog Devices, Inc. The baseband inputs are converted to
currents and then mixed to RF using high performance NPN
transistors. The mixer output currents are transformed to a
single-ended RF output using an integrated RF transformer
balun. The high performance active mixer core, coupled with
the low-loss RF transformer balun results in an exceptional
OIP3 and OP1dB, with a very low output noise floor for excel-
lent dynamic range. The use of a passive transformer balun
rather than an active output stage leads to an improvement
in OIP3 with no sacrifice in noise floor. At 2140 MHz the
ADRF6703 typically provides an output P1dB of 14.2 dBm,
OIP3 of 33.2 dBm, and an output noise floor of −159.6 dBm/Hz.
Typical image rejection under these conditions is −52.3 dBc
with no additional I and Q gain compensation.
PLL + VCO
The fractional divide function of the PLL allows the frequency
multiplication value from REFIN to the LOP/LON outputs to
be a fractional value rather than restricted to an integer as in
traditional PLLs. In operation, this multiplication value is INT
+ (FRAC/MOD) where INT is the integer value, FRAC is the
fractional value, and MOD is the modulus value, all of which
are programmable via the SPI port. In previous fractional-N
PLL designs, the fractional multiplication was achieved by
periodically changing the fractional value in a deterministic
way. The downside of this was often spurious components close
to the fundamental signal. In the ADRF6703, a sigma delta
modulator is used to distribute the fractional value randomly,
thus significantly reducing the spurious content due to the
fractional function.
BASIC CONNECTIONS FOR OPERATION
Figure 35 shows the basic connections for operating the
ADRF6703 as they are implemented on the device’s evaluation
board. The seven power supply pins should be individually
decoupled using 100 pF and 0.1 µF capacitors located as close
as possible to the pins. A single 10 µF capacitor is also recom-
mended. The three internal decoupling nodes (labeled DECL3,
DECL2, and DECL1) should be individually decoupled with
capacitors as shown in Figure 35.
The four I and Q inputs should be driven with a bias level of
500 mV. These inputs are generally dc-coupled to the outputs of
a dual DAC (see the DAC-to-IQ Modulator Interfacing and IQ
Filtering sections for more information).
A 1 V p-p (0.353 V rms) differential sine wave on the I and Q
inputs results in a single sideband output power of 4.95 dBm (at
2140 MHz) at the RFOUT pin (this pin should be ac-coupled as
shown in Figure 35). This corresponds to an IQ modulator
voltage gain of 0.95 dB.
The reference frequency for the PLL (typically 1 V p-p between
12 MHz and 160 MHz) should be applied to the REFIN pin,
which should be ac-coupled. If the REFIN pin is being driven
from a 50 Ω source (for example, a lab signal generator), the
pin should be terminated with 50 Ω as shown in Figure 35 (an
RF drive level of +4 dBm should be applied). Multiples or
fractions of the REFIN signal can be brought back off-chip at
the multiplexer output pin (MUXOUT). A lock-detect signal
and an analog voltage proportional to the ambient temperature
can also be brought out on this pin by setting the appropriate
bits on (DB21-DB23) in Register 4 (see the Register Description
section).
EXTERNAL LO
The internally generated local oscillator (LO) signal can be
brought off-chip as either a 1× LO or a 2× LO (via pins LOP
and LON) by asserting the LOSEL pin and making the appro-
priate internal register settings. The LO output must be disabled
whenever the RF output of the IQ modulator is disabled.
The LOP and LON pins can also be used to apply an external
LO. This can be used to bypass the internal PLL/VCO or if
operation using an external VCO is desired. To tur n off the
PLL Register 6, Bits[20:17] must be zero.
Data Sheet ADRF6703
Rev. B | Page 17 of 36
MUX
RSETNC
NOTES
1. NC = NO CONNEC T. DO NOT CONNECT TO THIS PIN.
CP VTUNE
LOSEL
LON
LOP
2:1
MUX
VCO
CORE
TEMP
SENSOR
DECL2
DECL1
DECL3 RFOUT
OPEN
–
+
CHARGE P UMP
250µA,
500µA (DEFAULT),
750µA,
1000µA
PRESCALER
÷2
MUXOUT
GND
REFIN
ADRF6703
PHASE
FREQUENCY
DETECTOR
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
FRACTION
REG MODULUS INTEGER
REG
N COUNT ER
21 TO 123
×2
÷2
÷4
DIVIDER
÷2
SPI
INTERFACE
C43
10µF
(0603)
C14
22pF
(0603)
CP
TEST
POINT
(OPEN) C13
6.8pF
(0603)
C40
22pF
(0603)
C3
100pF
(0402)
R3
OPEN
(0402)
VCC
VTUNE
OPEN
C15
2.7nF
(1206)
C2
OPEN
(0402)
C1
100pF
(0402)
R38
OPEN
(0402)
R37
0Ω
(0402)
R2
OPEN
(0402)
C42
10µF
(0603)
C17
0.1µF
(0402)
R63
OPEN
(0402)
R65 10kΩ
(0402)
R9 10kΩ
(0402)
R12
0Ω
(0402)
R10
3kΩ
(0603)
R62
0Ω
(0402)
R11
OPEN
(0402)
RFOUT
C16
100pF
(0402)
C41
OPEN
(0603)
C11
0.1µF
(0402)
C12
100pF
(0402)
R16
OPEN
(0402)
C29
100pF
(0402)
C5
100pF
(0402)
R39
10kΩ
(0402)
VCC
S1
R40
10kΩ
(0402)
C6
100pF
(0402)
R73
49.9Ω
(0402)
SEE TEXT
5
EXT LO
REF_IN
REFOUT OPEN
1
4 3
MABA-007159
R20
0Ω
(0402)
R43
10kΩ
(0402)
S2 R47
10kΩ
(0402)
VDDVDDVDDVDDVDDVDD VDD
ENOP
CLK
DATA
LE
C9
0.1µF
(0402)
C10
100pF
(0402)
C27
0.1µF
(0402)
C26
100pF
(0402)
C25
0.1µF
(0402)
C24
100pF
(0402)
C23
0.1µF
(0402)
C22
100pF
(0402)
C20
0.1µF
(0402)
C21
100pF
(0402)
C19
0.1µF
(0402)
C18
100pF
(0402)
C7
0.1µF
(0402)
VCC
RED
+5V
C28
10µF
(3216)
C8
100pF
(0402)
QN
QP
÷2
0/90
IP
IN
QN
QP
IP
IN
R23
OPEN
(0402)
LE (USB)
DATA (USB)
CLK ( US B)
08570-023
Figure 35. Basic Connections for Operation (Loop Filter Set to 130 kHz)
LOOP FILTER
The loop filter is connected between the CP and VTUNE pins.
The return for the loop filter components should be to Pin 40
(DECL3). The loop filter design in Figure 35 results in a 3 dB
loop bandwidth of 130 kHz. The ADRF6703 closed loop phase
noise was also characterized using a 2.5 kHz loop filter design.
The recommended components for both filter designs are
shown in Table 8. For assistance in designing loop filters with
other characteristics, download the most recent revision of
ADIsimPLL™ from www.analog.com/adisimpll. Operation with
an external VCO is possible. In this case, the return for the loop
filter components is ground (assuming a ground reference on
the external VCO tuning input). The output of the loop filter is
connected to the external VCO’s tuning pin. The output of the
VCO is brought back into the device on the LOP and LON pins
(using a balun if necessary).
Table 8. Recommended Loop Filter Components
Component 130 kHz Loop Filter 2.5 kHz Loop Filter
C14 22 pF 0.1 µF
R10 3 kΩ 68 Ω
C15 2.7 nF 4.7 µF
R9 10 kΩ 270 Ω
C13 6.8 pF 47 nF
R65 10 kΩ 0 Ω
C40 22 pF Open
R37 0 Ω 0 Ω
R11 Open Open
R12 0 Ω 0 Ω
ADRF6703 Data Sheet
Rev. B | Page 18 of 36
DAC-TO-IQ MODULATOR INTERFACING
The ADRF6703 is designed to interface with minimal components
to members of the Analog Devices, Inc., family of TxDACs®. These
dual-channel differential current output DACs provide an output
current swing from 0 mA to 20 mA. The interface described in
this section can be used with any DAC that has a similar output.
An example of an interface using the AD9122 TxDAC is shown
in Figure 36. The baseband inputs of the ADRF6703 require
a dc bias of 500 mV. The average output current on each of the
outputs of the AD9122 is 10 mA. Therefore, a single 50 Ω resis-
tor to ground from each of the DAC outputs results in an average
current of 10 mA flowing through each of the resistors, thus
producing the desired 500 mV dc bias for the inputs to the
ADRF6703.
RBIP
50Ω
RBIN
50Ω
OUT1_N
OUT1_P
IP
IN
AD9122 ADRF6703
RBQN
50Ω
RBQP
50Ω
OUT2_P
OUT2_N
QP
QN
08570-033
Figure 36. Interface Between the AD9122 and ADRF6703 with 50 Ω Resistors
to Ground to Establish the 500 mV DC Bias for the ADRF6703 Baseband Inputs
The AD9122 output currents have a swing that ranges from
0 mA to 20 mA. With the 50 Ω resistors in place, the ac voltage
swing going into the ADRF6703 baseband inputs ranges from
0 V to 1 V (with the DAC running at 0 dBFS). So the resulting
drive signal from each differential pair is 2 V p-p differential
with a 500 mV dc bias.
ADDING A SWING-LIMITING RESISTOR
The voltage swing for a given DAC output current can be
reduced by adding a third resistor to the interface. This resistor
is placed in the shunt across each differential pair, as shown in
Figure 37. It has the effect of reducing the ac swing without
changing the dc bias already established by the 50 Ω resistors.
RBIP
50Ω
RBIN
50ΩIN
IP
AD9122 ADRF6703
RBQN
50Ω
RBQP
50Ω
RSL2
(SEE TEXT)
RSL1
(SEE TEXT)
OUT1_N
OUT1_P
OUT2_P
OUT2_N
QP
QN
08570-034
Figure 37. AC Voltage Swing Reduction Through the Introduction
of a Shunt Resistor Between the Differential Pair
The value of this ac voltage swing limiting resistor(RSL as shown
in Figure 37) is chosen based on the desired ac voltage swing
and IQ modulator output power. Figure 38 shows the relation-
ship between the swing-limiting resistor and the peak-to-peak
ac swing that it produces when 50 Ω bias-setting resistors are
used. A higher value of swing-limiting resistor will increase the
output power of the ADRF6703 and signal-to-noise ratio (SNR)
at the cost if higher intermodulation distortion. For most
applications, the optimum value for this resistor will be between
100 Ω and 300 Ω.
When setting the size of the swing-limiting resistor, the input
impedance of the I and Q inputs should be taken into account.
The I and Q inputs have a differential input resistance of 920 Ω.
As a result, the effective value of the swing-limiting resistance is
920 Ω in parallel with the chosen swing-limiting resistor. For
example, if a swing-limiting resistance of 200 Ω is desired
(based on Figure 37), the value of RSL should be set such that
200 Ω = (920 × RSL)/(920 + RSL)
resulting in a value for RSL of 255 Ω.
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
010 100 1000 10000
DIFFERENTIAL SWING (V p-p )
R
SL
(Ω)
08570-235
Figure 38. Relationship Between the AC Swing-Limiting Resistor and the
Peak-to-Peak Voltage Swing with 50 Ω Bias-Setting Resistors
Data Sheet ADRF6703
Rev. B | Page 19 of 36
IQ FILTERING
An antialiasing filter must be placed between the DAC and
modulator to filter out Nyquist images and broadband DAC
noise. The interface for setting up the biasing and ac swing
discussed in the Adding a Swing-Limiting Resistor section,
lends itself well to the introduction of such a filter. The filter
can be inserted between the dc bias setting resistors and the
ac swing-limiting resistor. Doing so establishes the input and
output impedances for the filter.
Unless a swing-limiting resistor of 100 Ω is chosen, the filter
must be designed to support different source and load
impedances. In addition, the differential input capacitance of
the I and Q inputs (1 pF) should be factored into the filter
design. Modern filter design tools allow for the simulation and
design of filters with differing source and load impedances as
well as inclusion of reactive load components.
BASEBAND BANDWIDTH
Figure 39 shows the frequency response of the ADRF6703’s
baseband inputs. This plot shows 0.5 dB and 3 dB bandwidths
of 350 MHz and 750 MHz respectively. Any flatness variations
across frequency at the ADRF6703 RF output have been
calibrated out of this measurement.
–10
–8
–6
–4
–2
0
2
4
10 100 1000
BASEBAND FREQUENCY RESPONSE (dBc)
BB FRE QUENCY (MHz)
08570-234
Figure 39. Baseband Bandwidth
0
0.2
0.4
0.6
0.8
1.0
1.2
400
500
600
700
800
900
1000
0100 200 300 400 500
CAPACITANCE (pF )
RESISTANCE (Ω)
BASEBAND FREQ UE NCY (MHz)
RESISTANCE
CAPACITANCE
08570-141
Figure 40. Differential Baseband Input R and Input C Equivalents (Shunt R,
Shunt C)
DEVICE PROGRAMMING AND REGISTER
SEQUENCING
The device is programmed via a 3-pin SPI port. The timing
requirements for the SPI port are shown in Table 3 and Figure 2.
Eight programmable registers, each with 24 bits, control the
operation of the device. The register functions are listed in
Table 9. The eight registers should initially be programmed
in reverse order, starting with Register 7 and finishing with
Register 0. Once all eight registers have been initially
programmed, any of the registers can be updated without any
attention to sequencing.
Software is available on the ADRF6703 product page at
www.analog.com that allows programming of the evaluation
board from a PC running Windows® XP or Windows Vista.
To operate correctly under Windows XP, Version 3.5 of
Microsoft .NET must be installed. To run the software on
a Windows 7 PC, XP emulation mode must be used (using
Virtual PC).
ADRF6703 Data Sheet
Rev. B | Page 20 of 36
REGISTER SUMMARY
Table 9. Register Functions
Register Function
Register 0 Integer divide control (for the PLL)
Register 1 Modulus divide control (for the PLL)
Register 2 Fractional divide control (for the PLL)
Register 3 Σ-Δ modulator dither control
Register 4 PLL charge pump, PFD, and reference path control
Register 5 LO path and modulator control
Register 6 VCO control and VCO enable
Register 7
External VCO enable
Data Sheet ADRF6703
Rev. B | Page 21 of 36
REGISTER DESCRIPTION
REGISTER 0—INTEGER DIVIDE CONTROL
(DEFAULT: 0x0001C0)
With Register 0, Bits[2:0] set to 000, the on-chip integer divide
control register is programmed as shown in Figure 41.
Divide Mode
Divide mode determines whether fractional mode or integer
mode is used. In integer mode, the RF VCO output frequency
(fVCO) is calculated by
fVCO = 2 × fPFD × (INT) (1)
where:
fVCO is the output frequency of the internal VCO.
fPFD is the frequency of operation of the phase-frequency detector.
INT is the integer divide ratio value (21 to 123 in integer mode).
Integer Divide Ratio
The integer divide ratio bits are used to set the integer value in
Equation 2. The INT, FRAC, and MOD values make it possible
to generate output frequencies that are spaced by fractions of
the PFD frequency. The VCO frequency (fVCO) equation is
fVCO = 2 × fPFD × (INT + (FRAC/MOD)) (2)
where:
INT is the preset integer divide ratio value (24 to 119 in
fractional mode).
MOD is the preset fractional modulus (1 to 2047).
FRAC is the preset fractional divider ratio value (0 to MOD − 1).
DIVIDE
MODE
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 0 0 0 0 DM ID6 ID5 ID4 ID3 ID2 ID1 ID0 C3(0) C2(0) C1(0)
DM
0
1
ID6 ID5 ID4 ID3 ID2 ID1 ID0
0 0 1 0 1 0 1
0 0 1 0 1 1 0
0 0 1 0 1 1 1
0 0 1 1 0 0 0
... ... ... ... ... ... ...
... ... ... ... ... ... ...
0 1 1 1 0 0 0
... ... ... ... ... ... ...
... ... ... ... ... ... ...
1 1 1 0 1 1 1
1 1 1 1 0 0 0
1 1 1 1 0 0 1
1 1 1 1 0 1 0
1 1 1 1 0 1 1
...
...
119
120 (INTEGER MODE ONLY)
INTEGER DIVIDE RATIO
21 (INTEGER MODE ONLY)
22 (INTEGER MODE ONLY)
23 (INTEGER MODE ONLY)
24
...
...
56 (DEFAULT)
INTEGER
INTEGER DIVIDE RATIO CONTROL BITS
DIVIDE MODE
FRACTIONAL (DEFAULT)
121 (INTEGER MODE ONLY)
122 (INTEGER MODE ONLY)
123 (INTEGER MODE ONLY)
RESERVED
08570-014
Figure 41. Register 0—Integer Divide Control Register Map
ADRF6703 Data Sheet
Rev. B | Page 22 of 36
REGISTER 1—MODULUS DIVIDE CONTROL
(DEFAULT: 0x003001)
With Register 1, Bits[2:0] set to 001, the on-chip modulus
divide control register is programmed as shown in Figure 42.
Modulus Value
The modulus value is the preset fractional modulus ranging
from 1 to 2047.
REGISTER 2—FRACTIONAL DIVIDE CONTROL
(DEFAULT: 0x001802)
With Register 2, Bits[2:0] set to 010, the on-chip fractional
divide control register is programmed as shown in Figure 43.
Fractional Value
The FRAC value is the preset fractional modulus ranging from
0 to <MDR.
MODULUS VALUE
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 0 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 C3(0) C2(0) C1(1)
MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0
0 0000000001
0 0000000010
... ... ... ... ... ... ... ... ... ... ...
... ... ... ... ... ... ... ... ... ... ...
1 1000000000
... ... ... ... ... ... ... ... ... ... ...
... ... ... ... ... ... ... ... ... ... ...
1 1111111111
MODULUS VALUE
...
...
2047
CONTROL BITS
1
1536 (DEFAULT)
2
...
...
RESERVED
08570-015
Figure 42. Register 1—Modulus Divide Control Register Map
FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0
0 0000000000
0 0000000001
... ... ... ... ... ... ... ... ... ... ...
... ... ... ... ... ... ... ... ... ... ...
0 1100000000
... ... ... ... ... ... ... ... ... ... ...
... ... ... ... ... ... ... ... ... ... ...
FRACTIONAL VALUE MUST BE LESS THAN MODULUS.
FRACTIONAL VALUE
0
1
...
...
768 (DEFAULT)
...
...
<MDR
FRACTIONAL VALUERESERVED
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
CONTROL BITS
0 0 0 0 0 0 0 0 0 0 FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 C3(0) C2(1) C1(0)
08570-016
Figure 43. Register 2—Fractional Divide Control Register Map
Data Sheet ADRF6703
Rev. B | Page 23 of 36
REGISTER 3—Σ-Δ MODULATOR DITHER CONTROL
(DEFAULT: 0x10000B)
With Register 3, Bits[2:0] set to 011, the on-chip Σ-Δ modulator
dither control register is programmed as shown in Figure 44. The
recommended and default setting for dither enable is enabled (1).
The default value of the dither magnitude (15) should be set to a
recommended value of 1.
The dither restart value can be programmed from 0 to 217 − 1,
though a value of 1 is typically recommended.
DITHER
ENABLE
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 DITH1 DITH0 DEN DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0 C3(0) C2(1) C1(1)
DITH1 DITH0
0 0
0 1
1 0
1 1
DEN
0
1
DITHER
MAGNITUDE DITHER RESTART VALUE CONTROL BITS
DITHER MAGNITUDE
15 (DEFAULT)
7
3
1 (RECOMMENDED)
DITHER ENABLE
DISABLE
ENABLE (DEFAULT, RECOMMENDED)
DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
DV2
0
...
...
1 1
0x00001 (DEFAULT)
...
...
0x1FFFF
DITHER RESTART
VALUE
08570-017
Figure 44. Register 3—Σ-Δ Modulator Dither Control Register Map
ADRF6703 Data Sheet
Rev. B | Page 24 of 36
REGISTER 4—PLL CHARGE PUMP, PFD, AND
REFERENCE PATH CONTROL (DEFAULT:
0x0AA7E4)
With Register 4, Bits[2:0] set to 100, the on-chip charge pump,
PFD, and reference path control register is programmed as
shown in Figure 45.
CP Current
The nominal charge pump current can be set to 250 µA, 500 µA,
750 µA, or 1000 µA using DB10 and DB11 of Register 4 and by
setting DB18 to 0 (CP reference source).
In this mode, no external RSET is required. If DB18 is set to 1,
the four nominal charge pump currents (INOMINAL) can be
externally tweaked according to the following equation:
Ω−
×
=8.37
4.217
NOMINAL
CP
SET
I
I
R
(3)
where ICP is the base charge pump current in microamps.
The PFD phase offset multiplier (θPFD,OFS), which is set by
Bits[16:12] of Register 4, causes the PLL to lock with a
nominally fixed phase offset between the PFD reference signal
and the divided-down VCO signal. This phase offset is used
to linearize the PFD-to-CP transfer function and can improve
fractional spurs. The magnitude of the phase offset is deter-
mined by the following equation:
MULTCP
OFSPFD
I,
,
5.22(deg)
θ
=∆Φ (4)
The default value of the phase offset multiplier (10 × 22.5°)
should be set to a recommended value of 6 × 22.5°.
This phase offset can be either positive or negative depending
on the value of DB17 in Register 4.
The reference frequency applied to the PFD can be manipulated
using the internal reference path source. The external reference
frequency applied can be internally scaled in frequency by 2×,
1×, 0.5×, or 0.25×. This allows a broader range of reference
frequency selections while keeping the reference frequency
applied to the PFD within an acceptable range.
The device also has a MUXOUT pin that can be programmed
to output a selection of several internal signals. The default
mode is to provide a lock-detect output to allow the user to
verify when the PLL has locked to the target frequency. In
addition, several other internal signals can be passed to the
MUXOUT pin as described in Figure 35.
Data Sheet ADRF6703
Rev. B | Page 25 of 36
CP
CURRENT
REF
SOURCE
PFD
POL
CP
SOURCE
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
RMS2 RMS1 RMS
0 RS1 RS0 CPM CPBD CPB4 CPB3 CPB2 CPB1 CPB0 CPP1 CPP0 CPS CPC1 CPC0 PE1 PE0 PAB1 PAB0 C3(1) C2(0) C1(0)
CPC1 CPC0
0 0
0 1
1 0
1 1
CPS
0
1
CPP1 CPP0
0 0
0 1
1 0
1 1
CPB4 CPB3 CPB2 CPB1 CPB0
0 0 0 0 0
0 0 0 0 1
0 0 1 1 0
0 1 0 1 0
1 0 0 0 0
1 1 1 1 1
CPBD
0
1
CPM
0
1
RS1 RS0
0 0
1 0
0 1
1 1
RMS2 RMS1 RMS0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
10 × 22.5°/ICP,MULT (DEFAULT)
16 × 22.5°/ICP,MULT
31 × 22.5°/ICP,MULT
PFD PHASE OFFSET MULTIPLIER
0 × 22.5°/ICP,MULT
1 × 22.5°/ICP,MULT
6 × 22.5°/ICP,MULT (RECOMMENDED)
BOTH ON
PUMP DOWN
PUMP UP
TRISTATE (DEFAULT)
REF OUPUT
MUX SELECT INPUT REF
PATH PFD PHASE OFFSET
MULTIPLIER CP
CURRENT CP
CONTROL PFD EDGE CONTROL BITS
PFD ANTI-
BACKLASH
DELAY
PE0
0
1
REFERENCE PATH EDGE
SENSITIVITY
FALLING EDGE
RISING EDGE (DEFAULT)
PAB1 PAB0
0 0
1 0
0 1
1 1
PFD ANTIBACKLASH
DELAY
0ns (DEFAULT)
0.5ns
0.75ns
0.9ns
CHARGE PUMP CONTROL
0.5× REFIN (BUFFERED)
CHARGE PUMP CONTROL SOURCE
CONTROL BASED ON STATE OF DB7/DB8 (CP CONTROL)
CONTROL FROM PFD (DEFAULT)
REF OUTPUT MUX SELECT
LOCK DETECT (DEFAULT)
VPTAT
REFIN (BUFFERED)
PFD PHASE OFFSET POLARITY
NEGATIVE
POSITIVE (DEFAULT)
CHARGE PUMP CURRENT
REFERENCE SOURCE
INTERNAL (DEFAULT)
EXTERNAL
0.25× REFIN
CHARGE PUMP CURRENT
250µA
500µA (DEFAULT)
750µA
1000µA
INPUT REF
PATH SOURCE
2× REFIN
REFIN (DEFAULT)
0.5× REFIN
2× REFIN (BUFFERED)
TRISTATE
RESERVED
RESERVED
PE1
0
1
DIVIDER PATH EDGE
SENSITIVITY
FALLING EDGE
RISING EDGE (DEFAULT)
08570-018
Figure 45. Register 4—PLL Charge Pump, PFD, and Reference Path Control Register Map
ADRF6703 Data Sheet
Rev. B | Page 26 of 36
REGISTER 5—LO PATH AND MODULATOR
CONTROL (DEFAULT: 0X0000D5)
With Register 5, Bits[2:0] set to 101, the LO path and modulator
control register is programmed as shown in Figure 46.
The modulator output or the complete modulator can be
disabled using the modulator bias enable and modulator
output enable addresses of Register 5.
The LO port (LOP and LON pins) can be used to apply an
external 2× LO (that is, bypass internal PLL) to the IQ
modulator. A differential LO drive of 0 dBm is recommended.
The LO port can also be used as an output where a 2× LO or
1× LO can be brought out and used to drive another mixer.
The nominal output power provided at the LO port is 3 dBm.
The mode of operation of the LO port is determined by the
status of the LOSEL pin (3.3 V logic) along with the settings
in a number of internal registers (see Table 10).
Table 10. LO Port Configuration1, 2
LON/LOP
Function LOSEL
Register 5,
Bit DB5
(LDIV)
Register 5,
Bit DB4
(LXL)
Register 5,
Bit DB3
(LDRV)
Input (2× LO) 0 X 1 0
Output (Disabled) 0 X 0 0
Output (1× LO) 0 0 0 1
Output (1× LO) 1 0 0 0
Output (1× LO) 1 0 0 1
Output (2× LO) 0 1 0 1
Output (2× LO) 1 1 0 0
Output (2× LO) 1 1 0 1
1 X = don’t care.
2 LOSEL should not be left floating.
The internal VCO of the device can also be bypassed. In this
case, the charge pump output drives an external VCO through
the loop filter. The loop is completed by routing the VCO into
the device through the LO port.
RESERVED MOD
BIAS
ENABLE
RF
OUTPUT
ENABLE
LO
OUTPUT
DIVIDER
LO
IN/OUT
CONTROL
LO
OUTPUT
DRIVER
ENABLE
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7
MBE DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 RFEN LDIV LXL LDRV C3(1) C2(0) C1(1)
LDRV
0
1
LDIV
0
1DIVIDE BY 1
DIVIDE BY 2 (DEFAULT)
LO OUTPUT DRIVER
ENABLE
DRIVER OFF (DEFAULT)
DRIVER ON
RFEN
0
1DISABLE
ENABLE (DEFAULT)
RF OUTPUT ENABLE
LO OUTPUT DIVIDE MODE
CONTROL BITS
LXL
0
1LO OUTPUT (DEFAULT)
LO INPUT
LO INPUT/OUTPUT CONTROL
MBE
0
1DISABLE
ENABLE (DEFAULT)
MOD BIAS ENABLE
0 0 0 0 00 0 00 0 0 0
08570-019
Figure 46. Register 5—LO Path and Modulator Control Register Map
Data Sheet ADRF6703
Rev. B | Page 27 of 36
REGISTER 6—VCO CONTROL AND VCO ENABLE
(DEFAULT: 0X1E2106)
With Register 6, Bits[2:0] set to 110, the VCO control and
enable register is programmed as shown in Figure 47.
The VCO tuning band is normally selected automatically by the
band calibration algorithm, although the user can directly select
the VCO band using Register 6.
The VCO BS SRC bit (DB9) determines whether the result of
the calibration algorithm is used to select the VCO band or if
the band selected is based on the value in VCO band select
(DB8 to DB3).
The VCO amplitude can be controlled through Register 6. The
VCO amplitude setting can be controlled between 0 and 63. The
default value of 8 should be set to a recommended value of 63.
The internal VCOs can be disabled using Register 6.
The internal charge pump can be disabled through Register 6.
By default, the charge pump is enabled.
To turn off the PLL (for example, if the ADRF6703 is being
driven by an external LO), set Register 6, Bits[20:17] to zero.
REGISTER 7—EXTERNAL VCO ENABLE
With Register 7, Bits[2:0] set to 111, the external VCO control
register is programmed as shown in Figure 48.
The external VCO enable bit allows the use of an external VCO
in the PLL instead of the internal VCO. This can be advantageous
in cases where the internal VCO is not capable of providing the
desired frequency or where the internal VCO’s phase noise is
higher than desired. By setting this bit (DB22) to 1, and setting
Register 6, Bits[15:10] to 0, the internal VCO is disabled, and
the output of an external VCO can be fed into the part differ-
entially on Pin 38 and Pin 37 (LOP and LON). Because the
loop filter is already external, the output of the loop filter simply
needs to be connected to the external VCO’s tuning voltage pin.
CHARGE
PUMP
ENABLE
3.3V
LDO
ENABLE VCO
ENABLE VCO
SWITCH VCO
BW SW
CTRL
VBSRC
0
1
VCO EN
VCO LDO
ENABLE VCO AMPLITUDERESERVED VCO BAND SELECT FROM SPI
VBS[5:0] VCO BAND SELECT FROM SPI
0x00
DEFAULT 0x20
CHARGE PUMP ENABLE
0x01
….
0x00 0
…. ….
0x18 8 (DEFAULT)
…. ….
0x2B 43
…. ….
0x3F 63 (RECOMMENDED)
0x3F
VCO BW CAL AND SW SOURCE CONTROL
BAND CAL (DEFAULT)
VCO SW
0
1
VCO SWITCH CONTROL FROM SPI
REGULAR (DEFAULT)
BAND CAL
SPI
VCO ENABLE
DISABLE
ENABLE (DEFAULT)
DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
CONTROL BITS
DB23 CPEN L3EN VCO EN VCO SW VC5 VC4 VC3 VC2 VC1 VC0 VBSRC VBS5 VBS4 VBS3 VBS2 VBS1 VBS0 C3(1) C2(1) C1(0)
LVEN
VC[5:0] VCO AMPLITUDE
0
1
LVEN VCO LDO ENABLE
DISABLE
ENABLE (DEFAULT)
0
1
L3EN 3.3V LDO ENABLE
DISABLE
ENABLE (DEFAULT)
0
1
CPEN
DISABLE
ENABLE (DEFAULT)
0
1
000
08570-020
Figure 47. Register 6—VCO Control and VCO Enable Register Map
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 XVCO
EXTERNAL
VCO
ENABLE
RES
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C3(1) C2(1) C1(1)
RESERVED CONTROL BITS
XVCO
0
1INTERNAL VCO (DEFAULT)
EXTERNAL VCO
EXTERNAL VCO ENABLE
08570-021
Figure 48. Register 7—External VCO Enable Register Map
ADRF6703 Data Sheet
Rev. B | Page 28 of 36
CHARACTERIZATION SETUPS
Figure 49 and Figure 50 show characterization bench setups
used to characterize the ADRF6703. The setup shown in
Figure 49 was used to do most of the testing. An automated
VEE program was used to control equipment over the IEEE
bus. The setup was used to measure SSB, OIP2, OIP3, OP1dB,
LO, and USB NULL.
For phase noise and reference spurs measurements, see the
phase noise setup on Figure 50. Phase noise was measured on
LO and modulator output.
PC CONTROL
CONNECTED TO SYSTEM VIA USB TO GPIB ADAPTER
AEROFL
EX IFR 3416 FREQUENCY GENERATOR
(WITH BASEBAND OUTPUTS AT 1MHz)
34980A
WITH 34950 AND (×2) 34921 MODULES
ROHDE AND SCHWARTZ SMT 06 SIGNAL GENERATOR
(REFIN)
AGILENT E4440A PSA SPECTRUM ANALYZER
ADRF670x TEST RACK ASSEMBLY (INTERNAL VCO CONFIGURATION)
ALL INSTRUMENTS ARE CONNECTED IN DAISY CHAIN
FASHION VIA GBIP CABLE UNLESS OTHERWISE NOTED.
+5V FOR
VPOS TO 34950
MODULE
BASEBAND INPUTS AT 1MHz
9-PIN DSUB
CONNECTOR
(REGISTER
PROGRAMMING)
10-PIN CONNECTOR
DC HEADER
RF OUT
REF IN
E3631A POWER SUPPLY
(+6V ADJUSTED TO 5V)
KEITHLEY S46 SWITCH SYSTEM #1
(FOR RFOUT AND REFIN ON 6 SITES)
PROGRAMMING
AND DC CABLE
(×6 FOR MULTISITE)
OUTPUT (REF)
INPUT
(RFOUT)
KEITHLEY S46 SWITCH SYSTEM #2
(FOR BASEBAND INPUTS ON 6 SITES)
34401A DMM (FOR SUPPLY
CURRENT MEASUREMENT)
BASEBAND OUTPUTS
(IN, IP, QN, QP)
6dB
6dB
ADRF6703
EVAL BOARD
08570-043
Figure 49. General Characterization Setup
Data Sheet ADRF6703
Rev. B | Page 29 of 36
ADRF670x PHASE NOISE STAND SETUP
ALL INSTRUMENTS ARE CONNECTED IN DAISY CHAIN FASHION
VIA GBIP CABLE UNLESS OTHERWISE NOTED.
ROHDE AND SCHWARTZ
SMA 100 SIGNAL GENERATOR
AGILENT E3631A POWER
SUPPLY
AGILENT 34401A DMM
(IN DC I MODE, SUPPLY CURRENT
MEASUREMENT)
AGILENT E5052 SIGNAL SOURCE
ANALYZER
34980A MULTIFUNCTION SWITCH
(WITH 34950 AND 34921 MODULES)
AGILENT E4440A SPECTRUM
ANALYZER
KEITHLEY S46 SWITCH SYSTEM 1
(FOR BASEBAND INPUTS ON 6 SITES)
IFR 3416 SIGNAL GENERATOR
(BASEBAND SOURCE)
KEITHLEY S46 SWITCH SYSTEM 2
(FOR IF OUT AND REFIN ON 6 SITES)
INPUT DC
10 PIN CONNECTOR
(DC MEASUREMENT, +5V POS)
AND 9 PIN DSUB
CONNECTOR (VCO AND PLL
PROGRAMMING)
REFIN
IF OUT
REFIN LO OUT
BASEBAND INPUTS
(IP, IN, QP, QN)
PC CONTROL
CONNECTED TO SYSTEM VIA USB TO GPIB ADAPTER
ADRF6703
EVAL BOARD
08570-044
Figure 50. Characterization Setup for Phase Noise and Reference Spur Measurements
ADRF6703 Data Sheet
Rev. B | Page 30 of 36
EVALUATION BOARD
Figure 52 shows the schematic of the device’s RoHS-compliant
evaluation board. This board was designed using Rogers 4350
material to minimize losses at high frequencies. FR4 material
would also be adequate but with the slightly higher trace loss
of this material.
Whereas the on-board USB interface circuitry of the evaluation
board is powered directly from the PC, the main section of the
evaluation board requires a separate 5 V power supply.
The evaluation board is designed to operate using the internal
VCO (default configuration) of the device or with an external
VCO. To use an external VCO, R62 and R12 should be
removed. 0 Ω resistors should be placed in R63 and R11. A
side-launched SMA connector (Johnson 142-0701-851) must
be soldered to the pad labeled VTUNE. The input of the
external VCO should be connected to the VTUNE SMA
connector and a portion of the VCO’s output should be
connected to the EXT LO SMA connector. In addition to
these hardware changes, internal register settings must also
be changed (as detailed in the Register Description section)
to enable operation with an external VCO.
Additional configuration options for the evaluation board are
described in Table 11.
The serial port of the ADRF6703 can be programmed from a
PC’s USB port (a USB cable is provided with the evaluation
board). The on-board USB interface circuitry can if desired be
bypassed by removing the 0 Ω resistors, R15, R17, and R18 (see
Figure 52) and driving the ADRF6703 serial interface through
the P3 4-pin header (P3 must be first installed, Samtec TSW-
104-08-G-S).
EVALUATION BOARD CONTROL SOFTWARE
USB-based programming software is available to download
from the ADRF6703 product page at www.analog.com
(Evaluation Board Software Rev 6.1.0). To install the software,
download and extract the zip file. Then run the following
installation file: ADRF6X0X_6p1p0_customer_installer.exe.
To operate correctly under Windows XP, Version 3.5 of
Microsoft .NET must be installed. To run the software on a
Windows 7 PC, XP emulation mode must be used (using
Virtual PC).
08570-135
Figure 51. Control Software Opening Menu
Figure 51 shows the opening window of the software where the
user selects the device being programmed. Figure 55 shows a
screen shot of the control software’s main controls with the
default settings displayed. The text box in the bottom left corner
provides an immediate indication of whether the software is
successfully communicating with the evaluation board. If the
evaluation board is connected to the PC via the USB cable
provided and the software is successfully communicating with
the on-board USB circuitry, this text box shows the following
message: ADRF6X0X eval board connected.
Data Sheet ADRF6703
Rev. B | Page 31 of 36
MUX
RSETNC
NOTES
1. NC = NO CONNEC T. DO NOT CONNECT TO THIS PIN.
CP VTUNE
LOSEL
LON
LOP
2:1
MUX
VCO
CORE
TEMP
SENSOR
DECL2
DECL1
DECL3 RFOUT
OPEN
–
+
CHARGE P UMP
250µA,
500µA (DEFAULT),
750µA,
1000µA
PRESCALER
÷2
MUXOUT
GND
REFIN
ADRF6703
PHASE
FREQUENCY
DETECTOR
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
FRACTION
REG MODULUS INTEGER
REG
N COUNT ER
21 TO 123
×2
÷2
÷4
DIVIDER
÷2
SPI
INTERFACE
C43
10µF
(0603)
C14
22pF
(0603)
CP
TEST
POINT
(OPEN) C13
6.8pF
(0603)
C40
22pF
(0603)
C3
100pF
(0402)
R3
OPEN
(0402)
VCC
VTUNE
OPEN
C15
2.7nF
(1206)
C2
OPEN
(0402)
C1
100pF
(0402)
R38
OPEN
(0402)
R37
0Ω
(0402)
R2
OPEN
(0402)
C42
10µF
(0603)
C17
0.1µF
(0402)
R63
OPEN
(0402)
R65 10kΩ
(0402)
R9 10kΩ
(0402)
R12
0Ω
(0402)
R10
3kΩ
(0603)
R62
0Ω
(0402)
R11
OPEN
(0402)
RFOUT
C16
100pF
(0402)
C41
OPEN
(0603)
C11
0.1µF
(0402)
C12
100pF
(0402)
R16
OPEN
(0402)
C29
100pF
(0402)
C5
100pF
(0402)
R39
10kΩ
(0402)
VCC
S1
R40
10kΩ
(0402)
C6
100pF
(0402)
R73
49.9Ω
(0402)
SEE TEXT
5
EXT LO
REF_IN
REFOUT OPEN
1
4 3
MABA-007159
R20
0Ω
(0402)
R43
10kΩ
(0402)
S2 R47
10kΩ
(0402)
VDDVDDVDDVDDVDDVDD VDD
ENOP
CLK
DATA
LE
C9
0.1µF
(0402)
C10
100pF
(0402)
C27
0.1µF
(0402)
C26
100pF
(0402)
C25
0.1µF
(0402)
C24
100pF
(0402)
C23
0.1µF
(0402)
C22
100pF
(0402)
C20
0.1µF
(0402)
C21
100pF
(0402)
C19
0.1µF
(0402)
C18
100pF
(0402)
C7
0.1µF
(0402)
VCC
RED
+5V C28
10µF
(3216)
C8
100pF
(0402)
QN
QP
÷2
0/90
IP
IN
QN
QP
IP
IN
R23
OPEN
(0402)
LE (USB)
DATA (USB)
CLK ( US B)
08570-027
Figure 52. Evaluation Board Schematic (Loop Filter Set to 130 kHz)
08570-047
Figure 53. Evaluation Board Top Layer
08570-048
Figure 54. Evaluation Board Bottom Layer
ADRF6703 Data Sheet
Rev. B | Page 32 of 36
Table 11. Evaluation Board Configuration Options
Component Description
Default Condition/Option
Settings
S1, R39, R40 LO select. Switch and resistors to ground LOSEL pin. The LOSEL
pin setting in combination with internal register settings,
determines whether the LOP/LON pins function as inputs or
outputs. With the LOSEL pin grounded, register settings can
set the LOP/LON pins to be inputs or outputs.
EXT LO, T3 LO input/output. An external 1× LO or 2× LO can be applied to
this single-ended input connector. Alternatively, the internal
1× or 2× LO can be brought out on this pin. The differential LO
signal on LOP and LON is converted to a single-ended signal
using a broadband 1:1 balun (Macom MABA-007159, 4.5 MHz
to 3000 MHz frequency range). The balun footprint on the
evaluation board is also designed to accommodate Johanson
baluns: 3600BL14M050 (1:1, 3.3 GHz to 3.9 GHz) and
3700BL15B050E (1:1, 3.4 GHz to 4 GHz).
T3 = Macom MABA-007159
EXT LO SMA connector = installed
REFIN SMA Connector, R73 Reference input. The input reference frequency for the PLL is
applied to this connector. Input resistance is set by R73 (49.9 Ω).
FREFIN = 153.6 MHz
R73 = 49.9 Ω
REFOUT SMA Connector, R16 Multiplexer output. The REFOUT connector connects directly
to the device’s MUXOUT pin. The on-board multiplexer can
be programmed to bring out the following signals:
REFIN, 2× REFIN, REFIN/2, REFIN/4,
Temperature sensor output voltage ( VP TAT ),
Lock detect indicator.
REFOUT SMA connector = open
R16 = open
CP Test Point, R38 Charge pump test point. The unfiltered charge pump signal
can be probed at this test point. Note that this pin should not
be probed during critical measurements such as phase noise.
CP = open
R38 = open
C13, C14, C15, C40R9, R10, R37, R65 Loop filter. Loop filter components. See Table 8
R11, R12, R62, R63, VTUNE SMA
Connector
Internal vs. external VCO. When the internal VCO is enabled,
the loop filter components connect directly to the VTUNE pin
(Pin 39) by installing a 0 Ω resistor in R62. In addition, the loop
filter components should be returned to Pin 40 (DECL3) by
installing a 0 Ω resistor in R12.
To use an external VCO, R62 should be left open. A 0 Ω resistor
should be installed in R63, and the voltage input of the VCO
should be connected to the VTUNE SMA connector. The output
of the VCO is brought back into the PLL via the LO IN/OUT SMA
connector. In addition, the loop filter components should be
returned to ground by installing a 0 Ω resistor in R11.
Loop filter return.
R12 = 0 Ω (0402)
R11 = open (0402)
R62 = 0 Ω (0402)
R63 = open (0402)
VTUNE = open
R2 RSET. This pin is unused and should be left open. R2 = open (0402)
R23, R3 Baseband input termination. Termination resistors for the
baseband filter of the DAC can be placed on R23 and R3. In
addition to terminating the baseband filters, these resistors
also scale down the baseband voltage from the DAC without
changing the bias level. These resistors are generally set in the
100 Ω to 300 Ω range.
R3 = R23 = open (0402)
P3 4-Pin Header, R15, R17, R18 USB circuitry bypass. The USB circuitry can be bypassed,
allowing for the serial port of the ADRF6703 to be driven
directly. P3 (Samtec TSW-104-08-G-S) must be installed, and
0 Ω resistors (R15, R17 and R18) must be removed.
P3 = open
R15, R17, R18 = 0 Ω (0402)
Data Sheet ADRF6703
Rev. B | Page 33 of 36
08570-136
Figure 55. Main Controls of the Evaluation Board Control Software
ADRF6703 Data Sheet
Rev. B | Page 34 of 36
08570-028
Figure 56. USB Interface Circuitry on the Customer Evaluation Board
Data Sheet ADRF6703
Rev. B | Page 35 of 36
OUTLINE DIMENSIONS
1
40
10
11
31
30
21
20
4.25
4.10 S Q
3.95
TOP
VIEW
6.00
BSC SQ
PI N 1
INDICATOR 5.75
BSC SQ
12° M AX
0.30
0.23
0.18 0.20 REF
SEATING
PLANE
1.00
0.85
0.80
0.05 M AX
0.02 NOM
COPLANARITY
0.08
0.80 M AX
0.65 TYP
4.50
REF
0.50
0.40
0.30
0.50
BSC
PI N 1
INDICATOR
0.60 M AX
0.60 M AX
0.25 M IN
EXPOSED
PAD
(BOT TOM VIEW)
COMPLIANT TO JE DE C S TANDARDS MO-220- V JJD- 2
072108-A
FOR PRO P E R CONNECTI ON O F
THE EXPOSED PAD, REFER TO
THE P IN CONFI GURAT IO N AND
FUNCTION DES CRIPTI ONS
SECTION OF THIS DATA SHEET.
Figure 57. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
6 mm × 6 mm Body, Very Thin Quad
(CP-40-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range (°C) Package Description Package Option
ADRF6703ACPZ-R7 −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-40-1
ADRF6703-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
ADRF6703 Data Sheet
Rev. B | Page 36 of 36
NOTES
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08570-0-10/11(B)
Mouser Electronics
Authorized Distributor
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