Winbond = eEchoe Electronics Carp. ore GENERAL DESCRIPTION W78E51 8-BIT MTP MICROCONTROLLER The W/8E51 is an 8-bit microcontroller that is functionally compatible with the W78C51 except that the mask ROM is replaced by a flash EEPROM whose size is 4K bytes. For the user to program and verity their code easily, the flash EEPROM inside the W78E51 allows the program memory to be programmed and read electronically. Once the code is confirmed, the user can protect their code for security. The W78E51 microceniroller supplies a wider frequency range than most 8-bit microconirollers on the market. It is functionally compatible with the industry standard 80C51 microcontroller series. The W/8E41 contains four 8-bit bidirectional and bit-addressable I/O ports, two 16-bit timer/counters, and a serial port. These peripherals are supported by a five-source, two-level interrupt capability. There are 128 bytes of RAM and an 4 KB flash EEPROM for application programs. The W78E51 microcontroller has two power reduction modes, idle mode and power-down mode, both of which are software selectable. The idle mode turns off the processor clock but allows for continued peripheral operation. The power-dewn mode stops the crystal oscillator for minimum power consumption. The external clock can be stopped at any time and in any state without affecting the processor. FEATURES 8-bit CMOS microcontroller Fully static design Low standby current at full supply voltage DG-40 MHz operation * 128 bytes of on-chip scratchpad RAM 4 KB electrically erasable/programmable EPROM 64 KB program memory address space 64 KB data memory address space Four 8-bit bidirectional ports Two 16-bit timer/counters One Tull duplex serial port Boolean processor Five-source, two-level interrupt capability Built-in power management Goce protection mechanism Packages: DIP 40: W78E51-16/24/40 PLCC 44: W78E51P-16/2440 QFP 44: W78E51F-16/24/40 TQFP 44: W78E51M- 16/24/40 Publication Release Date: October 1997 Revision A3W78E51 \ Winbond KEELES Flentronic rr + Electronics Corn, IIIS SI DIS IIIB ISIS I IIIS IO SII IIE SII SIP II SSIS SIP ONI SID OSII IDES II OID IEE SII SID NIIIOPIIIIOWISIBOMIIIIESIISIPIIIIOIISIDINI IID ISPD IDES II OID IIBESII IID HII SOPIIIIOIISIIOMIISIESIIIIPRIISOIIIEP OI IIDOSIIIIOSIION PIN CONFIGURATIONS fetthey, 40-Pin DIP (W78E5 1) po Ot 4 49 B vo At 2 339 1 Po.0, ADO rPi2 O 3 38 1 PO4.AD1 pis 4 37 PO2. AD? pi4 5 36 ) P03, ADS pris O 6 35 O P04. AD4 Pie O 7 34 1 P05, ADS Pi7 & 33 1 P06. AD8 rast Cf 8 $2 1 P07. AD7 ASCTAL, RXD,P3.0 C 10 31 [7 EA, Vee AISCTRL. TXD. P31] 11 30 1 ALE AJ4CTRL. INTO. P32 ] 12 23 1 Psen OECTAL, INT1. P33 13 2a 1 P27.A15 To,P34 O 14 27 7 P26. At4 __ T1.P35 Of 15 76 P25. 413 CE.WR.PS6 16 25 p24, ai2 GE,RD.P37 O17 24 P23. att xTAL2 | 18 23 7 P22. A10 XTALT 19 22 1 P21, a9 Vss [ 20 21 P20, a8 44-Pin PLCC (W78E5 LP) 44-Pin QFP/TQFP (W78E5 LF/W78E5 LM) AR AA 5585 Bo BOD 047 28 91 23 : PPPPP P POPP pega voco8 rrr roy oa oo Nc 4324505004 28 4324909000123 6 5 4 3 2 1 4443 42 41 40 4443 42 41 4039 38 37 36 35 34 PLS 7 S 39 P04 AD4 PLS 19 33 (FO P04, AD4 P18 8 38 P05. ADS PLB 2 32 [O p05, ADS PL? g 37 Poe. ADB mF 3 31 [O Poe. Ade RST 10 36 7 P07, AD7 RST 4 30 FO P07, AD? ASCTAL, AXD, P3.0 " 35 EA Vee ASCTRL. RXD. PS.0 5 29 FO EA NC 12 4 Of ANC NC 8 28 FO Ne AISCTAL,TXD, P3.1 13 33: ALE AT3CTAL.TXD. P34 ? 27 0 ALE AI4CTAL, INTO, P32 14 32 1 PSeEN ATACTRL, INTO, P32 8 28 ED sen OECTRL, INT1, P3.3 15 3 P27, a5 OFCTRL INTI.F33 4 25 CO p27, 415 TO, P34 16 30) P28. Al4 To P34 10 24 TT P26. A14 THPSS Ye 49 20 21 22 23 24 25 2B 27 28. Hy F2.8,ats TT. PSS "te 13 14.75 1817 1819 20 24 Pad Po Fes. A'8 PPX XYNPP PPA PPX XYN PPPPP 33TTSC22222 337TTSC 222 22 . AAS AAS 8 FLL 041234 BFLLE o12 3 4 . , 24 : 24 tof AAAASA if AAA ARK WR egdi4 wA agi RD 042 RD 0 12 i Lo co o 6 EE EE1 : maser SOR Ps, PIN DESC W78E51 Winbond Electronics Corn, SIRES I SIDS IIIS IIIS II IIIS RIPTION The W78E51 runs under two operation modes, normal and flash. Under the normal mode, the W78E51 corresponds to W78C51. Under the flash mode, the user (the maker of the flash EEPROM writer) can access to the flash EEPROM. P0.7-P0.0 Port 0, Bits 7-0 MODE DESCRIPTION Normal Functions are the same as those in the W/8C51. Flash This port provides the data bus during access to the flash EEPROM. P1.7-P1.0 Port 1, Bits 7-0 MODE DESCRIPTION Normal Functions are the same as those in the W/8C51. Flash This port provides the low order address bus during access to the flash EEPROM. P2.7-P2.0 Port 2, Bits 7-0 MODE DESCRIPTION Normal | Functions are the same as those in the W78C51. Flash This port provides the high order address bus during access to the flasn EEPROM. P3.7-P3.0 Port 3, Bits 7-0 MODE DESCRIPTION Normal | Functions are the same as those in the W78C51. Flash P3.3-P3.0 and P3.7-P3.6 are the flash mode configuration pins, Input. P3.3-P3.0 and P3.7-P3.6 are configured to select or execute the flash operations. For details, see Flash Operations. EA/Vep MODE DESCRIPTION Normal EA, External Access, Input, active low. This pin forces the processor to execute program from the external ROM. When the internal flash EEPROM is accessed like the W78C51, this pin should be kept high. Flash VPP, Program Power supply pin, Input. This pin accepts high voltage that is needed by the program operations to the flash EEPROM. The program operation needs 12V. Publication Release Date: October 1997 Revision A3W78E51 Athy & Winbond RST MODE DESCRIPTION Normal RST, Reset, Input, active high. This pin resets the processor. It must be Kept high for at least two machine cycles in order to be recognized by the processor. Flash Flash mode configuration pin, Input, active high. RST is used to contigure the flash operations. For details, see Flash Operations. ALE MODE DESCRIPTION Normal | ALE, Address Latch Enable, Output, active high. ALE is used to enable the address latch that separates the address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. A single ALE pulse is skipped during external data memory accesses. ALE goes to a high impedance state with a weak pull-up during reset state. Flash Flash mode configuration pin, Input, active low. ALE is used to configure the flash operations. For details, see Flash Operations. PSEN MODE DESCRIPTION Normal | PSEN Program Store Enable, Output, active low. This pin enables the external ROM onto the Port 0 address/data bus during fetch and MOVC operations. PSEN goes to a high impedance state with a weak pull-up during reset state. Flash Flash mode configuration pin, Input, active high. PSEN is used to contigure the flash operations. For details, see Flash Operations. XTAL1 MODE DESCRIPTION Normal | Grystal 1. This is the crystal oscillator input. This pin may be driven by an external clock. Flash Connect to VSS. XTAL2 MODE DESCRIPTION Normal | Crystal 2. This is the crystal oscillator output. It is the inversion of XTAL1. Flash No use on this mode. Vss, Vcc Power Supplies. These are the chip ground and positive supplies.W78E51 G Winbond NE Flectronics Corn. SRR TITIES BLOCK DIAGRAM RAM SFR 128 Bytes CPU Data Bus CORE FLASH EEPROM 4K Byles FUNCTIONAL DESCRIPTION The W78ES51 architecture consists of a core controller surrounded by various registers, four general purpose I/O ports, 128 bytes of RAM, three timer/counters, and a serial port. The processor supports 111 different opcodes and references both a 64K program address space and a 64K dala storage space. Timers 0 and 1 Timers 0 and 1 each consist of two 8-bit data registers. These are called TLO and THO for Timer 0, TL1 and TH1 for Timer 1. The TCON and TMOD registers provide control functions for timers 0, 1. Clock The W78E51 is designed to be used with either a crystal oscillator or an external clock. Internally, the clock is divided by two before it is used. This makes the W78E51 relatively insensitive to duty cycle variations in the clock. Crystal Oscillator The W78E51 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each pin to ground,and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC bias when the crystal frequency is above 24 MHz. Publication Release Date: October 1997 -5- Revision A3W78E51 Athy @ Winbond SOR Electronics Corn, SIRES I SIDS IIIS IIIS II IIIS External Clock An external clock should be connected to pin XTAL1. Pin XTAL2 should be lett unconnected. The XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock signal should have an input one level of greater than 3.5 volts. Power Management Idle Mode The idle mode is entered by setting the IDL bit in the PCON register. In the idle made, the internal clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The processor will exit idle mode when either an interrupt or a reset occurs. Power-down Mode When the PD bit of the PCON register is set, the processor enters the power-down mode. In this mode all of the clacks, including the oscillator are stopped. The only way to exit power-down mode is by a reset. Power Reduction Function The status of the external pins during the idle and power-down modes for the W78E51 is shown in the following tables. ALE PSEN PO P41 P2 P3 Idle internal 1 1 Data Data Data Data external 1 1 Float Data Addr. Data Power internal 0 0 Data Data Data Data Down external 0 0 Float Data Addr. Data Reset The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to deglitch the reset line when the W/8E51 is used with an external RC network. The reset logic also has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to OOH, and all of the other SFR registers except SBUF to OOH. SBUF is not reset. Option Setting The users write the program into W78E51 by the Winbond proprietorial writer. The writer programs the data into internal 4K bytes region under programming operation and reads back to verify data. After contirming program all right, the user can lock the data and no data can be read again.W78E51 Athy a Hinbond CEPTS 5 SESE Electronics Corp Peebcccett AEE EEE Lock Bit This bit is used to protect the customer data in the W78E51. It may be turned on after the programmer finish the programming and verify sequence. Once this bit is set to logic 0, no flash data can be accessed again. MOVC Execute This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the program to be downloaded using this instruction if the program needs to jump outside to get data. When this bit is set to logic 0, a MOVC instruction in external program memory space will be able to access code in the external memory, but it will not be able to access code in the internal memory. A MOVG instruction in internal program memory space will always be able to access code in both internal and external memory. If this bit is logic 1, there are no restriction on the MOVG instruction. Flash Operations Under the normal operation, the W78E51 is functionally compatible with the W78C51. During the flash operation mode, the flasn EEPROM can be programmed and veritied. Until the code inside the flash EEPROM is confirmed OK, the code can be protected. The flash EEPROM and those operations on it are described as below. The W78E51 has several operations on the flash mode. All these operations are contigured by the pins RST, ALE, PSEN, ASCTRL (P3. 0), A A13CTRL (P3.1), A14CTRL (P3.2), OECTRL (P3.3), CE (P3.6), OE (P3.7), AO (P1.0) and VPP (EA). Moreover, the A15 to AO (P2.7 to P2.0, P1.7 to P1.0) and the D7 to DO (P0.7 to P0.0) serve as the address and data bus respectively for these operations. Read Operation This operation is supported for customer to read their code and the Option bits. The data will not be valid if the Lock bit is programmed to low. Program Operation This operation is used to program the data to flash EEPROM and the Option bits. Program operation is done when the VPP is reach to VcP (12V) level, CE set to low, and OE set to high. Program Verify Operation All the programming data must be checked after program operation. This operation should be performed after each byte is programmed and it will ensure a substantial program margin. OPERATIONS] P3.0 | P3.1 | P3.2 | P3.3 | P3.6|P3.7| EA | P2,P1 PO | NOTES (AQ | (A13 | (A14 | (OE | (CE) | (OE) | (Ver) | (A15-A0)| (D7D0) CTRL)|CTRL)| CTRL}| CTRL) Read Vi | Vi | Vue | vu | ve | Vi | Vin_| Address | Data Out| 1,2 Program VIL VIL VIL VIL VIL | VIH | Vcp | Address | Data In 1,2 Program Verify} VIL VIL VIL VIL VIH_ | VIL | VcP | Address | Data Out 3 Notes: 1. All these operations happen in RST = Vin, ALE = Vi_ and PSEN = Vin. 2. Vcp = 12V, Vep = 14.5V, VIH = VbbD, VIL = Vss. 3. The program verify operation is fallowing behind the program operaion. Publication Release Date: October 1997 -7- Revision A3Winbond fetthey, W78E51 SPIRIT, Continued +5 +5V AD tO AT PGM DATA Ato AT PGM DATA VIL Vop VIL Vee VIL VIL VIL vi VIL Vib vit Vin Vib iH VIL VIH Vi Vin VIL VIH AB to AIS AB to AIS Programming Configuration Programming Verification ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL MIN. MAX. UNIT DG Power Supply Vbb-Vss -0.3 +7.0 Vv Input Voltage VIN Vss -0.3 VDD +0.3 Vv Operating Temperature TA 0 70 C Storage Temperature TST -55 +150 C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. DC CHARACTERISTICS Vec-Vss = 5V +10%, TA = 25 C, Fosc = 20 MHz unless otherwise specified. PARAMETER SYMBOL | TEST CONDITIONS SPECIFICATION UNIT MIN. MAX. Operating Voltage VDD 4.5 5.5 Vv Operating Current IDD No load VDD = 5.5V - 50 mA Idle Current IIDLE Idle mode VoD = 5.5V - 7 mA Power Down Current IPWDN Power-down mode - 50 LA Vob= 5.5V Input Current P1, P2, P3 IInd VpD = 5.5V -50 +10 LA VIN = OV or VDDW78E51 Athy @ Winbond SOR Electronics Corn, SIRES I SIDS IIIS IIIS II IIIS DC Characteristics, continued PARAMETER SYMBOL | TEST CONDITIONS SPECIFICATION UNIT MIN. MAX. Logical 1-to-0 Transition ITL VDD = 5.5V -650 - LA Current P1, P2, P3 vin =2.0v !) Input Current RST '*) lin2 | VoD = 5.5V VIN= VoD - +300 uA Input Leakage Current ILK VbbD = 5.5V -10 +10 pA PO, EA OV < VIN < VDD Output Low Voltage VoLi Vop= 4.5V - 0.45 Vv P1, P2, P3 lOoLi = +2 mA Output Low Voltage Vole Vop= 4.5V - 0.45 V ALE, PSEN, Po (3) loL2 = +4 mA Output High Voltage VOH1 Vbp = 4.5V 2.4 - Vv P1, P2, P3 IOH1 = -100 WHA Output High Voltage VouHe Vop= 4.5V 2.4 - Vv ALE, PSEN, Po (3) lOH2 = -400 WA Input Low Voltage VILI VoD= 4.5V 0 0.8 Vv (Except RST) Input Low Voltage VIL2 Vop= 4.5V 0 0.8 Vv Rst 4) Input Low Voltage VIL3 VpD= 4.5V 0 0.8 Vv xTAL1 4) Input High Voltage VIHI Vop= 4.5V 2.4 Vbb +0.2 Vv {Except RST) Input High Voltage VIH2 Vop= 4.5V 2.4 Vbb+0.2 Vv Rst Input High Voltage VIH3 VoD= 4.5V 3.5 Vbb +0.2 Vv XTAL1 4) Notes: 1. Pins of P1, P2 and P3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 2. RST pin has an internal pull-down resistor. 3. PO, ALE, PSEN are in the external access mode. 4. XTAL1 is a CMOS input and RST is a Schmitt trigger input. Publication Release Date: October 1997 -9- Revision A3W78E51 an G Winbond NE Flectronics Corn. SRR TITIES AC CHARACTERISTICS The AC specifications are a function of the particular process used to manufacture the part, the ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications can be expressed in terms of multiple input clock periods (TCP), and actual paris will usually experience less than a +20 nS variation. The numbers below represent the performance expected from a 0.8 micron GMOS process when using 2 and 4 mA output buffers. Clock Input Waveform TALL _| \e/ es we To _ _ me PARAMETER SYMBOL MIN. TYP. MAX. UNIT | NOTES Operating Speed FoP 0 - 40 MHz 1 Clock Period TcP 25 - - ns 2 Clock High TCH 10 - - ns 3 Clock Low TCL 10 - - ns 3 Notes: 1. The clock may be stopped indefinitely in either state. 2. The TcP specification is used as a reference in other specifications. 3. There are no duty cycle requirements on the XTAL1 input. Program Fetch Cycle PARAMETER SYMBOL MIN. TYP. MAX. UNIT | NOTES Address Valid to ALE Low TAAS 1TcP-A - - ns 4 Address Hold from ALE Low TAAH 1 TCP-A - - ns 1,4 ALE Low to PSEN Low TAPL 1 TcP-A - - ns PSEN Low to Data Valid TPDA - - 2Tcr | nS 2 Data Hold after PSEN High TPDH 0 - 1 Top ns Data Float after PSEN High TPDZ 0 - 1 Tcp ns ALE Pulse Width TALW 2TcrP-A | 2TcP - ns 4 PSEN Pulse Width TPSw 3Tcp-A | 3TcP - ns 4 Notes: 1. PO.0-P0.7, P2.0P2.7 remain stable throughout entire memory cycle. 2. Memory access time is 3 Top. 3. Data have been latched internally prior to PSEN going high. 4. "A" (due to buffer driving delay and wire loading) is 20 nS. -10-Athy @ Winbond SOR Electronics Corn, SIRES I SIDS IIIS IIIS II IIIS Data Read Cycle W78E51 PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE ALE Low to RD Low TDAR 3 TCP -A - 3 Top + ns 1,2 A RD Low to Data Valid TDDA - - 4 TcP ns 1 Data Hold from RD High TDDH 0 - 2Tcp ns Data Float from RD High Tpbz 0 - 2TcP ns RD Pulse Width TDRD 6Tcr-A | 6TcP - ns 2 Notes: 1. Data memory access time is 8 TcP. 2. "A" (due to buffer driving delay and wire loading) is 20 nS. Data Write Cycle PARAMETER SYMBOL MIN. TYP. MAX. UNIT ALE Low to WR Low TDAW 3 TCP -A - 3TcP+A| nS Data Valid to WR Low TDAD 1 Tcp-A - - ns Data Hold from WR High Towp 1 Tcp-A - - ns WR Pulse Width TDWR 6Tcr-A | 6TCP - ns Note: "A" (due to buffer driving delay and wire loading) is 20 nS. Port Access Cycle PARAMETER SYMBOL MIN. TYP. MAX. UNIT Port Input Setup to ALE Low TPDS 1 Top - - ns Port Input Hold trom ALE Low TPDH 0 - - ns Port Output to ALE TPDA 1 TcP - - ns Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referencedto ALE, since it provides a convenient reference. Program Operation PARAMETER SYMBOL MIN. TYP. MAX. UNIT VpP Setup Time TvPS 2.0 - - us Data Setup Time TDs 2.0 - - ns Data Hold Time TDH 2.0 - - us Address Setup Time TAS 2.0 - - ns Publication Release Date: October 1997 -ii- Revision A3Winbond fetthey, Program Operation, continued W78E51 SPIRIT, PARAMETER SYMBOL | MIN. | TYP. | MAX. | UNIT Address Hold Time TAH 0 - - LS CE Program Pulse Width for PROGRAM operation | TPWP 95 | 100 | 105 | us OECTRL Setup Time Tocs 2.0 - - LS OECTRL Hold Time TOCH 2.0 - - us OE Setup Time TOES 2.0 - - us OE high to output Float TDFP 0 - | 180) ons Data Valid from OE TOEV - - ie Note: All the flash data access must be under flash mode condition, and the RST pin must pull in VIH status, the ALE pin must pull in Vit status, and the PSEN PSEN pin must pull in Vin status. TIMING WAVEFORMS Program Fetch Cycle XTALI PORT 2 PORT @ | S1 |, S2 ; $3 | S4 |, S5 | SB, SI | S2 |, 83 | S4 | SH | SEY JUUU UU UU UU UU UU UU Taw J fo oL TapL Tesw TAAS TpDA TAAH + Tepy, Tpoz i ee eo Code A0-A7 Data A0-A7 Code = A0-A7 Data A0-A7 -]2-W78E51 Winbond ott Electronics Corp. PRISE IETS, fetthey, & Timing Waveforms, continued Data Read Cycle j; 34, 3 | 56 |) Si | S2 , 53) S4 | SH | SB, St | S2 | S83 | A TUL ALE | | | | | | PSEN _| | | PORT 2 x AS-A15 x x AQ-A7 DATA Porro _-<__ > { -~<__>_L}+<_>> _ Je DAR, TDPA | TppH, Tppz RD TDRD Data Write Cycle | S4 | $5 | S6 | $1 | $2 | 83 | S4 | 85 | S6 | $1 | $2 | 83 | SA TUF ALE | | | PSEN LJ LL AB-A15 x 4 BATA OUT PORT 2 PORT 0 T, WR DAD Tpaw TpwR Publication Release Date: October 1997 -13- Revision A3W78E51 : Winbond citi Electronics Corp AIR IERIE SONI III IIIB IOI II RE SMI INI III IRIS SOI IIIB SIDI D ESI DDSI DI DID IB OOISIII ODI SOD IIIS DIDI I ISOS ISIS OS IOI I ESO DB DII ENE SID IDOI ISIS IS SSDI IBID III D DESO DIDI I ES ISII OOO SOOO SION & TES. & Timing Waveforms, continued Port Access Cycle 55 I 356 I S1 XTAL1 rf LIF LJ LOI LO ALE | | Tpos | |, TPDH __TPDA = | | PORT x x >X_DATA QUT INPUT | SAMPLE Program Operation Program Program : pe Verify y Read Verify p2,P1 IH - (A15... AO) y xX Address Stable { Address Valid x IL T, r P36 V4, pt L Tewe \ / (CE) ML na P3.3 Mn Tax (QECTRL) pilo cog os \ qe IL ! OCH 1 P37 VL i+ LL f. | Cy ea /T \__/ V Torq _ err Po IH (A7... AQ) + Data In Dour { Data Out \- Mie h Tos q > q Vep Vpp f Toev Vin p Types _J4-W78E51 . inbond ott Electronics Corp. PRISE IETS, TYPICAL APPLICATION CIRCUITS fetthey, & Expanded External Program Memory and Crystal Voc ee [at ca PO.0 =~ Do au AQ ooLli__Abo 13 PO.1 Di ai Al ol XTALI PO.2 be G2 AZ 02 410Uu P03 D3 93 A O3 C$ 128 PO.4 D4 a4 Ad o4 XTAL2 PO.5 D5 O5 AS o5 CRYSTAL PO.6 D6 Q6 AG oss PO.7 D7 G7 AT O7 19 3 | RST AB Pz.0 os Ag otf Tee NTO P24 G Ato > TF 129g P2.2 All 13 INT1 P2.3 74LS373 Alz 14] To P24 A13 15/71 P25 Al4 P2.6 AIS 1| P1.0 P27 = 2 | P14 _ GND 20 | cE 3 | P12 AD [47 12 4 ta WR Ls 5 . BeENb2a 27512 5] P15 PeEN ao _zZ_| P16 Txp Hie a | P17 Axp Lo W78E51 Figure A CRYSTAL C1 C2 R 16 MHz 30P 30P - 24 MHz 15P 15P - 33 MHz 10P 10P 6.8K 40 MHz 5P 5P 6.8K Above table shows the reference values for crystal applications. Note: C1, C2, R components refer to Figure A. Publication Release Date: October 1997 -15- Revision A3& cE, & Winbond SEE Flentronics Corp Typical Application Circuits, continued Expanded External Data Memory and Oscillator W78E51 PRISE IETS, -16- Vec Vi oe 31 [ P.O Do I 19 EA PO.1 Di XTAL1 PO.2 D2 + 10y |OSCILLATOR Po.3 D3 Po.4 D4 18 | xTAL2 PO.5 D5 PO.6 D6 B2K PO.7 D7 9 | RST P2.0 P2.1 = izq INTO P22 13g INT1 P2.3 14) To P2.4 15 TH P25 P2.6 1] Pio P2.7 [28 24 PA Rb L Pi2 2 4] P13 WR 16 54 Pid hyeo 20256 6| pis Pete p30 Z P16 TXD Lid A| P17 RXD Lio W78E51 Figure BW78E51 ett, & Winbond SEE Flentronics Corp. SRR TITIES PACKAGE DIMENSIONS 40-pin DIP Symbol Dimension in inch Dimension in mm Min. | Nom. | Max. | Min. | Nom. | Max. A | [oe | | | saa At ooo | | Joa] | fiz 0150 [0185 [0.160 | 3.64 3987 | 4.064 B OO OO | 0.082 0.406 | 0457 | 0.589 Bu 0.048 | 0.050 | 0.054 1.219 | 127 1.32 Cc 0008 | OO10 | O.014 0.203 | 0254 | 0.356 o D |2055 | 2.070 |5220 | 6258 Antanas E [esac |osco |oeto pases |ts24 5.404 E 1 O540 |O545 |os50 [1372 | 13.44 | ia97 @ 06090 | 0.100 [0.110 | 2286 254 | 2704 ra O C) L 0120 | 0130 [0.140 |S04@ | 3302 | 3556 a a | 45 0 | 15 o @a 0630 | 0.650 | 0.670 | 16.00 | 16.51 | 17.04 Wuyi a oi ot ot a ot Ss _ | O00 _ | 2288 * Notes ln = Dimension D Max. & & include mold flash or ha Dimension E1 does not include interlead flash AD HOBO OBOEPOUUUOOUOOUODUD rls] ome Plane t Geren &E1 include mold mismatch and rrr | L | | | | | | |! | TE seating Plane are determined at the mold parting line. . Dimension Bi dees not include dambar protrusion/intrusion. | op By le rz . Controlling dimension: Inches. . General appearance spec. should be based on final visual inspection spec. m 44-pin PLCC ; o Dimension in inch Dimension in mm 144 a ee Symbcl ~ oO Min. | Nom. | Max. | Min. |Nom. | Max. 7d On A | |ores | | |a609 q 0 A ooz0 | | |nsna | | q H Az [ots [0.150 [otss [3ee3 [3.1 bar q H b, [0.026 Jo.ozs Joos fose [o711 [vais q LJ b D016 [0.018 [0.022 |D4D6 Jno gsy | 0.559 q p E He Ge Cc 0.008 |0.010 0014 |O0203 [0254 | 0356 4 E D [oes josss loess [i646 [16.58 [16.71 q 0 E O648 |0.653 |0658 |1646 |16.58 (16.71 q 4 fel 0.050 BSC 1.27 BSC rf Hs G, [0.590 |oe10 [0630 |1493 [isa 16.00 Ge [0590 |o.sin |naso [14.99 [15.49 [16.00 Ho [0.680 |o.sa0 [ooo [17.27 |17s3 [17.78 He [0.680 |o.sao [0.700 |17.27 |17.53 [17.78 L o.og0 [0.100 jo iio |pzas | 254 |2794 y | [novos | | |{oi0 Co a a Ae Notes mean en man 2. Dimension 61 does not include dambar \ | | Ler | | b mo Ay protrusionintrusion. a Seating Plane by 3. Controlling dimension: Inches 4, General appearance spec. should be based o on final visual inspection spec. Publication Release Date: October 1997 -17- Revision A3eit, @ Winbond NokER ectronios Corp, W78E51 SRR TITIES Package Dimensions, continued 44-pin QFP Seating Plane See Detail F Detail F Dimension in inch Dimension in mm Symbol [iin [Nom. | Max. | Min. [Nom. | Max A oo _ ao a oa Aa Booz | oo joo |ons | oes | o5 Ag D075 [0.081 }o.087 | 1.30 | 2.05 | 2.20 b Do jo.oi4 Joos | 025 | oa5 | 0.45 o 0.004 | 0.006 |0.010 | 0.101 | 0.152 | o254 B pg90 [0394 |os98 | 39 qo.00 | 104 E o.330 joss |osss | 99 | io00 | 101 fel b.025 [0.031 |o0s6 | 0.635 | oan | 0.952 Ho 0.510 |o.520 |ossp [1295 | 1g2 | 1845 He D510 [0.520 |os30 | 12.95 | 13.2 | 13.45 L 0.025 |o.031 |oo3s7 | oss | 08 | 095 Li 0.051 | 0.068 |o.075 | 1.295 | 1.6 | 1.905 y _ |o.003 | | 0.08 6 o | {7 of} {| Notes: 4. Dimension D & E do not include interlead flash i} Dimension b dees not include dambar protrusion/ntrusion. Controlling dimension: Millimeter General appearance spec. should be based on final visual inspection spec. Bw 44-pin TQFP Seating Plane See Detail F Detail F Dimension in ineh Dirnension in mm Symbol Min. |Norm. | Max. | Min. | Nem Max. A _ - ee | 420 A 6.002 004 | 0.008 | 0.05 O10 0.15 Az 0.037 |o.0ss joo | oss | 1.00 | 1.05 b 8.0089 ) 0.013 | 0.015 O22 O22 0.38 Cc 0.004 _ 0.008 6.080 _ o200 D oaso |0.294 |o398 | og 10.00 | 40.4 E O390 | 0.354 o308 a9 10.00 104 fe] 0.025 [o.ost | 0088 | oegs | o8o | O952 Ho O468 joa | O476 | 1190 | 12.00 | 1210 He o4e8 | O472 | o47B | 1190 | 1200 | 1210 L oot |ooed |ooso | o45 060 | O75 Li | 0.089 _ _ 100 | -- _ | ooo | | one 9 oO __ 7 . __ 7 Notes 1. Dirnension D & Edo not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion Controlling dimension: Millimeter General appearance spec. should be based on final visual inspection spec Po -18 -W78E51 Winbond h chide Electronics Corp. PRISE IETS, fetthey, or Winbond Electronics Carp. Neadguartars Winbond Blectvanigs (MLL) Lid. | Winbond Flagtranios North dmerios Corp. No. 8, Creston fet is, Rin, 883, Warkt Trade Square, Tower 8, Wirkond Bhermary Lab. Solenos-Rased Industrial Park, 23 Hot Bad Re, Mave Tong, Winbond Migroskectenios Cam. Halnohu, Tahwan Rowhaan, Hong Kang ee . FEL E- FST INS TE: BOR BSS Winhond Systems Lab. FAR: SORT GRU? FAR: GS227 550088 AIT? N. Elrad Siveal, Sar doea, httoceerwaul nbd cen tin! TH GOSS, ESA. Voice & Pagosa BERETS ARS TE: QR RSS FAR: SR GS4 1783 sipal OSfices THE Ns. 098) Ses. 3, Mindheng Gant Rel, Jaina, Tahwar VEL: S8g-2- 74 SS TAR: RR 4 RTOS Mhoto: abodogs aact qagetbhkantnag gorg tdhacd bo qo enikogt acathe, Publication Release Date: October 1997 -19- Revision A3