Order Number: 290580, Revi sion: 020
18 Aug 2005
Intel® Advanced Boot Block Flash
Memory (B3)
28F008/800B 3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet
Product Featu res
The Intel® Advance d Boot Bloc k Fla sh Memory (B 3) devic e, manufa ctured on the Int el 0.13 µm
and 0. 18 µm te ch nolo g ies, i s a fe atu re- r ic h so lut ion at a lo w sy stem co st. The B3 de vi ce in x1 6 is
available in 48-lead TSOP and 48-ba ll CSP packages. The x8 option of this product family is
avai lable only in 40-lea d TSOP and 48-ball µBGA* packages. For additional information about
th is produ ct f amily, se e the Inte l website: http://www.intel.com/design/flash.
•Flexible SmartVoltage Technology
—2.7 V – 3.6 V read/program/erase
—12 V VPP fas t production programming
•1.65 V – .5 V or 2.7 V – 3.6 V I/O option
—Reduc es overall system power
•High Performance
—2.7 V – 3.6 V: 70 ns max access time
•Optim ized Block Sizes
—Eight 8-KB blocks for data, top or
bo ttom locations
—Up to 127 x 64-KB blocks for code
•Block Locking
—VCC-level control through Write Protect
WP#
•Low Power Consumption
—9 mA ty p i cal re ad cu r r en t
•Absolute Hardware-Protection
—VPP = GND option
—VCC lockout voltage
•Extended Temperat ure Operation
—–40 °C to +85 °C
•Autom ated Program and Block Erase
—Status r egiste r s
•Intel® Flash Data Integrator Software
—Flash Memory Manager
—System Interrupt Manager
—Supports parameter storage, streaming
data (for example, voice)
•Extended Cycling Capability
—Minimum 100,000 block erase cycl es
•Automa tic Power Savings Feature
—Typical ICCS af ter bus ina ctiv ity
•St andard Surface Mount Pac kaging
—48-Ball CSP packages
—40-Lead and 48-Lead TSOP packages
•Density and Footprint Upgradeable for
common package
—8-, 16-, 32-, and 64-Mbit densities
•ETOX™ VIII (0.13 µm) Flash
Technology
—16-Mbit and 32-Mbit densities
•ETOX™ VII (0. 18 µm) Flash Technology
—16-, 32-, and 64-Mbit dens ities
•ETOX ™ VI (0.25µm) Flash Technology
—8-, 16-, and 32-Mbit densities
•Bo not use the x8 option for new designs
Notice: This specificatio n is subj ect to change wi thout notice. Ver ify with your lo cal Intel sales
office that you have the latest datasheet before finalizing a design.
18 Aug 2005 Intel® Adv anced B oot Block Flash Memo ry (B3) Datasheet
2 Order Numbe r: 290580 , Revision: 020
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHA T SOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT.
Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The Intel® Advanced Boot Block Flash Memory (B3) may contain design defects or errors known as errata which may cause the product to deviate
from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800
548-4725 or by visiting Intel's website at http://www.intel.com.
Intel, the Intel logo, and ETOX are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2005, Intel Corporation.
28F008/800B3, 28F 016/160B3, 28F3 20B3, 28F640B 3
Datasheet Intel® Advanced Boot Block Flash Memory (B3) 18 Aug 2005
Order Number: 290580, Revisio n: 020 3
Contents
1.0 Introduction ...............................................................................................................................7
1.1 Nomenclature .......................................................................................................................7
1.2 Conventions..........................................................................................................................8
2.0 Functional Overview..............................................................................................................8
3.0 Functional Overview..............................................................................................................9
3.1 Architecture Diagram..........................................................................................................10
3.2 Memory Maps and Block Organization.................... ....... ................. ......... ....... ............ .......11
3.2.1 Parameter Blocks ..................................................................................................11
3.2.2 Main Blocks ...........................................................................................................11
3.2.3 4-Mbit, 8-Mbit, 1 6-Mbit, 32-Mbit, and 64-Mbit Word-Wide Me mory Maps.............11
3.2.4 4-Mbit, 8-Mbit, and 16-Mb it Byte-Wide Memory Map s...........................................20
4.0 P ack age Info rm at ion............................................................................................................24
4.1 mBGA * and Ver y Th i n Profile Fi n e Pitch Ba ll Gri d Arr a y (V F BGA) Pac ka ge...... ..... ..... ....24
4.2 TSOP Package...................................................................................................................25
4.3 Easy BGA Package............................................................................................................26
5.0 Pinout and Signal Descriptions.......................................................................................27
5.1 Signal Pinouts.....................................................................................................................27
5.1.1 40-Lead and 48-Lead TSOP Packages.............................................. ...................27
5.2 Signal Descriptions................. ....... ............ ............ ....... ......... ............ ....... ....... ............ .......30
6.0 Maximum Ratings and Ope rating Conditi ons ...........................................................32
6.1 Absolute Maxi mu m Ratings......... ..... ......... ..... ......... ..... ......... ..... .......... .... .......... ..... ......... ..32
6.2 Ope r at i n g Condi tions..... .... ..... .......... .... ..... .......... .... .......... .... .......... ..... .... .......... ..... ......... ..33
7.0 Electrical Specifications.....................................................................................................34
7.1 DC Curr ent Char a cte ristics............ ..... ......... ..... .......... .... .......... ..... ......... ..... ......... ..... .........34
7.2 DC Volt a ge Characteristics............ ..... ..... ......... ..... ......... ..... .......... .... .......... .... .......... ..... ....36
8.0 AC Characteristics................................................................................................................37
8.1 AC Read Characteri sti c s ... .......... ..... ......... ..... ......... .......... .... .......... ..... ......... ..... ......... ..... ..37
8.2 AC Writ e Chara cte r i stic s....... ......... ..... ......... ..... .......... .... .......... ..... ......... ..... ......... ..... .........41
8.3 Er as e an d Prog ra m Ti mi n g............ ..... ......... ..... ..... ......... ..... .......... .... ..... ......... ..... .......... ....45
8.4 AC I/O Test Conditions...... ....... ..... ....... ..... ....... ..... ....... .. ..... ....... ..... ....... .. ....... ..... ....... ..... ..46
8.5 Device Capacitanc e. ............................... .............................. ............................. .................46
9.0 Power and Reset Specifications .....................................................................................47
9.1 Power -U p /Down Characteristics.... ..... ......... ..... .......... .... .......... ..... .... .......... .... .......... ..... ....47
9.1.1 RP# Connected to System Reset...................... ....... .......... ....... .. ....... .......... ....... ..47
9.1.2 VCC, V PP, and RP# Trans itions. . ................... .......................... ................... ............47
9.2 Rese t Sp e cifications. ......... ..... .......... .... ..... .......... .... .......... .... ..... .......... .... .......... ..... .... .......48
9.3 Power Su p ply De co upl ing....... .......... .... ..... .......... .... .......... .... .......... ..... ......... ..... ..... ......... ..49
28F008/ 800B3, 28F016 /16 0B3, 28F320B3, 28F6 40B3
18 Aug 2005 Intel® Adv anced B oot Block Flash Memo ry (B3) Datasheet
4 Order Numbe r: 290580 , Revision: 020
9.4 Power Consumption...........................................................................................................49
9.4.1 Active Po wer............... .... .......... ..... .... .......... ..... ......... ..... ......... ..... ......... ..... ..... ......49
9.4.2 Automatic Powe r Savi n g s (APS)....... ..... .......... .... ..... .......... .... ..... ......... ..... ..... ......49
9.4.3 Standby P ower ................. ............................... .......................... ................... .........49
9.4.4 D eep Pow er-Down Mode . ......................... .............................................................50
10.0 Operations Overview...........................................................................................................50
10.1 Bus Operations...................................................................................................................51
10.1.1 Read......................................................................................................................51
10.1.2 Output Disable.......................................................................................................52
10.1.3 Standby..................................................................................................................52
10.1.4 D eep Pow er-Down / Reset. ...................................................................................52
10.1.5 Write ......................................................................................................................53
11.0 Operating Modes...................................................................................................................53
11.1 Read Array..........................................................................................................................54
11.2 R ead Identifier ........................ ............................................. ...............................................56
11.3 R ead Status Register........................................ .................................................... ..............56
11.3.1 Clearing the Status Reg ister..................................................................................57
11.4 Program Mode....................................................................................................................57
11.4.1 Sus pe nding and Resum ing P rogram ming.............. .......................... .....................58
11.5 Erase Mode........................................................................................................................58
11.5.1 Sus pending and Resum ing Eras e.......................... .......................... .....................59
12.0 Block Lo ckin g.........................................................................................................................62
12.1 WP# = VIL for Block Locking........... ..... ......... ..... ......... ..... ......... ..... ..... ......... ..... .......... .... ....62
12.2 WP# = VIH for Block Unlocking...........................................................................................62
13.0 VPP Program and Erase Voltages...................................................................................63
13.1 VPP = VIL for Complete Pro te c tion....... .... .......... ..... ......... ..... .... .......... ..... ......... ..... ..... ........63
14.0 Additional Information ........................................................................................................63
Appendix A Write State Machine Current/Next States.................................................64
Appendix B Program and Erase Flowcharts....................................................................66
Appendix C Ordering Information.........................................................................................70
28F008/800B3, 28F 016/160B3, 28F3 20B3, 28F640B 3
Datasheet Intel® Advanced Boot Block Flash Memory (B3) 18 Aug 2005
Order Number: 290580, Revisio n: 020 5
Revision History
Revision
Number Description
-001 Original version
-002
S ec tio n 3.4, VPP Progr a m an d E ras e Vol tage s , added
Updated Figure 9: A u to m at e d Blo ck E ras e Flow c ha r t
Updated Figure 10: Erase S uspe nd/Resume Flowchart (added program to table)
Updated Figure 16: AC Waveform: Pr ogram and Erase O perations (updated notes)
IPPR maximu m speci fic ation cha nge from ±25 µA to ±50 µA
Pro gram and Erase Su spen d Latency specification cha nge
Updated Appendix A: Ordering Information (included 8 M and 4 M information)
Updated Figure, Appendix D: A rchitecture Block Di agram (Block info. in words not bytes)
Minor wo rding changes
-003
Combined byte-wide specificat ion (previously 290605 ) with this document
Improved spe ed spe c ificat ion to 80 ns (3.0 V) and 9 0 ns (2.7 V)
Improved 1.8 V I/O option to mini mum 1. 65 V (Se c tion 3.4)
Improved several DC character isti c s (Section 4.4)
Improved severa l AC characteristics (Sections 4.5 and 4.6)
Combined 2.7 V and 1.8 V DC c haracteristics (Secti on 4. 4)
Added 5 V VPP rea d specification (S ection 3.4)
Removed 120 ns and 150 ns speed offerings
Moved Ordering Information from Appendix to Section 6.0; updated information
Moved Additional Information from Appendix to Section 7.0
Updated figure Appendix B, Acces s T im e vs . C apa citi v e Load
Updated figure Appendix C, Architecture Block Diagram
Moved P rog r a m an d E ras e F lo w c ha r ts to Appendix E
Updated Progr am Flowchart
Updated Pro gram Su spen d/Resume Fl owchar t
Minor text edits thro ugho ut
-004
Added 32-Mbit de nsity
Added 98H as a re served command (Table 4)
A1–A20 = 0 when in read identif ier m ode (Section 3.2.2)
Status register clarification for SR3 (Table 7)
VCC and VCCQ absolute maximum specification = 3.7 V (Section 4.1)
Combined IPPW an d ICCW into one sp ecific at i on (Se c tio n 4.4 )
Combined IPPE and ICCE into one specification (Section 4.4)
Max Parameter B lock Er ase Time (tWHQV2/tEHQV2) reduced to 4 sec (Section 4.7)
Max Main Block Er ase Time (tWHQV3/tEHQV3) reduced to 5 sec (Section 4.7)
Erase suspend time @ 12 V (tWHRH2/tEHRH2) changed to 5 µs t ypical and 20 µs maximum
(Section 4.7)
Ordering Information updated (Section 6.0)
Write State M achin e Current /Next States Table updat ed (Appendix A)
Pro gram Suspend/Resume Flowchart updated (Appen dix F)
Era s e Suspend/Resu me Flowchar t updated (Appendix F)
Tex t clar i fic ations th ro ughout
-005
µBGA package diagrams corrected (Figures 3 and 4)
IPPD test condi tions corrected (S ecti on 4. 4)
32-Mbit ordering information corrected (Sect ion 6)
µBGA pack age top si de mark information adde d (Section 6)
-006
VIH and VILSpecification change (Section 4.4)
ICCS test cond itions cl arification (Sect ion 4.4)
Added Command S eque nce Error Note (Ta ble 7)
Data sheet renamed from Smart 3 Advanced Boot Block 4-Mbit, 8-Mbit, 16-Mbit Flash
Memory Family.
Added device ID information for 4-Mbit x8 device
Removed 32-Mbit x8 to reflect product offerings
Minor text change s
28F008/ 800B3, 28F016 /16 0B3, 28F320B3, 28F6 40B3
18 Aug 2005 Intel® Adv anced B oot Block Flash Memo ry (B3) Datasheet
6 Order Numbe r: 290580 , Revision: 020
-007 Corrected RP# pin description in Table 2, 3 Volt Advanced Boot Block Pin Descr iptions
Corrected typographical error fixed i n Ordering Information
-008 4-Mbit packaging an d addressing in formation c orrected throughout document
-009 Corrected 4-Mbit memory addressing tables in Appendices D and E
-010 Max ICCD changed to 25 µA
VCCMax on 32 M (28F320B3) changed to 3.3 V
-011 Ad de d 64 - Mb it dens it y an d fas ter spe ed off eri ngs
Removed access time vs. capacitance load cur v e
-012
Changed references of 32Mbit 80ns devices to 70ns devices to reflect the faster pro duct
offering.
Changed VccMax=3.3V reference to indicate the affected product is the 0.25µm 32Mbit
device.
Minor text edits throughout document.
-013 Added New Pin-1 in dica tor information on 40 and 48Le ad TSOP packages.
Minor text edits throughout document.
-014 Added specifications for 0.13 micron product offerings throughout document
-015 Minor text edits throughout document.
-016
Adjusted ordering information.
Adjusted specifica tions for 0.13 micron product offering s.
Revised and corrected DC Characteristics Table.
Adjusted package diagram information.
Minor text edits throughout document.
-017
Updated ordering information.
Adjusted specifica tions for 0.13 micron product offering s.
Updated AC/DC Characteristics Table.
Ad de d TS O P an d µBGA* package diagram information.
Minor text edits throughout document.
-018 Updated the layout of the datasheet.
-01 9 Ad de d line it e m s to Ta bl e 3 4 “O r de ring Information: Val id C om b in ation s ” on page 70.
-020 Removed all x8 products from ordering information, page 70
Revision
Number Description
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet Intel® Advanced Boot Block Flash Memory (B3) 18 Aug 2005
Order Number: 290580, Revisio n: 020 7
1.0 Introduction
This data s heet des cr ibes t he s pe cific at ions fo r t he Inte l
®
A dvanced B oot Block F lash Me mory (B 3)
devic e (her ea fte r refe rred to as the B3 flash memory device).
The B3 flash memory device is opt im ized for portable, low-p ower, systems. This family of
products features 1.65 V to 2.5 V or 2.7 V to 3.6 V I/Os, and a low VCC/VPP operating range of
2.7 V to 3.6 V for Read, Program, and Erase operations. The B3 device is also capable of fast
programm ing at 12 V.
Throughout this docum ent:
•2.7 V refers to the full voltage range 2.7 V to 3.6 V (except wher e noted otherwise) .
•VPP = 12 V refer s to 12 V ±5%.
1.1 Nomenclature
Table 1. Nomenclature
Term Definition
0 x He xadecim a l pref i x
0b Bi na ry pr e fix
B yt e 8 bits
Word 16 bits
KW or Kword 1024 words
Mwor d 1,048,576 words
Kb 1024 bits
KB 1024 bytes
Mb 1,048,576 bits
MB 1,048,576 bytes
APS Automatic Power Savings
CS P Chip S c al e Pac ka ge
CUI Command User Interface
OTP One Time Programmable
PR Protection Register
PRD Protection Register Data
PLR Protection Lock Register
RFU Reserved f or Future Use
SR Status Register
SRD Status Register Data
WSM Write State Machine
28F008/ 800B3, 28F016 /16 0B3, 28F320B3, 28F6 40B3
18 Aug 2005 Intel® Adv anced B oot Block Flash Memo ry (B3) Datasheet
8 Order Numbe r: 290580 , Revision: 020
1.2 Conventions
2.0 Functional Overview
The B3 flash memory device features the following:
•Enha nced blocking for easy segmentation of code and da ta or additional design flexibility.
•Program Suspend to Read command.
•VCCQ input of 1.65 V to 2.5 V or 2.7 V t o 3.6 V on all I /Os . S ee Figure 1 through Figure 4 for
pinout diagrams and VCCQ location.
•Maxim um pr ogram and erase time specification for improved data storage .
Table 2. Conventions
Convention Description
P in or signal
Used interchangeably to refer to the external signal connections on the
package.
Note: Fo r a chip sc al e pa ckage (CS P) , the te rm ball is used in place of pin.
Group Membership Br ackets Square brackets designate group membership or define a group of signals
with similar function (for example, A[21:1], SR[4:1])
Set When referring to registers, the term set means the bit is a logical 1.
Clear: When referring to registers, the term clear means the bit is a logical 0.
Block A group of bits (or words) that era s e simultaneously using one block erase
instruction.
Main Block A block that contains 32 Kword s .
Parameter Block A block that contains 4 Kwo rds.
Table 3. B3 Device Feature Summary (Sheet 1 of 2)
Featur e 28F008B3, 28F016B3 28F800B3, 28F160B3,
28F320B3(3), 28 F 6 40 B 3 Reference
VCC R ead Vol tage 2.7 V– 3.6 V Section 6.2, Section
7.2
VCCQ I/O Voltage 1.65 V–2.5 V or 2.7 V– 3. 6 V Section 4.2, 4.4
VPP Program/Erase Volt age 2.7 V– 3.6 V or 11.4 V– 12.6 V Section 4.2, 4.4
Bus Width 8 bit 16 bit Tab le 27
Speed 70 ns, 80 ns, 90 ns, 100 ns, 110 ns Section 8.1
Memory Arrangement 1024 Kbit x 8 (8 Mbit),
2048 Kbit x 8 (16 Mbit)
512 Kbit x 16 (8 Mbit),
1024 Kbit x 16 (16 Mbit),
2048 Kbit x 16 (32 Mbit),
4096 Kbit x 16 (64 Mbit)
Section 3.2
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet Intel® Advanced Boot Block Flash Memory (B3) 18 Aug 2005
Order Number: 290580, Revisio n: 020 9
3.0 Functional Overview
Intel provides the most flexible voltage solution in the flash industry, providing three discrete
voltage supply pins:
•VCC for Read operation
•VCCQ for output swing
•VPP for Program and Erase operation.
All B3 flash m emory devices provide program/eras e capability at 2.7 V or 12 V (for fast
production programming), and read with VCC at 2.7 V. Because many designs read from the flash
memory a large perce ntage of the time, 2.7 V VCC operation can provide substantial power
savings.
The B3 flash memory device family is available in either x8 or x16 package s in the fol lowing
dens ities (see Appendix C, “Ordering Info rmation,” for avail ability):
•8-Mbit (8, 388, 608-bit) flash memory organiz ed as 512 Kwords of 16 bit s each or 1024
Kbytes of 8-bits each.
•16-Mbit (16, 777, 216-bit) flash mem ory organized as 1024 Kwords of 16 bits each or
2048 Kbytes of 8-bits each.
•32-Mbit (33, 554, 432-bit) flash memory organized as 2048 Kwords of 16 bits each.
•64-Mbit (67, 108, 864-bit) flash memory organized as 4096 Kwords of 16 bits each.
The parameter blocks are located at eit her the top (denoted by -T suffix) or the bottom (-B suffix)
of the address map, to acc ommodate different micr oprocessor protocols for kernel code location.
The upper two (or lower two) parameter blocks can be locke d to provide complete co de security
for system initi alizat ion code. Locking and unlocking is controlled by Write Protect WP# (see
Section 12.0, “Block Locking” on page 62 for details ).
Blocking (top or bottom)
Eight 8-Kbyte parameter blocks and
Fifteen 64-Kbyte blocks (8 Mbit) or
Thirty- one 64-Kbyte main blocks (16 Mbit)
Sixty- three 64-Kbyte mai n bloc ks (32 Mbit)
One hundr ed twenty-seven 64-Kbyte main blocks (64 Mbit)
Se c tio n 3.2, “M e m or y
Maps and Block
Organi zation” on
page 11
Locking WP# locks/unlocks paramet er blocks
A ll ot he r bloc k s pro t e cte d us in g VPP Se c tion 12 . 0
Tabl e 32
Operating Temperature Extended: –40 °C to +85 °CSec tion 6. 2 , Section
7.2
Pr ogram/Erase Cycl ing 100,000 cycles Se c tio n 6.2, Section
7.2
Packages 40- lead TSOP(1),
48-Ball µBGA* CSP(2) 48-Lead TSOP,
48- Ba ll µBGA CSP(2),
48-Ball VF BGA Fi gure 8, Figu re 9
Notes:
1. 32-Mbit an d 64-Mbit densities not availab le in 40- lead TSOP.
2. 8-Mbi t dens iti es not available in µBGA* CSP.
3. VCCMax is 3.3 V on 0.25µm 32 -M bit devic es .
Ta ble 3. B3 Device Feature Sum mary (S heet 2 of 2)
Fe ature 28F00 8 B 3, 28F 0 16 B 3 28F800B3, 28F160B3,
28F320B3(3), 28F640B3 Reference
28F008/ 800B3, 28F016 /16 0B3, 28F320B3, 28F6 40B3
18 Aug 2005 Intel® Adv anced B oot Block Flash Memo ry (B3) Datasheet
10 Order Numbe r: 290580 , Revision: 020
•The Command User Interface (CUI) is the int er face b etween th e microprocessor or
micr ocontroller and the internal operation of the flash m emory.
•The internal Write State Machine (WSM) automatically executes the algorithms and timings
necessary for Program and Erase operations (including verification), which unburdens the
microprocessor or microcontroller.
•To indica te the status of the WSM, the Status Register sign ifies block erase or word program
com pletion and s tatus.
The B3 flash me m ory device also provides Automatic Power Savings (AP S), whic h mi nimizes
system current drain and allows for very low power designs. This mode is entered follow ing the
completion of a read cycle (approximately 300 ns later).
The RP# pin pr ovides additional protection aga inst unwante d comma nd writes that mi ght occur
during system reset and power-up/down sequences due to invalid sys tem bus conditions (see
“P ower and Reset Specifica tions” on page 47).
•Section 10.0, “Operations Overview” on page 50 explai ns the di fferent mo des of operation.
•Section 7.0, “Electri ca l Specifications” on page 34 and Section 8.0, “AC Characteri st ics” on
page 37 pr ovide complete current and volt age specifications.
•Section 8.1, “AC Read Characteristics” on page 37 provides read, program, and erase
performance specifications.
3.1 Architecture Diagram
Figure 1. B3 Architecture Block Diagram
Output
Multiplexer
4-KWord
Parameter Bloc k
32-KWord
Main Block
32-KWord
Main Block
4-KWord
Parameter Bloc k
Y-Gating/Sensing Write State
Machine Program/Erase
Voltage Switch
Data
Comparator
Status
Register
Identifier
Register
Data
Register
I/O Logic
Address
Latch
Address
Counter
X-Decoder
Y-Decoder
Power
Reduction
Control
In put Bu ffe r
Output Buffe r
GND
V
CC
V
PP
CE#
WE#
OE#
RP#
Command
User
Interface
In put Bu ffe r
A
0
-A
19
DQ
0
-DQ
15
V
CCQ
WP#
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet Intel® Advanced Boot Block Flash Memory (B3) 18 Aug 2005
Order Number: 290580, Revisio n: 020 11
3.2 Memory Maps an d Block Organizati on
The B3 flash memory devi ce uses an asymmetrically blocked architecture , enabling system
integration of code and data within a single flash memory device. Each block can be era se d
independently of othe r blocks up to 100,000 times. For the address locations of each block, see the
following memory maps:
•Table 4 “16-Mbit and 32-Mbit Word-Wide Memory Addressing Map” on page 11
•Table 5 “4-Mbi t and 8-Mbit Word-Wi de Memory Addressing Map” on page 14
•Table 6 “16-Mbit, 32-Mbi t, and 64-Mbit Word-Wide Memory Addressing Map” on page 15
•Table 7 “8-Mbi t and 16-Mbit Byte-Wide Memory Addres sing Map” on page 20
•Table 8 “4-Mbit Byte Wide Memory Addre s sing Map” on page 23
3.2.1 Parameter Blocks
The B 3 flash memory device architecture incl udes param eter bloc ks to facilitate storing frequently
updated small parameters (such as data traditionally stored in an EEPROM). The word-rewrite
functionality of EE P ROMs can be emulated using softwa re techniq ues . Each flash memory device
contains eight parame ter blocks of 8 Kbytes/4 Kwords (8192 bytes/4,096 words) each.
3.2.2 Main Blocks
After t he param eter bl ocks, t he remai nder of t he fla sh m emory arra y is d ivided into eq ual-s ize main
blocks (65,536 bytes/32,768 words ) for data or code storage.
•The 8-Mbi t flash memory devic e contains 15 main blocks.
•The 16-Mb it flash memory device contains 31 main blocks .
•The 32-Mbit memory device contains 63 mai n blocks.
•The 64-Mbit memory device contains 127 ma in blocks.
3.2. 3 4-Mbi t , 8- Mb it, 1 6-M bit, 32- Mb it , a nd 64-M bit Word- Wide Mem ory M aps
Table 4. 16-Mbit and 32-Mbit Word-Wide Memory Addressing Map (Sheet 1 of 4)
16-Mbit and 32-Mbit Word-Wide Memory Addressing
Top Boot Bo ttom Bo ot
Size
(KW) 16 Mbit 32 Mbit Size
(KW) 8 Mbit 16 Mbit 32 Mbit
4FF000-FFFFF 1FF000-1FFFFF 32 1F8000-1FFFFF
4FE000-FEFFF 1FE000-1FEFFF 32 1F0000-1F7FFF
4FD000-FDFFF 1FD000-1FDFFF 32 1E8000-
1EFFFF
4FC000-FCFFF 1FC000-1FCFFF 32 1E0000-
1E7FFF
28F008/ 800B3, 28F016 /16 0B3, 28F320B3, 28F6 40B3
18 Aug 2005 Intel® Adv anced B oot Block Flash Memo ry (B3) Datasheet
12 Order Numbe r: 290580 , Revision: 020
4FB000-FBFFF 1FB000-1FBFFF 32 1D8000-
1DFFFF
4FA000-FAFFF 1FA000-1FAFFF 32 1D0000-
1D7FFF
4F9000-F9FFF 1F9000-1F9FFF 32 1C8000-
1CFFFF
4F8000-F8FFF 1F8000-1F8FFF 32 1C0000-
1C7FFF
32 F0000-F7FFF 1F0000-1F7FFF 32 1B8000-
1BFFFF
32 E8000-EFFFF 1E8000-1EFFFF 32 1B0000-
1B7FFF
32 E0000-E7FFF 1E0000-1E7FFF 32 1A8000-
1AFFFF
32 D8000-DFFFF 1D8000-1DFFFF 32 1A0000-
1A7FFF
32 D0000-D7FFF 1D0000-1D7FFF 32 198000-19FFFF
32 C8000-CFFFF 1C8000-1CFFFF 32 190000-197FFF
32 C0000-C7FFF 1C0000-1C7FFF 32 188000-18FFFF
32 B8000-BFFFF 1B8000-1BFFFF 32 180000-187FFF
32 B0000-B7FFF 1B0000-1B7FFF 32 178000-17FFFF
32 A8000-AFFFF 1A8000-1AFFFF 32 170000-177FFF
32 A0000-A7FFF 1A0000-1A7FFF 32 168000-16FFFF
32 98000-9FFFF 198000-19FFFF 32 160000-167FFF
32 90000-97FFF 190000-197FFF 32 158000-15FFFF
32 88000-8FFFF 188000-18FFFF 32 150000-157FFF
32 80000-87FFF 180000-187FFF 32 148000-14FFFF
32 78000-7FFFF 178000-17FFFF 32 140000-147FFF
32 70000-77FFF 170000-177FFF 32 138000-13FFFF
32 68000-6FFFF 168000-16FFFF 32 130000-137FFF
32 60000-67FFF 160000-167FFF 32 128000-12FFFF
32 58000-5FFFF 158000-15FFFF 32 120000-127FFF
32 50000-57FFF 150000-157FFF 32 118000-11FFFF
32 48000-4FFFF 148000-14FFFF 32 110000-117FFF
32 40000-47FFF 140000-147FFF 32 108000-10FFFF
32 38000-3FFFF 138000-13FFFF 32 100000-107FFF
32 30000-37FFF 130000-137FFF 32 F8000-FFFFF 0F8000-0FFFFF
32 28000-2FFFF 128000-12FFFF 32 F0000-F7FFF 0F0000-0F7FFF
Table 4. 16-Mbit an d 32-Mbit Word-Wide Memor y Addressi ng Map (Sheet 2 of 4)
16-Mbit and 32-Mbit Word-Wide Memory Addressing
Top Boot Bottom Boot
Size
(KW) 1 6 Mb it 32 Mbit Size
(KW) 8 Mbit 16 Mbit 3 2 Mb it
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet Intel® Advanced Boot Block Flash Memory (B3) 18 Aug 2005
Order Number: 290580, Revisio n: 020 13
32 20000-27FFF 120000-127FFF 32 E8000-EFFFF 0E8000-
0EFFFF
32 18000-1FFFF 118000-11FFFF 32 E0000-E7FFF 0E0000-
0E7FFF
32 10000-17FFF 110000-117FFF 32 D8000-DFFFF 0D8000-
0DFFFF
32 08000-0FFFF 108000-10FFFF 32 D0000-D7FFF 0D0000-
0D7FFF
32 00000-07FFF 100000-107FFF 32 C8000-CFFFF 0C8000-
0CFFFF
This column co ntinues on next page This column continues on nex t page
32 0F8000-0FFFFF 32 C0000-C7FFF 0C0000-
0C7FFF
32 0F0000-0F7FFF 32 B8000-BFFFF 0B8000-
0BFFFF
32 0E8000-0EFFFF 32 B0000-B7FFF 0B0000-
0B7FFF
32 0E0000-0E7FFF 32 A8000-AFFFF 0A8000-
0AFFFF
32 0D8000-0DFFFF 32 A0000-A7FFF 0A0000-
0A7FFF
32 0D0000-0D7FFF 32 98000-9FFFF 098000-09FFFF
32 0C8000-0CFFFF 32 90000-97FFF 090000-097FFF
32 0C0000-0C7FFF 32 88000-8FFFF 088000-08FFFF
32 0B8000-0BFFFF 32 80000-87FFF 080000-087FFF
32 0B0000-0B7FFF 32 78000-7FFFF 78000-7FFFF
32 0A8000-0AFFFF 32 70000-77FFF 70000-77FFF
32 0A0000-0A7FFF 32 68000-6FFFF 68000-6FFFF
32 098000-09FFFF 32 60000-67FFF 60000-67FFF
32 090000-097FFF 32 58000-5FFFF 58000-5FFFF
32 088000-08FFFF 32 50000-57FFF 50000-57FFF
32 080000-087FFF 32 48000-4FFFF 48000-4FFFF
32 078000-07FFFF 32 40000-47FFF 40000-47FFF
32 070000-077FFF 32 38000-3FFFF 38000-3FFFF
32 068000-06FFFF 32 30000-37FFF 30000-37FFF
32 060000-067FFF 32 28000-2FFFF 28000-2FFFF
32 058000-05FFFF 32 20000-27FFF 20000-27FFF
32 050000-057FFF 32 18000-1FFFF 18000-1FFFF
32 048000-04FFFF 32 10000-17FFF 10000-17FFF
32 040000-047FFF 32 08000-0FFFF 08000-0FFFF
Table 4. 16-Mbit and 32-Mbit Word-Wide Memory Addressing Map (Sheet 3 of 4)
16-Mbit and 32-Mbit Word-Wide Memory Addressing
Top Boot Bo ttom Bo ot
Size
(KW) 16 Mbit 32 Mbit Size
(KW) 8 Mbit 16 Mbit 32 Mbit
28F008/ 800B3, 28F016 /16 0B3, 28F320B3, 28F6 40B3
18 Aug 2005 Intel® Adv anced B oot Block Flash Memo ry (B3) Datasheet
14 Order Numbe r: 290580 , Revision: 020
038000-03FFFF 4 07000-07FFF 07000-07FFF
030000-037FFF 4 06000-06FFF 06000-06FFF
028000-02FFFF 4 05000-05FFF 05000-05FFF
020000-027FFF 4 04000-04FFF 04000-04FFF
018000-01FFFF 4 03000-03FFF 03000-03FFF
010000-017FFF 4 02000-02FFF 02000-02FFF
008000-00FFFF 4 01000-01FFF 01000-01FFF
000000-007FFF 4 00000-00FFF 00000-00FFF
Table 5. 4-Mbit and 8-Mb it Word-Wide Memory Ad dres sing Map (Sheet 1 of 2)
4-Mbit and 8-Mbit Word-Wide Memory Addressing
Top Boot Bottom Boot
Size
(KW) 4 Mbi t Size
(KW) 4 Mbit 8 Mbit
3F000-3FFFF 7F000-7FFFF 32 78000-7FFFF
3E000-3EFFF 7E000-7EFFF 32 70000-77FFF
3D000-3DFFF 7D000-7DFFF 32 68000-6FFFF
3C000-3CFFF 7C000-7CFFF 32 60000-67FFF
3B000-3BFFF 7B000-7BFFF 32 58000-5FFFF
3A000-3AFFF 7A000-7AFFF 32 50000-57FFF
39000-39FFF 79000-79FFF 32 48000-4FFFF
38000-38FFF 78000-78FFF 32 40000-47FFF
4 30000-37FFF 70000-77FFF 32 38000-3FFFF 38000-3FFFF
4 28000-2FFFF 68000-6FFFF 32 30000-37FFF 30000-37FFF
4 20000-27FFF 60000-67FFF 32 28000-2FFFF 28000-2FFFF
4 18000-1FFFF 58000-5FFFF 32 20000-27FFF 20000-27FFF
4 10000-17FFF 50000-57FFF 32 18000-1FFFF 18000-1FFFF
4 08000-0FFFF 48000-4FFFF 32 10000-17FFF 10000-17FFF
4 00000-07FFF 40000-47FFF 32 08000-0FFFF 08000-0FFFF
438000-3FFFF 4 07000-07FFF 07000-07FFF
32 30000-37FFF 4 06000-06FFF 06000-06FFF
32 28000-2FFFF 4 05000-05FFF 05000-05FFF
32 20000-27FFF 4 04000-04FFF 04000-04FFF
32 18000-1FFFF 4 03000-03FFF 03000-03FFF
le 4 .
16-Mb it and 32-Mbit Wo rd-Wide M emory Addressing M ap (Sheet 4 of 4)
16-Mbit and 32-Mbit W ord-Wide Memory Addressing
Top Boot Bottom Boot
ize
W)
16 Mbit 32 Mbit Size
(KW) 8 Mbit 16 Mbit 32 Mbit
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet Intel® Advanced Boot Block Flash Memory (B3) 18 Aug 2005
Order Number: 290580, Revisio n: 020 15
32 10000-17FFF 4 02000-02FFF 02000-02FFF
32 08000-0FFFF 4 01000-01FFF 01000-01FFF
32 00000-07FFF 4 00000-00FFF 00000-00FFF
Ta ble 6. 16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing M ap (Sheet 1 of 6)
16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing
Top Boot Bottom Boot
Size
(KW) 16 Mbit 32 Mbit 64 Mbit Size
(KW) 16 Mbit 32 Mbit 64 Mbit
4 FF000-FFFFF 1FF000-
1FFFFF 3FF000-3FFFFF 32 3F8000-
3FFFFF
4 FE000-FEFFF 1FE000-
1FEFFF 3FE000-3FEFFF 32 3F0000-
3F7FFF
4 FD000-FDFFF 1FD000-
1FDFFF 3FD000-3FDFFF 32 3E8000-
3EFFFF
4 FC000-FCFFF 1FC000-
1FCFFF 3FC000-3FCFFF 32 3E0000-
3E7FFF
4 FB000-FBFFF 1FB000-
1FBFFF 3FB000-3FBFFF 32 3D8000-
3DFFFF
4 FA000-FAFFF 1FA000-
1FAFFF 3FA000-3FAFFF 32 3D0000-
3D7FFF
4 F9000-F9FFF 1F9000-
1F9FFF 3F9000-3F9FFF 32 3C8000-
3CFFFF
4 F8000-F8FFF 1F8000-
1F8FFF 3F8000-3F8FFF 32 3C0000-
3C7FFF
32 F0000-F7FFF 1F0000-
1F7FFF 3F0000-3F7FFF 32 3B8000-
3BFFFF
32 E8000-EFFFF 1E8000-
1EFFFF 3E8000-3EFFFF 32 3B0000-
3B7FFF
32 E0000-E7FFF 1E0000-
1E7FFF 3E0000-3E7FFF 32 3A8000-
3AFFFF
32 D8000-DFFFF 1D8000-
1DFFFF 3D8000-3DFFFF 32 3A0000-
3A7FFF
32 D0000-D7FFF 1D0000-
1D7FFF 3D0000-3D7FFF 32 398000-39FFFF
32 C8000-CFFFF 1C8000-
1CFFFF 3C8000-3CFFFF 32 390000-397FFF
32 C0000-C7FFF 1C0000-
1C7FFF 3C0000-3C7FFF 32 388000-38FFFF
32 B8000-BFFFF 1B8000-
1BFFFF 3B8000-3BFFFF 32 380000-387FFF
Table 5. 4-Mbit and 8-Mbit Word-Wide Memory Addressing Map (Sheet 2 of 2)
4-Mbit and 8-Mb it Word- Wide Memory Addressing
Top Boot Bo ttom Bo ot
Size
(KW) 4 Mbit Size
(KW) 4 Mbit 8 Mbit
28F008/ 800B3, 28F016 /16 0B3, 28F320B3, 28F6 40B3
18 Aug 2005 Intel® Adv anced B oot Block Flash Memo ry (B3) Datasheet
16 Order Numbe r: 290580 , Revision: 020
32 B0000-B7FFF 1B0000-
1B7FFF 3B0000-3B7FFF 32 378000-37FFFF
32 A8000-AFFFF 1A8000-
1AFFFF 3A8000-3AFFFF 32 370000-377FFF
32 A0000-A7FFF 1A0000-
1A7FFF 3A0000-3A7FFF 32 368000-36FFFF
32 98000-9FFFF 198000-
19FFFF 398000-39FFFF 32 360000-367FFF
32 90000-97FFF 190000-
197FFF 390000-397FFF 32 358000-35FFFF
32 88000-8FFFF 188000-
18FFFF 388000-38FFFF 32 350000-357FFF
32 80000-87FFF 180000-
187FFF 380000-387FFF 32 348000-34FFFF
32 78000-7FFFF 178000-
17FFFF 378000-37FFFF 32 340000-347FFF
32 70000-77FFF 170000-
177FFF 370000-377FFF 32 338000-33FFFF
32 68000-6FFFF 168000-
16FFFF 368000-36FFFF 32 330000-337FFF
32 60000-67FFF 160000-
167FFF 360000-367FFF 32 328000-32FFFF
32 58000-5FFFF 158000-
15FFFF 358000-35FFFF 32 320000-327FFF
32 50000-57FFF 150000-
157FFF 350000-357FFF 32 318000-31FFFF
32 48000-4FFFF 148000-
14FFFF 348000-34FFFF 32 310000-317FFF
32 40000-47FFF 140000-
147FFF 340000-347FFF 32 308000-30FFFF
32 38000-3FFFF 138000-
13FFFF 338000-33FFFF 32 300000-307FFF
32 30000-37FFF 130000-
137FFF 330000-337FFF 32 2F8000-
2FFFFF
32 28000-2FFFF 128000-
12FFFF 328000-32FFFF 32 2F0000-
2F7FFF
32 20000-27FFF 120000-
127FFF 320000-327FFF 32 2E8000-
2EFFFF
32 18000-1FFFF 118000-11FFFF 318000-31FFFF 32 2E0000-
2E7FFF
32 10000-17FFF 110000-117FFF 310000-317FFF 32 2D8000-
2DFFFF
Table 6. 16-Mbit , 32-Mbit, a nd 64-Mbit Word-Wide Memory Add ressin g Map (S heet 2 of 6)
16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing
Top Boot B otto m Bo ot
Size
(KW) 16 Mb it 32 Mbit 64 Mb it Size
(KW) 16 Mbit 32 Mbit 64 Mbit
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet Intel® Advanced Boot Block Flash Memory (B3) 18 Aug 2005
Order Number: 290580, Revisio n: 020 17
32 08000-0FFFF 108000-
10FFFF 308000-30FFFF 32 2D0000-
2D7FFF
32 00000-07FFF 100000-
107FFF 300000-307FFF 32 2C8000-
2CFFFF
32 0F8000-
0FFFFF 2F8000-2FFFFF 32 2C0000-
2C7FFF
32 0F0000-
0F7FFF 2F0000-2F7FFF 32 2B8000-
2BFFFF
32 0E8000-
0EFFFF 2E8000-2EFFFF 32 2B0000-
2B7FFF
32 0E0000-
0E7FFF 2E0000-2E7FFF 32 2A8000-
2AFFFF
32 0D8000-
0DFFFF 2D8000-2DFFFF 32 2A0000-
2A7FFF
32 0D0000-
0D7FFF 2D0000-2D7FFF 32 298000-29FFFF
32 0C8000-
0CFFFF 2C8000-2CFFFF 32 290000-297FFF
32 0C0000-
0C7FFF 2C0000-2C7FFF 32 288000-28FFFF
32 0B8000-
0BFFFF 2B8000-2BFFFF 32 280000-287FFF
32 0B0000-
0B7FFF 2B0000-2B7FFF 32 278000-27FFFF
32 0A8000-
0AFFFF 2A8000-2AFFFF 32 270000-277FFF
32 0A0000-
0A7FFF 2A0000-2A7FFF 32 268000-26FFFF
32 098000-
09FFFF 298000-29FFFF 32 260000-267FFF
32 090000-
097FFF 290000-297FFF 32 258000-25FFFF
32 088000-
08FFFF 288000-28FFFF 32 250000-257FFF
32 080000-
087FFF 280000-287FFF 32 248000-24FFFF
32 078000-
07FFFF 278000-27FFFF 32 240000-247FFF
32 070000-
077FFF 270000-277FFF 32 238000-23FFFF
32 068000-
06FFFF 268000-26FFFF 32 230000-237FFF
Ta ble 6. 16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing M ap (Sheet 3 of 6)
16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing
Top Boot Bottom Boot
Size
(KW) 16 Mbit 32 Mbit 64 Mbit Size
(KW) 16 Mbit 32 Mbit 64 Mbit
28F008/ 800B3, 28F016 /16 0B3, 28F320B3, 28F6 40B3
18 Aug 2005 Intel® Adv anced B oot Block Flash Memo ry (B3) Datasheet
18 Order Numbe r: 290580 , Revision: 020
32 060000-
067FFF 260000-267FFF 32 228000-22FFFF
32 058000-
05FFFF 258000-25FFFF 32 220000-227FFF
32 050000-
057FFF 250000-257FFF 32 218000-21FFFF
32 048000-
04FFFF 248000-24FFFF 32 210000-217FFF
32 040000-
047FFF 240000-247FFF 32 208000-20FFFF
32 038000-
03FFFF 238000-23FFFF 32 200000-207FFF
32 030000-
037FFF 230000-237FFF 32 1F8000-
1FFFFF 1F8000-
1FFFFF
32 028000-
02FFFF 228000-22FFFF 32 1F0000-
1F7FFF 1F0000-
1F7FFF
32 020000-
027FFF 220000-227FFF 32 1E8000-
1EFFFF 1E8000-
1EFFFF
32 018000-
01FFFF 218000-21FFFF 32 1E0000-
1E7FFF 1E0000-
1E7FFF
32 010000-
017FFF 210000-217FFF 32 1D8000-
1DFFFF 1D8000-
1DFFFF
32 008000-
00FFFF 208000-21FFFF 32 1D0000-
1D7FFF 1D0000-
1D7FFF
32 000000-
007FFF 200000-207FFF 32 1C8000-
1CFFFF 1C8000-
1CFFFF
32 1F8000-1FFFFF 32 1C0000-
1C7FFF 1C0000-
1C7FFF
32 1F0000-1F7FFF 32 1B8000-
1BFFFF 1B8000-
1BFFFF
32 1E8000-1EFFFF 32 1B0000-
1B7FFF 1B0000-
1B7FFF
32 1E0000-1E7FFF 32 1A8000-
1AFFFF 1A8000-
1AFFFF
32 1D8000-1DFFFF 32 1A0000-
1A7FFF 1A0000-
1A7FFF
32 1D0000-1D7FFF 32 198000-19FFFF 198000-19FFFF
32 1C8000-1CFFFF 32 190000-197FFF 190000-197FFF
32 1C0000-1C7FFF 32 188000-18FFFF 188000-18FFFF
32 1B8000-1BFFFF 32 180000-187FFF 180000-187FFF
32 1B0000-1B7FFF 32 178000-17FFFF 178000-17FFFF
32 1A8000-1AFFFF 32 170000-177FFF 170000-177FFF
Table 6. 16-Mbit , 32-Mbit, a nd 64-Mbit Word-Wide Memory Add ressin g Map (S heet 4 of 6)
16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing
Top Boot B otto m Bo ot
Size
(KW) 16 Mb it 32 Mbit 64 Mb it Size
(KW) 16 Mbit 32 Mbit 64 Mbit
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet Intel® Advanced Boot Block Flash Memory (B3) 18 Aug 2005
Order Number: 290580, Revisio n: 020 19
32 1A0000-1A7FFF 32 168000-16FFFF 168000-16FFFF
32 198000-19FFFF 32 160000-167FFF 160000-167FFF
32 190000-197FFF 32 158000-15FFFF 158000-15FFFF
32 188000-18FFFF 32 150000-157FFF 150000-157FFF
32 180000-187FFF 32 148000-14FFFF 148000-14FFFF
32 178000-17FFFF 32 140000-147FFF 140000-147FFF
32 170000-177FFF 32 138000-13FFFF 138000-13FFFF
32 168000-16FFFF 32 130000-137FFF 130000-137FFF
32 160000-167FFF 32 128000-12FFFF 128000-12FFFF
32 158000-15FFFF 32 120000-127FFF 120000-127FFF
32 150000-157FFF 32 118000-11FFFF 118000-11FFFF
32 148000-14FFFF 32 110000-117FFF 110000-117FFF
32 140000-147FFF 32 108000-10FFFF 108000-10FFFF
32 138000-13FFFF 32 100000-107FFF 100000-107FFF
32 130000-137FFF 32 F8000-FFFFF F8000-FFFFF F8000-FFFFF
32 128000-12FFFF 32 F0000-F7FFF F0000-F7FFF F0000-F7FFF
32 120000-127FFF 32 E8000-EFFFF E8000-EFFFF E8000-EFFFF
32 118000-11FFFF 32 E0000-E7FFF E0000-E7FFF E0000-E7FFF
32 110000-117FFF 32 D8000-DFFFF D8000-DFFFF D8000-DFFFF
32 108000-10FFFF 32 D0000-D7FFF D0000-D7FFF D0000-D7FFF
32 100000-107FFF 32 C8000-CFFFF C8000-CFFFF C8000-CFFFF
32 0F8000-0FFFFF 32 C0000-C7FFF C0000-C7FFF C0000-C7FFF
32 0F0000-0F7FFF 32 B8000-BFFFF B8000-BFFFF B8000-BFFFF
32 0E8000-0EFFFF 32 B0000-B7FFF B0000-B7FFF B0000-B7FFF
32 0E0000-0E7FFF 32 A8000-AFFFF A8000-AFFFF A8000-AFFFF
32 0D8000-0DFFFF 32 A0000-A7FFF A0000-A7FFF A0000-A7FFF
32 0D0000-0D7FFF 32 98000-9FFFF 98000-9FFFF 98000-9FFFF
32 0C8000-0CFFFF 32 90000-97FFF 90000-97FFF 90000-97FFF
32 0C0000-0C7FFF 32 88000-8FFFF 88000-8FFFF 88000-8FFFF
32 0B8000-0BFFFF 32 80000-87FFF 80000-87FFF 80000-87FFF
32 0B0000-0B7FFF 32 78000-7FFFF 78000-7FFFF 78000-7FFFF
32 0A8000-0AFFFF 32 70000-77FFF 70000-77FFF 70000-77FFF
32 0A0000-0A7FFF 32 68000-6FFFF 68000-6FFFF 68000-6FFFF
32 098000-09FFFF 32 60000-67FFF 60000-67FFF 60000-67FFF
32 090000-097FFF 32 58000-5FFFF 58000-5FFFF 58000-5FFFF
Ta ble 6. 16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing M ap (Sheet 5 of 6)
16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing
Top Boot Bottom Boot
Size
(KW) 16 Mbit 32 Mbit 64 Mbit Size
(KW) 16 Mbit 32 Mbit 64 Mbit
28F008/ 800B3, 28F016 /16 0B3, 28F320B3, 28F6 40B3
18 Aug 2005 Intel® Adv anced B oot Block Flash Memo ry (B3) Datasheet
20 Order Numbe r: 290580 , Revision: 020
3.2.4 4-Mbit, 8-Mbit, and 16-Mbit Byte-Wide Memory Maps
32 088000-08FFFF 32 50000-57FFF 50000-57FFF 50000-57FFF
32 080000-087FFF 32 48000-4FFFF 48000-4FFFF 48000-4FFFF
32 078000-07FFFF 32 40000-47FFF 40000-47FFF 40000-47FFF
32 070000-077FFF 32 38000-3FFFF 38000-3FFFF 38000-3FFFF
32 068000-06FFFF 32 30000-37FFF 30000-37FFF 30000-37FFF
32 060000-067FFF 32 28000-2FFFF 28000-2FFFF 28000-2FFFF
32 058000-05FFFF 32 20000-27FFF 20000-27FFF 20000-27FFF
32 050000-057FFF 32 18000-1FFFF 18000-1FFFF 18000-1FFFF
32 048000-04FFFF 32 10000-17FFF 10000-17FFF 10000-17FFF
32 040000-047FFF 32 08000-0FFFF 08000-0FFFF 08000-0FFFF
32 038000-03FFFF 4 07000-07FFF 07000-07FFF 07000-07FFF
32 030000-037FFF 4 06000-06FFF 06000-06FFF 06000-06FFF
32 028000-02FFFF 4 05000-05FFF 05000-05FFF 05000-05FFF
32 020000-027FFF 4 04000-04FFF 04000-04FFF 04000-04FFF
32 018000-01FFFF 4 03000-03FFF 03000-03FFF 03000-03FFF
32 010000-017FFF 4 02000-02FFF 02000-02FFF 02000-02FFF
32 008000-00FFFF 4 01000-01FFF 01000-01FFF 01000-01FFF
32 000000-007FFF 4 00000-00FFF 00000-00FFF 00000-00FFF
Table 7. 8-Mbit and 16-Mbit Byte-Wide Memory Addressi ng Map (Sheet 1 of 3 )
8-Mbit and 16-Mbit Byte-Wide Byte-Wide Memory Addressing
Top Boot Bottom Boot
Size (KB) 8 Mbit 16 Mbit Size (KB) 8 Mbit 16 Mbit
8 FE000-FFFFF 1FE000-1FFFFF 64
8 FC000-FDFFF 1FC000-1FDFFF 64
8 FA000-FBFFF 1FA000-1FBFFF 64
8 F8000-F9FFF 1F8000-1F9FFF 64
8 F6000-F7FFF 1F6000-1F7FFF 64
8 F4000-F5FFF 1F4000-1F5FFF 64
8 F2000-F3FFF 1F2000-1F3FFF 64
8 F0000-F1FFF 1F0000-1F1FFF 64
Table 6. 16-Mbit , 32-Mbit, a nd 64-Mbit Word-Wide Memory Add ressin g Map (S heet 6 of 6)
16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing
Top Boot B otto m Bo ot
Size
(KW) 16 Mb it 32 Mbit 64 Mb it Size
(KW) 16 Mbit 32 Mbit 64 Mbit
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet Intel® Advanced Boot Block Flash Memory (B3) 18 Aug 2005
Order Number: 290580, Revisio n: 020 21
64 E0000-EFFFF 1E0000-1EFFFF 64
64 D0000-DFFFF 1D0000-1DFFFF 64
64 C0000-CFFFF 1C0000-1CFFFF 64
64 B0000-BFFFF 1B0000-1BFFFF 64
64 A0000-AFFFF 1A0000-1AFFFF 64
64 90000-9FFFF 190000-19FFFF 64
64 80000-8FFFF 180000-18FFFF 64
64 70000-7FFFF 170000-17FFFF 64
64 60000-6FFFF 160000-16FFFF 64
64 50000-5FFFF 150000-15FFFF 64
64 40000-4FFFF 140000-14FFFF 64
64 30000-3FFFF 130000-13FFFF 64
64 20000-2FFFF 120000-12FFFF 64
64 10000-1FFFF 110000-11FFFF 64
64 00000-0FFFF 100000-10FFFF 64
64 0F0000-0FFFFF 64
64 0E0000-0EFFFF 64
64 0D0000-0DFFFF 64
64 0C0000-0CFFFF 64
64 0B0000-0BFFFF 64
64 0A0000-0AFFFF 64
64 090000-09FFFF 64
64 080000-08FFFF 64
64 070000-07FFFF 64
64 060000-06FFFF 64 1F0000-1FFFFF
64 050000-05FFFF 64 1E0000-1EFFFF
64 040000-04FFFF 64 1D0000-1DFFFF
64 030000-03FFFF 64 1C0000-1CFFFF
64 020000-02FFFF 64 1B0000-1BFFFF
64 010000-01FFFF 64 1A0000-1AFFFF
64 000000-00FFFF 64 190000-19FFFF
64 64 180000-18FFFF
64 64 170000-17FFFF
64 64 160000-16FFFF
64 64 150000-15FFFF
Table 7. 8-Mbit and 16-Mbit Byte-Wide Memory Addressing Map (Sheet 2 of 3)
8-Mbit and 16-Mbit Byte-Wide Byte-Wide Memory Addressing
Top Boot Bottom Boot
Size (KB) 8 Mbit 16 Mbit Size (KB) 8 Mbit 16 Mbit
28F008/ 800B3, 28F016 /16 0B3, 28F320B3, 28F6 40B3
18 Aug 2005 Intel® Adv anced B oot Block Flash Memo ry (B3) Datasheet
22 Order Numbe r: 290580 , Revision: 020
64 64 140000-14FFFF
64 64 130000-13FFFF
64 64 120000-12FFFF
64 64 110000-11FFFF
64 64 100000-10FFFF
64 64 F0000-FFFFF 0F0000-0FFFFF
64 64 E0000-EFFFF 0E0000-0EFFFF
64 64 D0000-DFFFF 0D0000-0DFFFF
64 64 C0000-CFFFF 0C0000-0CFFFF
64 64 B0000-BFFFF 0B0000-0BFFFF
64 64 A0000-AFFFF 0A0000-0AFFFF
64 64 90000-9FFFF 090000-09FFFF
64 64 80000-8FFFF 080000-08FFFF
64 64 70000-7FFFF 070000-07FFFF
64 64 60000-6FFFF 060000-06FFFF
64 64 50000-5FFFF 050000-05FFFF
64 64 40000-4FFFF 040000-04FFFF
64 64 30000-3FFFF 030000-03FFFF
64 64 20000-2FFFF 020000-02FFFF
64 64 10000-1FFFF 010000-01FFFF
64 8 0E000-0FFFF 00E000-00FFFF
64 8 0C000-0DFFF 00C000-00DFFF
64 8 0A000-0BFFF 00A000-00BFFF
64 8 08000-09FFF 008000-009FFF
64 8 06000-07FFF 006000-007FFF
64 8 04000-05FFF 004000-005FFF
64 8 02000-03FFF 002000-003FFF
64 8 00000-01FFF 000000-001FFF
Table 7. 8-Mbit and 16-Mbit Byte-Wide Memory Addressi ng Map (Sheet 3 of 3 )
8-Mbit and 16-Mbit Byte-Wide Byte-Wide Memory Addressing
Top Boot Bottom Boot
Size (KB) 8 Mbit 16 Mbit Size (KB) 8 Mbit 16 Mbit
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet Intel® Advanced Boot Block Flash Memory (B3) 18 Aug 2005
Order Number: 290580, Revisio n: 020 23
Ta ble 8. 4-Mbit Byte Wid e Mem ory Addressing Map
4-Mbit Byte-Wide Memory Addressing
Top Boot Bottom Boot
Size
(KB) 4 Mbit Size
(KB) 4 Mbit
8 7E000-7FFFF 64 70000-7FFFF
8 7C000-7DFFF 64 60000-6FFFF
8 7A000-7BFFF 64 50000-5FFFF
8 78000-79FFF 64 40000-4FFFF
8 76000-77FFF 64 30000-3FFFF
8 74000-75FFF 64 20000-2FFFF
8 72000-73FFF 64 10000-1FFFF
8 70000-71FFF 8 0E000-0FFFF
64 60000-6FFFF 8 0C000-0DFFF
64 50000-5FFFF 8 0A000-0BFFF
64 40000-4FFFF 8 08000-09FFF
64 30000-3FFFF 8 06000-07FFF
64 20000-2FFFF 8 04000-05FFF
64 10000-1FFFF 8 02000-03FFF
64 00000-0FFFF 8 00000-01FFF
28F008/ 800B3, 28F016 /16 0B3, 28F320B3, 28F6 40B3
18 Aug 2005 Intel® Adv anced B oot Block Flash Memo ry (B3) Datasheet
24 Order Numbe r: 290580 , Revision: 020
4.0 Package Information
4.1 µBGA* and Very Thin Profile Fine Pitch Ball Grid Array
(VF BGA) Package
Figu re 2. µBGA* and VF BGA Package Drawing
Bottom View -Bump side up
e
b
S1
Ball A1
Corner
Top View - Bump Side down
Ball A1
Corner
E
D
Side Vi ew
A
A2
A
1
Seating
Y
A
B
C
D
E
F
S2
Plan
123
4
5678
A
B
C
D
E
F
123
4
5678
Note: Drawing not to scale
Millimeters Inches
Dimensions Symbol Min Nom Max Min Nom Max
Package Height A 1.000 0.0394
Ball Height A1 0.150 0.0059
Package Body Thickness A2 0.665 0.0262
Ball (Lead) Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167
Package Body Length 8M (.25) D 7.810 7.910 8.010
Package Body Length 16M (.25 /.18 /.13) 32M (.25/.18/.13) D 7.186 7.286 7.38 6 0.2829 0.2868 0.2908
Package Body Length 64M (.18) D 7.600 7.700 7.800 0.2992 0.3031 0.3071
Package Body Width 8 M (.25) E 6.400 6.500 6.600 0.2520 0.2559 0.2598
Package Body Width 16M (.25/.18/.13) 32M (.18/.13) E 6.864 6.964 7.06 4 0.2702 0.2742 0.2781
Package Body Width 32 M (.25) E 10 .75 0 10.850 10.860 0 .4232 0.4272 0.4276
Package Body Width 64 M (.18) E 8.900 9.000 9.10 0 0.3504 0.3543 0.3583
Pitch e 0.750 0.0295
Ball (Lea d) Count 8M, 16M N 46 46
Ball (Lea d) Count 32M N 4 7 47
Ball (Lea d) Count 64M N 4 8 48
S ea t i ng Pl an e C oplana r ity Y 0. 1 00 0 . 00 3 9
Corner to Ball A1 D i stance Along D 8M (.25) S1 1.230 1.330 1.43 0 0.0484 0.0524 0.0563
Corner to Ball A1 D i stance Along D 16M (.25/.18/.13) 32M (.18/.13) S1 0.918 1.018 1.11 8 0.0361 0.0401 0.0440
Corner to Ball A1 D i stance Along D 64M (.18) S1 1.125 1.225 1.32 5 0.0443 0.0482 0.0522
Corner to Ball A1 Distance Along E 8M (.25) S2 1.275 1.375 1.47 5 0.0502 0.0541 0.0581
Corner to Ball A1 D i stance Along E 16M (.25 /.18/.13) 32M (.18/.13)
S2 1.507 1.607 1.707 0.0593 0.0633 0.0672
Corner to Ball A1 D istance Along E 32M (.25) S2 3.450 3.550 3 .65 0 0.1358 0.1398 0.1437
Corner to Ball A1 D istance Along E 64M (.18) S2 2.525 2.625 2.72 5 0.0994 0.1 033 0.1073
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet Intel® Advanced Boot Block Flash Memory (B3) 18 Aug 2005
Order Number: 290580, Revisio n: 020 25
4.2 TSOP Pack age
Notes:
1. One dimple on package denotes Pin 1.
2. If two dimples, then the larger dimple denotes Pin 1.
3. Pin 1 is in th e uppe r left corner of the packag e, in reference to the product mark.
Figure 3. TSO P Package Drawi ng
Dimensions
A5568-02
A
0
L
Det ail A
Y
D
C
Z
Pin 1
E
D
1
b
Detail B
S ee D eta il A
e
See Detail B
A
1
A
2
Seating
Plane
See Not es 1, 2, 3 and 4
Family: Thin Small Out-Li ne Package
Symbol Millimeters Inches
Min Nom Max Notes Min Nom Max Notes
Package Height A 1.200 0.047
Standoff A1 0.050 0.002
Package Body Thic knes s A2 0.950 1.000 1.050 0.037 0.039 0.041
Lead Width b 0.150 0.200 0.300 0.006 0.008 0.012
Lead T hic kness c 0. 100 0. 150 0.200 0. 004 0.006 0. 008
Plast ic Body Lengt h D1 18.200 18. 400 18. 600 0.717 0.724 0.732
Package Body Width E 11. 800 12. 000 12. 200 0.465 0.472 0.480
Lead Pitc h e 0.500 0. 0197
Term inal Dimension D 19.800 20.000 20.200 0. 780 0.787 0.795
Lead T ip Length L 0.500 0.600 0. 700 0.020 0. 024 0. 028
Lead Count N 48 48
Lead Tip Angle Ø 0° 3° 5° 0° 3° 5°
Seating Plane Coplanarit y Y 0. 100 0.004
Lead to Pack age Off s et Z 0.150 0.250 0.350 0.006 0.010 0.014
28F008/ 800B3, 28F016 /16 0B3, 28F320B3, 28F6 40B3
18 Aug 2005 Intel® Adv anced B oot Block Flash Memo ry (B3) Datasheet
26 Order Numbe r: 290580 , Revision: 020
4.3 Easy BGA Package
Figure 4. Ea sy BGA Package Drawing
Millimeters Inches
Symbol Min Nom Max
Notes
Min Nom Max
Package Height A 1.200 0.0472
Ball Height A10.250 0.0098
Package Body Thickness A20.780 0.0307
Ball (Lead) Width b 0.330 0.430 0.530 0.0130 0.0169 0.0209
Package Body Width D 9.900 10.000 10.100 1 0.3898 0.3937 0.3976
Package Body Length E 12.900 13.000 13.100 1 0.5079 0.5118 0.5157
Pitch [e] 1.000 0.0394
Ball (Lead) C ount N 64 64
Seating Plane Coplanarity Y 0.100 0.0039
Corner to Ball A1 D istance Al ong D S11.400 1.500 1.600 1 0.0551 0.0591 0.0630
Corner to Ball A1 D istance Al ong E S22.900 3.000 3.100 1 0.1142 0.1181 0.1220
Dimensions Table
Note: (1) Package dimensions are for reference only. These dimensions are estimates based
on die size, and are subject to change.
E
Seating
Plane
S1
S2
e
Top View - Ball side down Bo ttom V i e w - Ba ll Si d e Up
Y
A
A1
D
Ball A1
Corner
A2
Note: Drawing not to scale
A
B
C
D
E
F
G
H
8765432187654321
A
B
C
D
E
F
G
H
b
Ball A1
Corner
Side View
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet Intel® Advanced Boot Block Flash Memory (B3) 18 Aug 2005
Order Number: 290580, Revisio n: 020 27
5.0 Pinout an d Signal D escrip tions
This se ction expla ins the package pinout and signal descriptions .
5.1 Signal Pinouts
The B3 flash m emory device is available in the following packages:
•40- lea d TSOP (x8, Figure 5).
•48- lea d TSOP (x16, Figure 6).
•48-ball µBGA (x8 in Figure 8 and x16 in Figu re 9).
•48- ball VF BGA (x16, F igure 9).
5.1.1 40-Lead and 48-Lead TSOP Packages
Notes:
1. 40-Lead TSOP available for 8-Mbit and 16-Mbit densities only.
2. Lower densities have NC on the upper address pins. For example, an 8-Mbit device has NC on Pin 38.
Figure 5. 40-L ead TSOP Packag e for x8 Configurati ons
A
17
GND
A
20
A
19
A
10
DQ
7
DQ
6
DQ
5
DQ
4
V
CCQ
V
CC
NC
DQ
3
DQ
2
DQ
1
DQ
0
OE#
GND
CE#
A
0
A
16
A
15
A
14
A
13
A
12
A
11
A
9
A
8
WE#
RP#
V
PP
WP#
A
18
A
7
A
6
A
5
A
4
A
3
A
2
A
1
16 M
8 M
Adv an ced Bo ot Block
40-L ead T SOP
10 mm x 20 mm
TOP VI EW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
4 M
28F008/ 800B3, 28F016 /16 0B3, 28F320B3, 28F6 40B3
18 Aug 2005 Intel® Adv anced B oot Block Flash Memo ry (B3) Datasheet
28 Order Numbe r: 290580 , Revision: 020
Note: The topside marking on 8-Mb, 16-Mb, and 32-Mb Intel
®
Advance d Boot Block 40L and 48L
TSOP products changed to a white ink triangle as a Pin-1 indicator. Products without the white
tria ngl e conti nue to use a dimpl e as a Pin-1 indica tor. No other change s were made in packa ge size,
ma terials , func tionality, customer handling, or manufacturability. The produ ct continues to meet
stringent Intel quality requirements. Table 9 lists the ordering code s of the affect ed products. See
also Table 34 “Ordering Information: Valid Combinations” on page 70.
Figure 6. 48-Lea d TSOP Package for x16 Configurations
Figure 7. New Mark for Pin-1 Ind icator: 40-Lead 8 /16 Mb TSOP and 48-Lead 8/ 16/32 Mb TSOP
Advanced Boot Block
48-Lead TSOP
12 mm x 20 mm
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A
16
V
CCQ
GND
DQ
15
DQ
7
DQ
14
DQ
6
DQ
13
DQ
5
DQ
12
DQ
4
V
CC
DQ
11
DQ
3
DQ
10
DQ
2
DQ
9
DQ
1
DQ
8
DQ
0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
21
A
20
WE#
RP#
V
PP
WP#
A
19
A
18
A
17
A
7
A
6
A
5
21
22
23
24
OE#
GND
CE#
A
0
28
27
26
25
A
4
A
3
A
2
A
1
32 M
16 M
64 M
ew Mark:
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet Intel® Advanced Boot Block Flash Memory (B3) 18 Aug 2005
Order Number: 290580, Revisio n: 020 29
Notes:
1. A19 and A2 0 indicate the upgrad e address connec tions. Lower dens ity devices do not have th e uppe r
addr es s sol d er ba l l s. D o no t route i s not don e i n this are a . A20 is the upgrade address for the 16-Mbit
device.
Table 9. B3 Flash Memory Device Ordering Information
Ordering Information Valid Combinations
40-Le ad TSOP 48-L ea d TSO P
Ext. Temp. 64
Mbit TE28F640B3TC70 TE28F640B3BC70
Ext. Temp. 32
Mbit
TE28F320B3TD70 TE28F320B3BD70
TE28F320B3TC70 TE28F320B3BC70
TE28F320B3TC90 TE28F320B3BC90
TE28F320B3TA100 TE28F320B3BA100
TE28F320B3TA110 TE28F320B3BA110
Ext. Temp. 16
Mbit
TE28F160B3TC70 TE28F160B3BC70
TE28F160B3TC80 TE28F160B3BC80
TE28F016B3TA90 TE28F016B3BA90 TE28F160B3TA90 TE28F160B3BA90
TE28F016B3TA110 TE28F016B3BA110 TE28F160B3TA110 TE28F160B3BA110
Ext. Temp. 8
Mbit TE28F008B3TA90 TE28F008B3BA90 TE28F800B3TA90 TE28F800B3BA90
TE28F008B3TA110 TE28F008B3BA110 TE28F800B3TA110 TE28F800B3BA110
Figure 8. x8 48-Bal l µBGA* Chip Size Package (To p View, Ball Do wn )
A14
A15
A16
A17
VCCQ
A12
A10
A13
NC
A11
A8
WE#
A9
D5
D6
VPP
RP#
NC
WP#
A19
D2
D3
A20
A18
A6
NC
NC
A7
A5
A3
CE#
D0
A4
A2
A1
A0
GND
GND D7 NC D4 VCC NC D1 OE#
A
B
C
D
E
F
13254768
16M
8M
NC
28F008/ 800B3, 28F016 /16 0B3, 28F320B3, 28F6 40B3
18 Aug 2005 Intel® Adv anced B oot Block Flash Memo ry (B3) Datasheet
30 Order Numbe r: 290580 , Revision: 020
Notes:
1. A19, A20, and A21 indicate the upgrade address connections. Lower density devices do not have the
upper address solder balls. Do not route in this area.
– A19 is the upgrade address for the 16- M bit devic e.
– A20 is the upgrade address for th e 32-Mbit device.
– A21 is the upgrade address for th e 64-Mbit device.
2. Table 10 “B3 Flash memory Device Signal Descriptions” on page 31 de tails the usage of each dev ice
pin.
5.2 Signal Descri ptions
Table 10 describes the act ive signals.
Figure 9. x16 48-Bal l VF BGA and µBGA* Chip S ize Package (Top View, Ball Down)
A
B
C
D
E
F
13254768
A13
A14
A15
A16
VCCQ
A11
A10
A12
D14
D15
A8
WE#
A9
D5
D6
VPP
RP#
A21
D11
D12
WP#
A18
A20
D2
D3
A19
A17
A6
D8
D9
A7
A5
A3
CE#
D0
A4
A2
A1
A0
Vss
Vss D7 D13 D4 VCC D10 D1 OE#
16M
32M64M
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet Intel® Advanced Boot Block Flash Memory (B3) 18 Aug 2005
Order Number: 290580, Revisio n: 020 31
Ta ble 10. B3 Flash memory Devi ce Signal Desc riptio ns (Sheet 1 of 2)
Symbol Type Description
A0–A21 Input
ADDRESS INPUTS fo r memo r y addr esse s. Addre sse s are in terna ll y lat ched duri ng a pro gra m or
er as e cycle.
28F008B3: A[0- 19], 28F0 16B3: A[0- 20],
28F800B3: A[0- 18], 28F1 60B3: A[0- 19],
28F320B3: A[0- 20], 28F6 40B3: A[0- 21]
DQ0–DQ7Input/
Output
DATA INPUTS/OUTPUTS: Inputs array data on the second CE # and WE# cycle during a
Prog ra m command .
• In puts comma nds to the Command User Interface when C E# and WE # are active. Data is
internally latched.
• Out pu ts ar ra y , i dent ifi er an d S tatus Re gist er d at a. T he dat a pin s fl oat to tri st ate whe n th e c hip
is deselected or t he outputs are disabled.
DQ8–DQ15 Input/
Output
DATA INPUTS/OUTPUTS:
• Inputs array data on the second CE# and WE# cycle during a Program command. Data is
internally latched.
• Outputs array and identifier data. The data pins float to tristate when the chip is de-selected.
Not inc lud ed on x8 produc ts.
CE# Input CHIP ENABLE: Activates the internal control logic, input buffers, decoders, and sense amplifiers.
CE # is active low. CE# high de- s elects the m emo ry dev ice and reduces power c onsumpti on to
st an dby l e vel s .
OE# Input OUTPUT ENABLE: En ables the fla s h memory device output s th ro ugh the data buffer s during a
Read operation. OE# is active low.
WE# Input WRITE ENABLE: Controls wr ites to the Comman d Register and memory array. WE# is active
low. Add r esses and data are la tched on the risi ng edg e of the second WE# pulse.
RP# Input
RESET/DEEP POWER-DOWN: Uses two voltage levels (VIL, VIH) to contro l reset/deep po wer-
down mo de.
•When R P# is a t logic low, the flash memory d evi ce is i n reset/deep po wer-down mode,
which dr ives the output s to Hi gh-Z, r esets the Write State Machine, and minimizes curr ent
levels (ICCD).
•When RP# is at logic high, the flash memory device is in standard operation. When
RP# transitions from logic-low to logic-high, the fla sh me mory device defaults to the read
array mode.
WP# Input
WR ITE PROTECT: Locks and unlocks the two lockable parameter blocks.
•When WP# is at logic low , the lockable blocks are locked, preventing Program and Erase
operations to th ose bl ocks. If a Program or Erase o peration i s attempted on a locked block ,
SR.1 and either SR.4 [program] or SR.5 [erase] are set to indicate the operation failed.
•When WP# is at logic high, the lockable blocks are unlocked and ca n be progr am me d or
erased.
See Se ction 12.0, “Block Lo cking” on page 62 for details on write pro tecti on.
VCCQ Input
OUTPUT VCC: Enables all outputs to be driven to 1.8 V to 2.5 V while the VCC is at 2.7 V to 3. 3 V.
If the VCC is regulated to 2.7 V to 2.85 V , VCCQ can be driven at 1.65 V to 2.5 V to achieve lowest
power opera tion ( s ee Sect io n 7. 2 , “DC Vo ltage Ch ar a cter istics” on page 36).
This input can be tied directly to VCC (2.7 V to 3.6 V).
VCC Power DE VICE Power Supply: 2.7 V to 3.6 V
28F008/ 800B3, 28F016 /16 0B3, 28F320B3, 28F6 40B3
18 Aug 2005 Intel® Adv anced B oot Block Flash Memo ry (B3) Datasheet
32 Order Numbe r: 290580 , Revision: 020
6. 0 Maximum Rat ings and Ope r a t ing Condi tions
6.1 Absolute Maximum Ratings
Warning: Stressing the flash memory devic e beyond the Absolute Maximum Ra tings in Table 11 can ca use
permanent damage. Th es e ra tings are stre ss ratings only.
VPP Power
PROGRAM/ERASE Power Supply: S up plie s po wer for Pr ogr am a nd Er ase op er ati on s. VPP can
be the same as VCC (2.7 V to 3.6 V) for si ngle suppl y vol tage operatio n. For fast programming at
manufacturing, 1 1.4 V to 12.6 V can be supplied to VPP. This pin cannot be left floating. 11.4 V to
12.6 V can be applied to VPP only for a maximum of 1000 cycles on the main blocks and 2500
c ycles on the parameter blocks. VPP can be connected to 12 V for a total of 80 hour s m axim um
(see Sectio n 13.0, “VPP Pro gr a m an d E r as e Vol tag es” on page 63 for details).
VPP < VPPLK protect s memory contents aga inst inadver tent or uninte nded pr ogram and erase
commands.
GND — Ground: For all internal circuitry . All ground inputs must be connected.
NC — No Connect: Pin c a n be dri ven or le ft fl oa t in g.
NOTICE: Specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest
datasheet before finalizing a design.
Table 11. Abso lute Maximum Rati ngs
Parameter Maximum Rating Notes
Extended Operating Temperature
During Read –40 °C to +85 °C
Durin g Bl ock Erase and Pr ogram –40 °C to +85 °C
Temperat ure under Bias –40 °C to +85 °C
Storage Temperature –65 °C to +125 °C
Voltage On Any Pin (except VCC and VPP) with Respect to GND –0.5 V to +3.7 V 1
VPP Voltage (for Block Er ase an d Program) with Respect to GND –0.5 V to +13.5 V 1,2 ,3
VCC and VCCQ Sup pl y Voltage with Respect to GND –0.2 V t o +3.6 V
Output Short C ircuit Cu rrent 100 m A 4
Notes:
1. Minimum DC voltage is –0.5 V on input/output pins. During transitions, this level might
undershoot to –2.0 V for periods <20 ns. Maximum DC voltage on input/output pins is
VCC +0.5 V w hich, durin g tran sitions, might overshoot to VCC +2.0 V for periods <20 ns.
2. Maximum DC voltage on VPP might over shoo t to +14.0 V for peri ods <2 0 ns.
3. VPP Program voltage is typically 1.65 V to 3.6 V . Connection to a 11.4 V to 12.6 V supply
can be do ne for a m aximu m of 1000 cyc les on the ma in block s and 25 00 cycles on the
parameter blocks during program/erase. VPP can be conne cted to 12 V for a total of 80
hou rs maximum.
4. Ou tput shorted for no m ore t han on e seco nd. No more than on e output shor ted at a time.
Table 10. B3 Flash mem ory Device Signal Descriptions (Sheet 2 of 2)
Symbol Type Description
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet Intel® Advanced Boot Block Flash Memory (B3) 18 Aug 2005
Order Number: 290580, Revisio n: 020 33
6.2 Operating Conditions
Do not operate the flash memory device beyond the Operating Conditions in Ta ble 12. Exte nded
expos ure beyond the Operat ing Condit ions can affect device re liability.
Table 12. Temperature and Volt ag e Operating Conditions
Symbol Parameter Min Max Units Notes
TAO perating Temperature –40 +85 °C
VCC1 VCC Sup ply Volt ag e 2 . 7 3 .6 Vol ts 1, 2
VCC2 3.0 3.6 1, 2
VCCQ1
I/O Supply Voltage
2.7 3.6
Volts
1
VCCQ2 1.65 2.5
VCCQ3 1.8 2.5
VPP1 Supply Voltage 1.65 3.6 Volts 1
VPP2 11.4 12.6 Volts 1, 3
Cycling Block Era se Cycli ng 100,000 Cycl es 3
Notes:
1. VCC an d VCCQ must share the same supply when they are in the VCC1 range.
2. VCCMax = 3.3 V fo r 0.25µm 32 - M bit de v i c es .
3. VPP = 11.4 V–12.6 V can be applied during a program/erase only for a maximum of
1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP can be
conne cted to 12 V for a total of 80 hours maxi mum.
28F008/ 800B3, 28F016 /16 0B3, 28F320B3, 28F6 40B3
18 Aug 2005 Intel® Adv anced B oot Block Flash Memo ry (B3) Datasheet
34 Order Numbe r: 290580 , Revision: 020
7.0 Electrical Specifications
7.1 DC Current Characteristics
Table 13. DC Current Characteristics (Sheet 1 of 2)
Sym Parameter
VCC 2.7 V–3.6 V 2.7 V–2.85 V 2.7 V–3.3 V
Unit Test ConditionsVCCQ 2.7 V–3.6 V 1.65 V–2.5 V 1.8 V –2.5 V
Note Typ Max Typ Max Typ Max
ILI In p ut Lo ad Cu rr en t 1,2 ± 1 ± 1 ± 1µA
VCC = VCCMax
VCCQ = VCCQMax
VIN = VCCQ or GND
ILO Ou t pu t Le ak age C urr ent 1,2 ± 10 ± 10 ± 10 µA VCC = VCCMax
VCCQ = VCCQMax
VIN = VCCQ or GND
ICCS
VCC Standby C urren t fo r
0.13 and 0.18 M icron
Product 1 7 15 20 50 150 250 µA VCC = VCCMax
CE# = RP# = VCCQ
or during Program/ Erase
Suspend
WP# = VCCQ or GND
VCC Standby C urren t fo r
0.25 Micron Produ ct 1 10 25 20 50 150 250 µA
ICCD
VCC Power-Down Current
for 0.13 and 0.18 Micron
Product 1,2 7 15 7 20 7 20 µA VCC = VCCMax
VCCQ = VCCQMax
VIN = VCCQ or GND
R P# = GND ± 0 .2 V
VCC Power-Down Current
for 0.25 Pr odu ct 1,2 7 25 7 25 7 25 µA
ICCR
VCC Read Current for
0.13 and 0.18 M icron
Product 1,2,3 9 18 8 15 9 15 mA VCC = VCCMax
VCCQ = VCCQMax
OE# = VIH, CE# =VIL
f = 5 MHz, IOUT=0 mA
Inputs = VIL or VIH
VCC Read Current for
0.25 Micron Produ ct 1,2,3 10 18 8 15 9 15 mA
IPPD VPP Deep Power-Down
Current 1 0.2 5 0.2 5 0.2 5 µA RP # = GND ± 0.2 V
VPP ≤ VCC
ICCW VCC Progra m Current 1 ,4 18 55 18 55 18 55 mA VPP =VPP1,
Program in Progress
82210301030mA
VPP = VPP2 (12v)
Program in Progress
ICCE VCC Erase Current 1,4 16 45 21 45 21 45 mA VPP = V PP1,
Era se in Pr ogress
81516451645mA
VPP = VPP2 (12v) ,
Era se in Pr ogress
ICCES/
ICCWS
VCC Erase Su spen d
Cu r rent for 0.13 and 0.18
Micron Product 1,4,5
7 15 50 200 50 200 µA CE# = VIH, Erase
Suspend in Progr ess
VCC Erase Su spen d
Cu r rent for 0.25 Mic r on
Product 10 25 50 200 50 200 µA
IPPR VPP Read Current 1,4 2±15 2 ±15 2 ±15 µA VPP ≤ VCC
50 200 50 200 50 200 µA VPP > VCC
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet Intel® Advanced Boot Block Flash Memory (B3) 18 Aug 2005
Order Number: 290580, Revisio n: 020 35
IPPW VPP Progr am Cur r e nt 1,4 0.05 0.1 0.05 0.1 0.05 0.1 mA VPP =VPP1,
Program in Progress
822822822mA
VPP = VPP2 (12v)
Program in Progress
IPPE VPP Eras e Current 1,4 0.05 0.1 0.05 0.1 0.05 0.1 mA VPP = VPP1,
Er ase in Pr ogress
82216451645mA
VPP = VPP2 (12v) ,
Er ase in Pr ogress
IPPES/
IPPWS VCC Eras e Su sp en d
Current 1,4
0.250.250.25µA
VPP = VPP1,
Pr ogram or Er ase
Su spend in Progr ess
50 200 50 200 50 200 µA VPP = VPP2 (12v) ,
Pr ogram or Er ase
Su spend in Progr ess
Notes:
1. Al l currents ar e in RMS unl ess otherw ise noted. Typical valu es at nomin al VCC, TA=+25 °C.
2. The test conditions VCCMa x, VCCQMax, V CCMin, and VCCQMin refer to the maximu m or minimum V CC or VCCQ voltage
listed at the top of each column. VCCMax = 3.3 V for 0.25µm 32- Mbit devic es.
3. Automatic Power Savings (APS) reduces ICCR to approximately standby levels in static operation (CMOS inputs).
4. Sam p l e d, no t 100% t es ted.
5. ICCES or I CCWS is specif ied with the flash memory device d eselected.
– If the device is read while in erase suspend, the current draw is the sum of ICCES an d ICCR.
– If the device is read while in program suspend, the current draw is the sum of ICCWS and ICCR.
Ta ble 13. DC Current Characteri stics (Sheet 2 of 2)
Sym Parameter
VCC 2.7 V–3.6 V 2.7 V–2.85 V 2 .7 V–3.3 V
Unit Test ConditionsVCCQ 2.7 V–3.6 V 1.65 V–2.5 V 1.8 V–2.5 V
Note Typ Max Typ Max Typ Max
28F008/ 800B3, 28F016 /16 0B3, 28F320B3, 28F6 40B3
18 Aug 2005 Intel® Adv anced B oot Block Flash Memo ry (B3) Datasheet
36 Order Numbe r: 290580 , Revision: 020
7.2 DC Voltage Characteristics
Table 14. DC Voltage Characteristics
Symbol Parameter
VCC 2.7 V–3.6 V 2.7 V–2.85 V 2.7 V–3.3 V
Un it Te st Cond it io nsVCCQ 2.7 V–3.6 V 1.65 V–2.5 V 1.8 V–2.5 V
Note Min Max Min Max Min Max
VIL Inpu t Low
Voltage –0.4 VCC *
0.22 V –0.4 0.4 –0.4 0.4 V
VIH Inpu t H igh
Voltage 2.0 VCCQ
+0.3V VCCQ –
0.4V VCCQ
+0.3V VCCQ –
0.4V VCCQ
+0.3V V
VOL Output Low
Voltage –0.1 0.1 -0.1 0.1 -0.1 0.1 V VCC = VCCMin
VCCQ = VCCQMin
IOL = 100 µA
VOH Output High
Voltage VCCQ
–0.1V VCCQ –
0.1V VCCQ –
0.1V V
VCC = VCCMin
VCCQ = VCCQMin
IOH = –100 µA
VPPLK VPP Lo ck -
Out Voltage 11.0 1.0 1.0V
Complete Write
Protection
VPP1 VPP During
Progra m /
Erase
Operations
1 1.65 3.6 1.65 3.6 1.65 3.6 V
VPP2 1,2 11.4 12.6 11.4 12.6 11.4 12.6 V
VLKO
VCC Prog/
Erase
Lock
Voltage 1.5 1.5 1.5 V
VLKO2
VCCQ Prog/
Erase
Lock
Voltage 1.2 1.2 1.2 V
Notes:
1. Er ase and Progr am ar e inhibited when VPP < VPPLK and no t guar ant ee d outs id e the val i d V PP ranges of VPP1 and VPP2.
2. VPP = 11.4 V–12.6 V can be applied during pr ogram/er ase only fo r a maximum of 1000 cycles on the m ain block s and
2500 cycles on the parameter blocks. VPP can be connec ted to 12 V for a total of 80 ho ur s m axim um.
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet Intel® Advanced Boot Block Flash Memory (B3) 18 Aug 2005
Order Number: 290580, Revisio n: 020 37
8.0 AC Characteristics
8.1 AC Read Characteristics
Table 15. Read Operations—8-Mbit Density
#SymParameter
Density 8 Mbit
Unit
Product 90 ns 1 10 ns
VCC 3.0 V – 3.6 V 2.7 V – 3.6 V 3.0 V – 3.6 V 2.7 V – 3.6 V
Note Min Max Min Max Min Max Min Max
R1 tAVAV Read Cycle Time 3,4 80 90 100 110 ns
R2 tAVQV Add ress to O utput D elay 3,4 80 90 100 110 ns
R3 tELQV CE# to Output Delay 1,3,4 80 90 10 0 110 ns
R4 tGLQV OE# to Ou tput D elay 1,3 ,4 30 30 30 30 ns
R5 tPHQV RP# to Output Delay 3,4 150 150 150 150 ns
R6 tELQX CE# to Output in Low Z 2,3,4 0 0 0 0 ns
R7 tGLQX OE# to Output in Low Z 2,3,4 0 0 0 0 ns
R8 tEHQZ C E# to Output in Hi gh Z 2,3, 4 20 20 20 20 ns
R9 tGHQZ O E# to Output in H igh Z 2,3, 4 20 20 20 20 ns
R10 tOH
Output Hold from
Address, CE#, or OE#
Change, Whichever
Occurs First 2,3,4 0 0 0 0 ns
Notes:
1. OE# can be delayed up to tELQV–tGLQV after the falling edge of CE# without impact on tELQV.
2. Sampled, but not 100% tested.
3. See Fi gure 10 “R ead Opera tion Wavefor m ” on page 40.
4. See Figure 12 “AC Input/Output Reference Waveform” on page 46 for timing measurements and maximum allowable
inp ut slew rate .
28F008/ 800B3, 28F016 /16 0B3, 28F320B3, 28F6 40B3
18 Aug 2005 Intel® Adv anced B oot Block Flash Memo ry (B3) Datasheet
38 Order Numbe r: 290580 , Revision: 020
Table 16. Read Operation s—1 6-M bit Density
#Sym
Param
eter
Density 16 Mbit
Unit Notes
Pr oduct 7 0 ns 80 ns 90 ns 110 ns
VCC 2.7 V–3.6
V2.7 V–3.6
V3. 0 V– 3.6
V2.7 V–3.6
V3.0 V–
3.6V 2.7 V–3.6V
Min Max Min Max Min Max Min Max Min Max Min Max
R1 tAVAV R ea d C yc le Time 70 80 80 90 100 11 0 ns 3,4
R2 tAVQV Addr ess to Outp ut
Delay 70 80 80 90 100 110 ns 3,4
R3 tELQV CE# t o Output
Delay 70 80 80 90 100 110 ns 1,3,4
R4 tGLQV OE# to Output
Delay 20 20 30 30 30 30 ns 1,3,4
R5 tPHQV RP# to Ou tput
Delay 150 150 150 150 150 150 ns 3,4
R6 tELQX CE# t o Output in
Low Z 0 0 0 0 0 0 ns 2,3,4
R7 tGLQX OE# to Output in
Low Z 0 0 0 0 0 0 ns 2,3,4
R8 tEHQZ C E# to Output in
High Z 20 20 20 20 20 20 ns 2,3,4
R9 tGHQZ OE# to Output in
High Z 20 20 20 20 20 20 ns 2,3,4
R10 tOH
Output Hold from
Ad dr e ss , C E#, or
OE # Change,
Whichever Occurs
First
0 0 0 0 0 0 ns 2,3,4
Notes:
1. OE# can be delayed up to tELQV–tGLQV af ter th e falli ng ed ge of CE # with out impa c t on tELQV.
2. Sampled, but not 100% tested.
3. See Figure 10 “Read Operation Waveform” on page 40.
4. See Figure 12 “AC Input/Output Reference W a veform” on page 46 for timing measurements and maximum allowable
input slew rate.
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet Intel® Advanced Boot Block Flash Memory (B3) 18 Aug 2005
Order Number: 290580, Revisio n: 020 39
Table 17. Read Operations—32-Mbit Density
#Sym
Param
eter
Density 32 Mbit
Unit Notes
Product 70 ns 90 ns 100 ns 110 ns
VCC 2.7 V–3.6
V2.7 V–3.6
V3.0 V –3 .3
V2.7 V–3.3
V3.0 V–3.3
V2.7 V–3.3
V
Min Max Min Max Min Max Min Max Min Max Min Max
R1 tAVAV Read Cycle Time 70 90 90 100 100 110 ns 3,4
R2 tAVQV Address to Output
Delay 70 90 90 100 100 110 ns 3,4
R3 tELQV CE# to Outpu t
Delay 70 90 90 100 100 110 ns 1,3,4
R4 tGLQV OE# to Output
Delay 20 20 30 30 30 30 ns 1,3,4
R5 tPHQV RP# to Output
Delay 150 150 150 150 150 150 ns 3,4
R6 tELQX CE# to Outpu t in
Low Z 0 0 0 0 0 0 ns 2,3,4
R7 tGLQX OE# to Output in
Low Z 0 0 0 0 0 0 ns 2,3,4
R8 tEHQZ CE# to Outp u t in
High Z 20 20 20 20 20 20 ns 2,3,4
R9 tGHQZ OE# to Output in
High Z 20 20 20 20 20 20 ns 2,3,4
R10 tOH
Output Hold from
Address, CE#, or
OE# Change,
Whichever
Occurs First
0 0 0 0 0 0 ns 2,3,4
Notes:
1. OE# can be delayed up to tELQV–tGLQV after the falling edge of CE# without impact on tELQV.
2. Sampled, but not 100% tested.
3. See Fi gure 10 “R ead Opera tion Wavefor m ” on page 40.
4. See Figure 12 “AC Input/Output Reference Waveform” on page 46 for timing measurements and maximum
allowable input slew rate.
28F008/ 800B3, 28F016 /16 0B3, 28F320B3, 28F6 40B3
18 Aug 2005 Intel® Adv anced B oot Block Flash Memo ry (B3) Datasheet
40 Order Numbe r: 290580 , Revision: 020
Table 18. Read Operation s — 64-M bit Density
#Sym Parameter
Density 64 Mbit
Unit
Product 70 ns 80 ns
VCC 2.7 V–3.6 V 2.7 V–3.6 V
Note Min Max Min Max
R1 tAVAV Read Cycle Time 3,4 70 80 ns
R2 tAVQV Address to O utput Dela y 3,4 70 80 ns
R3 tELQV CE# to Output Delay 1,3,4 70 80 ns
R4 tGLQV OE# to Ou tput D elay 1,3,4 20 20 ns
R5 tPHQV RP# to Output Delay 3,4 150 150 ns
R6 tELQX CE# to Output in Low Z 2,3,4 0 0 n s
R7 tGLQX OE# to Output in Low Z 2,3,4 0 0 ns
R8 tEHQZ C E# to Output in Hi gh Z 2,3,4 20 20 ns
R9 tGHQZ OE# to Output in High Z 2,3,4 20 20 ns
R10 tOH Output H old fr om Address, CE #, or OE#
Change, Whichever Occurs First 2,3,4 0 0 ns
Notes:
1. OE# can be delay ed up to t ELQV–tGLQV after the falling edge of CE# without impact on tELQV.
2. Sampled, but not 100% tested.
3. See Fig ure 10 “ Read O peration Wa vefor m ” on page 40.
4. See Fig ure 12 “ AC In put/O utput Reference Wavefor m ” on p age 46 for timing measurements and
maximum allowable input slew rate.
Figure 10. Read Op erati on Wave form
R5
R10
R7
R6
R9R4
R8R3
R1
R2 R1
A
ddress [A]
CE# [E]
OE# [G]
WE# [W]
Data [D/Q]
RST # [P]
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet Intel® Advanced Boot Block Flash Memory (B3) 18 Aug 2005
Order Number: 290580, Revisio n: 020 41
8.2 AC Write Characteristics
Table 19. Write Operations—8-Mbit Density
#Sym Parameter
Den sity 8 Mbit
Unit
Product 90 ns 110 ns
VCC
3.0 V – 3.6 V 80 100
2.7 V – 3.6 V 90 110
Note Min Min Min Min
W1 tPHWL /
tPHEL RP# High Recovery to WE# (CE#) Going Low 4,5 150 150 150 150 ns
W2 tELWL /
tWLEL CE# (WE#) Setup to WE# (CE#) Going Low 4,5 0 0 0 0 ns
W3 tWLWH /
tELEH WE # ( CE # ) Pulse Width 4,5 50 60 70 70 ns
W4 tDVWH /
tDVEH Data Setup to WE# (CE#) Going High 2,4,5 50 50 60 60 ns
W5 tAVWH /
tAVEH Address Se tup to WE # (CE#) Go ing High 2,4,5 50 60 70 70 ns
W6 tWHEH /
tEHWH CE# (WE#) Hold Ti me from WE# (CE#) High 4,5 0 0 0 0 ns
W7 tWHDX /
tEHDX Data Hold Time from WE# (CE#) High 2,4,5 0 0 0 0 ns
W8 tWHAX /
tEHAX Address Hold Time from WE# (CE#) High 2,4,5 0 0 0 0 ns
W9 tWH WL /
tEHEL WE# ( C E# ) Pul s e Width H igh 2,4, 5 30 30 30 3 0 ns
W10 tVPWH /
tVPEH VPP Setup to WE# (CE#) Going High 3,4,5 200 200 200 200 ns
W11 tQVVL VPP Hold from Valid SRD 3,4 0 0 0 0 ns
W12 tBHWH /
tBHEH WP # Setup to WE # (CE #) Go ing Hi gh 3,4 0 0 0 0 ns
W13 tQVBL WP# Hold from Va li d SRD 3,4 0 0 0 0 ns
W14 tWHGL WE# Hi g h to OE# Go ing Low 3,4 3 0 30 30 30 ns
Notes:
1. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high
(whichev er go es high fi r s t) . S o tWP =t
WLWH =t
ELEH =t
WLEH =t
ELWH.
Similarly, write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE # or W E#
going low (whicheve r goes low last ) . So tWPH =t
WHWL=t
EHEL =t
WHEL =t
EHWL.
2. Refer to Table 27 “B us Oper ations(1)” on page 51 for valid AIN or DIN.
3. Sampled, but not 100% tested.
4. See Figure 12 “AC Input/Output Reference Waveform” on page 46 f or t im ing me as ur em en t s an d ma x i m um allow a ble
inp ut slew rate.
5. See Figure 1 1 “Write Operations Waveform” on page 45.
28F008/ 800B3, 28F016 /16 0B3, 28F320B3, 28F6 40B3
18 Aug 2005 Intel® Adv anced B oot Block Flash Memo ry (B3) Datasheet
42 Order Numbe r: 290580 , Revision: 020
Table 20. Write Operations— 16-Mbit Density
#SymParameter
Den sity 1 6 Mb it
Unit
Prod uc t 70 ns 80 n s 90 ns 110 ns
VCC
3.0 V – 3.6 V 80 100
2.7 V – 3.6 V 70 80 90 110
Note Min Min Min Min Min Min
W1 tPHWL /
tPHEL RP# High Recovery to WE# (CE#) Going
Low 4,5 150 150 150 150 150 150 ns
W2 tELWL /
tWLEL CE# (WE#) Setup to WE# (CE#) Going Low 4,5 0 0 0 0 0 0 ns
W3 tWLWH /
tELEH WE# (CE#) Pulse Width 1,4,5 45 50 50 60 70 70 ns
W4 tDVWH /
tDVEH Data Setup to WE# (CE#) Going High 2,4,5 40 40 50 50 60 60 ns
W5 tAVWH /
tAVEH Addres s Setup to WE# (CE#) Going Hi gh 2,4,5 50 50 50 60 70 70 ns
W6 tWHEH /
tEHWH CE# (WE#) Hold T ime from WE# (CE#)
High 4,5 0 0 0 0 0 0 ns
W7 tWHDX /
tEHDX Data Hold T ime from WE# (CE#) High 2,4,5 0 0 0 0 0 0 ns
W8 tWHAX /
tEHAX Address Hold Time from WE# (CE#) High 2,4,5 0 0 0 0 0 0 ns
W9 tWHWL /
tEHEL WE# (CE#) Pu lse Width High 1,4,5 25 30 30 30 30 30 ns
W10 tVPWH /
tVPEH VPP Set up to WE# (C E#) Going High 3,4,5 200 2 00 2 00 200 200 200 ns
W11 tQVVL VPP Hold from Vali d SRD 3 ,4 0 0 0 0 0 0 ns
W12 tBHWH /
tBHEH WP# Setup to WE# (CE#) Going High 3,4 0 0 0 0 0 0 ns
W13 tQVBL WP# Hold from Va lid SRD 3,4 0 0 0 0 0 0 ns
W14 tWHGL WE# High t o OE# Going Low 3,4 30 30 30 30 30 30 ns
Notes:
1. Writ e puls e widt h (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high
(w hichever goes high first). So tWP =t
WLWH =t
ELEH =t
WLEH =t
ELWH.
Similarly , write pulse width high (tWPH) is de fined f rom CE# or WE# going high (whichever goes h igh first) to C E# or
WE# going low (whichever goes low last). So tWPH =t
WHWL =t
EHEL =t
WHEL=t
EHWL.
2. Refer to Table 27 “ Bus Op erations(1)” on pa ge 51 for valid AIN or DIN.
3. Sampled, but not 10 0% tested.
4. See Figure 12 “AC Input/Output Reference Wa veform” on page 46 for t iming m easurements and m axim um allowable
input slew rate.
5. See Figure 11 “Write Operations Waveform” on page 45.
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet Intel® Advanced Boot Block Flash Memory (B3) 18 Aug 2005
Order Number: 290580, Revisio n: 020 43
Ta ble 21. Write Operati on s—32-Mb it Density
#Sym Parameter
Density 32 Mbit
Unit
Product 70 ns 90 ns 100 ns 110 ns
VCC
3.0 V – 3.6 V690 100
2.7 V – 3.6 V 70 90 100 110
Note Min Min Min Min Min Min
W1 tPHWL /
tPHEL RP# High Recovery to WE# (CE#)
Going Low 4,5 150 150 150 150 150 150 ns
W2 tELWL /
tWLEL CE# (WE#) Setup to WE# (CE#)
Going Low 4,5000000ns
W3 tWLWH
/
tELEH WE# (CE#) Pulse Width 1,4,5 45 60 60 70 70 70 ns
W4 tDVWH /
tDVEH Data Setu p to WE# (CE#) G oin g High 2,4,5 40 40 50 60 60 60 ns
W5 tAVWH /
tAVEH Address Setup to WE# (CE#) Going
High 2,4,5506060707070ns
W6 tWHEH /
tEHWH CE# (WE#) Hold Time from WE#
(CE#) High 4,5000000ns
W7 tWHDX /
tEHDX Data Hold Time from WE# (CE#)
High 2,4,5000000ns
W8 tWHAX /
tEHAX Address Hold Time from WE# (CE#)
High 2,4,5000000ns
W9 tWHWL /
tEHEL WE# (CE#) Pulse Width High 1,4,5 25 30 30 30 30 30 ns
W10 tVPWH /
tVPEH VPP Setup to WE# (CE#) Going High 3,4,5 200 200 200 200 200 200 ns
W11 tQVVL VPP Hold from Valid SRD 3,4 0 0 0 0 0 0 ns
W12 tBHWH /
tBHEH WP# Setup to WE# (CE#) Going
High 3,4000000ns
W13 tQVBL WP# Hold from V alid SRD 3,4 0 0 0 0 0 0 ns
W14 tWHGL WE# High to OE# Going Low 3,4 30 30 30 30 30 30 ns
Notes:
1. Writ e pu lse w idth (t WP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high
(whichev er go es high f ir s t) . S o tWP =t
WLWH =t
ELEH =t
WLEH =t
ELWH.
Similarly, write pulse width high (tWPH) is def in ed fro m C E# or WE# go ing h ig h (whi ch ev er go es h igh f irs t) to CE # or W E #
going low (whicheve r goes low last). So tWPH =t
WHWL =t
EHEL =t
WHEL =t
EHWL.
2. Refer to Table 27 “Bus Op erati ons(1)” on page 51 for valid AIN or DIN.
3. Sampled, but not 100% tested.
4. See Fig ure 12 “ AC In put/O utput Reference Wavefor m ” on p age 46 f or ti m in g me asur em e nt s and ma x im um al l ow a ble
input slew rate.
5. See Figure 11 “Write Operations Waveform” on page 45.
6. VCCMa x = 3.3 V f or 32- M bit 0. 25 Micron product.
28F008/ 800B3, 28F016 /16 0B3, 28F320B3, 28F6 40B3
18 Aug 2005 Intel® Adv anced B oot Block Flash Memo ry (B3) Datasheet
44 Order Numbe r: 290580 , Revision: 020
Table 22. Write Operations— 64-M bit Densit y
# Symbol Parameter
Density 64 Mbit
UnitProduct 80 ns
VCC 2.7 V – 3.6 V Note Min
W1 tPHWL / tPHEL RP# High Recovery to WE# (CE#) Going Low 4,5 150 ns
W2 tELWL / tWLEL CE# (WE#) Setup to WE# (CE#) Going Low 4, 5 0 ns
W3 tWLWH / tELEH WE# (CE#) Pulse Width 1,4,5 60 ns
W4 tDVWH / t DVEH Da ta Setup t o WE# (C E#) Going High 2 ,4,5 40 ns
W5 tAVWH / t AVEH Address Setup to WE# (CE#) Going High 2,4,5 60 ns
W6 tWHEH / tEHWH CE# (WE#) Hold Time from WE# (CE#) High 4,5 0 ns
W7 tWHDX / t EHDX Data Hold Time from WE# (CE#) High 2,4,5 0 ns
W8 tWHAX / t EHAX Address Hold Time from WE# (CE#) High 2,4,5 0 ns
W9 tWHWL / tEHEL WE# (CE#) Pu lse W idth H igh 1,4, 5 30 n s
W10 tVPWH / tVPEH VPP Setup to WE# (CE#) Going High 3,4,5 200 ns
W11 tQVVL VPP H old from Valid SRD 3,4 0 ns
W12 tBHWH / tBHEH WP# Setup to WE# (CE#) Going High 3,4 0 ns
W13 tQVBL WP# Hold from V a lid SRD 3,4 0 ns
W14 tWHGL WE # High t o OE# Going Low 3,4 30 ns
Notes:
1. Write pulse width (tWP) is define d from C E# or WE# going low (whi chever goes low la st) to CE# or WE# going high
(whichever goes high first). So tWP =t
WLWH =t
ELEH =t
WLEH =t
ELWH.
Similarly, write pulse width hi gh (tWPH) is defined from CE# or WE# going high (whichever goes high first) t o C E# or
WE# going low (whi chev er goes l ow last) . So tWPH =t
WHWL =t
EHEL =t
WHEL =t
EHWL.
2. Refer to Table 27 “Bus Op erat i ons(1)” on page 51 for vali d AIN or DIN.
3. Sam p l ed , bu t not 10 0% test ed .
4. See Figure 12 “AC Input/Output Reference Waveform” on page 46 for timing me asurements and maximum allowable
input slew rate.
5. See Figure 11 “Write Operations Waveform” on page 45.
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet Intel® Advanced Boot Block Flash Memory (B3) 18 Aug 2005
Order Number: 290580, Revisio n: 020 45
8.3 Erase and Progr am Timing
Ta ble 23. Erase an d Progr am Timing
Figure 11. Write Operation s Wave form
Symbol Parameter VPP 1.65 V–3.6 V 11.4 V–12.6 V Unit
Note Typ Max Typ Max
tBWPB 4-KW Param et er Block
Word Program Time 1, 2, 3 0.10 0.30 0.03 0.12 s
tBWMB 32-KW Main Block
Word Program Time 1, 2, 3 0.8 2.4 0.24 1 s
tWHQV1 / tEHQV1
Wo rd Pr ogram T ime fo r 0.13
and 0.18 Micron Product 1, 2, 3 12 200 8 185 µs
Wo rd Pr ogram T ime fo r 0.25
Micron Product 1, 2, 3 22 200 8 185 µs
tWHQV2 / tEHQV2 4 -KW Par amet er Blo ck
Erase Time 1, 2, 3 0.5 4 0.4 4 s
tWHQV3 / tEHQV3 32-KW Ma in Block
Erase Time 1, 2, 3 1 5 0.6 5 s
tWHRH1 / tEHRH1 Program Suspend Latency 1,3 5 10 5 10 µs
tWHRH2 / tEHRH2 Erase Suspend Latency 1,3 5 20 5 20 µs
Notes:
1. Typical values measured at TA= +25 °C and nominal voltages.
2. Excludes external syst em-level overhead.
3. Sam p l e d, bu t not 10 0% test ed .
W10
W1
W7W4
W9W9
W3W3
W2
W6
W8W5
A
ddress [A]
CE# [E]
WE# [W]
OE# [G]
Da ta [D/Q ]
RP# [P]
Vpp [V]
28F008/ 800B3, 28F016 /16 0B3, 28F320B3, 28F6 40B3
18 Aug 2005 Intel® Adv anced B oot Block Flash Memo ry (B3) Datasheet
46 Order Numbe r: 290580 , Revision: 020
8.4 AC I/O Test Conditions
Note: Input t iming begi ns, and output timing end s, at VCCQ/2. Input rise and fall times (10% to 90%) < 5 ns.
Worst-case speed conditions are when VCC = VCCMin.
Note: See Table 24 fo r com ponent v alues.
8.5 Device Capacitance
TA = 25 °C , f = 1 MHz
Figure 12. AC Input/Ou tput Reference Waveform
V
CCQ
0V
V
CCQ
/2 V
CCQ
/2
Test Points
Input Outpu
t
Figure 13. Transient Equivalent Testing Load Circuit
Device
Under Test
V
CCQ
C
L
R
2
R
1
Out
Table 24. Test Con figuration Componen t Values for Worst Case Speed Condi tions
Test Configuration CL (pF) R1 (kΩ)R
2 (kΩ)
VCCQMin Standard Test 50 25 25
Note: CL in cludes jig capacitance.
Table 25. Devi ce Capacitance
Symbol Parameter§Typ Max Unit Condition
CIN Input Capacitance 6 8 pF VIN = 0.0 V
COUT O utput Capacitance 8 12 pF VOUT = 0.0 V
§Sampled, not 100% tested.
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet Intel® Advanced Boot Block Flash Memory (B3) 18 Aug 2005
Order Number: 290580, Revisio n: 020 47
9.0 Power and Reset Specifications
9.1 Power-Up/Down Characteristics
To prevent an y condition that might res ult in a spuriou s writ e or erase operation, power-up VCC
and VCCQ together. Conve rsely, VCC and VCCQ must power-down toget her.
Also powe r-up VPP with or slightly after VCC. Conversely, VPP must power-down with or slightly
before VCC.
If VCCQ and/or VPP are not connected to the VCC supply, then VCC must attain VCCMin before
applying VCCQ and VPP. Device inputs must not be driven before s upply voltage = VCCMin.
Power supply transitions must occur only when RP# is low.
9.1.1 RP# Connected to System Reset
Use RP# dur ing sys tem res et with au tomated pro gram/e rase dev ices , becaus e the sys tem expec ts to
read from the flash memory when the system exits rese t. If a CPU reset occurs without a flash
memory rese t, proper CPU initialization does not occ ur, because the flash memory might be
providing stat us inform ation ins tead of array da ta. Connecting RP# to the sys tem CPU RESET#
signal to allow proper CPU/flash initialization after a system reset.
Syste m design ers must guard aga inst spurio us write s when VCC vo lt age s ar e abo ve VLKO. Beca use
both WE# a nd CE# must b e lo w for a command wri te , drivi ng eith er si gnal to VIH inhib its wr ite s to
the flash memory devic e. The CUI architec ture pr ovides additional protection, beca use memory
contents can be altered only after successful completion of the two-step command sequences. The
flash memory device is also disabled until RP# is brought to VIH, regard less o f the state of its
control inputs. By holding the de vice in reset (RP# connect ed to s ys tem POWERGOOD) during
power-up/down, invalid bus condition s during power-up can be masked , providing yet a nother
level of memory protection.
9.1.2 VCC, VPP, and RP# Transitions
The CU I latches commands as issued by sys tem software, and is not alt ere d by VPP or CE#
transitions or WSM actions. The CUI default state upon power-up, after exit from res et mode or
aft er VCC transitions above VLKO (Lockout voltage), is read-array mode.
After any program or Block-Erase operation is complete (even after VPP transitions down to
VPPLK), the CUI must be reset to read-a rray mode, using the Read Array command if access to the
flash-m emory array is required.
28F008/ 800B3, 28F016 /16 0B3, 28F320B3, 28F6 40B3
18 Aug 2005 Intel® Adv anced B oot Block Flash Memo ry (B3) Datasheet
48 Order Numbe r: 290580 , Revision: 020
9.2 Res et Sp e cif ica tio ns
Table 26. Reset Specifications
Symbol Parameter VCC 2.7 V – 3.6 V Unit Notes
Min Max
tPLPH RP# Low to Reset during Read
(If RP# is tied to VCC, this specification is not
applicable) 100 ns 1, 2
tPLRH1 RP# Low to Reset during Block Erase 22 µs 3
tPLRH2 RP# Low to Reset during Program 12 µs 3
Notes:
1. If tPLPH is < 100 ns, the device can still reset, but reset is not guaranteed.
2. If RP# is assert ed while a Block Erase or Word Pr o gr a m op er a t ion is not ex ec ut in g, the
res et comple te s with in 100 ns.
3. Sampled, but not 100% tested.
Figure 14. Deep Pow er-Dow n/R eset Op erati ons Waveforms
IH
V
IL
V
RP# (P)
PLPH
t
IH
V
IL
V
RP# (P )
PLPH
t
(A) Reset during Read M ode
Abort
Complete PHQV
tPHWL
tPHEL
t
PHQV
tPHWL
tPHEL
t
(B) Reset during Program or B lock Erase, <
PLPH
tPLR
H
t
PLRH
t
IH
V
IL
V
RP# (P)
PLPH
t
Abort
Complete PHQV
tPHWL
tPHEL
t
PLRH
t
Deep
Power-
Down
(C) Reset Prog r a m or Block Erase, >
PLPH
tPLRH
t
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet Intel® Advanced Boot Block Flash Memory (B3) 18 Aug 2005
Order Number: 290580, Revisio n: 020 49
9.3 Power Supply Decoupling
Flas h me mory power-switching characteri stics requi re ca reful devic e decoupling . System
designers must consider the following three supply current issues:
1. Sta ndby current levels (ICCS).
2. Read curre nt levels (ICCR).
3. Tr ansient peaks produced by falling and rising edges of CE#.
Trans ient curr ent ma gnitudes depend on the devic e output capa citive and inductive loa ding.
Two-line control and proper decoupling capacitor selection suppresses these transient voltage
peaks. Each flash device must ha ve a 0. 1 µF ceramic capacitor connected between each VCC and
GND, and betw ee n its VPP and GND. These high-frequency, inherently low-inductance capacitors
must be placed as clo se as po ssible to the packag e leads .
9.4 Power Consumption
Intel® flash memory devices use a tiered approac h to power saving s that can signi ficantly reduce
overall system power consumption. The Automatic Power Savings (APS) feature reduces power
cons ump tion when the flash memory device is selected but idle. If CE# is deasserted, the flash
memory de vice enters it s standby mode, where curr ent consumption is even lower. The
combination of these features can minimize memory power consumption, and therefore minimize
overall syste m powe r cons um ption.
9.4.1 Active Power
When CE# is at a lo g ic-low l evel an d RP# is at a logic-hi gh leve l, the flash m emory devic e is in the
active mode. Refer to the DC Characteris tic tables for ICC current va lues. Activ e power is the
largest contributor to overall system power consum ption. Minim izing the a ctive current ca n
prof oundly affect system power consumption, especially for battery-operated devices.
9.4.2 Automatic Power Savings (APS)
Automati c Power Saving s provide s low-power operat ion du ring read mode. After data is read from
the flash memory array and the a ddress line s a re quiescent , APS circ uitry pl ac es the f lash memory
device in a mode where typical current is comparable to ICCS. The flash memory stays in this static
sta te with outputs valid until a new location is read.
9.4.3 Standby Power
When CE# is at a logic-hi gh level (VIH) and the flash memory device is in read mode, the flash
memory is in standby mode. This mode disables much of the device circuitry, and substantially
reduces power consumption. Outputs are placed in a high-impedance state independent of the
sta tus of the OE# signal. If CE# tra nsitions to a logic-high level during Erase or Program
operations , the flash memory device continues to perform the opera tion and consu me
correspondin g act ive power until the ope ration is comp leted.
System enginee rs must analyze the br eakdown of standby time versus active time and quantify the
res pec tive power consum ption in each mode for their specific applicat ion. This approa ch provides
a more accurate measure of application-specific power and ener gy requirements.
28F008/ 800B3, 28F016 /16 0B3, 28F320B3, 28F6 40B3
18 Aug 2005 Intel® Advanc ed Boot Block Flash M emo ry (B3) Datasheet
50 Order Numbe r: 290580 , Revision: 020
9.4.4 Deep Power-Down Mode
The deep power-down mode is activated when RP# = VIL (GND ±0.2 V). During read modes,
RP# going low deselects the flash mem ory and places the outputs in a high-impedance state.
Rec overy from deep power-down mode requires a minimum time of tPHQV (see “AC Read
Character is tics” on page 37).
During program or erase mode s , RP# transit ioning low aborts the in-progress operat ion. The
me mory contents of the address bein g pr ogrammed or the block being erased a r e no longer valid,
bec ause the a bort comprom ises da ta inte grity. During de ep power -down, all int ernal circui ts swi tch
to a low-power savings mode (RP # transiti oning to VIL or turn ing off power to the flash mem ory
dev ic e cl ear s th e Stat us Reg i ster ) .
10.0 Operati ons Overview
Flash memory combines EEPROM functionality with in-circuit electrical program-and-erase
cap ability. The B3 flash memory device family uses a Command User Interface (CUI) and
automated alg orithms to simplify Program and Erase operations. The CUI allows for 100%
CMOS- level control inputs and fixed power supplies durin g erasure and programming.
When VPP < VPPLK, the flash me mory device exe cutes onl y the following commands succes sful ly:
•Re ad Ar ra y
•Read St at us Reg i s t er
•Clear Status Register
•Read Identifier
The flash mem ory device provides st andard EEPROM read, standby, and Output-Disable
operations.
Manufacturer identification an d device identificati on data can be access ed through the CUI.
All functions that alt er mem ory contents (program and eras e) are accessible through the CUI. The
int er n al Write St at e M ac h in e ( W S M ) co m p l et el y a uto m a tes Pro g ram a nd Er ase op e r at io n s , wh il e
the CUI sign als the start of an operation and the Status Register reports statu s.
The CUI handles the WE# interface to the data and address latches, and system status requests
during WSM operation.
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet Intel® Advanced Boot Block Flash Memory (B3) 18 Aug 2005
Order Number: 290580, Revisio n: 020 51
10.1 Bus Operations
The B3 flash memory device performs read, program, and erase in-system operations through the
local CPU or microcontroller. All bus cyc les to or from the flash memory conform to s tandard
micr ocontroller bus cycles. Fou r control pins dictate the data flow in and out of the f lash memory
device:
•CE#
•OE#
•WE#
•RP#
Table 27 summarizes these bus operations.
10.1.1 Read
The B3 flas h me mor y device provides four read modes :
•read array
•read id en tifier
•read status
•read query
These mode s a re ac cessible indepe ndently of the VPP voltage. Issue the appr opriate Read Mode
command to the CU I to enter the corresponding mode. Upon initial device power-up or after exit
from reset, the flash memory device automatically defau lts to read-array mode.
CE# and OE# must be driven active to obtain data at the outputs.
•CE# is the device selection control. When acti ve, CE# enables the flash memory device.
•OE# is the da ta output control, and dri ves the se lected memory dat a onto the I/O bus.
For all rea d mod es, WE# and RP# must be at VIH. Figure 10 on page 40 illustrates a read cycle.
Tabl e 27 . Bus Oper atio ns(1)
Mode Note RP# CE# OE# WE# DQ0–7 DQ8–15
Read (Array, S t a tus, or Identifier) 2–4 VIH VIL VIL VIH DOUT DOUT
Output Disable 2 VIH VIL VIH VIH H igh Z High Z
Standby 2 VIH VIH X X Hi gh Z Hi gh Z
Reset 2, 7 VIL X X X High Z High Z
Write 2, 5–7 VIH VIL VIH VIL DIN DIN
Notes:
1. 8- bit devi ces us e only D Q [0:7] .
16- bit dev i c e s use D Q [0:15] .
2. X must be VIL, V IH for control pins and addresses.
3. See DC Characteristi cs for VPPLK, VPP1, VPP2, VPP3, VPP4 voltages.
4. Manufactur er and device cod es can a lso be accessed in re ad identifier m ode (A1–A21 =0). See Table 29.
5 . Re fer to Table 30 for valid DIN during a Write operation.
6. To program or erase the lockable blocks, hold WP# at VIH.
7. RP# must be at GND ± 0. 2 V to meet th e ma xim um deep pow er -dow n curren t spec i fied.
28F008/ 800B3, 28F016 /16 0B3, 28F320B3, 28F6 40B3
18 Aug 2005 Intel® Advanc ed Boot Block Flash M emo ry (B3) Datasheet
52 Order Numbe r: 290580 , Revision: 020
10.1.2 Output Disable
When OE# is at a logic-high level (V IH), the flas h memory d evice outputs are d isab led. Out put pin s
are p la ce d in a h igh -impedance state.
10.1.3 Standby
Des electin g the fla sh memory devic e by br inging CE# to a logic-high level (V IH) places the d evice
in st andby mode. S tandby mode substantia lly reduces device power consumption, without any
latency for subsequent read accesses. In standby mode, outputs are placed in a high-impedance
state independent of OE#. If deselected during Program or Erase operation, the flash memory
device continues to consume active power until the Program or Er ase operation is complete.
10.1.4 Deep Power-Down / Reset
From read mode, RP# at VIL for time tPLPH does the following:
•Desele cts the flash mem ory.
•Pl aces outpu t drivers in a hi gh -imped anc e s t at e.
•Tu r ns of f all in ternal circui ts.
•After a return fro m reset, a time tPHQV i s requi red unt il the in iti al re ad-acc ess ou tput s are vali d.
•After a return from reset, a delay (tPHWL or tPHEL) is required before a write can be initiated.
Af ter th i s w ak e-up interv al, normal operation is restored. The CUI reset s to read-array mode, and
the St at u s Regi ster is s et to 80 H . Figure 14 “Deep Power-Down/Reset Operations Waveforms” on
page 48 (A) illustr ates this case.
If RP# is taken low for time tPLPH during a Program or Erase operation, the operation aborts. The
me mory contents at the aborte d loca tion (for a progra m) or block (for an erase) are no long er valid,
because the da ta m ight b e partially erased or written.
The abort process uses the following sequence:
1. When RP# goes low, the flash memory device shuts down the operation in p rogress, a process
t h at takes time t PLRH to co mplete.
2. After this tim e tPLRH, the flash memory device either reset s to read-arra y mo de (if RP# has
gone high during tPLRH, see Figure 14 “Deep Power-Down/Reset Operations Waveforms” on
pa g e 48 ( B)), o r ent e r s r es e t m o d e ( if RP# is stil l log ic lo w a f te r tPLRH, see Figure 14 “Dee p
Power-Down/Rese t Operations Waveforms” on page 48 (C)).
3. In both cas es , after returning fr om an aborted operation, the releva nt time t PHQV or tPHWL/
tPHEL must elapse before initiating a Rea d or W ri te operation, as discussed in the prev ious
paragraph. However, in this case, these delays are referenced to the end of tPLRH rather than
when RP # goes high.
As with any automated device, RP# must be asserted during system reset. When the system
f inishes reset , the processor exp ects to rea d fr om the fla s h memory. Automated flash memories
pr ovide status informatio n when read during program or Block-Erase ope rations. If a CPU reset
occurs with no flas h memory reset, proper CPU init ializat ion cannot occur, because the flas h
me mory migh t be providing status information instead of array data.
Intel® Flash memo ries allow pr oper CPU initialization afte r a system reset, using the RP# input. In
th is application, RP# is controlled by th e same RESET # signal that rese ts the system CPU.
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet Intel® Advanced Boot Block Flash Memory (B3) 18 Aug 2005
Order Number: 290580, Revisio n: 020 53
10.1.5 Write
A write occurs when both CE# and WE# are low and OE# is hig h. Commands are written to the
Command User Interface (CUI) using standa rd microprocessor write timings to control flas h
memory ope rations. The CUI does not occupy an address able memory location. The addre ss and
data buses are latched on the risi ng edge of the second WE# or CE# pulse , whichever occurs first.
Table 30 shows the available commands, and App endix A provides detailed information about
moving betwe en the different modes of oper ation using CUI commands.
Two commands modify array data:
•Program (40H).
•Erase (20H).
W riting either of the se commands to the interna l Command User Interface (CUI) initiates a
sequence of internal ly timed f unctions that culminate in the completion of the requested tas k
(unless that operation is aborted by either RP# being driven to VIL for tPLRH or a n appr op r iate
Suspend command).
11.0 Operating Mode s
The flash memory device has four read modes:
•read array
•read id en tifier
•read status
•read query
See F igure 1 “B3 Architecture Block Diagram” on page 10).
The flash memory device also has two write modes:
•program
•block erase
Three additional modes are avai lable only during suspended operations:
•erase suspend to program
•erase suspend to read
•program su spend to read
Table 28 “Command C odes and De scri pti ons” on pa ge 54 summ ari ze s th e co mm an ds used to re ac h
th ese modes.
Ap p en d ix A , “Writ e St at e M ac hi n e Cu r r en t /Next St at es ,” is a comprehens ive chart showing the
st at e tr a nsit io n s.
28F008/ 800B3, 28F016 /16 0B3, 28F320B3, 28F6 40B3
18 Aug 2005 Intel® Advanc ed Boot Block Flash M emo ry (B3) Datasheet
54 Order Numbe r: 290580 , Revision: 020
11.1 Read Array
When RP# transitions from VIL (r es e t) to VIH, the flash memory device defaults to read-array
mode and responds to the read-control inputs (CE#, address inputs, and OE#) without any
additional CUI commands.
When the flash mem ory device is in rea d-array mode, four control signa ls cont rol data output:
•WE# must be logic high (VIH)
•CE# mus t be log ic low (VIL)
•OE# must be logic low (VIL)
•RP# must be l ogic high (VIH)
I n addition, the address of the pre ferred loca tion must be applied to the addre ss pins. If the flash
mem ory device is not in read-array mode, such as after a Program or Erase operation, the Read
Arr ay command (FFH) must be written to the CUI before array read s can occur.
Table 28. Comm an d Codes and Descriptions (Sheet 1 o f 2)
Code Device Mode Description
00, 01,
60, 2F,
C0, 98 Invalid/
Reserved Unassigned commands that must not be used. Intel reserves the right to redefine these codes
for future functions.
FF Read Array Places the flash memory device in read-array mode, so that array data is output on the data
pins.
40 Program Set- Up
A tw o-cyc l e co m mand.
• Th e first cycle prepares the CUI f or a pr ogram operation.
• The second cycle latches addresses and data information, and initiates the WSM to
ex ecute the progr am algor ithm.
The flash mem ory device outputs Statu s Register data when CE# or OE# is toggled. To re ad
arr ay data, a R ead Array c ommand is re quired after progr amming. S ee Section 11.4.
10 Alternate
Program Set-Up (See 40H/Program Set-Up)
20 Er as e S et- Up
Pr epares the CUI for the Erase Con firm comma nd. If the next command is not an Erase
Confirm command, then the CUI does the following:
1. Set s both SR. 4 and SR.5 of the Status Regi ster to 1.
2. Pla c es the flash m emory device into the rea d- Status Re gister m ode.
3. Waits for another command.
See Section 1 1.5, “Erase Mode” on page 58.
D0
Er ase Confir m
Pr ogram / Erase
Resume
If th e pr evi ou s co mma nd w as a n Er ase S et- Up com man d, t he n the CU I clo ses the a dd res s an d
data latches, and begins erasing the block indicated on the address pins.
During erase, the f lash m em ory device responds only to th e Read Stat us Registe r and Erase
Suspend commands. The device outputs Status R egis ter data when CE# or OE# is toggled.
If a Pr ogram or Erase o perat ion was previously susp ende d, thi s command re sumes t hat
operation.
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet Intel® Advanced Boot Block Flash Memory (B3) 18 Aug 2005
Order Number: 290580, Revisio n: 020 55
Note: See Chapter 14.0, “W rite S ta t e Machine Current/Next States,” for mode transition information.
B0 Program / Eras e
Suspend
Issuing this comman d susp ends the currentl y execu ting Program/Erase operat ion.
To indicate w hen the operati on has been su ccess fully suspen ded, the St atus Re gister set s
either the program suspend (S R .2) or erase suspend (SR.6), an d sets the WSM status bit
(SR.7) to 1 (ready).
The WSM continues to idle in the SUSPEND state, regardless of the state of all input-control
pins ex cept R P#, whic h imm ediately shuts down the WS M and the remainder o f the device, if it
is driven to VIL.
See Sect io n 11.4. 1, “ Susp en ding an d Re su ming Pro gr amm ing” on p ag e 58 an d Section 1 1.4.1,
“S usp endi ng and Resum ing Pr ogrammin g” on page 58.
70 Read Status
Register
This comman d plac es the flash memory device into Read-Status Register mode. Reading the
device ou tputs the c ontents of the S tatus Regist er, r egardless of the addr ess presen ted to t he
device.
The flash me m ory device automa ticall y enters this mode after a Pro gram or Erase oper ation is
in itia ted. See S ec ti o n 11.3, “Rea d Status Re gister ” on page 56.
50 Clear Status
Register The WS M can set th e bloc k-lock status (S R.1), VPP status (S R .3), progr am st atus (SR.4), an d
erase status (S R.5) bits in the Status Register to 1. H owever, t he WSM canno t clear t hese bits
to 0. Issuing this com m and clears t hese b its to 0.
90 Read Identifier Pl aces the fla sh m emory device into t he intelligent- identifie r-read mode, so that reading t he
device outputs the m anufactur er and de vice codes (A0 = 0 for man ufac ture r, A0 = 1 for the
device; all oth er addr ess inputs must be 0). See Section 11.2, “Read Identifier” on page 56.
Ta ble 28. Comm and Codes and Description s (Sheet 2 of 2)
Code Device Mo de Description
28F008/ 800B3, 28F016 /16 0B3, 28F320B3, 28F6 40B3
18 Aug 2005 Intel® Advanc ed Boot Block Flash M emo ry (B3) Datasheet
56 Order Numbe r: 290580 , Revision: 020
11.2 Read Identifier
To read the manufac turer and devi ce codes, the flash memory devi ce must be in read-identifier
mode , which can be reached by writ ing the Read Identifier command (90H).
As shown in Ta ble 2 9, once in read- identifier mode:
•A0 = 0 outputs the manufacturer identification code.
•A0 = 1 outputs the device identifier.
Note: A1–A21 = 0.
To return to read-array mode, write the Read-Array command (FFH).
11.3 Read Status Reg ist er
The flash memory device St atus Regi ster i ndi cate s when a Prog ram or Erase ope ratio n is compl et e,
and the success or failure of that operation.
•To read the Status Register, issue the Read Status Register (70H) command to the CUI.
This command causes all subsequent Read operations to output data from the Status Register
until another command is written to the CUI.
•To return to reading from the array, issue the Read Array (FFH) command.
The St atus Regis ter bits are output on DQ0–DQ7. The upper byte, DQ8–DQ15, outputs 00H du ring
a Read Status Register command.
The contents of the Status Register are latched on the falling edge of OE# or CE#, which prevent s
possible Bus errors that might occur if Status Register contents change while being read. CE# or
OE# must be toggl ed with each subsequent status read, or the S tatus Regis ter does not indicate
com pletion of a Program or Erase operat ion.
Wh en th e W SM is ac ti v e, SR .7 in d i cat es th e sta tu s o f the WSM . T h e re main i n g bit s in th e Statu s
Register indicate whe ther the WSM was successful in performing the prefe rred operation (see
Table 31 on page 60).
Table 29. Read I dentifier Table
Size Mfr . ID Device Identifier
-T (Top Boot) -B (Bo ttom Boot)
28F004B3 0089H D4H D5H
28F400B3 8894H 8895H
28F008B3
0089H
D2H D3H
28F800B3 8892H 8893H
28F016B3 D0H D1H
28F160B3
0089H
8890H 8891H
28F320B3 8896H 8897H
28F640B3 8898H 8899H
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet Intel® Advanced Boot Block Flash Memory (B3) 18 Aug 2005
Order Number: 290580, Revisio n: 020 57
11.3.1 Clearing the Status Register
The WSM sets status bits 1 through 7 to 1, and cl ears bits 2, 6, and 7 to 0. However, the WSM
cannot clear st atus bits 1 or 3 through 5 to 0.
Beca use bits 1, 3, 4, and 5 indicate various error conditions, these bits can be cleared only through
the Cle ar S tatus Regi ste r (50H) command. By allowing th e system sof twar e to control the resett ing
of thes e bits, several operations can be perf orm ed (s uch as cumulatively pr ogramming severa l
addre sses or erasi ng multi ple blo cks in s equence ) befor e readi ng the Stat us Regi ster t o determin e if
an error occurred during that s eries.
Clea r the S tatus Regis ter before beg inning another command or sequence.
Note: T he Read Array command must be issued before data can be read from t he fla s h me mory array.
11.4 Program Mode
Programming is executed using a two-w rite s e qu e n ce.
1. The Program Setup comm and (40H) is written to the CUI.
2. A second write specifies the address and data to program.
The WS M executes a sequence of internally timed events to program preferred bits of the
addressed location.
The W SM then verif ies that the bits are sufficiently programmed.
Programmi ng the memory changes specific bits within an address location to 0. If user s attempt to
program 1 ins tead of 0, the memory cell contents do not change and no error occurs .
The St atus Regist er indic ates the programming s tatus : while the program sequ ence exec utes, st atus
bit 7 is 0.
To poll the Status Regi ster, toggle either CE# or OE#.
While programming, the onl y valid commands ar e:
•Read Status Regi ster
•Program Suspend
•Program Resume
When programming is complet e, the program-status bits must be checked.
•If the programming operation was unsuccessful, SR.4 is set, indicating a program failure.
•If SR.3 is set, then VPP was no t within ac ceptable limits, and the W SM did not exec ute the
program command.
•If SR.1 is set, a program operation was attempted on a locked block and the operation aborted.
Clea r the S tatus Regis ter before atte mpt ing the next operation. Any CUI instruc tion can foll ow
after programming is completed; however, to prevent inadvertent Status Register reads, be sure to
reset the CUI to read-array mode.
28F008/ 800B3, 28F016 /16 0B3, 28F320B3, 28F6 40B3
18 Aug 2005 Intel® Advanc ed Boot Block Flash M emo ry (B3) Datasheet
58 Order Numbe r: 290580 , Revision: 020
11.4.1 Suspending and Resuming Programming
The P r ogram Suspend command halts the in-progress program operation to read data from another
flash memory location.
1. After the programming process starts, writ ing the Program Suspend comma nd to the CUI
r eque sts that the WSM suspend the program sequ enc e (at predeterm ined points i n the program
algorithm).
2. The flash memory device continues to output Status Register data after the Program Suspend
command is wr itten.
3. Polli ng SR .7 a nd SR .2 de termines when the program operation has been su spended (both are
se t to 1) .
tWHRH1/tEHRH1 specifies the program- suspend latenc y.
4. A Re ad Array c omman d can now be written to the CUI to read data from blocks other than the
suspended block.
The only other valid c ommands while program is suspended are:
— Read Status Register
— Read Identifier
—Program Resume
5. After the Progra m Resume comman d is written to the flash memory, the WSM continues with
the program process , and Status Regis ter bits SR. 2 and SR.7 are a utom atically cleared.
6. After the Pr ogram Resume command is wr itten, the f las h m em ory device automatically
outputs Status Register dat a when read.
See Appendix B, “Progr am and Erase Flowcharts.”
Note: VPP must r emain a t the same VPP level used for program while in program-suspend mode. RP#
must also rema in at VIH.
11. 5 Era se Mo de
To erase a block:
1. Write the Erase Set-up and Er as e Confirm commands to the CUI, along wit h an address
identifying the block to be erased.
This address is latche d in ternal ly w h en the Er ase Co n firm command is i ssued.
Block erasure set s all bits within the block to 1. Only one block can be eras ed at a time.
2. The W SM ex ecu tes a seq u en ce of in t er n al ly ti med ev e nt s :
a. programs al l bits within the block to 0.
b. Erase s all bits within the b lock to 1.
c. Verifies th at al l bits within the block are sufficiently erased.
While t h e eras e execute s, status b it 7 is 0.
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet Intel® Advanced Boot Block Flash Memory (B3) 18 Aug 2005
Order Number: 290580, Revisio n: 020 59
3. When t h e Status Regi ster ind i cat es th at erasure is comp lete, check the era se-status bit to verify
that the Erase operation was successful.
— If the Erase operat ion was unsuccessful, SR.5 of the S tatus Register is set to 1, indicat ing
an er a se fa i lu r e.
— If VPP was no t within acceptable limits after the Erase Confir m command was is sued, the
WSM does not execute the erase sequence. Instead, SR.5 is set to indicate an Erase error,
and SR .3 is set to 1, indicating that the VPP supply voltage was not within acceptable
limits.
4. After an E ras e operat ion, clear the Status Register (50H) be fore atte mp ting th e next ope ration.
Any CUI instruction can follow af ter eras ur e is completed.
5. To prevent in adve rtent status- regis ter reads, plac e the flash memory device in read-arra y
mo d e af t er th e er a s e is complete.
11.5.1 Suspending and Resuming Erase
Beca use an Erase opera tion requires on the order of se conds to comple te, an Erase Suspend
command is provided. Erase Suspend interrupts an erase sequence to read data from —or program
data to— another block in memory.
Af te r th e er as e s eq u en ce is sta r te d , w ri t in g th e Er as e S uspe n d comm a nd to th e C U I req u es ts th a t
th e WSM p aus es t h e eras e seq u ence at a p r edetermi ned po int in the erase algor ithm.
Note: The Stat us Regi ster will indicates if/when the Erase operation has been suspen ded.
•A Read Array/P rogram command can now be written to the CUI, to rea d data from/ program
data to blocks other than the one currently sus pended.
•The Program command can subsequently be susp ended to read yet anot her array location.
Th e o n ly valid co mmands while Eras e is suspended are:
•Era se R esu m e
•Program
•Read Array
•Read Status Regi ster
•Read Identifie r
During erase-suspend mode, to place the flash memory device in a pseudo-standby mode, set CE#
to VIH, which reduces active current consumption.
Era se Resu me c o n ti n ues the er a s e seq u e nc e w h en CE # = VIL. As with the end of a standard Erase
operation, the Stat us Register must be read and cleared before the next ins truction is issued.
28F008/ 800B3, 28F016 /16 0B3, 28F320B3, 28F6 40B3
18 Aug 2005 Intel® Advanc ed Boot Block Flash M emo ry (B3) Datasheet
60 Order Numbe r: 290580 , Revision: 020
Notes:PA: Program Address PD: Program Data BA: Block Address
IA: Identifier Address ID: Identifier Data SRD: Status Register Data
1. Bus operations are defined in Table 27.
2. Following the Int elligent I dentifier command, t w o Read operat ions ac cess m anufactur er and device
codes.
– A 0 = 0 for manufacturer code.
– A0 = 1 for de vice code.
– A1–A21 = 0.
3. Ei ther t he 40H or 10H command is valid. The s tandard i s 40H.
4. When writing commands to the flash memory device, the upper data bus [DQ 8–DQ15] must b e either
VIL or VIH, to minimiz e curr ent draw.
Table 30. Comman d Bus Definitions (1,4)
First Bus Cycle Second Bus Cycle
Command Notes Oper Addr Data Oper Addr Data
Read Array Write X FFH
Read Identifier 2 Write X 90H Re ad IA ID
Read Status Regi ster Write X 70H Read X SRD
Cle ar Stat us Re gi s t er Writ e X 50H
Program 3 Write X 40H /
10H Write PA PD
Block Erase/Confirm Write X 20H Write BA D0H
Pr ogram/Erase S uspend Writ e X B0H
Pr ogram/Er ase Resume W rite X D0 H
Table 31. Status Register Bit Definition
WSMS ESS ES PS VPPS PSS BLS R
76543210
Bits NOTES:
SR.7 = WRITE ST ATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
Check Write State Machine bit first to determine word program
or block-erase completion, before checking program or erase-
s tatus bits.
SR.6 = ERASE-SUSPEND STATUS (ESS)
1 = Er ase Suspen ded
0 = Er ase In Progress/Completed
When erase suspend is issued, WSM halts execution and sets
both WSMS and ESS bits to 1. ESS bit remains set at 1 until an
Er ase Resume comm and is issu ed.
SR .5 = E RASE STATUS (ES)
1 = Er ror In Block E rasure
0 = Succes sful Block Erase
When this bit is set to 1, WSM has applied the maximum
num ber of er ase pu lses to the block and is still unable to verify
successful block erasure.
SR.4 = PROGRAM STATUS (PS)
1 = Error in Word Program
0 = Succes sful Word Pr ogram When this bit is set to 1, WSM has attempted but failed to
program a word.
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet Intel® Advanced Boot Block Flash Memory (B3) 18 Aug 2005
Order Number: 290580, Revisio n: 020 61
SR.3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
The V PP st at us bit d oes no t cont in uousl y i ndic at e th e VPP level.
The WSM inter rogates the VPP level only after the Program or
Er ase command sequ ences are ent ered, and informs the
system if VPP has not been swit ched on. The VPP is also
check ed b efor e t he W SM ve rifi es the op era tion . T he VPP status
bit is not guaranteed to report accurate feedback between
VPPLK m ax and VPP1 m i n or bet ween V PP1 max and VPP4 min.
SR.2 = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/Completed
When program suspend i s issued, WSM halts execution and
set s bo th WS MS and P SS bi ts t o 1. Th e P SS b it re ma ins se t to
1 until a P rogra m Resume command is issued .
SR.1 = BLOCK LOCK STATUS
1 = Program/Erase attempted on locked block;
Opera tion abort ed
0 = N o operatio n to locked blocks
If a Program or Erase operation is attempted to one of the
lock ed block s, the W S M se ts t his b it. T he ope rat i on spe ci fie d i s
aborted and the flash mem ory device re turns to read st atus
mode.
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) This bit is reserved for future use and must be masked out
when polling the Status Regi ster.
Note: A Command Sequence Error is indicated when SR.4, SR.5, and SR.7 are set.
Bits NOTES:
28F008/ 800B3, 28F016 /16 0B3, 28F320B3, 28F6 40B3
18 Aug 2005 Intel® Advanc ed Boot Block Flash M emo ry (B3) Datasheet
62 Order Numbe r: 290580 , Revision: 020
12.0 Block Locking
The B3 flash memory device architecture features two hardware-lockable parameter blocks.
12.1 WP# = VIL for Block Lock ing
Th e lockable blocks are lo cked w hen WP# = VIL; any program or Erase operation to a locked
blo c k re sul ts in an er ro r, which is r ef le cted in the St at u s Re gi s t er :
•For top configuration, the top two parameter blocks are lockable:
— blocks #133 and #134 for 64 Mbit
— blocks #69 and #70 for 32 Mbit
— blocks #37 and #38 for 16 Mbit
— blocks #21 and #22 for 8 Mbit
— blocks #13 and #14 for 4 Mbit
•For the bottom configuration, the bottom two parameter blocks are lockable. Th es e are blocks
#0 and #1 for 4, 8 , 16, 32, and 64 Mbit.
Unlocked blocks can be programmed or erased normal ly (unless VPP is below VPPLK).
12.2 WP# = VIH for Block Unlocking
WP# = VIH unloc ks all locka ble blocks. These blocks can now be programmed or erased.
Note: RP # does not override WP# locking for the B3 flash memory device, as in previous Boot Block
devices.
•WP# controls all block locking.
•VPP provides pro tec tion against spurious writes.
Table 32 defines the wri te- protection meth ods.
Table 32. Write-Protection Tru th Table for the B3 Device Family
VPP WP# RP # Write Prote cti on Prov ide d
XXV
IL All Blocks Locked
VIL XV
IH All Blocks Locked
≥ VPPLK VIL VIH Lockable Blocks Locked
≥ VPPLK VIH VIH All Blocks Unlocked
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet Intel® Advanced Boot Block Flash Memory (B3) 18 Aug 2005
Order Number: 290580, Revisio n: 020 63
13.0 VPP Program and Erase Voltages
TheB3 flash memory device produc ts provide in-s ystem programmi ng and erase at 2.7 V. For
customers requiring fast programming in their manufacturing environment, the B3 flash memory
device includes an additional low-cost 12-V programming feature.
The 12-V VPP mode enhances programming performanc e during the short period of time typic ally
found in manufacturing processes. Howe ver, this mode is not intended for extended use. 12 V can
be appli ed to VPP during p r ogram and Erase operati ons for a maximum of 1000 cycles on the main
blocks, and 2500 cycles on the parameter blocks. VPP can be connected to 12 V for a total of 80
hours maximum.
Warning: Stressing the flash memory devic e beyond these limits might ca use permanent dam age.
During Rea d operations or idle times , VPP can be tied to a 5-V supply. For Program and Erase
operations , a 5-V supply is not permit ted. The VPP must be supplied with either 2.7 V to 3.6 V or
11.4 V to 12.6 V during Program and Erase operations.
13.1 VPP = VIL for Complete Protection
The VPP programming voltage can be held low for complete write protection of all blocks in the
flash memor y d evice. When VPP is below VPPLK, any P rogram or Erase opera tion results in an
error, prompting the corresponding SR.3 to be set.
14.0 Add itional Information
Order Number Document/Tool
297948 Intel
®
Advanced Boot Bl ock Flash Memory Family Specification Update
292199 AP-641 Achieving Low Power with the 3 Volt Advanced Boot Block Flash Memory
292200 AP-642 Designing for Upgrade to th e 3 Volt Advanced Boot Bl ock Fl ash Me mory
Note 2 3 Volt Advanced Boot Block Algorithms (‘C’ and assembly)
ht tp://d ev eloper.intel .c om / d es i g n/f las h/ s w to ols
Contact your Intel Representative Intel® Flash Data Integrator (IFDI) Software Developer’s Kit
297874 IFDI In teractive: P lay with Intel® Flash Data Integrator on Your PC
Notes:
1. Call the Intel Liter ature Cen ter at (800) 548-4725 to request Int el documentation . Int ernation al cus tome r s m ust c ontact
their local Intel or distribution sales office.
2. Visit the Intel home page at http://www.Intel.com or http://developer.intel.com for technical documentation and tools.
3. For the most current information about Intel
®
Advanced Boot Block Flash memory and Intel
®
Adv a nc ed+ Boot Block
Flash memory, visit http://developer.intel.com/design/flash/
28F008/ 800B3, 28F016 /16 0B3, 28F320B3, 28F6 40B3
18 Aug 2005 Intel® Advanc ed Boot Block Flash M emo ry (B3) Datasheet
64 Order Numbe r: 290580 , Revision: 020
Appendix A Write State Machine Current/Next States
Table 33. Write State Machine (She et 1 of 2)
Command In put (a nd Next State)
Current
State SR.7 Data
When
Read
Read
Array
(FFH)
Program
Setup
(10/40H)
Erase
Setup
(20H)
Erase
Confirm
(D0H)
Prog/Ers
Suspend
(B0H)
Prog/Ers
Resume
(D0H)
Read
Status
(70H)
Clear
Status
(50H)
Read
Identifier.
(90H)
Read Array “1” Array Read
Array Program
Setup Erase
Setup Read Array Read
Status Read
Array Read
Identifier
Read
Status “1” Status Read
Array Program
Setup Erase
Setup Read Array Read
Status Read
Array Read
Identifier
Read
Identifier “1” Identifier Read
Array Program
Setup Erase
Setup Read Array Read
Status Read
Array Read
Identifier
Prog. Setup “1” Status Program (Command Input = Data to be Programmed)
Program
(continue) “0” Status Progr am (continue) Prog.
Sysop. to
Rd.
Status
Program (continue)
Program
Suspend to
Read
Status “1” Status
Prog.
Susp.
to
Read
Array
Program Suspend
to Read Array Program
(continue
)
Program
Su s p. to
Read
Array
Program
(continue
)
Prog.
Susp. to
Read
Status
Prog.
Susp.
to
Read
Array
Prog.
Susp. to
Read
Identifier
Program
Suspend to
Read Array “1” Array
Prog.
Susp.
to
Read
Array
Program Suspend
to Read Array Program
(continue
)
Program
Su s p. to
Read
Array
Program
(continue
)
Prog.
Susp. to
Read
Status
Prog.
Sus. to
Read
Array
Prog.
Susp. to
Read
Identifier
Prog. Susp.
to Read
Identifier “1” Identifier
Prog.
Susp.
to
Read
Array
Program Suspend
to Read Array Program
(continue
)
Program
Su s p. to
Read
Array
Program
(continue
)
Prog.
Susp. to
Read
Status
Prog.
Sus. to
Read
Array
Prog.
Susp. to
Read
Identifier
Program
(complete) “1” Status Read
Array Program
Setup Erase
Setup Read Array Read
Status Read
Array Read
Identifier
Erase
Setup “1” Status Erase Comman d Error Erase
(continue
)
Erase
Cant.
Error
Erase
(continue
)E r as e Com m and E rr or
Erase Cant.
Error “1” Status Read
Array Program
Setup Erase
Setup Read Array Read
Status Read
Array Read
Identifier
Erase
(continue) “0” Status Erase (continue) Erase
Su s. to
Read
Status Erase (continue)
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet Intel® Advanced Boot Block Flash Memory (B3) 18 Aug 2005
Order Number: 290580, Revisio n: 020 65
Erase
Suspend to
Status “1” Status
Erase
Susp.
to
Read
Array
Program
Setup
Erase
Susp.
to
Read
Array
Erase
Erase
Susp. to
Read
Array Erase
Erase
Susp. to
Read
Status
Erase
Susp.
to
Read
Array
Ers.
Susp. to
Read
Identifier
Erase
Susp. to
Read Array “1” Array
Erase
Susp.
to
Read
Array
Program
Setup
Erase
Susp.
to
Read
Array
Erase
Erase
Susp. to
Read
Array Erase
Erase
Susp. to
Read
Status
Erase
Susp.
to
Read
Array
Ers.
Susp. to
Read
Identifier
Erase
Susp. to
Read
Identifier “1” Identifier
Erase
Susp.
to
Read
Array
Program
Setup
Erase
Susp.
to
Read
Array
Erase
Erase
Susp. to
Read
Array Erase
Erase
Susp. to
Read
Status
Erase
Susp.
to
Read
Array
Ers.
Susp. to
Read
Identifier
Erase
(complete) “1” Status Read
Array Program
Setup Erase
Setup Read Ar r ay Read
Status Read
Array Read
Identifier
Table 33. Write St ate Machine (Sheet 2 of 2)
Command Input (and Next State)
Current
State SR.7 Data
When
Read
Read
Array
(FFH)
Program
Setup
(10/40H)
Erase
Setup
(20H)
Erase
Confirm
(D0H)
Prog/Ers
Suspend
(B0H)
Prog/Ers
Resume
(D0H)
Read
Status
(70H)
Clear
Status
(50H)
Read
Identifier.
(90H)
28F008/ 800B3, 28F016 /16 0B3, 28F320B3, 28F6 40B3
18 Aug 2005 Intel® Advanc ed Boot Block Flash M emo ry (B3) Datasheet
66 Order Numbe r: 290580 , Revision: 020
Appendix B P rog ram and Erase Flowcharts
Figure 15. Pr ogr am Flowch art
Start
Write 40H
Program Address/Data
Read Status Register
SR.7 = 1?
Full Status
Check if Desired
Program Complete
Read Status Register
Data (See A bove)
V
PP
Range Error
Programming Error
Attempted Program to
Locked Block - Aborted
Program Successful
SR.3 =
SR.4 =
SR.1 =
FULL STATUS CHECK PROCEDURE
Bus Operation
Write
Write
Standby
Repeat for subsequent programming operations.
SR Ful l St atus Ch eck can be don e after each program or after a seq uen ce of
program operations.
Write FF H after t he l ast program op erat i on to reset devi ce to read array mod e.
Bus Operation
Standby
Standby
SR.3 MUST be cleared, if set during a program attempt, before further
att emp ts are allowed by t he Write State Machi ne.
SR.1, SR.3 and SR.4 are on ly cleared by the Clear St aus Regist er Comm and ,
in cases wh ere mu lti pl e byt es are programmed before ful l stat us is checked.
If an error is detected, clear the status register before attempting retry or other
error recov e ry.
No
Yes
1
0
1
0
1
0
Command
Program Setup
Program
Comments
Data = 40H
Data = Data to Program
Addr = Locat ion to P rogram
Ch eck SR. 7
1 = WSM Read y
0 = WSM B usy
Command Comments
Ch eck SR. 3
1 = V
PP
Low Detect
Ch eck SR. 1
1 = Attemp ted Program to
Locked Bl ock - P rogram
Aborted
Read Status Register Data Toggle
CE# or OE# to Update Statu s
Reg i ster Data
Standby Check SR.4
1 = V
PP
Program Erro r
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet Intel® Advanced Boot Block Flash Memory (B3) 18 Aug 2005
Order Number: 290580, Revisio n: 020 67
Figure 16. Prog ram S usp end /Resume Fl ow char t
Start
Write B0H
Read Status R egister
No
Comments
Data = 70H
Addr = X
Data = FFH
Addr = X
SR.7 =
SR.2 =
1
Write FFH
Read Array Data
Program Completed
Done
Reading
Yes
Write FFHWrite D0H
Program Resumed Read Array Data
0
1
Read array data from block
other than the one being
programmed.
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Addr = X
Check SR.7
1 = WSM Ready
0 = WSM Busy
Check SR.2
1 = Program Suspended
0 = Program Completed
Data = D0H
Addr = X
Bus
Operation
Write
Write
Read
Read
Standby
Standby
Write
Command
Read Status
Read Array
Program
Resume
Writ e 70H
0
Data = B0H
Addr = X
Write Program
Suspend
28F008/ 800B3, 28F016 /16 0B3, 28F320B3, 28F6 40B3
18 Aug 2005 Intel® Advanc ed Boot Block Flash M emo ry (B3) Datasheet
68 Order Numbe r: 290580 , Revision: 020
Figure 17. Block Er ase Flowc hart
Start
Write 20H
Write D0H and
Block Address
Read Status Register
SR.7 =
Full Status
Check if Desired
Block Eras e Complete
FULL STATUS CHECK PROCEDURE
Bus Operation
Write
Write
Standby
Repeat for subsequent block erasures.
Fu ll St at us Check can be don e after each block erase or after a sequen ce of
block erasures.
Write FF H after t he l ast write operat i on to reset device t o read array mode.
Bus Operation
Standby
SR. 1 and 3 M US T be cl eared, if set duri ng an erase attempt, before further
att emp ts are allowed by t he Write St at e M achin e.
SR.1, 3, 4, 5 are onl y cleared by the Clear S taus Reg i st er Comm and , i n cases
wh ere mu lti pl e byt es are erased before ful l stat us is checked.
If an error is d et ect ed, clear th e st at us regi ster before attemp tin g retry or ot her
error recov ery.
No Yes
Suspend Erase
Suspend
Erase Loop
1
0
Standby
Command
Erase Set up
Erase Confirm
Comments
Data = 20H
Addr = Within Block to Be
Erased
Data = D0H
Addr = Within Block to Be
Erased
Ch eck SR. 7
1 = WSM Read y
0 = WSM B usy
Command Comments
Ch eck SR. 3
1 = V
PP
Low Detect
Check SR.4,5
Both 1 = Command Sequence
Error
Read Status Register
Data (See A bove)
V
PP
Range Error
Command Sequence
Error
Block Erase
Successful
SR.3 =
SR.4,5 =
1
0
1
0
Block Eras e Er rorSR.5 = 1
0
Attempted E rase of
Locked Block - Aborted
SR.1 = 1
0
Read Status Register Data Toggle
CE# or OE# to Update Statu s
Register Data
Standby Check SR.5
1 = B lock E rase Error
Standby Check SR.1
1 = A t tem pted Erase of
Locked Bl ock - E rase Aborted
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet Intel® Advanced Boot Block Flash Memory (B3) 18 Aug 2005
Order Number: 290580, Revisio n: 020 69
Figure 18. E rase Susp end /Resume Fl ow cha rt
Start
Write B0H
Read Status Register
Bus Op eratio n
Write
Write
No
Command
Erase Su s pend
Read Arr ay
Comments
Data = B0H
Addr = X
Data = FFH
Addr = X
SR.7 =
SR.6 =
1
Write FFH
Read Array Data
Erase Completed
Done
Reading
Yes
Write FFHWrite D0H
Erase Resumed Read Array Data
0
1
0
Read Read array data f r om bloc k
other than t he one being
erased.
Read
Status Regis ter Data Toggle
CE# or O E# to Update Status
Register Data
Addr = X
Standby Check SR.7
1 = WS M Read y
0 = WSM Busy
Standby Check SR.6
1 = Erase Suspended
0 = Erase Complet ed
Write Erase Resume Data = D0H
Addr = X
Write Read St atus Data = 70H
Addr = X
Write 70H
28F008/ 800B3, 28F016 /16 0B3, 28F320B3, 28F6 40B3
18 Aug 2005 Intel® Advanc ed Boot Block Flash M emo ry (B3) Datasheet
70 Order Numbe r: 290580 , Revision: 020
Appendix C Orde ring Information
Figu re 19. Ordering I nf orm at io n
Table 34. Ordering Information: Valid Combinations (Sheet 1 of 2)
40-Lead TSOP 48-Lead TSOP 48-Ball µBGA CSP(1,2) 48-Ball VF BGA
Ext. Temp. 64 Mbit TE28F640B3TC80
TE28F640B3BC80 GE28F640B3TC80
GE28F640B3BC80
Ext. Temp. 32 Mbit TE28F320B3TD70
TE28F320B3BD70
TE28F320B3TC70
TE28F320B3BC70
TE28F320B3TC90
TE28F320B3BC90
TE28F320B3TA100
TE28F320B3BA100
TE28F320B3TA110
TE28F320B3BA110
JS28F320B3TD70
JS28F320B3BD70
GE28F320B3TD70
GE28F320B3BD70
GE28F320B3TC70
GE28F320B3BC70
GE28F320B3TC90
GE28F320B3BC90
PH28F320B3BD70
Package
TE = 4 8 -Le a d TS OP
GT = 48-Ball µBGA* CSP
GE = VF BG A CSP
RC = Ea sy B G A
PC = Pb Free Easy BG A
PH = Pb Free VFBG A
JS = Pb Fre e TS OP
Product line designator
for all Intel
®
Flas h product s
Access Speed (ns)
(70, 80, 90, 100, 110)
P rod uc t F a mily
C3 = 3 Volt Adv anc edBoo
t B
V
CC
=2.7V–3.6V
V
PP
=2.7V–3.6Vor
11.4 V–12 .6 V
Device Dens ity
640=x16(64Mbit)
320=x16(32Mbit)
160=x16(16Mbit)
800=x16(8Mbit)
T=Top Blocking
B=Bott o m Bloc king
Lithography
A = 0.25 µm
C = 0.18 µm
D = 0.13 µm
T E 2 8 F 3 2 0 B 3 T C 7 0
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet Intel® Advanced Boot Block Flash Memory (B3) 18 Aug 2005
Order Number: 290580, Revisio n: 020 71
Ext. Temp. 16 Mbit
TE28F016B3TA90
TE28F016B3BA90
TE28F016B3TA110
TE28F016B3BA110
TE28F160B3TD70
TE28F160B3BD70
TE28F160B3TC70
TE28F160B3BC70
TE28F160B3TC80
TE28F160B3BC80
TE28F160B3TC90
TE28F160B3BC90
TE28F160B3TA90
TE28F160B3BA90
TE28F160B3TA110
TE28F160B3BA110
JS28F160B3TA70
JS28F160B3BD70
GT28F160B3TA90(3)
GT28F160B3BA90(3)
GT28F160B3TA110(3)
GT28F160B3BA110(3)
GE28F160B3TD70
GE28F160B3BD70
GE28F160B3TC70
GE28F160B3BC70
GE28F160B3TC80
GE28F160B3BC80
GE28F160B3TC90
GE28F160B3BC90
PH28F160B3TD70
PH28F160B3BD70
Ext. Temp. 8 Mbit TE28F800B3TA90
TE28F800B3BA90
TE28F800B3TA110
TE28F800B3BA110
GE28F800B3TA70
GE28F800B3BA70
GE28F800B3TA90
GE28F800B3BA90
Notes:
1. The 48-ball µBGA pa ckage top side mark r ead s F160 B3. Th is mark is identical for both x8 and x16 products. All
product shipp ing b oxes or trays provide the corre ct info rmation regarding bus archite cture . H ow eve r, once the fla sh
me mory devi ces ar e remo ve d fr om th e s hipp in g m edia , di f fere nt iat ing b ase d on th e to p si de ma r k migh t be di f fi cult. Th e
device ident if ier (acc essible throu gh the Device ID command : see Sect ion 11.2, “Read Identifier” o n p age 56 for further
details) en ables x8 and x16 µBGA pack age product dif fere ntiat ion.
2. The second line of th e 48-ball µBGA pac kage top side m ark specif ies as sembly codes. For samples only, the firs t
charact er sign ifies e it her:
– E fo r engineerin g samp les, or
– S fo r silicon daisy-ch ain sam ples.
All other assembly codes wi thout an E or an S as the first character are production units.
3. Int el reco m m end s using.18 µm Intel
®
Adv an ced Boot Bl o c k P r od uc t s.
Table 34. Ordering Information: Valid Combinations (Sheet 2 of 2)
40-Lead TSOP 48-Lead TSOP 48-Ball µBGA CSP(1,2) 48-Ball VF BGA