DESCRIPTION
Document No. VAL UERAM1441-001.B00 10/14/14 Page 1
SPECIFICATIONS
*Power will vary depending on the SDRAM and
Register/PLL Used.
KVR18R13S8K3/12
12GB (4GB 1RX8 512M x 72-Bit x 3 pcs.) PC3-14900
CL13 Registered w/Parity 240-Pin DIMM Kit
Continued >>
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FEATURES
ValueRAM’s KVR18R13S8K3/12 is a kit of three 512M x 72-bit
(4GB) DDR3-1866 CL13 SDRAM (Synchronous DRAM),
registered w/ parity, 1Rx8, ECC, memory modules, based on
nine 512M x 8-bit FBGA components per module. Total kit
capacity is 12GB. The SPDs are programed to JEDEC standard
latency DDR3-1866 13-13-13 at 1.5V. Each 240-pin DIMM uses
gold contact fingers. The JEDEC standard electrical and
mechanical specifications are as follows:
• JEDEC standard 1.5V (1.425V ~ 1.575V) Power Supply
• VDDQ = 1.5V (1.425V ~ 1.575V)
• 933MHz fCK for 1866Mb/sec/pin
• 8 independent internal banks
• Programmable CAS latency: 13, 11, 10, 9, 8, 7, 6
• Programmable Additive Latency: 0, CL - 2, or CL - 1 clock
• 8-bit pre-fetch
• Burst Length: 8 (interleave without any limit, sequential with
starting address “000” only), 4 with tCCD = 4 which does not
allow seamless read or write (either on the fly using A12 or
MRS)
• Bi-directional Differential Data Strobe
• Internal (self) calibration: Internal self calibration through ZQ
pin (RZQ: 240 ohm ± 1%)
• On Die Termination using ODT pin
• On-DIMM thermal sensor (Grade B)
• Average Refresh Period 7.8us at lower than TCASE 85°C,
3.9us at 85°C < TCASE < 95°Cº
• Asynchronous Reset
• PCB: Height 1.180” (30.00mm), double sided component
CL(IDD)
Row Cycle Time (tRCmin)
Refresh to Active/Refresh
Command T ime (tRFCmin)
Row Active T ime (tRASmin)
Maximum Operating Power
UL Rating
Operating Temperature
Storage Temperature
13 cycles
47.125ns(min.)
260ns(min.)
34ns(min.)
3.373 W* (per module)
94 V - 0
0o C to +85o C
-55o C to +100o C
Memory Module Specifi cations
Document No. VALUERAM1441-001.B00 Page 2
MODULE DIMENSIONS
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