NT1GT72U89D0BD-AC / NT2GT72U8PD0BD-AC / NT4GT72U4ND0BD-AC / NT4GT72U8ND9BD-AC NT1GT72U89D1BD-3C / NT2GT72U8PD1BD-3C / NT4GT72U4ND1BD-3C / NT8GTT72U4ND3YD-3C NT1GT72U89D1BN-3C / NT2GT72U8PD1BN-3C / NT4GT72U4ND1BN-3C / NT8GTT72U4ND4YD-3C NT1GT72U89D2BD-3C / NT2GT72U8PD2BD-3C / NT4GT72U4ND2BD-3C / NT8GTT72U4ND5YD-3C NT1GT72U89D6BD-AC / NT2GT72U8PD6BD-AC / NT4GT72U8ND9BD-3C 240pin DDR2 SDRAM Fully Buffered DIMM Based on 128Mx8 (1GB/2GB/4GB), 256Mx4 (4GB), and 512Mx4 (8GB) DDR2 SDRAM Features *Performance: Speed Sort DIMM CAS Latency fck - Clock Freqency tck - Clock Cycle fDQ - DQ Burst Freqency PC2-5300 -3C PC2-6400 -AC Unit 5 333 5 400 MHz 3 2.5 ns 667 800 Mbps * 1GB/2GB: 128Mx72/256Mx72 DDR2 Fully Buffered DIMM based on 128Mx8 DDR2 SDRAM (NT5TU128M8DE-3C/-AC) * 4GB: 512Mx72 DDR2 Fully Buffered DIMM based on 128Mx8/256Mx4 DDR2 SDRAM (NT5TU256M4DE-3C/-AC)/ (NT5TU128M8DE-3C/-AC) * 8GB: 1Gx72 DDR2 Fully Buffered DIMM based on 512Mx4 DDR2 SDRAM (NT5TU512T4DY-3C) * JEDEC Standard 240-pin Fully Buffered ECC Dual In-Line Memory Module. * Intended for 333MHz/400MHz applications. * Inputs and outputs are SSTL-18 compatible. * VDD = 1.8V 0.1V, VDDQ = 1.8V 0.1V. * Host Interface and AMB component industry standard compliant. * Support SMBus protocol interface for access to the AMB configuration registers. * Detects errors on the channel and reports them to the host memory controller. * Automatic DDR2 DRAM Bus Calibration. * Full Host Control of the DDR2 DRAMs. * Over-Temperature Detection and Alert. * MBIST & IBIST Test Functions. * Transparent Mode for DRAM Test Support. * Serial Presence Detect (SPD) * Gold contacts * RoHS Compliant products * SDRAMs in 60-ball BGA Package Description Fully Buffered 240-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Dual In-Line Memory Module (DIMM), organized as an eight bank 128Mx72 (1GB), 256Mx72 (2GB), 512Mx72 (4GB), or 1Gx72 (8GB) high-speed memory array. The module uses nine 128Mx8 (1GB), eighteen 128Mx8 (2GB), thirty-six 128Mx8/256Mx4 (4GB), or thirty-six 512Mx4 (8GB) DDR2 SDRAMs in BGA packages. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All NANYA DDR2 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25" long space-saving footprint. The DIMM is intended for use in applications operating up to 333MHz/400 MHz clock speeds and achieves high-speed data transfer rates of up to 667 Mbps/800 Mbps. Prior to any access operation, the device latency and burst type/length/operation type must be programmed into the DIMM by address inputs A0-A13 and I/O inputs BA0, BA1, and BA2 using the mode register set cycle. REV 1.3 03/2009 1 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BD-AC / NT2GT72U8PD0BD-AC / NT4GT72U4ND0BD-AC / NT4GT72U8ND9BD-AC NT1GT72U89D1BD-3C / NT2GT72U8PD1BD-3C / NT4GT72U4ND1BD-3C / NT8GTT72U4ND3YD-3C NT1GT72U89D1BN-3C / NT2GT72U8PD1BN-3C / NT4GT72U4ND1BN-3C / NT8GTT72U4ND4YD-3C NT1GT72U89D2BD-3C / NT2GT72U8PD2BD-3C / NT4GT72U4ND2BD-3C / NT8GTT72U4ND5YD-3C NT1GT72U89D6BD-AC / NT2GT72U8PD6BD-AC / NT4GT72U8ND9BD-3C Ordering Information Part Number NT1GT72U89D0BD-AC NT1GT72U89D6BD-AC AMB IDT C1 NT1GT72U89D1BD-3C IDT C1 NT1GT72U89D2BD-3C IDT AMB+ NT1GT72U89D1BN-3C Intel D1 NT2GT72U8PD0BD-AC NT2GT72U8PD6BD-AC IDT C1 Speed 400MHz (2.5ns @ CL = 5) (3ns @ CL = 5) 400MHz (2.5ns @ CL = 5) NT2GT72U8PD2BD-3C IDT AMB+ NT2GT72U8PD1BN-3C Intel D1 NT4GT72U4ND0BD-AC IDT C1 400MHz IDT AMB+ (2.5ns @ CL = 5) 333MHz (3ns @ CL = 5) NT4GT72U4ND1BD-3C IDT C1 NT4GT72U4ND2BD-3C IDT AMB+ 333MHz NT4GT72U4ND1BN-3C Intel D1 (3ns @ CL = 5) NT4GT72U8ND9BD-3C IDT AMB+ NT8GTT72U4ND4YD-3C NT8GTT72U4ND5YD-3C IDT D0 IDT AMB+ Power Gold 1.8V PC2-6400 DDR2-667 PC2-5300 DDR2-800 PC2-6400 256Mx72 IDT C1 NT8GTT72U4ND3YD-3C Leads 128Mx72 333MHz NT2GT72U8PD1BD-3C NT4GT72U8ND9BD-AC DDR2-800 Organization DDR2-667 DDR2-800 PC2-5300 PC2-6400 512Mx72 333MHz (3ns @ CL = 5) DDR2-667 PC2-5300 DDR2-667 PC2-5300 1Gx72 Note: FBDIMM module revision will change if AMB, PCB, or Heat spreader version changes. Ex: REV 1.3 03/2009 2 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BD-AC / NT2GT72U8PD0BD-AC / NT4GT72U4ND0BD-AC / NT4GT72U8ND9BD-AC NT1GT72U89D1BD-3C / NT2GT72U8PD1BD-3C / NT4GT72U4ND1BD-3C / NT8GTT72U4ND3YD-3C NT1GT72U89D1BN-3C / NT2GT72U8PD1BN-3C / NT4GT72U4ND1BN-3C / NT8GTT72U4ND4YD-3C NT1GT72U89D2BD-3C / NT2GT72U8PD2BD-3C / NT4GT72U4ND2BD-3C / NT8GTT72U4ND5YD-3C NT1GT72U89D6BD-AC / NT2GT72U8PD6BD-AC / NT4GT72U8ND9BD-3C DIMM Connector Pin Description Pin Name SCK Pin Description 1 System Clock Input, negative line 1 PN0-PN13 Primary Northbound Data, positive lines - Primary Northbound Data, negative lines PS0-PS9 Primary Southbound Data, positive lines - Primary Southbound Data, negative lines SN0-SN13 Secondary Northbound Data, positive lines - Secondary Northbound Data, negative lines SS0-SS9 Secondary Southbound Data, positive lines - Secondary Southbound Data, negative lines SCL Serial Presence Detect (SPD) Clock Input SDA SPD Data Input / Output S0-S1 VID0-VID1 Note System Clock Input, positive line SPD Address Inputs, also used to select the DIMM number in the AMB Voltage ID: These pins must be unconnected for DDR2-based Fully Buffered DIMMs VID0 is VDD value: OPEN=1.8V, GND=1.5V; VID1 is VCC value: OPEN=1.5V, GND=1.2V AMB reset signal RFU Reserved for Future Use VCC AMB Core Power and AMB Channel Interface Power (1.5V) VDD DRAM Power and AMB DRAM I/O Power (1.8V) VTT DRAM Address/Command/Clock Termination Power (VDD/2) VDDSPD VSS DNU/M_TEST 2 SPD Power (3.3V) Ground It provides an external connection on R/Cs A-D for testing the margin of Vref which is produced by a voltage divider on the module. It is not intended to be used in normal system operation and must not be connected (DNU) in a system. This test pin may have other features on future card designs and if it does, will be included in this specification at that time. 1 Note: 1. System Clock Signals SCK and SCK switch at one half the DRAM CK/ frequency 2. Eight pins reserved for forwarded clocks, eight pins reserved for future architecture flexibility REV 1.3 03/2009 3 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BD-AC / NT2GT72U8PD0BD-AC / NT4GT72U4ND0BD-AC / NT4GT72U8ND9BD-AC NT1GT72U89D1BD-3C / NT2GT72U8PD1BD-3C / NT4GT72U4ND1BD-3C / NT8GTT72U4ND3YD-3C NT1GT72U89D1BN-3C / NT2GT72U8PD1BN-3C / NT4GT72U4ND1BN-3C / NT8GTT72U4ND4YD-3C NT1GT72U89D2BD-3C / NT2GT72U8PD2BD-3C / NT4GT72U4ND2BD-3C / NT8GTT72U4ND5YD-3C NT1GT72U89D6BD-AC / NT2GT72U8PD6BD-AC / NT4GT72U8ND9BD-3C DDR2 240-pin FBDIMM Pinout Pin Front Side Pin Front Side Pin Front Side 1 VDD 42 VSS 82 PS4 2 VDD 43 VSS 83 3 VDD 44 RFU* 84 4 VSS 45 RFU* 85 5 VDD 46 VSS 6 VDD 47 7 VDD 48 8 VSS 49 9 VCC 50 10 VCC 51 11 VSS 52 12 VCC 53 13 VCC 54 14 VSS 55 Pin Back Side Pin Back Side SS4 121 VDD 162 VSS 202 VDD 163 VSS 203 VSS 123 VDD 164 RFU* 204 VSS 124 VSS 165 RFU* 205 VSS 86 RFU* 125 VDD 166 VSS 206 RFU* VSS 87 RFU* 126 VDD 167 VSS 207 RFU* PN12 88 VSS 127 VDD 168 SN12 208 VSS 89 VSS 128 VSS 169 VSS 90 PS9 129 VCC 170 PN6 91 VSS 209 VSS VSS 210 SS9 SN6 211 130 VCC 171 92 VSS 131 VSS 172 212 VSS VSS 93 PS5 132 VCC 173 VSS 213 SS5 PN7 94 133 VCC 174 SN7 214 134 VSS 175 95 VSS PS6 VTT 56 VSS 96 16 VID1 57 PN8 97 58 18 VSS 59 VSS 19 RFU** 60 PN9 20 RFU** 61 21 VSS 62 22 PN0 63 23 Back Side 122 15 17 Pin 215 VSS SS6 135 VTT 176 VSS 216 136 VID0 177 SN8 217 98 VSS 137 DNU/M_TEST 178 218 VSS 99 PS7 138 VSS 179 VSS 219 SS7 SN9 220 139 RFU** 180 101 VSS 140 RFU** 181 221 VSS VSS 102 PS8 141 VSS 182 VSS 222 SS8 PN10 103 142 SN0 183 SN10 223 64 100 104 VSS 143 184 224 VSS 24 VSS 65 VSS 105 RFU** 144 VSS 185 VSS 225 RFU** 25 PN1 66 PN11 106 RFU** 145 SN1 186 SN11 226 RFU** 107 VSS 146 108 VDD 147 VSS SN2 26 67 27 VSS 28 PN2 29 68 109 VDD 148 69 KEY VSS 110 VSS 149 PS0 111 VDD 150 112 VDD 151 113 VDD 152 30 VSS 70 31 PN3 71 32 72 VSS PS1 33 VSS 73 34 PN4 74 35 VSS 187 188 VSS KEY 227 VSS 228 SCK 229 189 VSS 230 VSS VSS 190 SS0 231 VDD SN3 191 232 VDD 192 VSS 233 VDD SS1 234 VSS 235 VDD 114 VSS 153 VSS 193 115 VDD 154 SN4 194 75 VSS 116 VDD 155 195 VSS 236 VDD 36 VSS 76 PS2 117 VTT 156 VSS 196 SS2 237 VTT 37 PN5 77 SN5 197 238 VDDSPD 198 VSS 239 SA0 SS3 240 SA1 38 118 SA2 157 78 VSS 119 SDA 158 PS3 120 SCL 159 VSS 199 160 SN13 200 39 VSS 79 40 PN13 80 41 81 VSS 161 201 Note: 1. RFU = Reserved Future Use 2. * These pin positions are reserved for forwarded clocks to be used in future module implementation 3. ** These pin positions are reserved for future architecture flexibility 4. The following signals are CRC bits and thus appear out of the normal sequence: PN12/ , SN12/ PS9/ , SS9/ REV 1.3 03/2009 VSS , PN13/ , SN13/ , 4 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BD-AC / NT2GT72U8PD0BD-AC / NT4GT72U4ND0BD-AC / NT4GT72U8ND9BD-AC NT1GT72U89D1BD-3C / NT2GT72U8PD1BD-3C / NT4GT72U4ND1BD-3C / NT8GTT72U4ND3YD-3C NT1GT72U89D1BN-3C / NT2GT72U8PD1BN-3C / NT4GT72U4ND1BN-3C / NT8GTT72U4ND4YD-3C NT1GT72U89D2BD-3C / NT2GT72U8PD2BD-3C / NT4GT72U4ND2BD-3C / NT8GTT72U4ND5YD-3C NT1GT72U89D6BD-AC / NT2GT72U8PD6BD-AC / NT4GT72U8ND9BD-3C Functional Block Diagram (1GB, 1Rank, 128Mx8 DDR2 SDRAMs) REV 1.3 03/2009 5 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BD-AC / NT2GT72U8PD0BD-AC / NT4GT72U4ND0BD-AC / NT4GT72U8ND9BD-AC NT1GT72U89D1BD-3C / NT2GT72U8PD1BD-3C / NT4GT72U4ND1BD-3C / NT8GTT72U4ND3YD-3C NT1GT72U89D1BN-3C / NT2GT72U8PD1BN-3C / NT4GT72U4ND1BN-3C / NT8GTT72U4ND4YD-3C NT1GT72U89D2BD-3C / NT2GT72U8PD2BD-3C / NT4GT72U4ND2BD-3C / NT8GTT72U4ND5YD-3C NT1GT72U89D6BD-AC / NT2GT72U8PD6BD-AC / NT4GT72U8ND9BD-3C Functional Block Diagram (2GB, 2Ranks, 128Mx8 DDR2 SDRAMs) # # # 1 # 3 # 3 # 2 7% # # # # #2 #3 #5 #4 # % # # 7% # # $%& $%& $%& $%& 2 $%& 3 $%& 5 $%& 4 $%& % # # $%& $%& $%& $%& 2 $%& 3 $%& 5 $%& 4 $%& 7% # # #2 #22 #23 #25 #24 #2 #26 #21 1 # % # # # 3 2 3 5 4 7% # % # $%& $%& $%& $%& 2 $%& 3 $%& 5 $%& 4 $%& # # # # # # # # # # 2 # 5 # 5 # 3 # # 7% # #6 #1 # # # # 2 # 3 # 5 $%& $%& $%& $%& $%& $%& $%& $%& % # # 7% # # % # # 7% # # #3 #3 #3 #32 #33 #35 #34 #3 $%& $%& $%& $%& 2 $%& 3 $%& 5 $%& 4 $%& 2 3 5 4 # $%& $%& $%& $%& $%& $%& $%& $%& % # # # 5 2 3 5 4 7% # % # $%& $%& $%& $%& 2 $%& 3 $%& 5 $%& 4 $%& 3 # 4 # 4 # 5 # # 7% # # # # # # # # # $%& $%& $%& $%& $%& $%& $%& $%& 4 $%& $%& $%& $%& $%& $%& $%& $%& 6 1 2 % # # 7% # # % # # 7% # # #36 #31 #5 #5 #5 #52 #53 #55 $%& $%& $%& $%& 2 $%& 3 $%& 5 $%& 4 $%& 2 3 5 4 # 2 $%& $%& $%& $%& $%& $%& $%& $%& % # # # 4 2 3 5 4 7% # % # $%& $%& $%& $%& 2 $%& 3 $%& 5 $%& 4 $%& 5 # # # 4 # 2 # 7% # # 3 # 5 # 4 # # 6 # 1 #2 #2 $%& $%& $%& $%& $%& $%& $%& $%& % # 7% # # # 2 2 3 5 4 % # # 7% # # #54 #5 #56 #51 #4 #4 #4 #42 $%& $%& $%& $%& 2 $%& 3 $%& 5 $%& 4 $%& $%& $%& $%& $%& $%& $%& $%& $%& % # # # 7% # % # $%& $%& $%& $%& 2 $%& 3 $%& 5 $%& 4 $%& 2 3 5 4 4 # 6 # 6 6% # 2 2 1 1 # # # 1 1 9 9 8% 8 : -- ! REV 1.3 03/2009 2 3 5 4 8 8 %+ -%+ 7% # # : 6; 6; 9 8 : : 1 ; : 1 ; 8 9 8 & 9& : ; : ; 5: ; : ; : ; : ; #42 # # 6 8% 2 2 $%& $%& $%& $%& $%& $%& $%& $%& 2 3 5 4 % # # 6 # 7% # % # $%& $%& $%& $%& 2 $%& 3 $%& 5 $%& 4 $%& ; %+ +0 " # $%& ' ( ) * +, ( -' , *) " , ' .,) + + . / +, -%+ + %+ +0 -% 6 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BD-AC / NT2GT72U8PD0BD-AC / NT4GT72U4ND0BD-AC / NT4GT72U8ND9BD-AC NT1GT72U89D1BD-3C / NT2GT72U8PD1BD-3C / NT4GT72U4ND1BD-3C / NT8GTT72U4ND3YD-3C NT1GT72U89D1BN-3C / NT2GT72U8PD1BN-3C / NT4GT72U4ND1BN-3C / NT8GTT72U4ND4YD-3C NT1GT72U89D2BD-3C / NT2GT72U8PD2BD-3C / NT4GT72U4ND2BD-3C / NT8GTT72U4ND5YD-3C NT1GT72U89D6BD-AC / NT2GT72U8PD6BD-AC / NT4GT72U8ND9BD-3C Functional Block Diagram (4GB, 2Ranks, 256Mx4 DDR2 SDRAMs) REV 1.3 03/2009 7 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BD-AC / NT2GT72U8PD0BD-AC / NT4GT72U4ND0BD-AC / NT4GT72U8ND9BD-AC NT1GT72U89D1BD-3C / NT2GT72U8PD1BD-3C / NT4GT72U4ND1BD-3C / NT8GTT72U4ND3YD-3C NT1GT72U89D1BN-3C / NT2GT72U8PD1BN-3C / NT4GT72U4ND1BN-3C / NT8GTT72U4ND4YD-3C NT1GT72U89D2BD-3C / NT2GT72U8PD2BD-3C / NT4GT72U4ND2BD-3C / NT8GTT72U4ND5YD-3C NT1GT72U89D6BD-AC / NT2GT72U8PD6BD-AC / NT4GT72U8ND9BD-3C Functional Block Diagram (Part 1 of 2) (4GB REV 1.3 03/2009 4Rank, 128Mx8 DDR2 SDRAMs) 8 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BD-AC / NT2GT72U8PD0BD-AC / NT4GT72U4ND0BD-AC / NT4GT72U8ND9BD-AC NT1GT72U89D1BD-3C / NT2GT72U8PD1BD-3C / NT4GT72U4ND1BD-3C / NT8GTT72U4ND3YD-3C NT1GT72U89D1BN-3C / NT2GT72U8PD1BN-3C / NT4GT72U4ND1BN-3C / NT8GTT72U4ND4YD-3C NT1GT72U89D2BD-3C / NT2GT72U8PD2BD-3C / NT4GT72U4ND2BD-3C / NT8GTT72U4ND5YD-3C NT1GT72U89D6BD-AC / NT2GT72U8PD6BD-AC / NT4GT72U8ND9BD-3C Functional Block Diagram (Part 2 of 2) (4GB REV 1.3 03/2009 4Rank, 128Mx8 DDR2 SDRAMs) 9 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BD-AC / NT2GT72U8PD0BD-AC / NT4GT72U4ND0BD-AC / NT4GT72U8ND9BD-AC NT1GT72U89D1BD-3C / NT2GT72U8PD1BD-3C / NT4GT72U4ND1BD-3C / NT8GTT72U4ND3YD-3C NT1GT72U89D1BN-3C / NT2GT72U8PD1BN-3C / NT4GT72U4ND1BN-3C / NT8GTT72U4ND4YD-3C NT1GT72U89D2BD-3C / NT2GT72U8PD2BD-3C / NT4GT72U4ND2BD-3C / NT8GTT72U4ND5YD-3C NT1GT72U89D6BD-AC / NT2GT72U8PD6BD-AC / NT4GT72U8ND9BD-3C Functional Block Diagram (8GB, 4Ranks, 512Mx4 DDR2 SDRAMs) 2 # # 1 # # 1 # # # #2 # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # # # # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # # # $%& $%& $%& $%& 2 6 24 # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # # # 53 # # $%& $%& $%& $%& 2 # #3 #5 #4 # # $%& $%& $%& $%& 2 # # # 2 # 3 # 5 # $%& $%& $%& $%& 2 # # # # # 2 # $%& $%& $%& $%& 2 # # 6 # 1 #2 #2 # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # # # 1 # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # # # # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # # # 35 # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # # # 42 # # # #6 #1 # # 1 # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # 2 55 6 34 43 # # # # # 4 # # 6 # 1 $%& $%& $%& $%& 2 26 $%& $%& $%& $%& 2 54 # 2 1 $%& $%& $%& $%& 2 3 45 # # 2 # # 3 # 5 # 4 # # $%& $%& $%& $%& 2 # 2 21 # $%& $%& $%& $%& 2 # 5 # 3 # # 3 # #2 #22 #23 #25 # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # # # 3 # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # 3 # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # # # # 5 # 5 #3 #3 #3 #32 5 2 3 3 # 3 #33 #35 #34 #3 # 4 # # 4 # #36 #31 #5 #5 $%& $%& $%& $%& 2 4 3 $%& $%& $%& $%& 2 3 # # # # #54 #5 #56 #51 # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # 5 32 # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # 4 # 6 # # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # 36 44 2 3 # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # # $%& $%& $%& $%& 2 # 2 2 31 5 4 46 5 5 #5 #52 #53 #55 4 # $%& $%& $%& $%& 2 2 # 51 2 2 #24 #2 #26 #21 56 $%& $%& $%& $%& 2 5 22 5 41 4 4 #4 #4 #4 #42 $%& $%& $%& $%& 2 3 5 4 # $%& $%& $%& $%& 2 4 23 5 $%& $%& $%& $%& 2 # # 6 # 2 6 2 2 1 1 # # # #42 # # 6 8% REV 1.3 03/2009 8 4 1 1 4 2 2 -- : ; 9 8 9 8 : ; : 6 25; 9 8 9 8 : 6 25; & 9& : ; : ; 5: ; : ; : ; : ; 8% 8 : 33 ; %+ # -%+ 25 52 # $%& $%& $%& $%& 2 # %+ +0 25 25 25 ! " # " , 2" , $%& ' ( )* +, ( - ' , ** ' .,) + + . / +, -%+ / < .,) + + . / +, + +0 -%+ 10 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BD-AC / NT2GT72U8PD0BD-AC / NT4GT72U4ND0BD-AC / NT4GT72U8ND9BD-AC NT1GT72U89D1BD-3C / NT2GT72U8PD1BD-3C / NT4GT72U4ND1BD-3C / NT8GTT72U4ND3YD-3C NT1GT72U89D1BN-3C / NT2GT72U8PD1BN-3C / NT4GT72U4ND1BN-3C / NT8GTT72U4ND4YD-3C NT1GT72U89D2BD-3C / NT2GT72U8PD2BD-3C / NT4GT72U4ND2BD-3C / NT8GTT72U4ND5YD-3C NT1GT72U89D6BD-AC / NT2GT72U8PD6BD-AC / NT4GT72U8ND9BD-3C Absolute Maximum DC Ratings Symbol Min Typical DRAM VDD / VDDQ, AMB VDDQ 1.7 AMB VCC / VCCFBD 1.46 DRAM Interface VTT Max Units 1.8 1.9 V 1.5 1.54 V 0.48 x VDD 0.5 x VDD 0.52 x VDD V 3.0 3.3 3.6 V VDDSPD Notes 1 Note: 1. Estimate Operating Temperature Range Symbol Parameter Min Max Units Notes 1 Tcase DRAM Component Operating Temperature (Ambient) 0 +95 C Tcase AMB Component Operating Temperature (Ambient) 0 +110 C Note: 1. Within the DRAM Temperature range all DRAM will be support. Electrical Characteristics and Operating Conditions Symbol VDD, VDDQ Parameter Supply Voltage, I/O Supply Voltage Min Max Units Notes 1.7 1.9 V 1 VIH (DC) Input High (Logic1) Voltage VREF + 0.125 VDDQ + 0.3 V 1 VIL (DC) Input Low (Logic0) Voltage -0.3 VREF - 0.125 V 1 VIH (AC) Input High (Logic1) Voltage VREF + 0.2 - V VIL (AC) Input Low (Logic0) Voltage - VREF - 0.2 V VID (AC) AC differential input voltage 0.5 VDDQ + 0.6 VIX (AC) AC Differential cross point input Voltage 0.5* VDDQ - 0.175 0.5* VDDQ + 0.175 V AC Differential cross point output Voltage 0.5* VDDQ - 0.125 0.5* VDDQ + 0.125 V VOX (AC) VSS, VSSQ VREF VTT Supply Voltage, I/O Supply Voltage V 0 0 V I/O Reference Voltage 0.49 x VDDQ 0.51 x VDDQ V 1, 2 I/O Termination Voltage (System) VREF - 0.04 VREF + 0.04 V 1, 3 Note: 1. Inputs are not recognized as valid until VREF stabilizes. 2. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. 3. VTT is not applied directly to the DIMM. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. REV 1.3 03/2009 11 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BD-AC / NT2GT72U8PD0BD-AC / NT4GT72U4ND0BD-AC / NT4GT72U8ND9BD-AC NT1GT72U89D1BD-3C / NT2GT72U8PD1BD-3C / NT4GT72U4ND1BD-3C / NT8GTT72U4ND3YD-3C NT1GT72U89D1BN-3C / NT2GT72U8PD1BN-3C / NT4GT72U4ND1BN-3C / NT8GTT72U4ND4YD-3C NT1GT72U89D2BD-3C / NT2GT72U8PD2BD-3C / NT4GT72U4ND2BD-3C / NT8GTT72U4ND5YD-3C NT1GT72U89D6BD-AC / NT2GT72U8PD6BD-AC / NT4GT72U8ND9BD-3C Serial Presence Detect (Part 1 of 2) NT1GT72U89xxxx-xx, 1 RANK Fully Buffered DDR2 SDRAM DIMM Based on 128Mx8, 8Banks, 8K Refresh, DDR2 SDRAMs with SPD Byte Serial PD Data Entry (Hexadecimal) Description D0BD-AC D1BD-3C D1BN-3C D2BD-3C D6BD-3C 0 Number of Serial PD Bytes in CRC 92 92 92 92 92 1 SPD Revision 11 11 11 11 11 2 Key Byte / DRAM Device Type 09 09 09 09 09 3 Voltage Levels of this Assembly 12 12 12 12 12 4 SDRAM Addressing 45 45 45 45 45 5 Module Physical Attributes 24 24 24 24 24 6 Modules Type 07 07 07 07 07 7 Module Organization 09 09 09 09 09 8 Fine Timebase Dividend and Divisor 52 52 52 52 52 9 Medium Timebase Dividend 01 01 01 01 01 10 Medium Timebase Divisor 04 04 04 04 04 11 SDRAM Minimum Cycle Time (tCKmin) 0A 0C 0C 0C 0A 12 SDRAM Maximum Cycle Time (tCKmax) 20 20 20 20 20 13 SDRAM 43 43 43 43 43 14 SDRAM Minimum CAS Latency Time (tAA) 32 3C 3C 3C 32 15 SDRAM Write Recovery Times Supported 42 42 42 42 42 16 SDRAM Write Recovery Time (tWR) 3C 3C 3C 3C 3C 17 SDRAM Write Latencies Supported 42 42 42 42 42 18 SDRAM Additive Latencies Supported 60 60 60 60 60 19 SDRAM Minimum 32 3C 3C 3C 32 20 SDRAM Minimum Row Active to Row Active Delay (tRRD) 1E 1E 1E 1E 1E 21 SDRAM Minimum Row Precharge Time (tRP) 32 3C 3C 3C 32 22 SDRAM Upper Nibbles for tRAS and tRC 00 00 00 00 00 23 SDRAM Minimum Active to Precharge Time (tRAS) B4 B4 B4 B4 B4 24 SDRAM Minimum Auto-Refresh to Active/Auto-Refresh Time (tRC) E6 F0 F0 F0 E6 25~26 SDRAM Minimum Auto-Refresh to Active/Auto-Refresh Command Period (tRFC) FE01 FE01 FE01 FE01 FE01 27 SDRAM Internal Write to Read Command Delay (tWTR) 1E 1E 1E 1E 1E 28 SDRAM Internal Read to Precharge Command Delay (tRTP) 1E 1E 1E 1E 1E 29 SDRAM Burst Lengths Supported 03 03 03 03 03 30 SDRAM Terminations Supported 07 07 07 07 07 31 SDRAM Drivers Supported 01 01 01 01 01 32 SDRAM Average Refresh Interval (tREFI)/Double Refresh mode bit/High Temperature self-refresh rate support indication C2 C2 C2 C2 C2 33 Tcasemax 00 00 00 00 00 34 Thermal resistance of SDRAM device package from top (case0 to ambient (Psi T-A SDRAM) 00 00 00 00 00 Latencies Supported to Delay (tRCD) Serial Presence Detect (Part 2 of 2) NT1GT72U89xxxx-xx, 1 RANK Fully Buffered DDR2 SDRAM DIMM REV 1.3 03/2009 12 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BD-AC / NT2GT72U8PD0BD-AC / NT4GT72U4ND0BD-AC / NT4GT72U8ND9BD-AC NT1GT72U89D1BD-3C / NT2GT72U8PD1BD-3C / NT4GT72U4ND1BD-3C / NT8GTT72U4ND3YD-3C NT1GT72U89D1BN-3C / NT2GT72U8PD1BN-3C / NT4GT72U4ND1BN-3C / NT8GTT72U4ND4YD-3C NT1GT72U89D2BD-3C / NT2GT72U8PD2BD-3C / NT4GT72U4ND2BD-3C / NT8GTT72U4ND5YD-3C NT1GT72U89D6BD-AC / NT2GT72U8PD6BD-AC / NT4GT72U8ND9BD-3C Based on 128Mx8, 8Banks, 8K Refresh, DDR2 SDRAMs with SPD Byte Serial PD Data Entry (Hexadecimal) Description 35-41 Delta Temperature 42-80 Reserved 81~82 FB-DIMM Channel Protocols Supported D0BD-AC D1BD-3C D1BN-3C D2BD-3C D6BD-3C -- -- -- -- -- -- -- -- -- -- 0200 0200 0200 0200 0200 83 Additional Back to Back Access Turnaround Time 10 10 10 10 10 84 AMB Read Access Time for DDR2-800 36 36 56 4A 36 85 AMB Read Access Time for DDR2-667 34 34 40 46 34 86 AMB Read Access Time for DDR2-533 32 32 36 38 32 87 Thermal Resistance of AMB Package from top (case) to ambient (Psi T-A SDRAM) at still air condition. 2A 2A 30 2A 2A 88 AMB DT Idle_0 5D 56 60 33 5D 89 AMB DT Idle_1 71 6B 7A 40 71 90 AMB DT Idle_2 65 5C 6E 37 65 91 AMB DT Active_1 9B 91 A1 57 9B 92 AMB DT Active _2 7F 76 7F 46 7F 93 AMB DT L0s 00 00 00 00 00 -- -- -- -- -- 115~116 AMB Manufacturer ID Code 94~114 Reserved 7FB3 7FB3 8089 7FB3 7FB3 117-118 Module ID: Module Manufacture's JEDEC ID Code 830B 830B 830B 830B 830B 119-125 Reserved for Module ID -- -- -- -- -- 126-127 Cyclical Redundancy Code -- -- -- -- -- 128-145 Module Part Number -- -- -- -- -- 146-147 Module Revision Code -- -- -- -- -- 148-149 SDRAM Manufacture's JEDEC ID Code 830B 830B 830B 830B 830B 150-255 Reserved -- -- -- -- -- REV 1.3 03/2009 13 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BD-AC / NT2GT72U8PD0BD-AC / NT4GT72U4ND0BD-AC / NT4GT72U8ND9BD-AC NT1GT72U89D1BD-3C / NT2GT72U8PD1BD-3C / NT4GT72U4ND1BD-3C / NT8GTT72U4ND3YD-3C NT1GT72U89D1BN-3C / NT2GT72U8PD1BN-3C / NT4GT72U4ND1BN-3C / NT8GTT72U4ND4YD-3C NT1GT72U89D2BD-3C / NT2GT72U8PD2BD-3C / NT4GT72U4ND2BD-3C / NT8GTT72U4ND5YD-3C NT1GT72U89D6BD-AC / NT2GT72U8PD6BD-AC / NT4GT72U8ND9BD-3C Serial Presence Detect (Part 1 of 2) NT2GT72U8Pxxxx-xx, 2 RANK Fully Buffered DDR2 SDRAM DIMM Based on 128Mx8, 8Banks, 8K Refresh, DDR2 SDRAMs with SPD Byte Serial PD Data Entry (Hexadecimal) Description D0BD-AC D1BD-3C D1BN-3C D2BD-3C D6BD-3C 0 Number of Serial PD Bytes in CRC 92 92 92 92 92 1 SPD Revision 11 11 11 11 11 2 Key Byte / DRAM Device Type 09 09 09 09 09 3 Voltage Levels of this Assembly 12 12 12 12 12 4 SDRAM Addressing 45 45 45 45 45 5 Module Physical Attributes 24 24 24 24 24 6 Modules Type 07 07 07 07 07 7 Module Organization 11 11 11 11 11 8 Fine Timebase Dividend and Divisor 52 52 52 52 52 9 Medium Timebase Dividend 01 01 01 01 01 10 Medium Timebase Divisor 04 04 04 04 04 11 SDRAM Minimum Cycle Time (tCKmin) 0A 0C 0C 0C 0A 12 SDRAM Maximum Cycle Time (tCKmax) 20 20 20 20 20 13 SDRAM 43 43 43 43 43 14 SDRAM Minimum CAS Latency Time (tAA) 32 3C 3C 3C 32 15 SDRAM Write Recovery Times Supported 42 42 42 42 42 16 SDRAM Write Recovery Time (tWR) 3C 3C 3C 3C 3C 17 SDRAM Write Latencies Supported 42 42 42 42 42 18 SDRAM Additive Latencies Supported 60 60 60 60 60 19 SDRAM Minimum 32 3C 3C 3C 32 20 SDRAM Minimum Row Active to Row Active Delay (tRRD) 1E 1E 1E 1E 1E 21 SDRAM Minimum Row Precharge Time (tRP) 32 3C 3C 3C 32 22 SDRAM Upper Nibbles for tRAS and tRC 00 00 00 00 00 23 SDRAM Minimum Active to Precharge Time (tRAS) B4 B4 B4 B4 B4 24 SDRAM Minimum Auto-Refresh to Active/Auto-Refresh Time (tRC) E6 F0 F0 F0 E6 25~26 SDRAM Minimum Auto-Refresh to Active/Auto-Refresh Command Period (tRFC) FE01 FE01 FE01 FE01 FE01 27 SDRAM Internal Write to Read Command Delay (tWTR) 1E 1E 1E 1E 1E 28 SDRAM Internal Read to Precharge Command Delay (tRTP) 1E 1E 1E 1E 1E 29 SDRAM Burst Lengths Supported 03 03 03 03 03 30 SDRAM Terminations Supported 07 07 07 07 07 31 SDRAM Drivers Supported 01 01 01 01 01 32 SDRAM Average Refresh Interval (tREFI)/Double Refresh mode bit/High Temperature self-refresh rate support indication C2 C2 C2 C2 C2 33 Tcasemax 00 00 00 00 00 34 Thermal resistance of SDRAM device package from top (case0 to ambient (Psi T-A SDRAM) 00 00 00 00 00 REV 1.3 03/2009 Latencies Supported to Delay (tRCD) 14 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BD-AC / NT2GT72U8PD0BD-AC / NT4GT72U4ND0BD-AC / NT4GT72U8ND9BD-AC NT1GT72U89D1BD-3C / NT2GT72U8PD1BD-3C / NT4GT72U4ND1BD-3C / NT8GTT72U4ND3YD-3C NT1GT72U89D1BN-3C / NT2GT72U8PD1BN-3C / NT4GT72U4ND1BN-3C / NT8GTT72U4ND4YD-3C NT1GT72U89D2BD-3C / NT2GT72U8PD2BD-3C / NT4GT72U4ND2BD-3C / NT8GTT72U4ND5YD-3C NT1GT72U89D6BD-AC / NT2GT72U8PD6BD-AC / NT4GT72U8ND9BD-3C Serial Presence Detect (Part 2 of 2) NT2GT72U8Pxxxx-xx, 2 RANK Fully Buffered DDR2 SDRAM DIMM Based on 128Mx8, 8Banks, 8K Refresh, DDR2 SDRAMs with SPD Byte Serial PD Data Entry (Hexadecimal) Description D0BD-AC D1BD-3C D1BN-3C D2BD-3C D6BD-3C 35-41 Delta Temperature -- -- -- -- -- 42-80 Reserved -- -- -- -- -- 81~82 FB-DIMM Channel Protocols Supported 0200 0200 0200 0200 0200 83 Additional Back to Back Access Turnaround Time 10 10 10 10 10 84 AMB Read Access Time for DDR2-800 36 36 56 4A 36 85 AMB Read Access Time for DDR2-667 34 34 40 46 34 86 AMB Read Access Time for DDR2-533 32 32 36 38 32 87 Thermal Resistance of AMB Package from top (case) to ambient (Psi T-A SDRAM) at still air condition. 2A 2A 30 2A 2A 88 AMB DT Idle_0 5D 56 60 33 5D 89 AMB DT Idle_1 71 6B 7A 40 71 90 AMB DT Idle_2 65 5C 6E 37 65 91 AMB DT Active_1 9B 91 A1 57 9B 92 AMB DT Active _2 7F 76 7F 46 7F 93 AMB DT L0s 00 00 00 00 00 Reserved -- -- -- -- -- 115~116 AMB Manufacturer ID Code 7FB3 7FB3 8089 7FB3 7FB3 117-118 Module ID: Module Manufacture's JEDEC ID Code 830B 830B 830B 830B 830B 119-125 Reserved for Module ID -- -- -- -- -- 126-127 Cyclical Redundancy Code -- -- -- -- -- 128-145 Module Part Number -- -- -- -- -- 146-147 Module Revision Code 148-149 SDRAM Manufacture's JEDEC ID Code 150-255 Reserved 94~114 REV 1.3 03/2009 -- -- -- -- -- 830B 830B 830B 830B 830B -- -- -- -- -- 15 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BD-AC / NT2GT72U8PD0BD-AC / NT4GT72U4ND0BD-AC / NT4GT72U8ND9BD-AC NT1GT72U89D1BD-3C / NT2GT72U8PD1BD-3C / NT4GT72U4ND1BD-3C / NT8GTT72U4ND3YD-3C NT1GT72U89D1BN-3C / NT2GT72U8PD1BN-3C / NT4GT72U4ND1BN-3C / NT8GTT72U4ND4YD-3C NT1GT72U89D2BD-3C / NT2GT72U8PD2BD-3C / NT4GT72U4ND2BD-3C / NT8GTT72U4ND5YD-3C NT1GT72U89D6BD-AC / NT2GT72U8PD6BD-AC / NT4GT72U8ND9BD-3C Serial Presence Detect (Part 1 of 2) NT4GT72U4Nxxxx-xx, 2 RANK Fully Buffered DDR2 SDRAM DIMM Based on 256Mx4, 8Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte Serial PD Data Entry (Hexadecimal) Description D0BD-AC D1BD-3C D1BN-3C D2BD-3C 0 Number of Serial PD Bytes in CRC 92 92 92 92 1 SPD Revision 11 11 11 11 2 Key Byte / DRAM Device Type 09 09 09 09 3 Voltage Levels of this Assembly 12 12 12 12 4 SDRAM Addressing 49 49 49 49 5 Module Physical Attributes 24 24 24 24 6 Modules Type 07 07 07 07 7 Module Organization 10 10 10 10 8 Fine Timebase Dividend and Divisor 52 52 52 52 9 Medium Timebase Dividend 01 01 01 01 10 Medium Timebase Divisor 04 04 04 04 11 SDRAM Minimum Cycle Time (tCKmin) 0A 0C 0C 0C 12 SDRAM Maximum Cycle Time (tCKmax) 20 20 20 20 13 SDRAM 43 43 43 43 14 SDRAM Minimum CAS Latency Time (tAA) 3C 3C 3C 3C 15 SDRAM Write Recovery Times Supported 42 42 42 42 16 SDRAM Write Recovery Time (tWR) 3C 3C 3C 3C 17 SDRAM Write Latencies Supported 42 42 42 42 18 SDRAM Additive Latencies Supported 60 60 60 60 19 SDRAM Minimum 3C 3C 3C 3C 20 SDRAM Minimum Row Active to Row Active Delay (tRRD) 1E 1E 1E 1E 21 SDRAM Minimum Row Precharge Time (tRP) 3C 3C 3C 3C 22 SDRAM Upper Nibbles for tRAS and tRC 00 00 00 00 23 SDRAM Minimum Active to Precharge Time (tRAS) B4 B4 B4 B4 24 SDRAM Minimum Auto-Refresh to Active/Auto-Refresh Time (tRC) F0 F0 F0 F0 25~26 SDRAM Minimum Auto-Refresh to Active/Auto-Refresh Command Period (tRFC) FE01 FE01 FE01 FE01 27 SDRAM Internal Write to Read Command Delay (tWTR) 1E 1E 1E 1E 28 SDRAM Internal Read to Precharge Command Delay (tRTP) 1E 1E 1E 1E 29 SDRAM Burst Lengths Supported 03 03 03 03 30 SDRAM Terminations Supported 07 07 07 07 31 SDRAM Drivers Supported 01 01 01 01 32 SDRAM Average Refresh Interval (tREFI)/Double Refresh mode bit/High Temperature self-refresh rate support indication C2 C2 C2 C2 33 Tcasemax 00 00 00 00 34 Thermal resistance of SDRAM device package from top (case0 to ambient (Psi T-A SDRAM) 00 00 00 00 REV 1.3 03/2009 Latencies Supported to Delay (tRCD) 16 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BD-AC / NT2GT72U8PD0BD-AC / NT4GT72U4ND0BD-AC / NT4GT72U8ND9BD-AC NT1GT72U89D1BD-3C / NT2GT72U8PD1BD-3C / NT4GT72U4ND1BD-3C / NT8GTT72U4ND3YD-3C NT1GT72U89D1BN-3C / NT2GT72U8PD1BN-3C / NT4GT72U4ND1BN-3C / NT8GTT72U4ND4YD-3C NT1GT72U89D2BD-3C / NT2GT72U8PD2BD-3C / NT4GT72U4ND2BD-3C / NT8GTT72U4ND5YD-3C NT1GT72U89D6BD-AC / NT2GT72U8PD6BD-AC / NT4GT72U8ND9BD-3C Serial Presence Detect (Part 2 of 2) NT4GT72U4Nxxxx-xx, 2 RANK Fully Buffered DDR2 SDRAM DIMM Based on 256Mx4, 8Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte Serial PD Data Entry (Hexadecimal) Description D0BD-AC D1BD-3C D1BN-3C D2BD-3C 35-41 Delta Temperature -- -- -- -- 42-80 Reserved -- -- -- -- 81~82 FB-DIMM Channel Protocols Supported 0200 0200 0200 0200 83 Additional Back to Back Access Turnaround Time 10 10 10 10 84 AMB Read Access Time for DDR2-800 36 36 56 4A 85 AMB Read Access Time for DDR2-667 34 34 40 46 86 AMB Read Access Time for DDR2-533 32 32 36 38 87 Thermal Resistance of AMB Package from top (case) to ambient (Psi T-A SDRAM) at still air condition. 2A 2A 30 2A 88 AMB DT Idle_0 64 56 60 38 89 AMB DT Idle_1 7B 6B 7A 45 90 AMB DT Idle_2 65 5C 6E 37 91 AMB DT Active_1 A3 91 A1 5D 92 AMB DT Active _2 87 76 7F 4C 93 AMB DT L0s 00 00 00 00 Reserved -- -- -- -- 115~116 AMB Manufacturer ID Code 7FB3 7FB3 8089 7FB3 117-118 Module ID: Module Manufacture's JEDEC ID Code 830B 830B 830B 830B 119-125 Reserved for Module ID -- -- -- -- 126-127 Cyclical Redundancy Code -- -- -- -- 128-145 Module Part Number -- -- -- -- 146-147 Module Revision Code 148-149 SDRAM Manufacture's JEDEC ID Code 150-255 Reserved 94~114 REV 1.3 03/2009 -- -- -- -- 830B 830B 830B 830B -- -- -- -- 17 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BD-AC / NT2GT72U8PD0BD-AC / NT4GT72U4ND0BD-AC / NT4GT72U8ND9BD-AC NT1GT72U89D1BD-3C / NT2GT72U8PD1BD-3C / NT4GT72U4ND1BD-3C / NT8GTT72U4ND3YD-3C NT1GT72U89D1BN-3C / NT2GT72U8PD1BN-3C / NT4GT72U4ND1BN-3C / NT8GTT72U4ND4YD-3C NT1GT72U89D2BD-3C / NT2GT72U8PD2BD-3C / NT4GT72U4ND2BD-3C / NT8GTT72U4ND5YD-3C NT1GT72U89D6BD-AC / NT2GT72U8PD6BD-AC / NT4GT72U8ND9BD-3C Serial Presence Detect (Part 1 of 2) NT4GTT72U8Nxxxx-xx, 4 RANK Fully Buffered DDR2 SDRAM DIMM Based on 128Mx8, 8Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte Serial PD Data Entry (Hexadecimal) Description D9BD-3C D9BD-AC 0 Number of Serial PD Bytes in CRC 92 92 1 SPD Revision 11 11 2 Key Byte / DRAM Device Type 09 09 3 Voltage Levels of this Assembly 12 12 4 SDRAM Addressing 45 45 5 Module Physical Attributes 24 24 6 Modules Type 07 07 7 Module Organization 21 21 8 Fine Timebase Dividend and Divisor 52 52 9 Medium Timebase Dividend 01 01 10 Medium Timebase Divisor 04 04 11 SDRAM Minimum Cycle Time (tCKmin) 0C 0A 12 SDRAM Maximum Cycle Time (tCKmax) 20 20 13 SDRAM 43 43 14 SDRAM Minimum CAS Latency Time (tAA) 3C 3C 15 SDRAM Write Recovery Times Supported 42 42 16 SDRAM Write Recovery Time (tWR) 3C 3C 17 SDRAM Write Latencies Supported 42 42 18 SDRAM Additive Latencies Supported 60 60 19 SDRAM Minimum 3C 32 20 SDRAM Minimum Row Active to Row Active Delay (tRRD) 1E 1E 21 SDRAM Minimum Row Precharge Time (tRP) 3C 32 22 SDRAM Upper Nibbles for tRAS and tRC 00 00 23 SDRAM Minimum Active to Precharge Time (tRAS) B4 B4 24 SDRAM Minimum Auto-Refresh to Active/Auto-Refresh Time (tRC) F0 E6 25~26 SDRAM Minimum Auto-Refresh to Active/Auto-Refresh Command Period (tRFC) FE01 FE01 27 SDRAM Internal Write to Read Command Delay (tWTR) 1E 1E 28 SDRAM Internal Read to Precharge Command Delay (tRTP) 1E 1E 29 SDRAM Burst Lengths Supported 03 03 30 SDRAM Terminations Supported 07 07 31 SDRAM Drivers Supported 01 01 32 SDRAM Average Refresh Interval (tREFI)/Double Refresh mode bit/High Temperature self-refresh rate support indication C2 C2 33 Tcasemax 00 00 34 Thermal resistance of SDRAM device package from top (case0 to ambient (Psi T-A SDRAM) 00 00 REV 1.3 03/2009 Latencies Supported to Delay (tRCD) 18 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BD-AC / NT2GT72U8PD0BD-AC / NT4GT72U4ND0BD-AC / NT4GT72U8ND9BD-AC NT1GT72U89D1BD-3C / NT2GT72U8PD1BD-3C / NT4GT72U4ND1BD-3C / NT8GTT72U4ND3YD-3C NT1GT72U89D1BN-3C / NT2GT72U8PD1BN-3C / NT4GT72U4ND1BN-3C / NT8GTT72U4ND4YD-3C NT1GT72U89D2BD-3C / NT2GT72U8PD2BD-3C / NT4GT72U4ND2BD-3C / NT8GTT72U4ND5YD-3C NT1GT72U89D6BD-AC / NT2GT72U8PD6BD-AC / NT4GT72U8ND9BD-3C Serial Presence Detect (Part 2 of 2) NT4GTT72U8Nxxxx-xx, 4 RANK Fully Buffered DDR2 SDRAM DIMM Based on 128Mx8, 8Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte Serial PD Data Entry (Hexadecimal) Description D9BD-3C D9BD-AC 35-41 Delta Temperature -- -- 42-80 Reserved -- -- 81~82 FB-DIMM Channel Protocols Supported 0200 0200 83 Additional Back to Back Access Turnaround Time 10 10 84 AMB Read Access Time for DDR2-800 4A 4A 85 AMB Read Access Time for DDR2-667 46 46 86 AMB Read Access Time for DDR2-533 38 38 87 Thermal Resistance of AMB Package from top (case) to ambient (Psi T-A SDRAM) at still air condition. 2A 2A 88 AMB DT Idle_0 3A 3E 89 AMB DT Idle_1 47 4B 90 AMB DT Idle_2 3A 40 91 AMB DT Active_1 5F 64 92 AMB DT Active _2 4F 53 93 AMB DT L0s 00 00 Reserved -- -- 115~116 AMB Manufacturer ID Code 7FB3 7FB3 117-118 Module ID: Module Manufacture's JEDEC ID Code 830B 830B 119-125 Reserved for Module ID -- -- 126-127 Cyclical Redundancy Code -- -- 128-145 Module Part Number -- -- 146-147 Module Revision Code 148-149 SDRAM Manufacture's JEDEC ID Code 150-255 Reserved 94~114 REV 1.3 03/2009 -- -- 830B 830B -- -- 19 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BD-AC / NT2GT72U8PD0BD-AC / NT4GT72U4ND0BD-AC / NT4GT72U8ND9BD-AC NT1GT72U89D1BD-3C / NT2GT72U8PD1BD-3C / NT4GT72U4ND1BD-3C / NT8GTT72U4ND3YD-3C NT1GT72U89D1BN-3C / NT2GT72U8PD1BN-3C / NT4GT72U4ND1BN-3C / NT8GTT72U4ND4YD-3C NT1GT72U89D2BD-3C / NT2GT72U8PD2BD-3C / NT4GT72U4ND2BD-3C / NT8GTT72U4ND5YD-3C NT1GT72U89D6BD-AC / NT2GT72U8PD6BD-AC / NT4GT72U8ND9BD-3C Serial Presence Detect (Part 1 of 2) NT8GTT72U4Nxxxx-xx, 4 RANK Fully Buffered DDR2 SDRAM DIMM Based on 512Mx4, 8Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte Serial PD Data Entry (Hexadecimal) Description D3YD-3C D4YD-3C D5YD-3C 0 Number of Serial PD Bytes in CRC 92 92 92 1 SPD Revision 11 11 11 2 Key Byte / DRAM Device Type 09 09 09 3 Voltage Levels of this Assembly 12 12 12 4 SDRAM Addressing 49 49 49 5 Module Physical Attributes 24 24 24 6 Modules Type 07 07 07 7 Module Organization 20 20 20 8 Fine Timebase Dividend and Divisor 52 52 52 9 Medium Timebase Dividend 01 01 01 10 Medium Timebase Divisor 04 04 04 11 SDRAM Minimum Cycle Time (tCKmin) 0C 0C 0C 12 SDRAM Maximum Cycle Time (tCKmax) 20 20 20 13 SDRAM 43 43 43 14 SDRAM Minimum CAS Latency Time (tAA) 3C 3C 3C 15 SDRAM Write Recovery Times Supported 42 42 42 16 SDRAM Write Recovery Time (tWR) 3C 3C 3C 17 SDRAM Write Latencies Supported 42 42 42 18 SDRAM Additive Latencies Supported 40 40 40 19 SDRAM Minimum 3C 3C 3C 20 SDRAM Minimum Row Active to Row Active Delay (tRRD) 1E 1E 1E 21 SDRAM Minimum Row Precharge Time (tRP) 3C 3C 3C 22 SDRAM Upper Nibbles for tRAS and tRC 00 00 00 23 SDRAM Minimum Active to Precharge Time (tRAS) B4 B4 B4 24 SDRAM Minimum Auto-Refresh to Active/Auto-Refresh Time (tRC) F0 F0 F0 25~26 SDRAM Minimum Auto-Refresh to Active/Auto-Refresh Command Period (tRFC) FE01 FE01 FE01 27 SDRAM Internal Write to Read Command Delay (tWTR) 1E 1E 1E 28 SDRAM Internal Read to Precharge Command Delay (tRTP) 1E 1E 1E 29 SDRAM Burst Lengths Supported 03 03 03 30 SDRAM Terminations Supported 07 07 07 31 SDRAM Drivers Supported 01 01 01 32 SDRAM Average Refresh Interval (tREFI)/Double Refresh mode bit/High Temperature self-refresh rate support indication C2 C2 C2 33 Tcasemax 00 00 00 34 Thermal resistance of SDRAM device package from top (case0 to ambient (Psi T-A SDRAM) 00 00 00 REV 1.3 03/2009 Latencies Supported to Delay (tRCD) 20 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BD-AC / NT2GT72U8PD0BD-AC / NT4GT72U4ND0BD-AC / NT4GT72U8ND9BD-AC NT1GT72U89D1BD-3C / NT2GT72U8PD1BD-3C / NT4GT72U4ND1BD-3C / NT8GTT72U4ND3YD-3C NT1GT72U89D1BN-3C / NT2GT72U8PD1BN-3C / NT4GT72U4ND1BN-3C / NT8GTT72U4ND4YD-3C NT1GT72U89D2BD-3C / NT2GT72U8PD2BD-3C / NT4GT72U4ND2BD-3C / NT8GTT72U4ND5YD-3C NT1GT72U89D6BD-AC / NT2GT72U8PD6BD-AC / NT4GT72U8ND9BD-3C Serial Presence Detect (Part 2 of 2) NT8GTT72U4Nxxxx-xx, 4 RANK Fully Buffered DDR2 SDRAM DIMM Based on 512Mx4, 8Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte Serial PD Data Entry (Hexadecimal) Description D3YD-3C D4YD-3C D5YD-3C 35-41 Delta Temperature -- -- -- 42-80 Reserved -- -- -- 81~82 FB-DIMM Channel Protocols Supported 0200 0200 0200 83 Additional Back to Back Access Turnaround Time 10 10 10 84 AMB Read Access Time for DDR2-800 36 36 4A 85 AMB Read Access Time for DDR2-667 34 34 46 86 AMB Read Access Time for DDR2-533 32 32 38 87 Thermal Resistance of AMB Package from top (case) to ambient (Psi T-A SDRAM) at still air condition. 2A 2A 2A 88 AMB DT Idle_0 62 62 3A 89 AMB DT Idle_1 77 77 47 90 AMB DT Idle_2 61 61 3A 91 AMB DT Active_1 9F 9F 5F 92 AMB DT Active _2 84 84 4F 93 AMB DT L0s 00 00 00 Reserved -- -- -- 115~116 AMB Manufacturer ID Code 7FB3 7FB3 7FB3 117-118 Module ID: Module Manufacture's JEDEC ID Code 830B 830B 830B 119-125 Reserved for Module ID -- -- -- 126-127 Cyclical Redundancy Code -- -- -- 128-145 Module Part Number -- -- -- 146-147 Module Revision Code 148-149 SDRAM Manufacture's JEDEC ID Code 150-255 Reserved 94~114 REV 1.3 03/2009 -- -- -- 830B 830B 830B -- -- -- 21 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BD-AC / NT2GT72U8PD0BD-AC / NT4GT72U4ND0BD-AC / NT4GT72U8ND9BD-AC NT1GT72U89D1BD-3C / NT2GT72U8PD1BD-3C / NT4GT72U4ND1BD-3C / NT8GTT72U4ND3YD-3C NT1GT72U89D1BN-3C / NT2GT72U8PD1BN-3C / NT4GT72U4ND1BN-3C / NT8GTT72U4ND4YD-3C NT1GT72U89D2BD-3C / NT2GT72U8PD2BD-3C / NT4GT72U4ND2BD-3C / NT8GTT72U4ND5YD-3C NT1GT72U89D6BD-AC / NT2GT72U8PD6BD-AC / NT4GT72U8ND9BD-3C Environmental Requirements Symbol Parameter TOPR Operating temperature HOPR Operating humidity (relative) TSTG Storage temperature HSTG Storage humidity (without condensation) PBAR Barometric pressure (operating & Storage) Note: 1. 2. Units - Note 1 10 to 90 % 2 -50 to +100 C 2 5 to 95 % 2 105 to 69 K pascal 2 The designer must meet the case temperature specifications for individual module components. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only and device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. REV 1.3 03/2009 Rating 22 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BD-AC / NT2GT72U8PD0BD-AC / NT4GT72U4ND0BD-AC / NT4GT72U8ND9BD-AC NT1GT72U89D1BD-3C / NT2GT72U8PD1BD-3C / NT4GT72U4ND1BD-3C / NT8GTT72U4ND3YD-3C NT1GT72U89D1BN-3C / NT2GT72U8PD1BN-3C / NT4GT72U4ND1BN-3C / NT8GTT72U4ND4YD-3C NT1GT72U89D2BD-3C / NT2GT72U8PD2BD-3C / NT4GT72U4ND2BD-3C / NT8GTT72U4ND5YD-3C NT1GT72U89D6BD-AC / NT2GT72U8PD6BD-AC / NT4GT72U8ND9BD-3C Operating, Standby, and Refresh Currents Definition table Symbol Parameter/Condition Idd_Idle_0 Icc_Idle_0 Idle Current, single or last DIMM. L0 state, idle (0BW). Primary channel enabled; Secondary Channel disabled. CKE high. Command and address line stable. DRAM clock active. Idd_Idle_1 Icc_Idle_1 Idle Current, first DIMM. L0 stage, idle (0BW). Primary and Secondary channels enabled. CKE high. Command and address line stable. DRAM clock active. Idd_Idle_2 Icc_Idle_2 Idle Current, DRAM power down. L0 stage, idle (0BW). Primary and Secondary channels enabled CKE low. Command and address lines floated. DRAM clock active, ODT and CKE driven low. Idd_Active_1 Icc_Active_1 (Write) Active Power. L0 state. 50% DRAM BW to downstream DIMM, 67% read, 33% write. Primary and Secondary channels enabled. DRAM clock active, CKE high. Idd_Active_1 Icc_Active_1 (Read) Active Power. L0 state. 50% DRAM BW to downstream DIMM, 100% read. Primary and Secondary channels enabled. DRAM clock active, CKE high. Idd_Active_2 Icc_Active_2 Active Power, data pass through. L0 state. 50% DRAM BW to downstream DIMM, 67% read, 33% write. Primary and Secondary channels enabled. CKE high. Command and address lines stable. DRAM clock active. Idd_Training Icc_Training Primary and Secondary channels enabled. 100% toggle on all channel lanes. DRAMs idle. 0BW. CKE high, Command and address line stable. DRAM clock active. Part Number Idle_0 Idd Icc Idle_1 Idd Icc Idle_2 Idd Icc Active_1 (W) Active_1 (R) Idd Idd Icc Icc Active_2 Idd Icc Training Idd Icc Unit NT1GT72U89D0BD-AC 0.96 3.39 0.97 4.16 0.97 4.16 0.99 4.18 0.99 4.18 0.97 4.18 0.94 3.96 A NT1GT72U89D6BD-AC 0.96 3.39 0.97 4.16 0.97 4.16 0.99 4.18 0.99 4.18 0.97 4.18 0.94 3.96 A NT1GT72U89D1BD-3C 0.91 2.86 0.91 2.92 0.88 3.76 0.92 3.75 0.94 3.74 0.88 3.74 0.90 3.41 A NT1GT72U89D2BD-3C 0.77 1.85 0.77 2.37 0.79 2.37 0.77 2.35 0.77 2.37 0.77 2.42 0.77 2.33 A NT1GT72U89D1BN-3C 0.77 2.64 0.77 3.87 0.77 3.87 0.94 4.20 0.99 4.22 0.99 4.13 0.88 3.87 A NT2GT72U8PD0BD-AC 1.34 3.34 1.35 4.04 1.35 4.05 1.43 4.20 1.33 4.19 1.98 4.09 1.98 3.92 A NT2GT72U8PD6BD-AC 1.34 3.34 1.35 4.04 1.35 4.05 1.43 4.20 1.33 4.19 1.98 4.09 1.98 3.92 A NT2GT72U8PD1BD-3C 1.30 2.51 1.30 3.55 1.31 3.72 1.30 3.72 1.30 3.72 2.09 3.72 1.99 3.47 A NT2GT72U8PD2BD-3C 1.16 1.89 1.16 2.40 1.18 2.42 1.16 2.42 1.16 2.43 1.13 2.42 1.16 2.37 A NT2GT72U8PD1BN-3C 1.10 2.67 1.11 3.93 1.11 3.94 1.25 4.18 1.25 4.27 1.25 4.19 1.24 3.96 A NT4GT72U4ND0BD-AC 2.28 2.85 2.31 4.03 2.32 4.02 2.39 4.27 2.41 4.28 2.31 4.28 2.34 3.93 A NT4GT72U4ND1BD-3C 2.09 2.86 2.11 3.63 2.15 3.74 2.23 3.76 2.21 3.77 2.21 3.76 2.11 3.52 A NT4GT72U4ND2BD-3C 2.04 1.90 2.04 2.42 2.10 2.44 2.11 2.45 2.11 2.45 2.01 2.44 2.01 2.40 A NT4GT72U4ND1BN-3C 1.93 2.70 1.93 4.10 2.50 4.22 2.51 4.24 2.51 4.24 1.93 4.16 1.93 3.87 A NT8GTT72U4ND3YD-3C 3.60 2.96 3.67 3.74 3.70 3.78 3.78 3.80 3.76 3.80 3.63 3.81 3.63 3.74 A NT8GTT72U4ND4YD-3C 3.60 2.96 3.67 3.74 3.70 3.78 3.78 3.80 3.76 3.80 3.63 3.81 3.63 3.74 A NT4GT72U8ND9BD-3C A NT4GT72U8ND9BD-AC A REV 1.3 03/2009 23 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BD-AC / NT2GT72U8PD0BD-AC / NT4GT72U4ND0BD-AC / NT4GT72U8ND9BD-AC NT1GT72U89D1BD-3C / NT2GT72U8PD1BD-3C / NT4GT72U4ND1BD-3C / NT8GTT72U4ND3YD-3C NT1GT72U89D1BN-3C / NT2GT72U8PD1BN-3C / NT4GT72U4ND1BN-3C / NT8GTT72U4ND4YD-3C NT1GT72U89D2BD-3C / NT2GT72U8PD2BD-3C / NT4GT72U4ND2BD-3C / NT8GTT72U4ND5YD-3C NT1GT72U89D6BD-AC / NT2GT72U8PD6BD-AC / NT4GT72U8ND9BD-3C AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 1 of 2) Symbol -AC Max. Min. Max. Unit -0.45 +0.45 -0.40 +0.40 ns DQS output access time from CK/ -0.4 +0.4 -0.35 +0.35 ns tCH CK high-level width 0.48 0.52 0.48 0.52 tCK tCL CK low-level width 0.48 0.52 0.48 0.52 tCK tHP Minimum half clk period for any given cycle; defined by clk high (tCH) or clk low (tCL) time Min (tCH, tCL) - Min (tCH, tCL) - tCK tCK Clock Cycle Time 3 8 2.5 8 ns tDH DQ and DM input hold time 175 - 125 - ps tDS DQ and DM input setup time 100 - 50 - ps tIPW Input pulse width 0.6 - 0.6 - tCK DQ and DM input pulse width (each input) 0.35 - 0.35 - tCK - tAC max - tAC max ns tAC max ns tAC min tAC max tAC min tAC max ns tDQSCK tDIPW tHZ Data-out high-impedance time from CK/ tLZ(DQ) Data-out low-impedance time from CK/ tLZ(DQS) DQS/ tDQSQ 2tAC tAC max min low-impedance time from CK/ DQS-DQ skew (DQS & associated DQ signals) 0.24 - min - 0.20 ns 0.34 - 0.30 ns Data output hold time from DQS - tHP tQHS - ns tDQSS Write command to 1st DQS latching transition -0.25 0.25 -0.25 0.25 tCK tDQSL,(H) DQS input low (high) pulse width (write cycle) 0.35 - 0.35 - tCK tDSS DQS falling edge to CK setup time (write cycle) 0.2 - 0.2 - tCK tDSH DQS falling edge hold time from CK (write cycle) 0.2 - 0.2 - tCK tMRD Mode register set command cycle time 2 - 2 - tCK tQH Data hold Skew Factor - 2tAC tHP tQHS tQHS tWPST Write postamble 0.40 0.60 0.40 0.60 tCK tWPRE Write preamble 0.35 - 0.35 - tCK tIH Address and control input hold time 0.275 - 0.250 - ps tIS Address and control input setup time 0.2 - 0.175 - ps tRPRE Read preamble 0.9 1.1 0.9 1.1 tCK tRPST Read postamble 0.4 0.6 0.4 0.6 tCK tDelay Minimum time clocks remains ON after CKE asynchronously drops Low tRFC Refresh to active/Refresh command time tREFI tRRD 03/2009 Min. DQ output access time from CK/ tAC REV 1.3 -3C Parameter tIS + tCK + tIH tIS + tCK + tIH ns 127.5 127.5 ns Average Periodic Refresh Interval (85C < TCASE = 95C) 3.9 3.9 >s Average Periodic Refresh Interval (0C = TCASE = 85C) 7.8 7.8 >s Active bank A to Active bank B command 7.5 - 7.5 Notes - ns 24 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BD-AC / NT2GT72U8PD0BD-AC / NT4GT72U4ND0BD-AC / NT4GT72U8ND9BD-AC NT1GT72U89D1BD-3C / NT2GT72U8PD1BD-3C / NT4GT72U4ND1BD-3C / NT8GTT72U4ND3YD-3C NT1GT72U89D1BN-3C / NT2GT72U8PD1BN-3C / NT4GT72U4ND1BN-3C / NT8GTT72U4ND4YD-3C NT1GT72U89D2BD-3C / NT2GT72U8PD2BD-3C / NT4GT72U4ND2BD-3C / NT8GTT72U4ND5YD-3C NT1GT72U89D6BD-AC / NT2GT72U8PD6BD-AC / NT4GT72U8ND9BD-3C AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 2 of 2) Symbol tCCD -3C Parameter to tWR Write recovery time WR Write recovery time with Auto-Precharge -AC Min. Max. 2 15 Unit Min. Max. - 2 - tCK - 15 - ns tWR/tCK tWR/tCK - WR +tRP - tCK - 7.5 - ns ns tDAL Auto precharge write recovery + precharge time WR +tRP tWTR Internal write to read command delay 7.5 tRTP Internal read to precharge command delay 7.5 7.5 ns tXSNR Exit self refresh to a Non-read command tRFC +10 tRFC +10 ns tXSRD Exit self refresh to a Read command 200 200 tCK Exit precharge power down to any Non- read command 2 - 2 - tCK tXARD Exit active power down to read command 2 - 2 - tCK tXARDS Exit active power down to read command tXP Notes 7-AL 8-AL tCK tCKE CKE minimum pulse width 3 3 tCK tOIT OCD drive mode output delay 0 12 0 12 ns 2 2 2 2 tCK tAC tAC ODT tAOND tAON tAONPD tAOFD ODT turn-on delay ODT turn-on tAC(min) tAC(max) ns 2tCK + 2tCK + tAC(min) t tAC(max) AC(min) tAC(max) +2 +2 +1 +1 ns (min) ODT turn-on (Power down mode) ODT turn-off delay 2.5 (max) +1 2.5 +0.7 2.5 2.5 tCK ODT turn-off tAC(min) tAC(max) tAC(max) t +0.6 AC(min) +0.6 ns tAOFPD ODT turn-off (Power down mode) 2.5tCK 2.5tCK + + tAC(min) tAC(min) +2 tAC(max) +2 tAC(max) +1 +1 ns tANPD ODT to power down entry latency 3 3 tCK tAXPD ODT power down exit latency 8 8 tCK tAOF Speed Grade Definition REV 1.3 03/2009 tRAS Row Active Time 45 70000 45 70000 ns tRCD RAS to CAS delay 15 - 12.5 - ns tRC Row Cycle Time 60 - 57.5 - ns tRP Row Precharge Time 15 - 12.5 - ns 25 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BD-AC / NT2GT72U8PD0BD-AC / NT4GT72U4ND0BD-AC / NT4GT72U8ND9BD-AC NT1GT72U89D1BD-3C / NT2GT72U8PD1BD-3C / NT4GT72U4ND1BD-3C / NT8GTT72U4ND3YD-3C NT1GT72U89D1BN-3C / NT2GT72U8PD1BN-3C / NT4GT72U4ND1BN-3C / NT8GTT72U4ND4YD-3C NT1GT72U89D2BD-3C / NT2GT72U8PD2BD-3C / NT4GT72U4ND2BD-3C / NT8GTT72U4ND5YD-3C NT1GT72U89D6BD-AC / NT2GT72U8PD6BD-AC / NT4GT72U8ND9BD-3C Package Dimensions for the following part numbers: NT1GT72U89D0BD-AC / NT2GT72U8PD0BD-AC / NT4GT72U4ND0BD-AC NT1GT72U89D1BD-3C / NT2GT72U8PD1BD-3C / NT4GT72U4ND1BD-3C NT1GT72U89D1BN-3C / NT2GT72U8PD1BN-3C / NT4GT72U4ND1BN-3C NT1GT72U89D2BD-3C / NT2GT72U8PD2BD-3C / NT4GT72U4ND2BD-3C NT8GTT72U4ND3YD-3C / NT8GTT72U4ND4YD-3C / NT4GT72U8ND9BD-3C NT4GT72U8ND9BD-AC / NT8GTT72U4ND5YD-3C Max. 9.0 B 51 A 67 12 0 9.5 30.35 +/-0.15 17.3 133.35 +/- 0.15 1.27 +/- 0.10 74.67 Detail A Detail B 2.50 3.80 2.5 0.80 +/- 0.1 Width 1.00 Pitch 1.50+/- 0.10 REV 1.3 03/2009 Unit: mm 26 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BD-AC / NT2GT72U8PD0BD-AC / NT4GT72U4ND0BD-AC / NT4GT72U8ND9BD-AC NT1GT72U89D1BD-3C / NT2GT72U8PD1BD-3C / NT4GT72U4ND1BD-3C / NT8GTT72U4ND3YD-3C NT1GT72U89D1BN-3C / NT2GT72U8PD1BN-3C / NT4GT72U4ND1BN-3C / NT8GTT72U4ND4YD-3C NT1GT72U89D2BD-3C / NT2GT72U8PD2BD-3C / NT4GT72U4ND2BD-3C / NT8GTT72U4ND5YD-3C NT1GT72U89D6BD-AC / NT2GT72U8PD6BD-AC / NT4GT72U8ND9BD-3C Package Dimensions for the following part numbers: NT1GT72U89D6BD-AC / NT2GT72U8PD6BD-AC Max. 23.81 B 51 A 67 12 0 9.5 30.35 +/-0.15 17.3 133.35 +/- 0.15 1.27 +/- 0.10 74.67 3.80 Detail B 2.50 +/- 0.20 Detail A 2.5 0.80 +/- 0.1 Width 1.00 Pitch 1.50+/- 0.10 REV 1.3 03/2009 Unit: mm 27 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GT72U89D0BD-AC / NT2GT72U8PD0BD-AC / NT4GT72U4ND0BD-AC / NT4GT72U8ND9BD-AC NT1GT72U89D1BD-3C / NT2GT72U8PD1BD-3C / NT4GT72U4ND1BD-3C / NT8GTT72U4ND3YD-3C NT1GT72U89D1BN-3C / NT2GT72U8PD1BN-3C / NT4GT72U4ND1BN-3C / NT8GTT72U4ND4YD-3C NT1GT72U89D2BD-3C / NT2GT72U8PD2BD-3C / NT4GT72U4ND2BD-3C / NT8GTT72U4ND5YD-3C NT1GT72U89D6BD-AC / NT2GT72U8PD6BD-AC / NT4GT72U8ND9BD-3C Revision Log Rev Date 0.1 02/2008 Preliminary Release Modification 0.2 03/2008 Add IDT AMB+ Product Information 0.3 04/2008 Add 4GB product information Add environmental parameters Update Package Dimensions 0.4 05/2008 Add 8GB product information Update Package Dimensions Update typo 1.0 05/2008 Official release 1.1 06/2008 Add NT1GT72U89D6BD-AC, NT2GT72U8PD6BD-AC, and NT8GTT72U4ND4YD-3C related specification. 1.2 12/2008 Add NT4GT72U8ND9BD-3C/AC 1.3 03/2009 Add NT8GTT72U4ND5YD-3C Nanya Technology Corporation Hwa Ya Technology Park 669 Fu Hsing 3rd Rd., Kueishan, Taoyuan, 333, Taiwan, R.O.C. Tel: +886-3-328-1688 Please visit our home page for more information: www.nanya.com Printed in Taiwan (c)2008 REV 1.3 03/2009 28 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.