2013/3/1
Ver 1.2
2013/3/1
Semiconductor Business Group
Industrial Devices Company
Panasonic Corporation
Evaluation board circuit diagram
and implementation
<MN63Y1208>
Evaluation board circuit diagram
Evaluation board circuit diagram
and implementation
and implementation
<MN63Y1208>
<MN63Y1208>
22013/3/1
List of pin placement / pins of the NFC tag
Tab.１Pins of the NFC tag
Fig.１List of pin placement
PIN Number Terminal name Input/output Input and output type function
1 VB I/O － Coil terminal
2 VDDEX － Power Power supply for contact (Input 1.7V ～ 3.6V)
3VSS－ GNDGround
4 VA I/O － Coil terminal
5 N.C. － － Unconnected pin
6 VDDD － Power Digital internal power supply (Connect capacitance between VSS)
7 TEST1 input － Test control (Normally connected to VSS)
8 N.C. － － Unconnected pin
9 NIRQ output Open Drain Interrupt request output
10 TEST3 input － Test control (Normally connected to VSS)
11 SCL input － HOST I/F (I2C 100kHz)
12 SDA I/O Open Drain HOST I/F (I2C 100kHz)
13 N.C. － － Unconnected pin
14 TEST4 input － Test control (Normally connected to VSS)
15 TEST2 input － Test control (Normally connected to VSS)
16 VDDA － Power Analog internal power supply (Connect capacitance between VSS)
32013/3/1
Figure of pattern of the evaluation board
It is pulling up resistance to prevent an uncertainty state of SCL causing the malfunction.
When NFC tag LSI has the terms of use that R1 is not connected to, I am necessary.
100kΩR0
It is pulling up resistance for interrupt signal lines.
Please decide the resistance level in consideration of wiring capacity, current ability.
In our NFC tag board "ANT4030_02_0505_B0_L ," it is not implemented.
3.3kΩR3
It is a fixed value at the capacity between the power supply for operation stabilization of the tag LSI.
C2 is connected to VDDD, and C3 is connected to VDDA and C4 is connected to VDDEX
0.1μFC2、C3、C4
It is pulling up resistance for I2C signal lines.Please decide the resistance level in consideration
of transmission rate, wiring capacity, current ability.
In our NFC tag board "ANT4030_02_0505_B0_L ," it is not implemented.
3.3kΩR1,R2
Detailed explanationRecommendation ValueExternal part
※ I connect pulling up resistance (R,R2,R3) to the microcomputer board of our offer.
Chip and Parts are implemented b y the antenna b oard surface
C2
C3
C4
MN63Y1208
R0
SDA
VSS
SCL
NIRQ
VDDEX
R2
R１
Connect with
the other board ※
R３
VDD
42013/3/1
Connection example with the MCU board
Host
Controller
I2C
Antenna
RF
NFC tag system constitution
MN63Y1208
Control Board
Antenna
TAG circuit
R0 C3
C2
NIRQ
TEST3
SCL
SDA
NC
VDDD
VA
VSS
VDDEX
VB
TEST1
NC
VDDA
TEST2
TEST4
NC
C4
C0
MN63Y1208
9
10
11
12
54
3
2
1
16
6
7
8
15
1413
GPIO
Host
Controller
SDA
SCL
NIRQ
3.3V
R1
R2
Antenna
TAG circuit
Antenna Board 「ANT4030_02_0505_B0_L」
MCU Board
Antenna Board
R3 VSS
SCL
VDDEX
IRQ
SDA
52013/3/1
Implementation of the evaluation board
C2
MN63Y1208
C3
C4
R0
C0
Chip and Parts are implemented by the board surface
Antenna is implemented by the board back side
62013/3/1
Connector specifications
Connection image
MCU Board
[BTPB-101B]
Micon Board [BTPB101-B]
VSS １
SCL ３
５
７
２
４SDA
６NIRQ
８VDDEX
DF11CZ-8DP-2V(27)
( Hirose Electric )
Antenna Board [ANT4030_02_0505_B0_L]
７
５
SCL ３
VSS １
８VDDEX
６NIRQ
４SDA
２
HRS DF11CZ- 8DS-2V
( Hirose Electric )
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