CY8C24X93
PSoC® Programmable System-on-Chip
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-86894 Rev. *B Revised May 24, 2013
PSoC® Programmable System-on-Chip
Features
■Powerful Harvard-architecture processor
❐M8C CPU with a max speed of 24 MHz
■Operating Range: 1.71 V to 5.5 V
❐Standby Mode 1.1 μA (Typ)
❐Deep Sleep 0.1 μA (Typ)
■Operating Temperature range: –40 °C to +85 °C
■Flexible on-chip memory
❐8 KB flash, 1 KB SRAM
❐16 KB flash, 2 KB SRAM
❐32 KB flash, 2 KB SRAM
❐Read while Write with EEPROM emulation
❐50,000 flash erase/write cycles
❐In-system programming simplifies manufacturing process
■Four Clock Sources
❐Internal main oscillator (IMO): 6/12/24 MHz
❐Internal low-speed oscillator (ILO) at 32 kHz for watchdog
and sleep timers
❐External 32 KHz Crystal Oscillator
❐External Clock Input
■Programmable pin configurations
❐Up to 36 general purpose dual mode GPIO (Analog inputs
and Digital I/O supported)
❐High sink current of 25 mA per GPIO
• Max sink current 120 mA for all GPIOs
❐Source Current
• 5 mA on ports 0 and 1
• 1 mA on ports 2,3 and 4
❐Configurable internal pull-up, high-Z and open drain modes
❐Selectable, regulated digital I/O on port 1
❐Configurable input threshold on port 1
■Versatile Analog functions
❐Internal Low-Dropout voltage regulator for high power supply
rejection ratio (PSRR)
■Full-Speed USB
❐12 Mbps USB 2.0 compliant
❐Eight unidirectional endpoints
❐One bidirectional endpoint
❐Dedicated 512 byte SRAM
❐No external crystal required
■Additional system resources
❐I2C Slave:
• Selectable to 50 kHz, 100 kHz, or 400 kHz
❐Configurable up to 12 MHz SPI master and slave
❐Three 16-bit timers
❐Watchdog and sleep timers
❐Integrated supervisory circuit
❐10-bit incremental analog-to-digital converter (ADC) with
internal voltage reference
❐Two general-purpose Comparators
• 3 Voltage References (0.8 V, 1 V, 1.2 V)
• Any pin to either comparator inputs
• Low-power operation at 10 µA
❐One 8-bit IDAC with full scale range of 512 µA
❐One 8-bit Software PWM
■Development Platform
❐PSoC Designer™ IDE
■GPIOs and Package options
❐13 GPIOs - QFN 16
❐28 GPIOs - QFN 32
❐34 GPIOs - QFN 48
❐36 GPIOs - QFN 48
CY8C24X93
Document Number: 001-86894 Rev. *B Page 2 of 65
Logic Block Diagram
ANALOG
SYSTEM
1K/2K
SRAM
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
Internal Low Speed Oscillator (ILO)
6/12/24 MHz Internal Main Oscillator
(IMO)
PSoC CORE
CPU Core (M8C)
Supervisory ROM (SROM) 8K/16K/32K Flash
Nonvolatile Memory
SYSTEM RESOURCES
SYSTEM BUS
Analog
Reference
SYSTEM BUS
Port 3 Port 2 Port 1 Port 0
ADC
Global Analog Interconnect
1.8/2.5/3V
LDO
Analog Mux
I2C
Slave
SPI
Master/
Slave
POR
and
LVD
USB System
Resets
Internal
Voltage
References
Three 16-Bit
Programmable
Timers
PWRSYS
(Regulator)
Port 4
Digital
Clocks
IDAC
Two
Comparators
[1]
Note
1. Internal voltage regulator for internal circuitry.
CY8C24X93
Document Number: 001-86894 Rev. *B Page 3 of 65
Contents
PSoC® Functional Overview ............................................5
PSoC Core .................................................................. 5
Analog system ............................................................. 5
Additional System Resources ..................................... 6
Getting Started ..................... .............................................7
Silicon Errata ............................................................... 7
Development Kits ........................................................7
Training .......................................................................7
CYPros Consultants .................................................... 7
Solutions Library ..........................................................7
Technical Support ....................................................... 7
Development Tools ............. ... ............................ ..............8
PSoC Designer Software Subsystems ........................ 8
Designing with PSoC Designer ......................... .. ... .........9
Select User Modules ...................................................9
Configure User Modules .............................................. 9
Organize and Connect ................................................ 9
Generate, Verify, and Debug ....................................... 9
Pinouts ............................................................................10
16-pin QFN (13 GPIOs) [2] ........................................ 10
32-pin QFN (28 GPIOs) [6] ........................................ 11
32-pin QFN (28 GPIOs) [10] ......................................12
48-pin QFN (34 GPIOs) [14] ......................................13
48-pin QFN (36 GPIOs (With USB)) [19] ................... 14
48-pin QFN (OCD) (36 GPIOs) [23] .......................... 15
Electrical Specifications (CY8C24193/493) ..................16
Absolute Maximum Ratings
(CY8C24193/493) ............................................................. 16
Operating Temperature
(CY8C24193/493) ............................................................. 16
DC Chip-Level Specifications
(CY8C24193/493) ............................................................. 17
DC GPIO Specifications
(CY8C24193/493) ............................................................. 18
DC Analog Mux Bus Specifications
(CY8C24193/493) ............................................................. 21
DC Low Power Comparator Specifications
(CY8C24193/493) ............................................................. 21
Comparator User Module Electrical Specifications
(CY8C24193/493) ............................................................. 21
ADC Electrical Specifications
(CY8C24193/493) ............................................................. 22
DC POR and LVD Specifications
(CY8C24193/493) ............................................................. 23
DC Programming Specifications
(CY8C24193/493) ............................................................. 23
DC I2C Specifications
(CY8C24193/493) ............................................................. 24
Shield Driver DC Specifications
(CY8C24193/493) ............................................................. 24
DC IDAC Specifications
(CY8C24193/493) ............................................................. 24
AC Chip-Level Specifications
(CY8C24193/493) ............................................................. 25
AC General Purpose I/O Specifications
(CY8C24193/493) ............................................................. 26
AC Comparator Specifications
(CY8C24193/493) ............................................................. 26
AC External Clock Specifications
(CY8C24193/493) ............................................................. 26
AC Programming Specifications
(CY8C24193/493) ............................................................. 27
AC I2C Specifications (CY8C24193/493) .................. 28
Electrical Specifications
(CY8C24093/293/393/693) ...............................................31
Absolute Maximum Ratings
(CY8C24093/293/393/693) ............................................... 31
Operating Temperature
(CY8C24093/293/393/693) ............................................... 31
DC Chip-Level Specifications
(CY8C24093/293/393/693) ............................................... 32
DC GPIO Specifications
(CY8C24093/293/393/693) ............................................... 33
DC Analog Mux Bus Specifications
(CY8C24093/293/393/693) ............................................... 35
DC Low Power Comparator Specifications
(CY8C24093/293/393/693) ............................................... 35
Comparator User Module Electrical Specifications
(CY8C24093/293/393/693) ............................................... 36
ADC Electrical Specifications
(CY8C24093/293/393/693) ............................................... 36
DC POR and LVD Specifications
(CY8C24093/293/393/693) ............................................... 37
DC Programming Specifications
(CY8C24093/293/393/693) ............................................... 37
DC I2C Specifications
(CY8C24093/293/393/693) ............................................... 38
DC Reference Buffer Specifications
(CY8C24093/293/393/693) ............................................... 38
DC IDAC Specifications
(CY8C24093/293/393/693) ............................................... 38
AC Chip-Level Specifications
(CY8C24093/293/393/693) ............................................... 39
AC GPIO Specifications
(CY8C24093/293/393/693) ............................................... 40
AC Comparator Specifications
(CY8C24093/293/393/693) ............................................... 41
AC External Clock Specifications
(CY8C24093/293/393/693) ............................................... 41
AC Programming Specifications
(CY8C24093/293/393/693) ............................................... 42
AC I2C Specifications
(CY8C24093/293/393/693) ............................................... 43
Packaging Information .............................................. .....46
Thermal Impedances ................................................. 49
Capacitance on Crystal Pins ..................................... 49
Solder Reflow Specifications ..................................... 49
Development Tool Selection .........................................50
Software .................................................................... 50
CY8C24X93
Document Number: 001-86894 Rev. *B Page 4 of 65
Development Kits ......................................................50
Evaluation Tools ........................................................50
Device Programmers .................................................50
Ordering Information ......................................................51
Ordering Code Definitions ......................................... 51
Acronyms ........................................................................ 52
Document Conventions ......... .. ... ............................ ... ....53
Units of Measure .......................................................53
Reference Documents .............. ... ... ............................ ... .53
Numeric Naming .............................................................53
Glossary ..........................................................................54
Appendix A: Silicon Errata for the
CY8C24093/293/393/693 Family ............. ... ... ..................55
CY8C24093/293/393/693 Qualification Status ..........55
CY8C24093/293/393/693 Errata Summary ...............55
Appendix B: Silicon Errata for the
PSoC® CY8C24193/493 Families ..................................60
CY8C24193/493 Qualification Status ........................ 60
CY8C24193/493 Errata Summary ............................. 60
Document History Page .................................................64
Sales, Solutions, and Legal Information ......................65
Worldwide Sales and Design Support ....................... 65
Products .................................................................... 65
PSoC Solutions ......................................................... 65
CY8C24X93
Document Number: 001-86894 Rev. *B Page 5 of 65
PSoC® Functional Overview
The PSoC family consists of on-chip controller devices, which
are designed to replace multiple traditional microcontroller unit
(MCU)-based components with one, low cost single-chip
programmable component. A PSoC device includes
configurable analog and digital blocks, and programmable
interconnect. This architecture allows the user to create
customized peripheral configurations, to match the requirements
of each individual application. Additionally, a fast CPU, Flash
program memory, SRAM data memory, and configurable I/O are
included in a range of convenient pinouts.
The architecture for this device family, as shown in the Logic
Block Diagram on page 2, consists of three main areas:
■The Core
■Analog System
■System Resources (including a full-speed USB port).
A common, versatile bus allows connection between I/O and the
analog system.
Depending on the PSoC package, up to 36 GPIO are included in
the CY8C24x93 PSoC device. The GPIO provides access to the
MCU and analog mux.
PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO and
ILO. The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a 4-MIPS, 8-bit
Harvard-architecture microprocessor.
Analog system
The analog system is composed of an ADC, two comparators
and an IDAC. It has an internal 0.8 V, 1 V or 1.2 V analog
reference. All the pins can be configured to connect to the analog
system.
ADC
The ADC in the CY8C24x93 device is an incremental
analog-to-digital converter with a range of 8 to 10 bits supporting
signed and unsigned data formats. The input to the ADC can be
from any pin.
IDAC
The IDAC can provide current source up to 512 µA to any GPIO
pin. In the CY8C24x93 family of devices 4 ranges of current
source can be implemented that can vary in 255 steps, and are
connected to analog mux bus.
Comparator
The CY8C24x93 family has two high-speed, low-power
comparators. The comparators have three voltage references,
0.8 V, 1.0 V and 1.2 V. Comparator inputs can be connected from
any pin through the analog mux bus. The comparator output can
be read in firmware for processing or routed out via specific pins
(P1_0 or P1_4).
The output of the two comparators can be combined with 2-input
logic functions. The combinatorial output can be optionally
combined with a latched value and routed to a pin output or to
the interrupt controller. The input multiplexers and the
comparator are controller through the CMP User Module.
Table 1. IDAC Ranges
Range Full Scale Range in µA
1x 64
2x 128
4x 256
8x 512
CY8C24X93
Document Number: 001-86894 Rev. *B Page 6 of 65
Analog Multiplexer System
The Analog Mux Bus can connect to every GPIO pin and can be
internally connected to the ADC, Comprators or the IDAC.
Other multiplexer applications include:
■Chip-wide mux that allows analog input from any I/O pin.
■Crosspoint connection between any I/O pin combinations.
Additional System Resources
System resources provide additional capability, such as
configurable USB and I2C slave, SPI master/slave
communication interface, three 16-bit programmable timers,
software 8-bit PWM, low voltage detect, power on reset, and
various system resets supported by the M8C.
The merits of each system resource are listed here:
■The I2C slave/SPI master-slave module provides
50/100/400 kHz communication over two wires. SPI
communication over three or four wires runs at speeds of
46.9 kHz to 3 MHz (lower for a slower system clock).
■Low-voltage detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced
power-on-reset (POR) circuit eliminates the need for a system
supervisor.
■A register-controlled bypass mode allows the user to disable
the LDO regulator.
■An 8-bit Software PWM is provided for applications like buzzer
control or lighting control. A 16-bit Timer acts as the input clock
to the PWM. The ISR increments a software counter (8-bit),
checks for PWM compare condition and toggles a GPIO
accordingly. PWM Output is available on all GPIOs.
CY8C24X93
Document Number: 001-86894 Rev. *B Page 7 of 65
Getting Started
The quickest way to understand PSoC silicon is to read this
datasheet and then use the PSoC Designer Integrated
Development Environment (IDE). This datasheet is an overview
of the PSoC integrated circuit and presents specific pin, register,
and electrical specifications.
For in depth information, along with detailed programming
details, see the Technical Reference Manual for the PSoC
devices.
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device datasheets on the web
at www.cypress.com/psoc.
Silicon Errata
Errata documents known issues with silicon including errata
trigger conditions, scope of impact, available workarounds and
silicon revision applicability.
Development Kits
PSoC Development Kits are available online from and through a
growing number of regional and global distributors, which
include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and
Newark.
Training
Free PSoC technical training (on demand, webinars, and
workshops), which is available online via www.cypress.com,
covers a wide variety of topics and skill levels to assist you in
your designs.
CYPros Consultants
Certified PSoC consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC consultant go to the CYPros Consultants web site.
Solutions Library
Visit our growing library of solution focused designs. Here you
can find various application designs that include firmware and
hardware design files that enable you to complete your designs
quickly.
Technical Support
Technical support – including a searchable Knowledge Base
articles and technical forums – is also available online. If you
cannot find an answer to your question, call our Technical
Support hotline at 1-800-541-4736.
CY8C24X93
Document Number: 001-86894 Rev. *B Page 8 of 65
Development Tools
PSoC Designer™ is the revolutionary integrated design
environment (IDE) that you can use to customize PSoC to meet
your specific application requirements. PSoC Designer software
accelerates system design and time to market. Develop your
applications using a library of precharacterized analog and digital
peripherals (called user modules) in a drag-and-drop design
environment. Then, customize your design by leveraging the
dynamically generated application programming interface (API)
libraries of code. Finally, debug and test your designs with the
integrated debug environment, including in-circuit emulation and
standard software debug features. PSoC Designer includes:
■Application editor graphical user interface (GUI) for device and
user module configuration and dynamic reconfiguration
■Extensive user module catalog
■Integrated source-code editor (C and assembly)
■Free C compiler with no size restrictions or time limits
■Built-in debugger
■In-circuit emulation
■Built-in support for communication interfaces:
❐Hardware and software I2C slaves and masters
❐Full-speed USB 2.0
❐Up to four full-duplex universal asynchronous
receiver/transmitters (UARTs), SPI master and slave, and
wireless
PSoC Designer supports the entire library of PSoC 1 devices and
runs on Windows XP, Windows Vista, and Windows 7.
PSoC Designer Software Subsystems
Design Entry
In the chip-level view, choose a base device to work with. Then
select different onboard analog and digital components that use
the PSoC blocks, which are called user modules. Examples of
user modules are analog-to-digital converters (ADCs),
digital-to-analog converters (DACs), amplifiers, and filters.
Configure the user modules for your chosen application and
connect them to each other and to the proper pins. Then
generate your project. This prepopulates your project with APIs
and libraries that you can use to program your application.
The tool also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
reconfiguration makes it possible to change configurations at run
time. In essence, this lets you to use more than 100 percent of
PSoC’s resources for an application.
Code Generati on Tools
The code generation tools work seamlessly within the
PSoC Designer interface and have been tested with a full range
of debugging tools. You can develop your design in C, assembly,
or a combination of the two.
Assemblers. The assemblers allow you to merge assembly
code seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and linked
with other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices. The
optimizing C compilers provide all of the features of C, tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow you to read and program and
read and write data memory, and read and write I/O registers.
You can read and write CPU registers, set and clear breakpoints,
and provide program run, halt, and step control. The debugger
also lets you to create a trace buffer of registers and memory
locations of interest.
Online Help System
The online help system displays online, context-sensitive help.
Designed for procedural and quick reference, each functional
subsystem has its own context-sensitive help. This system also
provides tutorials and links to FAQs and an Online Support
Forum to aid the designer.
In-Circuit Emulator
A low-cost, high-functionality in-circuit emulator (ICE) is
available for development support. This hardware can program
single devices.
The emulator consists of a base unit that connects to the PC
using a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full-speed
(24 MHz) operation.
CY8C24X93
Document Number: 001-86894 Rev. *B Page 9 of 65
Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed-function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and lowering inventory costs. These
configurable resources, called PSoC blocks, have the ability to
implement a wide variety of user-selectable functions. The PSoC
development process is:
1. Select user modules.
2. Configure user modules.
3. Organize and connect.
4. Generate, verify, and debug.
Select User Modules
PSoC Designer provides a library of prebuilt, pretested hardware
peripheral components called “user modules”. User modules
make selecting and implementing peripheral devices, both
analog and digital, simple.
Configure User Modules
Each user module that you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a PWM
User Module configures one or more digital PSoC blocks, one
for each eight bits of resolution. Using these parameters, you can
establish the pulse width and duty cycle. Configure the
parameters and properties to correspond to your chosen
application. Enter values directly or by selecting values from
drop-down menus. All of the user modules are documented in
datasheets that may be viewed directly in PSoC Designer or on
the Cypress website. These user module datasheets explain the
internal operation of the user module and provide performance
specifications. Each datasheet describes the use of each user
module parameter, and other information that you may need to
successfully implement your design.
Organize and Connect
Build signal chains at the chip level by interconnecting user
modules to each other and the I/O pins. Perform the selection,
configuration, and routing so that you have complete control over
all on-chip resources.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, perform the “Generate
Configuration Files” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system. The
generated code provides APIs with high-level functions to control
and respond to hardware events at run time, and interrupt
service routines that you can adapt as needed.
A complete code development environment lets you to develop
and customize your applications in C, assembly language, or
both.
The last step in the development process takes place inside
PSoC Designer’s Debugger (accessed by clicking the Connect
icon). PSoC Designer downloads the HEX image to the ICE
where it runs at full-speed. PSoC Designer debugging
capabilities rival those of systems costing many times more. In
addition to traditional single-step, run-to-breakpoint, and
watch-variable features, the debug interface provides a large
trace buffer. It lets you to define complex breakpoint events that
include monitoring address and data bus values, memory
locations, and external signals.
CY8C24X93
Document Number: 001-86894 Rev. *B Page 10 of 65
Pinouts
16-pin QFN (13 GPIOs) [2]
Table 2. Pin Definitions – CY8C24093 [3]
Pin
No. Type Name Description Figure 1. CY8C24093 Device
Digital Analog
1I/O IP2[5] Crystal output (XOut)
2I/O IP2[3] Crystal input (XIn)
3IOHR IP1[7] I2C SCL, SPI SS
4IOHR IP1[5] I2C SDA, SPI MISO
5IOHR IP1[3] SPI CLK
6IOHR IP1[1] ISSP CLK[4], I2C SCL, SPI
MOSI
7Power VSS Ground connection
8IOHR IP1[0] ISSP DATA[4], I2C SDA, SPI
CLK[5]
9IOHR IP1[2]
10 IOHR IP1[4] Optional external clock
(EXTCLK)
11 Input XRES Active high external reset with
internal pull-down
12 IOH IP0[4]
13 Power VDD Supply voltage
14 IOH IP0[7]
15 IOH IP0[3]
16 IOH IP0[1]
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
QFN
(Top View )
AI, XOut, P2[5]
AI , I2 C SCL, SPI SS, P1[7]
AI , I2 C SDA, SPI MISO, P1[5]
AI, SPI CL
K, P1[3]
1
2
3
4
11
10
9
16
15
14
13
P0[3], AI
P0[7], AI
VDD
P0[4] , AI
AI, ISSP CLK, SPI MOSI, P1[1]
AI, ISSP DATA , I2C SDA, SPI CL
K, P1[0]
P1[2] , AI
AI , XIn , P2[3]
P1[4] , EXTCLK, AI
XRES
P0[1], AI
VSS
12
5
6
7
8
Notes
2. No center pad.
3. 13 GPIOs.
4. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
5. Alternate SPI clock.
CY8C24X93
Document Number: 001-86894 Rev. *B Page 11 of 65
32-pin QFN (28 GPIOs) [6]
Table 3. Pin Definitions – CY8C24193 [7]
Pin
No. Type Name Description Figure 2. CY8C24193
Digital Analog
1IOH IP0[1]
2I/O IP2[7]
3I/O I P2[5] Crystal output (XOut)
4I/O IP2[3] Crystal input (XIn)
5I/O IP2[1]
6I/O IP3[3]
7I/O IP3[1]
8IOHR IP1[7] I2C SCL, SPI SS
9IOHR IP1[5] I2C SDA, SPI MISO
10 IOHR IP1[3] SPI CLK.
11 IOHR IP1[1] ISSP CLK[8], I2C SCL, SPI MOSI.
12 Power VSS Ground connection.
13 IOHR IP1[0] ISSP DATA[8], I2C SDA,
SPI CLK[9]
14 IOHR IP1[2]
15 IOHR IP1[4] Optional external clock input
(EXTCLK)
16 IOHR IP1[6]
17 Input XRES Active high external reset with
internal pull-down
18 I/O IP3[0]
19 I/O IP3[2]
20 I/O IP2[0]
21 I/O IP2[2]
22 I/O IP2[4]
23 I/O IP2[6]
24 IOH IP0[0]
25 IOH IP0[2]
26 IOH IP0[4]
27 IOH IP0[6]
28 Power VDD Supply voltage
29 IOH IP0[7]
30 IOH IP0[5]
31 IOH IP0[3]
32 Power VSS Ground connection
CP Power VSS Center pad must be connected to
ground
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
AI , P0[1]
AI , P2[7]
AI, XOut, P2[5]
AI, XIn, P2[3]
AI , P2[1]
AI , P3[3]
QFN
(Top View)
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
Vss
P0 [3], AI
P0 [7], AI
Vdd
P0 [6], AI
P0 [4], AI
P0 [2], AI
AI , P3[1]
AI , I2 C SCL, SPI SS, P1[7]
P0[0] , AI
P2[6] , AI
P3[0] , AI
XRES
AI, I2C SDA, SPI MI SO, P 1[5]
AI, SPI CLK, P1[3]
Vss
AI, P 1[ 2]
AI, E XT CLK , P 1[ 4]
AI, P 1[ 6]
P2[4] , AI
P2[2] , AI
P2[0] , AI
P3[2] , AI
P0 [5], AI
AI
, ISSP CLK , I2C SCL, SPI MOSI, P1[1]
AI,
ISSP DATA , I2C SDA, SPI CLK, P1[0]
[8]
[8]
Notes
6. 28 GPIOs.
7. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground,
it must be electrically floated and not connected to any other signal.
8. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
9. Alternate SPI clock.
CY8C24X93
Document Number: 001-86894 Rev. *B Page 12 of 65
32-pin QFN (28 GPIOs) [10]
Table 4. Pin Definitions – CY8C24293 [11]
Pin
No. Digital Analog Name Description Figure 3. CY8C24293 Device
1IOH IP0[1]
2I/O I P2[5] Crystal output (XOut)
3I/O I P2[3] Crystal input (XIn)
4I/O IP2[1]
5I/O IP4[3]
6I/O I P3[3]
7I/O IP3[1]
8IOHR IP1[7] I2C SCL, SPI SS
9IOHR IP1[5] I2C SDA, SPI MISO
10 IOHR IP1[3] SPI CLK.
11 IOHR IP1[1] ISSP CLK [12], I2C SCL, SPI MOSI.
12 Power VSS Ground connection
13 IOHR IP1[0] ISSP DATA[12], I2C SDA, SPI CLK[13]
14 IOHR IP1[2]
15 IOHR IP1[4] Optional external clock input
(EXTCLK)
16 IOHR IP1[6]
17 Input XRES Active high external reset with
internal pull-down
18 I/O I P3[0]
19 I/O I P3[2]
20 I/O I P4[0]
21 I/O IP4[2]
22 I/O IP2[0]
23 I/O IP2[2]
24 I/O IP2[4]
25 IOH IP0[0]
26 IOH IP0[2]
27 IOH IP0[4]
28 IOH IP0[6]
29 Power VDD
30 IOH IP0[7]
31 IOH IP0[3]
32 Power VSS Ground connection
CP Power VSS Center pad must be connected to
ground
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
AI
, P0[1]
AI
, P2[5]
AI , XOut
, P2[3]
AI , XIn
, P2[1]
AI , P4[3]
AI , P3[3]
QFN
(Top View)
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
Vs s
P0 [3 ], AI
P0[6], AI
V
DD
P0 [4 ], AI
P0 [2 ], AI
P0 [0 ], AI
AI , P3[1]
AI , I2 C SCL, SPI SS, P1[7]
P2[4] , AI
P2[2] , AI
P3[0] , AI
XRES
AI, I2C SDA, SPI MI SO, P1[ 5]
AI, SPI CLK, P1[3]
Vss
AI , P 1[ 2]
AI, EXTCLK, P 1[ 4]
AI , P 1[ 6]
P2[0] , AI
P4[2] , AI
P4[0] , AI
P3[2] , AI
P0 [7 ], AIAI,ISSP CLK , I2C SCL, SPI MOSI, P1[1]
AI,ISSP DAT A , I 2 C S DA , S PI C L K, P 1[ 0]
[12]
[12]
Notes
10. 28 GPIOs.
11. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground,
it must be electrically floated and not connected to any other signal.
12. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
13. Alternate SPI clock.
CY8C24X93
Document Number: 001-86894 Rev. *B Page 13 of 65
48-pin QFN (34 GPIOs) [14]
Table 5. Pin Definitions – CY8C24393, CY8C24693 [15, 16]
Pin
No. Digital Analog Name Description Figure 4. CY8C24393, CY8C24693 Device
1NC No connection
2I/O IP2[7]
3I/O I P2[5] Crystal output (XOut)
4I/O I P2[3] Crystal input (XIn)
5I/O IP2[1]
6I/O IP4[3]
7I/O I P4[1]
8I/O IP3[7]
9I/O IP3[5]
10 I/O IP3[3]
11 I/O IP3[1]
12 IOHR IP1[7] I2C SCL, SPI SS
13 IOHR IP1[5] I2C SDA, SPI MISO
14 NC No connection
15 NC No connection
16 IOHR IP1[3] SPI CLK
17 IOHR IP1[1] ISSP CLK[17], I2C SCL, SPI MOSI
18 Power VSS Ground connection
19 NC No connection
20 NC No connection
21 Power VDD Supply voltage Pin
No. Digital Analog Name Description
22 IOHR IP1[0] ISSP DATA[17], I2C SDA, SPI CLK[18] 36 NC No connection
23 IOHR IP1[2] 37 IOH IP0[0]
24 IOHR IP1[4] Optional external clock input
(EXTCLK)
38 IOH IP0[2]
25 IOHR IP1[6] 39 IOH IP0[4]
26 Input XRES Active high external reset with
internal pull-down
40 IOH IP0[6]
27 I/O IP3[0] 41 Power VDD Supply voltage
28 I/O I P3[2] 42 NC No connection
29 I/O I P3[4] 43 NC No connection
30 I/O I P3[6] 44 IOH IP0[7]
31 I/O IP4[0] 45 NC No connection
32 I/O IP4[2] 46 IOH IP0[3]
33 I/O IP2[0] 47 Power VSS Ground connection
34 I/O IP2[2] 48 IOH IP0[1]
35 I/O IP2[4] CP Power VSS Center pad must be connected to
ground
LEGENDA = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.
QFN
(To p Vi ew)
Vss
P0[3], AI
NC ,
P0[7], AI
Vdd
P0[6], AI
P0[2], AI
P0[0], AI
10
11
12
AI , P2[7]
NC
AI, XOut, P2[5]
AI , XIn , P2[3]
AI , P2[1]
AI , P4[3]
AI , P4[1]
AI , P3[7]
AI, P3[5]
AI, P3[3]
AI P3[1]
AI, I2 C SCL, SPI SS, P1[ 7 ]
35
34
33
32
31
30
29
28
27
26
25
36
48
47
46
45
44
43
42
41
40
39
38
37
P2[ 4],
AI
P2[ 2],
AI
P2[ 0],
AI
P4[ 2],
AI
P4[ 0],
AI
P3[ 6],
AI
P3[ 4],
AI
P3[ 2],
AI
P3[0], AI
XRES
P1[ 6], AI
NC
1
2
3
4
5
6
7
8
9
13
14
15
16
17
18
19
20
21
22
23
24
I2C SDA, SPI MISO,A I, P1[5]
NC
SPICLK,AI,P1[3]
AI, ISSP C LK,I2C S CL, SPI MOSI ,P1[1]
Vss
NC
NC
Vdd
AI, ISSP DATA
1
, I2C SDA, SPI CLK, P1[0]
AI, P1[2]
AI, EXTCLK, P1[4]
NC
NC
NC
P0[4], AI
P0[1],AI
Notes
14. 38 GPIOs.
15. This part is available in limited quantities for In-Circuit Debugging during prototype development. It is not available in production volumes.
16. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground,
it must be electrically floated and not connected to any other signal.
17. On Power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to High impedance state. On reset, after XRES de- asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. In both cases, a pull-up resistance on these lines combines with the pull-down resistance
(5.6K ohm) and form a potential divider. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues.
18. Alternate SPI clock.
CY8C24X93
Document Number: 001-86894 Rev. *B Page 14 of 65
48-pin QFN (36 GPIOs (With USB)) [19]
Table 6. Pin Definitions – CY8C24493 [20, 21]
Pin
No. Digital Analog Name Description Figure 5. CY8C24493
1NC No connection
2I/O IP2[7]
3I/O I P2[5] Crystal output (XOut)
4I/O I P2[3] Crystal input (XIn)
5I/O IP2[1]
6I/O IP4[3]
7I/O I P4[1]
8I/O IP3[7]
9I/O IP3[5]
10 I/O IP3[3]
11 I/O IP3[1]
12 IOHR IP1[7] I2C SCL, SPI SS
13 IOHR IP1[5] I2C SDA, SPI MISO
14 NC No connection
15 NC No connection
16 IOHR IP1[3] SPI CLK
17 IOHR IP1[1] ISSP CLK[20], I2C SCL, SPI MOSI
18 Power VSS Ground connection
19 I/O D+ USB D+
20 I/O D- USB D-
21 Power VDD Supply voltage
22 IOHR IP1[0] ISSP DATA[20], I2C SDA, SPI
CLK[22]
23 IOHR IP1[2]
24 IOHR IP1[4] Optional external clock input
(EXTCLK)
25 IOHR IP1[6]
26 Input XRES Active high external reset with
internal pull-down
27 I/O IP3[0]
28 I/O I P3[2]
29 I/O I P3[4] Pin
No. Digital Analog Name Description
30 I/O I P3[6] 40 IOH IP0[6]
31 I/O IP4[0] 41 Power VDD Supply voltage
32 I/O IP4[2] 42 NC No connection
33 I/O IP2[0] 43 NC No connection
34 I/O IP2[2] 44 IOH IP0[7]
35 I/O IP2[4] 45 IOH IP0[5]
36 I/O IP2[6] 46 IOH IP0[3]
37 IOH IP0[0] 47 Power VSS Ground connection
38 IOH IP0[2] 48 IOH IP0[1]
39 IOH IP0[4] CP Power VSS Center pad must be connected to ground
LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.
QFN
Vss
P0[3], AI
P0[5], AI
P0[7], AI
Vdd
P0[6], AI
P0[2], AI
P0[0], AI
AI , P2[7]
NC
AI, XOut, P2[5]
AI , XIn , P2[3]
AI , P2[1]
AI , P4[3]
AI , P4[1]
AI , P3[7]
AI , P3[5]
AI , P3[3]
AI , P3[1]
AI, I2 C SCL, SPI SS, P1[7]
35
34
33
32
36
48
47
46
45
44
43
42
41
40
39
38
37
P2[4] , AI
P2[2] , AI
P2[0] , AI
P4[2] , AI
P2[6] , AI
1
2
3
4
5
NC
NC
P0[4], AI
P0[1], AI
(Top View)
10
11
12
31
30
29
28
27
26
25
P4[0] , AI
P3[6] , AI
P3[4] , AI
P3[2] , AI
P3[0], AI
XRES
P1[6] , AI
6
7
8
9
13
14
15
16
17
18
19
20
21
22
23
24
I2C SDA, SPI MISO, AI, P1[5]
NC
SPI CLK, AI, P1[3]
AI,ISSP CLK,I2CSCL,SPIMOSI,P1[1]
Vss
D+
D-
Vdd
AI,ISSP DATA, I2C SDA, SPI CLK,P1[0]
AI, P1[2]
AI, EXTCLK, P1[4]
NC
[20, 22]
[20]
Notes
19. 36 GPIOs.
20. On Power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to High impedance state. On reset, after XRES de- asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. In both cases, a pull-up resistance on these lines combines with the pull-down resistance
(5.6K ohm) and form a potential divider. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues.
21. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground,
it must be electrically floated and not connected to any other signal.
22. Alternate SPI clock.
CY8C24X93
Document Number: 001-86894 Rev. *B Page 15 of 65
48-pin QFN (OCD) (36 GPIOs) [23]
The 48-pin QFN part is for the CY8C240093 On-Chip Debug (OCD). Note that this part is only used for in-circuit debugging.
Table 7. Pin Definitions – CY8C240093 [24, 25]
Pin
No. Digital Analog Name Description Figure 6. CY8C240093
1[26] OCDOE OCD mode direction pin
2I/O IP2[7]
3I/O I P2[5] Crystal output (XOut)
4I/O I P2[3] Crystal input (XIn)
5I/O IP2[1]
6I/O IP4[3]
7I/O I P4[1]
8I/O IP3[7]
9I/O IP3[5]
10 I/O IP3[3]
11 I/O IP3[1]
12 IOHR IP1[7] I2C SCL, SPI SS
13 IOHR IP1[5] I2C SDA, SPI MISO
14[26] CCLK OCD CPU clock output
15[26] HCLK OCD high speed clock output
16 IOHR IP1[3] SPI CLK.
17 IOHR IP1[1] ISSP CLK[27], I2C SCL, SPI
MOSI
18 Power VSS Ground connection
19 I/O D+ USB D+
20 I/O D- USB D-
21 Power VDD Supply voltage
22 IOHR IP1[0] ISSP DATA[27], I2C SDA, SPI
CLK[28]
23 IOHR IP1[2] Pin
No. Digital Analog Name Description
24 IOHR IP1[4] Optional external clock input
(EXTCLK)
37 IOH IP0[0]
25 IOHR IP1[6] 38 IOH IP0[2]
26 Input XRES Active high external reset with
internal pull-down
39 IOH IP0[4]
27 I/O IP3[0] 40 IOH IP0[6]
28 I/O I P3[2] 41 Power VDD Supply voltage
29 I/O I P3[4] 42[26] OCDO OCD even data I/O
30 I/O I P3[6] 43[26] OCDE OCD odd data output
31 I/O IP4[0] 44 IOH IP0[7]
32 I/O IP4[2] 45 IOH IP0[5]
33 I/O IP2[0] 46 IOH IP0[3]
34 I/O IP2[2] 47 Power VSS Ground connection
35 I/O IP2[4] 48 IOH IP0[1]
36 I/O IP2[6] CP Power VSS Center pad must be connected to
ground
LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.
QFN
(Top View)
Vss
P0[3], AI
P0[5], AI
P0[7], AI
Vdd
P0[6], AI
P0[2], AI
P0[0], AI
10
11
12
A
I, P2[7]
AI , XOut, P2[5]
AI, XIn , P2[3]
AI , P2[1]
AI , P4[3]
AI , P4[1]
AI , P3[7]
AI , P3[5]
AI , P3[3]
AI , P3[1]
AI , I2 C SCL, SPI SS, P1[7]
35
34
33
32
31
30
29
28
27
26
25
36
48
47
46
45
44
43
42
41
40
39
38
37
P2[4] , AI
P2[2] , AI
P2[0] , AI
P4[2] , AI
P4[0] , AI
P3[6] , AI
P3[4] , AI
P3[2] , AI
P3[0] , AI
XRES
P1[6] , AI
P2[6] , AI
1
2
3
4
5
6
7
8
9
13
14
15
16
17
18
19
20
21
22
23
24
I2C SDA, SPI MISO, AI, P1[5]
SPI CLK, AI, P1[3]
AI,ISSP CLK6, I2C SCL, SPI MOSI, P1[1]
Vss
D+
D-
Vdd
AI,ISSP DATA1, I2C SDA, SPI CLK, P1[0]
AI, P1[2]
AI, EXTCLK, P1[4]
P0[4], AI
P0[1], AI
OCDO
E
CCLK
HCLK
OCDE
OCDO
[27, 28]
[27]
Notes
23. 36 GPIOs.
24. This part is available in limited quantities for In-Circuit Debugging during prototype development. It is not available in production volumes.
25. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground,
it must be electrically floated and not connected to any other signal.
26. This pin (associated with OCD part only) is required for connecting the device to ICE-Cube In-Circuit Emulator for firmware debugging purpose. To know more about
the usage of ICE-Cube, refer to CY3215-DK PSoC® IN-CIRCUIT EMULATOR KIT GUIDE.
27. On Power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to High impedance state. On reset, after XRES de- asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. In both cases, a pull-up resistance on these lines combines with the pull-down resistance
(5.6K ohm) and form a potential divider. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues.
28. Alternate SPI clock.
CY8C24X93
Document Number: 001-86894 Rev. *B Page 16 of 65
Electrical Specifications (CY8C24193/493)
This section presents the DC and AC electrical specifications of the CY8C24193/493 PSoC devices. For the latest electrical
specifications, confirm that you have the most recent datasheet by visiting the web at http://www.cypress.com/psoc.
Figure 7. Voltage versus CPU Frequency
Absolute Maximum Ratings (CY8C24193/493)
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Operating Temperature (CY8C24193/493)
5.5 V
750 kHz 24 MHz
CPU Frequency
VDD Voltage
1.71 V
3 MHz
Valid
Operating
Region
Table 8. Absolute Maximum Ratings
Symbol Description Conditions Min Typ Max Units
TSTG Storage temperature Higher storage temperatures reduce data
retention time. Recommended Storage
Temperature is +25 °C ± 25 °C. Extended
duration storage temperatures above 85 °C
degrades reliability.
–55 +25 +125 °C
VDD Supply voltage relative to VSS ––0.5 –+6.0 V
VIO DC input voltage – VSS – 0.5 – VDD + 0.5 V
VIOZ DC voltage applied to tristate – VSS – 0.5 – VDD + 0.5 V
IMIO Maximum current into any port pin – –25 –+50 mA
ESD Electro static discharge voltage Human body model ESD 2000 – – V
LU Latch up current In accordance with JESD78 standard – – 200 mA
Table 9. Operating Temperature
Symbol Description Conditions Min Typ Max Units
TAAmbient temperature – –40 –+85 °C
TCCommercial temperature range – 070 °C
TJOperational die temperature The temperature rise from ambient to junction
is package specific. See the Thermal
Impedances on page 49. The user must limit
the power consumption to comply with this
requirement.
–40 –+100 °C
CY8C24X93
Document Number: 001-86894 Rev. *B Page 17 of 65
DC Chip-Level Specifications (CY8C24193/493)
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 10. DC Chip-Level Specifications
Symbol Description Conditions Min Typ Max Units
VDD[29, 43] Supply voltage See table DC POR and LVD Specifications
(CY8C24093/293/393/693) on page 37
1.71 –5.50 V
IDD24 Supply current, IMO = 24 MHz Conditions are VDD 3.0 V, TA = 25 °C,
CPU = 24 MHz.
–2.88 4.00 mA
IDD12 Supply current, IMO = 12 MHz Conditions are VDD 3.0 V, TA = 25 °C,
CPU = 12 MHz.
–1.71 2.60 mA
IDD6 Supply current, IMO = 6 MHz Conditions are VDD 3.0 V, TA = 25 °C,
CPU = 6 MHz.
–1.16 1.80 mA
ISB0 Deep sleep current VDD 3.0 V, TA = 25 °C, I/O regulator turned off –0.10 1.1 A
ISB1 Standby current with POR, LVD
and sleep timer
VDD 3.0 V, TA = 25 °C, I/O regulator turned off –1.07 1.50 A
ISBI2C Standby current with I2C
enabled
Conditions are VDD = 3.3 V, TA = 25 °C and
CPU = 24 MHz
–1.64 –A
Notes
29. When VDD remains in the range from 1.71 V to 1.9 V for more than 50 µs, the slew rate when moving from the 1.71 V to 1.9 V range to greater than 2 V must be
slower than 1 V/500 µs to avoid triggering POR. The only other restriction on slew rates for any other voltage range or transition is the SRPOWER_UP parameter.
30. If powering down in standby sleep mode, to properly detect and recover from a VDD brown out condition any of the following actions must be taken:
a. Bring the device out of sleep before powering down.
b. Assure that VDD falls below 100 mV before powering back up.
c. Set the No Buzz bit in the OSC_CR0 register to keep the voltage monitoring circuit powered during sleep.
d. Increase the buzz rate to assure that the falling edge of VDD is captured. The rate is configured through the PSSDC bits in the SLP_CFG register. For the referenced
registers, refer to the Technical Reference Manual. In deep sleep/standby sleep mode, additional low power voltage monitoring circuitry allows VDD brown out
conditions to be detected and resets the device when VDD goes lower than 1.1 V at edge rates slower than 1 V/ms.
CY8C24X93
Document Number: 001-86894 Rev. *B Page 18 of 65
DC GPIO Specifications (CY8C24193/493)
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and
–40 °C T
A 85 °C, 2.4 V to 3.0 V and –40 °C T
A 85 °C, or 1.71 V to 2.4 V and –40 °C T
A 85 °C, respectively. Typical
parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only.
Table 11. 3.0 V to 5.5 V DC GPIO Specifications
Symbol Description Conditions Min Typ Max Units
RPU Pull-up resistor – 4 5.60 8 k
VOH1 High output voltage
Port 2 or 3 pins
IOH < 10 A, maximum of 10 mA source
current in all I/Os
VDD – 0.20 – – V
VOH2 High output voltage
Port 2 or 3 Pins
IOH = 1 mA, maximum of 20 mA source
current in all I/Os
VDD – 0.90 – – V
VOH3 High output voltage
Port 0 or 1 pins with LDO regulator Disabled
for port 1
IOH < 10 A, maximum of 10 mA source
current in all I/Os
VDD – 0.20 – – V
VOH4 High output voltage
Port 0 or 1 pins with LDO regulator Disabled
for port 1
IOH = 5 mA, maximum of 20 mA source
current in all I/Os
VDD – 0.90 – – V
VOH5 High output voltage
Port 1 Pins with LDO Regulator Enabled for
3 V out
IOH < 10 A, VDD > 3.1 V, maximum of
4 I/Os all sourcing 5 mA
2.85 3.00 3.30 V
VOH6 High output voltage
Port 1 pins with LDO regulator enabled for
3 V out
IOH = 5 mA, VDD > 3.1 V, maximum of 20 mA
source current in all I/Os
2.20 – – V
VOH7 High output voltage
Port 1 pins with LDO enabled for 2.5 V out
IOH < 10 A, VDD > 2.7 V, maximum of 20 mA
source current in all I/Os
2.35 2.50 2.75 V
VOH8 High output voltage
Port 1 pins with LDO enabled for 2.5 V out
IOH = 2 mA, VDD > 2.7 V, maximum of 20 mA
source current in all I/Os
1.90 – – V
VOH9 High output voltage
Port 1 pins with LDO enabled for 1.8 V out
IOH < 10 A, VDD > 2.7 V, maximum of 20 mA
source current in all I/Os
1.60 1.80 2.10 V
VOH10 High output voltage
Port 1 pins with LDO enabled for 1.8 V out
IOH = 1 mA, VDD > 2.7 V, maximum of 20 mA
source current in all I/Os
1.20 – – V
VOL Low output voltage IOL = 25 mA, VDD > 3.3 V, maximum of 60 mA
sink current on even port pins (for example,
P0[2] and P1[4]) and 60 mA sink current on
odd port pins (for example, P0[3] and P1[5])
– – 0.75 V
VIL Input low voltage – – – 0.80 V
VIH Input high voltage – 2.00 – – V
VHInput hysteresis voltage – –80 –mV
IIL Input leakage (Absolute Value) – –0.00
1
1A
CPIN Pin capacitance Package and pin dependent
Temp = 25 °C
0.50 1.70 7pF
VILLVT3.3 Input Low Voltage with low threshold enable
set, Enable for Port1
Bit3 of IO_CFG1 set to enable low threshold
voltage of Port1 input
0.8 V – –
VIHLVT3.3 Input High Voltage with low threshold enable
set, Enable for Port1
Bit3 of IO_CFG1 set to enable low threshold
voltage of Port1 input
1.4 – – V
VILLVT5.5 Input Low Voltage with low threshold enable
set, Enable for Port1
Bit3 of IO_CFG1 set to enable low threshold
voltage of Port1 input
0.8 V – –
VIHLVT5.5 Input High Voltage with low threshold enable
set, Enable for Port1
Bit3 of IO_CFG1 set to enable low threshold
voltage of Port1 input
1.7 – – V
CY8C24X93
Document Number: 001-86894 Rev. *B Page 19 of 65
Table 12. 2.4 V to 3.0 V DC GPIO Specificatio ns
Symbol Description Conditions Min Typ Max Units
RPU Pull-up resistor – 4 5.60 8 k
VOH1 High output voltage
Port 2 or 3 pins
IOH < 10 A, maximum of 10 mA source
current in all I/Os
VDD - 0.20 – – V
VOH2 High output voltage
Port 2 or 3 Pins
IOH = 0.2 mA, maximum of 10 mA
source current in all I/Os
VDD - 0.40 – – V
VOH3 High output voltage
Port 0 or 1 pins with LDO regulator
Disabled for port 1
IOH < 10 A, maximum of 10 mA source
current in all I/Os
VDD - 0.20 – – V
VOH4 High output voltage
Port 0 or 1 pins with LDO regulator
Disabled for Port 1
IOH = 2 mA, maximum of 10 mA source
current in all I/Os
VDD - 0.50 – – V
VOH5A High output voltage
Port 1 pins with LDO enabled for 1.8 V
out
IOH < 10 A, VDD > 2.4 V, maximum of
20 mA source current in all I/Os
1.50 1.80 2.10 V
VOH6A High output voltage
Port 1 pins with LDO enabled for 1.8 V
out
IOH = 1 mA, VDD > 2.4 V, maximum of
20 mA source current in all I/Os
1.20 – – V
VOL Low output voltage IOL = 10 mA, maximum of 30 mA sink
current on even port pins (for example,
P0[2] and P1[4]) and 30 mA sink
current on odd port pins (for example,
P0[3] and P1[5])
– – 0.75 V
VIL Input low voltage – – – 0.72 V
VIH Input high voltage – 1.40 – V
VHInput hysteresis voltage – –80 –mV
IIL Input leakage (absolute value) – – 1 1000 nA
CPIN Capacitive load on pins Package and pin dependent
Temp = 25 C
0.50 1.70 7pF
VILLVT2.5 Input Low Voltage with low threshold
enable set, Enable for Port1
Bit3 of IO_CFG1 set to enable low
threshold voltage of Port1 input
0.7 V –
VIHLVT2.5 Input High Voltage with low threshold
enable set, Enable for Port1
Bit3 of IO_CFG1 set to enable low
threshold voltage of Port1 input
1.2 – V
CY8C24X93
Document Number: 001-86894 Rev. *B Page 20 of 65
Table 13. 1.71 V to 2.4 V DC GPIO Specifications
Symbol Description Conditions Min Typ Max Units
RPU Pull-up resistor – 4 5.60 8 k
VOH1 High output voltage
Port 2 or 3 pins
IOH = 10 A, maximum of 10 mA
source current in all I/Os
VDD – 0.20 – – V
VOH2 High output voltage
Port 2 or 3 pins
IOH = 0.5 mA, maximum of 10 mA
source current in all I/Os
VDD – 0.50 – – V
VOH3 High output voltage
Port 0 or 1 pins with LDO regulator
Disabled for Port 1
IOH = 100 A, maximum of 10 mA
source current in all I/Os
VDD – 0.20 – – V
VOH4 High output voltage
Port 0 or 1 Pins with LDO Regulator
Disabled for Port 1
IOH = 2 mA, maximum of 10 mA source
current in all I/Os
VDD – 0.50 – – V
VOL Low output voltage IOL = 5 mA, maximum of 20 mA sink
current on even port pins (for example,
P0[2] and P1[4]) and 30 mA sink
current on odd port pins (for example,
P0[3] and P1[5])
– – 0.40 V
VIL Input low voltage – – – 0.30 × VDD V
VIH Input high voltage – 0.65 × VDD ––V
VHInput hysteresis voltage – –80 –mV
IIL Input leakage (absolute value) – – 1 1000 nA
CPIN Capacitive load on pins Package and pin dependent
temp = 25 C
0.50 1.70 7pF
Table 14. GPIO Current Sink and Source Specifications
Supply
Voltage Mode Port 1 per I/O (max) Port 2/3/4 per
I/O (max) T otal Current Even
Pins (max) Total Current Odd
Pins (max) Units
1.71 – 2.4 Sink 5 5 20 30 mA
Source 2 0.5 10[31] mA
2.4 – 3.0 Sink 10 10 30 30 mA
Source 2 0.2 10[31] mA
3.0 – 5.0 Sink 25 25 60 60 mA
Source 5 1 20[31] mA
Note
31. Total current (odd + even ports)
CY8C24X93
Document Number: 001-86894 Rev. *B Page 21 of 65
DC Analog Mux Bus Specifications (CY8C24193/493)
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
DC Low Power Comparator Specifications (CY8C24193/493)
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Comparator User Module Electrical Specifications (CY8C24193/493)
The following table lists the guaranteed maximum and minimum specifications. Unless stated otherwise, the specifications are for the
entire device voltage and temperature operating range: –40 °C TA 85 °C, 1.71 V VDD 5.5 V.
Table 15. DC Analog Mux Bus Specifications
Symbol Description Conditions Min Typ Max Units
RSW Switch resistance to common analog
bus
– – – 800
RGND Resistance of initialization switch to
VSS
– – – 800
The maximum pin voltage for measuring RSW and RGND is 1.8 V
Table 16. DC Comparator Specifications
Symbol Description Conditions Min Typ Max Units
VLPC Low power comparator (LPC) common
mode
Maximum voltage limited to VDD 0.2 – 1.8 V
ILPC LPC supply current – – 10 80 A
VOSLPC LPC voltage offset – – 2.5 30 mV
Table 17. Comparator User Module Electrical Specifications
Symbol Description Conditions Min Typ Max Units
TCOMP Comparator response time 50 mV overdrive –70 100 ns
Offset Valid from 0.2 V to 1.5 V –2.5 30 mV
Current Average DC current, 50 mV
overdrive
–20 80 µA
PSRR Supply voltage > 2 V Power supply rejection ratio –80 –dB
Supply voltage < 2 V Power supply rejection ratio –40 –dB
Input range –0.2 1.5 V
CY8C24X93
Document Number: 001-86894 Rev. *B Page 22 of 65
ADC Electrical Specifications (CY8C24193/493)
Table 18. ADC User Module Electrical Specifications
Symbol Description Conditions Min Typ Max Units
Input
VIN Input voltage range – 0 – VREFADC V
CIIN Input capacitance –––5 pF
RIN Input resistance Equivalent switched cap input
resistance for 8-, 9-, or 10-bit
resolution
1/(500fF ×
data clock)
1/(400fF ×
data clock)
1/(300fF ×
data clock)
Reference
VREFADC ADC reference voltage – 1.14 – 1.26 V
Conversion Rate
FCLK Data clock Source is chip’s internal main
oscillator. See AC Chip-Level
Specifications on page 25 for
accuracy
2.25 – 6 MHz
S8 8-bit sample rate Data clock set to 6 MHz.
sample rate = 0.001/
(2^Resolution/Data Clock)
–23.43 –ksps
S10 10-bit sample rate Data clock set to 6 MHz.
sample rate = 0.001/
(2^resolution/data clock)
– 5.85 – ksps
DC Accuracy
RES Resolution Can be set to 8, 9, or 10 bit 8 – 10 bits
DNL Differential nonlinearity
– –1 – +2 LSB
INL Integral nonlinearity
– –2 – +2 LSB
EOFFSET Offset error 8-bit resolution 0 3.20 19.20 LSB
10-bit resolution 0 12.80 76.80 LSB
EGAIN Gain error For any resolution –5 – +5 %FSR
Power
IADC Operating current – – 2.10 2.60 mA
PSRR Power supply rejection ratio PSRR (VDD > 3.0 V) – 24 – dB
PSRR (VDD < 3.0 V) – 30 – dB
CY8C24X93
Document Number: 001-86894 Rev. *B Page 23 of 65
DC POR and LVD Specificat ions (CY8C24193/493)
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
DC Programming Specifications (CY8C24193/493)
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 19. DC POR and LVD Specifications
Symbol Description Conditions Min Typ Max Units
VPOR0 1.66 V selected in PSoC Designer VDD must be greater than or equal to 1.71 V
during startup, reset from the XRES pin, or
reset from watchdog.
1.61 1.66 1.71 V
VPOR1 2.36 V selected in PSoC Designer – 2.36 2.41
VPOR2 2.60 V selected in PSoC Designer – 2.60 2.66
VPOR3 2.82 V selected in PSoC Designer – 2.82 2.95
VLVD0 2.45 V selected in PSoC Designer – 2.40 2.45 2.51 V
VLVD1 2.71 V selected in PSoC Designer 2.64[46] 2.71 2.78
VLVD2 2.92 V selected in PSoC Designer 2.85[47] 2.92 2.99
VLVD3 3.02 V selected in PSoC Designer 2.95[48] 3.02 3.09
VLVD4 3.13 V selected in PSoC Designer 3.06 3.13 3.20
VLVD5 1.90 V selected in PSoC Designer 1.84 1.90 2.32
VLVD6 1.80 V selected in PSoC Designer 1.75[49] 1.80 1.84
VLVD7 4.73 V selected in PSoC Designer 4.62 4.73 4.83
Table 20. DC Programming Specifications
Symbol Description Conditions Min Typ Max Units
VDDIWRITE Supply voltage for flash write
operations
–1.71 –5.25 V
IDDP Supply current during
programming or verify
– – 5 25 mA
VILP Input low voltage during
programming or verify
See appropriate DC GPIO Specifications
(CY8C24093/293/393/693) on page 33
– – VIL V
VIHP Input high voltage during
programming or verify
See appropriate DC GPIO Specifications
(CY8C24093/293/393/693) on page 33
VIH – – V
IILP Input current when Applying VILP
to P1[0] or P1[1] during
programming or verify
Driving internal pull-down resistor – – 0.2 mA
IIHP Input current when applying VIHP
to P1[0] or P1[1] during
programming or verify
Driving internal pull-down resistor – – 1.5 mA
VOLP Output low voltage during
programming or verify
– – VSS + 0.75 V
VOHP Output high voltage during
programming or verify
See appropriate DC GPIO Specifications
(CY8C24093/293/393/693) on page 33.
For VDD > 3V use VOH4 in Table 36 on
page 33.
VOH – VDD V
FlashENPB Flash write endurance Erase/write cycles per block 50,000 – – –
FlashDR Flash data retention Following maximum Flash write cycles;
ambient temperature of 55 °C
20 – – Yea rs
Notes
32. Always greater than 50 mV above VPPOR1 voltage for falling supply.
33. Always greater than 50 mV above VPPOR2 voltage for falling supply.
34. Always greater than 50 mV above VPPOR3 voltage for falling supply.
35. Always greater than 50 mV above VPPOR0 voltage for falling supply.
CY8C24X93
Document Number: 001-86894 Rev. *B Page 24 of 65
DC I2C Specifications (CY8C24193/493)
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and
–40 °C T
A 85 °C, 2.4 V to 3.0 V and –40 °C T
A 85 °C, or 1.71 V to 2.4 V and –40 °C T
A 85 °C, respectively. Typical
parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only.
Shield Driver DC Specifications (CY8C24193/493)
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and
–40 °C T
A 85 °C, 2.4 V to 3.0 V and –40 °C T
A 85 °C, or 1.71 V to 2.4 V and –40 °C T
A 85 °C, respectively. Typical
parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only.
DC IDAC Specifications (CY8C24193/493)
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 21. DC I2C Specifications[36]
Symbol Description Conditions Min Typ Max Units
VILI2C Input low level 3.1 V ≤ VDD ≤ 5.5 V – – 0.25 × VDD V
2.5 V ≤ VDD ≤ 3.0 V – – 0.3 × VDD V
1.71 V ≤ VDD ≤ 2.4 V – – 0.3 × VDD V
VIHI2C Input high level 1.71 V ≤ VDD ≤ 5.5 V 0.65 × VDD –V
DD +
0.7 V[37] V
Table 22. Shield Driver DC Specifications
Symbol Description Conditions Min Typ Max Units
VRef Reference buffer output 1.7 V ≤ VDD ≤ 5.5 V 0.942 – 1.106 V
VRefHi Reference buffer output 1.7 V ≤ VDD ≤ 5.5 V 1.104 – 1.296 V
Table 23. DC IDAC Specifications (8-bit IDAC)
Symbol Description Min Typ Max Units Notes
IDAC_DNL Differential nonlinearity –1 – 1 LSB
IDAC_DNL Integral nonlinearity –2 – 2 LSB
IDAC_Current Range = 4x 138 – 169 µA DAC setting = 127 dec
Range = 8x 138 – 169 µA DAC setting = 64 dec
Table 24. DC IDAC Specifications (7-bit IDAC)
Symbol Description Min Typ Max Units Notes
IDAC_DNL Differential nonlinearity –1 – 1 LSB
IDAC_DNL Integral nonlinearity –2 – 2 LSB
IDAC_Current Range = 4x 137 – 168 µA DAC setting = 127 dec
Range = 8x 138 – 169 µA DAC setting = 64 dec
Notes
36. Pull-up resistors on I2C interface cannot be connected to a supply voltage that is more than 0.7 V higher than the CY8C24x93 power supply. See the CY8C24x93
Silicon Errata document for more details.
37. Please refer to Item # 6 of the CY8C24x93 Family.
CY8C24X93
Document Number: 001-86894 Rev. *B Page 25 of 65
AC Chip-Level Specifications (CY8C24193/493)
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 25. AC Chip-Level Specifications
Symbol Description Conditions Min Typ Max Units
FIMO24 IMO frequency at 24 MHz Setting –22.8 24 25.2 MHz
FIMO12 IMO frequency at 12 MHz setting –11.4 12 12.6 MHz
FIMO6 IMO frequency at 6 MHz setting –5.7 6.0 6.3 MHz
FCPU CPU frequency –0.75 –25.20 MHz
F32K1 ILO frequency –15 32 50 kHz
F32K_U ILO untrimmed frequency –13 32 82 kHz
DCIMO Duty cycle of IMO –40 50 60 %
DCILO ILO duty cycle –40 50 60 %
SRPOWER_UP Power supply slew rate VDD slew rate during power-up – – 250 V/ms
tXRST External reset pulse width at power-up After supply voltage is valid 1 – – ms
tXRST2 External reset pulse width after power-up[50] Applies after part has booted 10 – – s
tJIT_IMO[39] 6 MHz IMO cycle-to-cycle jitter (RMS) – – 0.7 6.7 ns
6 MHz IMO long term N cycle-to-cycle jitter
(RMS); N = 32
– – 4.3 29.3 ns
6 MHz IMO period jitter (RMS) – – 0.7 3.3 ns
12 MHz IMO cycle-to-cycle jitter (RMS) – – 0.5 5.2 ns
12 MHz IMO long term N cycle-to-cycle jitter
(RMS); N = 32
– – 2.3 5.6 ns
12 MHz IMO period jitter (RMS) – – 0.4 2.6 ns
24 MHz IMO cycle-to-cycle jitter (RMS) – – 1.0 8.7 ns
24 MHz IMO long term N cycle-to-cycle jitter
(RMS); N = 32
– – 1.4 6.0 ns
24 MHz IMO period jitter (RMS) – – 0.6 4.0 ns
Note
38. The minimum required XRES pulse length is longer when programming the device (see Table 55 on page 42).
39. See the Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information.
CY8C24X93
Document Number: 001-86894 Rev. *B Page 26 of 65
AC General Purpose I/O Specifications (CY8C24193/493)
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Figure 8. GPIO Timing Diagram
AC Comparator Specifications (CY8C24193/493)
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
AC External Clock Specific atio n s (CY8 C24 19 3/ 493 )
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 26. AC GPIO Specifications
Symbol Description Conditions Min Typ Max Units
FGPIO GPIO operating frequency Normal strong mode Port 0, 1 0
0
–
–
6 MHz for
1.71 V <VDD < 2.40 V
12 MHz for
2.40 V < VDD< 5.50 V
MHz
MHz
tRISE23 Rise time, strong mode, Cload = 50 pF
Ports 2 or 3
VDD = 3.0 to 3.6 V, 10% to 90% 15 – 80 ns
tRISE23L Rise time, strong mode low supply,
Cload = 50 pF, Ports 2 or 3
VDD = 1.71 to 3.0 V, 10% to 90% 15 – 80 ns
tRISE01 Rise time, strong mode, Cload = 50 pF
Ports 0 or 1
VDD = 3.0 to 3.6 V, 10% to 90%
LDO enabled or disabled
10 – 50 ns
tRISE01L Rise time, strong mode low supply,
Cload = 50 pF, Ports 0 or 1
VDD = 1.71 to 3.0 V, 10% to 90%
LDO enabled or disabled
10 – 80 ns
tFALL Fall time, strong mode, Cload = 50 pF
all ports
VDD = 3.0 to 3.6 V, 10% to 90% 10 – 50 ns
tFALLL Fall time, strong mode low supply,
Cload = 50 pF, all ports
VDD = 1.71 to 3.0 V, 10% to 90% 10 – 70 ns
TFall
TRise23
TRise01
90%
10%
GPIO Pin
Output
Voltage
TRise23L
TRise01L
TFallL
Table 27. AC Low Power Comparator Specifications
Symbol Description Conditions Min Typ Max Units
tLPC Comparator response time,
50 mV overdrive
50 mV overdrive does not include
offset voltage.
––100ns
Table 28. AC External Clock Specifications
Symbol Description Conditions Min Typ Max Units
FOSCEXT Frequency (external oscillator
frequency)
–0.75– 25.20 MHz
High period – 20.60 –5300 ns
Low period – 20.60 ––ns
Power-up IMO to switch – 150 – – s
CY8C24X93
Document Number: 001-86894 Rev. *B Page 27 of 65
AC Programming Specifications (CY8C24193/493 )
Figure 9. AC Waveform
The following table lists the guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 29. AC Programming Specifications
Symbol Description Conditions Min Typ Max Units
tRSCLK Rise time of SCLK – 1 – 20 ns
tFSCLK Fall time of SCLK – 1 – 20 ns
tSSCLK Data setup time to falling edge of SCLK – 40 – – ns
tHSCLK Data hold time from falling edge of SCLK – 40 – – ns
FSCLK Frequency of SCLK – 0 – 8 MHz
tERASEB Flash erase time (block) – – – 18 ms
tWRITE Flash block write time – – – 25 ms
tDSCLK Data out delay from falling edge of SCLK 3.6 VDD – – 60 ns
tDSCLK3 Data out delay from falling edge of SCLK 3.0 VDD 3.6 – – 85 ns
tDSCLK2 Data out delay from falling edge of SCLK 1.71 VDD 3.0 – – 130 ns
tXRST3 External reset pulse width after power-up Required to enter programming
mode when coming out of sleep
300 – – s
tXRES XRES pulse length – 300 – – s
tVDDWAIT VDD stable to wait-and-poll hold off – 0.1 – 1 ms
tVDDXRES VDD stable to XRES assertion delay – 14.27 – – ms
tPOLL SDAT high pulse time – 0.01 –200 ms
tACQ “Key window” time after a VDD ramp
acquire event, based on 256 ILO clocks.
–3.20 –19.60 ms
tXRESINI “Key window” time after an XRES event,
based on 8 ILO clocks
–98 –615 s
SCLK (P1[1])
TRSCLK TFSCLK
SDATA (P1[0])
TSSCLK THSCLK TDSCLK
CY8C24X93
Document Number: 001-86894 Rev. *B Page 28 of 65
AC I2C Specifications (CY8C24193/493)
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Figure 10. Definition for Timing for Fast/Standard Mode on the I2C Bus
Table 30. AC Characteristics of the I2C SDA and SCL Pins
Symbol Description Standard
Mode Fast Mode Units
Min Max Min Max
fSCL SCL clock frequency 0 100 0 400 kHz
tHD;STA Hold time (repeated) START condition. After this period, the first clock pulse is
generated
4.0 –0.6–µs
tLOW LOW period of the SCL clock 4.7 –1.3–µs
tHIGH HIGH Period of the SCL clock 4.0 –0.6–µs
tSU;STA Setup time for a repeated START condition 4.7 –0.6–µs
tHD;DAT[40] Data hold time 20 3.45 20 0.90 µs
tSU;DAT Data setup time 250 – 100[53] –ns
tSU;STO Setup time for STOP condition 4.0 –0.6–µs
tBUF Bus free time between a STOP and START condition 4.7 –1.3–µs
tSP Pulse width of spikes are suppressed by the input filter ––050ns
Notes
40. To wake up from sleep using I2C hardware address match event, I2C interface needs 20 ns hold time on SDA line with respect to falling edge of SCL. See the
CY8C24x93 Silicon Errata document for more details.
41. A Fast-Mode I2C-bus device can be used in a standard mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This automatically be the
case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
CY8C24X93
Document Number: 001-86894 Rev. *B Page 29 of 65
Figure 11. SPI Master Mode 0 and 2
Figure 12. SPI Master Mode 1 and 3
Table 31. SPI Master AC Specifications
Symbol Description Conditions Min Typ Max Units
FSCLK SCLK clock frequency VDD 2.4 V
VDD < 2.4 V
–
–
–
–
6
3
MHz
MHz
DC SCLK duty cycle – – 50 – %
tSETUP MISO to SCLK setup time VDD 2.4 V
VDD < 2.4 V
60
100
–
–
–
–
ns
ns
tHOLD SCLK to MISO hold time – 40 – – ns
tOUT_VAL SCLK to MOSI valid time – – – 40 ns
tOUT_H MOSI high time – 40 – – ns
1/FSCLK
TLOW THIGH
TOUT_H
THOLD
TSETUP
TOUT_SU
MSB LSB
SPI Master, m od es 0 and 2
SCLK
(mode 0)
SCLK
(mode 2)
MISO
(input)
MOSI
(output)
1/FSCLK
THIGH TLOW
TOUT_H
THOLD
TSETUP
SCLK
(mode 1)
SCLK
(mode 3)
MISO
(input)
MOSI
(output)
SPI Master, modes 1 and 3
TOUT_SU
MSB
MSB LSB
LSB
CY8C24X93
Document Number: 001-86894 Rev. *B Page 30 of 65
Figure 13. SPI Slave Mode 0 and 2
Figure 14. SPI Slave Mode 1 and 3
Table 32. SPI Slave AC Specifications
Symbol Description Conditions Min Typ Max Units
FSCLK SCLK clock frequency – – – 4 MHz
tLOW SCLK low time – 42 – – ns
tHIGH SCLK high time – 42 – – ns
tSETUP MOSI to SCLK setup time – 30 – – ns
tHOLD SCLK to MOSI hold time – 50 – – ns
tSS_MISO SS high to MISO valid – – – 153 ns
tSCLK_MISO SCLK to MISO valid – – – 125 ns
tSS_HIGH SS high time – 50 – – ns
tSS_CLK Time from SS low to first SCLK – 2/SCLK – – ns
tCLK_SS Time from last SCLK to SS high – 2/SCLK – – ns
TCLK_SS TSS_HIGH
1/FSCLK
TLOW THIGH
TOUT_H
THOLD
TSETUP
TSS_MISO
TSS_CLK
MSB LSB
SPI Slave, modes 0 and 2
/SS
SCLK
(mode 0)
SCLK
(mode 2)
MISO
(output)
MOSI
(input)
TCLK_SS
1/FSCLK
THIGH TLOW
TSCLK_MISO
TOUT_H
THOLD
TSETUP
TSS_CLK
/SS
SCLK
(mode 1)
SCLK
(mode 3)
MISO
(output)
MOSI
(input)
SPI Slave, modes 1 and 3
TSS_MISO
MSB
MSB LSB
LSB
CY8C24X93
Document Number: 001-86894 Rev. *B Page 31 of 65
Electrical Specifications (CY8C24093/293/393/693)
This section presents the DC and AC electrical specifications of the CY8C24093/293/393/693 PSoC devices. For the latest electrical
specifications, confirm that you have the most recent datasheet by visiting the web at http://www.cypress.com/psoc.
Figure 15. Voltage versus CPU Frequency
Absolute Maximu m Ratings (CY8C24093/2 93/393/693)
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Operating Temperature (CY8C24093/293/393/693)
5.5V
750 kHz 24 MHz
CPU Frequency
Vdd Voltage
1.71V
3 MHz
Valid
Operating
Region
Table 33. Absolute Maximum Ratings
Symbol Description Conditions Min Typ Max Units
TSTG Storage temperature Higher storage temperatures reduce data
retention time. Recommended Storage
Temperature is +25 °C ± 25 °C. Extended
duration storage temperatures above 85 °C
degrades reliability.
–55 +25 +125 °C
VDD Supply voltage relative to VSS ––0.5 –+6.0 V
VIO DC input voltage – VSS – 0.5 – VDD + 0.5 V
VIOZ[42] DC voltage applied to tristate – VSS – 0.5 – VDD + 0.5 V
IMIO Maximum current into any port pin – –25 –+50 mA
ESD Electrostatic discharge voltage Human body model ESD 2000 – – V
LU Latch-up current In accordance with JESD78 standard – – 200 mA
Table 34. Operating Temperature
Symbol Description Conditions Min Typ Max Units
TAAmbient temperature – –40 –+85 °C
TCCommercial temperature range – 070 °C
TJOperational die temperature The temperature rise from ambient to
junction is package specific. Refer the
Thermal Impedances on page 49. The user
must limit the power consumption to comply
with this requirement.
–40 –+100 °C
Note
42. Port1 pins are hot-swap capable with I/O configured in High-Z mode, and pin input voltage above VDD.
CY8C24X93
Document Number: 001-86894 Rev. *B Page 32 of 65
DC Chip-Level Specifications (CY8C24093/293/393/693)
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 35. DC Chip-Level Specifications
Symbol Description Conditions Min Typ Max Units
VDD[43, 44, 45] Supply voltage No USB activity. Refer the table DC POR
and LVD Specifications
(CY8C24093/293/393/693) on page 37
1.71 –5.50 V
VDDUSB[43, 44, 45] Operating voltage USB activity, USB regulator enabled 4.35 –5.25 V
USB activity, USB regulator bypassed 3.15 3.3 3.60 V
IDD24 Supply current, IMO = 24 MHz Conditions are VDD 3.0 V, TA = 25 °C,
CPU = 24 MHz. No I/O sourcing current
– – 4.00 mA
IDD12 Supply current, IMO = 12 MHz Conditions are VDD 3.0 V, TA = 25 °C,
CPU = 12 MHz. No I/O sourcing current
– – 2.60 mA
IDD6 Supply current, IMO = 6 MHz Conditions are VDD 3.0 V, TA = 25 °C,
CPU = 6 MHz. No I/O sourcing current
– – 1.80 mA
ISB0 Deep sleep current VDD 3.0 V, TA = 25 °C, I/O regulator
turned off
–0.10 1.05 A
ISB1 Standby current with POR, LVD
and sleep timer
VDD 3.0 V, TA = 25 °C, I/O regulator
turned off
–1.07 1.50 A
ISBI2C Standby current with I2C
enabled
Conditions are VDD = 3.3 V, TA = 25 °C
and CPU = 24 MHz
–1.64 –A
Notes
43. When VDD remains in the range from 1.71 V to 1.9 V for more than 50 µs, the slew rate when moving from the 1.71 V to 1.9 V range to greater than 2 V must be
slower than 1 V/500 µs to avoid triggering POR. The only other restriction on slew rates for any other voltage range or transition is the SRPOWER_UP parameter.
44. If powering down in standby sleep mode, to properly detect and recover from a VDD brown out condition any of the following actions must be taken:
a.Bring the device out of sleep before powering down.
b.Assure that VDD falls below 100 mV before powering back up.
c.Set the No Buzz bit in the OSC_CR0 register to keep the voltage monitoring circuit powered during sleep.
d.Increase the buzz rate to assure that the falling edge of VDD is captured. The rate is configured through the PSSDC bits in the SLP_CFG register.
For the referenced registers, refer to the CY8C24x93 Technical Reference Manual . In deep sleep mode, additional low power voltage monitoring circuitry allows
VDD brown out conditions to be detected for edge rates slower than 1V/ms.
45. For USB mode, the VDD supply for bus-powered application should be limited to 4.35 V–5.35 V. For self-powered application, VDD should be 3.15 V–3.45 V.
CY8C24X93
Document Number: 001-86894 Rev. *B Page 33 of 65
DC GPIO Specifications (CY8C24093/293/393/693)
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and
–40 °C T
A 85 °C, 2.4 V to 3.0 V and –40 °C T
A 85 °C, or 1.71 V to 2.4 V and –40 °C T
A 85 °C, respectively. Typical
parameters apply to 5 V and 3.3 V at 25 C and are for design guidance only.
Table 36. 3.0 V to 5.5 V DC GPIO Specifications
Symbol Description Conditions Min Typ Max Units
RPU Pull-up resistor – 4 5.60 8 k
VOH1 High output voltage
Port 2 or 3 or 4 pins
IOH < 10 A, maximum of 10 mA source
current in all I/Os
VDD – 0.20 – – V
VOH2 High output voltage
Port 2 or 3 or 4 pins
IOH = 1 mA, maximum of 20 mA source
current in all I/Os
VDD – 0.90 – – V
VOH3 High output voltage
Port 0 or 1 pins with LDO regulator
Disabled for port 1
IOH < 10 A, maximum of 10 mA source
current in all I/Os
VDD – 0.20 – – V
VOH4 High output voltage
Port 0 or 1 pins with LDO regulator
Disabled for port 1
IOH = 5 mA, maximum of 20 mA source
current in all I/Os
VDD – 0.90 – – V
VOH5 High output voltage
Port 1 Pins with LDO Regulator Enabled
for 3 V out
IOH < 10 A, VDD > 3.1 V, maximum of 4 I/Os
all sourcing 5 mA
2.85 3.00 3.30 V
VOH6 High output voltage
Port 1 pins with LDO regulator enabled for
3 V out
IOH = 5 mA, VDD > 3.1 V, maximum of 20 mA
source current in all I/Os
2.20 – – V
VOH7 High output voltage
Port 1 pins with LDO enabled for 2.5 V out
IOH < 10 A, VDD > 2.7 V, maximum of 20 mA
source current in all I/Os
2.35 2.50 2.75 V
VOH8 High output voltage
Port 1 pins with LDO enabled for 2.5 V out
IOH = 2 mA, VDD > 2.7 V, maximum of 20 mA
source current in all I/Os
1.90 – – V
VOH9 High output voltage
Port 1 pins with LDO enabled for 1.8 V out
IOH < 10 A, VDD > 2.7 V, maximum of 20 mA
source current in all I/Os
1.60 1.80 2.10 V
VOH10 High output voltage
Port 1 pins with LDO enabled for 1.8 V out
IOH = 1 mA, VDD > 2.7 V, maximum of 20 mA
source current in all I/Os
1.20 – – V
VOL Low output voltage IOL = 25 mA, VDD > 3.3 V, maximum of
60 mA sink current on even port pins (for
example, P0[2] and P1[4]) and 60 mA sink
current on odd port pins (for example, P0[3]
and P1[5])
––0.75V
VIL Input low voltage – – – 0.80 V
VIH Input high voltage – 2.00 – – V
VHInput hysteresis voltage – –80 –mV
IIL Input leakage (Absolute Value) – –0.001 1A
CPIN Pin capacitance Package and pin dependent
Temp = 2 5 ° C
0.50 1.70 7pF
VILLVT3.3 Input Low Voltage with low threshold
enable set, Enable for Port1
Bit3 of IO_CFG1 set to enable low threshold
voltage of Port1 input
0.8 V – –
VIHLVT3.3 Input High Voltage with low threshold
enable set, Enable for Port1
Bit3 of IO_CFG1 set to enable low threshold
voltage of Port1 input
1.4 – – V
VILLVT5.5 Input Low Voltage with low threshold
enable set, Enable for Port1
Bit3 of IO_CFG1 set to enable low threshold
voltage of Port1 input
0.8 V – –
VIHLVT5.5 Input High Voltage with low threshold
enable set, Enable for Port1
Bit3 of IO_CFG1 set to enable low threshold
voltage of Port1 input
1.7 – – V
CY8C24X93
Document Number: 001-86894 Rev. *B Page 34 of 65
Table 37. 2.4 V to 3.0 V DC GPIO Specificatio ns
Symbol Description Conditions Min Typ Max Units
RPU Pull-up resistor – 4 5.60 8 k
VOH1 High output voltage
Port 2 or 3 or 4 pins
IOH < 10 A, maximum of 10 mA source
current in all I/Os
VDD – 0.20 – – V
VOH2 High output voltage
Port 2 or 3 or 4 pins
IOH = 0.2 mA, maximum of 10 mA source
current in all I/Os
VDD – 0.40 – – V
VOH3 High output voltage
Port 0 or 1 pins with LDO regulator
Disabled for port 1
IOH < 10 A, maximum of 10 mA source
current in all I/Os
VDD – 0.20 – – V
VOH4 High output voltage
Port 0 or 1 pins with LDO regulator
Disabled for Port 1
IOH = 2 mA, maximum of 10 mA source
current in all I/Os
VDD – 0.50 – – V
VOH5A High output voltage
Port 1 pins with LDO enabled for 1.8 V out
IOH < 10 A, VDD > 2.4 V, maximum of
20 mA source current in all I/Os
1.50 1.80 2.10 V
VOH6A High output voltage
Port 1 pins with LDO enabled for 1.8 V out
IOH = 1 mA, VDD > 2.4 V, maximum of 20 mA
source current in all I/Os
1.20 – – V
VOL Low output voltage IOL = 10 mA, maximum of 30 mA sink
current on even port pins (for example,
P0[2] and P1[4]) and 30 mA sink current on
odd port pins (for example, P0[3] and P1[5])
– – 0.75 V
VIL Input low voltage – – – 0.72 V
VIH Input high voltage – 1.40 – V
VHInput hysteresis voltage – –80 –mV
IIL Input leakage (absolute value) – – 1 1000 nA
CPIN Capacitive load on pins Package and pin dependent
Temp = 25 C
0.50 1.70 7pF
VILLVT2.5 Input Low Voltage with low threshold
enable set, Enable for Port1
Bit3 of IO_CFG1 set to enable low threshold
voltage of Port1 input
0.7 V –
VIHLVT2.5 Input High Voltage with low threshold
enable set, Enable for Port1
Bit3 of IO_CFG1 set to enable low threshold
voltage of Port1 input
1.2 – V
Table 38. 1.71 V to 2.4 V DC GPIO Specifications
Symbol Description Conditions Min Typ Max Units
RPU Pull-up resistor – 4 5.60 8 k
VOH1 High output voltage
Port 2 or 3 or 4 pins
IOH = 10 A, maximum of 10 mA
source current in all I/Os
VDD – 0.20 – – V
VOH2 High output voltage
Port 2 or 3 or 4 pins
IOH = 0.5 mA, maximum of 10 mA
source current in all I/Os
VDD – 0.50 – – V
VOH3 High output voltage
Port 0 or 1 pins with LDO regulator
Disabled for Port 1
IOH = 100 A, maximum of 10 mA
source current in all I/Os
VDD – 0.20 – – V
VOH4 High output voltage
Port 0 or 1 Pins with LDO Regulator
Disabled for Port 1
IOH = 2 mA, maximum of 10 mA source
current in all I/Os
VDD – 0.50 – – V
VOL Low output voltage IOL = 5 mA, maximum of 20 mA sink
current on even port pins (for example,
P0[2] and P1[4]) and 30 mA sink
current on odd port pins (for example,
P0[3] and P1[5])
– – 0.40 V
CY8C24X93
Document Number: 001-86894 Rev. *B Page 35 of 65
DC Analog Mux Bus Specifications (CY8C24093/293/393/693)
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
DC Low Power Comparator Specifications (CY8C24093/293/393/693)
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
VIL Input low voltage – – – 0.30 × VDD V
VIH Input high voltage – 0.65 × VDD ––V
VHInput hysteresis voltage – –80 –mV
IIL Input leakage (absolute value) – – 1 1000 nA
CPIN Capacitive load on pins Package and pin dependent
temp = 25 °C
0.50 1.70 7pF
Table 38. 1.71 V to 2.4 V DC GPIO Specifications (continued)
Symbol Description Conditions Min Typ Max Units
Table 39. DC Characteristics – USB Interface
Symbol Description Conditions Min Typ Max Units
RUSBI USB D+ pull-up resistance With idle bus 900 – 1575
RUSBA USB D+ pull-up resistance While receiving traffic 1425 – 3090
VOHUSB Static output high – 2.8 –3.6V
VOLUSB Static output low – – –0.3V
VDI Differential input sensitivity – 0.2 –V
VCM Differential input common mode range – 0.8 –2.5V
VSE Single ended receiver threshold – 0.8 –2.0V
CIN Transceiver capacitance – – –50pF
IIO High Z state data line leakage On D+ or D- line –10 –+10A
RPS2 PS/2 pull-up resistance – 3000 5000 7000
REXT External USB series resistor In series with each USB pin 21.78 22.0 22.22
Table 40. DC Analog Mux Bus Specifications
Symbol Description Conditions Min Typ Max Units
RSW Switch resistance to common analog bus – – – 800
RGND Resistance of initialization switch to VSS – – – 800
The maximum pin voltage for measuring RSW and RGND is 1.8 V
Table 41. DC Comparator Specifications
Symbol Description Conditions Min Typ Max Units
VLPC Low power comparator (LPC) common
mode
Maximum voltage limited to VDD 0.0 – 1.8 V
ILPC LPC supply current – – 10 40 A
VOSLPC LPC voltage offset – – 3 30 mV
CY8C24X93
Document Number: 001-86894 Rev. *B Page 36 of 65
Comparator User Module Electrical Specifications (CY8C24093/293/393/693)
The following table lists the guaranteed maximum and minimum specifications. Unless stated otherwise, the specifications are for the
entire device voltage and temperature operating range: –40 °C TA 85 °C, 1.71 V VDD 5.5 V.
ADC Electrical Specifications (CY8C24093/293/393/693)
Table 42. Comparator User Module Electrical Specifications
Symbol Description Conditions Min Typ Max Units
tCOMP Comparator response time 50 mV overdrive –70 100 ns
Offset Valid from 0.2 V to VDD – 0.2 V –2.5 30 mV
Current Average DC current, 50 mV
overdrive
–20 80 µA
PSRR Supply voltage > 2 V Power supply rejection ratio –80 –dB
Supply voltage < 2 V Power supply rejection ratio –40 –dB
Input range – 0 1.5 V
Table 43. ADC User Module Electrical Specifications
Symbol Description Conditions Min Typ Max Units
Input
VIN Input voltage range – 0 – VREFADC V
CIIN Input capacitance –––5pF
RIN Input resistance Equivalent switched cap input
resistance for 8-, 9-, or 10-bit
resolution
1/(500fF ×
data clock)
1/(400fF ×
data clock)
1/(300fF ×
data clock)
Reference
VREFADC ADC reference voltage – 1.14 – 1.26 V
Conversion Rate
FCLK Data clock Source is chip’s internal main
oscillator. See AC Chip-Level
Specifications for accuracy
2.25 – 6 MHz
S8 8-bit sample rate Data clock set to 6 MHz. sample
rate = 0.001/ (2^Resolution/Data
Clock)
– 23.43 – ksps
S10 10-bit sample rate Data clock set to 6 MHz. sample
rate = 0.001/ (2^resolution/data
clock)
– 5.85 – ksps
DC Accuracy
RES Resolution Can be set to 8-, 9-, or 10-bit 8 – 10 bits
DNL Differential nonlinearity – –1 – +2 LSB
INL Integral nonlinearity – –2 – +2 LSB
EOFFSET Offset error 8-bit resolution 0 3.20 19.20 LSB
10-bit resolution 0 12.80 76.80 LSB
EGAIN Gain error For any resolution –5 – +5 %FSR
Power
IADC Operating current – – 2.10 2.60 mA
PSRR Power supply rejection ratio PSRR (VDD > 3.0 V) – 24 – dB
PSRR (VDD < 3.0 V) – 30 – dB
CY8C24X93
Document Number: 001-86894 Rev. *B Page 37 of 65
DC POR and LVD Specificati ons (CY8C24093/293/393/693)
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
DC Programming Specifications (CY8C24093/293/393/693)
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 44. DC POR and LVD Specifications
Symbol Description Conditions Min Typ Max Units
VPOR0 1.66 V selected in PSoC Designer VDD must be greater than or equal
to 1.71 V during startup, reset
from the XRES pin, or reset from
watchdog.
1.61 1.66 1.71 V
VPOR1 2.36 V selected in PSoC Designer – 2.36 2.41
VPOR2 2.60 V selected in PSoC Designer – 2.60 2.66
VPOR3 2.82 V selected in PSoC Designer – 2.82 2.95
VLVD0 2.45 V selected in PSoC Designer – 2.40 2.45 2.51 V
VLVD1 2.71 V selected in PSoC Designer 2.64[46] 2.71 2.78
VLVD2 2.92 V selected in PSoC Designer 2.85[47] 2.92 2.99
VLVD3 3.02 V selected in PSoC Designer 2.95[48] 3.02 3.09
VLVD4 3.13 V selected in PSoC Designer 3.06 3.13 3.20
VLVD5 1.90 V selected in PSoC Designer 1.84 1.90 2.32
VLVD6 1.80 V selected in PSoC Designer 1.75[49] 1.80 1.84
VLVD7 4.73 V selected in PSoC Designer 4.62 4.73 4.83
Table 45. DC Programming Specifications
Symbol Description Conditions Min Typ Max Units
VDDIWRITE Supply voltage for flash write
operations
–1.71 –5.25 V
IDDP Supply current during
programming or verify
– – 5 25 mA
VILP Input low voltage during
programming or verify
See the appropriate DC GPIO
Specifications (CY8C24093/293/393/693)
on page 33
– – VIL V
VIHP Input high voltage during
programming or verify
See the appropriate DC GPIO
Specifications (CY8C24093/293/393/693)
on page 33
VIH – – V
IILP Input current when Applying VILP
to P1[0] or P1[1] during
programming or verify
Driving internal pull-down resistor – – 0.2 mA
IIHP Input current when applying VIHP
to P1[0] or P1[1] during
programming or verify
Driving internal pull-down resistor – – 1.5 mA
VOLP Output low voltage during
programming or verify
– – VSS + 0.75 V
VOHP Output high voltage during
programming or verify
See appropriate DC GPIO Specifications
(CY8C24093/293/393/693) on page 33. For
VDD > 3 V use VOH4 in Table 34 on page 31.
VOH – VDD V
FlashENPB Flash write endurance Erase/write cycles per block 50,000 – – –
FlashDR Flash data retention Following maximum Flash write cycles;
ambient temperature of 55 °C
20 – – Years
Notes
46. Always greater than 50 mV above VPPOR1 voltage for falling supply.
47. Always greater than 50 mV above VPPOR2 voltage for falling supply.
48. Always greater than 50 mV above VPPOR3 voltage for falling supply.
49. Always greater than 50 mV above VPPOR0 voltage for falling supply.
CY8C24X93
Document Number: 001-86894 Rev. *B Page 38 of 65
DC I2C Specifications (CY8C24093/293/393/693)
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and
–40 °C T
A 85 °C, 2.4 V to 3.0 V and –40 °C T
A 85 °C, or 1.71 V to 2.4 V and –40 °C T
A 85 °C, respectively. Typical
parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only.
DC Reference Buffer Specifications (CY8C24093/293/393/693)
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and
–40 °C T
A 85 °C, 2.4 V to 3.0 V and –40 °C T
A 85 °C, or 1.71 V to 2.4 V and –40 °C T
A 85 °C, respectively. Typical
parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only.
DC IDAC Specifications (CY8C24093/293/393/693)
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 46. DC I2C Specifications
Symbol Description Conditions Min Typ Max Units
VILI2C Input low level 3.1 V ≤ VDD ≤ 5.5 V – – 0.25 × VDD V
2.5 V ≤ VDD ≤ 3.0 V – – 0.3 × VDD V
1.71 V ≤ VDD ≤ 2.4 V – – 0.3 × VDD V
VIHI2C Input high level 1.71 V ≤ VDD ≤ 5.5 V 0.65 × VDD ––V
Table 47. DC Reference Buffer Specifications
Symbol Description Conditions Min Typ Max Units
VRef Reference buffer output 1.7 V ≤ VDD ≤ 5.5 V 1 – 1.05 V
VRefHi Reference buffer output 1.7 V ≤ VDD ≤ 5.5 V 1.2 – 1.25 V
Table 48. DC IDAC Specifications
Symbol Description Min Typ Max Units Notes
IDAC_DNL Differential nonlinearity –4.5 – +4.5 LSB
IDAC_INL Integral nonlinearity –5 – +5 LSB
IDAC_Gain
(Source)
Range = 0.5x 6.64 – 22.46 µA DAC setting = 128 dec
Range = 1x 14.5 – 47.8 µA
Range = 2x 42.7 – 92.3 µA
Range = 4x 91.1 – 170 µA DAC setting = 128 dec
Range = 8x 184.5 – 426.9 µA DAC setting = 128 dec
CY8C24X93
Document Number: 001-86894 Rev. *B Page 39 of 65
AC Chip-Level Specifications (CY8C24093/293/393/693)
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 49. AC Chip-Level Specifications
Symbol Description Conditions Min Typ Max Units
FIMO24 IMO frequency at 24 MHz Setting –22.8 24 25.2 MHz
FIMO12 IMO frequency at 12 MHz setting –11.4 12 12.6 MHz
FIMO6 IMO frequency at 6 MHz setting –5.7 6.0 6.3 MHz
FCPU CPU frequency –0.75 –25.20 MHz
F32K1 ILO frequency –15 32 50 kHz
F32K_U ILO untrimmed frequency –13 32 82 kHz
DCIMO Duty cycle of IMO –40 50 60 %
DCILO ILO duty cycle –40 50 60 %
SRPOWER_UP Power supply slew rate VDD slew rate during power-up – – 250 V/ms
tXRST External reset pulse width at power-up After supply voltage is valid 1 – – ms
tXRST2 External reset pulse width after
power-up[50] Applies after part has booted 10 – – s
tOS Startup time of ECO ––1–s
tJIT_IMO[51] N=32 6 MHz IMO cycle-to-cycle jitter (RMS) – 0.7 6.7 ns
6 MHz IMO long term N (N = 32)
cycle-to-cycle jitter (RMS)
– 4.3 29.3 ns
6 MHz IMO period jitter (RMS) – 0.7 3.3 ns
12 MHz IMO cycle-to-cycle jitter (RMS) – 0.5 5.2 ns
12 MHz IMO long term N (N = 32)
cycle-to-cycle jitter (RMS)
–2.35.6ns
12 MHz IMO period jitter (RMS) – 0.4 2.6 ns
24 MHz IMO cycle-to-cycle jitter (RMS) – 1.0 8.7 ns
24 MHz IMO long term N (N = 32)
cycle-to-cycle jitter (RMS)
–1.46.0ns
24 MHz IMO period jitter (RMS) – 0.6 4.0 ns
Notes
50. The minimum required XRES pulse length is longer when programming the device (see Table 55 on page 42).
51. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information.
CY8C24X93
Document Number: 001-86894 Rev. *B Page 40 of 65
AC GPIO Specifications (CY8C24093/293/393/693)
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Figure 16. GPIO Timing Diagram
Table 50. AC GPIO Specifications
Symbol Description Conditions Min Typ Max Units
FGPIO GPIO operating frequency Normal strong mode Port 0, 1 0
0
–
–
6 MHz for
1.71 V <VDD < 2.40 V
12 MHz for
2.40 V < VDD< 5.50 V
MHz
MHz
tRISE23 Rise time, strong mode, Cload = 50 pF
Port 2 or 3 or 4 pins
VDD = 3.0 to 3.6 V, 10% to 90% 15 – 80 ns
tRISE23L Rise time, strong mode low supply,
Cload = 50 pF, Port 2 or 3 or 4 pins
VDD = 1.71 to 3.0 V, 10% to 90% 15 – 80 ns
tRISE01 Rise time, strong mode, Cload = 50 pF
Ports 0 or 1
VDD = 3.0 to 3.6 V, 10% to 90%
LDO enabled or disabled
10 – 50 ns
tRISE01L Rise time, strong mode low supply,
Cload = 50 pF, Ports 0 or 1
VDD = 1.71 to 3.0 V, 10% to 90%
LDO enabled or disabled
10 – 80 ns
tFALL Fall time, strong mode, Cload = 50 pF
all ports
VDD = 3.0 to 3.6 V, 10% to 90% 10 – 50 ns
tFALLL Fall time, strong mode low supply,
Cload = 50 pF, all ports
VDD = 1.71 to 3.0 V, 10% to 90% 10 – 70 ns
tFALL
tRISE23
tRISE01
90%
10%
GPIO Pin
Output
Voltage
tRISE23L
tRISE01L
tFALLL
CY8C24X93
Document Number: 001-86894 Rev. *B Page 41 of 65
AC Comparator Specifications (CY8C24093/293/393/693)
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
AC External Clock Specifications (CY8C24093/293/393/693)
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 51. AC Characteristics – USB Data Timings
Symbol Description Conditions Min Typ Max Units
tDRATE Full speed data rate Average bit rate 12 – 0.25% 12 12 + 0.25% MHz
tJR1 Receiver jitter tolerance To next transition –18.5 – 18.5 ns
tJR2 Receiver jitter tolerance To pair transition –9.0 – 9 ns
tDJ1 FS Driver jitter To next transition –3.5 – 3.5 ns
tDJ2 FS Driver jitter To pair transition –4.0 – 4.0 ns
tFDEOP Source jitter for differential
transition
To SE0 transition –2.0 – 5 ns
tFEOPT Source SE0 interval of EOP – 160.0 – 175 ns
tFEOPR Receiver SE0 interval of EOP – 82.0 – – ns
tFST Width of SE0 interval during
differential transition
–––14ns
Table 52. AC Characteristics – USB Driver
Symbol Description Conditions Min Typ Max Units
tFR Transition rise time 50 pF 4 – 20 ns
tFF Transition fall time 50 pF 4 – 20 ns
tFRFM[52] Rise/fall time matching – 90 – 111 %
VCRS Output signal crossover voltage – 1.30 – 2.00 V
Table 53. AC Low Power Comparator Specifications
Symbol Description Conditions Min Typ Max Units
tLPC Comparator response time,
50 mV overdrive
50 mV overdrive does not include
offset voltage.
––100ns
Table 54. AC External Clock Specifications
Symbol Description Conditions Min Typ Max Units
FOSCEXT Frequency (external oscillator
frequency)
–0.75– 25.20 MHz
High period – 20.60 –5300 ns
Low period – 20.60 ––ns
Power-up IMO to switch – 150 – – s
Note
52. TFRFM is not met under all conditions. There is a corner case at lower supply voltages, such as those under 3.3 V. This condition does not affect USB communications.
Signal integrity tests show an excellent eye diagram at 3.15 V.
CY8C24X93
Document Number: 001-86894 Rev. *B Page 42 of 65
AC Programming Specifications (CY8C24093/293/393/693)
Figure 17. AC Waveform
The following table lists the guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 55. AC Programming Specifications
Symbol Description Conditions Min Typ Max Units
tRSCLK Rise time of SCLK – 1 – 20 ns
tFSCLK Fall time of SCLK – 1 – 20 ns
tSSCLK Data setup time to falling edge of SCLK – 40 – – ns
tHSCLK Data hold time from falling edge of SCLK – 40 – – ns
FSCLK Frequency of SCLK – 0 – 8 MHz
tERASEB Flash erase time (block) – – – 18 ms
tWRITE Flash block write time – – – 25 ms
tDSCLK Data out delay from falling edge of SCLK 3.6 VDD – – 60 ns
tDSCLK3 Data out delay from falling edge of SCLK 3.0 VDD 3.6 – – 85 ns
tDSCLK2 Data out delay from falling edge of SCLK 1.71 VDD 3.0 – – 130 ns
tXRST3 External reset pulse width after power-up Required to enter programming
mode when coming out of sleep
300 – – s
tXRES XRES pulse length – 300 – – s
tVDDWAIT VDD stable to wait-and-poll hold off – 0.1 – 1 ms
tVDDXRES VDD stable to XRES assertion delay – 14.27 – – ms
tPOLL SDATA high pulse time – 0.01 –200 ms
tACQ “Key window” time after a VDD ramp
acquire event, based on 256 ILO clocks.
–3.20 –19.60 ms
tXRESINI “Key window” time after an XRES event,
based on 8 ILO clocks
–98 –615 s
SCLK (P1[1])
TRSCLK TFSCLK
SDATA (P1[0])
TSSCLK THSCLK TDSCLK
CY8C24X93
Document Number: 001-86894 Rev. *B Page 43 of 65
AC I2C Specifications (CY8C24093/293/393/693)
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Figure 18. Definition for Timing for Fast/Standard Mode on the I2C Bus
Table 56. AC Characteristics of the I2C SDA and SCL Pins
Symbol Description Standard Mode Fast Mode Units
Min Max Min Max
fSCL SCL clock frequency 0 100 0 400 kHz
tHD;STA Hold time (repeated) START condition. After this period, the first
clock pulse is generated
4.0 –0.6–µs
tLOW LOW period of the SCL clock 4.7 –1.3–µs
tHIGH HIGH Period of the SCL clock 4.0 –0.6–µs
tSU;STA Setup time for a repeated START condition 4.7 –0.6–µs
tHD;DAT Data hold time 0 3.45 0 0.90 µs
tSU;DAT Data setup time 250 – 100[53] –ns
tSU;STO Setup time for STOP condition 4.0 –0.6–µs
tBUF Bus free time between a STOP and START condition 4.7 –1.3–µs
tSP Pulse width of spikes are suppressed by the input filter ––050ns
Note
53. A Fast-Mode I2C-bus device can be used in a standard mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This automatically be the
case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
CY8C24X93
Document Number: 001-86894 Rev. *B Page 44 of 65
Figure 19. SPI Master Mode 0 and 2
Figure 20. SPI Master Mode 1 and 3
Table 57. SPI Master AC Specifications
Symbol Description Conditions Min Typ Max Units
FSCLK SCLK clock frequency VDD 2.4 V
VDD < 2.4 V
–
–
–
–
6
3
MHz
MHz
DC SCLK duty cycle – – 50 – %
tSETUP MISO to SCLK setup time VDD 2.4 V
VDD < 2.4 V
60
100
–
–
–
–
ns
ns
tHOLD SCLK to MISO hold time – 40 – – ns
tOUT_VAL SCLK to MOSI valid time – – – 40 ns
tOUT_H MOSI high time – 40 – – ns
1/FSCLK
TLOW THIGH
TOUT_H
THOLD
TSETUP
TOUT_SU
MSB LSB
SPI Master, m od es 0 and 2
SCLK
(mode 0)
SCLK
(mode 2)
MISO
(input)
MOSI
(output)
1/FSCLK
THIGH TLOW
TOUT_H
THOLD
TSETUP
SCLK
(mode 1)
SCLK
(mode 3)
MISO
(input)
MOSI
(output)
SPI Master, modes 1 and 3
TOUT_SU
MSB
MSB LSB
LSB
CY8C24X93
Document Number: 001-86894 Rev. *B Page 45 of 65
Figure 21. SPI Slave Mode 0 and 2
Figure 22. SPI Slave Mode 1 and 3
Table 58. SPI Slave AC Specifications
Symbol Description Conditions Min Typ Max Units
FSCLK SCLK clock frequency – – – 4 MHz
tLOW SCLK low time – 42 – – ns
tHIGH SCLK high time – 42 – – ns
tSETUP MOSI to SCLK setup time – 30 – – ns
tHOLD SCLK to MOSI hold time – 50 – – ns
tSS_MISO SS high to MISO valid – – – 153 ns
tSCLK_MISO SCLK to MISO valid – – – 125 ns
tSS_HIGH SS high time – 50 – – ns
tSS_CLK Time from SS low to first SCLK – 2/SCLK – – ns
tCLK_SS Time from last SCLK to SS high – 2/SCLK – – ns
TCLK_SS TSS_HIGH
1/FSCLK
TLOW THIGH
TOUT_H
THOLD
TSETUP
TSS_MISO
TSS_CLK
MSB LSB
SPI Slave, modes 0 and 2
/SS
SCLK
(mode 0)
SCLK
(mode 2)
MISO
(output)
MOSI
(input)
TCLK_SS
1/FSCLK
THIGH TLOW
TSCLK_MISO
TOUT_H
THOLD
TSETUP
TSS_CLK
/SS
SCLK
(mode 1)
SCLK
(mode 3)
MISO
(output)
MOSI
(input)
SPI Slave, modes 1 and 3
TSS_MISO
MSB
MSB LSB
LSB
CY8C24X93
Document Number: 001-86894 Rev. *B Page 46 of 65
Packaging Information
This section illustrates the packaging specifications for the CY8C24X93 PSoC device, along with the thermal impedances for each
package.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/design/MR10161.
Figure 23. 32- pi n QFN (5 × 5 × 0.55 mm) LQ32 3.5 × 3.5 E-Pad (Sawn) Package Outline, 001-42168
001-42168 *E
CY8C24X93
Document Number: 001-86894 Rev. *B Page 47 of 65
Figure 24. 16-pin Chip On Lead (3 × 3 × 0.6 mm) LG16A/LD16A (Sawn) Package Ou tline, 001-09116
Figure 25. 48-pin QFN (6 × 6 × 0.6 mm) LQ48A 4.6 × 4.6 E-Pad (Sawn) Package Outline, 001-57280
001-09116 *H
001-57280 *E
CY8C24X93
Document Number: 001-86894 Rev. *B Page 48 of 65
Figure 26. 48-pin QFN (7 × 7 × 1.0 mm) LT48A 5.1 × 5.1 E-Pad (SAWN) Package Outline, 001-13191
Important Notes
■For information on the preferred dimensions for mounting QFN packages, see the following Application Note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
■Pinned vias for thermal conduction are not required for the low power PSoC device.
001-13191 *G
CY8C24X93
Document Number: 001-86894 Rev. *B Page 49 of 65
Thermal Impedances
Capacita nce on Crystal Pins
Solder Reflow Specifications
Table 61 shows the solder reflow temperature limits that must not be exceeded.
Table 59. Thermal Impedances per Package
Package Typical JA [54] Typical JC
16-pin QFN (No Center Pad) 33 C/W –
32-pin QFN [55] 20 C/W –
48-pin QFN (6 × 6 × 0.6 mm) [55] 25.20 C/W 3.04 C/W
48-pin QFN (7 × 7 × 1.0 mm) [55] 18 C/W –
Table 60. Typical Package Capacitance on Crystal Pins
Package Package Cap acitance
32-pin QFN 3.2 pF
48-pin QFN 3.3 pF
Table 61. Solder Reflow Specifications
Package Maximum Peak Temperature (TC)Maximum Time above TC – 5 °C
16-pin QFN 260 C30 seconds
32-pin QFN 260 C30 seconds
48-pin QFN (6 × 6 × 0.6 mm) 260 C30 seconds
48-pin QFN (7 × 7 × 1.0 mm) 260 C30 seconds
Notes
54. TJ = TA + Power × JA.
55. To achieve the thermal impedance specified for the QFN package, the center thermal pad must be soldered to the PCB ground plane.
CY8C24X93
Document Number: 001-86894 Rev. *B Page 50 of 65
Development Tool Selection
Software
PSoC Designer™
At the core of the PSoC development software suite is PSoC
Designer. Utilized by thousands of PSoC developers, this robust
software has been facilitating PSoC designs for over half a
decade. PSoC Designer is available free of charge at
http://www.cypress.com.
PSoC Programmer
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or it can operate
directly from PSoC Designer. PSoC Programmer software is
compatible with both PSoC ICE-Cube In-Circuit Emulator and
PSoC MiniProg. PSoC Programmer is available free of charge
at http://www.cypress.com.
Development Kits
All development kits are sold at the Cypress Online Store.
CY3215-DK Basic Development Kit
The CY3215-DK is for prototyping and development with PSoC
Designer. This kit supports in-circuit emulation and the software
interface enables users to run, halt, and single step the
processor and view the content of specific memory locations.
PSoC Designer supports the advance emulation features also.
The kit includes:
■PSoC Designer Software CD
■ICE-Cube In-Circuit Emulator
■ICE Flex-Pod for CY8C29X66A Family
■Cat-5 Adapter
■Mini-Eval Programming Board
■110 ~ 240 V Power Supply, Euro-Plug Adapter
■iMAGEcraft C Compiler (Registration Required)
■ISSP Cable
■USB 2.0 Cable and Blue Cat-5 Cable
■2 CY8C29466A-24PXI 28-PDIP Chip Samples
Evaluation Tools
All evaluation tools are sold at the Cypress Online Store. For
more information on PSoC 1 kits, visit the link
http://www.cypress.com/?rID=63754
Device Programmers
All device programmers are purchased from the Cypress Online
Store.
CY8C24X93
Document Number: 001-86894 Rev. *B Page 51 of 65
Ordering Information
The following table lists the CY8C24X93 PSoC devices' key package features and ordering codes.
Ordering Code Definitions
Table 62. PSoC Device Key Features and Ordering Information
Package Ordering Code Flash
(Bytes) SRAM
(Bytes) Digital
I/O Pins Analog
Inputs [56] XRES
Pin USB ADC Supported
by OCD
16-pin QFN
(3 × 3 × 0.6 mm)
CY8C24093-24LKXI 8 K 1 K 13 13 Yes No Yes No
32-pin QFN
(5 × 5 × 0.6 mm)
CY8C24193-24LQXI 8 K 1 K 28 28 Yes No Yes Yes
32-pin QFN
(5 × 5 × 0.6 mm)
CY8C24293-24LQXI 16 K 2 K 28 28 Yes No Yes No
48-pin QFN
(6 × 6 × 0.6 mm)
CY8C24393-24LQXI 16 K 2 K 34 34 Yes No Yes No
48-pin QFN
(7 × 7 × 1.0 mm)
CY8C24493-24LTXI 32 K 2 K 36 36 Yes Yes Yes Yes
48-pin QFN
(6 × 6 × 0.6 mm)
CY8C24693-24LQXI 32 K 2 K 34 34 Yes No Yes No
48-pin QFN (OCD)
(7 × 7 × 1.0 mm)
CY8C240093-24LTXI 32 K 2 K 36 36 Yes Yes Yes –
X = blank or T
blank = Tube; T = Tape and Reel
Temperature range:
I = Industrial
Pb-free
Package Type:
LK = 16-pin QFN; LQ = 32-pin QFN or 48-pin QFN
Speed Grade: 24 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = PSoC
Company ID: CY = Cypress
C24 X93 -24 XXX XCY 8 I
Note
56. Dual-function Digital I/O Pins also connect to the common analog mux.
CY8C24X93
Document Number: 001-86894 Rev. *B Page 52 of 65
Acronyms
Table 63. Acronyms Used in this Document
Acronym Description
AC Alternating Current
ADC Analog-to-Digital Converter
API Application Programming Interface
CMOS Complementary Metal Oxide Semiconductor
CPU Central Processing Unit
DAC Digital-to-Analog Converter
DC Direct Current
EOP End Of Packet
FSR Full Scale Range
GPIO General Purpose Input/Output
GUI Graphical User Interface
I2CInter-Integrated Circuit
ICE In-Circuit Emulator
IDAC Digital Analog Converter Current
ILO Internal Low Speed Oscillator
IMO Internal Main Oscillator
I/O Input/Output
ISSP In-System Serial Programming
LCD Liquid Crystal Display
LDO Low Dropout (regulator)
LSB Least-Significant Bit
LVD Low Voltage Detect
MCU Micro-Controller Unit
MIPS Mega Instructions Per Second
MISO Master In Slave Out
MOSI Master Out Slave In
MSB Most-Significant Bit
OCD On-Chip Debugger
POR Power On Reset
PPOR precision power on reset
PSRR Power Supply Rejection Ratio
PWRSYS Power System
PSoC®Programmable System-on-Chip
SLIMO Slow Internal Main Oscillator
SRAM Static Random Access Memory
SNR Signal to Noise Ratio
QFN Quad Flat No-lead
SCL Serial I2C Clock
SDA Serial I2C Data
SDATA Serial ISSP Data
SPI Serial Peripheral Interface
SS Slave Select
SSOP Shrink Small Outline Package
TC Test Controller
USB Universal Serial Bus
USB D+ USB Data+
USB D– USB Data–
WLCSP Wafer Level Chip Scale Package
XTAL Crystal
Table 63. Acronyms Used in this Document (continued)
Acronym Description
CY8C24X93
Document Number: 001-86894 Rev. *B Page 53 of 65
Document Conventions
Units of Measure
Reference Documents
■Technical refe rence manual for CY8C24x93 devices
■In-system Serial Programming (ISSP) protocol for CY8C24x93
(AN2026C)
■Host Sourced Serial Programming for CY8C24x93 devices
(AN59389)
Numeric Naming
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, 01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are
decimal.
Table 64. Units of Measure
Symbol Unit of Measure
°C degree Celsius
dB decibel
fF femtofarad
ggram
Hz hertz
KB 1024 bytes
Kbit 1024 bits
KHz kilohertz
Ksps kilo samples per second
kkilohm
MHz megahertz
Mmegaohm
Amicroampere
Fmicrofarad
Hmicrohenry
smicrosecond
Wmicrowatt
mA milliampere
ms millisecond
mV millivolt
nA nanoampere
nF nanofarad
ns nanosecond
nV nanovolt
Wohm
pA picoampere
pF picofarad
pp peak-to-peak
ppm parts per million
ps picosecond
sps samples per second
ssigma: one standard deviation
Vvolt
Wwatt
CY8C24X93
Document Number: 001-86894 Rev. *B Page 54 of 65
Glossary
Crosspoint connection Connection between any GPIO combination via analog multiplexer bus.
Differential non-linearity Ideally, any two adjacent digital codes correspond to output analog voltages that are exactly
one LSB apart. Differential non-linearity is a measure of the worst case deviation from the
ideal 1 LSB step.
Hold time Hold time is the time following a clock event during which the data input to a latch or flip-flop
must remain stable in order to guarantee that the latched data is correct.
I2C It is a serial multi-master bus used to connect low speed peripherals to MCU.
Integral nonlinearity It is a term describing the maximum deviation between the ideal output of a DAC/ADC and
the actual output level.
Latch-up current Current at which the latch-up test is conducted according to JESD78 standard (at 125
degree Celsius)
Power supply rejection ratio (PSRR) The PSRR is defined as the ratio of the change in supply voltage to the corresponding
change in output voltage of the device.
Setup time Period required to prepare a device, machine, process, or system for it to be ready to
function.
SPI Serial peripheral interface is a synchronous serial data link standard.
CY8C24X93
Document Number: 001-86894 Rev. *B Page 55 of 65
Appendix A: Silicon Errata for th e CY8C24093/293/393/693 Family
This section describes the errata for the CY8C24093/293/393/693 family. Details include errata trigger conditions, scope of impact,
available workarounds, and silicon revision applicability.
Contact your local Cypress Sales Representative if you have questions.
CY8C24093/293/393/693 Qualification Status
Product Status: Production released.
CY8C24093/293/393/693 Errata Summary
The following Errata items apply to the CY8C24093/293/393/693 datasheet 001-86894.
1. DoubleTimer0 ISR
■Problem Definition
When programmable timer 0 is used in “one-shot” mode by setting bit 1 of register 0,B0h (PT0_CFG), and the timer interrupt is
used to wake the device from sleep, the interrupt service routine (ISR) may be executed twice.
■Parameters Affected
No datasheet parameters are affected.
■Trigger Condition(S)
Triggered by enabling one-shot mode in the timer, and using the timer to wake from sleep mode.
■Scope of Impact
The ISR may be executed twice.
■Workaround
In the ISR, firmware should clear the one-shot bit with a statement such as “and reg[B0h], FDh”
■Fix Status
Will not be fixed
■Changes
None
CY8C24X93
Document Number: 001-86894 Rev. *B Page 56 of 65
2. Missed GPIO Interrupt
■Problem Definition
When in sleep mode, if a GPIO interrupt happens simultaneously with a Timer0 or Sleep Timer interrupt, the GPIO interrupt may
be missed, and the corresponding GPIO ISR not run.
■Parameters Affected
No datasheet parameters are affected.
■Trigger Condition(S)
Triggered by enabling sleep mode, then having GPIO interrupt occur simultaneously with a Timer 0 or Sleep Timer interrupt.
■Scope of Impact
The GPIO interrupt service routine will not be run.
■Workaround
The system should be architected such that a missed GPIO interrupt may be detected. For example, if a GPIO is used to wake
the system to perform some function, the system should detect if the function is not performed, and re-issue the GPIO interrupt.
Alternatively, if a GPIO interrupt is required to wake the system, then firmware should disable the Sleep Timer and Timer0.
Alternatively, the ISR’s for Sleep Timer and Timer0 should manually check the state of the GPIO to determine if the host system
has attempted to generate a GPIO interrupt.
■Fix Status
Will not be fixed
■Changes
None
3. Missed Interrupt During Transition to Sleep
■Problem Definition
If an interrupt is posted a short time (within 2.5 CPU cycles) before firmware commands the device to sleep, the interrupt will be
missed.
■Parameters Affected
No datasheet parameters are affected.
■Trigger Condition(S)
Triggered by enabling sleep mode just prior to an interrupt.
■Scope of Impact
The relevant interrupt service routine will not be run.
■Workaround
None.
■Fix Status
Will not be fixed
■Changes
None
CY8C24X93
Document Number: 001-86894 Rev. *B Page 57 of 65
4. Wakeup from sleep with analog interrupt
■Problem Definition
Device wakes up from sleep when an analog interrupt is trigger
■Parameters Affected
No datasheet parameters are affected.
■Trigger Condition(S)
Triggered by enabling analog interrupt during sleep mode when device operating temperature is 50 °C or above
■Scope of Impact
Device unexpectedly wakes up from sleep
■Workaround
Disable the analog interrupt before entering sleep and turn it back on upon wake-up.
■Fix Status
Will not be fixed
■Changes
None
CY8C24X93
Document Number: 001-86894 Rev. *B Page 58 of 65
5. Wake-up fr om Sleep with Hardware I2C Address match on Pins P1[0], P1[1]
■Problem Definition
I2C interface needs 20 ns hold time on SDA line with respect to falling edge of SCL, to wake-up from sleep using I2C hardware
address match event.
■Parameters Affected
tHD;DAT increased to 20 ns from 0 ns
■Trigger Condition(S)
This is an issue only when all these three conditions are met:
1) P1.0 and P1.1 are used as I2C pins,
2) Wakeup from sleep with hardware address match feature is enabled, and
3) I2C master does not provide 20 ns hold time on SDA with respect to falling edge of SCL.
■Scope of Impact
These trigger conditions cause the device to never wake-up from sleep based on I2C address match event
■Workaround
For a design that meets all of the trigger conditions, the following suggested circuit has to be implemented as a work-around. The
R and C values proposed are 100 ohm and 200 pF respectively.
■Fix Status
Will not be fixed
■Changes
None
CY8C24093/
293/393/693
CY8C24X93
Document Number: 001-86894 Rev. *B Page 59 of 65
6. I2C Port Pin Pull-up Supply Voltage
■Problem Definition
Pull-up resistor on I2C interface cannot be connected to a supply voltage that is greater than 0.7 V of CY8C24093/293/393/693
VDD.
■Parameters Affected
None.
■Trigger Condition(S)
This problem occurs only when the I2C master is powered at a higher voltage than CY8C24093/293/393/693.
■Scope of Impact
This trigger condition will corrupt the I2C communication between the I2C host and the CY8C24093/293/393/693 controller.
■Workaround
I2C master cannot be powered at a supply voltage that is greater than 0.7 V compared to CY8C24093/293/393/693 supply voltage.
■Fix Status
Will not be fixed
■Changes
None
7. Port1 Pin Voltage
■Problem Definition
Pull-up resistor on port1 pins cannot be connected to a voltage that is greater than 0.7 V higher than CY8C24093/293/393/693 VDD.
■Parameters Affected
None.
■Trigger Condition(S)
This problem occurs only when port1 pins are at voltage 0.7 V higher than VDD of CY8C24093/293/393/693.
■Scope of Impact
This trigger condition will not allow CY8C24093/293/393/693 to drive the output signal on port1 pins, input path is unaffected by
this condition.
■Workaround
Port1 should not be connected to a higher voltage than VDD of CY8C24093/293/393/693.
■Fix Status
Will not be fixed
■Changes
None
CY8C24X93
Document Number: 001-86894 Rev. *B Page 60 of 65
Appendix B: Silicon Errata for the PSoC® CY8C24193/493 Families
This section describes the errata for the PSoC® CY8C24193/493 families. Details include errata trigger conditions, scope of impact,
available workarounds, and silicon revision applicability.
Contact your local Cypress Sales Representative if you have questions.
CY8C24193/493 Qualification Status
Product Status: Production released.
CY8C24193/493 Errata Summary
The following Errata items apply to the CY8C24193/493 datasheet 001-86894.
1. Wakeup from sleep may intermittently fail
■Problem Definition
When the device is put to sleep in Standby or I2C_USB Mode and the bandgap circuit is refreshed less frequently than every 8 ms
(default), the device may not come out of sleep when a sleep-ending input is received.
■Parameters Affected
None
■Trigger Condition(S)
By default, when the device is in the Standby or I2C_USB sleep modes, the bandgap circuit is powered-up approximately every 8
ms to facilitate detection of POR or LVD events. This interval can be lengthened or the periodic power-up disabled to reduce sleep
current by setting the ALT_BUZZ bits in the SLP_CFG2 register or the Disable Buzz bit in the OSC_CR0 register respectively. If
the bandgap circuit refresh interval is set longer than the default 8 ms, the device may fail to wakeup from sleep and enter a locked
up state that can only be recovered by Watchdog Reset, XRES, or POR.
■Scope of Impact
The trigger conditions outlined above may cause the device to never wakeup.
■Workaround
Prior to entering Standby or I2C_USB sleep modes, do not lengthen or disable the bandgap refresh interval by manipulating the
ALT_BUZZ bits in the SLP_CFG2 register or the Disable Buzz bit in the OSC_CR0 register respectively.
■Fix Status
This issue will not be corrected in the next silicon revision.
CY8C24X93
Document Number: 001-86894 Rev. *B Page 61 of 65
2. I2C Errors
■Problem Definition
The I2C block exhibits occasional data and bus corruption errors when the I2C master initiates transactions while the device is
transitioning in to or out of sleep mode.
■Parameters Affected
Affects reliability of I2C communication to device, and between I2C master and third party I2C slaves.
■Trigger Condition(S)
Triggered by transitions into and out of the device’s sleep mode.
■Scope of Impact
Data errors result in incorrect data reported to the I2C master, or incorrect data received from the master by the device. Bus
corruption errors can corrupt data in transactions between the I2C master and third party I2C slaves.
■Workaround
Firmware workarounds are available in firmware. Generally the workaround consists of disconnecting the I2C block from the bus
prior to going to sleep modes. I2C transactions during sleep are supported by a protocol in which the master wakes the device prior
to the I2C transaction.
■Fix Status
To be fixed in future silicon.
■Changes
None
3. DoubleTimer0 ISR
■Problem Definition
When programmable timer 0 is used in “one-shot” mode by setting bit 1 of register 0,B0h (PT0_CFG), and the timer interrupt is
used to wake the device from sleep, the interrupt service routine (ISR) may be executed twice.
■Parameters Affected
No datasheet parameters are affected.
■Trigger Condition(S)
Triggered by enabling one-shot mode in the timer, and using the timer to wake from sleep mode.
■Scope of Impact
The ISR may be executed twice.
■Workaround
In the ISR, firmware should clear the one-shot bit with a statement such as “and reg[B0h], FDh”
■Fix Status
Will not be fixed
■Changes
None
CY8C24X93
Document Number: 001-86894 Rev. *B Page 62 of 65
4. Missed GPIO Interrupt
■Problem Definition
When in sleep mode, if a GPIO interrupt happens simultaneously with a Timer0 or Sleep Timer interrupt, the GPIO interrupt may
be missed, and the corresponding GPIO ISR not run.
■Parameters Affected
No datasheet parameters are affected.
■Trigger Condition(S)
Triggered by enabling sleep mode, then having GPIO interrupt occur simultaneously with a Timer 0 or Sleep Timer interrupt.
■Scope of Impact
The GPIO interrupt service routine will not be run.
■Workaround
The system should be architected such that a missed GPIO interrupt may be detected. For example, if a GPIO is used to wake
the system to perform some function, the system should detect if the function is not performed, and re-issue the GPIO interrupt.
Alternatively, if a GPIO interrupt is required to wake the system, then firmware should disable the Sleep Timer and Timer0.
Alternatively, the ISR’s for Sleep Timer and Timer0 should manually check the state of the GPIO to determine if the host system
has attempted to generate a GPIO interrupt.
■Fix Status
Will not be fixed
■Changes
None
5. Missed Interrupt During Transition to Sleep
■Problem Definition
If an interrupt is posted a short time (within 2.5 CPU cycles) before firmware commands the device to sleep, the interrupt will be
missed.
■Parameters Affected
No datasheet parameters are affected.
■Trigger Condition(S)
Triggered by enabling sleep mode just prior to an interrupt.
■Scope of Impact
The relevant interrupt service routine will not be run.
■Workaround
None.
■Fix Status
Will not be fixed
■Changes
None
CY8C24X93
Document Number: 001-86894 Rev. *B Page 63 of 65
6. Wakeup from sleep with analog interrupt
■Problem Definition
Device wakes up from sleep when an analog interrupt is trigger
■Parameters Affected
No datasheet parameters are affected.
■Trigger Condition(S)
Triggered by enabling analog interrupt during sleep mode when device operating temperature is 50 °C or above
■Scope of Impact
Device unexpectedly wakes up from sleep
■Workaround
Disable the analog interrupt before entering sleep and turn it back on upon wakeup.
■Fix Status
Will not be fixed
■Changes
None
CY8C24X93
Document Number: 001-86894 Rev. *B Page 64 of 65
Document History Page
Document Title: CY8C24X93, PSoC® Programmable System-on-Chip
Document Number: 001-86894
Revision ECN Orig. of
Change Submission
Date Description of Change
** 3947416 AMKA 04/02/2013 New data sheet.
*A 3971208 AMKA 04/30/2013 Changed status from Preliminary to Final.
Updated Features.
Updated PSoC® Functional Overview (Updated Analog system (Updated
IDAC), updated Additional System Resources).
Updated Ordering Information (Updated part numbers).
*B 4009884 AMKA 05/24/2013 Updated Logic Block Diagram.
Updated Getting Started (Updated Silicon Errata).
Updated Development Tool Selection (Updated Evaluation Tools (Removed
CY3210-PSoCEval1)).
Updated Reference Documents.
Added Appendix A: Silicon Errata for the CY8C24093/293/393/693 Family.
Added Appendix B: Silicon Errata for the PSoC® CY8C24193/493 Families.
Document Number: 001-86894 Rev. *B Revised May 24, 2013 Page 65 of 65
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CY8C24X93
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