EV2A16A 256Kx16bit3.3VAsynchronous MagnetoresistiveRAM Datasheet Features * Single3.3VPowerSupply * IndustrialTemperatureRange(-40Cto110C)andMilitaryTemperatureRange * * * * * * * (-55Cto125C) SymmetricalHighspeedReadandWritewithFastAccessTime(35ns) FlexibleDataBusControl:8bitor16bitAccess EqualAddressandChipenableAccessTimes AutomaticDataProtectionwithLowvoltageInhibitCircuitrytoPreventWritesonPowerLoss AllInputsandOutputsareTransistortransistorLogic(TTL)Compatible FullyStaticOperation FullNonvolatileOperationwith20YearsMinimumDataRetention Introduction TheEV2A16Aisa4,194,304bitmagnetoresistiverandomaccessmemory(MRAM)deviceorganizedas262,144wordsof16bits.The EV2A16Aisequippedwithchipenable(E),writeenable(W),andoutputenable(G)pins,allowingforsignificantsystemdesign flexibilitywithoutbuscontention.BecausetheEV2A16Ahasseparatebyteenablecontrols(LBandUB),individualbytescanbe writtenandread. MRAMisanonvolatilememorytechnologythatprotectsdataintheeventofpowerlossanddoesnotrequireperiodicrefreshing.The EV2A16Aistheidealmemorysolutionforapplicationsthatmustpermanentlystoreandretrievecriticaldataquickly. TheEV2A16Aisavailableina400mil,44leadplasticsmalloutlineTSOPtypeIIpackageRoHScompliant(MSL3accordingtoJedec standard)withanindustrystandardcenterpowerandgroundSRAMpinout. TheEV2A16AisavailableinIndustrial(-40Cto110C)andMilitary(-55Cto+125C)temperatureranges. Visitourwebsite:www.e2v.com forthelatestversionofthedatasheet e2vsemiconductorsSAS2015 0918F-HIREL-07/15 EV2A16A 1. DevicePinAssignment Figure11. G BlockDiagram Output Enable Buffer Upper Byte Output Enable Lower Byte Output Enable 8 A[17:0] Address Buffers 18 E W UB LB Table11. 10 Row Decoder Column Decoder Chip Enable Buffer 8 Sense AMPS 16 8 256K x 16 Bit Memory Array Write Enable Buffer 16 UB Byte Enable Buffer LB Upper Byte Output Buffer Lower Byte Output Buffer 8 Final Write Drivers 8 Upper Byte Write Enable 8 8 Upper Byte Write Driver Lower Byte Write Driver 8 8 DQU[15:8] DQL[7:0] Lower Byte Write Enable PinFunctions SignalName Function A AddressInput E ChipEnable W WriteEnable G OutputEnable UB UpperByteEnable LB LowerByteEnable DQ DataI/O VDD PowerSupply VSS Ground DC DoNotConnect NC NoConnection 2 0918F-BDC-07/15 e2v semiconductors SAS 2015 EV2A16A Figure12. PinDiagramsforAvailablePackages(TopView) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A0 A1 A2 A3 A4 E DQL0 DQL1 DQL2 DQL3 VDD VSS DQL4 DQL5 DQL6 DQL7 W A5 A6 A7 A8 A9 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 G UB LB DQU15 DQU14 DQU13 DQU12 VSS VDD DQU11 DQU10 DQU9 DQU8 DC A14 A13 A12 A11 A10 44-Pin TSOP Type2 Table12. (1) E OperatingModes G (1) W(1) LB(1) UB(1) Mode VDDCurrent DQL[7:0](2) DQU[15:8](2) H X X X X Notselected ISB1,ISB2 HiZ HiZ L H H X X Outputdisabled IDDR HiZ HiZ L X X H H Outputdisabled IDDR HiZ HiZ L L H L H LowerByteRead IDDR DOut HiZ L L H H L UpperByteRead IDDR HiZ DOut L L H L L WordRead IDDR DOut DOut L X L L H LowerByteWrite IDDW Din HiZ L X L H L UpperByteWrite IDDW HiZ Din L X L L L WordWrite IDDW Din Din Notes: 1. H=high,L=low,X=don'tcare 2. HiZ=highimpedance 3 0918F-BDC-07/15 e2vsemiconductorsSAS2015 EV2A16A 2. ElectricalSpecifications 2.1 AbsoluteMaximumRatings Thisdevicecontainscircuitrytoprotecttheinputsagainstdamagecausedbyhighstaticvoltagesorelectricfields; however,itisadvisedthatnormalprecautionsbetakentoavoidapplicationofanyvoltagegreaterthanmaxi mumratedvoltagestothesehighimpedance(HiZ)circuits. Thedevicealsocontainsprotectionagainstexternalmagneticfields.Precautionsshouldbetakentoavoidappli cationofanymagneticfieldmoreintensethanthemaximumfieldintensityspecifiedinthemaximumratings. Table21. Symbol AbsoluteMaximumRatings(1) Parameter Supplyvoltage(2) VDD (2) VIN Voltageonanypin IOUT Outputcurrentperpin Packagepowerdissipation PD (3) TempRange Package Value Unit - - -0.5to4.0 V - - -0.5toVDD+0.5 V - - 20 mA 0.600 W - Note (3) Industrial - -40to110 Military - -55to125 StorageTemperature - - -65to150 C Leadtemperatureduringsolder (3minutemax) - - 260 C TBIAS Temperatureunderbias Tstg TLead C Hmax_write Maximummagneticfield duringwrite Industrial,Military TSOP2 2000 A/m Hmax_read Maximummagneticfieldduringread orstandby Industrial,Military TSOP2 8000 A/m Notes: 1. Permanentdevicedamagemayoccurifabsolutemaximumratingsareexceeded.Functionaloperationshouldberestrictedtorecom mendedoperatingconditions.Exposuretoexcessivevoltagesormagneticfieldscouldaffectdevicereliability. 2. AllvoltagesarereferencedtoVSS. 3. Powerdissipationcapabilitydependsonpackagecharacteristicsanduseenvironment. Table22. OperatingConditions Parameter Powersupplyvoltage Symbol (1) VDD Min (1) 3.0 Typical Max Unit 3.3 3.6 V (1) V Writeinhibitvoltage VWI 2.5 2.7 Inputhighvoltage VIH 2.2 - VDD+0.3(2) V - 0.8 V +110 +125 C Inputlowvoltage Operatingtemperature Notes: VIL Tcase -0.5 (3) -40 -55 3.0 1. Thereisa2msstartuptimeonceVDDexceedsVDD,(max).SeePowerUpandPowerDownSequencingbelow. 2. VIH(max)=VDD+0.3VDC;VIH(max)=VDD+2.0VAC(pulsewidth 10ns)forI 20.0mA. 3. VIL(min)=-0.5VDC;VIL(min)=-2.0VAC(pulsewidth 10ns)forI 20.0mA. 4 0918F-BDC-07/15 e2v semiconductors SAS 2015 EV2A16A 2.2 PowerupandPowerdownSequencing TheMRAMisprotectedfromwriteoperationswheneverVDDislessthanVWI.AssoonasVDDexceedsVDD(min), thereisastartuptimeof2msbeforereadorwriteoperationscanstart.Thistimeallowsmemorypowersupplies tostabilize. TheEandWcontrolsignalsshouldtrackVDDonpoweruptoVDD-0.2VorVIH(whicheverislower)andremain highforthestartuptime.Inmostsystems,thismeansthatthesesignalsshouldbepulledupwitharesistorso thatsignalremainshighifthedrivingsignalisHiZduringpowerup.AnylogicthatdrivesEandWshouldholdthe signalshighwithapoweronresetsignalforlongerthanthestartuptime. DuringpowerlossorbrownoutwhereVDDgoesbelowVWI,writesareprotectedandastartuptimemustbe observedwhenpowerreturnsaboveVDD(min). Figure21. VWI PowerUpandPowerDownDiagram VDD BROWNOUT or POWER LOSS 2 ms 2 ms RECOVER STARTUP NORMAL OPERATION READ/WRITE INHIBITED NORMAL OPERATION READ/WRITE INHIBITED VIH E VIH W Table23. DCCharacteristics Parameter Symbol Min Typical Max Unit Inputleakagecurrent Ilkg(I) - - 1 A Outputleakagecurrent Ilkg(O) - - 1 A Outputlowvoltage (IOL=+4mA) (IOL=+100A) VOL - - 0.4 VSS+0.2 V Outputhighvoltage (IOH=-4mA) (IOH=-100A) VOH 2.4 VDD-0.2 - - V 5 0918F-BDC-07/15 e2vsemiconductorsSAS2015 EV2A16A Table24. PowerSupplyCharacteristics Parameter Symbol Typical Max Unit IDDR 55 80 mA ACactivesupplycurrent-writemodes(1)(VDD=max) IndustrialGrade MilitaryGrade IDDW 105 105 165 165 mA ACstandbycurrent (VDD=max,E=VIH) nootherrestrictionsonotherinputs ISB1 18 28 mA CMOSstandbycurrent (E VDD-0.2VandVIn VSS+0.2Vor VDD-0.2V) (VDD=max,f=0MHz) ISB2 9 12 mA ACactivesupplycurrent-readmodes (IOUT=0mA,VDD=max) Note: 3. (1) 1. Allactivecurrentmeasurementsaremeasuredwithoneaddresstransitionpercycleandatminimumcycletime. TimingSpecifications Table31. Capacitance(1) Parameter Symbol Typical Max Unit Addressinputcapacitance CIn - 6 pF Controlinputcapacitance CIn - 6 pF Input/Outputcapacitance CI/O - 8 pF Note: 1. f=1.0MHz,dV=3.0V,TA=25C,periodicallysampledratherthan100%tested. Table32. ACMeasurementConditions Parameter Value Unit Logicinputtimingmeasurementreferencelevel 1.5V V Logicoutputtimingmeasurementreferencelevel 1.5V V Logicinputpulselevels 0or3.0V V Inputrise/falltime 2 ns Outputloadforlowandhighimpedanceparameters SeeFigure31 Outputloadforallothertimingparameters SeeFigure32 Figure31. OutputLoadTestLowandHigh ZD = 50 Output RL = 50 VL = 1.5V 6 0918F-BDC-07/15 e2v semiconductors SAS 2015 EV2A16A Figure32. OutputLoadTestAllOthers 3.3V 590 Output 5 pF 435 Table33. ReadCycleTiming(1) Parameter Symbol Min Max Unit tAVAV 35 - ns tAVQV - 35 ns tELQV - 35 ns Outputenableaccesstime tGLQV - 15 ns Byteenableaccesstime tBLQV - 15 ns tAXQX 3 - ns tELQX 3 - ns tGLQX 0 - ns tBLQX 0 - ns EnablehightooutputHiZ(3) tEHQZ 0 15 ns OutputenablehightooutputHiZ(3) tGHQZ 0 10 ns tBHQZ 0 10 ns Readcycletime Addressaccesstime Enableaccesstime (2) Outputholdfromaddresschange Enablelowtooutputactive (3) Outputenablelowtooutputactive Byteenablelowtooutputactive (3) (3) (3) BytehightooutputHiZ Notes: 1. W is high for read cycle. Power supplies must be properly grounded and decoupled, and bus contention conditions must be minimized or eliminated during read or write cycles. 2. AddressesvalidbeforeoratthesametimeEgoeslow. 3. Thisparameterissampledandnot100%tested.Transitionismeasured200mVfromthesteadystatevoltage. Figure33. ReadCycle1 tAVAV A (Address) tAXQX Q (Data Out) Previous Data Valid Data Valid tAVQV Note: Deviceiscontinuouslyselected(E VIL,G VIL) 7 0918F-BDC-07/15 e2vsemiconductorsSAS2015 EV2A16A Figure34. ReadCycle2 t AVAV A (Address) tAVQV t ELQV E (Chip Enable) t EHQZ t ELQX G (Output Enable) t GHQZ t GLQV t GLQX LB, UB (Byte Enable) t BHQZ t BLQV t BLQX Data Valid Q (Data Out) Table34. WriteCycleTiming1(WControlled)(1) Parameter Symbol Min Max Unit Writecycletime(2) tAVAV 35 - ns Addresssetuptime tAVWL 0 - ns Addressvalidtoendofwrite(Ghigh) tAVWH 18 - ns Addressvalidtoendofwrite(Glow) tAVWH 20 - ns Writepulsewidth(Ghigh) tWLWH/tWLEH 15 - ns Writepulsewidth(Glow) tWLWH tWLEH 15 - ns Datavalidtoendofwrite tDVWH 10 - ns Dataholdtime tWHDX 0 - ns tWLQZ 0 12 ns tWHQX 3 - ns tWHAX 12 - ns WritelowtodataHiZ(3) Writehightooutputactive Writerecoverytime Notes: (3) 1. AllwriteoccursduringtheoverlapofElowandWlow.Powersuppliesmustbeproperlygroundedanddecoupledandbuscontention conditionsmustbeminimizedoreliminatedduringreadandwritecycles.IfGgoeslowatthesametimeorafterWgoeslow,theout putwillremaininahighimpedancestate.AfterW,EorUB/LBhasbeenbroughthigh,thesignalmustremaininsteadystatehighfora minimumof2ns.TheminimumtimebetweenEbeingassertedlowinonecycletoEbeingassertedlowinasubsequentcycleisthe sameastheminimumcycletimeallowedforthedevice. 2. Allwritecycletimingsarereferencedfromthelastvalidaddresstothefirsttransitionaddress. 3. Thisparameterissampledandnot100%tested.Transitionismeasured200mVfromthesteadystatevoltage.Atanygivenvoltageor temperate,tWLQZ(max)<tWHQX(min) 8 0918F-BDC-07/15 e2v semiconductors SAS 2015 EV2A16A Figure35. WriteCycleTiming1(WControlled)(1) tAVAV A (ADDRESS) tAVWH tWHAX E (CHIP ENABLE) tWLEH tWLWH W (WRITE ENABLE) tAVWL tDVWH D (DATA IN) tWHDX DATA VALID tWLQZ Q (DATA OUT) Hi-Z Hi-Z tWHQX Table35. WriteCycleTiming2(EControlled)(1) Parameter Symbol Min Max Unit tAVAV 35 - ns Addresssetuptime tAVEL 0 - ns Addressvalidtoendofwrite(Ghigh) tAVEH 18 - ns Addressvalidtoendofwrite(Glow) tAVEH 20 - ns Enabletoendofwrite(Ghigh) tELEH tELWH 15 - ns Enabletoendofwrite(Glow)(3) tELEH tELWH 15 - ns Datavalidtoendofwrite tDVEH 10 - ns Dataholdtime tEHDX 0 - ns Writerecoverytime tEHAX 12 - ns Writecycletime Notes: (2) 1. AllwriteoccursduringtheoverlapofElowandWlow.Powersuppliesmustbeproperlygroundedanddecoupledandbuscontention conditionsmustbeminimizedoreliminatedduringreadandwritecycles.IfGgoeslowatthesametimeorafterWgoeslow,theout putwillremaininahighimpedancestate.AfterW,EorUB/LBhasbeenbroughthigh,thesignalmustremaininsteadystatehighfora minimumof2ns.TheminimumtimebetweenEbeingassertedlowinonecycletoEbeingassertedlowinasubsequentcycleisthe sameastheminimumcycletimeallowedforthedevice. 2. Allwritecycletimingsarereferencedfromthelastvalidaddresstothefirsttransitionaddress. 3. IfEgoeslowatthesametimeorafterWgoeslow,theoutputwillremaininahighimpedancestate.IfEgoeshighatthesametimeor beforeWgoeshigh,theoutputwillremaininahighimpedancestate. 9 0918F-BDC-07/15 e2vsemiconductorsSAS2015 EV2A16A Figure36. WriteCycleTiming2(EControlled) tAVAV A (Address) tAVEH tEHAX tELEH E (Chip Enable) tAVEL tELWH W (Write Enable) UB, LB (Byte Enable) tDVEH tEHDX Data Valid D (Data In) Hi-Z Q (Data Out) Table36. WriteCycleTiming3(LB/UBControlled)(1) Parameter Symbol Min Max Unit Writecycletime(2) tAVAV 35 - ns Addresssetuptime tAVBL 0 - ns Addressvalidtoendofwrite(Ghigh) tAVBH 18 - ns Addressvalidtoendofwrite(Glow) tAVBH 20 - ns Writepulsewidth(Ghigh) tBLEH tBLWH 15 - ns Writepulsewidth(Glow) tBLEH tBLWH 15 - ns Datavalidtoendofwrite tDVBH 10 - ns Dataholdtime tBHDX 0 - ns Writerecoverytime tBHAX 12 - ns Notes: 1. All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state. After W, E or LB/UB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. If both byte control signals are asserted, the two signals must have no more than 2 ns skew between them. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. 2. Allwritecycletimingsarereferencedfromthelastvalidaddresstothefirsttransitionaddress. 10 0918F-BDC-07/15 e2v semiconductors SAS 2015 EV2A16A Figure37. WriteCycleTiming3(LB/UBControlled) tAVAV A (Address) tAVEH tBHAX E (Chip Enable) W (Write Enable tAVBL tBLEH tBLWH UB, LB (Byte Enable) tDVBH Data Valid D (Data In) Q (Data Out) tBHDX Hi-Z Hi-Z 11 0918F-BDC-07/15 e2vsemiconductorsSAS2015 EV2A16A 4. MechanicalDrawing Figure41. 44TSOP2 VIEW D 44 23 Seating Plane 0.05 0.15 0.30 0.45 0.2 Print Version Not To Scale 1. Dimensions and tolerances per ASME Y14.5M - 1994. 2. Dimensions in Millimeters. 3. Dimensions do not include mold protrusion. 4. Dimension does not include DAM bar protrusions. DAM Bar protrusion shall not cause the lead width to exceed 0.58. 12 0918F-BDC-07/15 e2v semiconductors SAS 2015 EV2A16A 5. OrderingInformation ThisproductisavailableinIndustrialandMilitarytemperatureversions. Figure51. EV OrderingInformation 2 A 16 A x N Density Code Memory Type I/O Configuration Revision Operating Temperature Range Package Type e2v Prefix 2 = 4 Mb A = async 16 = 16 bits Notes: A =180 mm Y U 35 RoHS Upscreening compliance (2) V = -40 to 110C (N = TSOP II) Y: RoHS M = -55 to 125C compliant U Timing Set (35 = 35 ns) 1. For availability of the different versions, contact your local e2v sales office. 2. Leadfinishing:puretin(Sn99,99%) 6. DocumentRevisionHistory Table61providesarevisionhistoryforthishardwarespecification. Table61. DocumentRevisionHistory Rev.No Date SubstantiveChange(s) 0918F 07/2015 CorrectederrorinTable21onpage4,"StorageTemperature" 0918E 02/2013 CorrectederrorinTable 11,"PinFunctions,"onpage 2.CorrectedFigure31onpage6. 0918D 06/2012 Updatedpicturepage1. 0918C 09/2010 UpdatedTable22onpage4. 0918B 06/2009 CorrectIohspecto100A AddSection2.2"PowerupandPowerdownSequencing"onpage5. CorrectACtestconditions. 0918A 12/2007 0918AX 11/2007 Table12:ChangedIDDAtoIDDRorIDDW Figure51:AddedRoHScompliancestatusinthepartnumber. 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