U62H256AS1K55G1 - Alliance Memory, Inc.

1 November 01, 2001

U62H256A

F32768 x 8 bit static CMOS RAM

F35 and 55 ns Access Time

FCommon data inputs and

data outputs

FThree-state outputs

FTyp. operating supply current

35 ns: 45mA

55 ns: 30mA

FStandby current < 50 µA at 1 25° C

FTTL/CMOS-compatible

FPower supply voltage 5 V

FOperating temperature range

-40 °C to 85 °C

-40 °C to 125 °C

FCECC 90000 Qua lity Standard

FESD protection > 2000 V

(MIL STD 883C M3015.7)

FLatch-up im mun ity >100 mA

FPackage: SOP28 (300/330 mil)

The U62H256A is a static RAM

manufactured using a CMOS pro-

cess technology with the following

operating modes:

- Read - Standby

- Write - Data Rete ntion

The memory array is based on a

6-Tra nsistor cell.

The circuit is activated by the fal-

ling edge of E. The address and

control inputs open simul taneous ly.

According to the information of W

and G, the data inputs, or outputs,

are active. In a Read cycle, the

data outputs are activated by the

falling edge of G, afterwards the

data word will be available at the

outputs DQ0-DQ7. After the

address change, the data outputs

go High-Z until the new information

is available. T he data outputs have

no preferred state. T he Read cycle

is finished by the falling edge of W,

or by the rising edge of E, respec-

tively.

Data retention is guaranteed down

to 2 V. With the exception of E, all

inputs consist of NOR gates, so

that no pull-up/pull-down resistors

are required.

Automotive Fast 32K x 8 SRAM

Pin Con figurat i on

Top View

Si gn a l Nam e Sign al Descrip t ion

A0 - A14 Address Inputs

D Q0 - DQ7 Data In/Out

EChip Enable

GOutput Enable

WWrit e En able

VCC Power Supply Vol t age

VSS Ground

Pin Descript ion

A14 VCC28

2A12 W

4A6 A825

5A5 A924

3A7 A1326

6A4 A1123

7A3 G

8A2 A1021

12DQ1 DQ517

9A1 E

A0 DQ719

11DQ0 DQ618

13DQ2 DQ416

14VSS DQ315

SOP

Features Description

2 November 01, 200 1

U62H256A

Operating Mode E W G DQ0 - DQ7

Standby /not selected H * * High-Z

Internal Read L H H High-Z

Read L H L Data Outputs Low-Z

Write L L * Data Inputs High-Z

Trut h Tabl e

Block Diagram

Characteristics

a Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress rating

only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not im plie d .

Exposure to absolute maximum rating conditions for extended periods may affect reliability

b Maximum volt age is 7 V

c Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.

All voltages are referenced to VSS = 0 V (ground).

All characteristics are valid in the power supply v oltage range and in the operating temperature range speci fied.

Dynamic measur emen ts are based on a rise and fal l time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as

input levels of VIL = 0 V and VIH = 3 V. The timi ng refere nce level of all input and output signals is 1.5 V,

with th e exce ption of the tdis-time s and ten-times, in which cases trans ition is meas ured ±200 mV from steady-state voltage.

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

VCC VSS W GE

Row Address

Inputs

Column Address

Inputs

Address

Change

Detector

Column Decoder Row Decoder

Se ns e Am plifi er /

Write Control Logic

Clock

Generator

Co mmo n Data I/O

Memory Cell

Array

512 Rows x

64 x 8 Columns

A10

A11

A12

A13

A14

*H or L

Maxim um Rating s aSymbol Min. Max. Unit

Powe r Supply Voltage VCC -0.5 7 V

Input Voltage VI-0.5 VCC + 0.5 bV

Out put Voltage VO-0.5 VCC + 0.5 bV

Power Dissipation PD-1W

Operating Temperature K-Type

A-Type Ta-40

-40 85

125 °C

Storage Temperature Tstg -65 150 °C

Out put Short-Circuit Current

at VCC = 5 V and VO = 0 V c| IOS | 200 mA

3 November 01, 2001

U62H256A

d -2 V at Pulse Width 30 ns

Recommended

Operating Conditions Symbol Conditions Min. Max. Unit

Power Supply Volta ge VCC 4.5 5.5 V

Input Low V ol t age d VIL -0.3 0.8 V

Input High V o ltage VIH 2.2 VCC + 0.3 V

Electrical Characteri stics Symbol Cond itions Min. Max. Unit

Supply Current - Operating Mode

Supply Current - Standby Mode

(CMOS level)

Supply Current - Standby Mode

(TTL level)

ICC(OP)

ICC(SB)

ICC(SB)1

VCC

VIL

VIH

tcW

VCC

K-Type

A-Type

= 5.5 V

= 0.8 V

=2.2 V

= 35 ns

= 55 ns

=5.5 V

= VCC - 0.2 V

= 5.5 V

= 2.2 V

µA

Output High Voltage

Output Low V ol t age

VOH

VOL

VCC

IOH

VCC

IOL

= 4.5 V

=-4.0 mA

=4.5 V

=8.0 mA

2.4

0.4

Input High Leakage Current

Input Low Leakage Curren t

IIH

IIL

VCC

VIH

VCC

VIL

= 5.5 V

= 0 V -2

2µA

µA

Output High Current

Output Low Current

IOH

IOL

VCC

VOH

VCC

VOL

=4.5 V

=2.4 V

=4.5 V

=0.4 V 8

-4 mA

Output Leakage Current

High at Three-S t ate Outputs

Low at Three-St ate Outputs

IOHZ

IOLZ

VCC

VOH

VCC

VOL

=5.5 V

=0 V -2

2µA

µA

4 November 01, 200 1

U62H256A

Switching Characteristics

Read Cycle

Symbol 35 55 Unit

Alt. IEC Min. Max. Min. Max.

Read Cycle Time tRC tcR 35 55 ns

Address Access Time to Data Valid tAA ta(A) 35 55 ns

Chip Enable Access Time to Data Vali d tACE ta(E) 35 55 ns

G LOW to Data Valid tOE ta(G) 15 25 ns

E HIGH to Output in High-Z tHZCE tdis(E) 15 20 ns

G HIGH to Output in High-Z tHZOE tdis(G) 12 15 ns

E LOW to Output in Low-Z tLZCE ten(E) 33ns

G LOW to Output in Low-Z tLZOE ten(G) 00ns

Output Hold Tim e from Address Change tOH tv(A) 33ns

E LOW to Power-Up Time tPU 00ns

E HIGH to Power-Down Time tPD 35 55 ns

Switching Characteristics

Write Cycle

Symbol 35 55 Unit

Alt. IEC Min. Max. Min. Max.

Write Cycle Ti me tWC tcW 35 55 ns

Write Pulse Width tWP tw(W) 20 35 ns

Write Setup Time tWP tsu(W) 20 35 ns

Address Setup Ti m e tAS tsu(A) 00ns

Address Valid to End of Write tAW tsu(A-WH) 25 40 ns

Chip Enable Setup T i me tCW tsu(E) 25 40 ns

Pulse Width Chip Enable to End of Writ e tCW tw(E) 25 40 ns

Da ta Se tup Time t DS tsu(D) 15 25 ns

Data Hold Tim e tDH th(D) 00ns

Address Hold from End of Write tAH th(A) 00ns

W LOW to Output in High-Z tHZWE tdis(W) 15 20 ns

G HIGH to Output in High-Z tHZOE tdis(G) 12 15 ns

W HIGH to Outpu t in Low- Z tLZWE ten(W) 00ns

G LOW to Output in Low-Z tLZOE ten(G) 00ns

5 November 01, 2001

U62H256A

E - controlled

Data Retenti on

4.5 V

tsu(DR) trec

VCC

VCC(DR) ≥ 2 V

0 V

2. 2 V

2.2 V

VCC(DR) - 0.2 V ≤ VE(DR) ≤ VCC(DR) + 0.3 V

Data Retention

Characteristics Symbol Conditions Min. Typ. Max. Unit

Alt. IEC

Data Retention Supply Voltage VCC(DR) 25.5V

Data Retention Supply Current ICC(DR) VCC(DR) = 3 V

VE = VCC(DR) - 0.2 V 30 µA

Data Retention Setup Time tCDR tsu(DR) See Data Retention

Waveforms (above) 0ns

Operating Recovery Ti me tRtrec tcR ns

Test Conf ig urat io n for Funct i onal Chec k

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

VIH

VIL

VSS

VCC

5 V

481

255

30 pF e

Input level according to the

rel ev a nt tes t me as ur em en t

Simultaneous measure-

m ent of all 8 output pins

A10

A11

A12

A13

A14

e In measurement of tdis(E),tdis(W), t en(E), ten(W), ten(G) th e capacitance is 5 pF.

Data Retention Mode

6 November 01, 200 1

U62H256A

Capacitance Conditions Symbol Min. Max. Unit

Inpu t Capacitance VCC

= 5.0 V

= VSS

= 1 MHz

= 25 °C

CI7pF

Out put Capacitance Co7pF

All pins not under test must be connected with ground by capacitors.

IC Code Numbers

U62H256A SA35

Type

Package

S = SOP28 300 m il

S1 = SOP 28 330 mi l

Opera ting Temperature Range

K = -40 to 85 °C

A = -40 to 125 °C

Access Time

35 = 35 ns

55 = 55 ns

The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year , and the last 2

digits th e calendar week.

7 November 01, 2001

U62H256A

tPU

tdis(G)

tdis(E)

tcR

Previous Data Valid Output Data Valid

Address Valid

Addres s Va lid

tsu(A)

High-Z

ten(E)

ten(G)

ta(G)

ta(E)

Read Cycle 1: Ai-con trolled (during Read Cycle : E = G = VIL, W = VIH)

Read Cycle 2: G-, E-c ontrol led (durin g R ea d C ycl e : W = VIH)

ta(A)

tcR

tv(A)

DQi

Output

DQi

Output tPD

ICC(OP)

ICC(SB) 50 % 50 %

Ou tp ut Data Vali d

8 November 01, 200 1

U62H256A

Wr ite Cycle1: W-controlled

th(D)

DQi

Input

DQi

Output

tcW

tsu(E) th(A)

tw(W)

tsu(A) tsu(D)

tdis(W) ten(W)

Address Valid

Input Data Valid

High-Z

tsu(A-WH)

Write Cycle 2: E -controlled

Input Data Valid

tsu(A)

th(D)

DQi

Input

DQi

Output

tcW

tw(E)

th(A)

tsu(W)

tsu(D)

tdis(W)

en(E)

High-Z

Ad dres s Va li d

tdis(G)

L- to H - l e v e l undefined H- to L-le ve l

The information describes the type of component and shall not be considered as assured characteristics.Terms of

delivery and rights to chang e design reserved .

Zentrum Mikroelektronik Dresden AG

Grenzstra ße 28 • D-01109 Dresden • P. O. B. 80 01 34 • D-01101 Dresden • Germany

Phone: +49 351 8822 306 • Fax: +49 351 8822 337 • Email : sales@zmd.de • http://www.zmd.de

November 01, 2001

U62H256A

LIFE S U PP O R T POLI CY

ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical

implant into the body, or other applic ations intended to support or sustain life, or for any other appli ca tion in which

the failure of the ZMD product could create a situation where personal injury or death may occur.

Componen ts used in lif e-support devices or systems must be express ly authorized by ZMD for such purpose.

LIMITED WARRANT Y

The information in this document has been carefully checked and is believed to be reliable. However Zentrum

Mikroelektronik Dresden AG (ZMD) makes no guarantee or warran ty concerning the accuracy of said information

and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it.

The inform ation in this docum ent des cribes t he t ype of comp onent and sh all not be c onsidere d as ass ured charac-

teristics.

ZMD does not guarantee that the use of any information contained herei n will not infringe upon the patent, trade-

mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This

document does not in any way extent ZMD’s warranty on any product beyond that set forth in its standard terms and

condition s of sale.

ZMD reserves terms of delivery a nd reserves the right to make changes in the products or specifications, or both,

presented in this publication at any time and without notice.

Change record

Date Name Change

31.01.2001 Steffen Buschbeck initial release of U62H256A based on U62H256S

29.08.2001 Steffen Buschbeck

Wilf rie d H o f r ic hter short ened Desc ription (page 1)

adjusted Block Diagram to array organization (page 2)

chang ed Addre ss Va lid to End of Write 20 -> 25 (page 4)